code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bitriquatB;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1000 init = 0;
#20000 $stop;
end
initial begin
$dumpfile("bitriquatB.vcd");
$dumpvars(0, bitriquatB);
end
wire [3:0] quatout;
wire [2:0] trinary;
wire [1:0] binary;
wire quatcomp;
ring3gen TB1 (
trinary[2:0],
quatcomp,
init
);
ring2gen TB2 (
binary[1:0],
quatcomp,
init
);
////// test bench
//////////////////////////////
////// circuit under test
// perform bitriquat
wire bt10, bt11;
// combinational logic
TH22 u4 (
bt10,
binary[1],
trinary[0]
);
TH22 u5 (
bt11,
binary[1],
trinary[1]
);
// output link for quat plus combinational logic
THnotN o0 (
quatenable,
quatcomp,
init
);
TH33 o1 (
quatout[0],
binary[0],
trinary[0],
quatenable
);
TH54W32 o2 (
quatout[1],
quatenable,
bt10,
binary[0],
trinary[1]
);
TH54W32 o3 (
quatout[2],
quatenable,
bt11,
binary[0],
trinary[2]
);
TH33 o4 (
quatout[3],
binary[1],
trinary[2],
quatenable
);
////// circuit under test
//////////////////////////////
////// test bench
TH14 u10 (
quatcomp,
quatout[0],
quatout[1],
quatout[2],
quatout[3]
); // auto consume
endmodule
| 6.904288 |
module bitriquatC (
output [3:0] quatout,
input quatoutcomp,
init
);
/* Make an init that pulses once. */
/* reg init = 1;
initial begin
# 1000 init = 0;
# 20000 $stop;
end
initial
begin
$dumpfile("bitriquatC.vcd");
$dumpvars(0, bitriquatC);
end
*/
//wire [3:0] quatout;
wire [2:0] trinary;
wire [1:0] binary;
//wire quatcomp;
ring3gen TB1 (
trinary[2:0],
quatcomp,
init
);
ring2gen TB2 (
binary[1:0],
quatcomp,
init
);
////// test bench
//////////////////////////////
////// circuit under test
// perform bitriquat
wire [1:0] temp;
// combinational logic
THXOR u1 (
temp[0],
binary[0],
trinary[1],
binary[1],
trinary[0]
);
THXOR u2 (
temp[1],
binary[0],
trinary[2],
binary[1],
trinary[1]
);
// output link for quat
THnotN o0 (
quatenable,
quatoutcomp,
init
);
TH33 o1 (
quatout[0],
binary[0],
trinary[0],
quatenable
);
TH22 o2 (
quatout[1],
quatenable,
temp[0]
);
TH22 o3 (
quatout[2],
quatenable,
temp[1]
);
TH33 o4 (
quatout[3],
binary[1],
trinary[2],
quatenable
);
////// circuit under test
//////////////////////////////
////// test bench
TH14 u10 (
quatcomp,
quatout[0],
quatout[1],
quatout[2],
quatout[3]
); // auto consume
endmodule
| 6.823705 |
module bits2prm_tb ();
`include "paramList.v"
reg start;
reg reset;
reg clk;
wire done;
reg muxSelect;
reg [11:0] memReadAddrTest;
wire [31:0] memInTest;
reg [11:0] memWriteAddrTest;
reg [31:0] memOutTest;
reg memWriteEnTest;
//I/O regs
reg [15:0] bitstream_data[0:400000];
reg [15:0] prm_data[0:400000];
integer i, j;
//file read in for inputs and output tests
initial begin // samples out are samples from ITU G.729 test vectors
$readmemh("bits2prm_prm_data.out", prm_data);
$readmemh("bits2prm_bitstream.out", bitstream_data);
end
bits2prm_ld8k_pipe i_pipe (
.start(start),
.clk(clk),
.reset(reset),
.done(done),
.muxSelect(muxSelect),
.scratch_mem_in(memInTest),
.memReadAddrTest(memReadAddrTest),
.memWriteAddrTest(memWriteAddrTest),
.memOutTest(memOutTest),
.memWriteEnTest(memWriteEnTest)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
start = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
reset = 1;
// Wait 50 ns for global reset to finish
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
reset = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
for (j = 0; j < 3658; j = j + 1) begin
//TEST1
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
muxSelect = 0;
memReadAddrTest = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
for (i = 0; i < 80; i = i + 1) begin
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
muxSelect = 1;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
memWriteAddrTest = {SERIAL[11:4], i[3:0]};
memOutTest = bitstream_data[80*j+i];
memWriteEnTest = 1;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
end
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
muxSelect = 0;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
start = 1;
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
start = 0;
// Add stimulus here
wait (done);
@(posedge clk);
@(posedge clk);
memWriteAddrTest = 0;
memOutTest = 0;
memWriteEnTest = 0;
@(posedge clk) #5;
muxSelect = 1;
//gamma1 read
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
for (i = 0; i < 11; i = i + 1) begin
@(posedge clk);
@(posedge clk);
@(posedge clk) #5;
memReadAddrTest = {PRM[11:4], i[3:0]};
@(posedge clk);
@(posedge clk) #5;
if (memInTest != {16'd0, prm_data[j*11+i]})
$display(
$time, " ERROR: prm_data[%d] = %x, expected = %x", i, memInTest, prm_data[j*11+i]
);
else if (memInTest == {16'd0, prm_data[j*11+i]})
$display($time, " CORRECT: prm_data[%d] = %x", i, memInTest);
@(posedge clk);
end
end //j for loop
end
initial forever #10 clk = ~clk;
endmodule
| 6.644274 |
module bitscan (
req,
sel
);
parameter WIDTH = 16;
input [WIDTH-1:0] req;
output [WIDTH-1:0] sel;
assign sel = req & ~(req - 1);
endmodule
| 7.452063 |
module returns the bit in the lowest order bit in the input with 0 as a 1. All
// other bits in output are Zero.
//
//
//
//
// Modification History:
// Date By Version Change Description
//
// 21/07/14 OB 1.0 Initial release version
//
//
// SVN Revision Information:
// SVN $Revision: 4805 $
// SVN $Date: 2014-07-21 17:48:48 +0530 (Mon, 21 Jul 2014) $
//
// Resolved SARs
// SAR Date Who Description
//
// Notes:
//
// ********************************************************************/
// synopsys translate_off
//`include "../include/Timescale.h"
// synopsys translate_on
module BitScan0 ( inMask,outMask );
parameter WIDTH = 4;
input [WIDTH-1:0] inMask;
output [WIDTH-1:0] outMask;
assign outMask = ~inMask & ~(~inMask-1);
endmodule
| 7.105653 |
module bitscan_tb ();
parameter WIDTH = 16;
reg [WIDTH-1:0] req;
wire [WIDTH-1:0] sel;
bitscan b (
.req(req),
.sel(sel)
);
defparam b.WIDTH = WIDTH;
initial begin
req = 16'h8000;
end
integer n;
reg [WIDTH-1:0] result;
reg fail = 0;
always begin
#100 req = $random & $random & $random;
#10 result = 0;
for (n = 0; n < WIDTH; n = n + 1) begin
if (req[n] == 1'b1) begin
result[n] = 1'b1;
n = WIDTH;
end
end
#10
if (sel !== result) begin
$display("Mismatch at time %d", $time);
fail = 1'b1;
$stop();
end
end
initial begin
#1000000 if (!fail) $display("PASS");
$stop();
end
endmodule
| 6.81586 |
module BUFT (
inout wire TO,
input wire D,
input wire E,
input wire CLK
);
reg save;
assign TO = E ? save : 2'bz;
always @(posedge CLK) save <= D;
endmodule
| 8.419665 |
module bit_find_last_bit (
bits,
bitsOutIndex,
found
);
parameter WIDTH = 128;
input [WIDTH-1:0] bits;
output [WIDTH-1:0] bitsOutIndex;
output found;
wire [WIDTH:0] bits1 = {bits, 1'b1};
wire [WIDTH:0] match;
wire notFound;
assign {bitsOutIndex, notFound} = match;
assign found = ~notFound;
genvar i;
generate
for (i = 0; i <= WIDTH; i = i + 1) begin : assignos
assign match[WIDTH-i] = ({1'b0, bits1[WIDTH:WIDTH-i]} == {{(i + 1) {1'b0}}, 1'b1});
end
endgenerate
endmodule
| 7.001777 |
module bit_alloc (
clkEn,
bits,
needed0,
needed1,
needed2,
needed3,
bitsOut0,
bitsOut1,
bitsOut2,
bitsOut3,
doStall
);
parameter WIDTH = 32;
input clkEn;
input [WIDTH-1:0] bits;
input needed0;
input needed1;
input needed2;
input needed3;
output [WIDTH-1:0] bitsOut0;
output [WIDTH-1:0] bitsOut1;
output [WIDTH-1:0] bitsOut2;
output [WIDTH-1:0] bitsOut3;
output doStall;
wire found0;
wire found1;
wire found2;
wire found3;
wire [WIDTH-1:0] bitsOutIndex0;
wire [WIDTH-1:0] bitsOutIndex1;
wire [WIDTH-1:0] bitsOutIndex2;
wire [WIDTH-1:0] bitsOutIndex3;
bit_find_first_bit first0_mod (
bits,
bitsOutIndex0,
found0
);
defparam first0_mod.WIDTH = WIDTH;
bit_find_first_bit first1_mod (
bits & ~bitsOutIndex0,
bitsOutIndex1,
found1
);
defparam first1_mod.WIDTH = WIDTH;
bit_find_last_bit last0_mod (
bits,
bitsOutIndex2,
found2
);
defparam last0_mod.WIDTH = WIDTH;
bit_find_last_bit last1_mod (
bits & ~bitsOutIndex2,
bitsOutIndex3,
found3
);
defparam last1_mod.WIDTH = WIDTH;
assign doStall=(~found1) | (~found3) | (bitsOutIndex1==bitsOutIndex2) | (bitsOutIndex1==bitsOutIndex3);
assign bitsOut0 = bitsOutIndex0 & {WIDTH{clkEn & needed0}};
assign bitsOut1 = bitsOutIndex1 & {WIDTH{clkEn & needed1}};
assign bitsOut2 = bitsOutIndex2 & {WIDTH{clkEn & needed2}};
assign bitsOut3 = bitsOutIndex3 & {WIDTH{clkEn & needed3}};
endmodule
| 6.678962 |
module bit_is_single_bit (
bits,
isSingle
);
parameter WIDTH = 32;
input [WIDTH-1:0] bits;
output isSingle;
wire [WIDTH-1:0] singleBits;
genvar i;
generate
for (i = 0; i <= WIDTH - 1; i = i + 1) begin : bits_block
assign singleBits[i] = (bits == ({{(WIDTH - 1) {1'b0}}, 1'b1} << i));
end
endgenerate
assign isSingle = |(singleBits);
endmodule
| 7.218538 |
module select2From8 (
X_all,
pos,
ans
);
input [7:0] X_all;
input [1:0] pos;
output reg [1:0] ans;
always @* begin
case (pos)
0: ans <= X_all[1:0];
1: ans <= X_all[3:2];
2: ans <= X_all[5:4];
3: ans <= X_all[7:6];
endcase
end
endmodule
| 8.363102 |
module select4From64 (
X_all,
pos,
ans
);
input [63:0] X_all;
input [3:0] pos;
output reg [3:0] ans;
always @* begin
case (pos)
0: ans <= X_all[3:0];
1: ans <= X_all[7:4];
2: ans <= X_all[11:8];
3: ans <= X_all[15:12];
4: ans <= X_all[19:16];
5: ans <= X_all[23:20];
6: ans <= X_all[27:24];
7: ans <= X_all[31:28];
8: ans <= X_all[35:32];
9: ans <= X_all[39:36];
10: ans <= X_all[43:40];
11: ans <= X_all[47:44];
12: ans <= X_all[51:48];
13: ans <= X_all[55:52];
14: ans <= X_all[59:56];
15: ans <= X_all[63:60];
endcase
end
endmodule
| 7.179536 |
module select5From80 (
X_all,
pos,
ans
);
input [79:0] X_all;
input [3:0] pos;
output reg [4:0] ans;
always @* begin
case (pos)
0: ans <= X_all[4:0];
1: ans <= X_all[9:5];
2: ans <= X_all[14:10];
3: ans <= X_all[19:15];
4: ans <= X_all[24:20];
5: ans <= X_all[29:25];
6: ans <= X_all[34:30];
7: ans <= X_all[39:35];
8: ans <= X_all[44:40];
9: ans <= X_all[49:45];
10: ans <= X_all[54:50];
11: ans <= X_all[59:55];
12: ans <= X_all[64:60];
13: ans <= X_all[69:65];
14: ans <= X_all[74:70];
15: ans <= X_all[79:75];
endcase
end
endmodule
| 6.783632 |
module bitSerialAdder (
input clk,
input rst_shift,
input rst_ff,
input load,
input sipo_load,
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
wire [7:0] x, z;
wire s, c;
ShiftReg INST1 (
clk,
rst_shift,
load,
a,
x
);
ShiftReg INST2 (
clk,
rst_shift,
load,
b,
z
);
dff D (
clk,
rst_ff,
cout,
cin,
c
);
//Calling adder module
Adder FA1 (
x[0],
z[0],
c,
s,
cout
);
//Store sum in SIPO
sipo S1 (
clk,
sipo_load,
s,
sum
);
endmodule
| 6.521384 |
module bitSerialAdder_tb;
// Inputs
reg clk;
reg rst_shift;
reg rst_ff;
reg load;
reg sipo_load;
reg [7:0] a;
reg [7:0] b;
reg cin;
// Outputs
wire [7:0] sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
bitSerialAdder uut (
.clk(clk),
.rst_shift(rst_shift),
.rst_ff(rst_ff),
.load(load),
.sipo_load(sipo_load),
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
// Initialize Inputs
clk = 0;
rst_shift = 0;
rst_ff = 1;
load = 1'b1;
sipo_load = 0;
a = 8'b01101001;
b = 8'b00110100;
cin = 0;
// Wait 100 ns for global reset to finish
#50 rst_ff = 1'b0;
#400 load = 1'b0;
end
always #25 clk = !clk;
initial begin
#850 sipo_load = 1'b1;
$display("%d, %d, %d", a, b, sum);
end
endmodule
| 6.521384 |
module BitSetClr (
input [15:0] ir, // Instruction word
input [ 7:0] io_rdata, // I/O register read data
input [ 7:0] rf_rdata, // Register file read data
input [ 7:0] sreg, // Status register
input sr_tf, // Transfer bit in status register
output reg [ 7:0] bsc_ro, // Operation result
output reg bst_tf // BST instruction transfer bit
);
`include "OpDefine.v"
always @* begin
bsc_ro = 8'h00;
bst_tf = 1'b0;
casex (ir)
//--------------------------------------------------
// Bit and Bit-test Instructions
//--------------------------------------------------
C_SBI : // 10011010AAAAAbbb SBI A,b
begin
bsc_ro = io_rdata;
bsc_ro[ir[2:0]] = 1'b1;
end
C_CBI : // 10011000AAAAAbbb CBI A,b
begin
bsc_ro = io_rdata;
bsc_ro[ir[2:0]] = 1'b0;
end
C_BST : // 1111101ddddd0bbb BST Rd,b
begin
bst_tf = rf_rdata[ir[2:0]];
end
C_BLD : // 1111100ddddd0bbb BLD Rd,b
begin
bsc_ro = rf_rdata;
bsc_ro[ir[2:0]] = sr_tf;
end
C_BSET : // 100101000sss1000 BSET s
begin
bsc_ro = sreg;
bsc_ro[ir[6:4]] = 1'b1;
end
C_BCLR : // 100101001sss1000 BCLR s
begin
bsc_ro = sreg;
bsc_ro[ir[6:4]] = 1'b0;
end
default: begin
bsc_ro = 8'h00;
bst_tf = 1'b0;
end
endcase
end
endmodule
| 7.096826 |
module mux2 (
input wire i0,
i1,
j,
output wire o
);
assign o = (j == 0) ? i0 : i1;
endmodule
| 7.816424 |
module barrelshifter16 (
input wire [15:0] i,
input wire [ 3:0] s,
input wire [ 1:0] op,
output wire [15:0] o
);
wire [15:0] t1, t2, t3;
bitshift8 b8 (
i,
s[3],
op,
t1
);
bitshift4 b4 (
t1,
s[2],
op,
t2
);
bitshift2 b2 (
t2,
s[1],
op,
t3
);
bitshift1 b1 (
t3,
s[0],
op,
o
);
endmodule
| 6.846779 |
module: shift_reg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BitshiftTest;
// Inputs
reg rx;
reg rst;
reg baud_clk;
// Outputs
wire [149:0] shifted_bus;
// Instantiate the Unit Under Test (UUT)
shift_reg uut (
.rx(rx),
.shifted_bus(shifted_bus),
.finished_rx(finished_rx),
.rst(rst),
.baud_clk(baud_clk)
);
initial begin
// Initialize Inputs
rx = 1'b1;
rst = 1;
baud_clk = 0;
#10 rst = 1'b0;
#1000 rx = 1'b0;
#12000 rx = 1'b1;
#2000 rx = 1'b0;
#2000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#4100 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#2000 rx = 1'b0;
#2000 rx = 1'b1;
#2000 rx = 1'b0;
#2000 rx = 1'b1;
#2000 rx = 1'b0;
#10000 rx = 1'b1;
#6000 rx = 1'b0;
#2000 rx = 1'b1;
#10000 rx = 1'b0;
#6000 rx = 1'b1;
#70000; $stop;
end
always #1000 baud_clk=~baud_clk;
endmodule
| 7.194325 |
module BitShift_Button (
// input i_Clk,
input i_Switch_2,
input i_Switch_4,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G
);
reg [0:7] r_Byte = 0;
// reg r_Switch_2 = 1;
// reg r_Switch_4 = 1;
// reg r_Any_Switch = 1;
// // Clever trick: share debounce filter
wire w_Any_Switch;
assign w_Any_Switch = i_Switch_2 || i_Switch_4;
//
// // Debounce Filter
// Debounce_Switch Debounce_Switch
// (.i_Clk(i_Clk),
// .i_Switch(i_Switch_2 || i_Switch_4),
// .o_Switch(w_Any_Switch));
always @(posedge w_Any_Switch) begin
// r_Switch_2 <= i_Switch_2; // 1
// r_Switch_4 <= i_Switch_4; // 0
// r_Any_Switch <= w_Any_Switch;
// if (r_Any_Switch == 0 && w_Any_Switch == 1) begin
if (i_Switch_4 == 1) begin
r_Byte <= r_Byte * 2;
end else if (i_Switch_2 == 1) begin
r_Byte <= r_Byte * 2 + 1;
end
// end
end
Byte_To_Seven_Segment_Display Byte_To_Seven_Segment_Display_a (
.i_Byte(r_Byte),
.o_Segment1_A(o_Segment1_A),
.o_Segment1_B(o_Segment1_B),
.o_Segment1_C(o_Segment1_C),
.o_Segment1_D(o_Segment1_D),
.o_Segment1_E(o_Segment1_E),
.o_Segment1_F(o_Segment1_F),
.o_Segment1_G(o_Segment1_G),
.o_Segment2_A(o_Segment2_A),
.o_Segment2_B(o_Segment2_B),
.o_Segment2_C(o_Segment2_C),
.o_Segment2_D(o_Segment2_D),
.o_Segment2_E(o_Segment2_E),
.o_Segment2_F(o_Segment2_F),
.o_Segment2_G(o_Segment2_G)
);
endmodule
| 7.247579 |
module BitsMuxModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire [7:0] Addr,
input wire [7:0] Value,
output wire [1:0] pixelBits
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire [1:0] BitsMuxModule_L14F76T77_Expr = 2'b10;
wire [7:0] Inputs_Addr;
wire [7:0] Inputs_Value;
wire [1:0] pixelAddress;
wire [1:0] BitsMuxModule_L13F37T54_Index;
wire [7:0] BitsMuxModule_L14F42T71_Source;
wire [1:0] BitsMuxModule_L14F41T100_Index;
wire [7:0] BitsMuxModule_L14F42T93_Expr;
wire [7:0] BitsMuxModule_L14F42T93_Expr_1;
wire [4:0] BitsMuxModule_L14F76T92_Expr;
wire signed [4:0] BitsMuxModule_L14F76T92_Expr_1;
wire signed [4:0] BitsMuxModule_L14F76T92_Expr_2;
assign BitsMuxModule_L14F42T93_Expr = BitsMuxModule_L14F42T93_Expr_1 >> BitsMuxModule_L14F76T92_Expr;
assign BitsMuxModule_L14F76T92_Expr = BitsMuxModule_L14F76T92_Expr_1 * BitsMuxModule_L14F76T92_Expr_2;
assign BitsMuxModule_L14F42T93_Expr_1 = BitsMuxModule_L14F42T71_Source;
assign BitsMuxModule_L14F76T92_Expr_1 = {{3{1'b0}}, BitsMuxModule_L14F76T77_Expr} /*expand*/;
assign BitsMuxModule_L14F76T92_Expr_2 = {{3{1'b0}}, pixelAddress} /*expand*/;
assign Inputs_Addr = Addr;
assign Inputs_Value = Value;
assign BitsMuxModule_L13F37T54_Index = Inputs_Addr[1:0];
assign pixelAddress = BitsMuxModule_L13F37T54_Index;
assign BitsMuxModule_L14F42T71_Source = Inputs_Value;
assign BitsMuxModule_L14F41T100_Index = BitsMuxModule_L14F42T93_Expr[1:0];
assign pixelBits = BitsMuxModule_L14F41T100_Index;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 7.742495 |
module bitsplit (
input clk,
input bit1_i,
input bit2_i,
output largebit_o,
output smallbit_o,
input swap_i,
output swap_o,
input run_i,
output run_o
);
reg r_bit1;
reg r_bit2;
reg r_small_bit;
reg r_large_bit;
reg r_compare_result;
reg r_freeze_compare;
reg [0:1] r_swap;
reg [0:1] r_run;
wire w_different_bits;
always @(posedge clk) begin
if (~run_i) begin
r_freeze_compare <= 0;
end else if (w_different_bits) begin
r_freeze_compare <= 1;
end
end
always @(posedge clk) begin
if (~run_i) begin
r_compare_result <= 0;
end else if (~r_freeze_compare) begin
if (bit1_i & ~bit2_i) begin
r_compare_result <= 1;
end else begin
r_compare_result <= 0;
end
end
end
always @(posedge clk) begin
r_bit1 <= bit1_i;
r_bit2 <= bit2_i;
if (~r_compare_result) begin
r_small_bit <= r_bit1;
r_large_bit <= r_bit2;
end else begin
r_small_bit <= r_bit2;
r_large_bit <= r_bit1;
end
end
always @(posedge clk) begin
r_swap[0] <= swap_i;
r_swap[1] <= r_swap[0] | r_compare_result;
end
always @(posedge clk) begin
r_run[0] <= run_i;
r_run[1] <= r_run[0];
end
assign w_different_bits = bit1_i ^ bit2_i;
assign largebit_o = r_large_bit;
assign smallbit_o = r_small_bit;
assign swap_o = r_swap[1];
assign run_o = r_run[1];
endmodule
| 7.065534 |
module bitstream (
input clk,
input reset_n,
// Data interface
output reg rdy,
input en,
input [15:0] in_bits,
input [3:0] in_len,
// Control interface
output full,
input setaddr,
input [31:0] abase,
input [31:0] aend,
// Avalon Master
output [31:0] address,
output reg write,
input waitrequest,
output [15:0] writedata
);
reg [31:0] next_wptr;
reg [15:0] next_wdata, next_in;
wire [15:0] in;
reg [ 1:0] next_state;
wire [ 1:0] state;
reg [ 3:0] next_len;
wire [ 3:0] len;
wire [4:0] curr_len, temp_len, new_len;
wire [31:0] shift_temp;
wire [31:0] shift_in;
register #(32) WPTR (
.clk(clk),
.in (reset_n ? next_wptr : 32'b0),
.out(address),
.en (1'b1)
);
register #(16) DATA (
.clk(clk),
.in (reset_n ? next_wdata : 16'b0),
.out(writedata),
.en (1'b1)
);
register #(16) INPUT (
.clk(clk),
.in (reset_n ? next_in : 16'b0),
.out(in),
.en (1'b1)
);
register #(4) LEN (
.clk(clk),
.in (reset_n ? next_len : 4'b0),
.out(len),
.en (1'b1)
);
register #(2) STATE (
.clk(clk),
.in (reset_n ? next_state : 2'b0),
.out(state),
.en (1'b1)
);
assign full = (address == aend);
assign shift_temp = {writedata, 16'b0};
assign shift_in = {16'b0, in_bits};
assign curr_len = (in_len == 4'b0) ? 5'd16 : {1'b0, in_len};
assign temp_len = {1'b0, len} + curr_len - 5'd16;
assign new_len = {1'b0, len} + curr_len;
always @(*) begin
write = 1'b0;
rdy = 1'b0;
next_wptr = address;
next_wdata = writedata;
next_in = in;
next_len = len;
next_state = state;
case (state)
2'b00: begin
rdy = (address != aend);
if (setaddr) begin
next_wptr = abase;
end else if (en) begin
if (new_len >= 5'd16) begin
next_state = 2'b01;
next_in = in_bits;
next_wdata = shift_temp[15+len-:16] | shift_in[new_len-1-:16];
next_len = temp_len[3:0];
end else begin
next_wdata = shift_temp[31-in_len-:16] | in_bits;
next_len = new_len[3:0];
end
end
end
2'b01: begin
if (waitrequest == 1'b0) begin
next_state = 2'b00;
write = 1'b1;
next_wdata = in;
next_wptr = address + 32'd2;
end
end
default: begin
next_state = 2'b00;
end
endcase
end
endmodule
| 7.254099 |
module bitstream_counter_simple #(
parameter P_N_WIDTH = 16
) (
input clk,
input rst,
// Controls
input inh,
input a,
input [P_N_WIDTH-1:0] period,
// Previous status
output y,
output reg valid = 0,
output reg update = 0,
output reg [P_N_WIDTH-1:0] n = 0
);
// Internals
reg [P_N_WIDTH-1:0] i_n = 0;
// Window update flag
reg [P_N_WIDTH-1:0] i_cnt = 0;
wire i_update;
assign i_update = (i_cnt >= period - 1);
always @(posedge clk)
if (rst) i_cnt <= 0;
else if (i_update) i_cnt <= 0;
else i_cnt <= i_cnt + 1;
always @(posedge clk)
if (rst) update <= 0;
else update <= i_update;
// Update the outputs
reg valid_0 = 0;
always @(posedge clk)
if (rst) begin
n <= 0;
valid <= valid_0;
valid_0 <= 0;
end else if (i_update) begin
n <= i_n;
valid <= valid_0;
valid_0 <= 1;
end
// Waveform conditions
assign y = a && !inh;
// Update the Internal Counters, don't let them overflow
always @(posedge clk)
if (rst) i_n <= 0;
else if (i_update) i_n <= y;
else if (i_n != {P_N_WIDTH{1'b1}}) i_n <= i_n + {{P_N_WIDTH - 1{1'b0}}, y};
endmodule
| 7.922757 |
module bitstream_ena_gen (
ena,
stream_mem_valid,
rbsp_buffer_valid,
bc_pps_ena,
bc_sps_ena,
bc_slice_header_ena,
bc_slice_data_ena,
bc_ena,
read_nalu_ena,
rbsp_buffer_ena,
pps_ena,
sps_ena,
slice_header_ena,
slice_data_ena,
residual_ena,
intra_pred_ena,
inter_pred_ena,
sum_ena,
ext_mem_writer_ena,
ext_mem_hub_ena
);
input ena;
input stream_mem_valid;
input rbsp_buffer_valid;
input bc_pps_ena;
input bc_sps_ena;
input bc_slice_header_ena;
input bc_slice_data_ena;
output read_nalu_ena;
output rbsp_buffer_ena;
output bc_ena;
output pps_ena;
output sps_ena;
output slice_header_ena;
output slice_data_ena;
output residual_ena;
output intra_pred_ena;
output inter_pred_ena;
output sum_ena;
output ext_mem_writer_ena;
output ext_mem_hub_ena;
assign read_nalu_ena = ena && stream_mem_valid;
assign rbsp_buffer_ena = ena && stream_mem_valid;
assign bc_ena = ena && rbsp_buffer_valid;
assign sps_ena = ena && rbsp_buffer_valid && bc_sps_ena;
assign pps_ena = ena && rbsp_buffer_valid && bc_pps_ena;
assign slice_header_ena = ena && rbsp_buffer_valid && bc_slice_header_ena;
assign slice_data_ena = ena && rbsp_buffer_valid && bc_slice_data_ena;
assign residual_ena = ena && rbsp_buffer_valid;
assign intra_pred_ena = ena;
assign inter_pred_ena = ena;
assign sum_ena = ena;
assign ext_mem_writer_ena = ena;
assign ext_mem_hub_ena = ena;
endmodule
| 7.179131 |
module bitstream_fifo (
read_clk,
rst_n,
read,
stream_out,
stream_out_valid,
stream_over,
write_clk,
write_data,
write_valid,
write_ready
);
input write_clk;
input read_clk;
input rst_n;
input [7:0] write_data;
input write_valid;
output write_ready;
(* KEEP = "TRUE" *) (*mark_debug = "true"*) input read;
(* KEEP = "TRUE" *) (*mark_debug = "true"*) output [7:0] stream_out;
(* KEEP = "TRUE" *) (*mark_debug = "true"*) output stream_out_valid;
(* KEEP = "TRUE" *) (*mark_debug = "true"*) output stream_over;
wire [10:0] usedw;
wire full;
wire empty;
assign stream_out_valid = ~empty;
wire [7:0] nal_data;
stream_fifo stream_fifo_inst (
.rst(~rst_n),
.din(nal_data),
.rd_clk(read_clk),
.rd_en(read),
.wr_clk(write_clk),
.wr_en(nal_data_valid && nal_data_ready),
.dout(stream_out),
.empty(empty),
.full(full),
.wr_data_count()
);
assign nal_data_ready = ~full;
reg ts_data_in_valid;
wire ts_data_out_ready;
wire [7:0] ts_data_out;
wire ts_data_out_valid;
wire ts_data_out_sync;
ts_adapter ts_adapter_inst (
.clk(write_clk),
.reset(~rst_n),
.i_tdata(write_data),
.i_tvalid(write_valid),
.i_tready(write_ready),
.o_tdata(ts_data_out),
.o_tvalid(ts_data_out_valid),
.o_tready(ts_data_out_ready),
.sync(ts_data_out_sync)
);
ts_checker ts_checker_inst (
.clk(write_clk),
.reset(~rst_n),
.i_ts_sync(ts_data_out_sync),
.i_tdata(ts_data_out),
.i_tvalid(ts_data_out_valid),
.i_tready(ts_data_out_ready),
.o_tdata(nal_data),
.o_tvalid(nal_data_valid),
.o_tready(nal_data_ready)
);
/*
stream_fifo stream_fifo (
.aclr(!rst_n),
.clock(clk),
.data(file_data),
.rdreq(read),
.wrreq(),
.empty(empty),
.full(full),
.q(),
.usedw(usedw)
);
*/
endmodule
| 7.20086 |
module bitstream_fifo (
read_clk,
rst_n,
read,
stream_out,
stream_out_valid,
stream_over,
write_clk,
write_data,
write_valid,
write_ready
);
input write_clk;
input read_clk;
input rst_n;
input [7:0] write_data;
input write_valid;
output write_ready;
(* KEEP = "TRUE" *) (*mark_debug = "true"*) input read;
(* KEEP = "TRUE" *) (*mark_debug = "true"*) output [7:0] stream_out;
(* KEEP = "TRUE" *) (*mark_debug = "true"*) output stream_out_valid;
(* KEEP = "TRUE" *) (*mark_debug = "true"*) output stream_over;
wire [10:0] usedw;
wire full;
wire empty;
assign stream_out_valid = ~empty;
/*
stream_fifo stream_fifo_inst(
.rst(~rst_n),
.din(write_data),
.rd_clk(read_clk),
.rd_en(read),
.wr_clk(write_clk),
.wr_en(write_valid),
.dout(stream_out),
.empty(empty),
.full(full),
.wr_data_count(usedw));
*/
dc_fifo #(
.data_bits(8),
.addr_bits(9)
) stream_fifo_inst (
.aclr(~rst_n),
.wr_clk(write_clk),
.wr(write_valid && write_ready),
.wr_data(write_data),
.wr_full(full),
.wr_words_avail(),
.rd_clk(read_clk),
.rd(read),
.rd_data(stream_out),
.rd_words_avail(),
.rd_empty(empty)
);
assign write_ready = ~full;
/*
stream_fifo stream_fifo (
.aclr(!rst_n),
.clock(clk),
.data(file_data),
.rdreq(read),
.wrreq(),
.empty(empty),
.full(full),
.q(),
.usedw(usedw)
);
*/
endmodule
| 7.20086 |
module bitstream_fifo_cfi_flash (
clk,
rst_n,
read,
q,
ready,
flash_addr,
flash_data,
flash_ce_n,
flash_oe_n,
flash_we_n,
flash_rst_n
);
input clk;
input rst_n;
input read;
output [7:0] q;
output ready;
output [21:0] flash_addr;
input [7:0] flash_data;
output flash_ce_n;
output flash_oe_n;
output flash_we_n;
output flash_rst_n;
parameter ReadPeriod = 3;
assign flash_rst_n = rst_n;
reg [2:0] counter;
reg state;
reg first_fill;
reg ready;
wire [6:0] usedw;
wire full;
parameter Idle = 1'b0, Fill = 1'b1;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
state <= Idle;
counter <= 0;
end else
case (state)
Idle: begin
if (usedw[6] == 0 && !full) state <= Fill;
end
Fill: begin
if (full) state <= Idle;
else if (counter < ReadPeriod) counter <= counter + 1;
else counter <= 0;
end
endcase
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
ready <= 0;
first_fill <= 1;
end else begin
if (first_fill && full) begin
ready <= 1;
first_fill <= 0;
end else if (first_fill) ready <= 0;
else ready <= usedw > 1 || full;
end
reg flash_ce_n;
reg flash_oe_n;
reg flash_we_n;
reg [21:0] flash_addr;
always @(*)
if (state == Fill) begin
flash_ce_n <= 0;
flash_oe_n <= 0;
flash_we_n <= 1;
end else begin
flash_ce_n <= 1;
flash_oe_n <= 1;
flash_we_n <= 1;
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
flash_addr <= 0;
end else if (state == Fill && counter == ReadPeriod) flash_addr <= flash_addr + 1;
stream_fifo stream_fifo (
.aclr(!rst_n),
.clock(clk),
.data(flash_data),
.rdreq(read),
.wrreq(state == Fill && counter == ReadPeriod),
.empty(empty),
.full(full),
.q(q),
.usedw(usedw)
);
endmodule
| 7.20086 |
module bitstream_loader (
input prog_clk,
input start,
output config_chain_head,
output reg done
);
parameter BITSTREAM_FILE = "";
parameter BITSTREAM_SIZE = 6140;
reg [BITSTREAM_SIZE<=2 ? 2 : $clog2(BITSTREAM_SIZE):0] bitstream_index;
reg [13:0] bram_addr;
reg [3:0] bram_line_index;
wire bram_output;
assign config_chain_head = bram_output;
EFX_RAM_5K #(
.READ_WIDTH (1),
.WRITE_WIDTH(0),
.INIT_0 (256'h00000000000000000000000000000000000000000000007f00000000000000ff),
.INIT_1 (256'h0000fff8ffffffff000000000000000000000000000000000000000000000000),
.INIT_2 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4 (256'h00000003f8000000000000000000000000000000000000000000000000000000),
.INIT_5 (256'h0000000000000000078000000000000000000000000000000000000000000000),
.INIT_6 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_8 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_9 (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_B (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_C (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_D (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_E (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_F (256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0021000000000000000000000000000000000000000000000000000000000000),
) EFX_RAM_5K_inst (
// Port A Data: 16-bit (each) output: Port A data
.WDATA(0), // Write data
.WADDR(0), // Write address
.WE (0), // Write enable
.WCLK (0),
.WCLKE(0),
.RDATA(bram_output),
.RADDR(bram_addr),
.RE(1'b1),
.RCLK(prog_clk)
);
initial begin
bram_addr <= 0;
bram_line_index <= 0;
bitstream_index <= 0;
done <= 1'b0;
end
always @(posedge prog_clk) begin
if (start && !done) begin
bram_addr <= bram_addr + 1;
bitstream_index <= bitstream_index + 1;
end
if (bitstream_index == BITSTREAM_SIZE) begin
done <= 1'b1;
end
end
endmodule
| 6.794149 |
module bitsum_comp (
input clk,
input resetn,
input [`SEARCH_AREA_W-1:0] data,
output [7:0] sum
);
wire [6:0] sum_h, sum_l;
sum_of_64 sum64l (
.clk(clk),
.resetn(resetn),
.data(data[63:0]),
.sum(sum_l)
);
sum_of_64 sum64h (
//TODO hardcoded
.clk(clk),
.resetn(resetn),
.data({32'h0, data[`SEARCH_AREA_W-1:64]}),
.sum(sum_h)
);
assign sum = sum_h + sum_l;
endmodule
| 6.69517 |
module bitswizzle (
d,
c,
y
);
input wire [3:0] d;
input wire [3:0] c;
output wire [7:0] y;
assign y = {c[2:1], {3{d[0]}}, c[0], 3'b101};
endmodule
| 7.469865 |
module BitSync (
rst,
clk,
yi,
yq,
di,
dq,
sync
);
input rst; //复位信号，高电平有效
input clk; //时钟信号/数据输入速率/4倍符号速率/4 MHz
input signed [15:0] yi; //基带I支路数据/4 MHz
input signed [15:0] yq; //基带Q支路数据/4 MHz
output signed [17:0] di; //插值I支路数据/1 MHz
output signed [17:0] dq; //插值Q支路数据/1 MHz
output sync; //位同步脉冲/1MHz
reg clk_half;
reg signed [15:0] dig, dqg;
always @(posedge clk or posedge rst)
if (rst) begin
clk_half <= 1'b0;
dig <= 16'd0;
dqg <= 16'd0;
end else begin
//对时钟分频，产生位同步模块时钟信号clk_half
clk_half <= !clk_half;
//对基带解调数据实现2倍抽取，送入位同步模块
if (!clk_half) begin
dig <= yi;
dqg <= yq;
end
end
wire signed [15:0] u, e, w;
wire bit_sync;
//实例化位同步模块
FpgaGardner u1 (
.rst(rst),
.clk(clk_half),
.di(dig),
.dq(dqg),
.yi(di),
.yq(dq),
.u(u),
.e(e),
.w(w),
.sync(bit_sync)
);
//bitsync周期为clk_half，载波同步环要求位同步时钟周期为clk
//用clk取bitsync的上升沿作为载波同步环位同步信号
reg bitsync_d;
always @(posedge clk or posedge rst)
if (rst) bitsync_d <= 1'b0;
else bitsync_d <= bit_sync;
assign sync = (!rst) ? (bit_sync & (!bitsync_d)) : 1'b0;
endmodule
| 8.073558 |
module bits_rhs (
output [6:0] out
);
assign out = {4'd8, 3'd5};
endmodule
| 7.355615 |
module is a n-level bits synchronizer.
//
// Dependencies:
// <None>
//
// Revision: 1.0
//
// Parameters:
// STAGE - stages of synchronizer.
// BITS - bit width of original data(input data).
// DEFAULT_LEVEL - reset level, must start with "1'b".
//
// Inputs:
// clk - system clock.
// rst - reset.
// din - data input.
//
// Outputs:
// dout - data output.
////////////////////////////////////////////////////////////////////////////////
module bits_synchronizer #(
parameter STAGE = 3,
parameter BITS = 1,
parameter DEFAULT_LEVEL = 1'b1
)(
input clk,
input rst,
input [BITS - 1:0] din,
output [BITS - 1:0] dout
);
reg [BITS - 1:0] sync_reg [STAGE - 1:0];
genvar i;
always @(posedge clk) begin
if(rst) begin
sync_reg[0] <= {BITS{DEFAULT_LEVEL}};
end
else begin
sync_reg[0] <= din;
end
end
generate
for(i = 0;i < STAGE - 1;i = i + 1) begin : sync_reg_generate
always @(posedge clk) begin
if(rst) begin
sync_reg[i + 1] <= {BITS{DEFAULT_LEVEL}};
end
else begin
sync_reg[i + 1] <= sync_reg[i];
end
end
end
endgenerate
assign dout = sync_reg[STAGE - 1];
endmodule
| 7.8626 |
module bits_to_bytes (
input clock,
input enable,
input reset,
input bit_in,
input input_strobe,
output reg [7:0] byte_out,
output reg output_strobe
);
reg [7:0] bit_buf;
reg [2:0] addr;
always @(posedge clock) begin
if (reset) begin
addr <= 0;
bit_buf <= 0;
byte_out <= 0;
output_strobe <= 0;
end else if (enable & input_strobe) begin
bit_buf[7] <= bit_in;
bit_buf[6:0] <= bit_buf[7:1];
addr <= addr + 1;
if (addr == 7) begin
byte_out <= {bit_in, bit_buf[7:1]};
output_strobe <= 1;
end else begin
output_strobe <= 0;
end
end else begin
output_strobe <= 0;
end
end
endmodule
| 7.248128 |
module BaudTickGen (
input clk,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log2 = log2 + 1;
end
endfunction
localparam AccWidth = log2(ClkFrequency / Baud) + 8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(
Baud * Oversampling >> (31 - AccWidth)
); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk)
if (enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
| 7.463142 |
module BitTime_Counter (
clk,
reset,
DOIT,
K,
BTU
);
input clk, reset;
input DOIT;
input [19:0] K;
output BTU;
reg [19:0] Q;
reg [19:0] mQ;
always @(posedge clk, posedge reset)
if (reset) Q <= 20'b0;
else Q <= mQ;
always @(*) begin
case ({
DOIT, BTU
})
2'b00: mQ = 0;
2'b01: mQ = 0;
2'b10: mQ = Q + 20'b1; //Bit Counter + 1
2'b11: mQ = 0;
endcase
end
assign BTU = (Q == K) ? 1'b1 : 1'b0;
endmodule
| 7.069411 |
module bitty_riscv_sopc (
input wire clk,
input wire rst
);
// 连接指令存储器
wire [`InstAddrBus] inst_addr_o;
wire [ `InstBus] inst_rom_o;
wire core_ce_o;
// risc-v ram
wire mem_ce_i;
wire mem_we_i;
wire [`DataAddrBus] mem_addr_i;
wire [ `DataBus] mem_data_i;
wire [ `DataBus] mem_data_o;
wire [ 3:0] mem_sel_i;
// 例化处理器 bitty risc-v
bitty_riscv u_bitty_riscv (
.clk(clk),
.rst(rst),
.rom_data_i(inst_rom_o),
.pc_addr_o(inst_addr_o),
.pc_ce_o(core_ce_o),
.ram_data_i(mem_data_o),
.ram_addr_o(mem_addr_i),
.ram_data_o(mem_data_i),
.ram_we_o (mem_we_i),
.ram_sel_o (mem_sel_i),
.ram_ce_o (mem_ce_i)
);
// 例化指令存储器 ROM
inst_rom u_inst_rom (
.ce_i (core_ce_o),
.addr_i(inst_addr_o),
.inst_o(inst_rom_o)
);
// ram data
data_ram u_data_ram (
.clk(clk),
.ce(mem_ce_i),
.we(mem_we_i),
.addr(mem_addr_i),
.sel(mem_sel_i),
.data_i(mem_data_i),
.data_o(mem_data_o)
);
endmodule
| 7.969159 |
module bitty_riscv_sopc_tb ();
reg CLOCK_50;
reg rst;
// 每隔 10ns CLOCK_50 信号翻转一次，所以周期是 20ns, 对应 50MHz
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
`ifdef IVERILOG
// 使用文件 inst_rom.data 初始化指令存储器
initial $readmemh("./rtl/sim/inst_rom.data", u_bitty_riscv_sopc.u_inst_rom.inst_mem);
initial $readmemh("./rtl/sim/inst_data0.data", u_bitty_riscv_sopc.u_data_ram.data_mem0);
initial $readmemh("./rtl/sim/inst_data1.data", u_bitty_riscv_sopc.u_data_ram.data_mem1);
initial $readmemh("./rtl/sim/inst_data2.data", u_bitty_riscv_sopc.u_data_ram.data_mem2);
initial $readmemh("./rtl/sim/inst_data3.data", u_bitty_riscv_sopc.u_data_ram.data_mem3);
`else // ModelSim 下
initial $readmemh("inst_rom.data", u_bitty_riscv_sopc.u_inst_rom.inst_mem);
initial $readmemh("inst_data0.data", u_bitty_riscv_sopc.u_data_ram.data_mem0);
initial $readmemh("inst_data1.data", u_bitty_riscv_sopc.u_data_ram.data_mem1);
initial $readmemh("inst_data2.data", u_bitty_riscv_sopc.u_data_ram.data_mem2);
initial $readmemh("inst_data3.data", u_bitty_riscv_sopc.u_data_ram.data_mem3);
`endif
wire [31:0] x3 = u_bitty_riscv_sopc.u_bitty_riscv.u_regsfile.regs[3];
wire [31:0] x26 = u_bitty_riscv_sopc.u_bitty_riscv.u_regsfile.regs[26];
wire [31:0] x27 = u_bitty_riscv_sopc.u_bitty_riscv.u_regsfile.regs[27];
// 最初时刻，复位信号有效，在第 195ns，复位信号无效，最小 SOPC 开始运行
// 运行 1000ns 后，暂停仿真
initial begin
rst = 1'b0;
#195 rst = 1'b1;
$display("--------- test running --------");
wait (x26 == 32'h1); // 测试结束
#100
if (x27 == 32'h1) begin // 27bit 为 1 就 ok
$display("********** ######### ***********");
$display("********** test pass ***********");
$display("********** ######### ***********");
end else begin
$display("********** ######### ***********");
$display("********** test fail ***********");
$display("********** ######### ***********");
$display("test fail inst = %2d", x3); // 第多少条指令出错
end
`ifdef IVERILOG
$finish;
`else
$stop;
`endif
end
initial begin
#100000 $display("#####--Time out--#####");
`ifdef IVERILOG
$finish;
`else
$stop;
`endif
end
`ifdef IVERILOG
initial begin
$display("#####-- Dump start --#####");
$dumpfile("./rtl/sim/bitty_riscv_sopc_tb.vcd");
$dumpvars;
end
`endif
// 例化最小 sopc
bitty_riscv_sopc u_bitty_riscv_sopc (
.clk(CLOCK_50),
.rst(rst)
);
endmodule
| 7.969159 |
module ternary;
wire [5:0] a;
wire [6:0] b;
wire c;
wire [5:0] d = c ? a : b;
initial begin
$display("PASSED");
$finish;
end
endmodule
| 6.762795 |
module BitWiseAndGate_8B (
a,
b,
z
);
input [7:0] a, b;
output [7:0] z;
and a1 (z[0], a[0], b[0]);
and a2 (z[1], a[1], b[1]);
and a3 (z[2], a[2], b[2]);
and a4 (z[3], a[3], b[3]);
and a5 (z[4], a[4], b[4]);
and a6 (z[5], a[5], b[5]);
and a7 (z[6], a[6], b[6]);
and a8 (z[7], a[7], b[7]);
endmodule
| 6.671626 |
module BitWiseAndGate_8B_t ();
reg [7:0] input_a, input_b, output_z;
BitWiseAndGate_8B a (
input_a,
input_b,
output_z
);
task test(input [7:0] A, input [7:0] B);
input_a = A;
input_b = B;
#100;
endtask
initial begin
$dumpfile("BitWiseAndGate_8B.vcd");
$dumpvars;
test(8'b00000000, 8'b00000000);
test(8'b11111111, 8'b11111111);
test(8'b00001111, 8'b11110000);
test(8'b00111100, 8'b01100110);
$finish;
end
endmodule
| 6.671626 |
module BitwiseAND_5Bit (
a,
select,
b
);
input [5:1] a;
input select;
output [5:1] b;
assign b[1] = select & a[1];
assign b[2] = select & a[2];
assign b[3] = select & a[3];
assign b[4] = select & a[4];
assign b[5] = select & a[5];
endmodule
| 7.682698 |
module BitwiseG (
input Ai,
input Bi,
output Gi
);
and #0.1 (Gi, Ai, Bi);
endmodule
| 6.610634 |
module BitWiseInverter_8B (
a,
enable,
z
);
input [7:0] a;
input enable;
output [7:0] z;
xor x1 (z[0], a[0], enable);
xor x2 (z[1], a[1], enable);
xor x3 (z[2], a[2], enable);
xor x4 (z[3], a[3], enable);
xor x5 (z[4], a[4], enable);
xor x6 (z[5], a[5], enable);
xor x7 (z[6], a[6], enable);
xor x8 (z[7], a[7], enable);
endmodule
| 7.402044 |
module BitWiseInverter_8B_t ();
reg [7:0] input_a, output_z;
reg input_enable;
reg [2:0] i;
BitWiseInverter_8B in (
input_a,
input_enable,
output_z
);
task test(input A, input E);
if (A == 0) begin
input_a = 8'b00000000;
end else begin
input_a = 8'b11111111;
end
input_enable = E;
#100;
endtask
initial begin
$dumpfile("BitWiseInverter_8B.vcd");
$dumpvars;
for (i = 3'b000; i < 3'b100; i = i + 3'b001) begin
test(i[0], i[1]);
end
$finish;
end
endmodule
| 7.402044 |
module BitwiseP (
input Ai,
input Bi,
output Pi
);
xor #0.1 (Pi, Ai, Bi);
endmodule
| 7.126071 |
module bitwise_module #(
parameter data_width = 16
) (
input [data_width - 1 : 0] _A,
input [data_width - 1 : 0] _B,
input [3 : 0] func,
output reg [data_width - 1 : 0] _C
);
always @(*) begin
case (func)
`FUNC_ID: begin
_C <= _A;
end
`FUNC_NOT: begin
_C <= ~_A;
end
`FUNC_AND: begin
_C <= _A & _B;
end
`FUNC_OR: begin
_C <= _A | _B;
end
`FUNC_NAND: begin
_C <= ~(_A & _B);
end
`FUNC_NOR: begin
_C <= ~(_A | _B);
end
`FUNC_XOR: begin
_C = _A ^ _B;
end
`FUNC_XNOR: begin
_C <= ~(_A ^ _B);
end
default: begin
_C <= 16'h0000;
end
endcase
end
endmodule
| 7.838613 |
module identity_not_module #(parameter data_width = 16) (
// input [data_width - 1 : 0]_A,
// input func,
// output reg [data_width - 1 : 0] _C
// );
// always @(*) begin
// if(func) // NOT
// _C <= ~_A;
// else // IDENTITY
// _C <= _A;
// end
// endmodule
| 7.772753 |
module and_or_module #(parameter data_width = 16) (
// input [data_width - 1 : 0]_A,
// input [data_width - 1 : 0]_B,
// input func,
// output reg [data_width - 1 : 0] _C
// );
// always @(*) begin
// if(func) // OR
// _C <= _A|_B;
// else // AND
// _C <= _A&_B;
// end
// endmodule
| 7.739475 |
module nand_nor_module #(parameter data_width = 16) (
// input [data_width - 1 : 0]_A,
// input [data_width - 1 : 0]_B,
// input func,
// output reg [data_width - 1 : 0] _C
// );
// always @(*) begin
// if(func) // NOR
// _C <= ~(_A|_B);
// else // NAND
// _C <= ~(_A&_B);
// end
// endmodule
| 7.156314 |
module bitwise_mux(i0,i1,mask,output);
input [7:0] i0;
input [7:0] i1;
input [7:0] mask;
output [7:0] output;
assign output = ;
endmodule
| 7.343592 |
module bitwise_operators ();
initial begin
// Bit Wise Negation
$display(" ~4'b0001 = %b", (~4'b0001));
$display(" ~4'bx001 = %b", (~4'bx001));
$display(" ~4'bz001 = %b", (~4'bz001));
// Bit Wise AND
$display(" 4'b0001 & 4'b1001 = %b", (4'b0001 & 4'b1001));
$display(" 4'b1001 & 4'bx001 = %b", (4'b1001 & 4'bx001));
$display(" 4'b1001 & 4'bz001 = %b", (4'b1001 & 4'bz001));
// Bit Wise OR
$display(" 4'b0001 | 4'b1001 = %b", (4'b0001 | 4'b1001));
$display(" 4'b0001 | 4'bx001 = %b", (4'b0001 | 4'bx001));
$display(" 4'b0001 | 4'bz001 = %b", (4'b0001 | 4'bz001));
// Bit Wise XOR
$display(" 4'b0001 ^ 4'b1001 = %b", (4'b0001 ^ 4'b1001));
$display(" 4'b0001 ^ 4'bx001 = %b", (4'b0001 ^ 4'bx001));
$display(" 4'b0001 ^ 4'bz001 = %b", (4'b0001 ^ 4'bz001));
// Bit Wise XNOR
$display(" 4'b0001 ~^ 4'b1001 = %b", (4'b0001 ~^ 4'b1001));
$display(" 4'b0001 ~^ 4'bx001 = %b", (4'b0001 ~^ 4'bx001));
$display(" 4'b0001 ~^ 4'bz001 = %b", (4'b0001 ~^ 4'bz001));
#10 $finish;
end
endmodule
| 7.179086 |
module Bitwise_PG #(
parameter WIDTH = 16
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:0] G,
output [WIDTH:0] P
);
assign P[0] = 0;
assign G[0] = Cin;
genvar i;
generate
for (i = 1; i <= WIDTH; i = i + 1) begin : bitwise_pg
xor x (P[i], A[i], B[i]);
and a (G[i], A[i], B[i]);
end
endgenerate
endmodule
| 6.727227 |
module implements a parameterized bitwise XOR logic.
module Bitwise_XOR(
input [DATA_WIDTH - 1:0] i_dataA,
input [DATA_WIDTH - 1:0] i_dataB,
output [DATA_WIDTH - 1:0] o_result
);
parameter DATA_WIDTH = 48;
assign o_result = i_dataA ^ i_dataB;
endmodule
| 6.904081 |
module bit_4_carry_lookahead (
input [3:0] a,
input [3:0] b,
input c_0,
output [3:0] s,
output c_4
);
wire [3:0] g;
wire [3:0] p;
wire c_1;
wire c_2;
wire c_3;
assign g[0] = a[0] & b[0];
assign g[1] = a[1] & b[1];
assign g[2] = a[2] & b[2];
assign g[3] = a[3] & b[3];
assign p[0] = a[0] ^ b[0];
assign p[1] = a[1] ^ b[1];
assign p[2] = a[2] ^ b[2];
assign p[3] = a[3] ^ b[3];
assign s[0] = p[0] ^ c_0;
assign c_1 = (c_0 & p[0]) | g[0];
assign s[1] = p[1] ^ c_1;
assign c_2 = (c_1 & p[1]) | g[1];
assign s[2] = p[2] ^ c_2;
assign c_3 = (c_2 & p[2]) | g[2];
assign s[3] = p[3] ^ c_3;
assign c_4 = (c_3 & p[3]) | g[3];
endmodule
| 6.903644 |
module bit_1_full_adder (
input a_i,
input b_i,
input c_i_1,
output s_i,
output c_i
);
wire mid = a_i ^ b_i;
assign s_i = mid ^ c_i_1;
assign c_i = (mid & c_i_1) | (a_i & b_i);
endmodule
| 8.003512 |
module bit_1_full_adder_tb;
reg a_i;
reg b_i;
reg c_i_1;
wire s_i;
wire c_i;
parameter stop_time = 2000;
bit_1_full_adder uut (
.a_i (a_i),
.b_i (b_i),
.c_i_1(c_i_1),
.s_i (s_i),
.c_i (c_i)
);
initial #stop_time $finish;
initial begin
a_i = 0;
b_i = 0;
c_i_1 = 0;
end
always begin
#5 a_i = ~a_i;
end
always begin
#10 b_i = ~b_i;
end
always begin
#15 c_i_1 = ~c_i_1;
end
endmodule
| 8.003512 |
module bit_23_reg (
in,
clk,
rst,
out
);
input [22:0] in;
input clk;
input rst;
output reg [22:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 23'b0000_0000_0000_0000_0000_000;
else out <= in;
end
endmodule
| 7.321384 |
module bit_23_reg_en (
in,
clk,
rst,
enable,
out
);
input [22:0] in;
input clk;
input rst;
input enable;
output reg [22:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 23'b0000_0000_0000_0000_0000_000;
else if (enable) out <= in;
end
endmodule
| 6.867802 |
module bit_24_reg (
in,
clk,
rst,
out
);
input [23:0] in;
input clk;
input rst;
output reg [23:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 24'b0000_0000_0000_0000_0000_0000;
else out <= in;
end
endmodule
| 7.340818 |
module bit_27_reg (
in,
clk,
rst,
out
);
input [26:0] in;
input clk;
input rst;
output reg [26:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 27'b0000_0000_0000_0000_0000_0000_000;
else out <= in;
end
endmodule
| 6.756418 |
module bit_2_reg (
in,
clk,
rst,
out
);
input [1:0] in;
input clk;
input rst;
output reg [1:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 2'b00;
else out <= in;
end
endmodule
| 6.750428 |
module bit_3_reg (
in,
clk,
rst,
out
);
input [2:0] in;
input clk;
input rst;
output reg [2:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 3'b000;
else out <= in;
end
endmodule
| 7.393562 |
module bit_4_carry_lookahead (
input [3:0] a,
input [3:0] b,
input c_0,
output [3:0] s,
output c_4
);
wire [3:0] g;
wire [3:0] p;
wire c_1;
wire c_2;
wire c_3;
assign g[0] = a[0] & b[0];
assign g[1] = a[1] & b[1];
assign g[2] = a[2] & b[2];
assign g[3] = a[3] & b[3];
assign p[0] = a[0] ^ b[0];
assign p[1] = a[1] ^ b[1];
assign p[2] = a[2] ^ b[2];
assign p[3] = a[3] ^ b[3];
assign s[0] = p[0] ^ c_0;
assign c_1 = (c_0 & p[0]) | g[0];
assign s[1] = p[1] ^ c_1;
assign c_2 = (c_1 & p[1]) | g[1];
assign s[2] = p[2] ^ c_2;
assign c_3 = (c_2 & p[2]) | g[2];
assign s[3] = p[3] ^ c_3;
assign c_4 = (c_3 & p[3]) | g[3];
endmodule
| 6.903644 |
module bit_4_ripple_carry_tb;
reg [3:0] a;
reg [3:0] b;
reg c_0;
wire [3:0] s;
wire c_4;
parameter stop_time = 2000;
bit_4_ripple_carry uut (
.a (a),
.b (b),
.c_0(c_0),
.s (s),
.c_4(c_4)
);
initial #stop_time $finish;
initial begin
a = 0;
b = 0;
c_0 = 0;
end
always begin
#5 a[0] = ~a[0];
end
always begin
#10 a[1] = ~a[1];
end
always begin
#15 a[2] = ~a[2];
end
always begin
#20 a[3] = ~a[3];
end
always begin
#25 b[0] = ~b[0];
end
always begin
#30 b[1] = ~b[1];
end
always begin
#35 b[2] = ~b[2];
end
always begin
#40 b[3] = ~b[3];
end
always begin
#45 c_0 = ~c_0;
end
endmodule
| 6.637454 |
module bit_1_full_adder (
input a_i,
input b_i,
input c_i_1,
output s_i,
output c_i
);
wire mid = a_i ^ b_i;
assign s_i = mid ^ c_i_1;
assign c_i = (mid & c_i_1) | (a_i & b_i);
endmodule
| 8.003512 |
module bit_4_ripple_carry (
input [3:0] a,
input [3:0] b,
input c_0,
output [3:0] s,
output c_4
);
wire c_1, c_2, c_3;
bit_1_full_adder ux1 (
a[0],
b[0],
c_0,
s[0],
c_1
);
bit_1_full_adder ux2 (
a[1],
b[1],
c_1,
s[1],
c_2
);
bit_1_full_adder ux3 (
a[2],
b[2],
c_2,
s[2],
c_3
);
bit_1_full_adder ux4 (
a[3],
b[3],
c_3,
s[3],
c_4
);
endmodule
| 6.637454 |
module bit_4_ripple_carry_tb;
reg [3:0] a;
reg [3:0] b;
reg c_0;
wire [3:0] s;
wire c_4;
parameter stop_time = 2000;
bit_4_ripple_carry uut (
.a (a),
.b (b),
.c_0(c_0),
.s (s),
.c_4(c_4)
);
initial #stop_time $finish;
initial begin
a = 0;
b = 0;
c_0 = 0;
end
always begin
#5 a[0] = ~a[0];
end
always begin
#10 a[1] = ~a[1];
end
always begin
#15 a[2] = ~a[2];
end
always begin
#20 a[3] = ~a[3];
end
always begin
#25 b[0] = ~b[0];
end
always begin
#30 b[1] = ~b[1];
end
always begin
#35 b[2] = ~b[2];
end
always begin
#40 b[3] = ~b[3];
end
always begin
#45 c_0 = ~c_0;
end
endmodule
| 6.637454 |
module bit_53_reg (
in,
clk,
rst,
out
);
input [52:0] in;
input clk;
input rst;
output reg [52:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 53'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0;
else out <= in;
end
endmodule
| 6.695577 |
module bit_56_reg (
in,
clk,
rst,
out
);
input [55:0] in;
input clk;
input rst;
output reg [55:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 56'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
else out <= in;
end
endmodule
| 7.400274 |
module bit_5_reg (
in,
clk,
rst,
out
);
input [4:0] in;
input clk;
input rst;
output reg [4:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 5'b00000;
else out <= in;
end
endmodule
| 6.934471 |
module bit_8_reg (
in,
clk,
rst,
out
);
input [7:0] in;
input clk;
input rst;
output reg [7:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 8'b0000_0000;
else out <= in;
end
endmodule
| 7.156376 |
module bit_8_reg_en (
in,
clk,
rst,
enable,
out
);
input [7:0] in;
input clk;
input rst;
input enable;
output reg [7:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 8'b0000_0000;
else if (enable) out <= in;
end
endmodule
| 7.003227 |
module //
// //
// Dependencies: None //
// //
//--------------------------------------------------------------------------------//
// Revision 0.02 - Updated with standard full adder module //
//--------------------------------------------------------------------------------//
module bit_adder (
input i_data_A,
input i_data_B,
input i_carry,
output o_sum,
output o_carry
);
wire prtl_sum;
assign prtl_sum = i_data_A ^ i_data_B;
assign o_sum = prtl_sum ^ i_carry;
assign o_carry = (prtl_sum && i_carry) || (i_data_A && i_data_B);
endmodule
| 8.238592 |
module bit_adj_32b_to_16b (
Data_in,
Data_out
);
input [31:0] Data_in;
output [15:0] Data_out;
wire [31:0] Data_in;
wire [15:0] Data_out;
wire [15:0] truncate_temp;
wire [15:0] rounding_temp;
assign truncate_temp = Data_in[27:12];
assign rounding_temp = {15'b0, Data_in[11]};
ksa_top_16b ksa_top_16b_inst0 (
.c0(1'b0),
.i_a(truncate_temp),
.i_b(rounding_temp),
.o_s(Data_out),
.o_carry()
);
endmodule
| 6.660614 |
module bit_align_102 (
input clk,
input rst,
input [9:0] data,
output reg flip,
output reg bitslip,
output reg aligned
);
localparam CLK_FREQ = 27'h47868c0;
localparam TOKEN_CTR_SIZE = 3'h7;
reg blank;
localparam INIT_state = 3'd0;
localparam SEARCH_state = 3'd1;
localparam BITSLIP_state = 3'd2;
localparam RX_TOKEN_state = 3'd3;
localparam ALIGNED_state = 3'd4;
reg [2:0] M_state_d, M_state_q = INIT_state;
reg [1:0] M_ctrl_rx_d, M_ctrl_rx_q = 1'h0;
reg [19:0] M_search_ctr_d, M_search_ctr_q = 1'h0;
reg [6:0] M_token_ctr_d, M_token_ctr_q = 1'h0;
reg [2:0] M_bitslip_ctr_d, M_bitslip_ctr_q = 1'h0;
always @* begin
M_state_d = M_state_q;
M_search_ctr_d = M_search_ctr_q;
M_bitslip_ctr_d = M_bitslip_ctr_q;
M_token_ctr_d = M_token_ctr_q;
M_ctrl_rx_d = M_ctrl_rx_q;
flip = M_bitslip_ctr_q[2+0-:1];
bitslip = 1'h0;
aligned = M_state_q == ALIGNED_state;
M_ctrl_rx_d[0+0-:1] = (data == 10'h354) || (data == 10'h0ab) || (data == 10'h154) || (data == 10'h2ab);
M_ctrl_rx_d[1+0-:1] = M_ctrl_rx_q[0+0-:1];
blank = M_ctrl_rx_q == 2'h1;
M_search_ctr_d = M_search_ctr_q + 1'h1;
M_token_ctr_d = 1'h0;
case (M_state_q)
INIT_state: begin
M_bitslip_ctr_d = 1'h0;
if ((&M_search_ctr_q)) begin
M_state_d = SEARCH_state;
end
end
SEARCH_state: begin
if (blank) begin
M_state_d = RX_TOKEN_state;
end else begin
if ((&M_search_ctr_q)) begin
M_state_d = BITSLIP_state;
end
end
end
BITSLIP_state: begin
bitslip = 1'h1;
M_bitslip_ctr_d = M_bitslip_ctr_q + 1'h1;
M_search_ctr_d = 1'h0;
M_state_d = SEARCH_state;
end
RX_TOKEN_state: begin
M_token_ctr_d = M_token_ctr_q + 1'h1;
if (M_ctrl_rx_q[0+0-:1]) begin
if ((&M_token_ctr_q)) begin
M_state_d = ALIGNED_state;
end
end else begin
M_search_ctr_d = 1'h0;
M_state_d = SEARCH_state;
end
end
endcase
end
always @(posedge clk) begin
M_ctrl_rx_q <= M_ctrl_rx_d;
M_search_ctr_q <= M_search_ctr_d;
M_token_ctr_q <= M_token_ctr_d;
M_bitslip_ctr_q <= M_bitslip_ctr_d;
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
endmodule
| 7.077305 |
module BIT_AND (
Reg1,
Reg2,
Out
);
input [15:0] Reg1, Reg2;
output [15:0] Out;
assign Out = Reg1 & Reg2;
endmodule
| 7.143688 |
module bit_com (
info_bits,
esti_bits,
ham_dis
);
input [11:0] info_bits, esti_bits;
output [3:0] ham_dis;
reg [3:0] count;
always @(*) begin
count = 0;
if (info_bits[0] != esti_bits[0]) begin
count = count + 1;
end
if (info_bits[1] != esti_bits[1]) begin
count = count + 1;
end
if (info_bits[2] != esti_bits[2]) begin
count = count + 1;
end
if (info_bits[3] != esti_bits[3]) begin
count = count + 1;
end
if (info_bits[4] != esti_bits[4]) begin
count = count + 1;
end
if (info_bits[5] != esti_bits[5]) begin
count = count + 1;
end
if (info_bits[6] != esti_bits[6]) begin
count = count + 1;
end
if (info_bits[7] != esti_bits[7]) begin
count = count + 1;
end
if (info_bits[8] != esti_bits[8]) begin
count = count + 1;
end
if (info_bits[9] != esti_bits[9]) begin
count = count + 1;
end
if (info_bits[10] != esti_bits[10]) begin
count = count + 1;
end
if (info_bits[11] != esti_bits[11]) begin
count = count + 1;
end
end
assign ham_dis = count;
endmodule
| 7.001136 |
module bit_counter (
sys_clk,
reset,
counter_reset,
counter_en,
scan_code_ready
);
input sys_clk, reset;
input counter_reset, counter_en;
output scan_code_ready;
wire scan_code_ready;
reg [3:0] bit_count = 0;
assign scan_code_ready = (bit_count == 11);
always @(posedge sys_clk) begin
if (reset || scan_code_ready || counter_reset) bit_count <= 0; // normal reset
else if (counter_en) bit_count <= bit_count + 1;
end
endmodule
| 6.711719 |
module bit_endian_converter (
ENABLE,
DATA_IN,
DATA_OUT
);
parameter DATA_WIDTH = 32; //8, 16, 32, 64
input ENABLE;
input [DATA_WIDTH-1:0] DATA_IN;
output [DATA_WIDTH-1:0] DATA_OUT;
genvar i;
generate
if (DATA_WIDTH == 8) begin
for (i = 0; i < 8; i = i + 1) begin : bit_endian_conv_loop
assign DATA_OUT[i] = ENABLE ? DATA_IN[DATA_WIDTH-1-i] : DATA_IN[i];
end
end else if (DATA_WIDTH == 16) begin
for (i = 0; i < 8; i = i + 1) begin : bit_endian_conv_loop
assign DATA_OUT[i] = ENABLE ? DATA_IN[DATA_WIDTH-1-8-i] : DATA_IN[i];
assign DATA_OUT[i+8] = ENABLE ? DATA_IN[DATA_WIDTH-1-i] : DATA_IN[i+8];
end
end else if (DATA_WIDTH == 32) begin
for (i = 0; i < 8; i = i + 1) begin : bit_endian_conv_loop
assign DATA_OUT[i] = ENABLE ? DATA_IN[DATA_WIDTH-1-24-i] : DATA_IN[i];
assign DATA_OUT[i+8] = ENABLE ? DATA_IN[DATA_WIDTH-1-16-i] : DATA_IN[i+8];
assign DATA_OUT[i+16] = ENABLE ? DATA_IN[DATA_WIDTH-1-8-i] : DATA_IN[i+16];
assign DATA_OUT[i+24] = ENABLE ? DATA_IN[DATA_WIDTH-1-i] : DATA_IN[i+24];
end
end else if (DATA_WIDTH == 64) begin
for (i = 0; i < 8; i = i + 1) begin : bit_endian_conv_loop
assign DATA_OUT[i] = ENABLE ? DATA_IN[DATA_WIDTH-1-56-i] : DATA_IN[i];
assign DATA_OUT[i+8] = ENABLE ? DATA_IN[DATA_WIDTH-1-48-i] : DATA_IN[i+8];
assign DATA_OUT[i+16] = ENABLE ? DATA_IN[DATA_WIDTH-1-40-i] : DATA_IN[i+16];
assign DATA_OUT[i+24] = ENABLE ? DATA_IN[DATA_WIDTH-1-32-i] : DATA_IN[i+24];
assign DATA_OUT[i+32] = ENABLE ? DATA_IN[DATA_WIDTH-1-24-i] : DATA_IN[i+32];
assign DATA_OUT[i+40] = ENABLE ? DATA_IN[DATA_WIDTH-1-16-i] : DATA_IN[i+40];
assign DATA_OUT[i+48] = ENABLE ? DATA_IN[DATA_WIDTH-1-8-i] : DATA_IN[i+48];
assign DATA_OUT[i+56] = ENABLE ? DATA_IN[DATA_WIDTH-1-i] : DATA_IN[i+56];
end
end
endgenerate
endmodule
| 8.118498 |
module Bit_Extender_12_32_SIGN (
imm_in,
imm_out
);
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input [11:0] imm_in;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output reg [31:0] imm_out;
always @(*) begin
imm_out = {{(20) {imm_in[11]}}, imm_in};
end
endmodule
| 8.92285 |
module Bit_Extender_20_32 (
imm_in,
imm_out
);
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input [19:0] imm_in;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output reg [31:0] imm_out;
always @(*) begin
imm_out = {{(12) {1'b0}}, imm_in};
end
endmodule
| 8.92285 |
module Bit_Extender_20_32_SIGN (
imm_in,
imm_out
);
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input [19:0] imm_in;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output reg [31:0] imm_out;
always @(*) begin
imm_out = {{(12) {imm_in[19]}}, imm_in};
end
endmodule
| 8.92285 |
module bit_flipper (
input clock,
input reset_n,
input unsigned [1:0] addr,
input rd_en,
input wr_en,
output reg unsigned [31:0] dataOut,
input unsigned [31:0] dataIn
);
reg unsigned [31:0] saved_value; // temp reg for result
integer i;
// writing
always @(posedge clock) begin
if (reset_n == 0) // synchronous reset
saved_value <= 32'b0; // clear result on reset
else if (wr_en == 1 && addr == 2'b00) // if write to address 0
saved_value <= dataIn; // store result
else if (wr_en == 1 && addr == 2'b01) // if write to address 1
saved_value <= saved_value + 1; // increment result
end
// reading
always @(*) begin
dataOut <= 32'b0; // default value is 0
if (rd_en == 1) begin
if (addr == 2'b00) begin // if reading from address 0
for (i = 0; i < 32; i = i + 1) dataOut[i] <= saved_value[31-i]; // flip bit order
end else if (addr == 2'b01) // if reading from address 1
dataOut <= saved_value; // give back result
else if (addr == 2'b10) // if reading from address 2
dataOut <= ~saved_value; // give back inverse all bits of result
end
end
endmodule
| 7.002793 |
module Bit_Getter (
input clk_100MHz,
input micData,
output reg pwm_val
);
parameter kHZ_Cnt = 5120; // 16*320
parameter Begin_kHZ_Cnt = 0;
parameter least_value = 2720; // 16*170
reg [12:0] begin_Cnt = 0;
reg [12:0] micInUse_Cnt = 0;
reg [12:0] micInUse = 0;
always @(posedge (clk_100MHz)) begin
if (begin_Cnt >= Begin_kHZ_Cnt) begin
if (micInUse_Cnt >= kHZ_Cnt) begin
micInUse_Cnt <= 0;
pwm_val <= (micInUse < least_value) ? 0 : 1;
micInUse <= 0;
end else begin
micInUse_Cnt <= micInUse_Cnt + 1;
micInUse <= micInUse + micData;
end
end else begin
begin_Cnt <= begin_Cnt + 1;
end
end
endmodule
| 6.889346 |
module sign_extend (
sOut32,
sIn16
);
output [31:0] sOut32;
input [15:0] sIn16;
assign sOut32 = {{16{sIn16[15]}}, sIn16};
endmodule
| 7.581479 |
module
module shift_left_2(Out32, In32);
output [31:0] Out32;
input [31:0] In32;
assign Out32 = {In32[29:0],2'b00};
endmodule
| 7.458004 |
module zero_extend (
zOut32,
zIn16
);
output [31:0] zOut32;
input [15:0] zIn16;
assign zOut32 = {{16{1'b0}}, zIn16};
endmodule
| 7.606311 |
module BIT_OR (
Reg1,
Reg2,
Out
);
input [15:0] Reg1, Reg2;
output [15:0] Out;
assign Out = Reg1 | Reg2;
endmodule
| 6.685946 |
module BIT_P (
output BP,
input A,
B
);
xor (BP, A, B);
endmodule
| 7.449601 |
module bit_queue #(
parameter integer bit_width = 64
) (
input wire rst,
clk,
input wire chk_in,
input wire [bit_width-1:0] bit_in,
input wire [bit_width-1:0] clr_in,
output reg [bit_width-1:0] bit_out
);
generate
genvar i;
for (i = 0; i < bit_width; i = i + 1) begin : bit_latch
always @(posedge clr_in[i] or posedge clk) begin
if (clr_in[i]) // NOTE: must be asynchronous clear!
bit_out[i] <= 1'b0;
else if (chk_in) bit_out[i] <= bit_in[i];
end
end
endgenerate
endmodule
| 6.868873 |
module bit_register (
clk,
input_enable,
output_enable,
data,
out
);
input clk, input_enable, output_enable, data;
output out;
wire not_out;
wire buf_out;
wire mem_data;
assign mem_data = (buf_out && ~input_enable) || (input_enable && data);
d_flip_flop flip_memory (
clk,
mem_data,
buf_out,
not_out
);
buffer buf_memory (
buf_out,
output_enable,
out
);
endmodule
| 6.556423 |
module buffer (
data,
enable,
out
);
input data, enable;
output reg out;
always @* begin
if (enable == 1) begin
out <= data;
end else begin
out <= 1'bZ;
end
end
endmodule
| 6.861394 |
module bit_register_tb;
reg input_enable, output_enable, data;
wire out, clk;
test_clock clock (clk);
bit_register uut (
clk,
input_enable,
output_enable,
data,
out
);
initial begin
$dumpfile("bit_register_tb.vcd");
$dumpvars(0, bit_register_tb);
input_enable <= 0;
output_enable <= 0;
data <= 0;
#2 input_enable <= 1; // Enable input
data <= 1; // Set data high
// On next clock pulse, the memory should go hgih
#2 input_enable <= 0; // Disable input
data <= 0; // Set data low
// Memory must stay high
#3 output_enable <= 1;
#1 output_enable <= 0; // Enable output for one clock pulse
// Output must show high
#2 input_enable <= 1;
#2 input_enable <= 0; // Enable input for one clock pulse
// Memory must switch to low
#2 output_enable <= 1;
#1 output_enable <= 0; // Enable output for one clock pulse
// Output must show low
#10 $finish;
$display("Test Complete");
end
endmodule
| 6.519573 |
module //
// Date: June 2012 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic functionality of the module, more //
// comprehensive testing is done in the python test file //
// //
//============================================================================//
module bit_reorder_tb;
//===================
// local paramters
//===================
localparam LOCAL_DATA_WIDTH = `ifdef DATA_WIDTH `DATA_WIDTH `else 32 `endif;
//=============
// local regs
//=============
reg en;
reg [LOCAL_DATA_WIDTH-1:0] in;
//==============
// local wires
//==============
wire [LOCAL_DATA_WIDTH-1:0] out;
//=====================================
// instance, "(d)esign (u)nder (t)est"
//=====================================
bit_reorder #(
.DATA_WIDTH (`ifdef DATA_WIDTH `DATA_WIDTH `else 32 `endif),
.BIT0 (0),
.BIT1 (5),
.BIT2 (6),
.BIT3 (7),
.BIT4 (1),
.BIT5 (2),
.BIT6 (3),
.BIT7 (4),
.BIT8 (8),
.BIT9 (9),
.BIT10 (10),
.BIT11 (11),
.BIT12 (12),
.BIT13 (13),
.BIT14 (14),
.BIT15 (15),
.BIT16 (16),
.BIT17 (17),
.BIT18 (18),
.BIT19 (19),
.BIT20 (20),
.BIT21 (21),
.BIT22 (22),
.BIT23 (23),
.BIT24 (24),
.BIT25 (25),
.BIT26 (26),
.BIT27 (27),
.BIT28 (28),
.BIT29 (29),
.BIT30 (30),
.BIT31 (31)
) dut (
.en (en),
.in (in),
.out (out)
);
//=============
// initialize
//=============
initial begin
$dumpvars;
en = 1;
in = 32'b11110000111100001111000011110000;
end
//===============
// print output
//===============
always #1
$display("%b", out);
//===============================
// finish after 100 clock cycles
//===============================
initial #10 $finish;
endmodule
| 8.238592 |
module bit_reversal
#(
parameter DATA_SIZE = 32
)
(
//OUTPUTS
output [DATA_SIZE - 1 : 0] data_out,
//INPUTS
input [DATA_SIZE - 1 : 0] data_in,
input [1 : 0] rev_type
);
//Bit reversing types
localparam NO_REVERSE = 2'b00;
localparam BYTE = 2'b01;
localparam HALF_WORD = 2'b10;
localparam WORD = 2'b11;
localparam TYPES = 4;
wire [DATA_SIZE - 1 : 0] data_reversed[0 : 3];
assign data_reversed[NO_REVERSE] = data_in; //bit order not affected
generate
genvar i, type;
for(type = 1 ; type < TYPES; type = type + 1)
for(i = 0; i < DATA_SIZE; i = i + 1)
begin
if(i < `size)
assign data_reversed[type][i] = data_in[`size*((i/`size) + 1) - 1 - i];
else
assign data_reversed[type][i] = data_in[`size*((i/`size) + 1) - 1 - (i%(`size*(i/`size)))];
end
endgenerate
//Output Mux
assign data_out = data_reversed[rev_type];
endmodule
| 6.714069 |
module bit_reverser #(
parameter WIDTH = 4
) (
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
);
genvar i;
for (i = 0; i < WIDTH; i = i + 1) begin
assign out[i] = in[WIDTH-1-i];
end
endmodule
| 6.690113 |
module bit_searcher_2 (
input wire [1:0] bits,
input wire target,
input wire direction,
output wire hit,
output reg index
);
assign hit = (bits[1:0] != {2{~target}});
always @(*) begin
if (direction) begin
if (bits[1] == ~target) index = 1'b0;
else index = 1'b1;
end else begin
if (bits[0] == ~target) index = 1'b1;
else index = 1'b0;
end
end
endmodule
| 8.72533 |
module bit_searcher_4 (
input wire [3:0] bits,
input wire target,
input wire direction,
output wire hit,
output reg [1:0] index
);
assign hit = (bits[3:0] != {4{~target}});
always @(*) begin
if (direction) begin
if (bits[3:1] == {3{~target}}) index = 2'b00;
else if (bits[3:2] == {2{~target}}) index = 2'b01;
else if (bits[3] == ~target) index = 2'b10;
else index = 2'b11;
end else begin
if (bits[2:0] == {3{~target}}) index = 2'b11;
else if (bits[1:0] == {2{~target}}) index = 2'b10;
else if (bits[0] == ~target) index = 2'b01;
else index = 2'b00;
end
end
endmodule
| 8.72533 |
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