code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bitriquatB;
/* Make an init that pulses once. */
reg init = 1;
initial begin
#1000 init = 0;
#20000 $stop;
end
initial begin
$dumpfile("bitriquatB.vcd");
$dumpvars(0, bitriquatB);
end
wire [3:0] quatout;
wire [2:0] trinary;
wire [1:0] binary;
wire quatcomp;
ring3gen TB1 (... | 6.904288 |
module bitriquatC (
output [3:0] quatout,
input quatoutcomp,
init
);
/* Make an init that pulses once. */
/* reg init = 1;
initial begin
# 1000 init = 0;
# 20000 $stop;
end
initial
begin
$dumpfile("bitriquatC.vcd");
$dumpvars(0, bitriquatC);
end
*/
//wire [3:0] quatout;
wir... | 6.823705 |
module bits2prm_tb ();
`include "paramList.v"
reg start;
reg reset;
reg clk;
wire done;
reg muxSelect;
reg [11:0] memReadAddrTest;
wire [31:0] memInTest;
reg [11:0] memWriteAddrTest;
reg [31:0] memOutTest;
reg memWriteEnTest;
//I/O regs
reg [15:0] bitstream_data[0:400000];
reg [15:0] pr... | 6.644274 |
module bitscan (
req,
sel
);
parameter WIDTH = 16;
input [WIDTH-1:0] req;
output [WIDTH-1:0] sel;
assign sel = req & ~(req - 1);
endmodule
| 7.452063 |
module returns the bit in the lowest order bit in the input with 0 as a 1. All
// other bits in output are Zero.
//
//
// ... | 7.105653 |
module bitscan_tb ();
parameter WIDTH = 16;
reg [WIDTH-1:0] req;
wire [WIDTH-1:0] sel;
bitscan b (
.req(req),
.sel(sel)
);
defparam b.WIDTH = WIDTH;
initial begin
req = 16'h8000;
end
integer n;
reg [WIDTH-1:0] result;
reg fail = 0;
always begin
#100 req = $random & $rand... | 6.81586 |
module BUFT (
inout wire TO,
input wire D,
input wire E,
input wire CLK
);
reg save;
assign TO = E ? save : 2'bz;
always @(posedge CLK) save <= D;
endmodule
| 8.419665 |
module bit_find_last_bit (
bits,
bitsOutIndex,
found
);
parameter WIDTH = 128;
input [WIDTH-1:0] bits;
output [WIDTH-1:0] bitsOutIndex;
output found;
wire [WIDTH:0] bits1 = {bits, 1'b1};
wire [WIDTH:0] match;
wire notFound;
assign {bitsOutIndex, notFound} = match;
assign found = ~notFoun... | 7.001777 |
module bit_alloc (
clkEn,
bits,
needed0,
needed1,
needed2,
needed3,
bitsOut0,
bitsOut1,
bitsOut2,
bitsOut3,
doStall
);
parameter WIDTH = 32;
input clkEn;
input [WIDTH-1:0] bits;
input needed0;
input needed1;
input needed2;
input needed3;
output [WIDTH-1:0] bi... | 6.678962 |
module bit_is_single_bit (
bits,
isSingle
);
parameter WIDTH = 32;
input [WIDTH-1:0] bits;
output isSingle;
wire [WIDTH-1:0] singleBits;
genvar i;
generate
for (i = 0; i <= WIDTH - 1; i = i + 1) begin : bits_block
assign singleBits[i] = (bits == ({{(WIDTH - 1) {1'b0}}, 1'b1} << i));
... | 7.218538 |
module select2From8 (
X_all,
pos,
ans
);
input [7:0] X_all;
input [1:0] pos;
output reg [1:0] ans;
always @* begin
case (pos)
0: ans <= X_all[1:0];
1: ans <= X_all[3:2];
2: ans <= X_all[5:4];
3: ans <= X_all[7:6];
endcase
end
endmodule
| 8.363102 |
module select4From64 (
X_all,
pos,
ans
);
input [63:0] X_all;
input [3:0] pos;
output reg [3:0] ans;
always @* begin
case (pos)
0: ans <= X_all[3:0];
1: ans <= X_all[7:4];
2: ans <= X_all[11:8];
3: ans <= X_all[15:12];
4: ans <= X_all[19:16];
5: ans <= X... | 7.179536 |
module select5From80 (
X_all,
pos,
ans
);
input [79:0] X_all;
input [3:0] pos;
output reg [4:0] ans;
always @* begin
case (pos)
0: ans <= X_all[4:0];
1: ans <= X_all[9:5];
2: ans <= X_all[14:10];
3: ans <= X_all[19:15];
4: ans <= X_all[24:20];
5: ans <= ... | 6.783632 |
module bitSerialAdder (
input clk,
input rst_shift,
input rst_ff,
input load,
input sipo_load,
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout
);
wire [7:0] x, z;
wire s, c;
ShiftReg INST1 (
clk,
rst_shift,
load,
a,
x
... | 6.521384 |
module bitSerialAdder_tb;
// Inputs
reg clk;
reg rst_shift;
reg rst_ff;
reg load;
reg sipo_load;
reg [7:0] a;
reg [7:0] b;
reg cin;
// Outputs
wire [7:0] sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
bitSerialAdder uut (
.clk(clk),
.rst_shift(rst_shift),
.rst_... | 6.521384 |
module BitSetClr (
input [15:0] ir, // Instruction word
input [ 7:0] io_rdata, // I/O register read data
input [ 7:0] rf_rdata, // Register file read data
input [ 7:0] sreg, // Status register
input sr_tf, // Transfer bit in status register
... | 7.096826 |
module mux2 (
input wire i0,
i1,
j,
output wire o
);
assign o = (j == 0) ? i0 : i1;
endmodule
| 7.816424 |
module barrelshifter16 (
input wire [15:0] i,
input wire [ 3:0] s,
input wire [ 1:0] op,
output wire [15:0] o
);
wire [15:0] t1, t2, t3;
bitshift8 b8 (
i,
s[3],
op,
t1
);
bitshift4 b4 (
t1,
s[2],
op,
t2
);
bitshift2 b2 (
t2,
s[1... | 6.846779 |
module: shift_reg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BitshiftTest;
// Inputs
reg rx;
reg rst;
reg baud_clk;
// Outputs
wire [149:0] shifted_bus;
// Instantiate... | 7.194325 |
module BitShift_Button (
// input i_Clk,
input i_Switch_2,
input i_Switch_4,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
... | 7.247579 |
module BitsMuxModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire [7:0] Addr,
input wire [7:0] Value,
output wire [1:0] pixelBits
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1... | 7.742495 |
module bitsplit (
input clk,
input bit1_i,
input bit2_i,
output largebit_o,
output smallbit_o,
input swap_i,
output swap_o,
input run_i,
output run_o
);
reg r_bit1;
reg r_bit2;
reg r_small_bit;
reg r_large_bit;
reg r_compare_result;
... | 7.065534 |
module bitstream (
input clk,
input reset_n,
// Data interface
output reg rdy,
input en,
input [15:0] in_bits,
input [3:0] in_len,
// Control interface
output full,
input setaddr,
input [31:0] abase,
input [31:0] aend,
// Avalon Master
output [31:0] address,
o... | 7.254099 |
module bitstream_counter_simple #(
parameter P_N_WIDTH = 16
) (
input clk,
input rst,
// Controls
input inh,
input a,
input [P_N_WIDTH-1:0] period,
// Previous status
output y... | 7.922757 |
module bitstream_ena_gen (
ena,
stream_mem_valid,
rbsp_buffer_valid,
bc_pps_ena,
bc_sps_ena,
bc_slice_header_ena,
bc_slice_data_ena,
bc_ena,
read_nalu_ena,
rbsp_buffer_ena,
pps_ena,
sps_ena,
slice_header_ena,
slice_data_ena,
residual_ena,
intra_pred_ena,
... | 7.179131 |
module bitstream_fifo (
read_clk,
rst_n,
read,
stream_out,
stream_out_valid,
stream_over,
write_clk,
write_data,
write_valid,
write_ready
);
input write_clk;
input read_clk;
input rst_n;
input [7:0] write_data;
input write_valid;
output write_ready;
(* KEEP = "TRUE... | 7.20086 |
module bitstream_fifo (
read_clk,
rst_n,
read,
stream_out,
stream_out_valid,
stream_over,
write_clk,
write_data,
write_valid,
write_ready
);
input write_clk;
input read_clk;
input rst_n;
input [7:0] write_data;
input write_valid;
output write_ready;
(* KEEP = "TRUE... | 7.20086 |
module bitstream_fifo_cfi_flash (
clk,
rst_n,
read,
q,
ready,
flash_addr,
flash_data,
flash_ce_n,
flash_oe_n,
flash_we_n,
flash_rst_n
);
input clk;
input rst_n;
input read;
output [7:0] q;
output ready;
output [21:0] flash_addr;
input [7:0] flash_data;
output ... | 7.20086 |
module bitstream_loader (
input prog_clk,
input start,
output config_chain_head,
output reg done
);
parameter BITSTREAM_FILE = "";
parameter BITSTREAM_SIZE = 6140;
reg [BITSTREAM_SIZE<=2 ? 2 : $clog2(BITSTREAM_SIZE):0] bitstream_index;
reg [13:0] bram_addr;
reg [3:0] bram_line_index;
wir... | 6.794149 |
module bitsum_comp (
input clk,
input resetn,
input [`SEARCH_AREA_W-1:0] data,
output [7:0] sum
);
wire [6:0] sum_h, sum_l;
sum_of_64 sum64l (
.clk(clk),
.resetn(resetn),
.data(data[63:0]),
.sum(sum_l)
);
sum_of_64 sum64h (
//TODO hardcoded
.clk(clk),
... | 6.69517 |
module bitswizzle (
d,
c,
y
);
input wire [3:0] d;
input wire [3:0] c;
output wire [7:0] y;
assign y = {c[2:1], {3{d[0]}}, c[0], 3'b101};
endmodule
| 7.469865 |
module BitSync (
rst,
clk,
yi,
yq,
di,
dq,
sync
);
input rst; //复位信号，高电平有效
input clk; //时钟信号/数据输入速率/4倍符号速率/4 MHz
input signed [15:0] yi; //基带I支路数据/4 MHz
input signed [15:0] yq; //基带Q支路数据/4 MHz
output signed [17:0] di; //插值I支路数据/1 MHz
output signed [17:0] dq; //插值Q支路数据/1 MH... | 8.073558 |
module bits_rhs (
output [6:0] out
);
assign out = {4'd8, 3'd5};
endmodule
| 7.355615 |
module is a n-level bits synchronizer.
//
// Dependencies:
// <None>
//
// Revision: 1.0
//
// Parameters:
// STAGE - stages of synchronizer.
// BITS - bit width of original data(input data).
// DEFAULT_LEVEL - reset level, must start with "1'b".
//
// Inputs:
// clk - system clock.
// rst - reset.
/... | 7.8626 |
module bits_to_bytes (
input clock,
input enable,
input reset,
input bit_in,
input input_strobe,
output reg [7:0] byte_out,
output reg output_strobe
);
reg [7:0] bit_buf;
reg [2:0] addr;
always @(posedge clock) begin
if (reset) begin
addr <= 0;
bit_buf <= 0;
b... | 7.248128 |
module BaudTickGen (
input clk,
enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log... | 7.463142 |
module BitTime_Counter (
clk,
reset,
DOIT,
K,
BTU
);
input clk, reset;
input DOIT;
input [19:0] K;
output BTU;
reg [19:0] Q;
reg [19:0] mQ;
always @(posedge clk, posedge reset)
if (reset) Q <= 20'b0;
else Q <= mQ;
always @(*) begin
case ({
DOIT, BTU
})
... | 7.069411 |
module bitty_riscv_sopc (
input wire clk,
input wire rst
);
// 连接指令存储器
wire [`InstAddrBus] inst_addr_o;
wire [ `InstBus] inst_rom_o;
wire core_ce_o;
// risc-v ram
wire mem_ce_i;
wire mem_we_i;
wire [`DataAddrBus] mem_addr_i;
wire [ `DataBus]... | 7.969159 |
module bitty_riscv_sopc_tb ();
reg CLOCK_50;
reg rst;
// 每隔 10ns CLOCK_50 信号翻转一次，所以周期是 20ns, 对应 50MHz
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
`ifdef IVERILOG
// 使用文件 inst_rom.data 初始化指令存储器
initial $readmemh("./rtl/sim/inst_rom.data", u_bitty_riscv_sopc.u_inst_rom.in... | 7.969159 |
module ternary;
wire [5:0] a;
wire [6:0] b;
wire c;
wire [5:0] d = c ? a : b;
initial begin
$display("PASSED");
$finish;
end
endmodule
| 6.762795 |
module BitWiseAndGate_8B (
a,
b,
z
);
input [7:0] a, b;
output [7:0] z;
and a1 (z[0], a[0], b[0]);
and a2 (z[1], a[1], b[1]);
and a3 (z[2], a[2], b[2]);
and a4 (z[3], a[3], b[3]);
and a5 (z[4], a[4], b[4]);
and a6 (z[5], a[5], b[5]);
and a7 (z[6], a[6], b[6]);
and a8 (z[7], a[7], b[7]);... | 6.671626 |
module BitWiseAndGate_8B_t ();
reg [7:0] input_a, input_b, output_z;
BitWiseAndGate_8B a (
input_a,
input_b,
output_z
);
task test(input [7:0] A, input [7:0] B);
input_a = A;
input_b = B;
#100;
endtask
initial begin
$dumpfile("BitWiseAndGate_8B.vcd");
$dumpvars;
... | 6.671626 |
module BitwiseAND_5Bit (
a,
select,
b
);
input [5:1] a;
input select;
output [5:1] b;
assign b[1] = select & a[1];
assign b[2] = select & a[2];
assign b[3] = select & a[3];
assign b[4] = select & a[4];
assign b[5] = select & a[5];
endmodule
| 7.682698 |
module BitwiseG (
input Ai,
input Bi,
output Gi
);
and #0.1 (Gi, Ai, Bi);
endmodule
| 6.610634 |
module BitWiseInverter_8B (
a,
enable,
z
);
input [7:0] a;
input enable;
output [7:0] z;
xor x1 (z[0], a[0], enable);
xor x2 (z[1], a[1], enable);
xor x3 (z[2], a[2], enable);
xor x4 (z[3], a[3], enable);
xor x5 (z[4], a[4], enable);
xor x6 (z[5], a[5], enable);
xor x7 (z[6], a[6], enab... | 7.402044 |
module BitWiseInverter_8B_t ();
reg [7:0] input_a, output_z;
reg input_enable;
reg [2:0] i;
BitWiseInverter_8B in (
input_a,
input_enable,
output_z
);
task test(input A, input E);
if (A == 0) begin
input_a = 8'b00000000;
end else begin
input_a = 8'b11111111;
end
... | 7.402044 |
module BitwiseP (
input Ai,
input Bi,
output Pi
);
xor #0.1 (Pi, Ai, Bi);
endmodule
| 7.126071 |
module bitwise_module #(
parameter data_width = 16
) (
input [data_width - 1 : 0] _A,
input [data_width - 1 : 0] _B,
input [3 : 0] func,
output reg [data_width - 1 : 0] _C
);
always @(*) begin
case (func)
`FUNC_ID: begin
_C <= _A;
end
`FUNC_NOT: begin
_C <= ~_... | 7.838613 |
module identity_not_module #(parameter data_width = 16) (
// input [data_width - 1 : 0]_A,
// input func,
// output reg [data_width - 1 : 0] _C
// );
// always @(*) begin
// if(func) // NOT
// _C <= ~_A;
// else // IDENTITY
// _C <= _A;
// end
// endmodule
| 7.772753 |
module and_or_module #(parameter data_width = 16) (
// input [data_width - 1 : 0]_A,
// input [data_width - 1 : 0]_B,
// input func,
// output reg [data_width - 1 : 0] _C
// );
// always @(*) begin
// if(func) // OR
// _C <= _A|_B;
// else // AND
// _C <= _A&_B;
// end
// endmodule
| 7.739475 |
module nand_nor_module #(parameter data_width = 16) (
// input [data_width - 1 : 0]_A,
// input [data_width - 1 : 0]_B,
// input func,
// output reg [data_width - 1 : 0] _C
// );
// always @(*) begin
// if(func) // NOR
// _C <= ~(_A|_B);
// else // NAND
// _C <= ~(_A&_B);
// end
// endmodule
| 7.156314 |
module bitwise_mux(i0,i1,mask,output);
input [7:0] i0;
input [7:0] i1;
input [7:0] mask;
output [7:0] output;
assign output = ;
endmodule
| 7.343592 |
module bitwise_operators ();
initial begin
// Bit Wise Negation
$display(" ~4'b0001 = %b", (~4'b0001));
$display(" ~4'bx001 = %b", (~4'bx001));
$display(" ~4'bz001 = %b", (~4'bz001));
// Bit Wise AND
$display(" 4'b0001 & 4'b1001 = %b", (4'b0001 & 4'b1001));
... | 7.179086 |
module Bitwise_PG #(
parameter WIDTH = 16
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:0] G,
output [WIDTH:0] P
);
assign P[0] = 0;
assign G[0] = Cin;
genvar i;
generate
for (i = 1; i <= WIDTH; i = i + 1) begin : bitwise_pg
xor x (P[i], A[i], B[i]);
... | 6.727227 |
module implements a parameterized bitwise XOR logic.
module Bitwise_XOR(
input [DATA_WIDTH - 1:0] i_dataA,
input [DATA_WIDTH - 1:0] i_dataB,
output [DATA_WIDTH - 1:0] o_result
);
parameter DATA_WIDTH = 48;
assign o_result = i_dataA ^ i_dataB;
endmodule
| 6.904081 |
module bit_4_carry_lookahead (
input [3:0] a,
input [3:0] b,
input c_0,
output [3:0] s,
output c_4
);
wire [3:0] g;
wire [3:0] p;
wire c_1;
wire c_2;
wire c_3;
assign g[0] = a[0] & b[0];
assign g[1] = a[1] & b[1];
assign g[2] = a[2] & b[2];
assign g[3] = a[3] & b[3];
assign p[... | 6.903644 |
module bit_1_full_adder (
input a_i,
input b_i,
input c_i_1,
output s_i,
output c_i
);
wire mid = a_i ^ b_i;
assign s_i = mid ^ c_i_1;
assign c_i = (mid & c_i_1) | (a_i & b_i);
endmodule
| 8.003512 |
module bit_1_full_adder_tb;
reg a_i;
reg b_i;
reg c_i_1;
wire s_i;
wire c_i;
parameter stop_time = 2000;
bit_1_full_adder uut (
.a_i (a_i),
.b_i (b_i),
.c_i_1(c_i_1),
.s_i (s_i),
.c_i (c_i)
);
initial #stop_time $finish;
initial begin
a_i = 0;
b_i =... | 8.003512 |
module bit_23_reg (
in,
clk,
rst,
out
);
input [22:0] in;
input clk;
input rst;
output reg [22:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 23'b0000_0000_0000_0000_0000_000;
else out <= in;
end
endmodule
| 7.321384 |
module bit_23_reg_en (
in,
clk,
rst,
enable,
out
);
input [22:0] in;
input clk;
input rst;
input enable;
output reg [22:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 23'b0000_0000_0000_0000_0000_000;
else if (enable) out <= in;
end
endmodule
| 6.867802 |
module bit_24_reg (
in,
clk,
rst,
out
);
input [23:0] in;
input clk;
input rst;
output reg [23:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 24'b0000_0000_0000_0000_0000_0000;
else out <= in;
end
endmodule
| 7.340818 |
module bit_27_reg (
in,
clk,
rst,
out
);
input [26:0] in;
input clk;
input rst;
output reg [26:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 27'b0000_0000_0000_0000_0000_0000_000;
else out <= in;
end
endmodule
| 6.756418 |
module bit_2_reg (
in,
clk,
rst,
out
);
input [1:0] in;
input clk;
input rst;
output reg [1:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 2'b00;
else out <= in;
end
endmodule
| 6.750428 |
module bit_3_reg (
in,
clk,
rst,
out
);
input [2:0] in;
input clk;
input rst;
output reg [2:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 3'b000;
else out <= in;
end
endmodule
| 7.393562 |
module bit_4_carry_lookahead (
input [3:0] a,
input [3:0] b,
input c_0,
output [3:0] s,
output c_4
);
wire [3:0] g;
wire [3:0] p;
wire c_1;
wire c_2;
wire c_3;
assign g[0] = a[0] & b[0];
assign g[1] = a[1] & b[1];
assign g[2] = a[2] & b[2];
assign g[3] = a[3] & b[3];
assign p[... | 6.903644 |
module bit_4_ripple_carry_tb;
reg [3:0] a;
reg [3:0] b;
reg c_0;
wire [3:0] s;
wire c_4;
parameter stop_time = 2000;
bit_4_ripple_carry uut (
.a (a),
.b (b),
.c_0(c_0),
.s (s),
.c_4(c_4)
);
initial #stop_time $finish;
initial begin
a = 0;
b = 0;
c_0 =... | 6.637454 |
module bit_1_full_adder (
input a_i,
input b_i,
input c_i_1,
output s_i,
output c_i
);
wire mid = a_i ^ b_i;
assign s_i = mid ^ c_i_1;
assign c_i = (mid & c_i_1) | (a_i & b_i);
endmodule
| 8.003512 |
module bit_4_ripple_carry (
input [3:0] a,
input [3:0] b,
input c_0,
output [3:0] s,
output c_4
);
wire c_1, c_2, c_3;
bit_1_full_adder ux1 (
a[0],
b[0],
c_0,
s[0],
c_1
);
bit_1_full_adder ux2 (
a[1],
b[1],
c_1,
s[1],
c_2
);
bit... | 6.637454 |
module bit_4_ripple_carry_tb;
reg [3:0] a;
reg [3:0] b;
reg c_0;
wire [3:0] s;
wire c_4;
parameter stop_time = 2000;
bit_4_ripple_carry uut (
.a (a),
.b (b),
.c_0(c_0),
.s (s),
.c_4(c_4)
);
initial #stop_time $finish;
initial begin
a = 0;
b = 0;
c_0 =... | 6.637454 |
module bit_53_reg (
in,
clk,
rst,
out
);
input [52:0] in;
input clk;
input rst;
output reg [52:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 53'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0;
else out <= in;
end
endmodule
| 6.695577 |
module bit_56_reg (
in,
clk,
rst,
out
);
input [55:0] in;
input clk;
input rst;
output reg [55:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 56'b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000;
else out <= in;
end
endmodule
| 7.400274 |
module bit_5_reg (
in,
clk,
rst,
out
);
input [4:0] in;
input clk;
input rst;
output reg [4:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 5'b00000;
else out <= in;
end
endmodule
| 6.934471 |
module bit_8_reg (
in,
clk,
rst,
out
);
input [7:0] in;
input clk;
input rst;
output reg [7:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 8'b0000_0000;
else out <= in;
end
endmodule
| 7.156376 |
module bit_8_reg_en (
in,
clk,
rst,
enable,
out
);
input [7:0] in;
input clk;
input rst;
input enable;
output reg [7:0] out;
always @(posedge rst or posedge clk) begin
if (rst) out <= 8'b0000_0000;
else if (enable) out <= in;
end
endmodule
| 7.003227 |
module //
// //
// Dependencies: None //
// //
//--------... | 8.238592 |
module bit_adj_32b_to_16b (
Data_in,
Data_out
);
input [31:0] Data_in;
output [15:0] Data_out;
wire [31:0] Data_in;
wire [15:0] Data_out;
wire [15:0] truncate_temp;
wire [15:0] rounding_temp;
assign truncate_temp = Data_in[27:12];
assign rounding_temp = {15'b0, Data_in[11]};
ksa_top_16b k... | 6.660614 |
module bit_align_102 (
input clk,
input rst,
input [9:0] data,
output reg flip,
output reg bitslip,
output reg aligned
);
localparam CLK_FREQ = 27'h47868c0;
localparam TOKEN_CTR_SIZE = 3'h7;
reg blank;
localparam INIT_state = 3'd0;
localparam SEARCH_state = 3'd1;
localparam BITSL... | 7.077305 |
module BIT_AND (
Reg1,
Reg2,
Out
);
input [15:0] Reg1, Reg2;
output [15:0] Out;
assign Out = Reg1 & Reg2;
endmodule
| 7.143688 |
module bit_com (
info_bits,
esti_bits,
ham_dis
);
input [11:0] info_bits, esti_bits;
output [3:0] ham_dis;
reg [3:0] count;
always @(*) begin
count = 0;
if (info_bits[0] != esti_bits[0]) begin
count = count + 1;
end
if (info_bits[1] != esti_bits[1]) begin
count = count ... | 7.001136 |
module bit_counter (
sys_clk,
reset,
counter_reset,
counter_en,
scan_code_ready
);
input sys_clk, reset;
input counter_reset, counter_en;
output scan_code_ready;
wire scan_code_ready;
reg [3:0] bit_count = 0;
assign scan_code_ready = (bit_count == 11);
always @(posedge sys_clk) begin... | 6.711719 |
module bit_endian_converter (
ENABLE,
DATA_IN,
DATA_OUT
);
parameter DATA_WIDTH = 32; //8, 16, 32, 64
input ENABLE;
input [DATA_WIDTH-1:0] DATA_IN;
output [DATA_WIDTH-1:0] DATA_OUT;
genvar i;
generate
if (DATA_WIDTH == 8) begin
for (i = 0; i < 8; i = i + 1) begin : bit_endian_conv_... | 8.118498 |
module Bit_Extender_12_32_SIGN (
imm_in,
imm_out
);
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input [11:0] imm_... | 8.92285 |
module Bit_Extender_20_32 (
imm_in,
imm_out
);
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input [19:0] imm_in;
... | 8.92285 |
module Bit_Extender_20_32_SIGN (
imm_in,
imm_out
);
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input [19:0] imm_... | 8.92285 |
module bit_flipper (
input clock,
input reset_n,
input unsigned [1:0] addr,
input rd_en,
input wr_en,
output reg unsigned [31:0] dataOut,
input unsigned [31:0] dataIn
);
reg unsigned [31:0] saved_value; // temp reg for result
integer i;
// writing
always @(posedge clock) begin
... | 7.002793 |
module Bit_Getter (
input clk_100MHz,
input micData,
output reg pwm_val
);
parameter kHZ_Cnt = 5120; // 16*320
parameter Begin_kHZ_Cnt = 0;
parameter least_value = 2720; // 16*170
reg [12:0] begin_Cnt = 0;
reg [12:0] micInUse_Cnt = 0;
reg [12:0] micInUse = 0;
always @(posedge (clk_100MHz)... | 6.889346 |
module sign_extend (
sOut32,
sIn16
);
output [31:0] sOut32;
input [15:0] sIn16;
assign sOut32 = {{16{sIn16[15]}}, sIn16};
endmodule
| 7.581479 |
module
module shift_left_2(Out32, In32);
output [31:0] Out32;
input [31:0] In32;
assign Out32 = {In32[29:0],2'b00};
endmodule
| 7.458004 |
module zero_extend (
zOut32,
zIn16
);
output [31:0] zOut32;
input [15:0] zIn16;
assign zOut32 = {{16{1'b0}}, zIn16};
endmodule
| 7.606311 |
module BIT_OR (
Reg1,
Reg2,
Out
);
input [15:0] Reg1, Reg2;
output [15:0] Out;
assign Out = Reg1 | Reg2;
endmodule
| 6.685946 |
module BIT_P (
output BP,
input A,
B
);
xor (BP, A, B);
endmodule
| 7.449601 |
module bit_queue #(
parameter integer bit_width = 64
) (
input wire rst,
clk,
input wire chk_in,
input wire [bit_width-1:0] bit_in,
input wire [bit_width-1:0] clr_in,
output reg [bit_width-1:0] bit_out
);
generate
genvar i;
for (i = 0; i < bit_width; i = i + 1) b... | 6.868873 |
module bit_register (
clk,
input_enable,
output_enable,
data,
out
);
input clk, input_enable, output_enable, data;
output out;
wire not_out;
wire buf_out;
wire mem_data;
assign mem_data = (buf_out && ~input_enable) || (input_enable && data);
d_flip_flop flip_memory (
clk,
... | 6.556423 |
module buffer (
data,
enable,
out
);
input data, enable;
output reg out;
always @* begin
if (enable == 1) begin
out <= data;
end else begin
out <= 1'bZ;
end
end
endmodule
| 6.861394 |
module bit_register_tb;
reg input_enable, output_enable, data;
wire out, clk;
test_clock clock (clk);
bit_register uut (
clk,
input_enable,
output_enable,
data,
out
);
initial begin
$dumpfile("bit_register_tb.vcd");
$dumpvars(0, bit_register_tb);
input_enable <... | 6.519573 |
module //
// Date: June 2012 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic ... | 8.238592 |
module bit_reversal
#(
parameter DATA_SIZE = 32
)
(
//OUTPUTS
output [DATA_SIZE - 1 : 0] data_out,
//INPUTS
input [DATA_SIZE - 1 : 0] data_in,
input [1 : 0] rev_type
);
//Bit reversing types
localparam NO_REVERSE = 2'b00;
localparam BYTE = 2'b01;
localparam HALF_WORD = 2'b10;
localparam WORD = 2... | 6.714069 |
module bit_reverser #(
parameter WIDTH = 4
) (
input [WIDTH-1:0] in,
output [WIDTH-1:0] out
);
genvar i;
for (i = 0; i < WIDTH; i = i + 1) begin
assign out[i] = in[WIDTH-1-i];
end
endmodule
| 6.690113 |
module bit_searcher_2 (
input wire [1:0] bits,
input wire target,
input wire direction,
output wire hit,
output reg index
);
assign hit = (bits[1:0] != {2{~target}});
always @(*) begin
if (direction) begin
if (bits[1] == ~target) index = 1'b0;
else index = 1'b1;
end else beg... | 8.72533 |
module bit_searcher_4 (
input wire [3:0] bits,
input wire target,
input wire direction,
output wire hit,
output reg [1:0] index
);
assign hit = (bits[3:0] != {4{~target}});
always @(*) begin
if (direction) begin
if (bits[3:1] == {3{~target}}) index = 2'b00;
else if (bits[3:2] ==... | 8.72533 |
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