code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fa (
input a,
b,
c,
output s,
cout
);
wire w1, w2, w3;
xor (s, a, b, c);
and (w1, a, b);
xor (w2, a, b);
and (w3, w2, c);
or (cout, w3, w1);
endmodule
| 7.001699 |
module bit4 (
input [3:0] inp1,
input [3:0] inp2,
output [7:0] outp
);
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15;
wire d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18;
and a1 (outp[0], inp1[0], inp2[0]);
and a2 (w15, inp1[1], inp2[0]);
and (w14, inp1[2], inp2[0]);
and (w13, inp1[3], inp2[0]);
and (w12, inp1[0], inp2[1]);
and (w11, inp1[1], inp2[1]);
and (w10, inp1[2], inp2[1]);
and (w9, inp1[3], inp2[1]);
and (w8, inp1[0], inp2[2]);
and (w7, inp1[1], inp2[2]);
and (w6, inp1[2], inp2[2]);
and (w5, inp1[3], inp2[2]);
and (w4, inp1[0], inp2[3]);
and (w3, inp1[1], inp2[3]);
and (w2, inp1[2], inp2[3]);
and (w1, inp1[3], inp2[3]);
fa fa1 (
w15,
w12,
0,
outp[1],
d1
);
fa fa2 (
w14,
w11,
d1,
d2,
d3
);
fa fa3 (
d2,
w8,
0,
outp[2],
d4
);
fa fa4 (
d3,
d4,
0,
d5,
d6
);
fa fa5 (
d5,
w13,
w10,
d7,
d8
);
fa fa6 (
d7,
w7,
w4,
outp[3],
d9
);
fa fa7 (
d6,
d8,
d9,
d10,
d11
);
fa fa8 (
w9,
w6,
w3,
d12,
d13
);
fa fa9 (
d10,
d12,
0,
outp[4],
d15
);
fa fa10 (
d15,
d13,
d11,
d16,
d17
);
fa fa11 (
d16,
w5,
w2,
outp[5],
d18
);
fa fa12 (
d17,
d18,
w1,
outp[6],
outp[7]
);
endmodule
| 6.541464 |
module fabit8 (
input [7:0] inp1,
input [7:0] inp2,
input cin,
output [7:0] outp,
output cout
);
wire w1;
fabit4 fa1 (
inp1[3:0],
inp2[3:0],
cin,
outp[3:0],
w1
);
fabit4 fa2 (
inp1[7:4],
inp2[7:4],
w1,
outp[7:4],
cout
);
endmodule
| 7.503689 |
module bit8 (
input [ 7:0] inp1,
input [ 7:0] inp2,
output [15:0] outp
);
wire [7:0] w1;
wire [7:0] w2;
wire [7:0] w3;
wire [7:0] w4;
wire [7:0] w5;
wire [7:0] w6;
wire [7:0] w7;
wire w8, w9, w10, w11, w12;
bit4 mul1 (
inp1[3:0],
inp2[3:0],
w1
);
bit4 mul2 (
inp1[3:0],
inp2[7:4],
w2
);
bit4 mul3 (
inp1[7:4],
inp2[3:0],
w3
);
bit4 mul4 (
inp1[7:4],
inp2[7:4],
w4
);
assign outp[3:0] = w1[3:0];
fabit8 fa1 (
w3[7:0],
w2[7:0],
0,
w5[7:0],
w8
);
fabit8 fa2 (
w5[7:0],
{w4[3:0], w1[7:4]},
0,
outp[11:4],
w9
);
fa fa3 (
w8,
w9,
0,
w10,
w11
);
wire [3:0] w13 = {2'b0, w11, w10};
fabit4 fa4 (
w4[7:4],
w13,
0,
outp[15:12],
w12
);
endmodule
| 7.211629 |
module mux8 (
s,
a,
b,
c,
d,
e,
f,
g,
h,
out
);
input [2:0] s;
input a, b, c, d, e, f, g, h;
output out;
bufif1 b1 (out, a, ((~s[0]) & (~s[1]) & (~s[2])));
bufif1 b2 (out, b, ((s[0]) & (~s[1]) & (~s[2])));
bufif1 b3 (out, c, ((~s[0]) & (s[1]) & (~s[2])));
bufif1 b4 (out, d, ((s[0]) & (s[1]) & (~s[2])));
bufif1 b5 (out, e, ((~s[0]) & (~s[1]) & (s[2])));
bufif1 b6 (out, f, ((s[0]) & (~s[1]) & (s[2])));
bufif1 b7 (out, g, ((~s[0]) & (s[1]) & (s[2])));
bufif1 b8 (out, h, ((s[0]) & (s[1]) & (s[2])));
endmodule
| 6.942993 |
module bit8alu (
input [7:0] a,
input [7:0] b,
input [2:0] s,
output [7:0] acc,
output [7:0] mulh,
output [7:0] flag
);
wire [7:0] ands;
wire [7:0] orrs;
wire [7:0] nots;
wire [7:0] lsl;
wire [7:0] lsr;
wire [7:0] add;
wire [7:0] sub;
wire [7:0] mul;
wire [7:0] mulhw;
wire wadd, asub;
wire [7:0] temp;
and u11 (ands[0], a[0], b[0]);
and u12 (ands[1], a[1], b[1]);
and u13 (ands[2], a[2], b[2]);
and u14 (ands[3], a[3], b[3]);
and u15 (ands[4], a[4], b[4]);
and u16 (ands[5], a[5], b[5]);
and u17 (ands[6], a[6], b[6]);
and u18 (ands[7], a[7], b[7]);
or u21 (orrs[0], a[0], b[0]);
or u22 (orrs[1], a[1], b[1]);
or u23 (orrs[2], a[2], b[2]);
or u24 (orrs[3], a[3], b[3]);
or u25 (orrs[4], a[4], b[4]);
or u26 (orrs[5], a[5], b[5]);
or u27 (orrs[6], a[6], b[6]);
or u28 (orrs[7], a[7], b[7]);
not u31 (nots[0], a[0]);
not u32 (nots[1], a[1]);
not u33 (nots[2], a[2]);
not u34 (nots[3], a[3]);
not u35 (nots[4], a[4]);
not u36 (nots[5], a[5]);
not u37 (nots[6], a[6]);
not u38 (nots[7], a[7]);
assign lsl = {a[7:1], 1'b0};
assign lsr = {1'b0, a[6:0]};
fabit8 u4 (
a,
b,
0,
add,
wadd
);
not u51 (temp[0], b[0]);
not u52 (temp[1], b[1]);
not u53 (temp[2], b[2]);
not u54 (temp[3], b[3]);
not u55 (temp[4], b[4]);
not u56 (temp[5], b[5]);
not u57 (temp[6], b[6]);
not u58 (temp[7], b[7]);
fabit8 u6 (
a,
temp,
1,
sub,
wsub
);
bit8 u7 (
a,
b,
{mulh, mul}
);
mux8 u81 (
s,
ands[0],
orrs[0],
nots[0],
lsl[0],
lsr[0],
add[0],
sub[0],
mul[0],
acc[0]
);
mux8 u82 (
s,
ands[1],
orrs[1],
nots[1],
lsl[1],
lsr[1],
add[1],
sub[1],
mul[1],
acc[1]
);
mux8 u83 (
s,
ands[2],
orrs[2],
nots[2],
lsl[2],
lsr[2],
add[2],
sub[2],
mul[2],
acc[2]
);
mux8 u84 (
s,
ands[3],
orrs[3],
nots[3],
lsl[3],
lsr[3],
add[3],
sub[3],
mul[3],
acc[3]
);
mux8 u85 (
s,
ands[4],
orrs[4],
nots[4],
lsl[4],
lsr[4],
add[4],
sub[4],
mul[4],
acc[4]
);
mux8 u86 (
s,
ands[5],
orrs[5],
nots[5],
lsl[5],
lsr[5],
add[5],
sub[5],
mul[5],
acc[5]
);
mux8 u87 (
s,
ands[6],
orrs[6],
nots[6],
lsl[6],
lsr[6],
add[6],
sub[6],
mul[6],
acc[6]
);
mux8 u88 (
s,
ands[7],
orrs[7],
nots[7],
lsl[7],
lsr[7],
add[7],
sub[7],
mul[7],
acc[7]
);
bufif1 b6 (flag[4], wadd, ((s[0]) & (~s[1]) & (s[2])));
bufif1 b7 (flag[5], wsub, ((s[0]) & (~s[1]) & (s[2])));
assign flag[0] = ~|a;
assign flag[1] = ~^a;
assign flag[2] = a[7];
assign flag[3] = a[0];
assign flag[6] = ~|acc;
assign flag[7] = ~acc;
endmodule
| 6.618196 |
module bit8to128 (
input wire sclk,
input wire rst,
input wire rx_flag,
input wire [ 7:0] rx_data,
output wire wr_en,
output wire [127:0] wr_data
);
parameter BURST_LEN = 64;
reg [15:0] shift_reg;
reg rx_cnt = 0;
reg wr_fifo_en;
wire [15:0] wr_fifo_data;
wire [7:0] rd_data_count;
reg rd_en;
reg [7:0] rd_cnt;
assign wr_fifo_data = shift_reg;
always @(posedge sclk) begin
if (rx_flag == 1'b1) begin
shift_reg <= {shift_reg[7:0], rx_data};
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
rx_cnt <= 1'b0;
end else if (rx_flag == 1'b1) begin
rx_cnt <= rx_cnt + 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
wr_fifo_en <= 1'b0;
end else if (rx_cnt == 1'b1 && rx_flag == 1'b1) begin
wr_fifo_en <= 1'b1;
end else begin
wr_fifo_en <= 1'b0;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
rd_en <= 1'b0;
end else if (rd_cnt == BURST_LEN - 1) begin
rd_en <= 1'b0;
end else if (rd_data_count >= BURST_LEN) begin
rd_en <= 1'b1;
end
end
always @(posedge sclk) begin
if (rst == 1'b1) begin
rd_cnt <= 'd0;
end else if (rd_cnt == BURST_LEN - 1 && rd_en == 1'b1) begin
rd_cnt <= 'd0;
end else if (rd_en == 1'b1) begin
rd_cnt <= rd_cnt + 1'b1;
end
end
assign wr_en = rd_en;
fifo_wr16x1024_rd128x128 uart_buffer_inst (
.clk (sclk), // input wire clk
.din (wr_fifo_data), // input wire [15 : 0] din
.wr_en (wr_fifo_en), // input wire wr_en
.rd_en (rd_en), // input wire rd_en
.dout (wr_data), // output wire [127 : 0] dout
.full (), // output wire full
.empty (), // output wire empty
.rd_data_count(rd_data_count) // output wire [7 : 0] rd_data_count
);
endmodule
| 8.060585 |
module bit8_2to1mux (
out,
sel,
in1,
in2
);
input [7:0] in1, in2;
output [7:0] out;
input sel;
genvar j;
generate
for (j = 0; j < 8; j = j + 1) begin : mux_loop
mux2to1 m1 (
out[j],
sel,
in1[j],
in2[j]
);
end
endgenerate
endmodule
| 6.846916 |
module bit8_3to1mux (
out,
sel1,
sel2,
in1,
in2,
in3
);
input [7:0] in1, in2, in3;
output [7:0] out;
input sel1, sel2;
genvar j;
//this is the variable that is be used in the generate
generate
for (j = 0; j < 8; j = j + 1) begin : mux_loop //mux_loop is the name of the loop
mux3to1 m1 (
out[j],
sel1,
sel2,
in1[j],
in2[j],
in3[j]
);
//mux3to1 is instantiated every time it is called
end
endgenerate
endmodule
| 6.929733 |
module bitadd (
A,
B,
CI,
Y,
C
); // add all inputs and outputs inside parentheses
// inputs
input A;
input B;
input CI;
// outputs
output reg Y;
output reg C;
// reg and internal variable definitions
// implement module here
always @(*) begin
if (A & B) begin
C <= 1'b1;
if (CI) Y <= 1'b1;
else Y <= 1'b0;
end else if (A | B) begin
if (CI) begin
Y <= 1'b0;
C <= 1'b1;
end else begin
Y <= 1'b1;
C <= 1'b0;
end
end else begin
C <= 1'b0;
if (CI) Y <= 1'b1;
else Y <= 1'b0;
end
end
endmodule
| 7.177831 |
module BITADD8 (
input [7:0] d,
output [3:0] q
);
assign q = d[0] + d[1] + d[2] + d[3] + d[4] + d[5] + d[6] + d[7];
endmodule
| 6.717507 |
module FullAdder (
input wire a,
input wire b,
input wire cin,
output wire s,
output wire cout
);
wire sha, cha1, cha2;
HalfAdder ha1 (
cin,
a,
sha,
cha1
);
HalfAdder ha2 (
sha,
b,
s,
cha2
);
assign cout = cha1 | cha2;
endmodule
| 7.610141 |
module BitAdder #(
parameter BUS_WIDTH = 8
) (
input wire [BUS_WIDTH-1:0] a,
input wire [BUS_WIDTH-1:0] b,
input wire substract,
output wire [BUS_WIDTH-1:0] out,
output wire carry
);
wire [BUS_WIDTH:0] c;
assign c[0] = substract;
assign carry = c[BUS_WIDTH];
generate
genvar i;
for (i = 0; i < BUS_WIDTH; i = i + 1) begin : RippleAdder
FullAdder add (
a[i],
b[i],
c[i],
out[i],
c[i+1]
);
end
endgenerate
endmodule
| 9.440111 |
module bitap (
// Control registers stuff
input control_regs_clock,
input control_regs_we,
input [0:0] control_regs_addr,
input [31:0] control_regs_data_in,
output reg [31:0] control_regs_data_out,
// Memory for haystack
output haystack_mem_clock,
output [15:0] haystack_mem_addr,
input [7:0] haystack_mem_data,
// Memory for needle
output needle_mem_clock,
output [7:0] needle_mem_addr,
input [31:0] needle_mem_data,
// Clock and reset
input clock,
input reset
);
reg run_enable;
reg [4:0] needle_shift;
reg [31:0] match_amount;
reg [31:0] state;
reg [31:0] needle_data;
reg [31:0] control_reg0;
reg wflag0, wflag1;
integer counter;
wire [31:0] state_limit = 32'hFFFF_FFFF << needle_shift;
wire [31:0] new_state = (state << 1) | needle_mem_data;
assign needle_mem_clock = clock;
assign needle_mem_addr = haystack_mem_data;
assign haystack_mem_clock = clock;
assign haystack_mem_addr = counter;
always @* begin
case (control_regs_addr)
1'b0: control_regs_data_out <= {needle_shift, run_enable};
1'b1: control_regs_data_out <= match_amount;
endcase
end
always @(posedge control_regs_clock) begin
if (reset) begin
wflag0 <= 1'b0;
control_reg0 <= 1'b0;
end else begin
if (control_regs_we) begin
case (control_regs_addr)
1'b0: control_reg0 <= control_regs_data_in;
endcase
if (wflag1 != wflag0) wflag0 <= ~wflag0;
end
end
end
always @(posedge reset or posedge clock) begin
if (reset) begin
wflag1 <= 1'b0;
run_enable <= 1'b0;
match_amount <= 1'b0;
end else begin
if (wflag1 == wflag0) begin
wflag1 <= ~wflag1;
{needle_shift, run_enable} <= control_reg0;
if (control_reg0[0]) // If run_enable will be set
begin
counter <= 1'b0;
match_amount <= 1'b0;
state <= 32'hFFFF_FFFF;
end
end
if (run_enable) begin
if (counter >= 2) begin
state <= new_state;
if (new_state >= state_limit) match_amount <= match_amount;
else match_amount <= match_amount + 1'b1;
end
// if we get null-terminator then stop
if (counter >= 1 && !haystack_mem_data) run_enable <= 1'b0;
counter <= counter + 1'b1;
end
end
end
endmodule
| 6.758748 |
module BitArrayGetterModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire [7:0] Value,
output wire [7:0] Getter
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire [7:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L17F46T59_Expr = 8'b11111111;
wire [5:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F36T38_Expr = 6'b110010;
wire [6:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F41T44_Expr = 7'b1100100;
wire [7:0] Inputs_Value;
wire [7:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L17F30T60_Source;
reg [7:0] BitArrayGetterModule_L16F13L25T14_result;
reg [7:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L20F30T38_Cast = 8'b00101010;
wire [7:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L22F30T59_Source;
wire [7:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L22F30T70_Resize;
wire BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_Expr;
wire signed [8:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_ExprLhs;
wire signed [8:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_ExprRhs;
wire BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_Expr;
wire signed [8:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_ExprLhs;
wire signed [8:0] BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_ExprRhs;
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_Expr = BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_ExprLhs < BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_ExprRhs ? 1'b1 : 1'b0;
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_Expr = BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_ExprLhs < BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_ExprRhs ? 1'b1 : 1'b0;
always @* begin
BitArrayGetterModule_L16F13L25T14_result = BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L17F30T60_Source;
if (BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_Expr == 1) begin
BitArrayGetterModule_L16F13L25T14_result = BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L20F30T38_Cast;
end else if (BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_Expr == 1) begin
BitArrayGetterModule_L16F13L25T14_result = BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L22F30T70_Resize;
end
end
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_ExprLhs = {
{1{1'b0}}, Inputs_Value
} /*expand*/;
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F21T38_ExprRhs = {
{3{1'b0}}, BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L19F36T38_Expr
} /*expand*/;
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_ExprLhs = {
{1{1'b0}}, Inputs_Value
} /*expand*/;
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F26T44_ExprRhs = {
{2{1'b0}}, BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L21F41T44_Expr
} /*expand*/;
assign Inputs_Value = Value;
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L17F30T60_Source = BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L17F46T59_Expr;
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L22F30T59_Source = Inputs_Value;
assign BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L22F30T70_Resize = BitArrayGetterModule_L16F13L25T14_BitArrayGetterModule_L22F30T59_Source;
assign Getter = BitArrayGetterModule_L16F13L25T14_result;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 6.935302 |
module bitbang (
s_clk,
s_data,
strobe,
data,
active,
clk
);
localparam on_pattern = 16'hFAB1;
localparam off_pattern = 16'hFAB0;
input s_clk;
input s_data;
output reg strobe;
output reg [31:0] data;
output reg active = 1'b0;
input clk;
reg [3:0] s_data_sample;
reg [3:0] s_clk_sample;
reg [31:0] serial_data;
reg [15:0] serial_control;
reg local_strobe;
reg old_local_strobe;
always @(posedge clk) begin : p_input_sync
s_data_sample <= {s_data_sample[3-1:0], s_data};
s_clk_sample <= {s_clk_sample[3-1:0], s_clk};
end
always @(posedge clk) begin : p_in_shift
// on s_clk_sample rising edge, we sample in a serial_data bit
if ((s_clk_sample[3] == 1'b0) && (s_clk_sample[3-1] == 1'b1)) begin
serial_data <= {serial_data[31-1:0], s_data_sample[3]};
end
// on s_clk_sample faling edge, we sample in a serial_data bit
if ((s_clk_sample[3] == 1'b1) && (s_clk_sample[3-1] == 1'b0)) begin
serial_control <= {
serial_control[15-1:0], s_data_sample[3]
}; // its data again, but its sampled on the other edge
end
end
// we could replicate the following
always @(posedge clk) begin : p_parallel_load
local_strobe <= 1'b0; // will be overwritten if next conditional is true
if (serial_control == on_pattern) begin // x"FAB1" then
data <= serial_data;
local_strobe <= 1'b1;
end //else begin
// data <= data;
// local_strobe <= 1'b0;
// end
old_local_strobe <= local_strobe;
strobe <= local_strobe & ~old_local_strobe; // activates strobe for one clock cycle after "FAB0" was detected
end
// we could replicate the following
always @(posedge clk) begin : active_FSM
if (serial_control == on_pattern) begin // x"FAB1" then
active <= 1'b1;
end
if (serial_control == off_pattern) begin // x"FAB0" then
active <= 1'b0;
end
end
// the following is just copy and past, in case we want use the bitbang interface to shift in other data (let's say to drive CPU port)
// we can also read back the data by loading the parallel shift and shifting the content to an output pin
//p_parallel_load2: process(clk)
//begin
// if clk'event and clk=1'b1 then
// local_strobe <= 1'b0; // will be overwritten if next conditional is true
// if serial_control = x"FAB1" then
// data2 <= serial_data;
// local_strobe2 <= 1'b1;
// old_local_strobe2 <= local_strobe;
// end if;
// strobe2 <= local_strobe2 and (not old_local_strobe2) // activates strobe for one clock cycle after "FAB0" was detected
// end if;
//end process;
endmodule
| 8.223262 |
module io_pad (
input wire in_dir,
input wire in_outval,
inout wire pin
);
assign pin = in_dir ? in_outval : 'bz;
endmodule
| 8.822936 |
module bitbang_ctrl #(
parameter IO_NUM_OF = 10
) ( // i.f. to the controller interface
input wire [IO_NUM_OF - 1 : 0] in_io_direction,
input wire [IO_NUM_OF - 1 : 0] in_io_outval,
// i.f. to the IO pad
inout wire [IO_NUM_OF - 1 : 0] io_pins
);
io_pad io_pads_set[IO_NUM_OF - 1 : 0] (
in_io_direction,
in_io_outval,
io_pins
);
endmodule
| 8.513454 |
module bitblock_1 (
clk,
rstn,
in,
ppi,
cci,
yi,
yo,
ppo,
psum,
ci,
co,
out
);
input clk;
input rstn;
input [4:0] in;
input ppi;
input cci;
input [3:0] yi;
output [3:0] yo;
output ppo;
input psum;
input ci;
output co;
output out;
wire [1:0] cprs_7_2_out;
cprs_7_2 I0 (
.in ({in, ppi, cci}),
.out(cprs_7_2_out[1:0]),
.yi (yi),
.yo (yo)
);
reg pp, ppo;
always @(posedge clk) begin
if (rstn == 1'b0) begin
ppo <= 1'b0;
pp <= 1'b0;
end else begin
ppo <= cprs_7_2_out[1];
pp <= cprs_7_2_out[0];
end
end
wire sum;
assign {co, sum} = pp + psum + ci;
reg out;
always @(posedge clk) begin
if (rstn == 1'b0) begin
out <= 1'b0;
end else begin
out <= sum;
end
end
endmodule
| 6.893755 |
module bitblock_4_core (
clk,
rstn,
in,
shift,
shift_r1,
ppi,
ci,
yi,
yo,
ppo,
psum,
out,
co
);
input clk;
input rstn;
input [19:0] in;
input shift;
input shift_r1;
input ppi;
input ci;
input [3:0] yi;
output [3:0] yo;
output [3:0] ppo;
input [3:0] psum;
output [3:0] out;
output co;
// ctrl logic
//reg shift_r1;
//always @ (posedge clk or negedge rstn) begin
// if (rstn == 0) begin
// shift_r1 <= 1'b0;
// end else begin
// shift_r1 <= shift;
// end
//end
// ppi selection
wire [3:0] ppi_in;
wire pp0, pp1, pp2, pp3;
assign ppi_in = (shift == 1) ? {pp3, pp2, pp1, pp0} : {pp2, pp1, pp0, ppi};
// cci selection
wire [3:0] cci_in;
wire shift_xor, shift_and, shift_nor;
assign shift_xor = shift ^ shift_r1;
assign shift_and = shift & shift_r1;
assign shift_nor = ~(shift | shift_r1);
assign cci_in[3] = (shift_xor == 1'b1) ? co : 0;
assign cci_in[2] = (shift_and == 1'b1) ? co : 0;
assign cci_in[1] = 0;
assign cci_in[0] = (shift_nor == 1'b1) ? ci : 0;
// bitblock_1 connection
wire [3:0] yo_I0, yo_I1, yo_I2, yo_I3;
wire co_I0, co_I1, co_I2, co_I3;
bitblock_1 I0 (
.clk (clk),
.rstn(rstn),
.in (in[4:0]),
.ppi (ppi_in[0]),
.cci (cci_in[0]),
.yi (yi),
.yo (yo_I0),
.ppo (pp0),
.psum(psum[0]),
.ci (1'b0),
.co (co_I0),
.out (out[0])
);
bitblock_1 I1 (
.clk (clk),
.rstn(rstn),
.in (in[9:5]),
.ppi (ppi_in[1]),
.cci (cci_in[1]),
.yi (yo_I0),
.yo (yo_I1),
.ppo (pp1),
.psum(psum[1]),
.ci (co_I0),
.co (co_I1),
.out (out[1])
);
bitblock_1 I2 (
.clk (clk),
.rstn(rstn),
.in (in[14:10]),
.ppi (ppi_in[2]),
.cci (cci_in[2]),
.yi (yo_I1),
.yo (yo_I2),
.ppo (pp2),
.psum(psum[2]),
.ci (co_I1),
.co (co_I2),
.out (out[2])
);
bitblock_1 I3 (
.clk (clk),
.rstn(rstn),
.in (in[19:15]),
.ppi (ppi_in[3]),
.cci (cci_in[3]),
.yi (yo_I2),
.yo (yo_I3),
.ppo (pp3),
.psum(psum[3]),
.ci (co_I2),
.co (co_I3),
.out (out[3])
);
// oupput logic
assign ppo = pp3;
assign yo = yo_I3;
reg co;
always @(posedge clk or negedge rstn) begin
if (rstn == 0) begin
co <= 1'b0;
end else begin
co <= co_I3;
end
end
endmodule
| 8.495237 |
module bitbrick (
input [1:0] x,
input s_x,
input [1:0] y,
input s_y,
input [2:0] shift,
output [9:0] prod
);
/* ORIGINAL VERSION */
/*wire [2:0] x1, y1;
wire ha0_co;
wire fa0_sum, fa0_co;
wire ha1_co;
wire fa1_sum, fa1_co;
wire ha2_co;
wire [5:0] p;
wire fa2_sum, fa2_co;
assign x1[1:0] = x[1:0];
assign y1[1:0] = y[1:0];
assign x1[2] = s_x & x[1];
assign y1[2] = s_y & y[1];
assign p[0] = x1[0] & y1[0];
half_adder ha0(
.in1(x1[1] & y1[0]),
.in2(x1[0] & y1[1]),
.sum(p[1]),
.carry_out(ha0_co)
);
full_adder fa0(
.in1(~(x1[0] & y1[2])),
.in2(x1[1] & y1[1]),
.carry_in(ha0_co),
.sum(fa0_sum),
.carry_out(fa0_co)
);
half_adder ha1(
.in1(fa0_sum),
.in2(~(x1[2] & y1[0])),
.sum(p[2]),
.carry_out(ha1_co)
);
full_adder fa1(
.in1(~(x1[1] & y1[2])),
.in2(~(x1[2] & y1[1])),
.carry_in(fa0_co),
.sum(fa1_sum),
.carry_out(fa1_co)
);
full_adder ha2(
.in1(fa1_sum),
.in2(ha1_co),
.carry_in(1'b1),
.sum(p[3]),
.carry_out(ha2_co)
);
// half_adder ha2(
// .in1(fa1_sum),
// .in2(ha1_co),
// .sum(p[3]),
// .carry_out(ha2_co)
// );
full_adder fa2(
.in1(fa1_co),
.in2(x1[2] & y1[2]),
.carry_in(ha2_co),
.sum(p[4]),
.carry_out(fa2_co)
);
half_adder ha3(
.in1(fa2_co),
.in2(1'b1),
.sum(p[5])
);
assign prod = (($signed(p) << 4) >>> 4) << shift; */
/* CARRY CHAIN VERSION */
wire [2:0] x1, y1;
wire [5:0] p0, p1, p2;
wire [5:0] p3 = 6'b101000;
wire [5:0] p;
assign x1[1:0] = x[1:0];
assign y1[1:0] = y[1:0];
assign x1[2] = s_x & x[1];
assign y1[2] = s_y & y[1];
assign p0 = {~(y1[0] & x1[2]), y1[0] & x1[1], y1[0] & x1[0]};
assign p1 = {~(y1[1] & x1[2]), y1[1] & x1[1], y1[1] & x1[0]} << 1;
assign p2 = {y1[2] & x1[2], ~(y1[2] & x1[1]), ~(y1[2] & x1[0])} << 2;
assign p = p0 + p1 + p2 + p3;
assign prod = (($signed(p) << 4) >>> 4) << shift;
endmodule
| 6.524565 |
module bitbrick_testbench ();
reg [2:0] x;
reg [2:0] y;
wire [9:0] p;
integer i;
integer j;
integer a;
bitbrick bitbrick0 (
.x(x[1:0]),
.s_x(x[2]),
.y(y[1:0]),
.s_y(y[2]),
.shift(0),
.prod(p)
);
initial begin
//$vcdpluson;
`ifdef IVERILOG
$dumpfile("bitbrick_testbench.fst");
$dumpvars(0, bitbrick_testbench);
`endif
for (i = 0; i <= 3; i = i + 1) begin
for (j = 0; j <= 3; j = j + 1) begin
x = i;
y = j;
#10;
if ((i * j) != p)
$display("Multiplicands: %d, %d, Correct: %d, Output: %d", i, j, (i * j), p);
end
end
for (i = -2; i <= 1; i = i + 1) begin
for (j = -2; j <= 1; j = j + 1) begin
x = i;
y = j;
a = i * j;
#10;
if (a[5:0] != p[5:0])
$display("Multiplicands: %d, %d, Correct: %b, Output: %b", i, j, a[5:0], p[5:0]);
end
end
i = 3'b111;
j = 3'b110;
x = i;
y = j;
#10 $display("Multiplicands: -2, -2, Correct: 4, Output: %b", p << 2);
i = 3'b001;
j = 3'b110;
x = i;
y = j;
#10 $display("Multiplicands: -1, -1, Correct: 1, Output: %b", p);
$display("%b", (($signed(p) << 8) >>> 8));
i = 3'b111;
j = 3'b110;
x = i;
y = j;
#10 $display("Multiplicands: 1, -1, Correct: -1, Output: %b", p << 4);
i = 3'b001;
j = 3'b110;
x = i;
y = j;
#10 $display("Multiplicands: -2, -1, Correct: 2, Output: %b", p << 2);
// for (i = 0; i < 3; i = i + 1) begin
// for (j = 0; j < 3; j = j + 1) begin
// x[2] = 1;
// y[2] = 1;
// x[1:0] = i;
// y[1:0] = j;
// #10;
// $display("Multiplicands: %d, %d, Correct: %d, Output: %b", i, j, (i*j), p);
// end
// end
$finish();
//$vcdplusoff;
end
endmodule
| 6.663228 |
module BitClock (
input clk,
output pair2,
output pair1,
output pair0,
output pairCLK,
output LED_indicator
);
fast_clock u1 (
.inclk0(clk),
.c0(bit_clock_out)
);
reg [23:0] cnt;
reg out_clock;
reg [3:0] slot = 6;
reg dataEnable = 1'b0;
reg vsync = 1'b0;
reg hsync = 1'b0;
reg [5:0] red = 6'b000000;
reg [5:0] green = 6'b111111;
reg [5:0] blue = 6'b000000;
reg [6:0] RX0data = 7'b0000000;
reg [6:0] RX1data = 7'b0000000;
reg [6:0] RX2data = 7'b0000000;
reg [6:0] CLKdata = 7'b1100011;
reg [15:0] hCurrent = 0;
reg [15:0] hBack = 59;
reg [15:0] hFront = 1023;
reg [15:0] hSyncPulse = 1152; //1200; //1380; //1216;
reg [15:0] hTotal = 1172; //1220; //1400; //1236;
reg [15:0] vCurrent = 0;
reg [15:0] vLines = 309;
reg [15:0] vTotal = 329;
always @* begin
RX2data[6] <= dataEnable;
RX2data[5] <= vsync;
RX2data[4] <= hsync;
RX2data[3:0] <= blue[5:2];
RX1data[6:5] <= blue[1:0];
RX1data[4:0] <= green[5:1];
RX0data[0] <= green[0];
RX0data[5:0] <= red[5:0];
end
always @(posedge bit_clock_out) begin
if (vCurrent == 309 || vCurrent == 0) begin
red <= 63;
end else begin
red <= 0;
end
if (hCurrent == 1 || hCurrent == 1023) begin
blue <= 63;
end else begin
blue <= 0;
end
if (hCurrent > hFront || vCurrent > vLines) begin
dataEnable <= 1'b0;
end else begin
dataEnable <= 1'b1;
end
if (hCurrent >= hSyncPulse) begin
hsync <= 1'b1;
end else begin
hsync <= 1'b0;
end
if (vCurrent == 311 || vCurrent == 312) begin
vsync <= 1'b1;
end else begin
vsync <= 1'b0;
end
if (slot == 0) begin
slot <= 6;
if (hCurrent == hTotal) begin
hCurrent <= 0;
if (vCurrent == vTotal) begin
vCurrent <= 0;
end else begin
vCurrent <= vCurrent + 1;
end
end else begin
hCurrent <= hCurrent + 1;
end
end else begin
slot <= slot - 1;
end
out_clock <= ~out_clock;
cnt <= cnt + 1'b1;
end
assign LED_indicator = cnt[23];
assign pair2 = RX2data[slot];
assign pair1 = RX1data[slot];
assign pair0 = RX0data[slot];
assign pairCLK = CLKdata[slot];
endmodule
| 7.99598 |
module BitClock (
input clk,
output pair2,
output pair1,
output pair0,
output pairCLK,
output LED_indicator
);
fast_clock u1 (
.inclk0(clk),
.c0(bit_clock_out)
);
reg [23:0] cnt;
reg out_clock;
reg [3:0] slot = 6;
reg dataEnable = 1'b0;
reg vsync = 1'b0;
reg hsync = 1'b0;
reg [5:0] red = 6'b000000;
reg [5:0] green = 6'b000000;
reg [5:0] blue = 6'b111111;
reg [6:0] RX0data = 7'b0000000;
reg [6:0] RX1data = 7'b0000000;
reg [6:0] RX2data = 7'b0000000;
reg [6:0] CLKdata = 7'b1100011;
reg [15:0] hCurrent = 0;
reg [15:0] hFront = 1024; //The actual visible pixels
reg [15:0] hSyncPulse = 1140; //1200; //1380; //1216;
reg [15:0] hTotal = 1160; //1220; //1400; //1236;
reg [15:0] vCurrent = 0;
reg [15:0] vLines = 309;
reg [15:0] vTotal = 329;
always @* begin
RX2data[6] <= dataEnable;
RX2data[5] <= vsync;
RX2data[4] <= hsync;
RX2data[3:0] <= blue[5:2];
RX1data[6:5] <= blue[1:0];
RX1data[4:0] <= green[5:1];
RX0data[0] <= green[0];
RX0data[5:0] <= red[5:0];
end
always @(posedge bit_clock_out) begin
case (hCurrent) //Draw white lines on left and right edge
1: begin
green <= 63;
end
2: begin
green <= 63;
end
1023: begin
green <= 63;
end
1024: begin
green <= 63;
end
default: begin
green <= 0;
end
endcase
case (vCurrent)
0: begin
red <= 63;
end
1: begin
red <= 63;
end
308: begin
red <= 63;
end
309: begin
red <= 63;
end
311: begin
vsync <= 1'b1;
end
312: begin
vsync <= 1'b1;
end
default: begin
vsync <= 1'b0;
red <= 0;
end
endcase
if (hCurrent > hFront || vCurrent > vLines) //Data is only enabled during visible pixels - disabled in H and V porches
begin
dataEnable <= 1'b0;
end else begin
dataEnable <= 1'b1;
end
if (hCurrent >= hSyncPulse) //A line ends with 20 pulses of the H sync bit
begin
hsync <= 1'b1;
end else begin
hsync <= 1'b0;
end
if (slot == 0) begin
slot <= 6;
//green <= hCurrent[5:0];
if (hCurrent == hTotal) begin
hCurrent <= 0;
if (vCurrent == vTotal) begin
vCurrent <= 0;
//red <= 0;
end else begin
vCurrent <= vCurrent + 1;
//red <= red + 1;
//if (red == 63)
//begin
//red <= 0;
//end
end
end else begin
hCurrent <= hCurrent + 1;
end
end else begin
slot <= slot - 1;
end
out_clock <= ~out_clock;
cnt <= cnt + 1'b1;
end
assign LED_indicator = cnt[23];
assign pair2 = RX2data[slot];
assign pair1 = RX1data[slot];
assign pair0 = RX0data[slot];
assign pairCLK = CLKdata[slot];
endmodule
| 7.99598 |
module bitcnt_bits_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
addr5,
ce5,
q5,
addr6,
ce6,
q6,
addr7,
ce7,
q7,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input [AWIDTH-1:0] addr5;
input ce5;
output reg [DWIDTH-1:0] q5;
input [AWIDTH-1:0] addr6;
input ce6;
output reg [DWIDTH-1:0] q6;
input [AWIDTH-1:0] addr7;
input ce7;
output reg [DWIDTH-1:0] q7;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[MEM_SIZE-1:0];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[MEM_SIZE-1:0];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram2[MEM_SIZE-1:0];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram3[MEM_SIZE-1:0];
initial begin
$readmemh("./bitcnt_bits_rom.dat", ram0);
$readmemh("./bitcnt_bits_rom.dat", ram1);
$readmemh("./bitcnt_bits_rom.dat", ram2);
$readmemh("./bitcnt_bits_rom.dat", ram3);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram0[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram1[addr3];
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram2[addr4];
end
end
always @(posedge clk) begin
if (ce5) begin
q5 <= ram2[addr5];
end
end
always @(posedge clk) begin
if (ce6) begin
q6 <= ram3[addr6];
end
end
always @(posedge clk) begin
if (ce7) begin
q7 <= ram3[addr7];
end
end
endmodule
| 7.228928 |
module bitcnt_bits (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4,
address5,
ce5,
q5,
address6,
ce6,
q6,
address7,
ce7,
q7
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
input [AddressWidth - 1:0] address2;
input ce2;
output [DataWidth - 1:0] q2;
input [AddressWidth - 1:0] address3;
input ce3;
output [DataWidth - 1:0] q3;
input [AddressWidth - 1:0] address4;
input ce4;
output [DataWidth - 1:0] q4;
input [AddressWidth - 1:0] address5;
input ce5;
output [DataWidth - 1:0] q5;
input [AddressWidth - 1:0] address6;
input ce6;
output [DataWidth - 1:0] q6;
input [AddressWidth - 1:0] address7;
input ce7;
output [DataWidth - 1:0] q7;
bitcnt_bits_rom bitcnt_bits_rom_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1),
.addr2(address2),
.ce2(ce2),
.q2(q2),
.addr3(address3),
.ce3(ce3),
.q3(q3),
.addr4(address4),
.ce4(ce4),
.q4(q4),
.addr5(address5),
.ce5(ce5),
.q5(q5),
.addr6(address6),
.ce6(ce6),
.q6(q6),
.addr7(address7),
.ce7(ce7),
.q7(q7)
);
endmodule
| 6.605695 |
module bitcoin_miner (
input wire clk,
input wire start,
input wire [255:0] first_block_hash,
input wire [127:0] second_block,
input wire [255:0] target,
input wire [31:0] max_nonce,
output reg running,
output reg found,
reg [31:0] nonce
);
localparam BLOCKSIZE = 512;
localparam HASHSIZE = 256;
reg [31:0] current_nonce_be;
wire [31:0] current_nonce_le;
wire [31:0] output_nonce = current_nonce_be - 130;
swap_endian swap_nonce_b2l (
.src(current_nonce_be),
.dst(current_nonce_le)
);
wire [31:0] start_nonce_le = second_block[31:0];
wire [31:0] start_nonce_be;
swap_endian swap_nonce_l2b (
.src(start_nonce_le),
.dst(start_nonce_be)
);
wire [HASHSIZE-1:0] hash_0, hash_1;
wire hash_valid_0, hash_valid_1;
wire [BLOCKSIZE-1:0] block_0 = {
second_block[127:32],
current_nonce_le,
32'h80000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000280
};
wire [BLOCKSIZE-1:0] block_1 = {
hash_0,
32'h80000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000000,
32'h00000100
};
wire [HASHSIZE-1:0] prev_hash_0 = first_block_hash;
wire [HASHSIZE-1:0] prev_hash_1 = {
32'h6a09e667,
32'hbb67ae85,
32'h3c6ef372,
32'ha54ff53a,
32'h510e527f,
32'h9b05688c,
32'h1f83d9ab,
32'h5be0cd19
};
sha256_pipeline sha256_0 (
.clk(clk),
.block_valid(running),
.block(block_0),
.prev_hash(prev_hash_0),
.hash(hash_0),
.hash_valid(hash_valid_0)
);
sha256_pipeline sha256_1 (
.clk(clk),
.block_valid(hash_valid_0),
.block(block_1),
.prev_hash(prev_hash_1),
.hash(hash_1),
.hash_valid(hash_valid_1)
);
wire [HASHSIZE-1:0] hash_sw;
swap_endian #(
.UNIT_WIDTH(8),
.UNIT_COUNT(HASHSIZE / 8)
) swap_hash (
.src(hash_1),
.dst(hash_sw)
);
initial begin
running <= 0;
found <= 0;
current_nonce_be <= 0;
end
wire nonce_end_flag = (nonce == max_nonce);
wire found_flag = (hash_sw <= target);
always @(posedge clk) begin
if (running) begin
current_nonce_be <= current_nonce_be + 1;
if (hash_valid_1) begin
nonce <= output_nonce;
found <= found_flag;
if (nonce_end_flag || found_flag) begin
running <= 0;
end
end
end else begin
if (start) begin
running <= 1;
found <= 0;
current_nonce_be <= start_nonce_be;
nonce <= start_nonce_be;
end
end
end
endmodule
| 6.631865 |
module bitcoin_miner_ip_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
) (
// Users to add ports here
input wire miner_clk,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
bitcoin_miner_ip_v1_0_S00_AXI #(
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) bitcoin_miner_ip_v1_0_S00_AXI_inst (
.miner_clk(miner_clk),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 6.631865 |
module BitComparator (
DataA,
DataB,
A_EQ_B,
A_GT_B,
A_LT_B
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
***************************************************************************/
parameter TwosComplement = 1;
/***************************************************************************
** Here the inputs are defined **
***************************************************************************/
input DataA;
input DataB;
/***************************************************************************
** Here the outputs are defined **
***************************************************************************/
output A_EQ_B;
output A_GT_B;
output A_LT_B;
assign A_EQ_B = (DataA == DataB);
assign A_LT_B = (DataA < DataB);
assign A_GT_B = (DataA > DataB);
endmodule
| 7.270264 |
module bitCounter8 (
KEY,
SW,
HEX0,
HEX1
);
input [3:0] KEY;
input [1:0] SW;
output [6:0] HEX0, HEX1;
wire [7:0] w1;
tFF8bit u0 (
SW[1],
w1,
KEY[0],
SW[0]
);
hexDisplay u1 (
w1,
HEX0,
HEX1
);
endmodule
| 8.618239 |
module bitcount (
B,
count
);
input [7:0] B;
output [3:0] count;
integer k;
reg [3:0] count;
always @(B) begin
count = 0;
for (k = 0; k <= 7; k = k + 1) count = count + B[k];
end
endmodule
| 6.668737 |
module halfadd_tb;
reg [7:0] halfadd_input;
wire [3:0] out_sum;
integer k;
mainmod BC (
.halfadd_input(halfadd_input),
.out_sum(out_sum)
);
initial begin
halfadd_input = 8'b0000_0000;
for (k = 0; k <= 256; k = k + 1) begin
halfadd_input = k;
#5 $display("Input: %b, Bitcount: %d", halfadd_input, out_sum);
end
end
endmodule
| 6.897753 |
module BitDdr (
input reset,
input clkin,
input din_p,
input din_n,
output dout
);
reg reset_i = 1'b0;
reg pflag = 1'b0;
reg nflag = 1'b0;
reg din_p_reg = 1'b0;
reg din_n_reg_i = 1'b0;
reg din_n_reg = 1'b0;
wire dout_p, dout_n;
always @(posedge clkin) reset_i <= reset;
always @(posedge clkin)
if (reset_i) begin
din_p_reg <= din_p;
din_n_reg_i <= 1'b0;
pflag <= 1'b0;
end else begin
din_p_reg <= din_p;
din_n_reg_i <= din_n;
pflag <= ~pflag;
end
always @(negedge clkin)
if (reset_i) begin
din_n_reg <= 1'b0;
nflag <= 1'b0;
end else begin
din_n_reg <= din_n_reg_i;
nflag <= ~nflag;
end
assign dout_p = din_p_reg & (~(pflag ^ nflag));
assign dout_n = din_n_reg & ((pflag ^ nflag));
assign dout = dout_p | dout_n;
endmodule
| 7.28625 |
module dp_analog_mappings (
input wire [1:0] vod,
input wire [1:0] pree,
output reg [4:0] out_vod,
output reg [5:0] out_pree_post_tap1 // bit5 is polarity, 1=neg 2=pos
);
always @(*)
case (vod)
2'b00 : // 400mv
begin
case (pree)
2'b00 : // (0db)
begin
out_vod = 5'd13;
out_pree_post_tap1 = {1'b1, 5'd0};
end
2'b01 : // (3.5db)
begin
out_vod = 5'd19;
out_pree_post_tap1 = {1'b1, 5'd6};
end
2'b10 : // (6db)
begin
out_vod = 5'd25;
out_pree_post_tap1 = {1'b1, 5'd12};
end
2'b11 : // (9db)
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd19};
end
endcase
end
2'b01 : // 600mv
begin
case (pree)
2'b00 : // (0db)
begin
out_vod = 5'd19;
out_pree_post_tap1 = {1'b1, 5'd0};
end
2'b01 : // (3.5db)
begin
out_vod = 5'd28;
out_pree_post_tap1 = {1'b1, 5'd9};
end
2'b10 : // (6db)
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd14};
end
2'b11 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd14};
end
endcase
end
2'b10 : // 800mv
begin
case (pree)
2'b00 : // (0db)
begin
out_vod = 5'd25;
out_pree_post_tap1 = {1'b1, 5'd0};
end
2'b01 : // (3.5db)
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd6};
end
2'b10 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd6};
end
2'b11 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd6};
end
endcase
end
2'b11 : // 1200mv
begin
case (pree)
2'b00 : // (0db)
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd0};
end
2'b01 : //
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd0};
end
2'b10 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd0};
end
2'b11 : // unused
begin
out_vod = 5'd31;
out_pree_post_tap1 = {1'b1, 5'd0};
end
endcase
end
endcase
endmodule
| 6.885853 |
module bitEncoder (
noise,
messageBit,
r_out
);
input wire [31:0] noise;
input wire messageBit;
output reg [7:0] r_out;
reg [7:0] dataStruct;
reg [7:0] noiseTemp;
always @(messageBit) begin
case (messageBit)
0: dataStruct = 10010000;
1: dataStruct = 00010000;
endcase
noiseTemp[7:0] = noise[31:24];
//Shift noiseTemp Here
noiseTemp = {4'b0000, noiseTemp[7:4]}; //shift by 6 >>
//noiseTemp = 8'b00000000;
r_out <= dataStruct + noiseTemp;
end
endmodule
| 6.87871 |
module BitError (
clk,
reset,
din,
dout
);
input clk;
input reset;
input [1:0] din;
output [1:0] dout;
parameter Le = 11;
reg [1:0] dout_reg;
reg [4:0] cnt;
reg flag;
always @(posedge clk or negedge reset) begin
if (!reset) begin
cnt <= 0;
flag <= 0;
end else begin
cnt <= (cnt + 1) % Le;
if (cnt == 2) begin
flag <= 1;
end else begin
flag <= 0;
end
end
end
assign dout[1] = flag ? ~din[1] : din[1];
assign dout[0] = flag ? ~din[0] : din[0];
endmodule
| 6.840476 |
module biterrordetect2 (
input wire clock,
input wire bitin, // vergleich 1
input wire bitout, // vergleich 2
input wire activ, // synchron neg. clock
input wire reset, // synchron neg. clock
output wire biterror // ergebnis
);
//tmrg default triplicate
//tmrg tmr_error false
reg error;
//triplication signals
wire [15:0] errorVoted = error;
assign biterror = errorVoted;
always@(posedge clock) // DW 2005_06_30 clock Flanke von negativ auf positiv geaendert.
begin
if (reset == 1'b0) error <= 1'b0;
else if (activ == 1'b1) begin
if (bitin != bitout) error <= 1'b1;
else error <= 1'b0;
end else error <= errorVoted;
end
endmodule
| 7.185164 |
module BITEXPAND (
input [31:0] inData,
output [63:0] outData
);
/*
* module to expand a 2's complement data from 32bits to 64bits
* input:
* 32 bit data input
* output:
* 64 bit sign preserved data
*/
assign outData[31:0] = inData[31:0];
assign outData[63:32] = inData[31] ? 32'hFFFFFFFF : 32'h00000000;
endmodule
| 8.844956 |
module bitExtension (
in,
out
);
input [0:15] in;
output reg [0:29] out;
always @(in) begin
if (in[0] == 1) begin
out = {14'b11111111111111, in};
end else begin
out = in;
end
end
endmodule
| 7.642333 |
module bitExtensionJump (
in,
out
);
input [0:23] in;
output reg [0:29] out;
always @(in) begin
if (in[0] == 1) begin
out = {6'b111111, in};
end else begin
out = {6'b000000, in};
end
end
endmodule
| 8.124643 |
module bitExtensionJump32 (
in,
out
);
input [0:23] in;
output reg [0:31] out;
always @(in) begin
if (in[0] == 1) begin
out = {8'b11111111, in};
end else begin
out = in;
end
end
endmodule
| 8.124643 |
module BitExtensor(Inpt, Outp);
parameter InputSize;
input [InputSize-1:0] Inpt;
output reg [31:0] Outp;
always@(*)
begin
Outp = {{(32-InputSize){1'b0}}, Inpt};
end
endmodule
| 7.772686 |
module sign extends inputs (usually immediate values) up to the size
* expected by the ALU (32 bits, in our case).
* May 3rd, 2016
* Conor O'Connell
**********************************/
//http://stackoverflow.com/questions/4176556/how-to-sign-extend-a-number-in-verilog
module bitFieldExt(valin, extended );
parameter size_in = 16;
parameter size_out = 32;
input [size_in - 1:0] valin;
output [size_out - 1:0] extended;
wire [size_in - 1:0] valin;
reg temp = 0;
assign extended[size_out - 1:0] = { {( size_out - size_in ){temp}}, valin[size_in-1:0] };
endmodule
| 9.119537 |
module bitgen (
SEL,
bitstream
);
input [3:0] SEL;
output reg bitstream;
always @(SEL) begin
bitstream = 0;
case (SEL)
4'b0001: bitstream = 1'b1;
4'b0010: bitstream = 1'b0;
4'b0011: bitstream = 1'b0;
4'b0100: bitstream = 1'b0;
4'b0101: bitstream = 1'b1;
4'b0110: bitstream = 1'b1;
4'b0111: bitstream = 1'b0;
4'b1000: bitstream = 1'b1;
endcase
end
endmodule
| 6.637749 |
module bitGen2 (
bright,
glyphData,
counter,
g,
b,
r,
hcount,
vcount,
lettervalue,
numbervalue
); // bitGen 1 that colors the whole screen depending on 8 switches colors
input bright;
input [9:0] hcount, vcount;
input [39:0] glyphData;
input [0:39] lettervalue, numbervalue;
input [5:0] counter;
reg [39:0] value;
output reg [7:0] r, g, b; // for red, green, blue
//always block to determine where we are within the vga by hcount and vcount
always @(*) begin
if (bright == 1) begin // start coloring when bright is on
//glyph building
if ((hcount >= 320) && (hcount < 640) && (vcount >= 80) && (vcount < 400)) begin
//if glyph number is 1 then white
if (glyphData[counter] == 1) begin
r = 8'd255;
g = 8'd255;
b = 8'd255;
end else if (glyphData[counter] == 0) begin
r = 8'd0;
g = 8'd0;
b = 8'd0;
end else begin
r = 8'd0;
g = 8'd0;
b = 8'd0;
end
end //building letters
else if(((hcount >= 320 && hcount < 640) && (vcount >= 40 && vcount < 80)))begin //top section for letters
if (lettervalue[counter] == 1) begin
r = 8'd255;
g = 8'd255;
b = 8'd255;
end else if (lettervalue[counter] == 0) begin
r = 8'd75;
g = 8'd25;
b = 8'd0;
end else begin
r = 8'd0;
g = 8'd0;
b = 8'd0;
end
end //building numbers
else if ((hcount >= 280 && hcount < 320) && (vcount >= 80 && vcount < 400)) begin
if (numbervalue[counter] == 1) begin
r = 8'd255;
g = 8'd255;
b = 8'd255;
end else if (numbervalue[counter] == 0) begin
r = 8'd75;
g = 8'd25;
b = 8'd0;
end else begin
r = 8'd0;
g = 8'd0;
b = 8'd0;
end
end //building boarder around chest board
else if((hcount >= 280 && hcount < 320 && vcount >= 40 && vcount < 80) ||
((hcount >= 280) && (hcount < 680) &&(vcount >= 400) && (vcount < 440))||
((hcount >= 640) && (hcount < 680) && (vcount >= 40) && (vcount < 440)) )begin
r = 8'd75;
g = 8'd25;
b = 8'd0;
end else begin
r = 8'd0;
g = 8'd0;
b = 8'd0;
end
end else begin
r = 8'd0;
g = 8'd0;
b = 8'd0;
end
end
endmodule
| 7.314791 |
module used for inversing every bit of a register input
module bitInv
#(parameter N = 8)
(
input [N-1:0] din,
output [N-1:0] out
);
assign out = ~din;
endmodule
| 10.101555 |
module Bitlet_AlignerArray #(
parameter N_align = 8
) (
input [N_align*`Wid_abs-1:0] Wabs_vec,
input [N_align*`Wid_exs-1:0] Esum_vec,
input [ `Wid_exs-1:0] Emax,
output [N_align*`Wid_abs-1:0] Walign_vec
);
generate
genvar g;
for (g = 0; g < N_align; g = g + 1) begin
Bitlet_Aligner UALIGNER (
.Wabs (Wabs_vec[(g*`Wid_abs)+:`Wid_abs]),
.Esum (Esum_vec[(g*`Wid_exs)+:`Wid_exs]),
.Emax (Emax),
.Walign(Walign_vec[(g*`Wid_abs)+:`Wid_abs])
);
end
endgenerate
endmodule
| 6.993304 |
module Bitlet_Aligner (
input [`Wid_abs-1:0] Wabs,
input [`Wid_exs-1:0] Esum,
input [`Wid_exs-1:0] Emax,
output [`Wid_abs-1:0] Walign
);
wire [`Wid_exs-1:0] Ediff;
assign Ediff = Emax - Esum;
assign Walign = Wabs >> Ediff;
endmodule
| 6.993304 |
module.
* Dependency: Bitlet_CE.v Bitlet_Accumulator.v
*
* Author: ZHU Zi-Xuan (UESTC), 2021.02
*/
`timescale 1ns / 1ps
`include "Bitlet_Defs.vh"
module Bitlet_Calculator
#(
parameter N_total = 64
)
(
input clk,
input rst_n,
input [$clog2(N_total)-1:0] N_calculate,
input [`Max_quant-1:0] prune,
input flush,
input Wabs_vld,
input [N_total*`Wid_abs-1:0] Wabs_vec,
input [N_total*`Wid_fix-1:0] Afix_vec,
output Aacc_vld,
output [`Wid_acc-1:0] Aacc
);
/* ---------------------------- Bitlet CE module ---------------------------- */
wire Asel_vld;
wire [`N_channel*`Wid_fix-1:0] Asel_vec;
Bitlet_CE #(.N_total(N_total)) UBCE
(
.clk(clk),
.rst_n(rst_n),
.N_calculate(N_calculate),
.prune(prune),
.flush(flush),
.Wabs_vld(Wabs_vld),
.Wabs_vec(Wabs_vec),
.Afix_vec(Afix_vec),
.Asel_vld(Asel_vld),
.Asel_vec(Asel_vec)
);
/* ----------------------- 24-input shift accumulator ----------------------- */
Bitlet_Accumulator UACCUMULATOR
(
.clk(clk),
.rst_n(rst_n),
.flush(flush),
.Asel_vld(Asel_vld),
.Asel_vec(Asel_vec),
.Aacc_vld(Aacc_vld),
.Aacc(Aacc)
);
endmodule
| 8.309359 |
module Bitlet_FindMax #(
parameter N_input = 16,
parameter P_input = 4
) (
input clk,
input rst_n,
input flush,
input Esum_vld,
input [N_input*`Wid_exs-1:0] Esum_vec,
output reg Emax_vld,
output reg [ `Wid_exs-1:0] Emax
);
wire [ `Wid_exs-1:0] pmax;
wire pmax_vld;
reg [$clog2(P_input)-1:0] max_cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) max_cnt <= 'b0;
else if (flush) max_cnt <= 'b0;
else if (pmax_vld) max_cnt <= max_cnt + 1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Emax <= 'b0;
else if (flush) Emax <= 'b0;
else if (pmax_vld && (pmax > Emax)) Emax <= pmax;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Emax_vld <= 1'b0;
else if (pmax_vld && (max_cnt == (P_input - 1))) Emax_vld <= 1'b1;
else if (Emax_vld) Emax_vld <= 1'b0;
end
Bitlet_MaxTree #(
.N(N_input),
.W(`Wid_exs)
) UMAXTREE (
.clk(clk),
.rst_n(rst_n),
.DI_vld(Esum_vld),
.DI_vec(Esum_vec),
.MAX_vld(pmax_vld),
.MAX(pmax)
);
endmodule
| 6.776531 |
module FindMax #(
parameter W = 9
) (
input [W-1:0] I1,
input [W-1:0] I0,
output [W-1:0] O
);
assign O = (I1 < I0) ? I0 : I1;
endmodule
| 7.80141 |
module Bitlet_PackFixed (
input clk,
input rst_n,
input [`Wid_quant-1:0] quant,
input Aacc_vld,
input [ `Wid_acc-1:0] Aacc,
output reg res_vld,
output reg [ `Wid_bin-1:0] res
);
wire [`Max_quant:0] illigal_sign_bit;
reg tmp_flow, tmp_overflow;
wire Aacc_sig;
assign Aacc_sig = Aacc[`Wid_acc-1];
generate
genvar g;
assign illigal_sign_bit[`Max_quant] = ^(Aacc[(`Wid_acc-1):(`Max_quant+`Wid_abs)]);
for (g = 0; g < `Max_quant; g = g + 1)
assign illigal_sign_bit[g] = illigal_sign_bit[g+1] | (Aacc_sig ^ Aacc[g+`Wid_abs]);
endgenerate
always @(*) begin
tmp_flow = illigal_sign_bit[quant];
tmp_overflow = tmp_flow & (!Aacc_sig);
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) res <= 'b0;
else if (Aacc_vld) begin
res[`Wid_bin-1] <= Aacc_sig;
res[0+:`Wid_abs] <= (tmp_flow) ? {`Wid_abs{tmp_overflow}} : Aacc[quant+:`Wid_abs];
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) res_vld <= 1'b0;
else if (res_vld) res_vld <= 1'b0;
else res_vld <= Aacc_vld;
end
endmodule
| 6.601929 |
module Bitlet_PackFloat (
input clk,
input rst_n,
input Aacc_vld,
input [`Wid_acc-1:0] Aacc,
input Emax_vld,
input [`Wid_exs-1:0] Emax,
output reg res_vld,
output reg [`Wid_bin-1:0] res
);
integer i;
localparam Wid_cnt = $clog2(`Wid_acc);
wire Aacc_sig;
assign Aacc_sig = Aacc[`Wid_acc-1];
/* ----------------- calculate final Emax with correct bias ----------------- */
reg [`Wid_exs:0] Emax_correct;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Emax_correct <= 'b0;
else if (Emax_vld) Emax_correct <= $signed({1'b0, Emax}) - `Const_bias - `Const_frac;
end
/* --------------- pack float point step 1: calculate acc_abs --------------- */
reg [`Wid_acc-1:0] Aacc_abs;
reg abs_vld;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Aacc_abs <= 'b0;
else if (Aacc_vld) Aacc_abs <= (Aacc_sig) ? (~Aacc + 1) : Aacc;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) abs_vld <= 1'b0;
else if (abs_vld != Aacc_vld) abs_vld <= Aacc_vld;
end
/* -------------------- pack float point step 2: findMSB -------------------- */
wire tmp_zero;
wire [Wid_cnt-1:0] tmp_cnt;
reg zero;
reg [Wid_cnt-1:0] cnt;
reg cnt_vld;
Bitlet_FindMSB #(
.W(`Wid_acc)
) UFINDMSB (
.DI (Aacc_abs),
.zero(tmp_zero),
.cnt (tmp_cnt)
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
zero <= 'b0;
cnt <= 'b0;
end else if (abs_vld) begin
zero <= tmp_zero;
cnt <= tmp_cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_vld <= 'b0;
else if (cnt_vld != abs_vld) cnt_vld <= abs_vld;
end
/* ----------------- pack float point step 3: normalization ----------------- */
wire [ `Wid_exs:0] tmp_exp_norm;
wire [`Wid_abs-1:0] tmp_abs_norm;
reg [`Wid_exp-1:0] exp_norm;
reg [ `Wid_exs:0] abs_sa;
reg [`Wid_abs-1:0] abs_norm;
reg fp_inf;
reg norm_vld;
assign tmp_exp_norm = $signed(Emax_correct) + cnt;
assign tmp_abs_norm = {Aacc_abs, `Wid_man'b0} >> cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
exp_norm <= 'b0;
abs_sa <= 'b0;
abs_norm <= 'b0;
fp_inf <= 'b0;
end else if (cnt_vld) begin
exp_norm <= (($signed(tmp_exp_norm) < `Const_emin) || zero) ? 'b0 : tmp_exp_norm[0+:`Wid_exp];
abs_sa <= (($signed(
tmp_exp_norm
) < `Const_emin) && !zero) ? (1 - $signed(
tmp_exp_norm
)) : 'b0;
abs_norm <= (zero) ? 'b0 : tmp_abs_norm[0+:`Wid_abs];
fp_inf <= (($signed(tmp_exp_norm) > `Const_emax) && (!zero)) ? 1'b1 : 1'b0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) norm_vld <= 1'b0;
else if (norm_vld != cnt_vld) norm_vld <= cnt_vld;
end
/* ------------------- pack float point step 4: exception ------------------- */
wire [`Wid_abs-1:0] tmp_final_abs;
reg [`Wid_man-1:0] final_man;
reg [`Wid_exp-1:0] final_exp;
assign tmp_final_abs = abs_norm >> abs_sa;
always @(*) begin
final_man = (zero | fp_inf) ? 'b0 : tmp_final_abs[0+:`Wid_man];
final_exp = (fp_inf) ? (`Const_emax + 1) : exp_norm;
end
/* ---------------------------- pack float point ---------------------------- */
always @(posedge clk or negedge rst_n) begin
if (!rst_n) res <= 'b0;
else if (norm_vld) res <= {Aacc_sig, final_exp, final_man};
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) res_vld <= 1'b0;
else if (res_vld != norm_vld) res_vld <= norm_vld;
end
endmodule
| 6.926859 |
module.
* Dependency: Bitlet_Processor.v Bitlet_Calculator.v Bitlet_Postprocessor.v
*
* Author: ZHU Zi-Xuan (UESTC), 2021.02
*/
`timescale 1ns / 1ps
`include "Bitlet_Defs.vh"
module Bitlet_PE
#(
parameter N_total = 64,
parameter N_input = 16
)
(
input clk,
input rst_n,
input isfix, // active high, stable
input relu, // active high, stable
input [`Wid_quant-1:0] quant, // quantization, 24~0, SPI
input [`Max_quant-1:0] prune, // prunning width, 24~0, SPI
input flush, // active high, 1 cycle
input [N_total*1-1:0] Wsig_vec,
input [N_total*`Wid_exp-1:0] Wexp_vec,
input [N_total*`Wid_abs-1:0] Wabs_vec,
input Abin_vld, // active high, 1 cycle
input [N_input*`Wid_bin-1:0] Abin_vec,
output res_vld, // active high, 1 cycle
output [`Wid_bin-1:0] res
);
wire Emax_vld;
wire [`Wid_exs-1:0] Emax;
wire Wabs_vld;
wire [N_total*`Wid_fix-1:0] Afix_buff;
wire [N_total*`Wid_abs-1:0] Wabs_buff;
wire Aacc_vld;
wire [`Wid_acc-1:0] Aacc;
Bitlet_Preprocessor #(.N_total(N_total), .N_input(N_input)) UPREPROCESSOR
(
.clk(clk),
.rst_n(rst_n),
.isfix(isfix),
.flush(flush),
.Wsig_vec(Wsig_vec),
.Wexp_vec(Wexp_vec),
.Wabs_vec(Wabs_vec),
.Abin_vld(Abin_vld),
.Abin_vec(Abin_vec),
.Emax_vld(Emax_vld),
.Emax(Emax),
.finish(Wabs_vld),
.Afix_buff(Afix_buff),
.Wabs_buff(Wabs_buff)
);
Bitlet_Calculator #(.N_total(N_total)) UCALCULATOR
(
.clk(clk),
.rst_n(rst_n),
.prune(prune),
.flush(flush),
.Wabs_vld(Wabs_vld),
.Wabs_vec(Wabs_buff),
.Afix_vec(Afix_buff),
.Aacc_vld(Aacc_vld),
.Aacc(Aacc)
);
Bitlet_Postprocessor UPOSTPROCESSOR
(
.clk(clk),
.rst_n(rst_n),
.isfix(isfix),
.relu(relu),
.quant(quant),
.Aacc_vld(Aacc_vld),
.Aacc(Aacc),
.Emax_vld(Emax_vld),
.Emax(Emax),
.res_vld(res_vld),
.res(res)
);
endmodule
| 8.309359 |
module Bitlet_Prim_BufferArray #(
parameter N = 4, // number of data
parameter W = 16 // width of data
) (
input clk,
input rst_n,
input enw, // active high, 1 cycle
input [$clog2(N)-1:0] sel,
input [ 1*W-1:0] DI,
output [ N*W-1:0] DO
);
wire [N-1:0] sel_dec;
wire [N-1:0] enw_dec;
Bitlet_Prim_Decoder_Decimal_to_Onehot #(
.W(N)
) UDECODER (
.DI(sel),
.DO(sel_dec)
);
generate
genvar g;
for (g = 0; g < N; g = g + 1) begin
assign enw_dec[g] = enw & sel_dec[g];
end
for (g = 0; g < N; g = g + 1) begin
Bitlet_Prim_Buffer #(
.W(W)
) UBUFFER (
.clk(clk),
.rst_n(rst_n),
.enw(enw_dec[g]),
.DI(DI),
.DO(DO[(g*W)+:W])
);
end
endgenerate
endmodule
| 8.719267 |
module Bitlet_Prim_Buffer #(
parameter W = 16 // width of data
) (
input clk,
input rst_n,
input enw, // active high, 1 cycle
input [W-1:0] DI,
output reg [W-1:0] DO
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) DO <= 'b0;
else if (enw) DO <= DI;
end
endmodule
| 8.719267 |
module Bitlet_Cmp4to2 #(
parameter W = 16 // width of data
) (
input [W-1:0] I3,
input [W-1:0] I2,
input [W-1:0] I1,
input [W-1:0] I0,
output [W-1:0] O1,
output [W-1:0] O0
);
wire [ W:0] Cin;
wire [W-1:0] Ctmp;
assign Cin[0] = 1'b0;
assign O0 = Ctmp << 1;
generate
genvar g;
for (g = 0; g < W; g = g + 1) begin
Bitlet_Compactor_4to2 UCOMPACTOR4TO2 (
.I3(I3[g]),
.I2(I2[g]),
.I1(I1[g]),
.I0(I0[g]),
.Cin(Cin[g]),
.S(O1[g]),
.C(Ctmp[g]),
.Cout(Cin[g+1])
);
end
endgenerate
endmodule
| 7.24442 |
module Bitlet_Compactor_4to2 (
input Cin,
input I3,
I2,
I1,
I0,
output Cout,
output C,
S
);
wire m0, m1, m2;
assign m0 = I0 ^ I1;
assign m1 = I2 ^ I3;
assign m2 = m0 ^ m1;
assign Cout = (m1) ? I1 : I3;
assign C = (m2) ? Cin : I0;
assign S = Cin ^ m2;
endmodule
| 7.988716 |
module Bitlet_Compactor_3to2 (
input I2,
I1,
I0,
output C,
S
);
wire m0;
assign m0 = I0 ^ I1;
assign C = (m0) ? I2 : I1;
assign S = I2 ^ m0;
endmodule
| 7.988716 |
module Bitlet_Prim_Decoder_Decimal_to_Onehot #(
parameter W = 16 // width of output
) (
input [$clog2(W)-1:0] DI,
output [ W-1:0] DO
);
assign DO = 'b1 << DI;
endmodule
| 8.659769 |
module Bitlet_ReassemblerArray #(
parameter N_input = 16
) (
input isfix, // active high, stable
input [ N_input*1-1:0] Wsig_vec,
input [N_input*`Wid_exp-1:0] Wexp_vec,
input [N_input*`Wid_bin-1:0] Abin_vec,
output [N_input*`Wid_exs-1:0] Esum_vec,
output [N_input*`Wid_fix-1:0] Afix_vec
);
generate
genvar g;
for (g = 0; g < N_input; g = g + 1) begin
Bitlet_Reassembler UDEASSEMBLER (
.isfix(isfix),
.Wsig (Wsig_vec[(g*1)+:1]),
.Wexp (Wexp_vec[(g*`Wid_exp)+:`Wid_exp]),
.Abin (Abin_vec[(g*`Wid_bin)+:`Wid_bin]),
.Esum (Esum_vec[(g*`Wid_exs)+:`Wid_exs]),
.Afix (Afix_vec[(g*`Wid_fix)+:`Wid_fix])
);
end
endgenerate
endmodule
| 7.731219 |
module Bitlet_Reassembler (
input isfix,
input Wsig,
input [`Wid_exp-1:0] Wexp,
input [`Wid_bin-1:0] Abin,
output [`Wid_exs-1:0] Esum,
output [`Wid_fix-1:0] Afix
);
wire Asig;
wire [`Wid_exp-1:0] Aexp;
wire [`Wid_abs-1:0] Aman;
Bitlet_Unpack UUNPACK (
.bin (Abin),
.isfix(isfix),
.sig (Asig),
.exp (Aexp),
.man (Aman)
);
reg [`Wid_fix-1:0] tmp_fix;
assign Esum = Wexp + Aexp;
assign Afix = tmp_fix;
always @(*) begin
if (isfix) tmp_fix = (Wsig) ? (~{Asig, Aman} + 1) : {Asig, Aman};
else tmp_fix = (Wsig ^ Asig) ? (~{1'b0, Aman} + 1) : {1'b0, Aman};
end
endmodule
| 7.731219 |
module Bitlet_Unpack (
input [`Wid_bin-1:0] bin,
input isfix,
output sig,
output [`Wid_exp-1:0] exp,
output [`Wid_abs-1:0] man
);
assign sig = bin[`Wid_bin-1];
assign exp = ((~|bin[`Wid_man+:`Wid_exp]) & (|bin[0+:`Wid_man])) ? 'b1 : bin[`Wid_man+:`Wid_exp];
assign man = (isfix) ? bin[0+:`Wid_abs] : {|exp, bin[0+:`Wid_man]};
endmodule
| 6.766586 |
module for 10-digit bitmap ROM
module digits10_case(digit, yofs, bits);
input [3:0] digit; // digit 0-9
input [2:0] yofs; // vertical offset (0-4)
output reg [4:0] bits; // output (5 bits)
// combine {digit,yofs} into single ROM address
wire [6:0] caseexpr = {digit,yofs};
always @(*)
case (caseexpr)/*{w:5,h:5,count:10}*/
7'o00: bits = 5'b11111;
7'o01: bits = 5'b10001;
7'o02: bits = 5'b10001;
7'o03: bits = 5'b10001;
7'o04: bits = 5'b11111;
7'o10: bits = 5'b01100;
7'o11: bits = 5'b00100;
7'o12: bits = 5'b00100;
7'o13: bits = 5'b00100;
7'o14: bits = 5'b11111;
7'o20: bits = 5'b11111;
7'o21: bits = 5'b00001;
7'o22: bits = 5'b11111;
7'o23: bits = 5'b10000;
7'o24: bits = 5'b11111;
7'o30: bits = 5'b11111;
7'o31: bits = 5'b00001;
7'o32: bits = 5'b11111;
7'o33: bits = 5'b00001;
7'o34: bits = 5'b11111;
7'o40: bits = 5'b10001;
7'o41: bits = 5'b10001;
7'o42: bits = 5'b11111;
7'o43: bits = 5'b00001;
7'o44: bits = 5'b00001;
7'o50: bits = 5'b11111;
7'o51: bits = 5'b10000;
7'o52: bits = 5'b11111;
7'o53: bits = 5'b00001;
7'o54: bits = 5'b11111;
7'o60: bits = 5'b11111;
7'o61: bits = 5'b10000;
7'o62: bits = 5'b11111;
7'o63: bits = 5'b10001;
7'o64: bits = 5'b11111;
7'o70: bits = 5'b11111;
7'o71: bits = 5'b00001;
7'o72: bits = 5'b00001;
7'o73: bits = 5'b00001;
7'o74: bits = 5'b00001;
7'o100: bits = 5'b11111;
7'o101: bits = 5'b10001;
7'o102: bits = 5'b11111;
7'o103: bits = 5'b10001;
7'o104: bits = 5'b11111;
7'o110: bits = 5'b11111;
7'o111: bits = 5'b10001;
7'o112: bits = 5'b11111;
7'o113: bits = 5'b00001;
7'o114: bits = 5'b11111;
default: bits = 0;
endcase
endmodule
| 7.337151 |
module digits10_array (
digit,
yofs,
bits
);
input [3:0] digit; // digit 0-9
input [2:0] yofs; // vertical offset (0-4)
output [7:0] bits; // output (5 bits)
reg [7:0] bitarray[0:15][0:7]; // ROM array (16 x 5 x 5 bits)
assign bits = bitarray[digit][yofs]; // assign module output
integer i, j;
initial begin /*{w:5,h:5,count:10}*/
bitarray[0][0] = 5'b11111;
bitarray[0][1] = 5'b10001;
bitarray[0][2] = 5'b10001;
bitarray[0][3] = 5'b10001;
bitarray[0][4] = 5'b11111;
bitarray[1][0] = 5'b01100;
bitarray[1][1] = 5'b00100;
bitarray[1][2] = 5'b00100;
bitarray[1][3] = 5'b00100;
bitarray[1][4] = 5'b11111;
bitarray[2][0] = 5'b11111;
bitarray[2][1] = 5'b00001;
bitarray[2][2] = 5'b11111;
bitarray[2][3] = 5'b10000;
bitarray[2][4] = 5'b11111;
bitarray[3][0] = 5'b11111;
bitarray[3][1] = 5'b00001;
bitarray[3][2] = 5'b11111;
bitarray[3][3] = 5'b00001;
bitarray[3][4] = 5'b11111;
bitarray[4][0] = 5'b10001;
bitarray[4][1] = 5'b10001;
bitarray[4][2] = 5'b11111;
bitarray[4][3] = 5'b00001;
bitarray[4][4] = 5'b00001;
bitarray[5][0] = 5'b11111;
bitarray[5][1] = 5'b10000;
bitarray[5][2] = 5'b11111;
bitarray[5][3] = 5'b00001;
bitarray[5][4] = 5'b11111;
bitarray[6][0] = 5'b11111;
bitarray[6][1] = 5'b10000;
bitarray[6][2] = 5'b11111;
bitarray[6][3] = 5'b10001;
bitarray[6][4] = 5'b11111;
bitarray[7][0] = 5'b11111;
bitarray[7][1] = 5'b00001;
bitarray[7][2] = 5'b00001;
bitarray[7][3] = 5'b00001;
bitarray[7][4] = 5'b00001;
bitarray[8][0] = 5'b11111;
bitarray[8][1] = 5'b10001;
bitarray[8][2] = 5'b11111;
bitarray[8][3] = 5'b10001;
bitarray[8][4] = 5'b11111;
bitarray[9][0] = 5'b11111;
bitarray[9][1] = 5'b10001;
bitarray[9][2] = 5'b11111;
bitarray[9][3] = 5'b00001;
bitarray[9][4] = 5'b11111;
// clear unused array entries
for (i = 0; i <= 9; i++) for (j = 5; j <= 7; j++) bitarray[i][j] = 0;
for (i = 10; i <= 15; i++) for (j = 0; j <= 7; j++) bitarray[i][j] = 0;
end
endmodule
| 7.526921 |
module top (
input CLK, // 16 or 12MHz clock
output VGA_BLUE,
output VGA_GREEN,
output VGA_RED,
output VGA_HSYNC,
output VGA_VSYNC
);
wire vsync, hsync, red, green, blue;
assign VGA_VSYNC = vsync;
assign VGA_HSYNC = hsync;
assign VGA_RED = red;
assign VGA_GREEN = green;
assign VGA_BLUE = blue;
wire pclk;
reg [10:0] hpos;
reg [10:0] vpos;
wire video_active;
VGASyncGen vga_generator (
.clk(CLK),
.hsync(hsync),
.vsync(vsync),
.x_px(hpos),
.y_px(vpos),
.activevideo(video_active),
.px_clk(pclk)
);
reg prev_vsync;
wire [3:0] digit = hpos[7:4];
wire [2:0] xofs = hpos[3:1];
wire [2:0] yofs = vpos[3:1];
wire [7:0] bits;
digits10_array numbers (
.digit(digit),
.yofs (yofs),
.bits (bits)
);
always @(posedge pclk) begin
prev_vsync <= vsync;
if (prev_vsync && !vsync) begin
// vsync has been brought low; we're in the vertical blanking period;
// update per-frame animation values
end
if (video_active) begin
red = 0;
green = bits[xofs^3'b111]; // 0..7
blue = 0;
end else begin
blue = 1'b0;
green = 1'b0;
red = 1'b0;
end
end
endmodule
| 7.233807 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 (1'b0),
.sel(reset),
.o (resetout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(resetout),
.reset(1'b0),
.set(set),
.q(q)
);
endmodule
| 7.286889 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module bitmap_gen (
input wire clk,
reset,
input wire video_on,
input [1:0] btn,
input [2:0] sw,
input wire [9:0] pix_x,
pix_y,
output reg [2:0] bit_rgb
);
// constant and signal declaration
wire refr_tick, load_tick;
//--------------------------------------------
// video sram
//--------------------------------------------
wire we;
wire [13:0] addr_r, addr_w;
wire [2:0] din, dout;
//--------------------------------------------
// dot location and velocity
//--------------------------------------------
localparam MAX_X = 128;
localparam MAX_Y = 128;
// dot velocity can be pos or neg
localparam DOT_V_P = 1;
localparam DOT_V_N = -1;
// reg to keep track of dot location
reg [6:0] dot_x_reg, dot_y_reg;
wire [6:0] dot_x_next, dot_y_next;
// reg to keep track of dot velocity
reg [6:0] v_x_reg, v_y_reg;
wire [6:0] v_x_next, v_y_next;
//--------------------------------------------
// object output signals
//--------------------------------------------
wire bitmap_on;
wire [2:0] bitmap_rgb;
// body
// instantiate debounce circuit for a button
debounce deb_unit (
.clk(clk),
.reset(reset),
.sw(btn[0]),
.db_level(),
.db_tick(load_tick)
);
// instantiate dual-port video RAM (2^12-by-7)
xilinx_dual_port_ram_sync #(
.ADDR_WIDTH(14),
.DATA_WIDTH(3)
) video_ram (
.clk(clk),
.we(we),
.addr_a(addr_w),
.addr_b(addr_r),
.din_a(din),
.dout_a(),
.dout_b(dout)
);
// video ram interface
assign addr_w = {dot_y_reg, dot_x_reg};
assign addr_r = {pix_y[6:0], pix_x[6:0]};
assign we = 1'b1;
assign din = sw;
assign bitmap_rgb = dout;
// registers
always @(posedge clk, posedge reset)
if (reset) begin
dot_x_reg <= 0;
dot_y_reg <= 0;
v_x_reg <= DOT_V_P;
v_y_reg <= DOT_V_P;
end else begin
dot_x_reg <= dot_x_next;
dot_y_reg <= dot_y_next;
v_x_reg <= v_x_next;
v_y_reg <= v_y_next;
end
// refr_tick: 1-clock tick asserted at start of v-sync
assign refr_tick = (pix_y == 481) && (pix_x == 0);
// pixel within bit map area
assign bitmap_on = (pix_x <= 127) & (pix_y <= 127);
// dot position
// "randomly" load dot location when btn[0] pressed
assign dot_x_next = (load_tick) ? pix_x[6:0] : (refr_tick) ? dot_x_reg + v_x_reg : dot_x_reg;
assign dot_y_next = (load_tick) ? pix_y[6:0] : (refr_tick) ? dot_y_reg + v_y_reg : dot_y_reg;
// dot x velocity
assign v_x_next = (dot_x_reg == 1) ? DOT_V_P : // reach left
(dot_x_reg == (MAX_X - 2)) ? DOT_V_N : // reach right
v_x_reg;
// dot y velocity
assign v_y_next = (dot_y_reg == 1) ? DOT_V_P : // reach top
(dot_y_reg == (MAX_Y - 2)) ? DOT_V_N : // reach bottom
v_y_reg;
//--------------------------------------------
// rgb multiplexing circuit
//--------------------------------------------
always @*
if (~video_on) bit_rgb = 3'b000; // blank
else if (bitmap_on) bit_rgb = bitmap_rgb;
else bit_rgb = 3'b110; // yellow background
endmodule
| 8.06692 |
module bitmap_testbench;
reg simul_Clock;
reg simul_reset;
wire simul_hsync;
wire simul_vsync;
wire [3:0] simul_RED;
wire [3:0] simul_GREEN;
wire [3:0] simul_BLUE;
initial begin
simul_Clock = 1'b0;
forever simul_Clock = #1 ~simul_Clock;
end
initial begin
simul_reset = 1'b1;
#100 simul_reset = 1'b0;
end
initial begin
repeat (100) @(negedge simul_Clock);
$finish;
end
always @(negedge simul_Clock)
$strobe(
"%b %b %b #%h%h%h%h%h%h",
simul_Clock,
simul_hsync,
simul_vsync,
simul_RED,
simul_RED,
simul_GREEN,
simul_GREEN,
simul_BLUE,
simul_BLUE
);
test_numbers_top digits (
.Clock(simul_Clock),
.reset(simul_reset),
.hsync(simul_hsync),
.vsync(simul_vsync),
.VGA_R(simul_RED),
.VGA_G(simul_GREEN),
.VGA_B(simul_BLUE)
);
endmodule
| 6.92145 |
module BitMux2_1 (
out,
a,
b,
select
);
output out;
input a, b, select;
reg out;
always @(select or a or b)
case (select)
1'b0: out <= a;
1'b1: out <= b;
default: out <= b;
endcase
endmodule
| 7.642084 |
module bitNegator (
bitIn,
bitN,
bitOut
);
input bitIn, bitN;
output bitOut;
reg bitOut;
always @(bitIn or bitN) begin
if (bitN) begin
bitOut = ~bitIn;
end else begin
bitOut = bitIn;
end
end
endmodule
| 6.935942 |
module BitonicSortX4 #(
parameter DSIZE = 18,
parameter OFFSET = 8
) (
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3
);
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
// half-clean
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(a0),
.b(a2),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(a1),
.b(a3),
.sort0(sort1_0),
.sort1(sort1_1)
);
// divide sort
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sort0_0),
.b(sort1_0),
.sort0(sort0),
.sort1(sort1)
);
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sort0_1),
.b(sort1_1),
.sort0(sort2),
.sort1(sort3)
);
endmodule
| 6.764159 |
module BitonicSortX8 #(
parameter DSIZE = 18,
parameter OFFSET = 8
) (
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7
);
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
// half-clean
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(a0),
.b(a4),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(a1),
.b(a5),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(a2),
.b(a6),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(a3),
.b(a7),
.sort0(sort3_0),
.sort1(sort3_1)
);
// divide sort
BitonicSortX4 #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx4_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.sort0(sort0),
.sort1(sort1),
.sort2(sort2),
.sort3(sort3)
);
BitonicSortX4 #(
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx4_inst1 (
.a0 (sort0_1),
.a1 (sort1_1),
.a2 (sort2_1),
.a3 (sort3_1),
.sort0(sort4),
.sort1(sort5),
.sort2(sort6),
.sort3(sort7)
);
endmodule
| 6.836592 |
module bitonic_block #(
parameter DATA_WIDTH = 16,
parameter ORDER = 0,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire clk,
input wire [DATA_WIDTH*2**(ORDER+1)-1:0] data_in,
output wire [DATA_WIDTH*2**(ORDER+1)-1:0] data_out
);
localparam STAGES = ORDER + 1;
localparam STAGE_DATA_WIDTH = DATA_WIDTH * 2 ** (ORDER + 1);
wire [DATA_WIDTH*2**(ORDER+1)-1:0] stage_data[STAGES:0];
assign stage_data[0] = data_in;
assign data_out = stage_data[STAGES];
genvar stage;
genvar node;
generate
for (stage = 0; stage < STAGES; stage = stage + 1) begin : BLOCK_STAGE
localparam NODES = 2 ** stage;
localparam NODE_ORDER = STAGES - stage - 1;
wire [STAGE_DATA_WIDTH-1:0] stage_data_in;
wire [STAGE_DATA_WIDTH-1:0] stage_data_out;
assign stage_data_in = stage_data[stage];
assign stage_data[stage+1] = stage_data_out;
for (node = 0; node < NODES; node = node + 1) begin : NODE
localparam NODE_DATA_WIDTH = DATA_WIDTH * 2 ** (NODE_ORDER + 1);
wire [NODE_DATA_WIDTH-1:0] node_data_in;
wire [NODE_DATA_WIDTH-1:0] node_data_out;
assign node_data_in = stage_data_in[NODE_DATA_WIDTH*(node+1)-1-:NODE_DATA_WIDTH];
assign stage_data_out[NODE_DATA_WIDTH*(node+1)-1-:NODE_DATA_WIDTH] = node_data_out;
bitonic_node #(
.DATA_WIDTH(DATA_WIDTH),
.ORDER(NODE_ORDER),
.POLARITY(POLARITY),
.SIGNED(SIGNED)
) bitonic_node_inst (
.clk(clk),
.data_in(node_data_in),
.data_out(node_data_out)
);
end
end
endgenerate
endmodule
| 8.129443 |
module bitonic_comp #(
parameter DATA_WIDTH = 16,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire CLK,
input wire [DATA_WIDTH-1:0] A,
input wire [DATA_WIDTH-1:0] B,
output wire [DATA_WIDTH-1:0] H,
output wire [DATA_WIDTH-1:0] L,
output wire O
);
reg [DATA_WIDTH-1:0] H_REG;
reg [DATA_WIDTH-1:0] L_REG;
reg O_REG;
wire LESS;
assign H = H_REG;
assign L = L_REG;
assign O = O_REG;
generate
if (SIGNED == 0) begin
assign LESS = $unsigned(A) < $unsigned(B);
end else begin
assign LESS = $signed(A) < $signed(B);
end
if (POLARITY == 0) begin
always @(posedge CLK) begin
H_REG <= (LESS) ? A : B;
L_REG <= (LESS) ? B : A;
O_REG <= LESS;
end
end else begin
always @(posedge CLK) begin
H_REG <= (LESS) ? B : A;
L_REG <= (LESS) ? A : B;
O_REG <= ~LESS;
end
end
endgenerate
endmodule
| 8.894266 |
module bitonic_merge_tree_5entry (
input clk,
reset,
input [0:`NUM_RIDS * `RIDS_WIDTH - 1] in,
output [0:`RIDS_WIDTH - 1] out
);
//// Merge RIDS #0 and RIDS #1
wire [0:`RIDS_WIDTH - 1] RIDS_0_1; // new RIDS which contains common rule IDs in RIDS #0 and RIDS #1
wire [0:`RIDS_WIDTH - 1] RIDS_0 = in[(0*`RIDS_WIDTH)+:`RIDS_WIDTH];
wire [0:`RIDS_WIDTH - 1] RIDS_1 = in[(1*`RIDS_WIDTH)+:`RIDS_WIDTH];
// We need to inverse RIDS #1 to make {RIDS_0, RIDS_1_r} a bitonic sequence
wire [0:`RIDS_WIDTH - 1] RIDS_1_r;
genvar i;
generate
begin
for (i = 0; i < `NUM_RID; i = i + 1) begin : for_loop_0
assign RIDS_1_r[(i * `RID_WIDTH)+:`RID_WIDTH]
= RIDS_1[((`NUM_RID - 1 - i) * `RID_WIDTH)+:`RID_WIDTH];
end
end
endgenerate
BMNC_bitonic #(
.N(`NUM_RID),
.log_N(`log_NUM_RID),
.elements_width(`RID_WIDTH)
) BMNC_0 (
.clk(clk),
.reset(reset),
.in({RIDS_0, RIDS_1_r}),
.out(RIDS_0_1)
);
//// Merge RIDS #2 and RIDS #3
wire [0:`RIDS_WIDTH - 1] RIDS_2_3; // new RIDS which contains common rule IDs in RIDS #2 and RIDS #3
wire [0:`RIDS_WIDTH - 1] RIDS_2 = in[(2*`RIDS_WIDTH)+:`RIDS_WIDTH];
wire [0:`RIDS_WIDTH - 1] RIDS_3 = in[(3*`RIDS_WIDTH)+:`RIDS_WIDTH];
// We need to inverse RIDS #3 to make {RIDS_2, RIDS_3_r} a bitonic sequence
wire [0:`RIDS_WIDTH - 1] RIDS_3_r;
generate
begin
for (i = 0; i < `NUM_RID; i = i + 1) begin : for_loop_0
assign RIDS_3_r[(i * `RID_WIDTH)+:`RID_WIDTH]
= RIDS_3[((`NUM_RID - 1 - i) * `RID_WIDTH)+:`RID_WIDTH];
end
end
endgenerate
BMNC_bitonic #(
.N(`NUM_RID),
.log_N(`log_NUM_RID),
.elements_width(`RID_WIDTH)
) BMNC_1 (
.clk(clk),
.reset(reset),
.in({RIDS_2, RIDS_3_r}),
.out(RIDS_2_3)
);
//// Merge RIDS_0_1 with RIDS_2_3
wire [0:`RIDS_WIDTH - 1] RIDS_01_23; // new RIDS which contains common rule IDs in RIDS_0_1 and RIDS_2_3
BMNC_random #(
.N(`NUM_RID),
.log_N(`log_NUM_RID),
.elements_width(`RID_WIDTH)
) BMNC_2 (
.clk(clk),
.reset(reset),
.in({RIDS_0_1, RIDS_2_3}),
.out(RIDS_01_23)
);
//// Merge RIDS_01_23 with RIDS #4
wire [0:`RIDS_WIDTH - 1] RIDS_4 = in[(4*`RIDS_WIDTH)+:`RIDS_WIDTH];
BMNC_random #(
.N(`NUM_RID),
.log_N(`log_NUM_RID),
.elements_width(`RID_WIDTH)
) BMNC_3 (
.clk(clk),
.reset(reset),
.in({RIDS_01_23, RIDS_4}),
.out(out)
);
endmodule
| 7.376928 |
module bitonic_merge_tree_scalable #(
parameter M = 256, // # of RIDS need to be merge, M msut be 2 ** (x), x is postive integer
parameter log_M = 8, // log2(M)
parameter RID_WIDTH = 4, // width of RID in each RIDS
parameter NUM_RID = 8, // the number of RID in each RIDS
parameter log_NUM_RID = 3 // log2(NUM_RID)
) (
input clk,
reset, // // positve edge triggering and sync high active reset
input [0:RIDS_WIDTH * M - 1] in,
output [0:RIDS_WIDTH - 1] out
);
localparam RIDS_WIDTH = RID_WIDTH * NUM_RID; // width of rule ID set, RIDS
// First we need to reverse all odd RIDS
wire [0:RIDS_WIDTH - 1] RIDS_r[0:M / 2 - 1];
genvar i, j;
generate
begin
for (i = 0; i < M / 2; i = i + 1) begin : loop_0
for (j = 0; j < NUM_RID; j = j + 1) begin : loop_1
assign RIDS_r[i][(j * RID_WIDTH)+:RID_WIDTH] =
in[((2 * i + 1) * RIDS_WIDTH + (NUM_RID - 1 - j) * RID_WIDTH)+:RID_WIDTH];
end
end
end
endgenerate
wire [0:RIDS_WIDTH * M - 1] wire_array[0:log_M]; // bunch of wire used to connect each two stage
generate
begin
for (i = 0; i < M; i = i + 1) begin : loop_2
if (i % 2 == 0)
assign wire_array[0][(i*RIDS_WIDTH)+:RIDS_WIDTH] = in[(i*RIDS_WIDTH)+:RIDS_WIDTH];
else assign wire_array[0][(i*RIDS_WIDTH)+:RIDS_WIDTH] = RIDS_r[(i-1)/2];
end
end
endgenerate
generate
begin
for (i = 0; i < log_M; i = i + 1) begin : loop_3
for (j = 0; j < M / (2 ** (i + 1)); j = j + 1) begin : loop_4
if (i == 0) begin
BMNC_bitonic #(
.N(NUM_RID),
.log_N(log_NUM_RID),
.elements_width(RID_WIDTH)
) BMNC_b (
.clk(clk),
.reset(reset),
.in(wire_array[i][(j*2*RIDS_WIDTH)+:2*RIDS_WIDTH]),
.out(wire_array[i+1][(j*RIDS_WIDTH)+:RIDS_WIDTH])
);
end else begin
BMNC_random #(
.N(NUM_RID),
.log_N(log_NUM_RID),
.elements_width(RID_WIDTH)
) BMNC_r (
.clk(clk),
.reset(reset),
.in(wire_array[i][(j*2*RIDS_WIDTH)+:2*RIDS_WIDTH]),
.out(wire_array[i+1][(j*RIDS_WIDTH)+:RIDS_WIDTH])
);
end
end
end
end
endgenerate
assign out = wire_array[log_M][0:RIDS_WIDTH-1];
endmodule
| 7.376928 |
module BITONIC_NETWORK_2 #(
parameter DATA_WIDTH = 128,
parameter KEY_WIDTH = 80
) (
input i_clk,
input switch_output,
input stall,
input [DATA_WIDTH-1:0] top_tuple,
input [DATA_WIDTH-1:0] i_elems_0,
input [DATA_WIDTH-1:0] i_elems_1,
output reg [DATA_WIDTH-1:0] o_elems_0,
output reg [DATA_WIDTH-1:0] o_elems_1,
output reg o_switch_output,
output reg o_stall,
output [DATA_WIDTH-1:0] o_top_tuple
);
initial begin
o_stall <= 0;
o_elems_0 <= 0;
o_elems_1 <= 0;
end
assign o_top_tuple = top_tuple;
always @(posedge i_clk) begin
o_stall <= stall;
if (~stall) begin
o_switch_output <= switch_output;
if (i_elems_1[KEY_WIDTH-1:0] >= i_elems_0[KEY_WIDTH-1:0]) begin
o_elems_0 <= i_elems_0;
o_elems_1 <= i_elems_1;
end else begin
o_elems_0 <= i_elems_1;
o_elems_1 <= i_elems_0;
end
end // if (~stall)
end
endmodule
| 7.118922 |
module CAS #(
parameter DATA_WIDTH = 128,
parameter KEY_WIDTH = 80
) (
input i_clk,
input stall,
input [DATA_WIDTH-1:0] i_elems_0,
input [DATA_WIDTH-1:0] i_elems_1,
output reg [DATA_WIDTH-1:0] o_elems_0,
output reg [DATA_WIDTH-1:0] o_elems_1
);
initial begin
o_elems_0 <= 0;
o_elems_1 <= 0;
end
always @(posedge i_clk) begin
if (~stall) begin
if (i_elems_0[KEY_WIDTH-1:0] > i_elems_1[KEY_WIDTH-1:0]) begin
/* switch */
o_elems_1 <= i_elems_0;
o_elems_0 <= i_elems_1;
end else begin
/* stay */
o_elems_1 <= i_elems_1;
o_elems_0 <= i_elems_0;
end
end
end
endmodule
| 8.703018 |
module BITONIC_NETWORK_4 #(
parameter DATA_WIDTH = 128,
parameter KEY_WIDTH = 80
) (
input i_clk,
input switch_output,
input stall,
input [2*DATA_WIDTH-1:0] top_tuple,
input [2*DATA_WIDTH-1:0] i_elems_0,
input [2*DATA_WIDTH-1:0] i_elems_1,
output reg [2*DATA_WIDTH-1:0] o_elems_0,
output reg [2*DATA_WIDTH-1:0] o_elems_1,
output reg o_switch_output,
output reg o_stall,
output reg [2*DATA_WIDTH-1:0] o_top_tuple
);
reg stall_1;
reg switch_output_1;
reg [2*DATA_WIDTH-1:0] elems_1_0;
reg [2*DATA_WIDTH-1:0] elems_1_1;
wire [2*DATA_WIDTH-1:0] top_tuple_1;
assign top_tuple_1 = top_tuple;
initial begin
stall_1 <= 0;
switch_output_1 <= 0;
o_stall <= 0;
elems_1_0 <= 0;
elems_1_1 <= 0;
o_elems_0 <= 0;
o_elems_1 <= 0;
o_switch_output <= 0;
o_top_tuple <= 0;
o_stall <= 0;
end
/* step 1 */
always @(posedge i_clk) begin
stall_1 <= stall;
if (~stall) begin
switch_output_1 <= switch_output;
if (i_elems_1[DATA_WIDTH+KEY_WIDTH-1 : DATA_WIDTH] >= i_elems_0[DATA_WIDTH+KEY_WIDTH-1 : DATA_WIDTH]) begin
elems_1_1[2*DATA_WIDTH-1 : DATA_WIDTH] <= i_elems_1[2*DATA_WIDTH-1 : DATA_WIDTH];
elems_1_0[2*DATA_WIDTH-1 : DATA_WIDTH] <= i_elems_0[2*DATA_WIDTH-1 : DATA_WIDTH];
end else begin
elems_1_1[2*DATA_WIDTH-1 : DATA_WIDTH] <= i_elems_0[2*DATA_WIDTH-1 : DATA_WIDTH];
elems_1_0[2*DATA_WIDTH-1 : DATA_WIDTH] <= i_elems_1[2*DATA_WIDTH-1 : DATA_WIDTH];
end
if (i_elems_1[KEY_WIDTH-1:0] >= i_elems_0[KEY_WIDTH-1:0]) begin
elems_1_1[DATA_WIDTH-1:0] <= i_elems_1[DATA_WIDTH-1:0];
elems_1_0[DATA_WIDTH-1:0] <= i_elems_0[DATA_WIDTH-1:0];
end else begin
elems_1_1[DATA_WIDTH-1:0] <= i_elems_0[DATA_WIDTH-1:0];
elems_1_0[DATA_WIDTH-1:0] <= i_elems_1[DATA_WIDTH-1:0];
end
end // if (~stall)
end
/* step 2 */
always @(posedge i_clk) begin
o_stall <= stall_1;
if (~stall_1) begin
o_switch_output <= switch_output_1;
o_top_tuple <= top_tuple_1;
o_elems_1[2*DATA_WIDTH-1 : DATA_WIDTH] <= elems_1_1[2*DATA_WIDTH-1 : DATA_WIDTH];
o_elems_0[DATA_WIDTH-1:0] <= elems_1_0[DATA_WIDTH-1:0];
if (elems_1_0[DATA_WIDTH+KEY_WIDTH-1 : DATA_WIDTH] >= elems_1_1[KEY_WIDTH-1:0]) begin
o_elems_1[DATA_WIDTH-1:0] <= elems_1_0[2*DATA_WIDTH-1 : DATA_WIDTH];
o_elems_0[2*DATA_WIDTH-1 : DATA_WIDTH] <= elems_1_1[DATA_WIDTH-1:0];
end else begin
o_elems_1[DATA_WIDTH-1:0] <= elems_1_1[DATA_WIDTH-1:0];
o_elems_0[2*DATA_WIDTH-1 : DATA_WIDTH] <= elems_1_0[2*DATA_WIDTH-1 : DATA_WIDTH];
end
end
end
endmodule
| 7.118922 |
module bitonic_node #(
parameter DATA_WIDTH = 16,
parameter ORDER = 0,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire clk,
input wire [DATA_WIDTH*2**(ORDER+1)-1:0] data_in,
output wire [DATA_WIDTH*2**(ORDER+1)-1:0] data_out
);
localparam COMP_NUM = 2 ** ORDER;
genvar i;
generate
for (i = 0; i < COMP_NUM; i = i + 1) begin : COMP
wire [DATA_WIDTH-1:0] A;
wire [DATA_WIDTH-1:0] B;
wire [DATA_WIDTH-1:0] H;
wire [DATA_WIDTH-1:0] L;
assign A = data_in[DATA_WIDTH*(i+1+COMP_NUM*0)-1-:DATA_WIDTH];
assign B = data_in[DATA_WIDTH*(i+1+COMP_NUM*1)-1-:DATA_WIDTH];
assign data_out[DATA_WIDTH*(i+1+COMP_NUM*0)-1-:DATA_WIDTH] = H;
assign data_out[DATA_WIDTH*(i+1+COMP_NUM*1)-1-:DATA_WIDTH] = L;
bitonic_comp #(
.DATA_WIDTH(DATA_WIDTH),
.POLARITY(POLARITY),
.SIGNED(SIGNED)
) comp_inst (
.CLK(clk),
.A (A),
.B (B),
.H (H),
.L (L)
);
end
endgenerate
endmodule
| 8.346627 |
module compare_swap #(
parameter W = 2
) (
a1,
a2,
dir,
o1,
o2
);
input [W-1:0] a1, a2;
input dir; // dir = 1 -> ascending
output [W-1:0] o1, o2;
wire comp;
wire isCorrect;
COMP #(
.N(W)
) COMP_ (
.A(a1),
.B(a2),
.O(comp)
);
assign isCorrect = (dir == 1 & comp == 1) | (dir == 0 & comp == 0);
MUX #(
.N(W)
) MUX_o1 (
.A(a2),
.B(a1),
.S(isCorrect),
.O(o1)
);
MUX #(
.N(W)
) MUX_o2 (
.A(a1),
.B(a2),
.S(isCorrect),
.O(o2)
);
endmodule
| 7.27735 |
module bitonic_merge #(
parameter W = 2,
parameter K = 3
) (
in_array,
dir,
out_array
);
input [W*K-1:0] in_array;
input dir;
output [W*K-1:0] out_array;
wire [W-1:0] in_mat[K-1:0];
wire [W-1:0] out_interm_mat[K-1:0];
wire [W*K-1:0] out_interm_array;
wire [W*K-1:0] out_merge;
localparam lo = 0;
genvar i;
generate
for (i = K - 1; i >= 0; i = i - 1) begin
assign in_mat[i] = in_array[(i+1)*W-1:i*W];
assign out_interm_array[(i+1)*W-1:i*W] = out_interm_mat[i];
end
endgenerate
generate
if (K > 1) begin
localparam k = K / 2;
for (i = lo; i < lo + k; i = i + 1) begin
compare_swap #(
.W(W)
) compare_swap_ (
.a1 (in_mat[i]),
.a2 (in_mat[i+k]),
.dir(dir),
.o1 (out_interm_mat[i]),
.o2 (out_interm_mat[i+k])
);
end
bitonic_merge #(
.W(W),
.K(k)
) bitonic_merge_1 (
.in_array(out_interm_array[(lo+k)*W-1:lo*W]),
.dir(dir),
.out_array(out_merge[(lo+k)*W-1:lo*W])
);
bitonic_merge #(
.W(W),
.K(k)
) bitonic_merge_2 (
.in_array(out_interm_array[(lo+2*k)*W-1:(lo+k)*W]),
.dir(dir),
.out_array(out_merge[(lo+2*k)*W-1:(lo+k)*W])
);
end
endgenerate
assign out_array = (K > 1) ? out_merge : in_array;
endmodule
| 7.376928 |
module bitonic_sort #(
parameter W = 2,
parameter K = 2
) (
in_array,
dir,
out_array
);
input [W*K-1:0] in_array;
input dir;
output [W*K-1:0] out_array;
wire [W*K-1:0] out_sort;
wire [W*K-1:0] out_merge;
localparam lo = 0;
genvar i;
generate
if (K > 1) begin
localparam k = K / 2;
bitonic_sort #(
.W(W),
.K(k)
) bitonic_sort_1 (
.in_array(in_array[(lo+k)*W-1:lo*W]),
.dir(1'b1),
.out_array(out_sort[(lo+k)*W-1:lo*W])
);
bitonic_sort #(
.W(W),
.K(k)
) bitonic_sort_2 (
.in_array(in_array[(lo+2*k)*W-1:(lo+k)*W]),
.dir(1'b0),
.out_array(out_sort[(lo+2*k)*W-1:(lo+k)*W])
);
bitonic_merge #(
.W(W),
.K(K)
) bitonic_merge_ (
.in_array(out_sort),
.dir(dir),
.out_array(out_merge)
);
end
endgenerate
assign out_array = (K > 1) ? out_merge : in_array;
endmodule
| 8.005591 |
module bitonic_sorter_orange #(
parameter SINGLE_WAY_WIDTH_IN_BITS = 32,
parameter NUM_WAY = 16 // must be a power of 2
) (
input [SINGLE_WAY_WIDTH_IN_BITS * NUM_WAY - 1 : 0] pre_sort_flatted_in,
output [SINGLE_WAY_WIDTH_IN_BITS * NUM_WAY - 1 : 0] post_sort_flatted_out
);
generate
genvar gen;
for (gen = 0; gen < NUM_WAY / 2; gen = gen + 1) begin
assign post_sort_flatted_out[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] =
(pre_sort_flatted_in[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] <
pre_sort_flatted_in[(NUM_WAY - gen - 1) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS]) ?
pre_sort_flatted_in[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] :
pre_sort_flatted_in[(NUM_WAY - gen - 1) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS];
assign post_sort_flatted_out[(NUM_WAY - gen - 1) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] =
(pre_sort_flatted_in[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] >
pre_sort_flatted_in[(NUM_WAY - gen - 1) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS]) ?
pre_sort_flatted_in[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] :
pre_sort_flatted_in[(NUM_WAY - gen - 1) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS];
end
endgenerate
endmodule
| 6.650761 |
module bitonic_sorter_pink #(
parameter SINGLE_WAY_WIDTH_IN_BITS = 32,
parameter NUM_WAY = 16 // must be a power of 2
) (
input [SINGLE_WAY_WIDTH_IN_BITS * NUM_WAY - 1 : 0] pre_sort_flatted_in,
output [SINGLE_WAY_WIDTH_IN_BITS * NUM_WAY - 1 : 0] post_sort_flatted_out
);
parameter NUM_WAY_HALF = NUM_WAY / 2;
generate
genvar gen;
for (gen = 0; gen < NUM_WAY_HALF; gen = gen + 1) begin
assign post_sort_flatted_out[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] =
(pre_sort_flatted_in[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] <
pre_sort_flatted_in[(gen + NUM_WAY_HALF) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS]) ?
pre_sort_flatted_in[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] :
pre_sort_flatted_in[(gen + NUM_WAY_HALF) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS];
assign post_sort_flatted_out[(gen + NUM_WAY_HALF) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] =
(pre_sort_flatted_in[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] >
pre_sort_flatted_in[(gen + NUM_WAY_HALF) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS]) ?
pre_sort_flatted_in[gen * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS] :
pre_sort_flatted_in[(gen + NUM_WAY_HALF) * SINGLE_WAY_WIDTH_IN_BITS +: SINGLE_WAY_WIDTH_IN_BITS];
end
endgenerate
endmodule
| 6.650761 |
module bitonic_sorting_recursion #(
parameter LOG_INPUT_NUM = 4, // Eg: If LOG_INPUT_NUM=4, then input number is 2**4=16
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = LOG_INPUT_NUM,
parameter SIGNED = 0,
parameter ASCENDING = 1
) (
input clk,
rst,
x_valid,
// Put all the inputs into one vector.
// x[DATA_WIDTH-1 : 0] is the first input x_0,
// x[DATA_WIDTH*2-1 : DATA_WIDTH] is the second input x_1, etc.
input [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x,
input [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x_label,
output [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y,
output [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y_label,
output y_valid
);
if (LOG_INPUT_NUM > 1) begin
// Declare the wires which come out of the 2 2**(n-1)-input comparators with opposite ascending feature.
wire [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1:0] stage0_labl;
wire stage0_valid;
// Stage 1, use two 2**(n-1)-input comparators with opposite ascending features to sort.
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the opposite ascending feature with the entire network output.
bitonic_sorting_recursion #(
.LOG_INPUT_NUM(LOG_INPUT_NUM - 1),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
) inst_stage0_0 (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x(x[DATA_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.x_label(x_label[LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y(stage0_rslt[DATA_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y_label(stage0_labl[LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y_valid(stage0_valid)
);
bitonic_sorting_recursion #(
.LOG_INPUT_NUM(LOG_INPUT_NUM - 1),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(1 - ASCENDING)
) inst_stage0_1 (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x(x[DATA_WIDTH*(2**LOG_INPUT_NUM)-1:DATA_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.x_label(x_label[LABEL_WIDTH*(2**LOG_INPUT_NUM)-1:LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y(stage0_rslt[DATA_WIDTH*(2**LOG_INPUT_NUM)-1:DATA_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y_label(stage0_labl[LABEL_WIDTH*(2**LOG_INPUT_NUM)-1:LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y_valid()
);
// Stage 2, use a 2**n-input bitonic submodule to sort the outputs of the stage 1.
// bitonic_sorting_resursion_submodule should have the same ascending feature with the entire network output.
bitonic_sorting_recursion_submodule #(
.LOG_INPUT_NUM(LOG_INPUT_NUM),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
) inst_stage1 (
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x(stage0_rslt),
.x_label(stage0_labl),
.y(y),
.y_label(y_label),
.y_valid(y_valid)
);
end else if (LOG_INPUT_NUM == 1) begin
input_2 #(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
) input_2_stage0_1 (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x[DATA_WIDTH-1:0]),
.x_1(x[DATA_WIDTH*2-1:DATA_WIDTH]),
.x_label_0(x_label[LABEL_WIDTH-1:0]),
.x_label_1(x_label[LABEL_WIDTH*2-1:LABEL_WIDTH]),
.y_0(y[DATA_WIDTH-1:0]),
.y_1(y[DATA_WIDTH*2-1:DATA_WIDTH]),
.y_label_0(y_label[LABEL_WIDTH-1:0]),
.y_label_1(y_label[LABEL_WIDTH*2-1:LABEL_WIDTH]),
.y_valid(y_valid)
);
end
endmodule
| 7.049537 |
module bitonic_sorting_top #(
parameter LOG_INPUT_NUM = 4, // Eg: If LOG_INPUT_NUM=4, then input number is 2**4=16
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = LOG_INPUT_NUM,
parameter SIGNED = 0,
parameter ASCENDING = 1
) (
input clk,
rst,
x_valid,
// Put all the inputs into one vector.
// x[DATA_WIDTH-1 : 0] is the first input x_0,
// x[DATA_WIDTH*2-1 : DATA_WIDTH] is the second input x_1, etc.
input [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x,
input [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x_label,
output [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y,
output [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y_label,
output y_valid
);
bitonic_sorting_recursion #(
.LOG_INPUT_NUM(LOG_INPUT_NUM),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
) bitonic_sorting_inst (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x(x),
.x_label(x_label),
.y(y),
.y_label(y_label),
.y_valid(y_valid)
);
endmodule
| 7.049537 |
module bitops_get_hi (
in,
out
);
parameter width = 8;
input wire [(width-1):0] in;
output wire [(width-1):0] out;
wire [(width-1):0] r_data;
bitops_get_hilo_abf gen0_abfh (
.r(0),
.a(in[width-1]),
.out(out[width-1]),
.out_r(r_data[width-1])
);
genvar gi;
generate
for (gi = 1; gi < width; gi = gi + 1) begin : bl_generation_h
bitops_get_hilo_abf gen_abf (
.a(in[width-1-gi]),
.r(r_data[width-gi]),
.out(out[width-1-gi]),
.out_r(r_data[width-1-gi])
);
end
endgenerate
endmodule
| 7.814454 |
module bitops_get_hilo_abf (
a,
r,
out,
out_r
);
input wire a, r;
output wire out, out_r;
assign out = (~r) && a; //out = (r==0) ? a : 0;
assign out_r = r || a; //(r==1)||(a==1);
endmodule
| 7.814454 |
module bitops_get_lo (
in,
out
);
parameter width = 8;
input wire [(width-1):0] in;
output wire [(width-1):0] out;
wire [(width-1):0] r_data;
bitops_get_hilo_abf gen0_abf (
.r(0),
.a(in[0]),
.out(out[0]),
.out_r(r_data[0])
);
genvar gi;
generate
for (gi = 1; gi < width; gi = gi + 1) begin : bl_generation
bitops_get_hilo_abf gen_abf (
.a(in[gi]),
.r(r_data[gi-1]),
.out(out[gi]),
.out_r(r_data[gi])
);
end
endgenerate
endmodule
| 6.986425 |
module Bitparidad (
input [2:0] A,
input [2:0] B,
output BP
);
wire BG;
assign BG = A[2] ^ A[1] ^ A[0] ^ B[2] ^ B[1] ^ B[0];
assign BP = BG;
endmodule
| 8.033985 |
module playfields (
input [6:1] bpldata, //raw bitplane data in
input dblpf, //double playfield select
input [6:0] bplcon2, //bplcon2 (playfields priority)
output reg [2:1] nplayfield, //playfield 1,2 valid data
output reg [5:0] plfdata //playfield data out
);
//local signals
wire pf2pri; //playfield 2 priority over playfield 1
wire [2:0] pf2p; //playfield 2 priority code
assign pf2pri = bplcon2[6];
assign pf2p = bplcon2[5:3];
//generate playfield 1,2 data valid signals
always @(dblpf or bpldata) begin
if (dblpf) //dual playfield
begin
if (bpldata[5] || bpldata[3] || bpldata[1]) //detect data valid for playfield 1
nplayfield[1] = 1;
else nplayfield[1] = 0;
if (bpldata[6] || bpldata[4] || bpldata[2]) //detect data valid for playfield 2
nplayfield[2] = 1;
else nplayfield[2] = 0;
end else //single playfield is always playfield 2
begin
nplayfield[1] = 0;
if (bpldata[6:1] != 6'b000000) nplayfield[2] = 1;
else nplayfield[2] = 0;
end
end
//--------------------------------------------------------------------------------------
//playfield 1 and 2 priority logic
always @(nplayfield or dblpf or pf2pri or bpldata or pf2p) begin
if (dblpf) //dual playfield
begin
if (pf2pri) //playfield 2 (2,4,6) has priority
begin
if (nplayfield[2]) plfdata[5:0] = {3'b001, bpldata[6], bpldata[4], bpldata[2]};
else if (nplayfield[1]) plfdata[5:0] = {3'b000, bpldata[5], bpldata[3], bpldata[1]};
else //both planes transparant, select background color
plfdata[5:0] = 6'b000000;
end else //playfield 1 (1,3,5) has priority
begin
if (nplayfield[1]) plfdata[5:0] = {3'b000, bpldata[5], bpldata[3], bpldata[1]};
else if (nplayfield[2]) plfdata[5:0] = {3'b001, bpldata[6], bpldata[4], bpldata[2]};
else //both planes transparant, select background color
plfdata[5:0] = 6'b000000;
end
end else //normal single playfield (playfield 2 only)
//OCS/ECS undocumented feature when bpu=5 and pf2pri>5 (Swiv score display)
if (pf2p > 5 && bpldata[5])
plfdata[5:0] = {6'b010000};
else plfdata[5:0] = bpldata[6:1];
end
//--------------------------------------------------------------------------------------
endmodule
| 7.872049 |
module bitplane_shifter (
input clk28m, //35ns pixel clock
input c1,
input c3,
input load, //load shift register
input hires, //high resolution select
input shres, //super high resolution select (takes priority over hires)
input [15:0] data_in, //parallel load data input
input [ 3:0] scroll, //scrolling value
output out //shift register out
);
//local signals
reg [15:0] shifter; //main shifter
reg [15:0] scroller; //scroller shifter
reg shift; //shifter enable
reg [3:0] select; //delayed pixel select
wire scroller_out;
reg [3:0] delay;
//--------------------------------------------------------------------------------------
//main shifter
always @(posedge clk28m)
if (load && !c1 && !c3) //load new data into shifter
shifter[15:0] <= data_in[15:0];
else if (shift) //shift already loaded data
shifter[15:0] <= {shifter[14:0], 1'b0};
always @(posedge clk28m)
if (shift) //shift scroller data
scroller[15:0] <= {scroller[14:0], shifter[15]};
assign scroller_out = scroller[select[3:0]]; //select odd pixel
//--------------------------------------------------------------------------------------
//delay by one low resolution pixel
always @(posedge clk28m) delay[3:0] <= {delay[2:0], scroller_out};
// select output pixel
assign out = delay[3];
//--------------------------------------------------------------------------------------
// main shifter and scroller control
always @(hires or shres or scroll or c1 or c3)
if (shres) // super hires mode
begin
shift = 1'b1; // shifter always enabled
select[3:0] = {scroll[1:0], 2'b11}; // scroll in 4 pixel steps
end
else if (hires) // hires mode
begin
shift = ~c1 ^ c3; // shifter enabled every other clock cycle
select[3:0] = {scroll[2:0], 1'b1}; // scroll in 2 pixel steps
end else // lowres mode
begin
shift = ~c1 & ~c3; // shifter enabled once every 4 clock cycles
select[3:0] = scroll[3:0]; // scroll in 1 pixel steps
end
endmodule
| 6.99515 |
module a_bitRegester_tb;
reg p, d, c, r, l;
wire q1, q2;
bit_regester b (
q1,
q2,
p,
d,
l,
c,
r
);
initial begin
p = 'b1;
#5 l = 'b1;
#5 d = 'b1;
r = 'b1;
#5 c = 'b1;
#5 c = 'b0;
#5 #5 golden(q1, 'b1, l, d, r);
end
task golden;
input result, expected, l, d, r;
begin
$write("l:%d d:%d r:%d= Exp-q:%d and Act-q:%d", l, p, r, expected, result);
if (result == expected) begin
$write("[PASSED]");
end else begin
$write("[FAILED]");
end
$write("\n");
$write("Ran bitReg TB\n");
end
endtask
endmodule
| 6.539908 |
module a_bitRegesterB_tb;
reg p, d, c, r, l;
wire q1, q2;
bit_regester b (
q1,
q2,
p,
d,
l,
c,
r
);
initial begin
p = 'b1;
#5 l = 'b0;
#5 d = 'b1;
r = 'b0;
#5 c = 'b1;
#5 c = 'b0;
#5 golden(q1, 'b0, l, d, r);
#5 l = 'b1;
#5 d = 'b1;
r = 'b1;
#5 c = 'b1;
#5 c = 'b0;
#5 golden(q1, 'b1, l, d, r);
#5 l = 'b0;
#5 d = 'b0;
r = 'b1;
#5 c = 'b1;
#5 c = 'b0;
#5 golden(q1, 'b1, l, d, r);
end
task golden;
input result, expected, l, d, r;
begin
$write("l:%d d:%d r:%d= Exp-q:%d and Act-q:%d", l, p, r, expected, result);
if (result == expected) begin
$write("[PASSED]");
end else begin
$write("[FAILED]");
end
$write("\n");
$write("Ran bitReg TB\n");
end
endtask
endmodule
| 6.539908 |
module bitRevOrderSM (
Clk,
start,
reset,
DinA,
DinB,
write_enableA,
write_enableB,
addrA,
addrB,
DoutA,
DoutB,
tc
);
input Clk, start, reset;
input [17:0] DinA, DinB;
output reg write_enableA, write_enableB;
output [9:0] addrA, addrB;
output [17:0] DoutA, DoutB;
output tc;
reg [8:0] addr;
reg [3:0] state;
localparam INITIAL = 4'b0001, C1DELAY = 4'b0010, RDATA = 4'b0100, DONE = 4'b1000;
bitRevRam brRam (
.Clk (Clk),
.addr (addr),
.DoutA(addrA),
.DoutB(addrB)
);
assign DoutB = DinA;
assign DoutA = DinB;
assign tc = addr[8] & addr[7] & addr[6] & addr[5] & addr[4] & ~addr[3] & ~addr[2] & ~addr[1] & ~addr[0];
always @(posedge Clk) begin
if (reset) begin
state <= INITIAL;
addr <= 9'bxxxxxxxxx;
write_enableA <= 1'bx;
write_enableB <= 1'bx;
end
case (state)
INITIAL: begin
// State transitions
if (start) state <= C1DELAY;
// RTL Statements
addr <= 9'b000000000;
write_enableA <= 0;
write_enableB <= 0;
end
C1DELAY: begin
// State transitions
state <= RDATA;
// RTL Statements
write_enableA <= 1;
write_enableB <= 1;
end
RDATA: begin
// State transitions and RTL
if (tc) begin
state <= DONE;
end else begin
state <= RDATA;
addr <= addr + 1;
end
end
DONE: begin
// State transitions
state <= INITIAL;
// RTL Statements
write_enableA <= 0;
write_enableB <= 0;
end
endcase
end
endmodule
| 6.987238 |
module: bitRevRam
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bitRevRam_tb;
parameter HALF_PERIOD = 5;
// Inputs
reg Clk;
reg [8:0] addr;
// Outputs
wire [9:0] DoutA;
wire [9:0] DoutB;
// Instantiate the Unit Under Test (UUT)
bitRevRam uut (
.Clk(Clk),
.addr(addr),
.DoutA(DoutA),
.DoutB(DoutB)
);
initial begin : CLK_GENERATOR
Clk = 0;
forever begin
#HALF_PERIOD Clk = ~Clk;
end
end
initial begin
// Initialize Inputs
Clk = 0;
addr = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
addr = 5;
#10
addr = 10;
#10
addr = 15;
#10
addr = 20;
#10
addr = 500;
end
endmodule
| 6.722992 |
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