code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module fa (
input a,
b,
c,
output s,
cout
);
wire w1, w2, w3;
xor (s, a, b, c);
and (w1, a, b);
xor (w2, a, b);
and (w3, w2, c);
or (cout, w3, w1);
endmodule
| 7.001699 |
module bit4 (
input [3:0] inp1,
input [3:0] inp2,
output [7:0] outp
);
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15;
wire d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16, d17, d18;
and a1 (outp[0], inp1[0], inp2[0]);
and a2 (w15, inp1[1], inp2[0]);
... | 6.541464 |
module fabit8 (
input [7:0] inp1,
input [7:0] inp2,
input cin,
output [7:0] outp,
output cout
);
wire w1;
fabit4 fa1 (
inp1[3:0],
inp2[3:0],
cin,
outp[3:0],
w1
);
fabit4 fa2 (
inp1[7:4],
inp2[7:4],
w1,
outp[7:4],
cout
);
endmodule... | 7.503689 |
module bit8 (
input [ 7:0] inp1,
input [ 7:0] inp2,
output [15:0] outp
);
wire [7:0] w1;
wire [7:0] w2;
wire [7:0] w3;
wire [7:0] w4;
wire [7:0] w5;
wire [7:0] w6;
wire [7:0] w7;
wire w8, w9, w10, w11, w12;
bit4 mul1 (
inp1[3:0],
inp2[3:0],
w1
);
bit4 mul2 (
i... | 7.211629 |
module mux8 (
s,
a,
b,
c,
d,
e,
f,
g,
h,
out
);
input [2:0] s;
input a, b, c, d, e, f, g, h;
output out;
bufif1 b1 (out, a, ((~s[0]) & (~s[1]) & (~s[2])));
bufif1 b2 (out, b, ((s[0]) & (~s[1]) & (~s[2])));
bufif1 b3 (out, c, ((~s[0]) & (s[1]) & (~s[2])));
bufif1 b4 ... | 6.942993 |
module bit8alu (
input [7:0] a,
input [7:0] b,
input [2:0] s,
output [7:0] acc,
output [7:0] mulh,
output [7:0] flag
);
wire [7:0] ands;
wire [7:0] orrs;
wire [7:0] nots;
wire [7:0] lsl;
wire [7:0] lsr;
wire [7:0] add;
wire [7:0] sub;
wire [7:0] mul;
wire [7:0] mulhw;
wi... | 6.618196 |
module bit8to128 (
input wire sclk,
input wire rst,
input wire rx_flag,
input wire [ 7:0] rx_data,
output wire wr_en,
output wire [127:0] wr_data
);
parameter BURST_LEN = 64;
reg [15:0] shift_reg;
reg rx_cnt = 0;
reg wr_fifo_en;
wire [15:0] wr_fifo_... | 8.060585 |
module bit8_2to1mux (
out,
sel,
in1,
in2
);
input [7:0] in1, in2;
output [7:0] out;
input sel;
genvar j;
generate
for (j = 0; j < 8; j = j + 1) begin : mux_loop
mux2to1 m1 (
out[j],
sel,
in1[j],
in2[j]
);
end
endgenerate
endmodule... | 6.846916 |
module bit8_3to1mux (
out,
sel1,
sel2,
in1,
in2,
in3
);
input [7:0] in1, in2, in3;
output [7:0] out;
input sel1, sel2;
genvar j;
//this is the variable that is be used in the generate
generate
for (j = 0; j < 8; j = j + 1) begin : mux_loop //mux_loop is the name of the loop
... | 6.929733 |
module bitadd (
A,
B,
CI,
Y,
C
); // add all inputs and outputs inside parentheses
// inputs
input A;
input B;
input CI;
// outputs
output reg Y;
output reg C;
// reg and internal variable definitions
// implement module here
always @(*) begin
if (A & B) begin
C <=... | 7.177831 |
module BITADD8 (
input [7:0] d,
output [3:0] q
);
assign q = d[0] + d[1] + d[2] + d[3] + d[4] + d[5] + d[6] + d[7];
endmodule
| 6.717507 |
module FullAdder (
input wire a,
input wire b,
input wire cin,
output wire s,
output wire cout
);
wire sha, cha1, cha2;
HalfAdder ha1 (
cin,
a,
sha,
cha1
);
HalfAdder ha2 (
sha,
b,
s,
cha2
);
assign cout = cha1 | cha2;
endmodule
| 7.610141 |
module BitAdder #(
parameter BUS_WIDTH = 8
) (
input wire [BUS_WIDTH-1:0] a,
input wire [BUS_WIDTH-1:0] b,
input wire substract,
output wire [BUS_WIDTH-1:0] out,
output wire carry
);
wire [BUS_WIDTH:0] c;
assign c[0] = substract;
assign carry = c[BUS_WIDTH];
generate
genvar i;
... | 9.440111 |
module bitap (
// Control registers stuff
input control_regs_clock,
input control_regs_we,
input [0:0] control_regs_addr,
input [31:0] control_regs_data_in,
output reg [31:0] control_regs_data_out,
// Memory for haystack
output haystack_mem_clock,
output [15:0] haystack_mem_addr,
... | 6.758748 |
module BitArrayGetterModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire [7:0] Value,
output wire [7:0] Getter
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;... | 6.935302 |
module bitbang (
s_clk,
s_data,
strobe,
data,
active,
clk
);
localparam on_pattern = 16'hFAB1;
localparam off_pattern = 16'hFAB0;
input s_clk;
input s_data;
output reg strobe;
output reg [31:0] data;
output reg active = 1'b0;
input clk;
reg [3:0] s_data_sample;
reg [3:0] s_c... | 8.223262 |
module io_pad (
input wire in_dir,
input wire in_outval,
inout wire pin
);
assign pin = in_dir ? in_outval : 'bz;
endmodule
| 8.822936 |
module bitbang_ctrl #(
parameter IO_NUM_OF = 10
) ( // i.f. to the controller interface
input wire [IO_NUM_OF - 1 : 0] in_io_direction,
input wire [IO_NUM_OF - 1 : 0] in_io_outval,
// i.f. to the IO pad
inout wire [IO_NUM_OF - 1 : 0] io_pins
);
io_pad io_pads_set[IO_NUM_OF - 1 : 0] (
in_io... | 8.513454 |
module bitblock_1 (
clk,
rstn,
in,
ppi,
cci,
yi,
yo,
ppo,
psum,
ci,
co,
out
);
input clk;
input rstn;
input [4:0] in;
input ppi;
input cci;
input [3:0] yi;
output [3:0] yo;
output ppo;
input psum;
input ci;
output co;
output out;
wire [1:0] cpr... | 6.893755 |
module bitblock_4_core (
clk,
rstn,
in,
shift,
shift_r1,
ppi,
ci,
yi,
yo,
ppo,
psum,
out,
co
);
input clk;
input rstn;
input [19:0] in;
input shift;
input shift_r1;
input ppi;
input ci;
input [3:0] yi;
output [3:0] yo;
output [3:0] ppo;
input [... | 8.495237 |
module bitbrick (
input [1:0] x,
input s_x,
input [1:0] y,
input s_y,
input [2:0] shift,
output [9:0] prod
);
/* ORIGINAL VERSION */
/*wire [2:0] x1, y1;
wire ha0_co;
wire fa0_sum, fa0_co;
wire ha1_co;
wire fa1_sum, fa1_co;
wire ha2_co;
wire [5:0] p;
wire fa2_su... | 6.524565 |
module bitbrick_testbench ();
reg [2:0] x;
reg [2:0] y;
wire [9:0] p;
integer i;
integer j;
integer a;
bitbrick bitbrick0 (
.x(x[1:0]),
.s_x(x[2]),
.y(y[1:0]),
.s_y(y[2]),
.shift(0),
.prod(p)
);
initial begin
//$vcdpluson;
`ifdef IVERILOG
$dumpfile("bitbri... | 6.663228 |
module BitClock (
input clk,
output pair2,
output pair1,
output pair0,
output pairCLK,
output LED_indicator
);
fast_clock u1 (
.inclk0(clk),
.c0(bit_clock_out)
);
reg [23:0] cnt;
reg out_clock;
reg [3:0] slot = 6;
reg dataEnable = 1'b0;
reg vsync = 1'b0;
reg hs... | 7.99598 |
module BitClock (
input clk,
output pair2,
output pair1,
output pair0,
output pairCLK,
output LED_indicator
);
fast_clock u1 (
.inclk0(clk),
.c0(bit_clock_out)
);
reg [23:0] cnt;
reg out_clock;
reg [3:0] slot = 6;
reg dataEnable = 1'b0;
reg vsync = 1'b0;
reg hs... | 7.99598 |
module bitcnt_bits_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
addr5,
ce5,
q5,
addr6,
ce6,
q6,
addr7,
ce7,
q7,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 8;
parameter... | 7.228928 |
module bitcnt_bits (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4,
address5,
ce5,
q5,
address6,
ce6,
q6,
address7,
ce7,
q7
);
parameter DataWidth = 32'd... | 6.605695 |
module bitcoin_miner (
input wire clk,
input wire start,
input wire [255:0] first_block_hash,
input wire [127:0] second_block,
input wire [255:0] target,
input wire [31:0] max_nonce,
output reg running,
output reg found,
reg [31:0] nonce
);
localparam BLOCKSIZE = 512;
localparam... | 6.631865 |
module bitcoin_miner_ip_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 7
) (
// Users to... | 6.631865 |
module BitComparator (
DataA,
DataB,
A_EQ_B,
A_GT_B,
A_LT_B
);
/***************************************************************************
** Here all module parameters are defined with a dummy value **
*************************************************************************... | 7.270264 |
module bitCounter8 (
KEY,
SW,
HEX0,
HEX1
);
input [3:0] KEY;
input [1:0] SW;
output [6:0] HEX0, HEX1;
wire [7:0] w1;
tFF8bit u0 (
SW[1],
w1,
KEY[0],
SW[0]
);
hexDisplay u1 (
w1,
HEX0,
HEX1
);
endmodule
| 8.618239 |
module bitcount (
B,
count
);
input [7:0] B;
output [3:0] count;
integer k;
reg [3:0] count;
always @(B) begin
count = 0;
for (k = 0; k <= 7; k = k + 1) count = count + B[k];
end
endmodule
| 6.668737 |
module halfadd_tb;
reg [7:0] halfadd_input;
wire [3:0] out_sum;
integer k;
mainmod BC (
.halfadd_input(halfadd_input),
.out_sum(out_sum)
);
initial begin
halfadd_input = 8'b0000_0000;
for (k = 0; k <= 256; k = k + 1) begin
halfadd_input = k;
#5 $display("Input: %b, Bitcount... | 6.897753 |
module BitDdr (
input reset,
input clkin,
input din_p,
input din_n,
output dout
);
reg reset_i = 1'b0;
reg pflag = 1'b0;
reg nflag = 1'b0;
reg din_p_reg = 1'b0;
reg din_n_reg_i = 1'b0;
reg din_n_reg = 1'b0;
wire dout_p, dout_n;
always @(posedge clkin) reset_i <= reset;
alway... | 7.28625 |
module dp_analog_mappings (
input wire [1:0] vod,
input wire [1:0] pree,
output reg [4:0] out_vod,
output reg [5:0] out_pree_post_tap1 // bit5 is polarity, 1=neg 2=pos
);
always @(*)
case (vod)
2'b00 : // 400mv
begin
case (pree)
2'b00 : // (0db)
begin
... | 6.885853 |
module bitEncoder (
noise,
messageBit,
r_out
);
input wire [31:0] noise;
input wire messageBit;
output reg [7:0] r_out;
reg [7:0] dataStruct;
reg [7:0] noiseTemp;
always @(messageBit) begin
case (messageBit)
0: dataStruct = 10010000;
1: dataStruct = 00010000;
endcase
... | 6.87871 |
module BitError (
clk,
reset,
din,
dout
);
input clk;
input reset;
input [1:0] din;
output [1:0] dout;
parameter Le = 11;
reg [1:0] dout_reg;
reg [4:0] cnt;
reg flag;
always @(posedge clk or negedge reset) begin
if (!reset) begin
cnt <= 0;
flag <= 0;
end else be... | 6.840476 |
module biterrordetect2 (
input wire clock,
input wire bitin, // vergleich 1
input wire bitout, // vergleich 2
input wire activ, // synchron neg. clock
input wire reset, // synchron neg. clock
output wire biterror // ergebnis
);
//tmrg default triplicate
//tmrg tmr_error fal... | 7.185164 |
module BITEXPAND (
input [31:0] inData,
output [63:0] outData
);
/*
* module to expand a 2's complement data from 32bits to 64bits
* input:
* 32 bit data input
* output:
* 64 bit sign preserved data
*/
assign outData[31:0] = inData[31:0];
assign outData[63:32] = inData[31] ? 32'hFFFFFFFF : 32'... | 8.844956 |
module bitExtension (
in,
out
);
input [0:15] in;
output reg [0:29] out;
always @(in) begin
if (in[0] == 1) begin
out = {14'b11111111111111, in};
end else begin
out = in;
end
end
endmodule
| 7.642333 |
module bitExtensionJump (
in,
out
);
input [0:23] in;
output reg [0:29] out;
always @(in) begin
if (in[0] == 1) begin
out = {6'b111111, in};
end else begin
out = {6'b000000, in};
end
end
endmodule
| 8.124643 |
module bitExtensionJump32 (
in,
out
);
input [0:23] in;
output reg [0:31] out;
always @(in) begin
if (in[0] == 1) begin
out = {8'b11111111, in};
end else begin
out = in;
end
end
endmodule
| 8.124643 |
module BitExtensor(Inpt, Outp);
parameter InputSize;
input [InputSize-1:0] Inpt;
output reg [31:0] Outp;
always@(*)
begin
Outp = {{(32-InputSize){1'b0}}, Inpt};
end
endmodule
| 7.772686 |
module sign extends inputs (usually immediate values) up to the size
* expected by the ALU (32 bits, in our case).
* May 3rd, 2016
* Conor O'Connell
**********************************/
//http://stackoverflow.com/questions/4176556/how-to-sign-extend-a-number-in-verilog
module bitFieldExt(valin, extended );
p... | 9.119537 |
module bitgen (
SEL,
bitstream
);
input [3:0] SEL;
output reg bitstream;
always @(SEL) begin
bitstream = 0;
case (SEL)
4'b0001: bitstream = 1'b1;
4'b0010: bitstream = 1'b0;
4'b0011: bitstream = 1'b0;
4'b0100: bitstream = 1'b0;
4'b0101: bitstream = 1'b1;
4'b0110... | 6.637749 |
module bitGen2 (
bright,
glyphData,
counter,
g,
b,
r,
hcount,
vcount,
lettervalue,
numbervalue
); // bitGen 1 that colors the whole screen depending on 8 switches colors
input bright;
input [9:0] hcount, vcount;
input [39:0] glyphData;
input [0:39] lettervalue, numberva... | 7.314791 |
module used for inversing every bit of a register input
module bitInv
#(parameter N = 8)
(
input [N-1:0] din,
output [N-1:0] out
);
assign out = ~din;
endmodule
| 10.101555 |
module Bitlet_AlignerArray #(
parameter N_align = 8
) (
input [N_align*`Wid_abs-1:0] Wabs_vec,
input [N_align*`Wid_exs-1:0] Esum_vec,
input [ `Wid_exs-1:0] Emax,
output [N_align*`Wid_abs-1:0] Walign_vec
);
generate
genvar g;
for (g = 0; g < N_align; g = g + 1) begin
Bitlet... | 6.993304 |
module Bitlet_Aligner (
input [`Wid_abs-1:0] Wabs,
input [`Wid_exs-1:0] Esum,
input [`Wid_exs-1:0] Emax,
output [`Wid_abs-1:0] Walign
);
wire [`Wid_exs-1:0] Ediff;
assign Ediff = Emax - Esum;
assign Walign = Wabs >> Ediff;
endmodule
| 6.993304 |
module.
* Dependency: Bitlet_CE.v Bitlet_Accumulator.v
*
* Author: ZHU Zi-Xuan (UESTC), 2021.02
*/
`timescale 1ns / 1ps
`include "Bitlet_Defs.vh"
module Bitlet_Calculator
#(
parameter N_total = 64
)
(
input clk,
input rst_n,
input [$c... | 8.309359 |
module Bitlet_FindMax #(
parameter N_input = 16,
parameter P_input = 4
) (
input clk,
input rst_n,
input flush,
input Esum_vld,
input [N_input*`Wid_exs-1:0] Esum_vec,
outp... | 6.776531 |
module FindMax #(
parameter W = 9
) (
input [W-1:0] I1,
input [W-1:0] I0,
output [W-1:0] O
);
assign O = (I1 < I0) ? I0 : I1;
endmodule
| 7.80141 |
module Bitlet_PackFixed (
input clk,
input rst_n,
input [`Wid_quant-1:0] quant,
input Aacc_vld,
input [ `Wid_acc-1:0] Aacc,
output reg res_vld,
output reg [ `Wid_bin-1:0] res
);
wire [`Max_quant... | 6.601929 |
module Bitlet_PackFloat (
input clk,
input rst_n,
input Aacc_vld,
input [`Wid_acc-1:0] Aacc,
input Emax_vld,
input [`Wid_exs-1:0] Emax,
output reg res_vld,
output reg [`Wid_bin-1:0] r... | 6.926859 |
module.
* Dependency: Bitlet_Processor.v Bitlet_Calculator.v Bitlet_Postprocessor.v
*
* Author: ZHU Zi-Xuan (UESTC), 2021.02
*/
`timescale 1ns / 1ps
`include "Bitlet_Defs.vh"
module Bitlet_PE
#(
parameter N_total = 64,
parameter N_input = 16
)
(
input clk,
... | 8.309359 |
module Bitlet_Prim_BufferArray #(
parameter N = 4, // number of data
parameter W = 16 // width of data
) (
input clk,
input rst_n,
input enw, // active high, 1 cycle
input [$clog2(N)-1:0] sel,
input [ 1*W-1:0] DI,
output [ ... | 8.719267 |
module Bitlet_Prim_Buffer #(
parameter W = 16 // width of data
) (
input clk,
input rst_n,
input enw, // active high, 1 cycle
input [W-1:0] DI,
output reg [W-1:0] DO
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) DO <= 'b0;
... | 8.719267 |
module Bitlet_Cmp4to2 #(
parameter W = 16 // width of data
) (
input [W-1:0] I3,
input [W-1:0] I2,
input [W-1:0] I1,
input [W-1:0] I0,
output [W-1:0] O1,
output [W-1:0] O0
);
wire [ W:0] Cin;
wire [W-1:0] Ctmp;
assign Cin[0] = 1'b0;
assign O0 = Ctmp << 1;
generate
... | 7.24442 |
module Bitlet_Compactor_4to2 (
input Cin,
input I3,
I2,
I1,
I0,
output Cout,
output C,
S
);
wire m0, m1, m2;
assign m0 = I0 ^ I1;
assign m1 = I2 ^ I3;
assign m2 = m0 ^ m1;
assign Cout = (m1) ? I1 : I3;
assign C = (m2) ? Cin : I0;
assign S = Cin ^ m2;
endmod... | 7.988716 |
module Bitlet_Compactor_3to2 (
input I2,
I1,
I0,
output C,
S
);
wire m0;
assign m0 = I0 ^ I1;
assign C = (m0) ? I2 : I1;
assign S = I2 ^ m0;
endmodule
| 7.988716 |
module Bitlet_Prim_Decoder_Decimal_to_Onehot #(
parameter W = 16 // width of output
) (
input [$clog2(W)-1:0] DI,
output [ W-1:0] DO
);
assign DO = 'b1 << DI;
endmodule
| 8.659769 |
module Bitlet_ReassemblerArray #(
parameter N_input = 16
) (
input isfix, // active high, stable
input [ N_input*1-1:0] Wsig_vec,
input [N_input*`Wid_exp-1:0] Wexp_vec,
input [N_input*`Wid_bin-1:0] Abin_vec,
output [N_input*`Wid_exs-1:0] Esum_vec,
output ... | 7.731219 |
module Bitlet_Reassembler (
input isfix,
input Wsig,
input [`Wid_exp-1:0] Wexp,
input [`Wid_bin-1:0] Abin,
output [`Wid_exs-1:0] Esum,
output [`Wid_fix-1:0] Afix
);
wire Asig;
wire [`Wid_exp-1:0] Aexp;
wire [`Wid_abs-1:0] Aman;
Bitlet_Un... | 7.731219 |
module Bitlet_Unpack (
input [`Wid_bin-1:0] bin,
input isfix,
output sig,
output [`Wid_exp-1:0] exp,
output [`Wid_abs-1:0] man
);
assign sig = bin[`Wid_bin-1];
assign exp = ((~|bin[`Wid_man+:`Wid_exp]) & (|bin[0+:`Wid_man])) ? 'b1 : bin[`Wid_man+:`Wid_exp];
ass... | 6.766586 |
module for 10-digit bitmap ROM
module digits10_case(digit, yofs, bits);
input [3:0] digit; // digit 0-9
input [2:0] yofs; // vertical offset (0-4)
output reg [4:0] bits; // output (5 bits)
// combine {digit,yofs} into single ROM address
wire [6:0] caseexpr = {digit,yofs};
always @(*)
case (case... | 7.337151 |
module digits10_array (
digit,
yofs,
bits
);
input [3:0] digit; // digit 0-9
input [2:0] yofs; // vertical offset (0-4)
output [7:0] bits; // output (5 bits)
reg [7:0] bitarray[0:15][0:7]; // ROM array (16 x 5 x 5 bits)
assign bits = bitarray[digit][yofs]; // assign module output
intege... | 7.526921 |
module top (
input CLK, // 16 or 12MHz clock
output VGA_BLUE,
output VGA_GREEN,
output VGA_RED,
output VGA_HSYNC,
output VGA_VSYNC
);
wire vsync, hsync, red, green, blue;
assign VGA_VSYNC = vsync;
assign VGA_HSYNC = hsync;
assign VGA_RED = red;
assign VGA_GREEN = green;
assign VG... | 7.233807 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (... | 7.286889 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
... | 7.774683 |
module bitmap_gen (
input wire clk,
reset,
input wire video_on,
input [1:0] btn,
input [2:0] sw,
input wire [9:0] pix_x,
pix_y,
output reg [2:0] bit_rgb
);
// constant and signal declaration
wire refr_tick, load_tick;
//--------------------------------------------
// video sram
... | 8.06692 |
module bitmap_testbench;
reg simul_Clock;
reg simul_reset;
wire simul_hsync;
wire simul_vsync;
wire [3:0] simul_RED;
wire [3:0] simul_GREEN;
wire [3:0] simul_BLUE;
initial begin
simul_Clock = 1'b0;
forever simul_Clock = #1 ~simul_Clock;
end
initial begin
simul_reset = 1'b1;
#100 si... | 6.92145 |
module BitMux2_1 (
out,
a,
b,
select
);
output out;
input a, b, select;
reg out;
always @(select or a or b)
case (select)
1'b0: out <= a;
1'b1: out <= b;
default: out <= b;
endcase
endmodule
| 7.642084 |
module bitNegator (
bitIn,
bitN,
bitOut
);
input bitIn, bitN;
output bitOut;
reg bitOut;
always @(bitIn or bitN) begin
if (bitN) begin
bitOut = ~bitIn;
end else begin
bitOut = bitIn;
end
end
endmodule
| 6.935942 |
module BitonicSortX4 #(
parameter DSIZE = 18,
parameter OFFSET = 8
) (
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
out... | 6.764159 |
module BitonicSortX8 #(
parameter DSIZE = 18,
parameter OFFSET = 8
) (
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input ... | 6.836592 |
module bitonic_block #(
parameter DATA_WIDTH = 16,
parameter ORDER = 0,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire clk,
input wire [DATA_WIDTH*2**(ORDER+1)-1:0] data_in,
output wire [DATA_WIDTH*2**(ORDER+1)-1:0] data_out
);
localparam STAGES = ORDER + 1;
localparam STAG... | 8.129443 |
module bitonic_comp #(
parameter DATA_WIDTH = 16,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire CLK,
input wire [DATA_WIDTH-1:0] A,
input wire [DATA_WIDTH-1:0] B,
output wire [DATA_WIDTH-1:0] H,
output wire [DATA_WIDTH-1:0] L,
output wire O
);
reg [DATA_WIDTH-1:0] H_... | 8.894266 |
module bitonic_merge_tree_5entry (
input clk,
reset,
input [0:`NUM_RIDS * `RIDS_WIDTH - 1] in,
output [0:`RIDS_WIDTH - 1] out
);
//// Merge RIDS #0 and RIDS #1
wire [0:`RIDS_WIDTH - 1] RIDS_0_1; // new RIDS which contains common rule IDs in RIDS #0 and RIDS #1
wire [0:`RIDS_WIDTH - 1] RIDS_0 = i... | 7.376928 |
module bitonic_merge_tree_scalable #(
parameter M = 256, // # of RIDS need to be merge, M msut be 2 ** (x), x is postive integer
parameter log_M = 8, // log2(M)
parameter RID_WIDTH = 4, // width of RID in each RIDS
parameter NUM_RID = 8, // the number of RID in each RIDS
parameter log_NUM_RID = ... | 7.376928 |
module BITONIC_NETWORK_2 #(
parameter DATA_WIDTH = 128,
parameter KEY_WIDTH = 80
) (
input i_clk,
input switch_output,
input stall,
input [DATA_WIDTH-1:0] top_tuple,
input [DATA_WIDTH-1:0] i_elems_0,
input ... | 7.118922 |
module CAS #(
parameter DATA_WIDTH = 128,
parameter KEY_WIDTH = 80
) (
input i_clk,
input stall,
input [DATA_WIDTH-1:0] i_elems_0,
input [DATA_WIDTH-1:0] i_elems_1,
output reg [DATA_WIDTH-1:0] o_elems_0,
output reg [DATA_WIDTH-1:0] o... | 8.703018 |
module BITONIC_NETWORK_4 #(
parameter DATA_WIDTH = 128,
parameter KEY_WIDTH = 80
) (
input i_clk,
input switch_output,
input stall,
input [2*DATA_WIDTH-1:0] top_tuple,
input [2*DATA_WIDTH-1:0] i_elems_0,
input [2*DATA_WIDTH-1:0] i_elems_1,
output reg [2*DATA_WIDTH-1:0] o_elems_0,
... | 7.118922 |
module bitonic_node #(
parameter DATA_WIDTH = 16,
parameter ORDER = 0,
parameter POLARITY = 0,
parameter SIGNED = 0
) (
input wire clk,
input wire [DATA_WIDTH*2**(ORDER+1)-1:0] data_in,
output wire [DATA_WIDTH*2**(ORDER+1)-1:0] data_out
);
localparam COMP_NUM = 2 ** ORDER;
genvar i;
... | 8.346627 |
module compare_swap #(
parameter W = 2
) (
a1,
a2,
dir,
o1,
o2
);
input [W-1:0] a1, a2;
input dir; // dir = 1 -> ascending
output [W-1:0] o1, o2;
wire comp;
wire isCorrect;
COMP #(
.N(W)
) COMP_ (
.A(a1),
.B(a2),
.O(comp)
);
assign isCorrect = (dir ... | 7.27735 |
module bitonic_merge #(
parameter W = 2,
parameter K = 3
) (
in_array,
dir,
out_array
);
input [W*K-1:0] in_array;
input dir;
output [W*K-1:0] out_array;
wire [W-1:0] in_mat[K-1:0];
wire [W-1:0] out_interm_mat[K-1:0];
wire [W*K-1:0] out_interm_array;
wire [W*K-1:0] out_merge;
lo... | 7.376928 |
module bitonic_sort #(
parameter W = 2,
parameter K = 2
) (
in_array,
dir,
out_array
);
input [W*K-1:0] in_array;
input dir;
output [W*K-1:0] out_array;
wire [W*K-1:0] out_sort;
wire [W*K-1:0] out_merge;
localparam lo = 0;
genvar i;
generate
if (K > 1) begin
localparam ... | 8.005591 |
module bitonic_sorter_orange #(
parameter SINGLE_WAY_WIDTH_IN_BITS = 32,
parameter NUM_WAY = 16 // must be a power of 2
) (
input [SINGLE_WAY_WIDTH_IN_BITS * NUM_WAY - 1 : 0] pre_sort_flatted_in,
output [SINGLE_WAY_WIDTH_IN_BITS * NUM_WAY - 1 : 0] post_sort_flatted_out
);
generate... | 6.650761 |
module bitonic_sorter_pink #(
parameter SINGLE_WAY_WIDTH_IN_BITS = 32,
parameter NUM_WAY = 16 // must be a power of 2
) (
input [SINGLE_WAY_WIDTH_IN_BITS * NUM_WAY - 1 : 0] pre_sort_flatted_in,
output [SINGLE_WAY_WIDTH_IN_BITS * NUM_WAY - 1 : 0] post_sort_flatted_out
);
parameter ... | 6.650761 |
module bitonic_sorting_recursion #(
parameter LOG_INPUT_NUM = 4, // Eg: If LOG_INPUT_NUM=4, then input number is 2**4=16
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = LOG_INPUT_NUM,
parameter SIGNED = 0,
parameter ASCENDING = 1
) (
input clk,
rst,
x_valid,
// Put all the input... | 7.049537 |
module bitonic_sorting_top #(
parameter LOG_INPUT_NUM = 4, // Eg: If LOG_INPUT_NUM=4, then input number is 2**4=16
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = LOG_INPUT_NUM,
parameter SIGNED = 0,
parameter ASCENDING = 1
) (
input clk,
rst,
x_valid,
// Put all the inputs into... | 7.049537 |
module bitops_get_hi (
in,
out
);
parameter width = 8;
input wire [(width-1):0] in;
output wire [(width-1):0] out;
wire [(width-1):0] r_data;
bitops_get_hilo_abf gen0_abfh (
.r(0),
.a(in[width-1]),
.out(out[width-1]),
.out_r(r_data[width-1])
);
genvar gi;
generate
... | 7.814454 |
module bitops_get_hilo_abf (
a,
r,
out,
out_r
);
input wire a, r;
output wire out, out_r;
assign out = (~r) && a; //out = (r==0) ? a : 0;
assign out_r = r || a; //(r==1)||(a==1);
endmodule
| 7.814454 |
module bitops_get_lo (
in,
out
);
parameter width = 8;
input wire [(width-1):0] in;
output wire [(width-1):0] out;
wire [(width-1):0] r_data;
bitops_get_hilo_abf gen0_abf (
.r(0),
.a(in[0]),
.out(out[0]),
.out_r(r_data[0])
);
genvar gi;
generate
for (gi = 1; gi < w... | 6.986425 |
module Bitparidad (
input [2:0] A,
input [2:0] B,
output BP
);
wire BG;
assign BG = A[2] ^ A[1] ^ A[0] ^ B[2] ^ B[1] ^ B[0];
assign BP = BG;
endmodule
| 8.033985 |
module playfields (
input [6:1] bpldata, //raw bitplane data in
input dblpf, //double playfield select
input [6:0] bplcon2, //bplcon2 (playfields priority)
output reg [2:1] nplayfield, //playfield 1,2 valid data
output reg [5:0] plfdata //playfield data out
)... | 7.872049 |
module bitplane_shifter (
input clk28m, //35ns pixel clock
input c1,
input c3,
input load, //load shift register
input hires, //high resolution select
input shres, //super high resolution select (takes priority over hires)
input [1... | 6.99515 |
module a_bitRegester_tb;
reg p, d, c, r, l;
wire q1, q2;
bit_regester b (
q1,
q2,
p,
d,
l,
c,
r
);
initial begin
p = 'b1;
#5 l = 'b1;
#5 d = 'b1;
r = 'b1;
#5 c = 'b1;
#5 c = 'b0;
#5 #5 golden(q1, 'b1, l, d, r);
end
task golden;
in... | 6.539908 |
module a_bitRegesterB_tb;
reg p, d, c, r, l;
wire q1, q2;
bit_regester b (
q1,
q2,
p,
d,
l,
c,
r
);
initial begin
p = 'b1;
#5 l = 'b0;
#5 d = 'b1;
r = 'b0;
#5 c = 'b1;
#5 c = 'b0;
#5 golden(q1, 'b0, l, d, r);
#5 l = 'b1;
#5 d = 'b1... | 6.539908 |
module bitRevOrderSM (
Clk,
start,
reset,
DinA,
DinB,
write_enableA,
write_enableB,
addrA,
addrB,
DoutA,
DoutB,
tc
);
input Clk, start, reset;
input [17:0] DinA, DinB;
output reg write_enableA, write_enableB;
output [9:0] addrA, addrB;
output [17:0] DoutA, Dou... | 6.987238 |
module: bitRevRam
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bitRevRam_tb;
parameter HALF_PERIOD = 5;
// Inputs
reg Clk;
reg [8:0] addr;
// Outputs
wire [9:0] DoutA;
... | 6.722992 |
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