code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module oh_gray2gray #(
parameter DW = 32 // width of data inputs
) (
input [DW-1:0] in,
output [DW-1:0] out
);
wire [DW-1:0] interm;
oh_gray2bin #(
.DW(DW)
) rd_g2b (
.out(interm),
.in (in)
);
oh_bin2gray #(
.DW(DW)
) rd_b2g (
.out(out),
.in (interm)
);... | 7.995634 |
module oh_bin2gray #(
parameter DW = 32 // width of data inputs
) (
input [DW-1:0] in, //binary encoded input
output [DW-1:0] out //gray encoded output
);
reg [DW-1:0] gray;
wire [DW-1:0] bin;
integer i;
assign bin[DW-1:0] = in[DW-1:0];
assign out[DW-1:0] = gray[DW-1:0];
... | 7.563555 |
module oh_gray2bin #(
parameter DW = 32
) // width of data inputs
(
input [DW-1:0] in, //gray encoded input
output [DW-1:0] out //binary encoded output
);
reg [DW-1:0] bin;
wire [DW-1:0] gray;
integer i, j;
assign gray[DW-1:0] = in[DW-1:0];
assign out[DW-1:0] = bin[DW-1:0];
always @* b... | 8.05566 |
module bin_gry #(
parameter N = 8
) //parameter declaration
(
binary, //input
gray //output
);
//port declaration
input [N-1:0] binary; //input declaration
output reg [N-1:0] gray; //output declaration
/*implement binary to gray conversion*/
always @(binary) begin
gray[N-1] = binary[N... | 7.405175 |
module bin_gry_tb; //testbench module
parameter N = 8; //initializing parameter
reg [N-1:0] binary; //declaring binary input as regster
wire [N-1:0] gray; //declaring output as wire
reg [N-1:0] new_gray; //declaring output as gegister for self checking
//instantiation of design under ... | 7.15536 |
module bin_mask (
input wire [7 : 0] Ta,
input wire [7 : 0] Tb,
input wire [7 : 0] Tc,
input wire [7 : 0] Td,
input wire [7 : 0] Cb,
input wire [7 : 0] Cr,
output wire [7 : 0] mask
);
assign mask = (Cb > Ta && Cb < Tb && Cr > Tc && Cr < Td) ? 8'd255 : 0;
endmodule
| 6.898314 |
module bin_to_1h #(
parameter OUTPUT_WIDTH = 2,
parameter INPUT_WIDTH = $clog2(OUTPUT_WIDTH)
) (
input [ INPUT_WIDTH-1:0] binary,
output [OUTPUT_WIDTH-1:0] one_hot
);
genvar i;
for (i = 0; i < OUTPUT_WIDTH; i = i + 1) begin
assign one_hot[i] = binary == i;
end
endmodule
| 6.76573 |
module bin_to_7seg (
bin,
seg
);
input [3:0] bin;
output [6:0] seg;
reg [6:0] seg;
always @(bin) begin
case (bin)
4'h0: seg = 7'b1000000; // output = 0 indicates a lit segment
4'h1: seg = 7'b1111001; // ---0---
4'h2: seg = 7'b0100100; // | |
4'h3: seg = 7'b0110000; //... | 6.806475 |
module bin_to_asc_hex (
in,
out
);
parameter METHOD = 1;
parameter WIDTH = 16;
localparam PAD_BITS = (WIDTH % 4) == 0 ? 0 : (4 - (WIDTH % 4));
localparam PADDED_WIDTH = WIDTH + PAD_BITS;
localparam NYBBLES = PADDED_WIDTH >> 2;
input [WIDTH-1:0] in;
output [8*NYBBLES-1:0] out;
wire [PADDED_WI... | 7.170833 |
module bin_to_asc_hex_tb ();
parameter WIDTH = 16;
parameter OUT_WIDTH = 4; // Number of nybbles in WIDTH
reg [WIDTH-1:0] in;
wire [8*OUT_WIDTH-1:0] oa, ob;
bin_to_asc_hex a (
.in (in),
.out(oa)
);
bin_to_asc_hex b (
.in (in),
.out(ob)
);
initial begin
#100000 $stop();... | 7.170833 |
module bin_to_bcd (
bin,
bcd_t,
bcd_o
);
input [5:0] bin;
output [3:0] bcd_t, bcd_o;
reg [7:0] bcd;
reg [3:0] i;
//implements an algorithm for binary to bcd conversion
always @(bin) begin
bcd = 0;
for (i = 0; i < 6; i = i + 1) begin
bcd = {bcd[7:0], bin[5-i]};
if (i < 5 && bc... | 7.085337 |
module bin_to_bcd_13 (
input wire [12:0] bin, // binary input
output reg [15:0] dec // BCD output
);
reg [12:0] b; // local copy of bin
integer i; // loop counter
always @* begin
b = bin;
dec = 13'd0;
for (i = 0; i < 12; i = i + 1) begin
// shift left dec and b
... | 6.768218 |
module bin_to_bcd_14 (
input wire [13:0] bin, // binary input
output reg [15:0] dec // BCD output
);
reg [13:0] b; // local copy of bin
integer i; // loop counter
always @* begin
b = bin;
dec = 16'd0;
for (i = 0; i < 13; i = i + 1) begin
// shift left dec and b
... | 6.819304 |
module bin_to_bcd_8 (
input wire [7:0] bin, // binary input
output reg [9:0] dec // BCD output
);
reg [7:0] b; // local copy of b
integer i; // loop counter
always @* begin
b = bin;
dec = 10'd0;
for (i = 0; i < 7; i = i + 1) begin
// shift left d and bi
{dec, ... | 6.947695 |
module will separate the number in to decimal bits for the convenience of number display
Input: clk
rst_n
Output: tho
hun
ten
one
done
External resource found at https://blog.csdn.net/li200503028/article/details/19507061
originally created by stubben_bear
for design purpose the i... | 6.776419 |
module bin_to_gray (
bin,
gray
);
parameter WIDTH = 8;
input [WIDTH-1:0] bin;
output [WIDTH-1:0] gray;
wire [WIDTH-1:0] gray;
assign gray = bin ^ (bin >> 1);
endmodule
| 6.875833 |
module bin_to_gray_using_decoder (
input [3:0] b_i, // Binary Input
output [3:0] g_o // Gray Output
);
wire [15:0] y; // Decoder output
// Instantiation
decoder_4_to_16 dut (
.i_i (b_i),
.en_i(1'b1),
.y_o (y)
);
or or_0 (g_o[0], y[1], y[2], y[5], y[6], y[9], y[10], y[13], y[1... | 6.676721 |
module bin_to_gray_using_decoder_tb ();
// Signal Decleration
reg [3:0] b_i;
wire [3:0] g_o;
integer i;
// Instantiation
bin_to_gray_using_decoder dut (
.b_i(b_i),
.g_o(g_o)
);
// Logic to drive inputs and check outputs
initial begin
for (i = 0; i < 16; i = i + 1) begin
b_i =... | 6.676721 |
module bin_to_onehot(
clk,
rst,
bin,
onehot
);
input clk;
input [BIN_WIDTH-1:0] bin;
output reg [ONEHOT_WIDTH-1:0] onehot;
parameter BIN_WIDTH = 4;
localparam ONEHOT_WIDTH = 2 << (BIN_WIDTH - 1);
genvar i;
generate
for(i=0; i < ONEHOT_WIDTH; i = i + 1)
begin: CONVERSION
always @(posedge clk)
on... | 6.560098 |
module bin_to_real (
bin_speed,
real_speed,
direction,
clk
);
parameter width = 32;
parameter MAX_SPEED = 1000; //rotation per second
parameter SPEED_ONE = MAX_SPEED / 3;
parameter SPEED_TWO = MAX_SPEED / 2;
parameter SPEED_THREE = MAX_SPEED;
input [2:0] bin_speed; //3 bits: [direction s... | 6.90482 |
module bin_to_sseg (
// input wire CLOCK,
input wire [3:0] BIN,
output wire [6:0] HEX
);
assign HEX = (BIN == 4'b0000) ? 7'b1000000 : // 0
(BIN == 4'b0001) ? 7'b1111001 : // 1
(BIN == 4'b0010) ? 7'b0100100 : // 2
(BIN == 4'b0011) ? 7'b0110000 : // 3
(BIN == 4'b0100) ? 7'b0011... | 6.821705 |
module authorization (
auth,
check,
checkhash
);
input [7:0] auth;
input [7:0] checkhash;
output reg check;
always @(*) begin
// Simple logic of hash-match or not
if (auth == checkhash) check = 1;
else check = 0;
end
endmodule
| 6.518535 |
module test;
wire check;
reg [0:7] auth;
reg [0:7] checkhash;
authorization authen (
auth,
check,
checkhash
);
initial begin
$dumpfile("vcd/BiometricsImplement.vcd");
$dumpvars(0, test);
$display("Bytes \t Checker");
$monitor("%b %b", auth, check);
checkhash = 8'b11101... | 6.964054 |
module biosrom (
input clk,
input en,
input [8:0] addr,
output reg [31:0] data
);
reg [31:0] rom[0:511];
initial begin
`ifdef SIMULATION
$readmemh("../../../software/biosrom/biosrom.d32", rom, 0, 511);
`else
$readmemh("/home/tmatsuya/ipnuma/software/biosrom/biosrom.d32", rom, 0, 511);
`end... | 6.692556 |
module bios_integration_testbench ();
parameter SYSTEM_CLK_PERIOD = 8;
parameter SYSTEM_CLK_FREQ = 125_000_000;
reg sys_clk = 0;
reg sys_rst = 0;
always #(SYSTEM_CLK_PERIOD / 2) sys_clk <= ~sys_clk;
// UART Signals between the on-chip and off-chip UART
wire FPGA_SERIAL_RX, FPGA_SERIAL_TX;
// Off-chip... | 7.101457 |
module bios_loader (
input wire clk,
input wire rst,
output reg [27:0] address,
output reg [ 3:0] byteenable,
output reg write,
output reg [31:0] writedata,
output reg read,
input wire [31:0] readdata,
input wire waitrequest
);
parameter... | 6.971526 |
module bios_mem (
input clk,
input ena,
input [11:0] addra,
output reg [31:0] douta,
input enb,
input [11:0] addrb,
output reg [31:0] doutb
);
parameter DEPTH = 4096;
reg [31:0] mem[4096-1:0];
always @(posedge clk) begin
if (ena) begin
douta <= mem[addra];
end
end
al... | 6.646569 |
module bios_sram (
input clka,
input ena,
input wea,
input [15:0] addra,
input [ 7:0] dina,
output reg [ 7:0] douta,
output reg [20:0] SRAM_ADDR,
inout [ 7:0] SRAM_DATA,
output reg SRAM_WE_n
);
reg [7:0] data;
assign SRA... | 7.086996 |
module bip39 (
input i_clk,
input i_reset_n,
input [31:0] i_random_seed
// input [31:0] i_entropy;
);
wire [ 7:0] w_random;
wire [13:0] w_rd_addr;
wire w_rd_en;
wire [ 7:0] w_q_data;
random random_inst0 (
.i_clk (i_clk),
.i_reset_n(i_r... | 6.979845 |
module bipolar_stepper_motor_drive #(
parameter Q_WIDTH = 16, // 小数点サイズ
parameter MICROSTEP_WIDTH = 12,
parameter PAHSE_WIDTH = 2 + Q_WIDTH
) (
input wire reset,
input wire clk,
input wire microstep_en,
input wire nanostep_en,
input wire asyc_update_en,
input ... | 7.038099 |
module bip_calculator #(
parameter LEN_CODED_BLOCK = 66,
parameter AM_ENCODING_LOW = 24'd0, //{M0,M1,M2} tabla 82-2
parameter AM_ENCODING_HIGH = 24'd0, //{M4,M5,M6} tabla 82-2
parameter NB_BIP = 8
) (
input wire i_clock,
input wire i_reset,
i... | 7.118397 |
module bip_calculator #(
parameter LEN_CODED_BLOCK = 66,
parameter NB_BIP = 8
) (
input wire i_clock,
input wire i_reset,
input wire [LEN_CODED_BLOCK-1 : 0] i_data,
input wire i_enable,
input wire ... | 7.118397 |
module biquad_filter #(
parameter io_width = 16,
parameter internal_width = io_width * 2
) (
input wire clk,
input wire reset,
input wire en,
input wire signed [io_width-1:0] b0,
input wire signed [io_width-1:0] b1,
input wire signed [io_width-1:0] b2,
input wire signed [io_width-1:... | 6.722098 |
module biquad_filter #(
parameter io_width = 16,
parameter internal_width = io_width * 2 - 1
) (
input wire clk,
input wire reset,
input wire en,
input wire signed [io_width-1:0] b0,
input wire signed [io_width-1:0] b1,
input wire signed [io_width-1:0] b2,
input wire signed [io_widt... | 6.722098 |
module bird (
input clk,
input frameclk,
input up,
input down,
input [2:0] state,
input [5:0] count,
input [10:0] pos_x,
input [10:0] pos_y,
input sw0,
output reg isbird,
output reg [3:0] birdr,
output reg [3:0] birdg,
output reg [3:0] birdb,
output reg [10:0] bir... | 7.107135 |
module bridge (
input [31:0] PrAddr,
input [31:0] PrWD,
output [31:0] PrRD,
input [31:0] rd1,
input [31:0] rd2,
input [31:0] rd3,
input IRQ,
output [5:0] HWInt,
input wen,
output outwe,
output twe
);
wire HitDEV_timer, HitDEV_output, HitDEV_input;
assign HWInt = {5'b0, IR... | 8.006498 |
module birdPosition_17 (
input clk,
input rst,
input btn,
output reg [7:0] outPosition
);
wire [16-1:0] M_alu_out;
wire [ 1-1:0] M_alu_overflow;
reg [16-1:0] M_alu_a;
reg [16-1:0] M_alu_b;
reg [ 6-1:0] M_alu_alufn;
alu_3 alu (
.a(M_alu_a),
.b(M_alu_b),
.alufn(M_alu_al... | 6.803567 |
module: bird
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bird_tb;
// Inputs
reg clk;
reg rst;
reg enable;
reg jump;
reg [1:0] fall_accel;
reg state;
// Outputs
wire [... | 7.199531 |
module biriscv_lsu_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
... | 7.011414 |
module biriscv_npc_lfsr
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter DEPTH = 32
, parameter ADDR_W = 5
, parameter INITIAL_VALUE = 16'h0001
, parameter TAP_VALUE = 16'hB... | 6.91699 |
module RAM16X1D (
DPO,
SPO,
A0,
A1,
A2,
A3,
D,
DPRA0,
DPRA1,
DPRA2,
DPRA3,
WCLK,
WE
);
parameter INIT = 16'h0000;
output DPO, SPO;
input A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE;
reg [15:0] mem;
wire [ 3:0] adr;
assign adr = {A3, A2, A... | 7.214201 |
module is taken from:
// Implementations/crypto_aead/drygascon128/add_verilog/drygascon128_1round_cycle/drygascon128_ACC_PIPE_MIX_SHIFT_REG.v
// source: (sebastien-riou/DryGascon)[https://github.com/sebastien-riou/DryGASCON]
`timescale 1ns / 1ps
`default_nettype none
module birotr(
input wire [64-1:0] din,
i... | 7.591788 |
module bistable_domain_cross (
rst,
clk_a,
in,
clk_b,
out
);
parameter width = 1;
input rst;
input clk_a;
input [width-1:0] in;
input clk_b;
output [width-1:0] out;
// We use a two-stages shift-register to synchronize in to the clk_b clock domain
reg [width-1:0] sync_clk_b[1:0];
a... | 7.501432 |
module controller_new (
clk,
rst,
BIST_mode,
data_in,
finish,
fault_detected,
result_dut,
misr_output
);
input [8:0] data_in;
input clk; //clock
input rst; //reset
input finish; //finish flag
input BIST_mode; //BIST mode
output reg fault_detected; //fault detected flag
... | 6.606807 |
module BIST_controller (
rst,
clk,
error,
pat_end,
count_end,
nxt_pat,
nxt_count,
tst_state,
tst_pass,
tst_fail,
rst_count,
rst_pat,
tst_count[1]
);
input rst;
input clk;
input error;
input pat_end;
input count_end;
output nxt_pat;
output reg nxt_count;
... | 6.687146 |
module BIST_controller_tb ();
reg b_rst;
reg b_clk;
reg b_error;
reg b_pat_end;
reg b_count_end;
wire b_nxt_pat;
wire b_nxt_count;
wire b_tst_state;
wire b_tst_pass;
wire b_tst_fail;
wire b_rst_count;
wire b_rst_pat;
BIST_controller My_BIST (
b_rst,
b_clk,
b_error,
... | 6.687146 |
module BIST_MUX (
input wire [7:0] user_input,
input wire [7:0] BIST_input,
input wire select, //1 for BIST 0 for user input
output wire [7:0] out
);
reg [7:0] out_temp;
always @(*) begin
if (select == 0) out_temp = user_input;
else out_temp = BIST_input;
end
assign out =... | 7.971307 |
module BIST_tb;
localparam clk_period = 20;
reg clk;
reg [3:0] select;
integer i;
wire [3:0] dat_in;
wire [3:0] dat_out;
wire [7:0] addr_out;
wire op_done, w_en;
BIST_engine_top BIST (
.select(select),
.dat_out(dat_out),
.dat_in(dat_in),
.addr_out(addr_out),
.w_en(w_en... | 6.721843 |
module bist_test;
// Inputs
reg clk;
wire rst_n;
wire sck_transition;
reg [11:0] rf_bist_start_val;
reg [ 7:0] rf_bist_inc;
reg [11:0] rf_bist_up_limit;
// Internal Variables
reg i2si_sck;
reg sck_d1; // serial clock delay
reg [31:0] count;
reg [31:0... | 6.52078 |
module BIST_TestBench ();
reg [2:0] What_Do_You_Want_To_Check;
reg clk, WE;
reg [7:0] Address;
reg [3:0] Data_Input;
wire [3:0] Data_output;
wire GoNoGo;
Full_BIST dut (
.What_Do_You_Want_To_Check(What_Do_You_Want_To_Check),
.clk(clk),
.WE(WE),
.Address(Address),
.Data_Inpu... | 6.628833 |
module BIST_engine_top (
output [7:0] addr_out,
output [3:0] dat_out,
input [3:0] dat_in,
output w_en,
op_done,
input [3:0] select,
input clk
);
wire [3:0] dat_out_bg0;
wire [7:0] add_out_bg0;
wire w_en_bg0, rst_done_bg0, rev_out_bg0;
wire [3:0] dat_out_c1;
wire [7:0] add_out_c... | 7.744874 |
module BIST_tb;
localparam clk_period = 50;
reg clk;
reg [3:0] select;
reg [7:0] i;
wire [3:0] dat_in;
wire [3:0] dat_out;
wire [7:0] addr_out;
wire op_done, w_en;
BIST_engine_top BIST (
.select(select),
.dat_out(dat_out),
.dat_in(dat_in),
.addr_out(addr_out),
.w_en(w_e... | 6.721843 |
module main (
clock
);
input clock;
reg [2:0] a, b;
initial a = 3'b010;
initial b = 3'b110;
always @(posedge clock) begin
a[2] <= b[0];
a[1:0] <= b[2:1];
b[2:1] <= a[1:0];
b[0] <= a[2];
end
endmodule
| 7.779865 |
module Bit (
input wire clk,
input wire in,
input wire load,
output wire out
);
// your implementation comes here:
// Mux(a=muxb, b=in, sel=load, out=muxo);
// DFF(in=muxo, out=out, out=muxb);
// reg muxb;
wire muxo;
Mux MUX (
.a (out),
.b (in),
.sel(load),
.ou... | 7.70558 |
module Bit10MUX (
a,
b,
select,
out
);
input [10:1] a;
input [10:1] b;
input select;
output [10:1] out;
assign out[1] = ((!select) & a[1]) | ((select) & b[1]);
assign out[2] = ((!select) & a[2]) | ((select) & b[2]);
assign out[3] = ((!select) & a[3]) | ((select) & b[3]);
assign out... | 8.337265 |
module Bit11Adder (
a,
b,
sum,
carry
);
input [11:1] a;
input [11:1] b;
output [11:1] sum;
output carry;
wire [10:1] w;
FullAdder fa_1 (
a[1],
b[1],
1'b0,
sum[1],
w[1]
);
FullAdder fa_2 (
a[2],
b[2],
w[1],
sum[2],
w[2]
);
... | 7.58013 |
module Bit11Adder (
a,
b,
sum,
carry
);
input [11:1] a;
input [11:1] b;
output [11:1] sum;
output carry;
wire [16:1] A, B, SUM;
wire CARRY;
assign A[11:1] = a;
assign A[16:12] = 5'b00000;
assign B[11:1] = b;
assign B[16:12] = 5'b00000;
RDAdder addr (
A,
B,
... | 7.58013 |
module bit2byte(
clk ,
reset_n ,
ldpc_en_out ,
ldpc_dout ,
ts0_win, ,
ts1_win, ,
byte_sync ,
byte_data ,
byte_win0 ,
byte_win1 ,
ts0_new ,
ts1_new
);
//inputs
input clk ... | 6.725177 |
module bit32and (
out,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
assign {out} = in1 & in2;
endmodule
| 8.092568 |
module bit32not (
not_a,
a
);
input [31:0] a;
output [31:0] not_a;
assign not_a = ~a;
endmodule
| 8.283339 |
module bit32or (
out,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
assign {out} = in1 | in2;
endmodule
| 6.970673 |
module bit32_2to1mux (
out,
sel,
in1,
in2
);
input [31:0] in1, in2;
input sel;
output [31:0] out;
genvar j;
generate
for (j = 0; j < 32; j = j + 1) begin : muxloop
mux2to1 m1 (
out[j],
sel,
in1[j],
in2[j]
);
end
endgenerate
endmodu... | 6.916393 |
module mux3to1 (
out,
sel,
in1,
in2,
in3
);
input in1, in2, in3;
input [1:0] sel;
output out;
assign out = sel[1] ? (sel[0] ? out : in3) : (sel[0] ? in2 : in1);
endmodule
| 6.860137 |
module bit32_3to1mux (
out,
sel,
in1,
in2,
in3
);
input [31:0] in1, in2, in3;
output [31:0] out;
input [1:0] sel;
genvar j;
generate
for (j = 0; j < 32; j = j + 1) begin : mux_loop
mux3to1 m (
out[j],
sel,
in1[j],
in2[j],
in3[j]
... | 7.021035 |
module bit32_8mux (
out,
sel,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
input sel;
genvar j;
generate
for (j = 0; j < 32; j = j + 8) begin : mux_loop
bit8_2to1mux m2 (
out[j+:8],
sel,
in1[j+:8],
in2[j+:8]
);
end
endgene... | 7.341413 |
module xor_gate (
input x1,
input x2,
input x3,
output y
);
wire y1;
assign y1 = x1 ^ x2;
assign y = y1 ^ x3;
endmodule
| 8.121905 |
module: bit3XOR_code
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module xor_gate_tb;
// Inputs
reg x1;
reg x2;
reg x3;
// Outputs
wire y;
// Instantiate the Unit Under Test (U... | 7.481672 |
module bit4 (
input shift_rot,
input [4:0] r,
input [31:0] x,
output [31:0] y
);
mux u1 (
r[2],
x[0],
x[4],
y[0]
);
mux u2 (
r[2],
x[1],
x[5],
y[1]
);
mux u3 (
r[2],
x[2],
x[6],
y[2]
);
mux u4 (
r[2],
x[3]... | 6.541464 |
module bit4_adder (
input [3:0] A,
input [3:0] B,
output [3:0] S,
output Cout
);
wire C1, C2, C3;
half_adder ha0 (
A[0],
B[0],
C1,
S[0]
);
full_adder fa1 (
A[1],
B[1],
C1,
C2,
S[1]
);
full_adder fa2 (
A[2],
B[2],
C2,
... | 7.229567 |
module Bit5Adder (
a,
b,
sum,
carry
);
input [5:1] a;
input [5:1] b;
output [5:1] sum;
output carry;
wire [4:1] w;
FullAdder fa_1 (
a[1],
b[1],
1'b0,
sum[1],
w[1]
);
FullAdder fa_2 (
a[2],
b[2],
w[1],
sum[2],
w[2]
);
Ful... | 8.341554 |
module Bit5Adder (
a,
b,
sum,
carry
);
input [5:1] a;
input [5:1] b;
output [5:1] sum;
output carry;
wire [16:1] A, B, SUM;
wire CARRY;
assign A[5:1] = a;
assign A[16:6] = 11'b00000000000;
assign B[5:1] = b;
assign B[16:6] = 11'b00000000000;
RDAdder addr (
A,
B,
... | 8.341554 |
module Bit5MUX (
a,
b,
select,
out
);
input [5:1] a;
input [5:1] b;
input select;
output [5:1] out;
assign out[1] = ((!select) & a[1]) | ((select) & b[1]);
assign out[2] = ((!select) & a[2]) | ((select) & b[2]);
assign out[3] = ((!select) & a[3]) | ((select) & b[3]);
assign out[4] = (... | 8.559446 |
module bit5_encode (
input clk,
input rst_n,
input [4:0] code,
output [2:0] op
);
reg [2:0] outdata;
always @(posedge clk, negedge rst_n)
if (~rst_n) outdata <= 3'd0;
else
casex (code)
5'bxxxx1: outdata <= 3'd0;
5'bxxx10: outdata <= 3'd1;
5'bxx1... | 6.960318 |
module FullAdder (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
wire a, b, cin;
wire sum, cout;
wire n_0, n_1;
MOAI22D0BWP g33 (
.A1(n_1),
.A2(n_0),
.B1(a),
.B2(b),
.ZN(cout)
);
MUX2ND0BWP g34 (
.I0(cin),
.I1(n_1),
.S (n_0... | 7.610141 |
module FullAdder_1 (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
wire a, b, cin;
wire sum, cout;
wire n_0, n_1;
AO22D2BWP g33 (
.A1(cin),
.A2(n_1),
.B1(a),
.B2(b),
.Z (cout)
);
CKXOR2D0BWP g34 (
.A1(n_0),
.A2(n_1),
.Z (su... | 6.801587 |
module FullAdder_3 (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
wire a, b, cin;
wire sum, cout;
wire n_0;
AO22D1BWP g33 (
.A1(cin),
.A2(n_0),
.B1(a),
.B2(b),
.Z (cout)
);
CKXOR2D0BWP g34 (
.A1(cin),
.A2(n_0),
.Z (sum)
... | 7.164723 |
module Bit4Adder (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder_1 FA_1 (
... | 7.608783 |
module Bit4Adder_1 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_4 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
... | 7.442301 |
module Bit4Adder_2 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_8 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
... | 7.073135 |
module Bit4Adder_3 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_12 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)... | 7.571329 |
module Bit16Adder (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire [16:1] a, b;
wire cin;
wire [16:1] sum;
wire cout;
wire w1, w2, w3;
Bit4Adder B4A_0 (
a[4:1],
b[4:1],
cin,
sum[4:1],
w1
);
Bit4Adder_1 ... | 6.99225 |
module Bit4Adder_4 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_16 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)... | 6.961725 |
module Bit4Adder_5 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_20 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)... | 7.165281 |
module Bit4Adder_6 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_24 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)... | 6.888112 |
module Bit4Adder_7 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_28 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)... | 7.213282 |
module Bit16Adder_1 (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire [16:1] a, b;
wire cin;
wire [16:1] sum;
wire cout;
wire w1, w2, w3;
Bit4Adder_4 B4A_0 (
.a(a[4:1]),
.b(b[4:1]),
.cin(cin),
.sum(sum[4:1]),
... | 7.190901 |
module Bit4Adder_8 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_32 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)... | 7.141654 |
module Bit4Adder_9 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_36 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)... | 6.741012 |
module Bit4Adder_10 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_40 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1... | 6.984917 |
module Bit4Adder_11 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_44 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1... | 6.909616 |
module Bit16Adder_2 (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire [16:1] a, b;
wire cin;
wire [16:1] sum;
wire cout;
wire w1, w2, w3;
Bit4Adder_8 B4A_0 (
.a(a[4:1]),
.b(b[4:1]),
.cin(cin),
.sum(sum[4:1]),
... | 7.132911 |
module Bit4Adder_12 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_48 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1... | 6.870252 |
module Bit4Adder_13 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_52 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1... | 7.073332 |
module Bit4Adder_14 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_56 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1... | 7.133875 |
module Bit4Adder_15 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_60 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1... | 6.968445 |
module Bit16Adder_3 (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire [16:1] a, b;
wire cin;
wire [16:1] sum;
wire cout;
wire w1, w2, w3;
Bit4Adder_12 B4A_0 (
.a(a[4:1]),
.b(b[4:1]),
.cin(cin),
.sum(sum[4:1]),
... | 7.429827 |
module Bit64Adder (
a,
b,
cin,
sum,
cout
);
input [64:1] a, b;
input cin;
output [64:1] sum;
output cout;
wire [64:1] a, b;
wire cin;
wire [64:1] sum;
wire cout;
wire w1, w2, w3;
Bit16Adder B16A_0 (
a[16:1],
b[16:1],
cin,
sum[16:1],
w1
);
Bit16Ad... | 6.759327 |
module Bit6Adder (
a,
b,
sum,
carry
);
input [6:1] a;
input [6:1] b;
output [6:1] sum;
output carry;
wire [5:1] w;
FullAdder fa_1 (
a[1],
b[1],
1'b0,
sum[1],
w[1]
);
FullAdder fa_2 (
a[2],
b[2],
w[1],
sum[2],
w[2]
);
Ful... | 7.483202 |
module bit8 (
input shift_rot,
input [4:0] r,
input [31:0] x,
output [31:0] y
);
mux u1 (
r[3],
x[0],
x[8],
y[0]
);
mux u2 (
r[3],
x[1],
x[9],
y[1]
);
mux u3 (
r[3],
x[2],
x[10],
y[2]
);
mux u4 (
r[3],
x[3... | 7.211629 |
module bit8alu (
a,
b,
s,
acc,
mulh,
flag
);
parameter width = 8, w = width - 1;
input [w:0] a;
input [w:0] b;
input [2:0] s;
output reg [w:0] acc;
output reg [w:0] mulh;
output reg [7:0] flag;
always @(*) begin
flag = 8'b0;
case (s)
3'b000: acc = a & b;
3'... | 6.618196 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.