code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module oh_gray2gray #(
parameter DW = 32 // width of data inputs
) (
input [DW-1:0] in,
output [DW-1:0] out
);
wire [DW-1:0] interm;
oh_gray2bin #(
.DW(DW)
) rd_g2b (
.out(interm),
.in (in)
);
oh_bin2gray #(
.DW(DW)
) rd_b2g (
.out(out),
.in (interm)
);
endmodule
| 7.995634 |
module oh_bin2gray #(
parameter DW = 32 // width of data inputs
) (
input [DW-1:0] in, //binary encoded input
output [DW-1:0] out //gray encoded output
);
reg [DW-1:0] gray;
wire [DW-1:0] bin;
integer i;
assign bin[DW-1:0] = in[DW-1:0];
assign out[DW-1:0] = gray[DW-1:0];
always @* begin
gray[DW-1] = bin[DW-1];
for (i = 0; i < (DW - 1); i = i + 1) gray[i] = bin[i] ^ bin[i+1];
end
endmodule
| 7.563555 |
module oh_gray2bin #(
parameter DW = 32
) // width of data inputs
(
input [DW-1:0] in, //gray encoded input
output [DW-1:0] out //binary encoded output
);
reg [DW-1:0] bin;
wire [DW-1:0] gray;
integer i, j;
assign gray[DW-1:0] = in[DW-1:0];
assign out[DW-1:0] = bin[DW-1:0];
always @* begin
bin[DW-1] = gray[DW-1];
for (i = 0; i < (DW - 1); i = i + 1) begin
bin[i] = 1'b0;
for (j = i; j < DW; j = j + 1) bin[i] = bin[i] ^ gray[j];
end
end
endmodule
| 8.05566 |
module bin_gry #(
parameter N = 8
) //parameter declaration
(
binary, //input
gray //output
);
//port declaration
input [N-1:0] binary; //input declaration
output reg [N-1:0] gray; //output declaration
/*implement binary to gray conversion*/
always @(binary) begin
gray[N-1] = binary[N-1]; //first bit is same as binary code
gray[N-2:0] = binary[N-1:1] ^ binary[N-2:0]; //xor the first bit with 2nd bit and so on
end
endmodule
| 7.405175 |
module bin_gry_tb; //testbench module
parameter N = 8; //initializing parameter
reg [N-1:0] binary; //declaring binary input as regster
wire [N-1:0] gray; //declaring output as wire
reg [N-1:0] new_gray; //declaring output as gegister for self checking
//instantiation of design under test
bin_gry #(
.N(8)
) dut (
.binary(binary), //input
.gray (gray) //output
);
initial begin
repeat (10) begin
stimulus; //call task
if (new_gray == gray) //check if design output and testbench output are same
$display(
"input binary = %b, output gray = %b, new output gray = %b, Testcase Pass",
binary,
gray,
new_gray
); //dispaly for testcase Pass
else
$display(
"input binary = %b, output gray = %b, new output gray = %b, Testcase Fail",
binary,
gray,
new_gray
); //display for testcase Fail
end
end
task stimulus;
begin
binary = $random; //random input generation
new_gray[N-1] = binary[N-1]; //test output
new_gray[N-2:0] = binary[N-1:1] ^ binary[N-2:0];
#5; //test output
end
endtask
endmodule
| 7.15536 |
module bin_mask (
input wire [7 : 0] Ta,
input wire [7 : 0] Tb,
input wire [7 : 0] Tc,
input wire [7 : 0] Td,
input wire [7 : 0] Cb,
input wire [7 : 0] Cr,
output wire [7 : 0] mask
);
assign mask = (Cb > Ta && Cb < Tb && Cr > Tc && Cr < Td) ? 8'd255 : 0;
endmodule
| 6.898314 |
module bin_to_1h #(
parameter OUTPUT_WIDTH = 2,
parameter INPUT_WIDTH = $clog2(OUTPUT_WIDTH)
) (
input [ INPUT_WIDTH-1:0] binary,
output [OUTPUT_WIDTH-1:0] one_hot
);
genvar i;
for (i = 0; i < OUTPUT_WIDTH; i = i + 1) begin
assign one_hot[i] = binary == i;
end
endmodule
| 6.76573 |
module bin_to_7seg (
bin,
seg
);
input [3:0] bin;
output [6:0] seg;
reg [6:0] seg;
always @(bin) begin
case (bin)
4'h0: seg = 7'b1000000; // output = 0 indicates a lit segment
4'h1: seg = 7'b1111001; // ---0---
4'h2: seg = 7'b0100100; // | |
4'h3: seg = 7'b0110000; // 5 1
4'h4: seg = 7'b0011001; // | |
4'h5: seg = 7'b0010010; // ---6---
4'h6: seg = 7'b0000010; // | |
4'h7: seg = 7'b1111000; // 4 2
4'h8: seg = 7'b0000000; // | |
4'h9: seg = 7'b0011000; // ---3---
4'ha: seg = 7'b0001000;
4'hb: seg = 7'b0000011;
4'hc: seg = 7'b1000110;
4'hd: seg = 7'b0100001;
4'he: seg = 7'b0000110;
4'hf: seg = 7'b0001110;
default: seg = 7'b1111111;
endcase
end
endmodule
| 6.806475 |
module bin_to_asc_hex (
in,
out
);
parameter METHOD = 1;
parameter WIDTH = 16;
localparam PAD_BITS = (WIDTH % 4) == 0 ? 0 : (4 - (WIDTH % 4));
localparam PADDED_WIDTH = WIDTH + PAD_BITS;
localparam NYBBLES = PADDED_WIDTH >> 2;
input [WIDTH-1:0] in;
output [8*NYBBLES-1:0] out;
wire [PADDED_WIDTH-1:0] padded_in = {{PAD_BITS{1'b0}}, in};
genvar i;
generate
for (i = 0; i < NYBBLES; i = i + 1) begin : h
wire [3:0] tmp_in = padded_in[4*(i+1)-1:4*i];
if (METHOD == 0) begin
// C style comparison.
wire [7:0] tmp_out;
assign tmp_out = (tmp_in < 10) ? ("0" | tmp_in) : ("A" + tmp_in - 10);
assign out[8*(i+1)-1:8*i] = tmp_out;
end else begin
/////////////////////////////////////
// METHOD = 1 is an equivalent case
// statement, to make the minimizations
// more obvious.
/////////////////////////////////////
reg [7:0] tmp_out;
always @(tmp_in) begin
case (tmp_in)
4'h0: tmp_out = 8'b00110000;
4'h1: tmp_out = 8'b00110001;
4'h2: tmp_out = 8'b00110010;
4'h3: tmp_out = 8'b00110011;
4'h4: tmp_out = 8'b00110100;
4'h5: tmp_out = 8'b00110101;
4'h6: tmp_out = 8'b00110110;
4'h7: tmp_out = 8'b00110111;
4'h8: tmp_out = 8'b00111000;
4'h9: tmp_out = 8'b00111001;
4'ha: tmp_out = 8'b01000001;
4'hb: tmp_out = 8'b01000010;
4'hc: tmp_out = 8'b01000011;
4'hd: tmp_out = 8'b01000100;
4'he: tmp_out = 8'b01000101;
4'hf: tmp_out = 8'b01000110;
endcase
end
assign out[8*(i+1)-1:8*i] = tmp_out;
end
end
endgenerate
endmodule
| 7.170833 |
module bin_to_asc_hex_tb ();
parameter WIDTH = 16;
parameter OUT_WIDTH = 4; // Number of nybbles in WIDTH
reg [WIDTH-1:0] in;
wire [8*OUT_WIDTH-1:0] oa, ob;
bin_to_asc_hex a (
.in (in),
.out(oa)
);
bin_to_asc_hex b (
.in (in),
.out(ob)
);
initial begin
#100000 $stop();
end
always begin
#100 in = $random;
#100 if (oa !== ob) $display("Disagreement at time %d", $time);
end
endmodule
| 7.170833 |
module bin_to_bcd (
bin,
bcd_t,
bcd_o
);
input [5:0] bin;
output [3:0] bcd_t, bcd_o;
reg [7:0] bcd;
reg [3:0] i;
//implements an algorithm for binary to bcd conversion
always @(bin) begin
bcd = 0;
for (i = 0; i < 6; i = i + 1) begin
bcd = {bcd[7:0], bin[5-i]};
if (i < 5 && bcd[3:0] > 4) bcd[3:0] = bcd[3:0] + 3;
if (i < 5 && bcd[7:4] > 4) bcd[7:4] = bcd[7:4] + 3;
end
end
assign bcd_t = bcd[7:4], //splitting the bcd result into 2 parts
bcd_o = bcd[3:0];
endmodule
| 7.085337 |
module bin_to_bcd_13 (
input wire [12:0] bin, // binary input
output reg [15:0] dec // BCD output
);
reg [12:0] b; // local copy of bin
integer i; // loop counter
always @* begin
b = bin;
dec = 13'd0;
for (i = 0; i < 12; i = i + 1) begin
// shift left dec and b
{dec, b} = {dec, b} << 1;
if (dec[3:0] > 4) // check units
dec[3:0] = dec[3:0] + 4'd3;
if (dec[7:4] > 4) // check tens
dec[7:4] = dec[7:4] + 4'd3;
if (dec[11:8] > 4) // check hundreds
dec[11:8] = dec[11:8] + 4'd3;
// thousands are never > 4
end
{dec, b} = {dec, b} << 1; // shift once more
end
endmodule
| 6.768218 |
module bin_to_bcd_14 (
input wire [13:0] bin, // binary input
output reg [15:0] dec // BCD output
);
reg [13:0] b; // local copy of bin
integer i; // loop counter
always @* begin
b = bin;
dec = 16'd0;
for (i = 0; i < 13; i = i + 1) begin
// shift left dec and b
{dec, b} = {dec, b} << 1;
if (dec[3:0] > 4) // check units
dec[3:0] = dec[3:0] + 4'd3;
if (dec[7:4] > 4) // check tens
dec[7:4] = dec[7:4] + 4'd3;
if (dec[11:8] > 4) // check hundreds
dec[11:8] = dec[11:8] + 4'd3;
if (dec[15:12] > 4) // check thousands
dec[15:12] = dec[15:12] + 4'd3;
end
{dec, b} = {dec, b} << 1; // shift once more
end
endmodule
| 6.819304 |
module bin_to_bcd_8 (
input wire [7:0] bin, // binary input
output reg [9:0] dec // BCD output
);
reg [7:0] b; // local copy of b
integer i; // loop counter
always @* begin
b = bin;
dec = 10'd0;
for (i = 0; i < 7; i = i + 1) begin
// shift left d and bi
{dec, b} = {dec, b} << 1;
if (dec[7:4] > 4) // check tens
dec[7:4] = dec[7:4] + 4'd3;
if (dec[3:0] > 4) // check units
dec[3:0] = dec[3:0] + 4'd3;
end
{dec, b} = {dec, b} << 1; // shift once more
end
endmodule
| 6.947695 |
module will separate the number in to decimal bits for the convenience of number display
Input: clk
rst_n
Output: tho
hun
ten
one
done
External resource found at https://blog.csdn.net/li200503028/article/details/19507061
originally created by stubben_bear
for design purpose the input bit are extended to 12 bits
modified by Yifan Cui
*/
module bin_dec(clk,bin,rst_n,one,ten,hun,tho,done
);
input [11:0] bin;
input clk,rst_n;
output [3:0] one,ten,hun;
output [2:0] tho;
output reg done;
reg [3:0] one,ten,hun;
reg [2:0] tho;
reg [3:0] count;
reg [26:0]shift_reg=27'b000_0000_0000_0000_0000_0000_0000;
////////////////////// counters ////////////////////////
always @ ( posedge clk or negedge rst_n )
begin
if( !rst_n )
count<=0;
else if (count==13)
count<=0;
else
count<=count+1'b1;
end
////////////////////// binary to decimal /////////////////
always @ (posedge clk or negedge rst_n )
begin
if (!rst_n)
shift_reg=0;
else if (count==0)
shift_reg={15'b000_0000_0000_0000,bin};
else if ( count<=13) //shift 8times
begin
if(shift_reg[15:12]>=5)//check if >5，if yes +3
begin
if(shift_reg[19:16]>=5) //check if the 10's bit >5，if yes +3
if(shift_reg[23:20]>=5)begin //check if the 100's bit >5，if yes +3
shift_reg[23:20]=shift_reg[23:20]+2'b11;
shift_reg[19:16]=shift_reg[19:16]+2'b11;
shift_reg[15:12]=shift_reg[15:12]+2'b11;
shift_reg=shift_reg<<1; //after finishing 100's bit, 10's bit and 1's bit，shift left
end
else begin
shift_reg[23:20]=shift_reg[23:20];
shift_reg[19:16]=shift_reg[19:16]+2'b11;
shift_reg[15:12]=shift_reg[15:12]+2'b11;
shift_reg=shift_reg<<1; //after finishing 10's bit and 1's bit，shift left
end
else begin
if(shift_reg[23:20]>=5)begin
shift_reg[23:20]=shift_reg[23:20]+2'b11;
shift_reg[19:16]=shift_reg[19:16];
shift_reg[15:12]=shift_reg[15:12]+2'b11;
shift_reg=shift_reg<<1;
end
end
end
else
begin
if(shift_reg[19:16]>=5) //check if the 10's bit >5，if yes +3
if(shift_reg[23:20]>=5)
begin //check if the 100's bit >5，if yes +3
shift_reg[23:20]=shift_reg[23:20]+2'b11;
shift_reg[19:16]=shift_reg[19:16]+2'b11;
shift_reg[15:12]=shift_reg[15:12];
shift_reg=shift_reg<<1; //after finishing 100's bit, 10's bit and 1's bit，shift left
end
else
begin
shift_reg[23:20]=shift_reg[23:20];
shift_reg[19:16]=shift_reg[19:16]+2'b11;
shift_reg[15:12]=shift_reg[15:12];
shift_reg=shift_reg<<1; //after finishing 10's bit and 1's bit，shift left
end
else
begin
if(shift_reg[23:20]>=5)begin
shift_reg[23:20]=shift_reg[23:20]+2'b11;
shift_reg[19:16]=shift_reg[19:16];
shift_reg[15:12]=shift_reg[15:12];
shift_reg=shift_reg<<1;
end
end
end
end
end
/////////////////outputs//////////////////////////
always @ ( posedge clk or negedge rst_n )
begin
if( !rst_n )
begin
one<=0;
ten<=0;
hun<=0;
tho<=0;
done = 1'b0;
end
else if (count==13) //finish shifting, set 100's, 10's, and 1's
begin
one<=shift_reg[15:12];
ten<=shift_reg[19:16];
hun<=shift_reg[23:20];
tho<=shift_reg[26:24];
done = 1'b1;
end
end
endmodule
| 6.776419 |
module bin_to_gray (
bin,
gray
);
parameter WIDTH = 8;
input [WIDTH-1:0] bin;
output [WIDTH-1:0] gray;
wire [WIDTH-1:0] gray;
assign gray = bin ^ (bin >> 1);
endmodule
| 6.875833 |
module bin_to_gray_using_decoder (
input [3:0] b_i, // Binary Input
output [3:0] g_o // Gray Output
);
wire [15:0] y; // Decoder output
// Instantiation
decoder_4_to_16 dut (
.i_i (b_i),
.en_i(1'b1),
.y_o (y)
);
or or_0 (g_o[0], y[1], y[2], y[5], y[6], y[9], y[10], y[13], y[14]);
or or_1 (g_o[1], y[2], y[3], y[4], y[5], y[10], y[11], y[12], y[13]);
or or_2 (g_o[2], y[4], y[5], y[6], y[7], y[8], y[9], y[10], y[11]);
or or_3 (g_o[3], y[8], y[9], y[10], y[11], y[12], y[13], y[14], y[15]);
endmodule
| 6.676721 |
module bin_to_gray_using_decoder_tb ();
// Signal Decleration
reg [3:0] b_i;
wire [3:0] g_o;
integer i;
// Instantiation
bin_to_gray_using_decoder dut (
.b_i(b_i),
.g_o(g_o)
);
// Logic to drive inputs and check outputs
initial begin
for (i = 0; i < 16; i = i + 1) begin
b_i = i;
#5;
// Display the output
$write($time, "ns Binary : %b, Gray : %b", b_i, g_o);
// Check output
if (g_o == (b_i ^ (b_i >> 1))) $display(" Pass");
else $display(" Fail");
end
#10 $finish;
end
endmodule
| 6.676721 |
module bin_to_onehot(
clk,
rst,
bin,
onehot
);
input clk;
input [BIN_WIDTH-1:0] bin;
output reg [ONEHOT_WIDTH-1:0] onehot;
parameter BIN_WIDTH = 4;
localparam ONEHOT_WIDTH = 2 << (BIN_WIDTH - 1);
genvar i;
generate
for(i=0; i < ONEHOT_WIDTH; i = i + 1)
begin: CONVERSION
always @(posedge clk)
onehot[i] = (i == bin)? 1'b1 : 1'b0;
end
endmodule
| 6.560098 |
module bin_to_real (
bin_speed,
real_speed,
direction,
clk
);
parameter width = 32;
parameter MAX_SPEED = 1000; //rotation per second
parameter SPEED_ONE = MAX_SPEED / 3;
parameter SPEED_TWO = MAX_SPEED / 2;
parameter SPEED_THREE = MAX_SPEED;
input [2:0] bin_speed; //3 bits: [direction speed1 speed0]
input clk;
output [width-1:0] real_speed;
output direction; // direction=bin_speed[2]
reg [width-1:0] real_speed;
reg direction;
always @(posedge clk) begin
direction = bin_speed[2];
case (bin_speed[1:0])
2'b00: real_speed = 0;
2'b01: real_speed = SPEED_ONE;
2'b10: real_speed = SPEED_TWO;
2'b11: real_speed = SPEED_THREE;
endcase
end //always
endmodule
| 6.90482 |
module bin_to_sseg (
// input wire CLOCK,
input wire [3:0] BIN,
output wire [6:0] HEX
);
assign HEX = (BIN == 4'b0000) ? 7'b1000000 : // 0
(BIN == 4'b0001) ? 7'b1111001 : // 1
(BIN == 4'b0010) ? 7'b0100100 : // 2
(BIN == 4'b0011) ? 7'b0110000 : // 3
(BIN == 4'b0100) ? 7'b0011001 : // 4
(BIN == 4'b0101) ? 7'b0010010 : // 5
(BIN == 4'b0110) ? 7'b0000010 : // 6
(BIN == 4'b0111) ? 7'b1111000 : // 7
(BIN == 4'b1000) ? 7'b0000000 : // 8
(BIN == 4'b1001) ? 7'b0010000 : // 9
(BIN == 4'b1010) ? 7'b1001000 : // n
(BIN == 4'b1011) ? 7'b0000011 : // b
(BIN == 4'b1100) ? 7'b1000110 : // c
(BIN == 4'b1101) ? 7'b0100001 : // d
(BIN == 4'b1110) ? 7'b0000110 : // e
7'b1111111; // off
endmodule
| 6.821705 |
module authorization (
auth,
check,
checkhash
);
input [7:0] auth;
input [7:0] checkhash;
output reg check;
always @(*) begin
// Simple logic of hash-match or not
if (auth == checkhash) check = 1;
else check = 0;
end
endmodule
| 6.518535 |
module test;
wire check;
reg [0:7] auth;
reg [0:7] checkhash;
authorization authen (
auth,
check,
checkhash
);
initial begin
$dumpfile("vcd/BiometricsImplement.vcd");
$dumpvars(0, test);
$display("Bytes \t Checker");
$monitor("%b %b", auth, check);
checkhash = 8'b11101101;
auth = 8'b10010110;
#10 auth = 8'b10110010;
#10 auth = 8'b11101101;
$finish;
end
endmodule
| 6.964054 |
module biosrom (
input clk,
input en,
input [8:0] addr,
output reg [31:0] data
);
reg [31:0] rom[0:511];
initial begin
`ifdef SIMULATION
$readmemh("../../../software/biosrom/biosrom.d32", rom, 0, 511);
`else
$readmemh("/home/tmatsuya/ipnuma/software/biosrom/biosrom.d32", rom, 0, 511);
`endif
end
always @(posedge clk) begin
if (en) data <= rom[addr];
end
endmodule
| 6.692556 |
module bios_integration_testbench ();
parameter SYSTEM_CLK_PERIOD = 8;
parameter SYSTEM_CLK_FREQ = 125_000_000;
reg sys_clk = 0;
reg sys_rst = 0;
always #(SYSTEM_CLK_PERIOD / 2) sys_clk <= ~sys_clk;
// UART Signals between the on-chip and off-chip UART
wire FPGA_SERIAL_RX, FPGA_SERIAL_TX;
// Off-chip UART Ready/Valid interface
reg [ 7:0] data_in;
reg data_in_valid;
wire data_in_ready;
wire [ 7:0] data_out;
wire data_out_valid;
reg data_out_ready;
reg [ 4:0] i = 0;
reg [8*`MSG_LENGTH:1] msg = "";
z1top #(
.SYSTEM_CLOCK_FREQ (SYSTEM_CLK_FREQ),
.B_SAMPLE_COUNT_MAX(5),
.B_PULSE_COUNT_MAX (5)
) top (
.CLK_125MHZ_FPGA(sys_clk),
.BUTTONS({3'b0, sys_rst}),
.SWITCHES(2'b0),
.LEDS(),
.FPGA_SERIAL_RX(FPGA_SERIAL_RX),
.FPGA_SERIAL_TX(FPGA_SERIAL_TX)
);
// Instantiate the off-chip UART
uart #(
.CLOCK_FREQ(SYSTEM_CLK_FREQ)
) off_chip_uart (
.clk(sys_clk),
.reset(sys_rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_in_ready(data_in_ready),
.data_out(data_out),
.data_out_valid(data_out_valid),
.data_out_ready(data_out_ready),
.serial_in(FPGA_SERIAL_TX),
.serial_out(FPGA_SERIAL_RX)
);
reg done = 0;
reg [31:0] cycle = 0;
initial begin
$readmemh("../../software/bios151v3/bios151v3.hex", top.cpu.bios_mem.mem, 0, 4095);
`ifndef IVERILOG
$vcdpluson;
`endif
`ifdef IVERILOG
$dumpfile("bios_integration_testbench.fst");
$dumpvars(0, bios_integration_testbench);
`endif
// Reset all parts
sys_rst = 1'b0;
data_in = 8'h7a;
data_in_valid = 1'b0;
data_out_ready = 1'b0;
repeat (20) @(posedge sys_clk);
#1;
sys_rst = 1'b1;
repeat (50) @(posedge sys_clk);
#1;
sys_rst = 1'b0;
fork
begin
// Wait for the off-chip UART to receive the '151>'
for (i = 0; i < `MSG_LENGTH; i = i + 1) begin
while (!data_out_valid) @(posedge sys_clk);
#1;
$display("Got %h", data_out);
msg = {msg[8*(`MSG_LENGTH-1):1], data_out};
// Clear the off-chip UART's receiver for another UART packet
data_out_ready = 1'b1;
@(posedge sys_clk);
#1;
data_out_ready = 1'b0;
end
$display("Recieved %s", msg);
done = 1;
end
begin
for (cycle = 0; cycle < 100000; cycle = cycle + 1) begin
if (done) $finish();
@(posedge sys_clk);
end
if (!done) begin
$display("Failed: timing out");
$finish();
end
end
join
`ifndef IVERILOG
$vcdplusoff;
`endif
$finish();
end
endmodule
| 7.101457 |
module bios_loader (
input wire clk,
input wire rst,
output reg [27:0] address,
output reg [ 3:0] byteenable,
output reg write,
output reg [31:0] writedata,
output reg read,
input wire [31:0] readdata,
input wire waitrequest
);
parameter PIO_OUTPUT_ADDR = 32'h00008860;
parameter DRIVER_SD_ADDR = 32'h00000000;
parameter BIOS_SECTOR = 72;
parameter BIOS_SIZE = (64 * 1024);
parameter BIOS_ADDR = 32'hF0000 | 32'h8000000;
parameter VBIOS_SECTOR = 8;
parameter VBIOS_SIZE = (32 * 1024);
parameter VBIOS_ADDR = 32'hC0000 | 32'h8000000;
parameter CTRL_READ = 2;
reg [31:0] state;
always @(posedge clk) begin
if (rst) state <= 1;
else if (state != 0 && (!(waitrequest && write))) state <= state + 1;
end
always @(posedge clk) begin
if (rst) begin
write <= 0;
read <= 0;
writedata <= 0;
address <= 0;
byteenable <= 4'b0000;
end else if (!(waitrequest && write)) begin
case (state)
20000000: begin
// set pio_output to 1 (set ao486_reset to low)
address <= PIO_OUTPUT_ADDR;
writedata <= 32'h1;
write <= 1;
end
20001000: begin
// load bios
// bios address
write <= 1;
address <= DRIVER_SD_ADDR;
writedata <= BIOS_ADDR;
end
20002000: begin
// load bios
// SD sector
write <= 1;
address <= DRIVER_SD_ADDR + 4;
writedata <= BIOS_SECTOR;
end
20003000: begin
// load bios
// sector count
write <= 1;
address <= DRIVER_SD_ADDR + 8;
writedata <= BIOS_SIZE / 512;
end
20004000: begin
// load bios
// control READ
write <= 1;
address <= DRIVER_SD_ADDR + 12;
writedata <= CTRL_READ;
end
40004000: begin
// load vbios
// vbios address
write <= 1;
address <= DRIVER_SD_ADDR;
writedata <= VBIOS_ADDR;
end
40005000: begin
// load vbios
// SD sector
write <= 1;
address <= DRIVER_SD_ADDR + 4;
writedata <= VBIOS_SECTOR;
end
40006000: begin
// load vbios
// sector count
write <= 1;
address <= DRIVER_SD_ADDR + 8;
writedata <= VBIOS_SIZE / 512;
end
40007000: begin
// load vbios
// control READ
write <= 1;
address <= DRIVER_SD_ADDR + 12;
writedata <= CTRL_READ;
end
60007000: begin
// set pio_output to 0 (set ao486_reset to high)
address <= PIO_OUTPUT_ADDR;
writedata <= 32'h0;
write <= 1;
end
default: begin
write <= 0;
writedata <= 0;
address <= 0;
end
endcase
end
end
endmodule
| 6.971526 |
module bios_mem (
input clk,
input ena,
input [11:0] addra,
output reg [31:0] douta,
input enb,
input [11:0] addrb,
output reg [31:0] doutb
);
parameter DEPTH = 4096;
reg [31:0] mem[4096-1:0];
always @(posedge clk) begin
if (ena) begin
douta <= mem[addra];
end
end
always @(posedge clk) begin
if (enb) begin
doutb <= mem[addrb];
end
end
`define STRINGIFY_BIOS(x) `"x/../software/bios/bios.hex`"
`ifdef SYNTHESIS
initial begin
$readmemh(`STRINGIFY_BIOS(`ABS_TOP), mem);
end
`endif
endmodule
| 6.646569 |
module bios_sram (
input clka,
input ena,
input wea,
input [15:0] addra,
input [ 7:0] dina,
output reg [ 7:0] douta,
output reg [20:0] SRAM_ADDR,
inout [ 7:0] SRAM_DATA,
output reg SRAM_WE_n
);
reg [7:0] data;
assign SRAM_DATA = (ena && ~SRAM_WE_n) ? data : 8'bZZZZZZZZ;
always @(negedge clka)
if (ena) begin
SRAM_ADDR = {5'b00000, addra};
if (wea) begin
SRAM_WE_n <= 1'b0;
data <= dina;
end else begin
SRAM_WE_n <= 1'b1;
douta <= SRAM_DATA;
end
end
endmodule
| 7.086996 |
module bip39 (
input i_clk,
input i_reset_n,
input [31:0] i_random_seed
// input [31:0] i_entropy;
);
wire [ 7:0] w_random;
wire [13:0] w_rd_addr;
wire w_rd_en;
wire [ 7:0] w_q_data;
random random_inst0 (
.i_clk (i_clk),
.i_reset_n(i_reset_n),
.i_seed (),
.o_data (w_random)
);
bip39_table bip39_table_inst (
.address(w_rd_addr),
.clock (i_clk),
.rden (w_rd_en),
.q (w_q_data)
);
// sha256_transform #(.LOOP(LOOP)) sha256_inst (
// .clk (CLOCK_50),
// .feedback (1'b0),
// .cnt (6'd0),
// .rx_state (255'd0),
// .rx_input (data),
// .tx_hash (hash)
// );
endmodule
| 6.979845 |
module bipolar_stepper_motor_drive #(
parameter Q_WIDTH = 16, // 小数点サイズ
parameter MICROSTEP_WIDTH = 12,
parameter PAHSE_WIDTH = 2 + Q_WIDTH
) (
input wire reset,
input wire clk,
input wire microstep_en,
input wire nanostep_en,
input wire asyc_update_en,
input wire [PAHSE_WIDTH-1:0] phase,
output wire update,
output wire out_a,
output wire out_b
);
wire [1:0] out_val;
microstep_pwm_control #(
.PAHSE_WIDTH (2 + Q_WIDTH),
.Q_WIDTH (Q_WIDTH),
.OUTPUT_WIDTH (2),
.MICROSTEP_WIDTH(MICROSTEP_WIDTH)
) i_microstep_pwm_control (
.reset(reset),
.clk (clk),
.microstep_en (microstep_en),
.nanostep_en (nanostep_en),
.asyc_update_en(asyc_update_en),
.phase (phase),
.update(update),
.out_val(out_val)
);
reg [1:0] reg_out;
always @(posedge clk) begin
if (reset) begin
reg_out <= 2'b00;
end else begin
case (out_val)
2'd0: reg_out <= 2'b00;
2'd1: reg_out <= 2'b01;
2'd2: reg_out <= 2'b11;
2'd3: reg_out <= 2'b10;
endcase
end
end
assign out_a = reg_out[0];
assign out_b = reg_out[1];
endmodule
| 7.038099 |
module bip_calculator #(
parameter LEN_CODED_BLOCK = 66,
parameter AM_ENCODING_LOW = 24'd0, //{M0,M1,M2} tabla 82-2
parameter AM_ENCODING_HIGH = 24'd0, //{M4,M5,M6} tabla 82-2
parameter NB_BIP = 8
) (
input wire i_clock,
input wire i_reset,
input wire [LEN_CODED_BLOCK-1 : 0] i_data,
input wire i_enable,
input wire i_am_insert,
output wire [NB_BIP-1 : 0] o_bip3,
output wire [NB_BIP-1 : 0] o_bip7
);
localparam CTRL_SH = 2'b10;
//INTERNAL SIGNALS
integer i;
reg [0 : LEN_CODED_BLOCK-1] data;
reg [NB_BIP-1 : 0] bip, bip_next, bip_rst;
reg [0 : LEN_CODED_BLOCK-1] am_inv;
reg [ LEN_CODED_BLOCK-1:0] am_block;
//PORTS
assign o_bip3 = bip;
assign o_bip7 = ~bip;
//Update state
always @(posedge i_clock) begin
if (i_reset) //[CHECK]
bip <= {8{1'b1}};
else if (i_enable && ~i_am_insert) bip <= bip_next;
else if (i_enable && i_am_insert) bip <= bip_rst;
end
//Parity calculation
always @* begin
bip_next = bip[NB_BIP-1 : 0];
bip_rst = {NB_BIP{1'b1}};
//am_block = data <= {CTRL_SH,AM_ENCODING_LOW,bip,AM_ENCODING_HIGH,~bip};
am_block = {CTRL_SH, AM_ENCODING_LOW, bip, AM_ENCODING_HIGH, ~bip};
am_inv = am_block;
data = i_data;
for (i = 0; i < ((LEN_CODED_BLOCK - 2) / 8); i = i + 1) begin
bip_next[0] = bip_next[0] ^ data[2+(8*i)];
bip_next[1] = bip_next[1] ^ data[3+(8*i)];
bip_next[2] = bip_next[2] ^ data[4+(8*i)];
bip_next[3] = bip_next[3] ^ data[5+(8*i)];
bip_next[4] = bip_next[4] ^ data[6+(8*i)];
bip_next[5] = bip_next[5] ^ data[7+(8*i)];
bip_next[6] = bip_next[6] ^ data[8+(8*i)];
bip_next[7] = bip_next[7] ^ data[9+(8*i)];
end
bip_next[3] = bip_next[3] ^ data[0];
bip_next[4] = bip_next[4] ^ data[1];
for (i = 0; i < ((LEN_CODED_BLOCK - 2) / 8); i = i + 1) begin
bip_rst[0] = bip_rst[0] ^ am_inv[2+(8*i)];
bip_rst[1] = bip_rst[1] ^ am_inv[3+(8*i)];
bip_rst[2] = bip_rst[2] ^ am_inv[4+(8*i)];
bip_rst[3] = bip_rst[3] ^ am_inv[5+(8*i)];
bip_rst[4] = bip_rst[4] ^ am_inv[6+(8*i)];
bip_rst[5] = bip_rst[5] ^ am_inv[7+(8*i)];
bip_rst[6] = bip_rst[6] ^ am_inv[8+(8*i)];
bip_rst[7] = bip_rst[7] ^ am_inv[9+(8*i)];
end
bip_rst[3] = bip_rst[3] ^ am_inv[0];
bip_rst[4] = bip_rst[4] ^ am_inv[1];
end
endmodule
| 7.118397 |
module bip_calculator #(
parameter LEN_CODED_BLOCK = 66,
parameter NB_BIP = 8
) (
input wire i_clock,
input wire i_reset,
input wire [LEN_CODED_BLOCK-1 : 0] i_data,
input wire i_enable,
input wire i_am_insert,
input wire [ NB_BIP-1 : 0] i_bip,
output wire [NB_BIP-1 : 0] o_bip3,
output wire [NB_BIP-1 : 0] o_bip7
);
//INTERNAL SIGNALS
integer i;
reg [0 : LEN_CODED_BLOCK-1] data;
reg [NB_BIP-1 : 0] bip, bip_next;
//PORTS
//assign o_bip3 = bip;
assign o_bip3 = bip_next;
assign o_bip7 = ~bip;
//Update state
always @(posedge i_clock) begin
if (i_reset || i_am_insert) //[CHECK]
bip <= {8{1'b1}};
else if (i_enable) bip <= bip_next;
end
//Parity calculation
always @* begin
//bip_next = bip[NB_BIP-1 : 0];
if (i_am_insert) bip_next = {NB_BIP{1'b1}};
else bip_next = i_bip;
data = i_data;
for (i = 0; i < ((LEN_CODED_BLOCK - 2) / 8); i = i + 1) begin
bip_next[0] = bip_next[0] ^ data[2+(8*i)];
bip_next[1] = bip_next[1] ^ data[3+(8*i)];
bip_next[2] = bip_next[2] ^ data[4+(8*i)];
bip_next[3] = bip_next[3] ^ data[5+(8*i)];
bip_next[4] = bip_next[4] ^ data[6+(8*i)];
bip_next[5] = bip_next[5] ^ data[7+(8*i)];
bip_next[6] = bip_next[6] ^ data[8+(8*i)];
bip_next[7] = bip_next[7] ^ data[9+(8*i)];
end
bip_next[3] = bip_next[3] ^ data[0];
bip_next[4] = bip_next[4] ^ data[1];
/*
if(i_enable)
begin
for(i=0; i<((LEN_CODED_BLOCK-2)/8); i=i+1)
begin
bip_next[0] = bip_next[0] ^ data[2+(8*i)] ;
bip_next[1] = bip_next[1] ^ data[3+(8*i)] ;
bip_next[2] = bip_next[2] ^ data[4+(8*i)] ;
bip_next[3] = bip_next[3] ^ data[5+(8*i)] ;
bip_next[4] = bip_next[4] ^ data[6+(8*i)] ;
bip_next[5] = bip_next[5] ^ data[7+(8*i)] ;
bip_next[6] = bip_next[6] ^ data[8+(8*i)] ;
bip_next[7] = bip_next[7] ^ data[9+(8*i)] ;
end
bip_next[3] =bip_next[3] ^ data[0];
bip_next[4] =bip_next[4] ^ data[1];
end
*/
end
endmodule
| 7.118397 |
module biquad_filter #(
parameter io_width = 16,
parameter internal_width = io_width * 2
) (
input wire clk,
input wire reset,
input wire en,
input wire signed [io_width-1:0] b0,
input wire signed [io_width-1:0] b1,
input wire signed [io_width-1:0] b2,
input wire signed [io_width-1:0] q,
input wire signed [io_width-1:0] a1,
input wire signed [io_width-1:0] a2,
input wire signed [io_width-1:0] x,
output wire signed [io_width-1:0] y
);
reg signed [io_width-1:0] xin;
reg signed [io_width-1:0] x_n1, x_n2;
reg signed [io_width-1:0] y_n1, y_n2;
wire signed [internal_width-1:0] pb0, pb1, pb2;
wire signed [internal_width-1:0] pa1, pa2;
wire [5:0] l;
//wire signed[15:0] pd_check0, pd_check1, pd_check2, pd_check3, pd_check4, pd_check5;
assign pb0 = b0 * xin;
assign pb1 = b1 * x_n1;
assign pb2 = b2 * x_n2;
assign pa1 = a1 * y_n1;
assign pa2 = a2 * y_n2;
always @(posedge clk, posedge reset) begin
if (reset) xin <= 0;
else begin
if (en) xin <= x;
end
end
always @(posedge clk, posedge reset) begin
if (reset) x_n1 <= 0;
else begin
if (en) x_n1 <= xin;
end
end
always @(posedge clk, posedge reset) begin
if (reset) x_n2 <= 0;
else begin
if (en) x_n2 <= x_n1;
end
end
assign y = (pb0 + pb1 + pb2 - pa1 - pa2) >>> q[3:0];
always @(posedge clk, posedge reset) begin
if (reset) y_n1 <= 0;
else begin
if (en) y_n1 <= y;
end
end
always @(posedge clk, posedge reset) begin
if (reset) y_n2 <= 0;
else begin
if (en) y_n2 <= y_n1;
end
end
/* `ifdef COCOTB_SIM
initial begin
$dumpfile ("biquad.vcd");
$dumpvars(0);
#1;
end
`endif
*/
endmodule
| 6.722098 |
module biquad_filter #(
parameter io_width = 16,
parameter internal_width = io_width * 2 - 1
) (
input wire clk,
input wire reset,
input wire en,
input wire signed [io_width-1:0] b0,
input wire signed [io_width-1:0] b1,
input wire signed [io_width-1:0] b2,
input wire signed [io_width-1:0] q,
input wire signed [io_width-1:0] a1,
input wire signed [io_width-1:0] a2,
input wire signed [io_width-1:0] x,
output wire signed [io_width-1:0] y
);
localparam signed [io_width-1:0] a0 = 16384;
reg signed [io_width-1:0] xin;
wire signed [io_width-1:0] w_n;
reg signed [io_width-1:0] w_n1, w_n2;
wire signed [internal_width-1:0] pd0, pd1, pd2, pd3, pd4, pd5;
//wire signed[15:0] pd_check0, pd_check1, pd_check2, pd_check3, pd_check4, pd_check5;
assign pd0 = a0 * xin;
assign pd1 = a1 * w_n1;
assign pd2 = a2 * w_n2;
always @(posedge clk, posedge reset) begin
if (reset) xin <= 0;
else begin
if (en) xin <= x;
end
end
assign w_n = (pd0 - pd1 - pd2) >>> q[3:0];
always @(posedge clk, posedge reset) begin
if (reset) w_n1 <= 0;
else begin
if (en) w_n1 <= w_n;
end
end
always @(posedge clk, posedge reset) begin
if (reset) w_n2 <= 0;
else begin
if (en) w_n2 <= w_n1;
end
end
assign pd3 = b0 * w_n;
assign pd4 = b1 * w_n1;
assign pd5 = b2 * w_n2;
assign y = ((pd3 + pd4 + pd5) >>> (2 * q[3:0] - io_width));
/* `ifdef COCOTB_SIM
initial begin
$dumpfile ("biquad.vcd");
$dumpvars(0);
#1;
end
`endif*/
endmodule
| 6.722098 |
module bird (
input clk,
input frameclk,
input up,
input down,
input [2:0] state,
input [5:0] count,
input [10:0] pos_x,
input [10:0] pos_y,
input sw0,
output reg isbird,
output reg [3:0] birdr,
output reg [3:0] birdg,
output reg [3:0] birdb,
output reg [10:0] birdx,
output reg [10:0] birdy
);
// for image handling
reg [17:0] pic_addr;
reg [11:0] pic_color;
wire [11:0] pic1;
wire [11:0] pic2;
// init position of bird, left top corner
initial begin
birdx = 420;
birdy = 460;
end
always @(posedge frameclk) begin // det bird moving
if (state[1]) begin // if is playing
if (up) birdy <= birdy - 11'd8;
else if (down) birdy <= birdy + 11'd8;
else if (sw0) birdy <= birdy; // cheat code, prevent bird falling
else birdy <= birdy + 11'd3;
end else birdy <= 11'd460; // reset position
end
always @(posedge clk) begin
if((pos_x >= birdx) && (pos_x <= (birdx+84)) && (pos_y >= birdy) && (pos_y <= (birdy+90))) begin
isbird <= 1'b1;
pic_addr <= ((pos_y - birdy) * 84 + (pos_x - birdx - 1));
birdr <= pic_color[11:8];
birdg <= pic_color[7:4];
birdb <= pic_color[3:0];
end else begin
isbird <= 1'b0;
birdr <= 4'h7;
birdg <= 4'hc;
birdb <= 4'hc;
pic_addr <= 1;
end
end
always @(posedge clk) begin
if (count <= 30) pic_color <= pic1;
else pic_color <= pic2;
end
ghost1 ghost1 (
.clka(clk), // input wire clka
.addra(pic_addr), // input wire [12 : 0] addra
.douta(pic1) // output wire [11 : 0] douta
);
ghost2 ghost2 (
.clka(clk), // input wire clka
.addra(pic_addr), // input wire [12 : 0] addra
.douta(pic2) // output wire [11 : 0] douta
);
endmodule
| 7.107135 |
module bridge (
input [31:0] PrAddr,
input [31:0] PrWD,
output [31:0] PrRD,
input [31:0] rd1,
input [31:0] rd2,
input [31:0] rd3,
input IRQ,
output [5:0] HWInt,
input wen,
output outwe,
output twe
);
wire HitDEV_timer, HitDEV_output, HitDEV_input;
assign HWInt = {5'b0, IRQ};
assign twe = wen && (PrAddr[31:4] == 'h00007F0);
assign HitDEV_timer = (PrAddr[31:4] == 'h00007F0);
assign outwe = wen && (PrAddr[31:4] == 'h00007F1);
assign HitDEV_output = (PrAddr[31:4] == 'h00007F1);
assign HitDEV_input = (PrAddr == 'h00007F20);
//0:COUNTER 1:OUTPUT 2:INPUT
assign PrRD = (HitDEV_timer) ? rd1 : (HitDEV_output) ? rd2 : (HitDEV_input) ? rd3 : PrWD;
endmodule
| 8.006498 |
module birdPosition_17 (
input clk,
input rst,
input btn,
output reg [7:0] outPosition
);
wire [16-1:0] M_alu_out;
wire [ 1-1:0] M_alu_overflow;
reg [16-1:0] M_alu_a;
reg [16-1:0] M_alu_b;
reg [ 6-1:0] M_alu_alufn;
alu_3 alu (
.a(M_alu_a),
.b(M_alu_b),
.alufn(M_alu_alufn),
.out(M_alu_out),
.overflow(M_alu_overflow)
);
reg [7:0] M_position_d, M_position_q = 8'h10;
always @* begin
M_position_d = M_position_q;
M_alu_a = M_position_q;
M_alu_b = 1'h1;
outPosition = M_position_q;
if (btn == 1'h1) begin
M_alu_alufn = 17'h186a0;
M_position_d = M_alu_out;
end else begin
M_alu_alufn = 17'h186a1;
M_position_d = M_alu_out;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_position_q <= 8'h10;
end else begin
M_position_q <= M_position_d;
end
end
endmodule
| 6.803567 |
module: bird
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bird_tb;
// Inputs
reg clk;
reg rst;
reg enable;
reg jump;
reg [1:0] fall_accel;
reg state;
// Outputs
wire [9:0] y_coord;
// Instantiate the Unit Under Test (UUT)
bird uut (
.clk(clk),
.rst(rst),
.enable(enable),
.jump(jump),
.state(state),
.fall_accel(fall_accel),
.y_coord(y_coord)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
enable = 1;
jump = 1;
fall_accel = 1;
state = 0;
// Wait 100 ns for global reset to finish
#100;
state = 1;
enable = 1;
clk = 0;
rst = 0;
enable = 1;
jump = 0;
fall_accel = 1;
//jump = 1;
// Add stimulus here
end
always #5 clk = ~clk;
endmodule
| 7.199531 |
module biriscv_lsu_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input [WIDTH-1:0] data_in_i
, input push_i
, input pop_i
// Outputs
, output [WIDTH-1:0] data_out_o
, output accept_o
, output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
integer i;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
if (rst_i) begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
for (i = 0; i < DEPTH; i = i + 1) begin
ram_q[i] <= {(WIDTH) {1'b0}};
end
end else begin
// Push
if (push_i & accept_o) begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o) rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o)) count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o)) count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
| 7.011414 |
module biriscv_npc_lfsr
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter DEPTH = 32
, parameter ADDR_W = 5
, parameter INITIAL_VALUE = 16'h0001
, parameter TAP_VALUE = 16'hB400
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
, input rst_i
, input hit_i
, input [ADDR_W-1:0] hit_entry_i
, input alloc_i
// Outputs
, output [ADDR_W-1:0] alloc_entry_o
);
//-----------------------------------------------------------------
// Scheme: LFSR
//-----------------------------------------------------------------
reg [15:0] lfsr_q;
always @(posedge clk_i or posedge rst_i)
if (rst_i) lfsr_q <= INITIAL_VALUE;
else if (alloc_i) begin
if (lfsr_q[0]) lfsr_q <= {1'b0, lfsr_q[15:1]} ^ TAP_VALUE;
else lfsr_q <= {1'b0, lfsr_q[15:1]};
end
assign alloc_entry_o = lfsr_q[ADDR_W-1:0];
endmodule
| 6.91699 |
module RAM16X1D (
DPO,
SPO,
A0,
A1,
A2,
A3,
D,
DPRA0,
DPRA1,
DPRA2,
DPRA3,
WCLK,
WE
);
parameter INIT = 16'h0000;
output DPO, SPO;
input A0, A1, A2, A3, D, DPRA0, DPRA1, DPRA2, DPRA3, WCLK, WE;
reg [15:0] mem;
wire [ 3:0] adr;
assign adr = {A3, A2, A1, A0};
assign SPO = mem[adr];
assign DPO = mem[{DPRA3, DPRA2, DPRA1, DPRA0}];
initial mem = INIT;
always @(posedge WCLK) if (WE == 1'b1) mem[adr] <= D;
endmodule
| 7.214201 |
module is taken from:
// Implementations/crypto_aead/drygascon128/add_verilog/drygascon128_1round_cycle/drygascon128_ACC_PIPE_MIX_SHIFT_REG.v
// source: (sebastien-riou/DryGascon)[https://github.com/sebastien-riou/DryGASCON]
`timescale 1ns / 1ps
`default_nettype none
module birotr(
input wire [64-1:0] din,
input wire [ 6-1:0] shift,
output reg [64-1:0] out
);
wire [32-1:0] i0 = din[0*32+:32];
wire [32-1:0] i1 = din[1*32+:32];
wire [ 6-1:0] shift2 = shift>>1;
wire [ 6-1:0] shift3 = (shift2 + 1'b1) % 6'd32;
always @* begin
if(shift & 1'b1) begin
out[ 0+:32] = (i1>>shift2) | (i1 << (6'd32-shift2));
out[32+:32] = (i0>>shift3) | (i0 << (6'd32-shift3));
end else begin
out[ 0+:32] = (i0>>shift2) | (i0 << (6'd32-shift2));
out[32+:32] = (i1>>shift2) | (i1 << (6'd32-shift2));
end
end
endmodule
| 7.591788 |
module bistable_domain_cross (
rst,
clk_a,
in,
clk_b,
out
);
parameter width = 1;
input rst;
input clk_a;
input [width-1:0] in;
input clk_b;
output [width-1:0] out;
// We use a two-stages shift-register to synchronize in to the clk_b clock domain
reg [width-1:0] sync_clk_b[1:0];
always @(posedge clk_b or posedge rst) begin
if (rst == 1) begin
sync_clk_b[0] <= 0;
sync_clk_b[1] <= 0;
end else begin
sync_clk_b[0] <= in;
sync_clk_b[1] <= sync_clk_b[0];
end
end
assign out = sync_clk_b[1]; // new signal synchronized to (=ready to be used in) clk_b domain
endmodule
| 7.501432 |
module controller_new (
clk,
rst,
BIST_mode,
data_in,
finish,
fault_detected,
result_dut,
misr_output
);
input [8:0] data_in;
input clk; //clock
input rst; //reset
input finish; //finish flag
input BIST_mode; //BIST mode
output reg fault_detected; //fault detected flag
wire [3:0] a_dut; //4 bits of 9 bit LFSR output
wire [3:0] b_dut;
wire sel; //assign 1 bit of LFSR output to select
wire output_dut; //carry output of DUT
input [3:0] result_dut; //result of DUT fed to MISR for compaction to compare with the Golden Signature
parameter golden_signature = 4'b0101; // golden signature as derived from the tapping of LFSR bits
output [3:0] misr_output; //output of the misr
reg [3:0] a, b;
//port-mapping LFSR with controller
ML_lfsr lfsr (
.data_out(data_in),
.complete(finish),
.reset(rst),
.clock(clk)
);
//assignment of data_in bits to different bits of a, b and Sel
assign a_dut = data_in[8:5];
assign b_dut = data_in[4:1];
assign sel = data_in[0];
//port-mapping DUT with controller
AU DUT (
.A(a),
.B(b),
.Sel(sel),
.Result(result_dut),
.Output(output_dut)
);
//port-mapping MISR with controller
MISR_4bit MISR (
.dataIn (result_dut),
.reset (rst),
.clock (clk),
.dataOut(misr_output)
);
always @(posedge clk) begin
if (BIST_mode == 0) //when bist mode is not on, faults can't be detected
fault_detected = 0;
else begin
assign a = a_dut; //assigning values of a
assign b = b_dut; //assigning values of b
if (rst == 1) //when reset is high, faults can't be detected
fault_detected = 0;
else begin
if (finish == 1) begin
//match the golden signature with misr_output, if the mtch is found then fault is not detected and fault_detected bit is 0
if (golden_signature == misr_output) fault_detected = 0;
else fault_detected = 1;
end
end
end
end
endmodule
| 6.606807 |
module BIST_controller (
rst,
clk,
error,
pat_end,
count_end,
nxt_pat,
nxt_count,
tst_state,
tst_pass,
tst_fail,
rst_count,
rst_pat,
tst_count[1]
);
input rst;
input clk;
input error;
input pat_end;
input count_end;
output nxt_pat;
output reg nxt_count;
output reg tst_state;
output reg tst_pass;
output reg tst_fail;
output rst_count;
output rst_pat;
output reg [1:0] tst_count;
reg rst_2nd_test;
reg mode;
assign nxt_pat = count_end;
assign rst_pat = rst | rst_2nd_test;
assign rst_count = rst | count_end | rst_2nd_test;
always @(posedge clk) begin
if (rst_2nd_test) rst_2nd_test <= ~rst_2nd_test;
if (rst) begin
mode = 1;
tst_pass = 0;
tst_fail = 0;
nxt_count = 0;
tst_count = 0;
rst_2nd_test = 0;
end
tst_state <= mode & ~rst;
if (tst_state) begin
if (pat_end | error) begin
mode = 0;
tst_pass <= pat_end;
tst_fail <= error;
nxt_count = 0;
tst_count <= tst_count + 1;
end else begin
nxt_count = mode;
end
end
if (~tst_state & tst_fail & tst_count[1]) begin
mode = 1;
nxt_count = 0;
rst_2nd_test = 1;
end
end
endmodule
| 6.687146 |
module BIST_controller_tb ();
reg b_rst;
reg b_clk;
reg b_error;
reg b_pat_end;
reg b_count_end;
wire b_nxt_pat;
wire b_nxt_count;
wire b_tst_state;
wire b_tst_pass;
wire b_tst_fail;
wire b_rst_count;
wire b_rst_pat;
BIST_controller My_BIST (
b_rst,
b_clk,
b_error,
b_pat_end,
b_count_end,
b_nxt_pat,
b_nxt_count,
b_tst_state,
b_tst_pass,
b_tst_fail,
b_rst_count,
b_rst_pat
);
initial begin
b_clk = 1'b0;
forever #50 b_clk = ~b_clk;
end
initial begin
b_rst = 0;
#1000 b_rst = 1;
#500 b_rst = 0;
#200 b_count_end = 1;
#100 b_count_end = 0;
#300 b_pat_end = 1;
#200 b_error = 1;
end
endmodule
| 6.687146 |
module BIST_MUX (
input wire [7:0] user_input,
input wire [7:0] BIST_input,
input wire select, //1 for BIST 0 for user input
output wire [7:0] out
);
reg [7:0] out_temp;
always @(*) begin
if (select == 0) out_temp = user_input;
else out_temp = BIST_input;
end
assign out = out_temp;
endmodule
| 7.971307 |
module BIST_tb;
localparam clk_period = 20;
reg clk;
reg [3:0] select;
integer i;
wire [3:0] dat_in;
wire [3:0] dat_out;
wire [7:0] addr_out;
wire op_done, w_en;
BIST_engine_top BIST (
.select(select),
.dat_out(dat_out),
.dat_in(dat_in),
.addr_out(addr_out),
.w_en(w_en),
.clk(clk),
.op_done(op_done)
);
SRAM sram_1 (
.dat_in(dat_out),
.addr_in(addr_out),
.w_en(w_en),
.clk(clk),
.read_d(dat_in)
);
initial begin
clk = 0;
#100;
select = 4'b0001;
end
always @(posedge clk) begin
i = 0;
if (select == 7) begin
select = 0;
end
if (op_done) begin
select = select + 1;
for (i = 0; i < 50; i = i + 1) begin
@(posedge clk) begin
end
end
end
end
//Clocking
always begin
#(clk_period / 2) clk = ~clk;
end
endmodule
| 6.721843 |
module bist_test;
// Inputs
reg clk;
wire rst_n;
wire sck_transition;
reg [11:0] rf_bist_start_val;
reg [ 7:0] rf_bist_inc;
reg [11:0] rf_bist_up_limit;
// Internal Variables
reg i2si_sck;
reg sck_d1; // serial clock delay
reg [31:0] count;
reg [31:0] sck_cnt; // serial clock counter
reg [31:0] cyc_per_half_sck = 40; // about (100 MHz / 1.44 MHz)/2
// Outputs
wire [31:0] i2si_bist_out_data;
wire i2si_bist_out_xfc;
// Instantiate the Unit Under Test (UUT)
i2si_bist_gen uut (
.clk(clk),
.rst_n(rst_n),
.sck_transition(sck_transition),
.rf_bist_start_val(rf_bist_start_val),
.rf_bist_inc(rf_bist_inc),
.rf_bist_up_limit(rf_bist_up_limit),
.i2si_bist_out_data(i2si_bist_out_data),
.i2si_bist_out_xfc(i2si_bist_out_xfc)
);
initial begin
// Initialize Inputs
clk = 0;
i2si_sck = 0;
rf_bist_start_val = 12'h001;
rf_bist_inc = 12'h001;
rf_bist_up_limit = 12'h019;
end
always begin
count = 0; // set clock counter to zero
forever begin
#5 clk = ~clk; // 100 MHz clock
count = count + 1; // increment clock counter
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sck_cnt<=0; // counts master clock cycles, causes sck to toggle each time it hits cyc_per_half_sck
i2si_sck <= 0; // serial clock
sck_d1 <= 0; // serial clock delayed by one clock cycle
end else sck_cnt <= sck_cnt + 1; // increment serial clock counter
sck_d1 <= i2si_sck; // generate 1 cycle delay of i2si_sck
if (sck_cnt == cyc_per_half_sck-1) // cyc_per_half_sck ~ (100 MHz/1.44 MHz)/2
begin
sck_cnt <= 0; // reset serial clock counter
i2si_sck <= ~i2si_sck; // toggle serial clock
end
end
assign sck_transition = i2si_sck & ~sck_d1;
assign rst_n = !(count < 20);
endmodule
| 6.52078 |
module BIST_TestBench ();
reg [2:0] What_Do_You_Want_To_Check;
reg clk, WE;
reg [7:0] Address;
reg [3:0] Data_Input;
wire [3:0] Data_output;
wire GoNoGo;
Full_BIST dut (
.What_Do_You_Want_To_Check(What_Do_You_Want_To_Check),
.clk(clk),
.WE(WE),
.Address(Address),
.Data_Input(Data_Input),
.Data_output(Data_output),
.GoNoGo(GoNoGo)
);
always begin
clk = 1;
#5;
clk = 0;
#5;
end
initial begin
What_Do_You_Want_To_Check <= 0;
#12000;
What_Do_You_Want_To_Check <= 1;
#20000;
What_Do_You_Want_To_Check <= 2;
#30000;
What_Do_You_Want_To_Check <= 3;
#40000;
end
endmodule
| 6.628833 |
module BIST_engine_top (
output [7:0] addr_out,
output [3:0] dat_out,
input [3:0] dat_in,
output w_en,
op_done,
input [3:0] select,
input clk
);
wire [3:0] dat_out_bg0;
wire [7:0] add_out_bg0;
wire w_en_bg0, rst_done_bg0, rev_out_bg0;
wire [3:0] dat_out_c1;
wire [7:0] add_out_c1;
wire w_en_c1, rst_done_c1, rev_out_c1;
wire [3:0] dat_out_mc;
wire [7:0] add_out_mc;
wire w_en_mc, rst_done_mc, rev_out_mc;
wire [3:0] dat_out_mlr;
wire [7:0] add_out_mlr;
wire w_en_mlr, rst_done_mlr, rev_out_mlr;
reg [3:0] r_dat_out;
reg [7:0] r_add_out;
reg [3:0] r_select;
reg r_rst_done, r_w_en;
wire bg0, c1, mar_c, mar_lr;
localparam clk_period = 20;
control c_unit (
.select(select),
.rst_done(r_rst_done),
.clk(clk),
.bg0(bg0),
.mar_lr(mar_lr),
.c1(c1),
.mar_c(mar_c),
.rev_out(rev_out_c1),
.bln_out(rev_out_bg0)
);
blanket_0 bg_0 (
.dat_out(dat_out_bg0),
.addr_out(add_out_bg0),
.w_en_out(w_en_bg0),
.rst_done(rst_done_bg0),
.clk(clk),
.en_in(bg0),
.rev_in(rev_out_bg0)
);
chk_1 chk_for (
.dat_out(dat_out_c1),
.addr_out(add_out_c1),
.w_en_out(w_en_c1),
.rst_done(rst_done_c1),
.clk(clk),
.en_in(c1),
.rev_in(rev_out_c1)
);
March_C march_c (
.dat_out(dat_out_mc),
.addr_out(add_out_mc),
.dat_in(dat_in),
.w_en_out(w_en_mc),
.rst_done(rst_done_mc),
.clk(clk),
.en_in(mar_c)
);
March_LR march_lr (
.dat_out(dat_out_mlr),
.addr_out(add_out_mlr),
.dat_in(dat_in),
.w_en_out(w_en_mlr),
.rst_done(rst_done_mlr),
.clk(clk),
.en_in(mar_lr)
);
always @(posedge clk) begin
case (select)
1: begin
r_dat_out = dat_out_bg0;
r_add_out = add_out_bg0;
r_rst_done = rst_done_bg0;
r_w_en = w_en_bg0;
end
2: begin
r_dat_out = dat_out_bg0;
r_add_out = add_out_bg0;
r_rst_done = rst_done_bg0;
r_w_en = w_en_bg0;
end
3: begin
r_dat_out = dat_out_c1;
r_add_out = add_out_c1;
r_rst_done = rst_done_c1;
r_w_en = w_en_c1;
end
4: begin
r_dat_out = dat_out_c1;
r_add_out = add_out_c1;
r_rst_done = rst_done_c1;
r_w_en = w_en_c1;
end
5: begin
r_dat_out = dat_out_mc;
r_add_out = add_out_mc;
r_rst_done = rst_done_mc;
r_w_en = w_en_mc;
end
6: begin
r_dat_out = dat_out_mlr;
r_add_out = add_out_mlr;
r_rst_done = rst_done_mlr;
r_w_en = w_en_mlr;
end
default: begin
end
endcase
end
assign dat_out = r_dat_out;
assign addr_out = r_add_out;
assign w_en = r_w_en;
assign op_done = r_rst_done;
endmodule
| 7.744874 |
module BIST_tb;
localparam clk_period = 50;
reg clk;
reg [3:0] select;
reg [7:0] i;
wire [3:0] dat_in;
wire [3:0] dat_out;
wire [7:0] addr_out;
wire op_done, w_en;
BIST_engine_top BIST (
.select(select),
.dat_out(dat_out),
.dat_in(dat_in),
.addr_out(addr_out),
.w_en(w_en),
.clk(clk),
.op_done(op_done)
);
SRAM sram_1 (
.dat_in(dat_out),
.addr_in(addr_out),
.w_en(w_en),
.clk(clk),
.read_d(dat_in)
);
initial begin
clk = 0;
#100;
select = 4'b0001;
end
always @(posedge clk) begin
i = 0;
if (select == 7) begin
select = 0;
end
if (op_done) begin
select = select + 1;
for (i = 0; i < 50; i = i + 1) begin
@(posedge clk) begin
end
end
end
end
always begin
#(clk_period / 2) clk = ~clk;
end
endmodule
| 6.721843 |
module main (
clock
);
input clock;
reg [2:0] a, b;
initial a = 3'b010;
initial b = 3'b110;
always @(posedge clock) begin
a[2] <= b[0];
a[1:0] <= b[2:1];
b[2:1] <= a[1:0];
b[0] <= a[2];
end
endmodule
| 7.779865 |
module Bit (
input wire clk,
input wire in,
input wire load,
output wire out
);
// your implementation comes here:
// Mux(a=muxb, b=in, sel=load, out=muxo);
// DFF(in=muxo, out=out, out=muxb);
// reg muxb;
wire muxo;
Mux MUX (
.a (out),
.b (in),
.sel(load),
.out(muxo)
);
DFFusr DFF1 (
.clk(clk),
.in (muxo),
.out(out)
);
endmodule
| 7.70558 |
module Bit10MUX (
a,
b,
select,
out
);
input [10:1] a;
input [10:1] b;
input select;
output [10:1] out;
assign out[1] = ((!select) & a[1]) | ((select) & b[1]);
assign out[2] = ((!select) & a[2]) | ((select) & b[2]);
assign out[3] = ((!select) & a[3]) | ((select) & b[3]);
assign out[4] = ((!select) & a[4]) | ((select) & b[4]);
assign out[5] = ((!select) & a[5]) | ((select) & b[5]);
assign out[6] = ((!select) & a[6]) | ((select) & b[6]);
assign out[7] = ((!select) & a[7]) | ((select) & b[7]);
assign out[8] = ((!select) & a[8]) | ((select) & b[8]);
assign out[9] = ((!select) & a[9]) | ((select) & b[9]);
assign out[10] = ((!select) & a[10]) | ((select) & b[10]);
endmodule
| 8.337265 |
module Bit11Adder (
a,
b,
sum,
carry
);
input [11:1] a;
input [11:1] b;
output [11:1] sum;
output carry;
wire [10:1] w;
FullAdder fa_1 (
a[1],
b[1],
1'b0,
sum[1],
w[1]
);
FullAdder fa_2 (
a[2],
b[2],
w[1],
sum[2],
w[2]
);
FullAdder fa_3 (
a[3],
b[3],
w[2],
sum[3],
w[3]
);
FullAdder fa_4 (
a[4],
b[4],
w[3],
sum[4],
w[4]
);
FullAdder fa_5 (
a[5],
b[5],
w[4],
sum[5],
w[5]
);
FullAdder fa_6 (
a[6],
b[6],
w[5],
sum[6],
w[6]
);
FullAdder fa_7 (
a[7],
b[7],
w[6],
sum[7],
w[7]
);
FullAdder fa_8 (
a[8],
b[8],
w[7],
sum[8],
w[8]
);
FullAdder fa_9 (
a[9],
b[9],
w[8],
sum[9],
w[9]
);
FullAdder fa_10 (
a[10],
b[10],
w[9],
sum[10],
w[10]
);
FullAdder fa_11 (
a[11],
b[11],
w[10],
sum[11],
carry
);
endmodule
| 7.58013 |
module Bit11Adder (
a,
b,
sum,
carry
);
input [11:1] a;
input [11:1] b;
output [11:1] sum;
output carry;
wire [16:1] A, B, SUM;
wire CARRY;
assign A[11:1] = a;
assign A[16:12] = 5'b00000;
assign B[11:1] = b;
assign B[16:12] = 5'b00000;
RDAdder addr (
A,
B,
1'b0,
SUM,
CARRY
);
assign sum = SUM[11:1];
assign carry = SUM[12];
endmodule
| 7.58013 |
module bit2byte(
clk ,
reset_n ,
ldpc_en_out ,
ldpc_dout ,
ts0_win, ,
ts1_win, ,
byte_sync ,
byte_data ,
byte_win0 ,
byte_win1 ,
ts0_new ,
ts1_new
);
//inputs
input clk ;
input reset_n ;
input ldpc_en_out ;
input ldpc_dout ;
input ts0_win ;
input ts1_win ;
output byte_sync ;
output [7:0] byte_data ;
output byte_win0 ;
output byte_win1 ;
output ts0_new ;
output ts1_new ;
reg [2:0] counter ;
reg [7:0] byte_data ;
reg byte_sync ;
reg byte_win0 ;
reg byte_win1 ;
reg ts0_new ;
reg ts1_new ;
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
counter <= #1 3'b0;
else if(ldpc_en_out & (ts0_win | ts1_win) )
counter <= #1 counter + 1'b1;
// else
// counter <= #1 3'b0;
end
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
byte_data <= #1 8'h0;
else if(ldpc_en_out)
byte_data <= #1 {ldpc_dout, byte_data[7:1]};
// else
// byte_data <= #1 8'h0;
end
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
byte_sync <= #1 1'b0;
else if(counter == 3'b111)
byte_sync <= #1 1'b1;
else
byte_sync <= #1 1'b0;
end
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
byte_win0 <= #1 1'b0;
else if(!ts0_win)
byte_win0 <= #1 1'b0;
else if(counter === 3'b111)
byte_win0 <= #1 1'b1;
end
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
byte_win1 <= #1 1'b0;
else if(!ts1_win)
byte_win1 <= #1 1'b0;
else if(counter === 3'b111)
byte_win1 <= #1 1'b1;
end
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
ts0_new <= #1 1'b0;
else
ts0_new <= #1 ts0_win & ldpc_en_out;
end
always @ (posedge clk or negedge reset_n)
begin
if(!reset_n)
ts1_new <= #1 1'b0;
else
ts1_new <= #1 ts1_win & ldpc_en_out;
end
endmodule
| 6.725177 |
module bit32and (
out,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
assign {out} = in1 & in2;
endmodule
| 8.092568 |
module bit32not (
not_a,
a
);
input [31:0] a;
output [31:0] not_a;
assign not_a = ~a;
endmodule
| 8.283339 |
module bit32or (
out,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
assign {out} = in1 | in2;
endmodule
| 6.970673 |
module bit32_2to1mux (
out,
sel,
in1,
in2
);
input [31:0] in1, in2;
input sel;
output [31:0] out;
genvar j;
generate
for (j = 0; j < 32; j = j + 1) begin : muxloop
mux2to1 m1 (
out[j],
sel,
in1[j],
in2[j]
);
end
endgenerate
endmodule
| 6.916393 |
module mux3to1 (
out,
sel,
in1,
in2,
in3
);
input in1, in2, in3;
input [1:0] sel;
output out;
assign out = sel[1] ? (sel[0] ? out : in3) : (sel[0] ? in2 : in1);
endmodule
| 6.860137 |
module bit32_3to1mux (
out,
sel,
in1,
in2,
in3
);
input [31:0] in1, in2, in3;
output [31:0] out;
input [1:0] sel;
genvar j;
generate
for (j = 0; j < 32; j = j + 1) begin : mux_loop
mux3to1 m (
out[j],
sel,
in1[j],
in2[j],
in3[j]
);
end
endgenerate
endmodule
| 7.021035 |
module bit32_8mux (
out,
sel,
in1,
in2
);
input [31:0] in1, in2;
output [31:0] out;
input sel;
genvar j;
generate
for (j = 0; j < 32; j = j + 8) begin : mux_loop
bit8_2to1mux m2 (
out[j+:8],
sel,
in1[j+:8],
in2[j+:8]
);
end
endgenerate
endmodule
| 7.341413 |
module xor_gate (
input x1,
input x2,
input x3,
output y
);
wire y1;
assign y1 = x1 ^ x2;
assign y = y1 ^ x3;
endmodule
| 8.121905 |
module: bit3XOR_code
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module xor_gate_tb;
// Inputs
reg x1;
reg x2;
reg x3;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
xor_gate uut (
.x1(x1),
.x2(x2),
.x3(x3),
.y(y)
);
initial begin
// Initialize Inputs
x1 = 0;
x2 = 0;
x3 = 0;
#20;
x1 = 1;
x2 = 0;
x3 = 0;
#20;
x1 = 0;
x2 = 1;
x3 = 0;
#20;
x1 = 1;
x2 = 1;
x3 = 0;
#20;
//4
x1 = 0;
x2 = 0;
x3 = 1;
#20;
x1 = 1;
x2 = 0;
x3 = 1;
#20;
x1 = 0;
x2 = 1;
x3 = 1;
#20;
x1 = 1;
x2 = 1;
x3 = 1;
#20;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.481672 |
module bit4 (
input shift_rot,
input [4:0] r,
input [31:0] x,
output [31:0] y
);
mux u1 (
r[2],
x[0],
x[4],
y[0]
);
mux u2 (
r[2],
x[1],
x[5],
y[1]
);
mux u3 (
r[2],
x[2],
x[6],
y[2]
);
mux u4 (
r[2],
x[3],
x[7],
y[3]
);
mux u5 (
r[2],
x[4],
x[8],
y[4]
);
mux u6 (
r[2],
x[5],
x[9],
y[5]
);
mux u7 (
r[2],
x[6],
x[10],
y[6]
);
mux u8 (
r[2],
x[7],
x[11],
y[7]
);
mux u9 (
r[2],
x[8],
x[12],
y[8]
);
mux u10 (
r[2],
x[9],
x[13],
y[9]
);
mux u11 (
r[2],
x[10],
x[14],
y[10]
);
mux u12 (
r[2],
x[11],
x[15],
y[11]
);
mux u13 (
r[2],
x[12],
x[16],
y[12]
);
mux u14 (
r[2],
x[13],
x[17],
y[13]
);
mux u15 (
r[2],
x[14],
x[18],
y[14]
);
mux u16 (
r[2],
x[15],
x[19],
y[15]
);
mux u17 (
r[2],
x[16],
x[20],
y[16]
);
mux u18 (
r[2],
x[17],
x[21],
y[17]
);
mux u19 (
r[2],
x[18],
x[22],
y[18]
);
mux u20 (
r[2],
x[19],
x[23],
y[19]
);
mux u21 (
r[2],
x[20],
x[24],
y[20]
);
mux u22 (
r[2],
x[21],
x[25],
y[21]
);
mux u23 (
r[2],
x[22],
x[26],
y[22]
);
mux u24 (
r[2],
x[23],
x[27],
y[23]
);
mux u25 (
r[2],
x[24],
x[28],
y[24]
);
mux u26 (
r[2],
x[25],
x[29],
y[25]
);
mux u27 (
r[2],
x[26],
x[30],
y[26]
);
mux u28 (
r[2],
x[27],
x[31],
y[27]
);
mux u29 (
r[2],
x[28],
(1'b0 & (~shift_rot) | x[0] & shift_rot),
y[28]
);
mux u30 (
r[2],
x[29],
(1'b0 & (~shift_rot) | x[1] & shift_rot),
y[29]
);
mux u31 (
r[2],
x[30],
(1'b0 & (~shift_rot) | x[2] & shift_rot),
y[30]
);
mux u32 (
r[2],
x[31],
(1'b0 & (~shift_rot) | x[3] & shift_rot),
y[31]
);
endmodule
| 6.541464 |
module bit4_adder (
input [3:0] A,
input [3:0] B,
output [3:0] S,
output Cout
);
wire C1, C2, C3;
half_adder ha0 (
A[0],
B[0],
C1,
S[0]
);
full_adder fa1 (
A[1],
B[1],
C1,
C2,
S[1]
);
full_adder fa2 (
A[2],
B[2],
C2,
C3,
S[2]
);
full_adder fa3 (
A[3],
B[3],
C3,
Cout,
S[3]
);
endmodule
| 7.229567 |
module Bit5Adder (
a,
b,
sum,
carry
);
input [5:1] a;
input [5:1] b;
output [5:1] sum;
output carry;
wire [4:1] w;
FullAdder fa_1 (
a[1],
b[1],
1'b0,
sum[1],
w[1]
);
FullAdder fa_2 (
a[2],
b[2],
w[1],
sum[2],
w[2]
);
FullAdder fa_3 (
a[3],
b[3],
w[2],
sum[3],
w[3]
);
FullAdder fa_4 (
a[4],
b[4],
w[3],
sum[4],
w[4]
);
FullAdder fa_5 (
a[5],
b[5],
w[4],
sum[5],
carry
);
endmodule
| 8.341554 |
module Bit5Adder (
a,
b,
sum,
carry
);
input [5:1] a;
input [5:1] b;
output [5:1] sum;
output carry;
wire [16:1] A, B, SUM;
wire CARRY;
assign A[5:1] = a;
assign A[16:6] = 11'b00000000000;
assign B[5:1] = b;
assign B[16:6] = 11'b00000000000;
RDAdder addr (
A,
B,
1'b0,
SUM,
CARRY
);
assign sum = SUM[5:1];
assign carry = SUM[6];
endmodule
| 8.341554 |
module Bit5MUX (
a,
b,
select,
out
);
input [5:1] a;
input [5:1] b;
input select;
output [5:1] out;
assign out[1] = ((!select) & a[1]) | ((select) & b[1]);
assign out[2] = ((!select) & a[2]) | ((select) & b[2]);
assign out[3] = ((!select) & a[3]) | ((select) & b[3]);
assign out[4] = ((!select) & a[4]) | ((select) & b[4]);
assign out[5] = ((!select) & a[5]) | ((select) & b[5]);
endmodule
| 8.559446 |
module bit5_encode (
input clk,
input rst_n,
input [4:0] code,
output [2:0] op
);
reg [2:0] outdata;
always @(posedge clk, negedge rst_n)
if (~rst_n) outdata <= 3'd0;
else
casex (code)
5'bxxxx1: outdata <= 3'd0;
5'bxxx10: outdata <= 3'd1;
5'bxx100: outdata <= 3'd2;
5'bx1000: outdata <= 3'd3;
5'b10000: outdata <= 3'd4;
default: outdata <= 3'd0;
endcase
assign op = outdata;
endmodule
| 6.960318 |
module FullAdder (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
wire a, b, cin;
wire sum, cout;
wire n_0, n_1;
MOAI22D0BWP g33 (
.A1(n_1),
.A2(n_0),
.B1(a),
.B2(b),
.ZN(cout)
);
MUX2ND0BWP g34 (
.I0(cin),
.I1(n_1),
.S (n_0),
.ZN(sum)
);
CKND1BWP g38 (
.I (cin),
.ZN(n_1)
);
XNR2D1BWP g2 (
.A1(a),
.A2(b),
.ZN(n_0)
);
endmodule
| 7.610141 |
module FullAdder_1 (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
wire a, b, cin;
wire sum, cout;
wire n_0, n_1;
AO22D2BWP g33 (
.A1(cin),
.A2(n_1),
.B1(a),
.B2(b),
.Z (cout)
);
CKXOR2D0BWP g34 (
.A1(n_0),
.A2(n_1),
.Z (sum)
);
XOR2D1BWP g35 (
.A1(a),
.A2(b),
.Z (n_1)
);
BUFFD0BWP fopt (
.I(cin),
.Z(n_0)
);
endmodule
| 6.801587 |
module FullAdder_3 (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
wire a, b, cin;
wire sum, cout;
wire n_0;
AO22D1BWP g33 (
.A1(cin),
.A2(n_0),
.B1(a),
.B2(b),
.Z (cout)
);
CKXOR2D0BWP g34 (
.A1(cin),
.A2(n_0),
.Z (sum)
);
XOR2D1BWP g35 (
.A1(a),
.A2(b),
.Z (n_0)
);
endmodule
| 7.164723 |
module Bit4Adder (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder FA_0 (
a[1],
b[1],
cin,
sum[1],
w1
);
FullAdder_1 FA_1 (
a[2],
b[2],
w1,
sum[2],
w2
);
FullAdder_2 FA_2 (
a[3],
b[3],
w2,
sum[3],
w3
);
FullAdder_3 FA_3 (
a[4],
b[4],
w3,
sum[4],
cout
);
endmodule
| 7.608783 |
module Bit4Adder_1 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_4 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_5 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_6 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_7 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 7.442301 |
module Bit4Adder_2 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_8 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_9 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_10 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_11 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 7.073135 |
module Bit4Adder_3 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_12 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_13 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_14 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_15 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 7.571329 |
module Bit16Adder (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire [16:1] a, b;
wire cin;
wire [16:1] sum;
wire cout;
wire w1, w2, w3;
Bit4Adder B4A_0 (
a[4:1],
b[4:1],
cin,
sum[4:1],
w1
);
Bit4Adder_1 B4A_1 (
a[8:5],
b[8:5],
w1,
sum[8:5],
w2
);
Bit4Adder_2 B4A_2 (
a[12:9],
b[12:9],
w2,
sum[12:9],
w3
);
Bit4Adder_3 B4A_3 (
a[16:13],
b[16:13],
w3,
sum[16:13],
cout
);
endmodule
| 6.99225 |
module Bit4Adder_4 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_16 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_17 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_18 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_19 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 6.961725 |
module Bit4Adder_5 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_20 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_21 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_22 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_23 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 7.165281 |
module Bit4Adder_6 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_24 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_25 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_26 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_27 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 6.888112 |
module Bit4Adder_7 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_28 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_29 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_30 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_31 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 7.213282 |
module Bit16Adder_1 (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire [16:1] a, b;
wire cin;
wire [16:1] sum;
wire cout;
wire w1, w2, w3;
Bit4Adder_4 B4A_0 (
.a(a[4:1]),
.b(b[4:1]),
.cin(cin),
.sum(sum[4:1]),
.cout(w1)
);
Bit4Adder_5 B4A_1 (
.a(a[8:5]),
.b(b[8:5]),
.cin(w1),
.sum(sum[8:5]),
.cout(w2)
);
Bit4Adder_6 B4A_2 (
.a(a[12:9]),
.b(b[12:9]),
.cin(w2),
.sum(sum[12:9]),
.cout(w3)
);
Bit4Adder_7 B4A_3 (
.a(a[16:13]),
.b(b[16:13]),
.cin(w3),
.sum(sum[16:13]),
.cout(cout)
);
endmodule
| 7.190901 |
module Bit4Adder_8 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_32 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_33 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_34 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_35 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 7.141654 |
module Bit4Adder_9 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_36 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_37 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_38 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_39 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 6.741012 |
module Bit4Adder_10 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_40 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_41 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_42 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_43 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 6.984917 |
module Bit4Adder_11 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_44 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_45 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_46 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_47 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 6.909616 |
module Bit16Adder_2 (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire [16:1] a, b;
wire cin;
wire [16:1] sum;
wire cout;
wire w1, w2, w3;
Bit4Adder_8 B4A_0 (
.a(a[4:1]),
.b(b[4:1]),
.cin(cin),
.sum(sum[4:1]),
.cout(w1)
);
Bit4Adder_9 B4A_1 (
.a(a[8:5]),
.b(b[8:5]),
.cin(w1),
.sum(sum[8:5]),
.cout(w2)
);
Bit4Adder_10 B4A_2 (
.a(a[12:9]),
.b(b[12:9]),
.cin(w2),
.sum(sum[12:9]),
.cout(w3)
);
Bit4Adder_11 B4A_3 (
.a(a[16:13]),
.b(b[16:13]),
.cin(w3),
.sum(sum[16:13]),
.cout(cout)
);
endmodule
| 7.132911 |
module Bit4Adder_12 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_48 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_49 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_50 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_51 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 6.870252 |
module Bit4Adder_13 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_52 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_53 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_54 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_55 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 7.073332 |
module Bit4Adder_14 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_56 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_57 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_58 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_59 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 7.133875 |
module Bit4Adder_15 (
a,
b,
cin,
sum,
cout
);
input [4:1] a, b;
input cin;
output [4:1] sum;
output cout;
wire [4:1] a, b;
wire cin;
wire [4:1] sum;
wire cout;
wire w1, w2, w3;
FullAdder_60 FA_0 (
.a(a[1]),
.b(b[1]),
.cin(cin),
.sum(sum[1]),
.cout(w1)
);
FullAdder_61 FA_1 (
.a(a[2]),
.b(b[2]),
.cin(w1),
.sum(sum[2]),
.cout(w2)
);
FullAdder_62 FA_2 (
.a(a[3]),
.b(b[3]),
.cin(w2),
.sum(sum[3]),
.cout(w3)
);
FullAdder_63 FA_3 (
.a(a[4]),
.b(b[4]),
.cin(w3),
.sum(sum[4]),
.cout(cout)
);
endmodule
| 6.968445 |
module Bit16Adder_3 (
a,
b,
cin,
sum,
cout
);
input [16:1] a, b;
input cin;
output [16:1] sum;
output cout;
wire [16:1] a, b;
wire cin;
wire [16:1] sum;
wire cout;
wire w1, w2, w3;
Bit4Adder_12 B4A_0 (
.a(a[4:1]),
.b(b[4:1]),
.cin(cin),
.sum(sum[4:1]),
.cout(w1)
);
Bit4Adder_13 B4A_1 (
.a(a[8:5]),
.b(b[8:5]),
.cin(w1),
.sum(sum[8:5]),
.cout(w2)
);
Bit4Adder_14 B4A_2 (
.a(a[12:9]),
.b(b[12:9]),
.cin(w2),
.sum(sum[12:9]),
.cout(w3)
);
Bit4Adder_15 B4A_3 (
.a(a[16:13]),
.b(b[16:13]),
.cin(w3),
.sum(sum[16:13]),
.cout(cout)
);
endmodule
| 7.429827 |
module Bit64Adder (
a,
b,
cin,
sum,
cout
);
input [64:1] a, b;
input cin;
output [64:1] sum;
output cout;
wire [64:1] a, b;
wire cin;
wire [64:1] sum;
wire cout;
wire w1, w2, w3;
Bit16Adder B16A_0 (
a[16:1],
b[16:1],
cin,
sum[16:1],
w1
);
Bit16Adder_1 B16A_1 (
a[32:17],
b[32:17],
w1,
sum[32:17],
w2
);
Bit16Adder_2 B16A_2 (
a[48:33],
b[48:33],
w2,
sum[48:33],
w3
);
Bit16Adder_3 B16A_3 (
a[64:49],
b[64:49],
w3,
sum[64:49],
cout
);
endmodule
| 6.759327 |
module Bit6Adder (
a,
b,
sum,
carry
);
input [6:1] a;
input [6:1] b;
output [6:1] sum;
output carry;
wire [5:1] w;
FullAdder fa_1 (
a[1],
b[1],
1'b0,
sum[1],
w[1]
);
FullAdder fa_2 (
a[2],
b[2],
w[1],
sum[2],
w[2]
);
FullAdder fa_3 (
a[3],
b[3],
w[2],
sum[3],
w[3]
);
FullAdder fa_4 (
a[4],
b[4],
w[3],
sum[4],
w[4]
);
FullAdder fa_5 (
a[5],
b[5],
w[4],
sum[5],
w[5]
);
FullAdder fa_6 (
a[6],
b[6],
w[5],
sum[6],
carry
);
endmodule
| 7.483202 |
module bit8 (
input shift_rot,
input [4:0] r,
input [31:0] x,
output [31:0] y
);
mux u1 (
r[3],
x[0],
x[8],
y[0]
);
mux u2 (
r[3],
x[1],
x[9],
y[1]
);
mux u3 (
r[3],
x[2],
x[10],
y[2]
);
mux u4 (
r[3],
x[3],
x[11],
y[3]
);
mux u5 (
r[3],
x[4],
x[12],
y[4]
);
mux u6 (
r[3],
x[5],
x[13],
y[5]
);
mux u7 (
r[3],
x[6],
x[14],
y[6]
);
mux u8 (
r[3],
x[7],
x[15],
y[7]
);
mux u9 (
r[3],
x[8],
x[16],
y[8]
);
mux u10 (
r[3],
x[9],
x[17],
y[9]
);
mux u11 (
r[3],
x[10],
x[18],
y[10]
);
mux u12 (
r[3],
x[11],
x[19],
y[11]
);
mux u13 (
r[3],
x[12],
x[20],
y[12]
);
mux u14 (
r[3],
x[13],
x[21],
y[13]
);
mux u15 (
r[3],
x[14],
x[22],
y[14]
);
mux u16 (
r[3],
x[15],
x[23],
y[15]
);
mux u17 (
r[3],
x[16],
x[24],
y[16]
);
mux u18 (
r[3],
x[17],
x[25],
y[17]
);
mux u19 (
r[3],
x[18],
x[26],
y[18]
);
mux u20 (
r[3],
x[19],
x[27],
y[19]
);
mux u21 (
r[3],
x[20],
x[28],
y[20]
);
mux u22 (
r[3],
x[21],
x[29],
y[21]
);
mux u23 (
r[3],
x[22],
x[30],
y[22]
);
mux u24 (
r[3],
x[23],
x[31],
y[23]
);
mux u25 (
r[3],
x[24],
(1'b0 & (~shift_rot) | x[0] & shift_rot),
y[24]
);
mux u26 (
r[3],
x[25],
(1'b0 & (~shift_rot) | x[1] & shift_rot),
y[25]
);
mux u27 (
r[3],
x[26],
(1'b0 & (~shift_rot) | x[2] & shift_rot),
y[26]
);
mux u28 (
r[3],
x[27],
(1'b0 & (~shift_rot) | x[3] & shift_rot),
y[27]
);
mux u29 (
r[3],
x[28],
(1'b0 & (~shift_rot) | x[4] & shift_rot),
y[28]
);
mux u30 (
r[3],
x[29],
(1'b0 & (~shift_rot) | x[5] & shift_rot),
y[29]
);
mux u31 (
r[3],
x[30],
(1'b0 & (~shift_rot) | x[6] & shift_rot),
y[30]
);
mux u32 (
r[3],
x[31],
(1'b0 & (~shift_rot) | x[7] & shift_rot),
y[31]
);
endmodule
| 7.211629 |
module bit8alu (
a,
b,
s,
acc,
mulh,
flag
);
parameter width = 8, w = width - 1;
input [w:0] a;
input [w:0] b;
input [2:0] s;
output reg [w:0] acc;
output reg [w:0] mulh;
output reg [7:0] flag;
always @(*) begin
flag = 8'b0;
case (s)
3'b000: acc = a & b;
3'b001: acc = a | b;
3'b010: acc = ~a;
3'b011: acc = a << 1;
3'b100: acc = acc >> 1;
3'b101: {flag[4], acc} = a + b;
3'b110: {flag[5], acc} = a - b;
3'b111: {mulh, acc} = a * b;
endcase
if (a == 8'b00000000) begin
flag[0] = 1'b1;
end else begin
flag[0] = 1'b0;
end
if (a == 8'b11111111) begin
flag[1] = 1'b1;
end else begin
flag[1] = 1'b0;
end
flag[2] = a[w];
flag[3] = a[0];
if (acc == 8'b00000000) begin
flag[6] = 1'b1;
end else begin
flag[6] = 1'b0;
end
if (acc == 8'b11111111) begin
flag[7] = 1'b1;
end else begin
flag[7] = 1'b0;
end
end
endmodule
| 6.618196 |
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