code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width less than output width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
$error(
"std_pad: Output width less than input width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_not1_1 _impl (
in,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_not8_1 _impl (
in,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_and1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_and32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_or1_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
// if (WIDTH == x) begin
// lakeroad_xilinx_ultrascale_plus_op _impl(in, out);
// end
// //else begin
$error("Unsupported bitwidth %0d", WIDTH);
// end
endmodule
| 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 2) begin
lakeroad_xilinx_ultrascale_plus_add2_2 _impl (
left,
right,
out
);
end else if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_add3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_add4_2 _impl (
left,
right,
out
);
end else if (WIDTH == 8) begin
lakeroad_xilinx_ultrascale_plus_add8_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_add32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_sub5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) begin
lakeroad_xilinx_ultrascale_plus_sub6_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_ugt5_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 3) begin
lakeroad_xilinx_ultrascale_plus_ult3_2 _impl (
left,
right,
out
);
end else if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ult4_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_ult32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 1) begin
lakeroad_xilinx_ultrascale_plus_eq1_2 _impl (
left,
right,
out
);
end else if (WIDTH == 5) begin
lakeroad_xilinx_ultrascale_plus_eq5_2 _impl (
left,
right,
out
);
end else if (WIDTH == 6) begin
lakeroad_xilinx_ultrascale_plus_eq6_2 _impl (
left,
right,
out
);
end else if (WIDTH == 32) begin
lakeroad_xilinx_ultrascale_plus_eq32_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (0 == 1) begin
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
if (WIDTH == 4) begin
lakeroad_xilinx_ultrascale_plus_ule4_2 _impl (
left,
right,
out
);
end else begin
$error("Unsupported bitwidth %0d", WIDTH);
end
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
if (reset) begin
out <= 0;
done <= 0;
end else if (write_en) begin
out <= in;
done <= 1'd1;
end else done <= 1'd0;
end
endmodule
| 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
logic [WIDTH-1:0] mem[SIZE-1:0];
/* verilator lint_off WIDTH */
assign read_data = mem[addr0];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= SIZE)
$error("std_mem_d1: Out of bounds access\n", "addr0: %0d\n", addr0, "SIZE: %0d", SIZE);
end
`endif
endmodule
| 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0];
assign read_data = mem[addr0][addr1];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d2: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d2: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
end
`endif
endmodule
| 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [D2_IDX_SIZE-1:0] addr2,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0];
assign read_data = mem[addr0][addr1][addr2];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1][addr2] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
if (addr2 >= D2_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE);
end
`endif
endmodule
| 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [D2_IDX_SIZE-1:0] addr2,
input wire logic [D3_IDX_SIZE-1:0] addr3,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0][D3_SIZE-1:0];
assign read_data = mem[addr0][addr1][addr2][addr3];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1][addr2][addr3] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
if (addr2 >= D2_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE);
if (addr3 >= D3_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr3: %0d\n", addr3, "D3_SIZE: %0d", D3_SIZE);
end
`endif
endmodule
| 9.168498 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_read_data;
input [31:0] lhs_read_data;
wire [0:0] E;
wire [15:0] Q;
wire clk;
wire do_unsigned_mul_go_in;
wire [31:0] lhs_read_data;
wire mul_done;
wire [15:0] out_tmp_reg;
wire reset;
wire [31:0] rhs_read_data;
std_fp_mult_pipe__parameterized0 comp (
.E(E),
.Q(Q),
.clk(clk),
.do_unsigned_mul_go_in(do_unsigned_mul_go_in),
.\done_buf_reg[2]_0 (mul_done),
.lhs_read_data(lhs_read_data),
.out_tmp_reg_0(out_tmp_reg),
.reset(reset),
.rhs_read_data(rhs_read_data)
);
endmodule
| 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividend_reg[3]_0 ,
left_abs__2,
reset,
D
);
output sdiv_done;
output [3:0] signed_mod_write_data;
output [3:0] signed_div_write_data;
output [0:0] SR;
output signed_div_write_en;
output reset_0;
output [0:0] \quotient_msk_reg[0] ;
output [0:0] Q;
input done0;
input clk;
input [0:0] E;
input [3:0] srhs_read_data;
input [1:0] slhs_read_data;
input running_reg;
input do_signed_div_mod_go_in;
input \dividend_reg[3] ;
input \dividend_reg[3]_0 ;
input [1:0] left_abs__2;
input reset;
input [0:0] D;
wire \<const0> ;
wire [0:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire different_signs__0;
wire \dividend_reg[3] ;
wire \dividend_reg[3]_0 ;
wire do_signed_div_mod_go_in;
wire done0;
wire [1:0] left_abs__2;
wire left_sign;
wire [0:0] \quotient_msk_reg[0] ;
wire reset;
wire reset_0;
wire [3:1] right_abs;
wire [3:0] right_save;
wire right_sign;
wire running_reg;
wire sdiv_done;
wire [3:0] signed_div_write_data;
wire signed_div_write_en;
wire [3:0] signed_mod_write_data;
wire [1:0] slhs_read_data;
wire [3:0] srhs_read_data;
GND GND (.G(\<const0> ));
std_div_pipe comp (
.D(D),
.E(\quotient_msk_reg[0] ),
.Q(right_save),
.SS(SR),
.clk(clk),
.different_signs__0(different_signs__0),
.\dividend_reg[3]_0 (\dividend_reg[3] ),
.\dividend_reg[3]_1 (\dividend_reg[3]_0 ),
.\divisor_reg[6]_0 (Q),
.do_signed_div_mod_go_in(do_signed_div_mod_go_in),
.done0(done0),
.done_reg_0(sdiv_done),
.left_abs__2(left_abs__2),
.left_sign(left_sign),
.reset(reset),
.reset_0(reset_0),
.right_sign(right_sign),
.running_reg_0(running_reg),
.signed_div_write_data(signed_div_write_data),
.signed_div_write_en(signed_div_write_en),
.signed_mod_write_data(signed_mod_write_data),
.slhs_read_data(slhs_read_data[0]),
.srhs_read_data(srhs_read_data)
);
FDRE left_sign_reg (
.C (clk),
.CE(E),
.D (slhs_read_data[1]),
.Q (left_sign),
.R (\<const0> )
);
LUT3 #(
.INIT(8'h6C)
) \right_save[1]_i_1 (
.I0(srhs_read_data[3]),
.I1(srhs_read_data[1]),
.I2(srhs_read_data[0]),
.O (right_abs[1])
);
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h1FE0)
) \right_save[2]_i_1 (
.I0(srhs_read_data[1]),
.I1(srhs_read_data[0]),
.I2(srhs_read_data[3]),
.I3(srhs_read_data[2]),
.O (right_abs[2])
);
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h0004)
) \right_save[3]_i_1 (
.I0(srhs_read_data[2]),
.I1(srhs_read_data[3]),
.I2(srhs_read_data[0]),
.I3(srhs_read_data[1]),
.O (right_abs[3])
);
FDRE \right_save_reg[0] (
.C (clk),
.CE(E),
.D (srhs_read_data[0]),
.Q (right_save[0]),
.R (\<const0> )
);
FDRE \right_save_reg[1] (
.C (clk),
.CE(E),
.D (right_abs[1]),
.Q (right_save[1]),
.R (\<const0> )
);
FDRE \right_save_reg[2] (
.C (clk),
.CE(E),
.D (right_abs[2]),
.Q (right_save[2]),
.R (\<const0> )
);
FDRE \right_save_reg[3] (
.C (clk),
.CE(E),
.D (right_abs[3]),
.Q (right_save[3]),
.R (\<const0> )
);
FDRE right_sign_reg (
.C (clk),
.CE(E),
.D (srhs_read_data[3]),
.Q (right_sign),
.R (\<const0> )
);
LUT2 #(
.INIT(4'h6)
) \signed_div_write_data[3]_INST_0_i_1 (
.I0(right_sign),
.I1(left_sign),
.O (different_signs__0)
);
endmodule
| 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0] E;
wire [3:0] D;
wire [0:0] E;
wire clk;
wire do_signed_mul_go_in;
wire [3:0] \ltmp_reg[3] ;
wire reset;
wire [3:0] signed_mul_write_data;
wire smul_done;
std_fp_mult_pipe comp (
.D(D),
.E(E),
.clk(clk),
.do_signed_mul_go_in(do_signed_mul_go_in),
.\ltmp_reg[3]_0 (\ltmp_reg[3] ),
.reset(reset),
.signed_mul_write_data(signed_mul_write_data),
.smul_done(smul_done)
);
endmodule
| 6.968167 |
module std_sub (
sub_out,
sub_left,
\unsigned_sub_write_data[7] ,
\unsigned_sub_write_data[15] ,
\unsigned_sub_write_data[23] ,
S
);
output [31:0] sub_out;
input [30:0] sub_left;
input [7:0] \unsigned_sub_write_data[7] ;
input [7:0] \unsigned_sub_write_data[15] ;
input [7:0] \unsigned_sub_write_data[23] ;
input [7:0] S;
wire \<const0> ;
wire \<const1> ;
wire GND_2;
wire [7:0] S;
wire out_carry__0_n_0;
wire out_carry__1_n_0;
wire out_carry_n_0;
wire [30:0] sub_left;
wire [31:0] sub_out;
wire [7:0] \unsigned_sub_write_data[15] ;
wire [7:0] \unsigned_sub_write_data[23] ;
wire [7:0] \unsigned_sub_write_data[7] ;
wire [7:0] NLW_out_carry_CO_UNCONNECTED;
wire [7:0] NLW_out_carry__0_CO_UNCONNECTED;
wire [7:0] NLW_out_carry__1_CO_UNCONNECTED;
GND GND (.G(\<const0> ));
GND GND_1 (.G(GND_2));
VCC VCC (.P(\<const1> ));
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry (
.CI(\<const1> ),
.CI_TOP(GND_2),
.CO({out_carry_n_0, NLW_out_carry_CO_UNCONNECTED[6:0]}),
.DI(sub_left[7:0]),
.O(sub_out[7:0]),
.S(\unsigned_sub_write_data[7] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__0 (
.CI(out_carry_n_0),
.CI_TOP(GND_2),
.CO({out_carry__0_n_0, NLW_out_carry__0_CO_UNCONNECTED[6:0]}),
.DI(sub_left[15:8]),
.O(sub_out[15:8]),
.S(\unsigned_sub_write_data[15] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__1 (
.CI(out_carry__0_n_0),
.CI_TOP(GND_2),
.CO({out_carry__1_n_0, NLW_out_carry__1_CO_UNCONNECTED[6:0]}),
.DI(sub_left[23:16]),
.O(sub_out[23:16]),
.S(\unsigned_sub_write_data[23] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__2 (
.CI(out_carry__1_n_0),
.CI_TOP(GND_2),
.DI({\<const0> , sub_left[30:24]}),
.O(sub_out[31:24]),
.S(S)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_read_data;
input [31:0] lhs_read_data;
wire [0:0] E;
wire [15:0] Q;
wire clk;
wire do_unsigned_mul_go_in;
wire [31:0] lhs_read_data;
wire mul_done;
wire [15:0] out_tmp_reg;
wire reset;
wire [31:0] rhs_read_data;
std_fp_mult_pipe__parameterized0 comp (
.E(E),
.Q(Q),
.clk(clk),
.do_unsigned_mul_go_in(do_unsigned_mul_go_in),
.\done_buf_reg[2]_0 (mul_done),
.lhs_read_data(lhs_read_data),
.out_tmp_reg_0(out_tmp_reg),
.reset(reset),
.rhs_read_data(rhs_read_data)
);
endmodule
| 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividend_reg[3]_0 ,
left_abs__2,
reset,
D
);
output sdiv_done;
output [3:0] signed_mod_write_data;
output [3:0] signed_div_write_data;
output [0:0] SR;
output signed_div_write_en;
output reset_0;
output [0:0] \quotient_msk_reg[0] ;
output [0:0] Q;
input done0;
input clk;
input [0:0] E;
input [3:0] srhs_read_data;
input [1:0] slhs_read_data;
input running_reg;
input do_signed_div_mod_go_in;
input \dividend_reg[3] ;
input \dividend_reg[3]_0 ;
input [1:0] left_abs__2;
input reset;
input [0:0] D;
wire \<const0> ;
wire [0:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire different_signs__0;
wire \dividend_reg[3] ;
wire \dividend_reg[3]_0 ;
wire do_signed_div_mod_go_in;
wire done0;
wire [1:0] left_abs__2;
wire left_sign;
wire [0:0] \quotient_msk_reg[0] ;
wire reset;
wire reset_0;
wire [3:1] right_abs;
wire [3:0] right_save;
wire right_sign;
wire running_reg;
wire sdiv_done;
wire [3:0] signed_div_write_data;
wire signed_div_write_en;
wire [3:0] signed_mod_write_data;
wire [1:0] slhs_read_data;
wire [3:0] srhs_read_data;
GND GND (.G(\<const0> ));
std_div_pipe comp (
.D(D),
.E(\quotient_msk_reg[0] ),
.Q(right_save),
.SS(SR),
.clk(clk),
.different_signs__0(different_signs__0),
.\dividend_reg[3]_0 (\dividend_reg[3] ),
.\dividend_reg[3]_1 (\dividend_reg[3]_0 ),
.\divisor_reg[6]_0 (Q),
.do_signed_div_mod_go_in(do_signed_div_mod_go_in),
.done0(done0),
.done_reg_0(sdiv_done),
.left_abs__2(left_abs__2),
.left_sign(left_sign),
.reset(reset),
.reset_0(reset_0),
.right_sign(right_sign),
.running_reg_0(running_reg),
.signed_div_write_data(signed_div_write_data),
.signed_div_write_en(signed_div_write_en),
.signed_mod_write_data(signed_mod_write_data),
.slhs_read_data(slhs_read_data[0]),
.srhs_read_data(srhs_read_data)
);
FDRE left_sign_reg (
.C (clk),
.CE(E),
.D (slhs_read_data[1]),
.Q (left_sign),
.R (\<const0> )
);
LUT3 #(
.INIT(8'h6C)
) \right_save[1]_i_1 (
.I0(srhs_read_data[3]),
.I1(srhs_read_data[1]),
.I2(srhs_read_data[0]),
.O (right_abs[1])
);
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h1FE0)
) \right_save[2]_i_1 (
.I0(srhs_read_data[1]),
.I1(srhs_read_data[0]),
.I2(srhs_read_data[3]),
.I3(srhs_read_data[2]),
.O (right_abs[2])
);
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h0004)
) \right_save[3]_i_1 (
.I0(srhs_read_data[2]),
.I1(srhs_read_data[3]),
.I2(srhs_read_data[0]),
.I3(srhs_read_data[1]),
.O (right_abs[3])
);
FDRE \right_save_reg[0] (
.C (clk),
.CE(E),
.D (srhs_read_data[0]),
.Q (right_save[0]),
.R (\<const0> )
);
FDRE \right_save_reg[1] (
.C (clk),
.CE(E),
.D (right_abs[1]),
.Q (right_save[1]),
.R (\<const0> )
);
FDRE \right_save_reg[2] (
.C (clk),
.CE(E),
.D (right_abs[2]),
.Q (right_save[2]),
.R (\<const0> )
);
FDRE \right_save_reg[3] (
.C (clk),
.CE(E),
.D (right_abs[3]),
.Q (right_save[3]),
.R (\<const0> )
);
FDRE right_sign_reg (
.C (clk),
.CE(E),
.D (srhs_read_data[3]),
.Q (right_sign),
.R (\<const0> )
);
LUT2 #(
.INIT(4'h6)
) \signed_div_write_data[3]_INST_0_i_1 (
.I0(right_sign),
.I1(left_sign),
.O (different_signs__0)
);
endmodule
| 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0] E;
wire [3:0] D;
wire [0:0] E;
wire clk;
wire do_signed_mul_go_in;
wire [3:0] \ltmp_reg[3] ;
wire reset;
wire [3:0] signed_mul_write_data;
wire smul_done;
std_fp_mult_pipe comp (
.D(D),
.E(E),
.clk(clk),
.do_signed_mul_go_in(do_signed_mul_go_in),
.\ltmp_reg[3]_0 (\ltmp_reg[3] ),
.reset(reset),
.signed_mul_write_data(signed_mul_write_data),
.smul_done(smul_done)
);
endmodule
| 6.968167 |
module std_sub (
sub_out,
sub_left,
\unsigned_sub_write_data[7] ,
\unsigned_sub_write_data[15] ,
\unsigned_sub_write_data[23] ,
S
);
output [31:0] sub_out;
input [30:0] sub_left;
input [7:0] \unsigned_sub_write_data[7] ;
input [7:0] \unsigned_sub_write_data[15] ;
input [7:0] \unsigned_sub_write_data[23] ;
input [7:0] S;
wire \<const0> ;
wire \<const1> ;
wire GND_2;
wire [7:0] S;
wire out_carry__0_n_0;
wire out_carry__1_n_0;
wire out_carry_n_0;
wire [30:0] sub_left;
wire [31:0] sub_out;
wire [7:0] \unsigned_sub_write_data[15] ;
wire [7:0] \unsigned_sub_write_data[23] ;
wire [7:0] \unsigned_sub_write_data[7] ;
wire [7:0] NLW_out_carry_CO_UNCONNECTED;
wire [7:0] NLW_out_carry__0_CO_UNCONNECTED;
wire [7:0] NLW_out_carry__1_CO_UNCONNECTED;
GND GND (.G(\<const0> ));
GND GND_1 (.G(GND_2));
VCC VCC (.P(\<const1> ));
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry (
.CI(\<const1> ),
.CI_TOP(GND_2),
.CO({out_carry_n_0, NLW_out_carry_CO_UNCONNECTED[6:0]}),
.DI(sub_left[7:0]),
.O(sub_out[7:0]),
.S(\unsigned_sub_write_data[7] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__0 (
.CI(out_carry_n_0),
.CI_TOP(GND_2),
.CO({out_carry__0_n_0, NLW_out_carry__0_CO_UNCONNECTED[6:0]}),
.DI(sub_left[15:8]),
.O(sub_out[15:8]),
.S(\unsigned_sub_write_data[15] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__1 (
.CI(out_carry__0_n_0),
.CI_TOP(GND_2),
.CO({out_carry__1_n_0, NLW_out_carry__1_CO_UNCONNECTED[6:0]}),
.DI(sub_left[23:16]),
.O(sub_out[23:16]),
.S(\unsigned_sub_write_data[23] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__2 (
.CI(out_carry__1_n_0),
.CI_TOP(GND_2),
.DI({\<const0> , sub_left[30:24]}),
.O(sub_out[31:24]),
.S(S)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_read_data;
input [31:0] lhs_read_data;
wire [0:0] E;
wire [15:0] Q;
wire clk;
wire do_unsigned_mul_go_in;
wire [31:0] lhs_read_data;
wire mul_done;
wire [15:0] out_tmp_reg;
wire reset;
wire [31:0] rhs_read_data;
std_fp_mult_pipe__parameterized0 comp (
.E(E),
.Q(Q),
.clk(clk),
.do_unsigned_mul_go_in(do_unsigned_mul_go_in),
.\done_buf_reg[2]_0 (mul_done),
.lhs_read_data(lhs_read_data),
.out_tmp_reg_0(out_tmp_reg),
.reset(reset),
.rhs_read_data(rhs_read_data)
);
endmodule
| 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividend_reg[3]_0 ,
left_abs__2,
reset,
D
);
output sdiv_done;
output [3:0] signed_mod_write_data;
output [3:0] signed_div_write_data;
output [0:0] SR;
output signed_div_write_en;
output reset_0;
output [0:0] \quotient_msk_reg[0] ;
output [0:0] Q;
input done0;
input clk;
input [0:0] E;
input [3:0] srhs_read_data;
input [1:0] slhs_read_data;
input running_reg;
input do_signed_div_mod_go_in;
input \dividend_reg[3] ;
input \dividend_reg[3]_0 ;
input [1:0] left_abs__2;
input reset;
input [0:0] D;
wire \<const0> ;
wire [0:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire different_signs__0;
wire \dividend_reg[3] ;
wire \dividend_reg[3]_0 ;
wire do_signed_div_mod_go_in;
wire done0;
wire [1:0] left_abs__2;
wire left_sign;
wire [0:0] \quotient_msk_reg[0] ;
wire reset;
wire reset_0;
wire [3:1] right_abs;
wire [3:0] right_save;
wire right_sign;
wire running_reg;
wire sdiv_done;
wire [3:0] signed_div_write_data;
wire signed_div_write_en;
wire [3:0] signed_mod_write_data;
wire [1:0] slhs_read_data;
wire [3:0] srhs_read_data;
GND GND (.G(\<const0> ));
std_div_pipe comp (
.D(D),
.E(\quotient_msk_reg[0] ),
.Q(right_save),
.SS(SR),
.clk(clk),
.different_signs__0(different_signs__0),
.\dividend_reg[3]_0 (\dividend_reg[3] ),
.\dividend_reg[3]_1 (\dividend_reg[3]_0 ),
.\divisor_reg[6]_0 (Q),
.do_signed_div_mod_go_in(do_signed_div_mod_go_in),
.done0(done0),
.done_reg_0(sdiv_done),
.left_abs__2(left_abs__2),
.left_sign(left_sign),
.reset(reset),
.reset_0(reset_0),
.right_sign(right_sign),
.running_reg_0(running_reg),
.signed_div_write_data(signed_div_write_data),
.signed_div_write_en(signed_div_write_en),
.signed_mod_write_data(signed_mod_write_data),
.slhs_read_data(slhs_read_data[0]),
.srhs_read_data(srhs_read_data)
);
FDRE left_sign_reg (
.C (clk),
.CE(E),
.D (slhs_read_data[1]),
.Q (left_sign),
.R (\<const0> )
);
LUT3 #(
.INIT(8'h6C)
) \right_save[1]_i_1 (
.I0(srhs_read_data[3]),
.I1(srhs_read_data[1]),
.I2(srhs_read_data[0]),
.O (right_abs[1])
);
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h1FE0)
) \right_save[2]_i_1 (
.I0(srhs_read_data[1]),
.I1(srhs_read_data[0]),
.I2(srhs_read_data[3]),
.I3(srhs_read_data[2]),
.O (right_abs[2])
);
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h0004)
) \right_save[3]_i_1 (
.I0(srhs_read_data[2]),
.I1(srhs_read_data[3]),
.I2(srhs_read_data[0]),
.I3(srhs_read_data[1]),
.O (right_abs[3])
);
FDRE \right_save_reg[0] (
.C (clk),
.CE(E),
.D (srhs_read_data[0]),
.Q (right_save[0]),
.R (\<const0> )
);
FDRE \right_save_reg[1] (
.C (clk),
.CE(E),
.D (right_abs[1]),
.Q (right_save[1]),
.R (\<const0> )
);
FDRE \right_save_reg[2] (
.C (clk),
.CE(E),
.D (right_abs[2]),
.Q (right_save[2]),
.R (\<const0> )
);
FDRE \right_save_reg[3] (
.C (clk),
.CE(E),
.D (right_abs[3]),
.Q (right_save[3]),
.R (\<const0> )
);
FDRE right_sign_reg (
.C (clk),
.CE(E),
.D (srhs_read_data[3]),
.Q (right_sign),
.R (\<const0> )
);
LUT2 #(
.INIT(4'h6)
) \signed_div_write_data[3]_INST_0_i_1 (
.I0(right_sign),
.I1(left_sign),
.O (different_signs__0)
);
endmodule
| 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0] E;
wire [3:0] D;
wire [0:0] E;
wire clk;
wire do_signed_mul_go_in;
wire [3:0] \ltmp_reg[3] ;
wire reset;
wire [3:0] signed_mul_write_data;
wire smul_done;
std_fp_mult_pipe comp (
.D(D),
.E(E),
.clk(clk),
.do_signed_mul_go_in(do_signed_mul_go_in),
.\ltmp_reg[3]_0 (\ltmp_reg[3] ),
.reset(reset),
.signed_mul_write_data(signed_mul_write_data),
.smul_done(smul_done)
);
endmodule
| 6.968167 |
module std_sub (
sub_out,
sub_left,
\unsigned_sub_write_data[7] ,
\unsigned_sub_write_data[15] ,
\unsigned_sub_write_data[23] ,
S
);
output [31:0] sub_out;
input [30:0] sub_left;
input [7:0] \unsigned_sub_write_data[7] ;
input [7:0] \unsigned_sub_write_data[15] ;
input [7:0] \unsigned_sub_write_data[23] ;
input [7:0] S;
wire \<const0> ;
wire \<const1> ;
wire GND_2;
wire [7:0] S;
wire out_carry__0_n_0;
wire out_carry__1_n_0;
wire out_carry_n_0;
wire [30:0] sub_left;
wire [31:0] sub_out;
wire [7:0] \unsigned_sub_write_data[15] ;
wire [7:0] \unsigned_sub_write_data[23] ;
wire [7:0] \unsigned_sub_write_data[7] ;
wire [7:0] NLW_out_carry_CO_UNCONNECTED;
wire [7:0] NLW_out_carry__0_CO_UNCONNECTED;
wire [7:0] NLW_out_carry__1_CO_UNCONNECTED;
GND GND (.G(\<const0> ));
GND GND_1 (.G(GND_2));
VCC VCC (.P(\<const1> ));
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry (
.CI(\<const1> ),
.CI_TOP(GND_2),
.CO({out_carry_n_0, NLW_out_carry_CO_UNCONNECTED[6:0]}),
.DI(sub_left[7:0]),
.O(sub_out[7:0]),
.S(\unsigned_sub_write_data[7] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__0 (
.CI(out_carry_n_0),
.CI_TOP(GND_2),
.CO({out_carry__0_n_0, NLW_out_carry__0_CO_UNCONNECTED[6:0]}),
.DI(sub_left[15:8]),
.O(sub_out[15:8]),
.S(\unsigned_sub_write_data[15] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__1 (
.CI(out_carry__0_n_0),
.CI_TOP(GND_2),
.CO({out_carry__1_n_0, NLW_out_carry__1_CO_UNCONNECTED[6:0]}),
.DI(sub_left[23:16]),
.O(sub_out[23:16]),
.S(\unsigned_sub_write_data[23] )
);
(* ADDER_THRESHOLD = "35" *) (* OPT_MODIFIED = "SWEEP" *)
CARRY8 out_carry__2 (
.CI(out_carry__1_n_0),
.CI_TOP(GND_2),
.DI({\<const0> , sub_left[30:24]}),
.O(sub_out[31:24]),
.S(S)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_read_data;
input [31:0] lhs_read_data;
wire [0:0] E;
wire [15:0] Q;
wire clk;
wire do_unsigned_mul_go_in;
wire [31:0] lhs_read_data;
wire mul_done;
wire [15:0] out_tmp_reg;
wire reset;
wire [31:0] rhs_read_data;
std_fp_mult_pipe__parameterized0 comp (
.E(E),
.Q(Q),
.clk(clk),
.do_unsigned_mul_go_in(do_unsigned_mul_go_in),
.\done_buf_reg[2]_0 (mul_done),
.lhs_read_data(lhs_read_data),
.out_tmp_reg_0(out_tmp_reg),
.reset(reset),
.rhs_read_data(rhs_read_data)
);
endmodule
| 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividend_reg[3]_0 ,
left_abs__2,
reset,
D
);
output sdiv_done;
output [3:0] signed_mod_write_data;
output [3:0] signed_div_write_data;
output [0:0] SR;
output signed_div_write_en;
output reset_0;
output [0:0] \quotient_msk_reg[0] ;
output [0:0] Q;
input done0;
input clk;
input [0:0] E;
input [3:0] srhs_read_data;
input [1:0] slhs_read_data;
input running_reg;
input do_signed_div_mod_go_in;
input \dividend_reg[3] ;
input \dividend_reg[3]_0 ;
input [1:0] left_abs__2;
input reset;
input [0:0] D;
wire \<const0> ;
wire [0:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [0:0] SR;
wire clk;
wire different_signs__0;
wire \dividend_reg[3] ;
wire \dividend_reg[3]_0 ;
wire do_signed_div_mod_go_in;
wire done0;
wire [1:0] left_abs__2;
wire left_sign;
wire [0:0] \quotient_msk_reg[0] ;
wire reset;
wire reset_0;
wire [3:1] right_abs;
wire [3:0] right_save;
wire right_sign;
wire running_reg;
wire sdiv_done;
wire [3:0] signed_div_write_data;
wire signed_div_write_en;
wire [3:0] signed_mod_write_data;
wire [1:0] slhs_read_data;
wire [3:0] srhs_read_data;
GND GND (.G(\<const0> ));
std_div_pipe comp (
.D(D),
.E(\quotient_msk_reg[0] ),
.Q(right_save),
.SS(SR),
.clk(clk),
.different_signs__0(different_signs__0),
.\dividend_reg[3]_0 (\dividend_reg[3] ),
.\dividend_reg[3]_1 (\dividend_reg[3]_0 ),
.\divisor_reg[6]_0 (Q),
.do_signed_div_mod_go_in(do_signed_div_mod_go_in),
.done0(done0),
.done_reg_0(sdiv_done),
.left_abs__2(left_abs__2),
.left_sign(left_sign),
.reset(reset),
.reset_0(reset_0),
.right_sign(right_sign),
.running_reg_0(running_reg),
.signed_div_write_data(signed_div_write_data),
.signed_div_write_en(signed_div_write_en),
.signed_mod_write_data(signed_mod_write_data),
.slhs_read_data(slhs_read_data[0]),
.srhs_read_data(srhs_read_data)
);
FDRE left_sign_reg (
.C (clk),
.CE(E),
.D (slhs_read_data[1]),
.Q (left_sign),
.R (\<const0> )
);
LUT3 #(
.INIT(8'h6C)
) \right_save[1]_i_1 (
.I0(srhs_read_data[3]),
.I1(srhs_read_data[1]),
.I2(srhs_read_data[0]),
.O (right_abs[1])
);
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h1FE0)
) \right_save[2]_i_1 (
.I0(srhs_read_data[1]),
.I1(srhs_read_data[0]),
.I2(srhs_read_data[3]),
.I3(srhs_read_data[2]),
.O (right_abs[2])
);
(* SOFT_HLUTNM = "soft_lutpair171" *)
LUT4 #(
.INIT(16'h0004)
) \right_save[3]_i_1 (
.I0(srhs_read_data[2]),
.I1(srhs_read_data[3]),
.I2(srhs_read_data[0]),
.I3(srhs_read_data[1]),
.O (right_abs[3])
);
FDRE \right_save_reg[0] (
.C (clk),
.CE(E),
.D (srhs_read_data[0]),
.Q (right_save[0]),
.R (\<const0> )
);
FDRE \right_save_reg[1] (
.C (clk),
.CE(E),
.D (right_abs[1]),
.Q (right_save[1]),
.R (\<const0> )
);
FDRE \right_save_reg[2] (
.C (clk),
.CE(E),
.D (right_abs[2]),
.Q (right_save[2]),
.R (\<const0> )
);
FDRE \right_save_reg[3] (
.C (clk),
.CE(E),
.D (right_abs[3]),
.Q (right_save[3]),
.R (\<const0> )
);
FDRE right_sign_reg (
.C (clk),
.CE(E),
.D (srhs_read_data[3]),
.Q (right_sign),
.R (\<const0> )
);
LUT2 #(
.INIT(4'h6)
) \signed_div_write_data[3]_INST_0_i_1 (
.I0(right_sign),
.I1(left_sign),
.O (different_signs__0)
);
endmodule
| 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0] E;
wire [3:0] D;
wire [0:0] E;
wire clk;
wire do_signed_mul_go_in;
wire [3:0] \ltmp_reg[3] ;
wire reset;
wire [3:0] signed_mul_write_data;
wire smul_done;
std_fp_mult_pipe comp (
.D(D),
.E(E),
.clk(clk),
.do_signed_mul_go_in(do_signed_mul_go_in),
.\ltmp_reg[3]_0 (\ltmp_reg[3] ),
.reset(reset),
.signed_mul_write_data(signed_mul_write_data),
.smul_done(smul_done)
);
endmodule
| 6.968167 |
module std_sub (
sub_out,
sub_left,
\unsigned_sub_write_data[7] ,
\unsigned_sub_write_data[15] ,
\unsigned_sub_write_data[23] ,
S
);
output [31:0] sub_out;
input [30:0] sub_left;
input [7:0] \unsigned_sub_write_data[7] ;
input [7:0] \unsigned_sub_write_data[15] ;
input [7:0] \unsigned_sub_write_data[23] ;
input [7:0] S;
wire \<const0> ;
wire \<const1> ;
wire GND_2;
wire [7:0] S;
wire out_carry__0_n_0;
wire out_carry__0_n_1;
wire out_carry__0_n_2;
wire out_carry__0_n_3;
wire out_carry__0_n_4;
wire out_carry__0_n_5;
wire out_carry__0_n_6;
wire out_carry__0_n_7;
wire out_carry__1_n_0;
wire out_carry__1_n_1;
wire out_carry__1_n_2;
wire out_carry__1_n_3;
wire out_carry__1_n_4;
wire out_carry__1_n_5;
wire out_carry__1_n_6;
wire out_carry__1_n_7;
wire out_carry__2_n_1;
wire out_carry__2_n_2;
wire out_carry__2_n_3;
wire out_carry__2_n_4;
wire out_carry__2_n_5;
wire out_carry__2_n_6;
wire out_carry__2_n_7;
wire out_carry_n_0;
wire out_carry_n_1;
wire out_carry_n_2;
wire out_carry_n_3;
wire out_carry_n_4;
wire out_carry_n_5;
wire out_carry_n_6;
wire out_carry_n_7;
wire [30:0] sub_left;
wire [31:0] sub_out;
wire [7:0] \unsigned_sub_write_data[15] ;
wire [7:0] \unsigned_sub_write_data[23] ;
wire [7:0] \unsigned_sub_write_data[7] ;
GND GND (.G(\<const0> ));
GND GND_1 (.G(GND_2));
VCC VCC (.P(\<const1> ));
(* ADDER_THRESHOLD = "35" *)
CARRY8 out_carry (
.CI(\<const1> ),
.CI_TOP(GND_2),
.CO({
out_carry_n_0,
out_carry_n_1,
out_carry_n_2,
out_carry_n_3,
out_carry_n_4,
out_carry_n_5,
out_carry_n_6,
out_carry_n_7
}),
.DI(sub_left[7:0]),
.O(sub_out[7:0]),
.S(\unsigned_sub_write_data[7] )
);
(* ADDER_THRESHOLD = "35" *)
CARRY8 out_carry__0 (
.CI(out_carry_n_0),
.CI_TOP(GND_2),
.CO({
out_carry__0_n_0,
out_carry__0_n_1,
out_carry__0_n_2,
out_carry__0_n_3,
out_carry__0_n_4,
out_carry__0_n_5,
out_carry__0_n_6,
out_carry__0_n_7
}),
.DI(sub_left[15:8]),
.O(sub_out[15:8]),
.S(\unsigned_sub_write_data[15] )
);
(* ADDER_THRESHOLD = "35" *)
CARRY8 out_carry__1 (
.CI(out_carry__0_n_0),
.CI_TOP(GND_2),
.CO({
out_carry__1_n_0,
out_carry__1_n_1,
out_carry__1_n_2,
out_carry__1_n_3,
out_carry__1_n_4,
out_carry__1_n_5,
out_carry__1_n_6,
out_carry__1_n_7
}),
.DI(sub_left[23:16]),
.O(sub_out[23:16]),
.S(\unsigned_sub_write_data[23] )
);
(* ADDER_THRESHOLD = "35" *)
CARRY8 out_carry__2 (
.CI(out_carry__1_n_0),
.CI_TOP(GND_2),
.CO({
out_carry__2_n_1,
out_carry__2_n_2,
out_carry__2_n_3,
out_carry__2_n_4,
out_carry__2_n_5,
out_carry__2_n_6,
out_carry__2_n_7
}),
.DI({\<const0> , sub_left[30:24]}),
.O(sub_out[31:24]),
.S(S)
);
endmodule
| 6.592934 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
output logic [WIDTH-1:0] out,
output logic done
);
logic [ WIDTH-1:0] rtmp;
logic [ WIDTH-1:0] ltmp;
logic [(WIDTH << 1) - 1:0] out_tmp;
// Buffer used to walk through the 3 cycles of the pipeline.
logic done_buf[2:0];
assign done = done_buf[2];
assign out = out_tmp[(WIDTH<<1)-INT_WIDTH-1 : WIDTH-INT_WIDTH];
// If the done buffer is completely empty and go is high then execution
// just started.
logic start;
assign start = go & done_buf[0] == 0 & done_buf[1] == 0;
// Start sending the done signal.
always_ff @(posedge clk) begin
if (start) done_buf[0] <= 1;
else done_buf[0] <= 0;
end
// Push the done signal through the pipeline.
always_ff @(posedge clk) begin
if (go) begin
done_buf[2] <= done_buf[1];
done_buf[1] <= done_buf[0];
end else begin
done_buf[2] <= 0;
done_buf[1] <= 0;
end
end
// Move the multiplication computation through the pipeline.
always_ff @(posedge clk) begin
if (reset) begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= 0;
end else if (go) begin
if (SIGNED) begin
rtmp <= $signed(right);
ltmp <= $signed(left);
out_tmp <= $signed({{WIDTH{ltmp[WIDTH-1]}}, ltmp} * {{WIDTH{rtmp[WIDTH-1]}}, rtmp});
end else begin
rtmp <= right;
ltmp <= left;
out_tmp <= ltmp * rtmp;
end
end else begin
rtmp <= 0;
ltmp <= 0;
out_tmp <= out_tmp;
end
end
endmodule
| 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
localparam ITERATIONS = WIDTH + FRAC_WIDTH;
logic [WIDTH-1:0] quotient, quotient_next;
logic [WIDTH:0] acc, acc_next;
logic [$clog2(ITERATIONS)-1:0] idx;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign dividend_is_zero = start && left == 0;
assign finished = idx == ITERATIONS - 1 && running;
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
always_comb begin
if (acc >= {1'b0, right}) begin
acc_next = acc - right;
{acc_next, quotient_next} = {acc_next[WIDTH-1:0], quotient, 1'b1};
end else begin
{acc_next, quotient_next} = {acc, quotient} << 1;
end
end
// `done` signaling
always_ff @(posedge clk) begin
if (dividend_is_zero || finished) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (running) idx <= idx + 1;
else idx <= 0;
end
always_ff @(posedge clk) begin
if (reset) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (start) begin
out_quotient <= 0;
out_remainder <= left;
end else if (go == 0) begin
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end else if (dividend_is_zero) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient_next;
out_remainder <= out_remainder;
end else begin
out_quotient <= out_quotient;
if (right <= out_remainder) out_remainder <= out_remainder - right;
else out_remainder <= out_remainder;
end
end
always_ff @(posedge clk) begin
if (reset) begin
acc <= 0;
quotient <= 0;
end else if (start) begin
{acc, quotient} <= {{WIDTH{1'b0}}, left, 1'b0};
end else begin
acc <= acc_next;
quotient <= quotient_next;
end
end
endmodule
| 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH),
.SIGNED(1)
) comp (
.clk(clk),
.done(done),
.reset(reset),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out_quotient,
output signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_fp_div_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(INT_WIDTH),
.FRAC_WIDTH(FRAC_WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
endmodule
| 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(0)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
output logic done
);
logic [WIDTH-1:0] dividend;
logic [(WIDTH-1)*2:0] divisor;
logic [WIDTH-1:0] quotient;
logic [WIDTH-1:0] quotient_msk;
logic start, running, finished, dividend_is_zero;
assign start = go && !running;
assign finished = quotient_msk == 0 && running;
assign dividend_is_zero = start && left == 0;
always_ff @(posedge clk) begin
// Early return if the divisor is zero.
if (finished || dividend_is_zero) done <= 1;
else done <= 0;
end
always_ff @(posedge clk) begin
if (reset || finished || dividend_is_zero) running <= 0;
else if (start) running <= 1;
else running <= running;
end
// Outputs
always_ff @(posedge clk) begin
if (dividend_is_zero || start) begin
out_quotient <= 0;
out_remainder <= 0;
end else if (finished) begin
out_quotient <= quotient;
out_remainder <= dividend;
end else begin
// Otherwise, explicitly latch the values.
out_quotient <= out_quotient;
out_remainder <= out_remainder;
end
end
// Calculate the quotient mask.
always_ff @(posedge clk) begin
if (start) quotient_msk <= 1 << WIDTH - 1;
else if (running) quotient_msk <= quotient_msk >> 1;
else quotient_msk <= quotient_msk;
end
// Calculate the quotient.
always_ff @(posedge clk) begin
if (start) quotient <= 0;
else if (divisor <= dividend) quotient <= quotient | quotient_msk;
else quotient <= quotient;
end
// Calculate the dividend.
always_ff @(posedge clk) begin
if (start) dividend <= left;
else if (divisor <= dividend) dividend <= dividend - divisor;
else dividend <= dividend;
end
always_ff @(posedge clk) begin
if (start) begin
divisor <= right << WIDTH - 1;
end else if (finished) begin
divisor <= 0;
end else begin
divisor <= divisor >> 1;
end
end
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && $unsigned(out_remainder) != $unsigned(l % r))
$error(
"\nstd_div_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l % r
),
" computed: %0d",
$unsigned(
out_remainder
)
);
if (done && $unsigned(out_quotient) != $unsigned(l / r))
$error(
"\nstd_div_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
$unsigned(
l
),
" right: %0d\n",
$unsigned(
r
),
"expected: %0d",
$unsigned(
l / r
),
" computed: %0d",
$unsigned(
out_quotient
)
);
end
`endif
endmodule
| 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
.WIDTH(WIDTH),
.INT_WIDTH(WIDTH),
.FRAC_WIDTH(0),
.SIGNED(1)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left),
.right(right),
.out(out)
);
endmodule
| 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
output logic signed [WIDTH-1:0] out_remainder,
output logic done
);
logic signed [WIDTH-1:0]
left_abs, right_abs, comp_out_q, comp_out_r, right_save, out_rem_intermediate;
// Registers to figure out how to transform outputs.
logic different_signs, left_sign, right_sign;
// Latch the value of control registers so that their available after
// go signal becomes low.
always_ff @(posedge clk) begin
if (go) begin
right_save <= right_abs;
left_sign <= left[WIDTH-1];
right_sign <= right[WIDTH-1];
end else begin
left_sign <= left_sign;
right_save <= right_save;
right_sign <= right_sign;
end
end
assign right_abs = right[WIDTH-1] ? -right : right;
assign left_abs = left[WIDTH-1] ? -left : left;
assign different_signs = left_sign ^ right_sign;
assign out_quotient = different_signs ? -comp_out_q : comp_out_q;
// Remainder is computed as:
// t0 = |left| % |right|
// t1 = if left * right < 0 and t0 != 0 then |right| - t0 else t0
// rem = if right < 0 then -t1 else t1
assign out_rem_intermediate = different_signs & |comp_out_r ? $signed(
right_save - comp_out_r
) : comp_out_r;
assign out_remainder = right_sign ? -out_rem_intermediate : out_rem_intermediate;
std_div_pipe #(
.WIDTH(WIDTH)
) comp (
.reset(reset),
.clk(clk),
.done(done),
.go(go),
.left(left_abs),
.right(right_abs),
.out_quotient(comp_out_q),
.out_remainder(comp_out_r)
);
// Simulation self test against unsynthesizable implementation.
`ifdef VERILATOR
logic signed [WIDTH-1:0] l, r;
always_ff @(posedge clk) begin
if (go) begin
l <= left;
r <= right;
end else begin
l <= l;
r <= r;
end
end
always @(posedge clk) begin
if (done && out_quotient != $signed(l / r))
$error(
"\nstd_sdiv_pipe (Quotient): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
l / r
),
" computed: %0d",
$signed(
out_quotient
),
);
if (done && out_remainder != $signed(((l % r) + r) % r))
$error(
"\nstd_sdiv_pipe (Remainder): Computed and golden outputs do not match!\n",
"left: %0d",
l,
" right: %0d\n",
r,
"expected: %0d",
$signed(
((l % r) + r) % r
),
" computed: %0d",
$signed(
out_remainder
),
);
end
`endif
endmodule
| 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
module std_slt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left < right);
endmodule
| 8.095256 |
module std_seq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left == right);
endmodule
| 8.302327 |
module std_sneq #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left != right);
endmodule
| 7.44378 |
module std_sge #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left >= right);
endmodule
| 7.297458 |
module std_sle #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left <= right);
endmodule
| 8.057164 |
module std_slsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left <<< right;
endmodule
| 7.70425 |
module std_srsh #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = left >>> right;
endmodule
| 8.663189 |
module std_const #(
parameter WIDTH = 32,
parameter VALUE = 0
) (
output logic [WIDTH - 1:0] out
);
assign out = VALUE;
endmodule
| 8.794277 |
module std_wire #(
parameter WIDTH = 32
) (
input wire logic [WIDTH - 1:0] in,
output logic [WIDTH - 1:0] out
);
assign out = in;
endmodule
| 8.485736 |
module std_slice #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
assign out = in[OUT_WIDTH-1:0];
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH < OUT_WIDTH)
$error(
"std_slice: Input width less than output width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.248138 |
module std_pad #(
parameter IN_WIDTH = 32,
parameter OUT_WIDTH = 32
) (
input wire logic [ IN_WIDTH-1:0] in,
output logic [OUT_WIDTH-1:0] out
);
localparam EXTEND = OUT_WIDTH - IN_WIDTH;
assign out = {{EXTEND{1'b0}}, in};
`ifdef VERILATOR
always_comb begin
if (IN_WIDTH > OUT_WIDTH)
$error(
"std_pad: Output width less than input width\n",
"IN_WIDTH: %0d",
IN_WIDTH,
"OUT_WIDTH: %0d",
OUT_WIDTH
);
end
`endif
endmodule
| 8.450332 |
module std_not #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] in,
output logic [WIDTH-1:0] out
);
assign out = ~in;
endmodule
| 8.707194 |
module std_and #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left & right;
endmodule
| 8.159461 |
module std_or #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left | right;
endmodule
| 8.160076 |
module std_xor #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left ^ right;
endmodule
| 8.185133 |
module std_add #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 7.105468 |
module std_sub #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 7.29825 |
module std_gt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 7.445889 |
module std_lt #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left < right;
endmodule
| 7.925865 |
module std_eq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left == right;
endmodule
| 8.155468 |
module std_neq #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left != right;
endmodule
| 7.624981 |
module std_ge #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left >= right;
endmodule
| 6.896227 |
module std_le #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic out
);
assign out = left <= right;
endmodule
| 8.161124 |
module std_lsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left << right;
endmodule
| 8.684363 |
module std_rsh #(
parameter WIDTH = 32
) (
input wire logic [WIDTH-1:0] left,
input wire logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left >> right;
endmodule
| 8.622539 |
module std_mux #(
parameter WIDTH = 32
) (
input wire logic cond,
input wire logic [WIDTH-1:0] tru,
input wire logic [WIDTH-1:0] fal,
output logic [WIDTH-1:0] out
);
assign out = cond ? tru : fal;
endmodule
| 9.56204 |
module std_reg #(
parameter WIDTH = 32
) (
input wire [ WIDTH-1:0] in,
input wire write_en,
input wire clk,
input wire reset,
// output
output logic [WIDTH - 1:0] out,
output logic done
);
always_ff @(posedge clk) begin
if (reset) begin
out <= 0;
done <= 0;
end else if (write_en) begin
out <= in;
done <= 1'd1;
end else done <= 1'd0;
end
endmodule
| 7.672256 |
module std_mem_d1 #(
parameter WIDTH = 32,
parameter SIZE = 16,
parameter IDX_SIZE = 4
) (
input wire logic [IDX_SIZE-1:0] addr0,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
logic [WIDTH-1:0] mem[SIZE-1:0];
/* verilator lint_off WIDTH */
assign read_data = mem[addr0];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= SIZE)
$error("std_mem_d1: Out of bounds access\n", "addr0: %0d\n", addr0, "SIZE: %0d", SIZE);
end
`endif
endmodule
| 8.560454 |
module std_mem_d2 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0];
assign read_data = mem[addr0][addr1];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d2: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d2: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
end
`endif
endmodule
| 8.570777 |
module std_mem_d3 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [D2_IDX_SIZE-1:0] addr2,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0];
assign read_data = mem[addr0][addr1][addr2];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1][addr2] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
if (addr2 >= D2_SIZE)
$error("std_mem_d3: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE);
end
`endif
endmodule
| 9.018781 |
module std_mem_d4 #(
parameter WIDTH = 32,
parameter D0_SIZE = 16,
parameter D1_SIZE = 16,
parameter D2_SIZE = 16,
parameter D3_SIZE = 16,
parameter D0_IDX_SIZE = 4,
parameter D1_IDX_SIZE = 4,
parameter D2_IDX_SIZE = 4,
parameter D3_IDX_SIZE = 4
) (
input wire logic [D0_IDX_SIZE-1:0] addr0,
input wire logic [D1_IDX_SIZE-1:0] addr1,
input wire logic [D2_IDX_SIZE-1:0] addr2,
input wire logic [D3_IDX_SIZE-1:0] addr3,
input wire logic [ WIDTH-1:0] write_data,
input wire logic write_en,
input wire logic clk,
output logic [ WIDTH-1:0] read_data,
output logic done
);
/* verilator lint_off WIDTH */
logic [WIDTH-1:0] mem[D0_SIZE-1:0][D1_SIZE-1:0][D2_SIZE-1:0][D3_SIZE-1:0];
assign read_data = mem[addr0][addr1][addr2][addr3];
always_ff @(posedge clk) begin
if (write_en) begin
mem[addr0][addr1][addr2][addr3] <= write_data;
done <= 1'd1;
end else done <= 1'd0;
end
// Check for out of bounds access
`ifdef VERILATOR
always_comb begin
if (addr0 >= D0_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr0: %0d\n", addr0, "D0_SIZE: %0d", D0_SIZE);
if (addr1 >= D1_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr1: %0d\n", addr1, "D1_SIZE: %0d", D1_SIZE);
if (addr2 >= D2_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr2: %0d\n", addr2, "D2_SIZE: %0d", D2_SIZE);
if (addr3 >= D3_SIZE)
$error("std_mem_d4: Out of bounds access\n", "addr3: %0d\n", addr3, "D3_SIZE: %0d", D3_SIZE);
end
`endif
endmodule
| 9.168498 |
module binary #(
parameter depth = 32,
parameter target_depth = 2,
parameter WIDTH = 3
) (
input reg signed [ depth-1:0] data_raw [WIDTH-1:0],
output reg signed [target_depth-1:0] data_binarized[WIDTH-1:0]
);
genvar cnt;
generate
for (cnt = 0; cnt < WIDTH; cnt = cnt + 1) begin : binaryLoop
always @(*) begin
if (data_raw[cnt] >= 'd0) begin
data_binarized[cnt] <= 3'd1;
end else begin
data_binarized[cnt] <= -3'd1;
end
end
end
endgenerate
endmodule
| 7.03472 |
module binary2bcdlight (
clk,
en,
a,
seg_led,
seg_sel
);
input clk, en;
input [7:0] a;
output wire [7:0] seg_led;
output wire [5:0] seg_sel;
wire [3:0] bcd1, bcd2, bcd3;
binary2bcd binary (
.a(a),
.b({bcd3[3:0], bcd2[3:0], bcd1[3:0]})
);
wire tmp_clk;
clock_division fp (
.clk_in(clk),
.divclk(tmp_clk)
);
wire [1:0] tmp_cnt;
counter count (
.clk(tmp_clk),
.cnt(tmp_cnt)
);
wire [3:0] reg_1, reg_2, reg_3;
register_4bit register_1 (
.clk(clk),
.data_in(bcd1),
.en(en),
.data_out(reg_1)
);
register_4bit register_2 (
.clk(clk),
.data_in(bcd2),
.en(en),
.data_out(reg_2)
);
register_4bit register_3 (
.clk(clk),
.data_in(bcd3),
.en(en),
.data_out(reg_3)
);
wire [3:0] data_disp;
Mux Mux (
.sel(tmp_cnt),
.ina(reg_1),
.inb(reg_2),
.inc(reg_3),
.data_out(data_disp)
);
seg_sel_decoder seg_sel_decoder (
.bit_disp(tmp_cnt),
.seg_sel (seg_sel)
);
seg_led_decoder seg_led_decoder (
.data_disp(data_disp),
.seg_led (seg_led)
);
endmodule
| 7.198317 |
module binary2decimal (
d0,
d1,
d2,
d3,
d4,
d5,
d6,
d7,
d8,
d9,
b3,
b2,
b1,
b0
);
input d0;
input d1;
input d2;
input d3;
input d4;
input d5;
input d6;
input d7;
input d8;
input d9;
output b3;
output b2;
output b1;
output b0;
wire w18;
wire w16;
wire w14;
wire w12;
wire w10;
wire w19;
wire w20;
wire w21;
wire w22;
wire w13;
wire w15;
wire w17;
wire w23;
wire w24;
wire w25;
wire w26;
assign w10 = d0;
assign w22 = d1;
assign w12 = d2;
assign w13 = d3;
assign w14 = d4;
assign w15 = d5;
assign w16 = d6;
assign w17 = d7;
assign w18 = d8;
assign w23 = d9;
assign b3 = w19;
assign b2 = w20;
assign b1 = w21;
assign b0 = w24;
PNU_OR2 s0 (
.i1(w18),
.o1(w19),
.i2(w23)
);
PNU_OR4 s1 (
.i3(w16),
.i1(w14),
.o1(w20),
.i2(w15),
.i4(w17)
);
PNU_OR4 s2 (
.i3(w16),
.i1(w12),
.o1(w21),
.i2(w13),
.i4(w17)
);
PNU_OR2 s3 (
.i1(w22),
.i2(w13),
.o1(w25)
);
PNU_OR3 s4 (
.i1(w15),
.i2(w17),
.i3(w23),
.o1(w26)
);
PNU_OR2 s5 (
.o1(w24),
.i1(w25),
.i2(w26)
);
endmodule
| 6.611924 |
module is used to covert binary counter into gray code.
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Binary2Gray #(
parameter WIDTH=5
) (
input [WIDTH-1:0] BIN_i,
output [WIDTH-1:0] GRAY_o
);
reg [WIDTH-1:0] g;
wire [WIDTH-1:0] b;
integer i;
assign b = BIN_i;
assign GRAY_o = g;
always @(*) begin
g[WIDTH-1] <= b[WIDTH-1];
for(i=0;i<WIDTH-1;i=i+1)
g[i] <= b[i]^b[i+1];
end
//assign g[4] = b[4];
//assign g[3] = b[3]^b[4];
//assign g[2] = b[2]^b[3];
//assign g[1] = b[1]^b[2];
//assign g[0] = b[0]^b[1];
endmodule
| 6.693155 |
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