code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Reg4bit (
output wire [3:0] O,
input wire SP,
input wire Is,
input wire [3:0] Ip,
input wire C,
input wire CE,
input wire nCLR
);
wire CCE;
and (CCE, C, CE);
RS1bit r3 (
O[3],
SP,
Is,
Ip[3],
CCE,
nCLR
);
RS1bit r2 (
O[2],
SP,
... | 8.011379 |
module sra (
input wire s, // puesta a '1'
input wire r, // puesta a '0'
output reg q // estado (valor almacenado)
/* Las variables (tipo 'reg') son el único tipo de señal que pueden
* retener su valor y por tanto deben usarse para describir
* comportamiento secuencial (con memoria) */
);... | 7.412971 |
module srl (
input wire ck, // reloj
input wire s, // puesta a '1'
input wire r, // puesta a '0'
output reg q // estado
);
always @(ck, s, r)
case ({
ck, s, r
})
3'b101: q <= 1'b0;
3'b110: q <= 1'b1;
3'b111: q <= 1'bx;
endcase
endmodule
| 7.074097 |
module srms (
input wire ck,
input wire s,
input wire r,
output wire q
);
srl master (
.ck(ck),
.s (s),
.r (r),
.q (qm)
);
/* Las entradas del esclavo se conectan de forma que copien el estado
* del maestro. */
srl slave (
.ck(ck_neg),
.s (qm),
... | 7.701316 |
module RS_C (
output wire Q,
output wire NQ,
input wire R,
input wire S,
input wire C
);
wire RC, SC;
and (RC, R, C);
and (SC, C, S);
RS rs1 (
Q,
NQ,
RC,
SC
);
endmodule
| 8.080012 |
module RS_CA (
output wire Q,
output wire NQ,
input wire R,
input wire S,
input wire C
);
wire NC, DET;
not #(1) (NC, C);
and (DET, NC, C);
RS_C rs1 (
Q,
NQ,
R,
S,
DET
);
endmodule
| 8.348841 |
module T (
output reg Q,
input wire T
);
initial Q = 0;
always @(negedge T) Q = ~Q;
endmodule
| 7.299747 |
module T (
output reg Q,
output wire nQ,
input wire T,
input wire nPRESET,
input wire nCLEAR
);
initial Q = 0;
not (nQ, Q);
always @(negedge T) if (nPRESET && nCLEAR) Q = ~Q;
always @(nPRESET, nCLEAR)
case ({
nPRESET, nCLEAR
})
2'b01: Q = 1;
2'b10: Q = 0;
... | 7.299747 |
module Thold (
output wire Q,
output wire nQ,
input wire T,
input wire nPRESET,
input wire nCLEAR,
input wire nHOLD
);
wire a1s, a2s, o1s, o2s;
T t1 (
Q,
nQ,
T,
a2s,
a1s
);
or (o1s, nHOLD, Q);
or (o2s, nHOLD, nQ);
and (a1s, o1s, nCLEAR);
and (a2s... | 6.76102 |
module BigALU (
input [31:0] src1,
input [31:0] src2,
input [3:0] alu_ctrl,
output reg zero,
output reg [31:0] alu_out
);
always @* begin
case (alu_ctrl)
4'b0000: alu_out = src1 & src2;
4'b0001: alu_out = src1 | src2;
4'b0010: alu_out = src1 + src2;
4'b0110: alu_out = s... | 8.436403 |
module bigCircle (
input Pi,
input Gi,
input Pprev,
input Gprev,
output P,
output G
);
wire w;
and and0 (P, Pi, Pprev);
and and1 (w, Pi, Gprev);
or or0 (G, Gi, w);
endmodule
| 7.016847 |
module bigfifo (
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full,
wr_data_count
);
input [8 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [8 : 0] dout;
output empty;
output full;
output [16 : 0] wr_data_count;
... | 7.101283 |
module bigger #(
parameter xDW = 16
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
input wire clk, //时钟
input wire signed [(xDW -1 ) : 0] x, //输入16位有符号数
output reg OUT, //输出，判断为真=1，假=0
output reg valid //输出是否有效
);
wire EN;
AND_2_1 AND_2_1_inst (
.IN_1(... | 7.505889 |
module biggerAndSmallerOrEqual #(
parameter xDW = 16
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
//input wire clk, //时钟
input wire [(xDW - 1) : 0] a,
input wire [(xDW - 1) : 0] b,
input wire [(xDW - 1) : 0] xAbs, //输入16位无符号数
output reg OUT, //输出，判断为真=1，假=0
... | 7.052223 |
module biggerOrEqual #(
parameter xDW = 16
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
input wire clk, //时钟
input wire signed [(xDW -1 ) : 0] x, //输入16位有符号数
output reg OUT, //输出，判断为真=1，假=0
output reg valid //输出是否有效
);
wire EN;
AND_2_1 AND_2_1_inst (
... | 6.956823 |
module biggerOrEqualAndSmaller #(
parameter xDW = 16
) (
input wire en, //使能端，=1工作，=0不工作且输出valid=0&OUT=0
input wire rst_n,
//input wire clk, //时钟
input wire [(xDW - 1) : 0] a,
input wire [(xDW - 1) : 0] b,
input wire [(xDW - 1) : 0] xAbs, //输入16位无符号数
output reg OUT, //输出，判断为真=1，假=0
... | 6.956823 |
module biggest #(
//parameter N_DATA = 2, // Data's binary repr length
parameter N_KEY = 16 // Key's binary repr length
) (
input clk,
input reset,
input enable,
input [2-1:0] data,
input [N_KEY-1:0] key,
output reg [N_KEY-1:0] max_key
);
reg [2*8-1:0] mem_data;
reg [2-1:0] max_da... | 7.579699 |
module bigmux.v (
input [0:1023] in,
input [0:9] sel,
output y);
assign y= in[sel];
endmodule
| 6.762397 |
module bigproduct (
input [10:0] mantissa_A,
input [10:0] mantissa_B,
output reg [21:0] product
);
always @(mantissa_A, mantissa_B) begin
product = mantissa_A * mantissa_B;
end
endmodule
| 7.062375 |
module bigshift (
clk,
inp,
out
);
parameter BITS = 7500;
input clk;
input inp;
output out;
reg [BITS-1:0] r;
always @(posedge clk) r <= {r[BITS-2:0], inp};
assign out = r[BITS-1];
endmodule
| 7.216364 |
module bigsmpy (
i_clk,
i_sync,
i_sgn,
i_a,
i_b,
o_r,
o_sync
);
parameter NCLOCKS = 1;
input wire i_clk, i_sync, i_sgn;
input wire [31:0] i_a, i_b;
output reg [63:0] o_r;
output reg o_sync;
generate
if (NCLOCKS == 1) begin
wire signed [31:0] w_sa, w_sb;
wire [31:... | 6.787472 |
module bigsum (
input sign_A,
input sign_B,
input [10:0] mantissa_A,
input [10:0] mantissa_B,
output reg sign_res,
output reg [11:0] bigsum12
);
always @(mantissa_A, mantissa_B, sign_A, sign_B) begin
case ({
sign_A, sign_B
})
2'b00, 2'b11: begin
bigsum12 = mantiss... | 6.821909 |
module bigword (
input clk,
input rst,
input newframe,
input [9:0] x, // Current pixel to evaluate
input [9:0] y,
input fizzOrBuzz,
output reg out // 1 = set pixel
);
reg dx, dy; // 1 = increment, 0 = decrement
reg [9:0] xpos; // Position of the moving box
reg [9:0] ypos;
reg... | 7.499662 |
module generic_fifo_sc_a #(
parameter dw = 8,
parameter aw = 8
) (
clk,
rst,
clr,
din,
we,
dout,
re,
full,
empty
);
parameter max_size = 1 << aw;
input clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input wire re;
output full;
output empt... | 6.701278 |
module dpram #(
parameter DWIDTH = 32,
parameter AWIDTH = 10
) (
clk,
address_a,
address_b,
wren_a,
wren_b,
data_a,
data_b,
out_a,
out_b
);
parameter NUM_WORDS = 1 << AWIDTH;
input clk;
input [(AWIDTH-1):0] address_a;
input [(AWIDTH-1):0] address_b;
input wren_a;
... | 7.813216 |
module big_function (
in,
key,
out
);
input [1:32] in;
input [1:48] key;
output [1:32] out;
wire [1:48] expanded;
selection_table uut (
in,
expanded
);
wire [1:6] box1, box2, box3, box4, box5, box6, box7, box8;
assign {box1, box2, box3, box4, box5, box6, box7, box8} = expand... | 7.602803 |
module bijiao (
input [31:0] datatwo,
output dataone
);
assign dataone = ($signed(datatwo) >= 0) ? 1 : 0;
endmodule
| 7.294582 |
module bijiaoqi (
input [31:0] a,
input [31:0] b,
output c
);
assign c = (a == b) ? 1 : 0;
endmodule
| 8.537185 |
module bijiaoqi_bltz (
input [31:0] bltz_data,
output bltz_dataout
);
assign bltz_dataout = ($signed(bltz_data) < 0) ? 1 : 0;
endmodule
| 7.824259 |
module bijiaoqi_bne (
input [31:0] a,
input [31:0] b,
output c
);
assign c = (a != b) ? 1 : 0;
endmodule
| 7.548005 |
module bijiaoqi_movz (
input [31:0] a,
output b
);
assign b = (a == 0) ? 1 : 0;
endmodule
| 7.830266 |
module bijiao_bgtz (
input [31:0] bgtz_data,
output bgtz_dataout
);
assign bgtz_dataout = ($signed(bgtz_data) > 0) ? 1 : 0;
endmodule
| 8.189529 |
module bijiao_blez (
input [31:0] blez_data,
output blez_dataout
);
assign blez_dataout = ($signed(blez_data) <= 0) ? 1 : 0;
endmodule
| 8.071908 |
module ramFifo #(
parameter DATA_WIDTH = 8,
parameter ADDRESS_WIDTH = 8,
parameter BUFFER_SIZE = 3,
parameter BUFFER_SIZE_WIDTH = ((BUFFER_SIZE+1) <= 2) ? 1 : //wide enough to hold value BUFFER_SIZE + 1
((BUFFER_SIZE+1) <= 4) ? 2 :
((BUFFER_SIZE+1) <= 8) ? 3 :
((BUFFER_SIZE+1) <= 1... | 8.218147 |
module ramDualPort #(
parameter DATA_WIDTH = 8,
parameter ADDRESS_WIDTH = 8
) (
input wire [(DATA_WIDTH-1):0] dataA,
dataB,
input wire [(ADDRESS_WIDTH-1):0] addrA,
addrB,
input wire weA,
weB,
clk,
output reg [(DATA_WIDTH-1):0] qA,
qB
);
// Declare the RAM variable
reg [D... | 8.70941 |
module bilinearintrp (
u01a,
u01b,
u01c,
v01a,
v01b,
v01c,
u10a,
u10b,
u10c,
v10a,
v10b,
v10c,
selectuv,
ru,
rv,
rw,
gu,
gv,
gw,
bu,
bv,
bw,
r,
g,
b,
clk
);
input [7:0] u01a;
input [7:0] u01b;
input [7:0] u01c... | 6.725338 |
module bimodal (
in_PC,
in_hit,
in_Clk,
in_Rst_N,
out_prediction
);
input in_hit, in_Clk, in_Rst_N;
input [8:0] in_PC;
output out_prediction;
pht pht_Inst0 (
.in_addr(in_PC),
.in_data(in_hit),
.in_Clk(in_Clk),
.in_Rst_N(in_Rst_N),
.out_prediction(out_prediction... | 6.767516 |
module Bimodal_Table (
Clk,
wr,
rd,
index /*pc*/,
rdata_c_bits,
correct_prediction,
inc_counter,
dec_counter,
update_enable
);
parameter IL = 13; //Index size ie number of addresses
parameter CL = 3; //Counter length
reg [CL-1 : 0] c_bits[(1 << IL) - 1 : 0]; //Counter tab... | 6.659628 |
module bimpy #(
// {{{
parameter BW = 18, // Number of bits in i_b
// DESIGN COMPILER MODIFICATON - Parameters must be declared before use
parameter LUTB = 2 // Number of bits in i_a for our LUT multiply
// }}}
) (
// {{{
input wire i_clk,
i_reset,
i_ce,
input wire [(LUTB-1... | 6.898984 |
module BIN12_to_DEC4 (
input [11:0] BIN,
output wire [15:0] DEC,
input st,
output reg [2:0] ptr_dig = 0, //
input clk,
output reg en_conv = 0
); //
reg [ 3:0] D1dec = 0;
reg [ 3:0] D2dec = 0;
reg [ 3:0] D3dec = 0;
reg [ 3:0] D4dec = 0;
reg [16:0] rest = 0; //
assign DEC = {D4d... | 7.018131 |
module BIN16_to_DEC4 (
input [15:0] BIN,
output reg [15:0] DEC = 0,
input clk,
output reg [4:0] ptr_dig = 0, //
input st,
output reg en_conv = 0,
output reg ok = 0
);
//----
reg [3:0] D1dec = 0;
reg [3:0] D2dec = 0;
reg [3:0] D3dec = 0;
reg [3:0] D4dec = 0;
reg q = 0;
re... | 6.941222 |
module bin2AsciiHex (
output wire [7:0] asciiHex,
input [3:0] hx
);
wire lowerTen;
assign lowerTen = ~hx[3] | ~hx[2] & ~hx[1];
assign asciiHex = lowerTen ?
{4'h3, hx[3:0]} :
{4'h6, 1'b0,
~hx[1] & hx[0] | hx[2] & hx[1],
~hx[1] & ~hx[0] | hx[1] & hx[0],... | 6.715758 |
module bin2AsciiHex (
// output reg [7:0] asciiHex,
// input [3:0] inVal);
//
// always @(*) begin
// casex (inVal)
// 4'ha : asciiHex = 8'h61;
// 4'hb : asciiHex = 8'h62;
// 4'hc : asciiHex = 8'h63;
// 4'hd : asciiHex = 8'h64;
// 4'he : asciiHex = 8'h65;
// 4'hf : asciiHex = 8'h66;
// default : asciiHex ... | 6.715758 |
module bin2bcd32 (
input CLK,
input RST,
input en,
input [31:0] bin,
output [3:0] bcd0,
output [3:0] bcd1,
output [3:0] bcd2,
output [3:0] bcd3,
output [3:0] bcd4,
output [3:0] bcd5,
output [3:0] bcd6,
output [3:0] bcd7,
output [3:0] bcd8,
output [3:0] bc... | 6.8071 |
module bin2bcd_12 (
input wire clk,
nrst,
input wire start,
input wire [11:0] bin,
output reg [15:0] bcd,
output reg valid
);
reg [11:0] bin_in;
reg op;
reg [3:0] cnt;
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bin_in <= 0;
else if (start) bin_in <= bin;
end
... | 7.16587 |
module bin2bcd_c (
input wire clk,
nrst,
input wire start,
input wire [11:0] bin,
output reg [15:0] bcd,
output reg valid
);
reg [11:0] bin_in;
reg op;
reg [3:0] cnt;
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bin_in <= 0;
else if (start) bin_in <= bin;
end
... | 7.100714 |
module bcd_digit (
input wire clock,
input wire ce,
input wire init,
input wire mod_in,
output wire mod_out,
output reg [3:0] digit
);
wire fiveOrMore = digit >= 5;
assign mod_out = fiveOrMore & ~init;
always @(posedge clock) begin
if (ce) begin
digit[0] <= mod_in;
digit[... | 6.918817 |
module bin2bcd_test (
input wire clk,
reset,
input wire btn,
input wire [12:0] sw,
output wire [ 3:0] an,
output wire [ 7:0] sseg,
output wire [ 1:0] led
);
// signal declaration
wire start;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
// instance of debouncer
debounce db_... | 8.045954 |
module bin2bcd_testbench;
reg [13:0] in;
wire [15:0] out;
integer i;
bin2bcd myConverter (
.binary(in),
.bcd(out)
);
initial begin
in <= 0;
$monitor("in=0x%0h out=%0b", in, out);
for (i = 0; i < 32; i = i + 1) begin
in = i;
#10;
end
#10;
in = 8'b11110011;
... | 6.67359 |
module Bin2Chr (
bin,
chr
);
input [2:0] bin;
output reg [7:0] chr;
always @(*) begin
case (bin)
3'b000: chr <= 8'd48; // 0
3'b001: chr <= 8'd49; // 1
3'b010: chr <= 8'd50; // 2
3'b011: chr <= 8'd51; // 3
3'b100: chr <= 8'd52; // 4
3'b101: chr <= 8'd53; ... | 6.62552 |
module bin2comp #(
parameter NUMBER_OF_BITS = 12
) (
bin,
inv_add
);
//Input
input [NUMBER_OF_BITS-1:0] bin;
//Ouput
output [NUMBER_OF_BITS-1:0] inv_add;
assign inv_add = bin[NUMBER_OF_BITS-1] ? (~bin + 1'b1) : bin;
// assign inv_add = (~ bin +1'b1);
endmodule
| 6.990781 |
module bin2gray #(
parameter WIDTH = 8
) (
input [WIDTH-1:0] bin,
output [WIDTH-1:0] gray
);
assign gray = (bin >> 1) ^ bin;
endmodule
| 7.498057 |
module bin2gray_tb;
reg clock = 1;
always #5 clock <= ~clock;
reg reset = 0;
reg [`MSB:0] count_b = 0;
wire [`MSB:0] count_g;
always @(posedge clock)
if (reset) count_b <= 0;
else count_b <= count_b + 1;
initial begin : Sim
$display("%t: Count = %d, Gray = %b", $time, count_b, count_g... | 6.624144 |
module bin2hex (
input [3:0] in,
output reg [7:0] out
);
always @(in) begin
case (in)
4'h0: out = 7'h30;
4'h1: out = 7'h31;
4'h2: out = 7'h32;
4'h3: out = 7'h33;
4'h4: out = 7'h34;
4'h5: out = 7'h35;
4'h6: out = 7'h36;
4'h7: out = 7'h37;
4'h8: out = 7... | 7.54151 |
module bin2hex32 (
input wire [31:0] value,
output wire [ 3:0] dig0,
output wire [ 3:0] dig1,
output wire [ 3:0] dig2,
output wire [ 3:0] dig3,
output wire [ 3:0] dig4,
output wire [ 3:0] dig5,
output wire [ 3:0] dig6,
output wire [ 3:0] dig7
);
assign dig0 = value & 4'hFF;
ass... | 6.687659 |
module receives a 4-bit input and converts it to 7-segment
// LED (HEX)
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: INCOMPLETE CODE
//
//////////////////////////////////////////////////////////////////////////////////
module binary_to_segment(
input[2:0] player_sc... | 6.985545 |
module bin2onehot #(
parameter DW = 32
) (
input [NB-1:0] bin, // unsigned binary input
output [DW-1:0] onehot // one hot output vector
);
parameter NB = $clog2(DW);
`ifdef OPTIMISED
integer i;
reg [DW-1:0] ronehot;
always @(*) begin
for (i = 0; i < DW; i = i + 1) ronehot[i] = (bin[NB-1:0... | 6.976573 |
module bin2seg (
input wire [3:0] bin,
output reg [7:0] seg
);
always @(bin) begin
case (bin)
4'd0: seg = 8'b0000_0011; // 0
4'd1: seg = 8'b1001_1111; // 1
4'd2: seg = 8'b0010_0101; // 2
4'd3: seg = 8'b0000_1101; // 3
4'd4: seg = 8'b1001_1001; // 4
4'd5: seg = 8'... | 7.226392 |
module top (
input clock_100Mhz, // 100 Mhz clock source on Basys 3 FPGA
input reset, // reset
output reg [3:0] Anode_Activate, // anode signals of the 7-segment LED display
output reg [6:0] LED_out // cathode patterns of the 7-segment LED display
);
reg [26:0] one_second_counter; // counter for ... | 7.233807 |
module BIN32_to_DEC8 (
input [31:0] BIN,
output reg [31:0] DEC = 0,
input clk,
output reg [3:0] ptr_dig = 0, //
input st,
output reg en_conv = 0,
output reg ok_conv = 0
);
reg [3:0] D1dec = 0;
reg [3:0] D2dec = 0;
reg [3:0] D3dec = 0;
reg [3:0] D4dec = 0;
reg [3:0] D5dec = 0;
... | 6.780046 |
module Bin8Bcd10 (
input wire [7:0] b,
output reg [9:0] led
);
reg [17:0] z;
integer i;
always @(*) begin
for (i = 0; i <= 17; i = i + 1) z[i] = 0;
z[10:3] = b;
repeat (5) begin
if (z[11:8] > 4) z[11:8] = z[11:8] + 3;
if (z[15:12] > 4) z[15:12] = z[15:12] + 3;
z[17:1] = ... | 6.569694 |
module bin8_to_bcd (
i_bin,
o_bcd
);
input [7:0] i_bin;
output reg [11:0] o_bcd;
integer i;
always @* begin
o_bcd = 0;
for (i = 0; i < 8; i = i + 1) begin
o_bcd = {o_bcd[10:0], i_bin[7-i]};
if (i < 7 && o_bcd[3:0] > 4) o_bcd[3:0] = o_bcd[3:0] + 3;
if (i < 7 && o_bcd[7:4... | 6.948654 |
module bin8_to_bcd_DE10_Lite (
SW,
HEX0,
HEX1,
HEX2
);
input [9:0] SW;
output [6:0] HEX0, HEX1, HEX2;
wire [11:0] bcd;
bin8_to_bcd bin2bcd_inst (
.i_bin(SW[7:0]),
.o_bcd(bcd)
);
dec_7seg bcd0 (
.i_dat(bcd[3:0]),
.o_seg(HEX0)
);
dec_7seg bcd1 (
.i_dat(bc... | 6.715793 |
module testbench;
parameter DELAY = 20;
reg [7:0] bin;
wire [11:0] bcd;
integer i;
bin8_to_bcd bin2bcd_inst (
.i_bin(bin),
.o_bcd(bcd)
);
initial begin
for (i = 0; i < 256; i = i + 1) begin
bin = i;
#DELAY;
end
$finish;
end
endmodule
| 7.015571 |
module binario_bcd (
binario,
unidade,
dezena,
centena,
milhar,
d_milhar,
c_milhar,
milhao,
d_milhao
);
input [31:0] binario;
output reg [3:0] unidade, dezena, centena, milhar, d_milhar, c_milhar, milhao, d_milhao;
integer i;
always @(binario) begin
unidade = 4'b0;
... | 6.789979 |
module binarization (
input clk, // 时钟信号
input rst_n, // 复位信号，低电平有效
//图像处理前的数据接口
input pre_frame_vsync , // vsync信号
input pre_frame_hsync , // hsync信号
input pre_frame_de , // data enable信号
input [7:0] color ,
//图像处理后的数据接口
output post_frame_vsy... | 8.748897 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_rea... | 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividen... | 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0]... | 6.968167 |
module std_sub (
out0,
a,
b
);
output [31:0] out0;
input [31:0] a;
input [31:0] b;
wire [31:0] a;
wire [31:0] b;
wire [31:0] out0;
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
.a(a),
.b(b),
.out0(out0)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_rea... | 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividen... | 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0]... | 6.968167 |
module std_sub (
out0,
a,
b
);
output [31:0] out0;
input [31:0] a;
input [31:0] b;
wire [31:0] a;
wire [31:0] b;
wire [31:0] out0;
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
.a(a),
.b(b),
.out0(out0)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_rea... | 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividen... | 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0]... | 6.968167 |
module std_sub (
out0,
a,
b
);
output [31:0] out0;
input [31:0] a;
input [31:0] b;
wire [31:0] a;
wire [31:0] b;
wire [31:0] out0;
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
.a(a),
.b(b),
.out0(out0)
);
endmodule
| 6.592934 |
module std_mult_pipe (
mul_done,
out_tmp_reg,
Q,
clk,
E,
reset,
do_unsigned_mul_go_in,
rhs_read_data,
lhs_read_data
);
output mul_done;
output [15:0] out_tmp_reg;
output [15:0] Q;
input clk;
input [0:0] E;
input reset;
input do_unsigned_mul_go_in;
input [31:0] rhs_rea... | 7.504255 |
module std_sdiv_pipe (
sdiv_done,
signed_mod_write_data,
signed_div_write_data,
SR,
signed_div_write_en,
reset_0,
\quotient_msk_reg[0] ,
Q,
done0,
clk,
E,
srhs_read_data,
slhs_read_data,
running_reg,
do_signed_div_mod_go_in,
\dividend_reg[3] ,
\dividen... | 7.505299 |
module std_smult_pipe (
smul_done,
signed_mul_write_data,
clk,
do_signed_mul_go_in,
reset,
D,
\ltmp_reg[3] ,
E
);
output smul_done;
output [3:0] signed_mul_write_data;
input clk;
input do_signed_mul_go_in;
input reset;
input [3:0] D;
input [3:0] \ltmp_reg[3] ;
input [0:0]... | 6.968167 |
module std_sub (
out0,
a,
b
);
output [31:0] out0;
input [31:0] a;
input [31:0] b;
wire [31:0] a;
wire [31:0] b;
wire [31:0] out0;
lakeroad_xilinx_ultrascale_plus_sub32_2 _impl (
.a(a),
.b(b),
.out0(out0)
);
endmodule
| 6.592934 |
module std_fp_add #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left + right;
endmodule
| 9.124708 |
module std_fp_sub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] out
);
assign out = left - right;
endmodule
| 8.85803 |
module std_fp_mult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16,
parameter SIGNED = 0
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic go,
input logic clk,
input logic reset,
... | 6.609331 |
module std_fp_div_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic go,
input logic clk,
input logic reset,
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic [WIDTH-1:0] o... | 7.871496 |
module std_fp_gt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
output logic out
);
assign out = left > right;
endmodule
| 8.426383 |
module std_fp_sadd #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.768295 |
module std_fp_ssub #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.839041 |
module std_fp_smult_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0]... | 7.173413 |
module std_fp_sdiv_pipe #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input clk,
input go,
input reset,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH... | 8.37227 |
module std_fp_sgt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left > right);
endmodule
| 8.236193 |
module std_fp_slt #(
parameter WIDTH = 32,
parameter INT_WIDTH = 16,
parameter FRAC_WIDTH = 16
) (
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed out
);
assign out = $signed(left < right);
endmodule
| 8.595041 |
module std_mult_pipe #(
parameter WIDTH = 32
) (
input logic [WIDTH-1:0] left,
input logic [WIDTH-1:0] right,
input logic reset,
input logic go,
input logic clk,
output logic [WIDTH-1:0] out,
output logic done
);
std_fp_mult_pipe #(
... | 7.504255 |
module std_div_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input [WIDTH-1:0] left,
input [WIDTH-1:0] right,
output logic [WIDTH-1:0] out_remainder,
output logic [WIDTH-1:0] out_quotient,
out... | 6.929139 |
module std_sadd #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left + right);
endmodule
| 8.670882 |
module std_ssub #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed [WIDTH-1:0] out
);
assign out = $signed(left - right);
endmodule
| 8.103836 |
module std_smult_pipe #(
parameter WIDTH = 32
) (
input logic reset,
input logic go,
input logic clk,
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out,
output logic... | 6.968167 |
module std_sdiv_pipe #(
parameter WIDTH = 32
) (
input reset,
input clk,
input go,
input logic signed [WIDTH-1:0] left,
input logic signed [WIDTH-1:0] right,
output logic signed [WIDTH-1:0] out_quotient,
outp... | 7.505299 |
module std_sgt #(
parameter WIDTH = 32
) (
input signed [WIDTH-1:0] left,
input signed [WIDTH-1:0] right,
output signed out
);
assign out = $signed(left > right);
endmodule
| 7.663941 |
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