code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module beta_read_decode (
input wire clk,
input wire [2:0] read_select, //need to pipeline
input wire [31:0] ram_dout,
input wire [31:0] IO_dout,
input wire [31:0] shared_read_dout,
input wire [31:0] shared_write_dout,
output reg [31:0] beta_mdin = 0
);
reg [2:0] old_read_select = 0;
always @(posedge clk) begin
old_read_select <= read_select;
end
always @(*) begin
case (old_read_select)
0: begin //select ram
beta_mdin <= ram_dout;
end
1: begin //select IO
beta_mdin <= IO_dout;
end
2: begin //select shared_read
beta_mdin <= shared_read_dout;
end
3: begin //select shared write
beta_mdin <= shared_write_dout;
end
default: begin //this should not happen, select ram?
beta_mdin <= ram_dout;
end
endcase
end
endmodule
| 8.210318 |
module ascii_input (
input clk25, // 25MHz clock
input rst, // active high reset
input enable, // active high reset
// I/O interface to virtual disk
input ioctl_download,
//output reg ioctl_wait,
output ioctl_wait,
input [ 7:0] ioctl_data,
input [13:0] ioctl_addr,
// I/O interface to computer
input cs, // chip select, active high
input address, // =0 RX buffer, =1 RX status
output reg [7:0] dout, // 8-bit output bus.
output data_ready // 8-bit output bus.
);
assign data_ready = ascii_rdy | ioctl_download;
reg nextbyte = 0;
assign ioctl_wait = nextbyte;
reg [7:0] counter = 0;
// keyboard translation signals
reg [7:0] ascii; // ASCII code of received character
reg ascii_rdy; // new ASCII character received
always @(posedge clk25 or posedge rst) begin
if (rst) begin
ascii_rdy <= 0;
//ioctl_wait = 0 ;
end else begin
// get a byte from the virtual disk
if (!ascii_rdy & ioctl_download) begin
ascii = ioctl_data;
// case(ioctl_data)
// 8'h0A: ascii=8'h0D;
// default: ascii= ioctl_data;
// endcase
ascii_rdy <= 1;
nextbyte = 1;
counter = 0;
// $display("inside a %x %x",ascii,ioctl_data);
end
// ioctl_wait = enable;
// handle I/O from CPU
if (cs == 1'b1) begin
if (address == 1'b0) begin
//$display("inside rx buffer %x %c %x %x %x ena %x" ,ascii, ascii,ascii_rdy,textinput_addr,textinput_dout,enable);
// RX buffer address
dout <= {1'b1, ascii[6:0]};
ascii_rdy <= 1'b0;
counter = counter + 1;
if (counter == 8) nextbyte = 0;
//$display("dout %x ",dout);
$display("ascii send %x %x", dout, enable);
// if (enable) nextbyte = 0;
end else begin
// RX status register
dout <= {ascii_rdy, 7'b0};
//if (dout!=0) $display("dout %x ",dout);
end
end
end
end
endmodule
| 7.377676 |
module BET_FSM (
clk_50,
rst,
// ram (BET) ports
ram_addr,
ram_r,
ram_w,
ram_w_en,
// garbage collection ports
garbage_en,
garbage_state,
garbage_addr
);
parameter T = 100;
parameter BET_size = 8192;
parameter cmp_ratio = 3'd0,
cmp_flag_count = 3'd1,
rst_bet = 3'd2,
read_bet = 3'd3,
check_flag = 3'd4,
errase_start = 3'd5,
errase_done = 3'd6;
input clk_50, rst;
input ram_r, garbage_state;
output ram_w, ram_w_en, garbage_en;
output [11:0] garbage_addr, ram_addr;
reg ram_w, ram_w_en, flag, garbage_en;
reg [2:0] NS, S;
reg [11:0] f_index, f_index_next, ram_addr, garbage_addr, count;
reg [31:0] e_cnt, f_cnt, ratio;
always @(posedge clk_50 or negedge rst) begin
if (rst == 1'b0) begin
S <= cmp_ratio;
NS <= cmp_ratio;
end else begin
S <= NS;
case (S)
cmp_ratio: begin
if (ratio < T) NS <= cmp_ratio;
else NS <= cmp_flag_count;
end
cmp_flag_count: begin
if (f_cnt < BET_size) NS <= read_bet;
else NS <= rst_bet;
end
rst_bet: begin
if (count <= BET_size) begin
count <= count + 1'b1;
ram_w_en <= 1'b1;
ram_w <= 1'b0;
ram_addr <= count;
end else begin
f_cnt <= 32'd0;
count <= 12'd0;
NS <= cmp_ratio;
end
end
read_bet: begin
flag <= ram_r;
ram_addr <= f_index_next;
end
check_flag: begin
if (flag == 1'b1) begin
NS <= read_bet;
f_index <= f_index_next;
f_index_next <= f_index_next + 1'b1;
end else begin
NS <= errase_start;
end
end
errase_start: begin
garbage_addr <= f_index;
if (garbage_state == 1'b0) begin
garbage_en <= 1'b1;
NS <= errase_done;
end else begin
garbage_en <= 1'b0;
NS <= errase_start;
end
end
errase_done: begin
if (garbage_state == 1'b1) begin
NS <= errase_done;
end else begin
NS <= cmp_ratio;
end
end
default: begin
NS <= cmp_ratio;
end
endcase
end
end
always @(posedge clk_50 or negedge rst) begin
if (rst == 1'b0) begin
ratio <= 32'd0;
end else begin
ratio <= e_cnt / f_cnt;
end
end
endmodule
| 6.756887 |
module top (
input clk_i,
input rst_i,
output halt
);
if_wb rambus ();
if_wb cpubus ();
bexkat1p cpu0 (
.clk_i(clk_i),
.rst_i(rst_i),
.bus(cpubus.master),
.halt(halt),
.inter(inter),
.exception(exception),
.supervisor(supervisor),
.int_en(int_en)
);
ram ram0 (
.clk_i(clk_i),
.rst_i(rst_i),
.bus (rambus.slave)
);
endmodule
| 7.233807 |
module bextdep64g3 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(1),
.XLEN(64),
.FFS (3)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.501649 |
module bextdep64p3 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(0),
.XLEN(64),
.FFS (3)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.449698 |
module bextdep64g2 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(1),
.XLEN(64),
.FFS (2)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.189357 |
module bextdep64p2 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(0),
.XLEN(64),
.FFS (2)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.21886 |
module bextdep64g1 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(1),
.XLEN(64),
.FFS (1)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.029467 |
module bextdep64p1 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(0),
.XLEN(64),
.FFS (1)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.068791 |
module bextdep32g3 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(1),
.XLEN(32),
.FFS (3)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.234018 |
module bextdep32p3 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(0),
.XLEN(32),
.FFS (3)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.195055 |
module bextdep32g2 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(1),
.XLEN(32),
.FFS (2)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 6.84396 |
module bextdep32p2 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(0),
.XLEN(32),
.FFS (2)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 6.895214 |
module bextdep32g1 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(1),
.XLEN(32),
.FFS (1)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 6.703706 |
module bextdep32p1 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
.GREV(0),
.XLEN(32),
.FFS (1)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 6.850681 |
module bextdep64sh (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_seq #(
.XLEN (64),
.STEPS(4)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.102412 |
module bextdep64sb (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_seq #(
.XLEN (64),
.STEPS(8)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.812095 |
module bextdep64sn (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_seq #(
.XLEN (64),
.STEPS(16)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.434055 |
module bextdep32sb (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_seq #(
.XLEN (32),
.STEPS(4)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.488141 |
module bextdep32sn (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_seq #(
.XLEN (32),
.STEPS(8)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.266771 |
module bextdep_xlen_seq #(
parameter integer XLEN = 32,
parameter integer STEPS = 2
) (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [XLEN-1:0] din_value,
input [XLEN-1:0] din_mask,
output dout_valid,
input dout_ready,
output [XLEN-1:0] dout_result
);
localparam integer SUMBITS =
XLEN/STEPS == 32 ? 6 :
XLEN/STEPS == 16 ? 5 :
XLEN/STEPS == 8 ? 4 :
XLEN/STEPS == 4 ? 3 : 'bx;
localparam integer STEPBITS =
STEPS == 16 ? 5 :
STEPS == 8 ? 4 :
STEPS == 4 ? 3 :
STEPS == 2 ? 2 : 'bx;
reg running;
reg mode_bdep;
reg [STEPBITS-1:0] stepcnt;
reg [XLEN-1:0] buffer_a;
reg [XLEN-1:0] buffer_b;
reg [XLEN-1:0] buffer_c;
wire [XLEN/STEPS-1:0] direct_value;
wire [XLEN/STEPS-1:0] direct_mask;
wire [XLEN/STEPS-1:0] direct_result;
wire [SUMBITS-1:0] direct_sum;
function [XLEN-1:0] xlen_reverse;
input [XLEN-1:0] v;
integer i;
begin
for (i = 0; i < XLEN; i = i + 1) xlen_reverse[i] = v[XLEN-i-1];
end
endfunction
function [XLEN/STEPS-1:0] step_reverse;
input [XLEN/STEPS-1:0] v;
integer i;
begin
for (i = 0; i < XLEN / STEPS; i = i + 1) step_reverse[i] = v[XLEN/STEPS-i-1];
end
endfunction
assign direct_value = mode_bdep ? step_reverse(
buffer_c[XLEN-1-:XLEN/STEPS]
) : buffer_a[XLEN-1-:XLEN/STEPS];
assign direct_mask = mode_bdep ? step_reverse(
buffer_b[XLEN-1-:XLEN/STEPS]
) : buffer_b[XLEN-1-:XLEN/STEPS];
bextdep_direct #(
.XLEN(XLEN / STEPS),
.SUMBITS(SUMBITS)
) direct (
.din_mode (mode_bdep),
.din_value (direct_value),
.din_mask (direct_mask),
.dout_result(direct_result),
.dout_sum (direct_sum)
);
always @(posedge clock) begin
stepcnt <= stepcnt - |stepcnt;
if (dout_valid && dout_ready) begin
running <= 0;
end
if (reset) begin
running <= 0;
end else if (din_valid && din_ready) begin
running <= 1;
stepcnt <= STEPS;
mode_bdep <= din_mode[0];
if (din_mode[0]) begin
buffer_b <= xlen_reverse(din_mask);
buffer_c <= xlen_reverse(din_value);
end else begin
buffer_a <= din_value;
buffer_b <= din_mask;
buffer_c <= 0;
end
end else if (stepcnt) begin
buffer_a <= {buffer_a, step_reverse(direct_result)};
buffer_b <= buffer_b << (XLEN / STEPS);
buffer_c <= (buffer_c << direct_sum) | direct_result;
end
end
assign din_ready = !running || (dout_valid && dout_ready);
assign dout_valid = running && !stepcnt;
assign dout_result = mode_bdep ? xlen_reverse(buffer_a) : buffer_c;
endmodule
| 7.252398 |
module bextdep_direct #(
parameter integer XLEN = 32,
parameter integer SUMBITS = 8
) (
input din_mode,
input [ XLEN-1:0] din_value,
input [ XLEN-1:0] din_mask,
output [ XLEN-1:0] dout_result,
output [SUMBITS-1:0] dout_sum
);
wire [XLEN/2-1:0] decoder_s1, decoder_s2, decoder_s4;
wire [XLEN/2-1:0] decoder_s8, decoder_s16, decoder_s32;
wire [7:0] decoder_sum;
bextdep_decoder #(
.XLEN(XLEN),
.FFSTAGE(0)
) decoder (
.mask(din_mask),
.s1 (decoder_s1),
.s2 (decoder_s2),
.s4 (decoder_s4),
.s8 (decoder_s8),
.s16 (decoder_s16),
.s32 (decoder_s32),
.sum (decoder_sum)
);
wire [XLEN-1:0] result_fwd;
wire [XLEN-1:0] result_bwd;
bextdep_butterfly_fwd #(
.XLEN(XLEN)
) butterfly_fwd (
.din (din_value),
.s1 (~decoder_s1),
.s2 (~decoder_s2),
.s4 (~decoder_s4),
.s8 (~decoder_s8),
.s16 (~decoder_s16),
.s32 (~decoder_s32),
.dout(result_fwd)
);
bextdep_butterfly_bwd #(
.XLEN(XLEN)
) butterfly_bwd (
.din (din_value & din_mask),
.s1 (~decoder_s1),
.s2 (~decoder_s2),
.s4 (~decoder_s4),
.s8 (~decoder_s8),
.s16 (~decoder_s16),
.s32 (~decoder_s32),
.dout(result_bwd)
);
assign dout_result = din_mode ? (result_fwd & din_mask) : result_bwd;
assign dout_sum = decoder_sum;
endmodule
| 6.960414 |
module bextdep64sx (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_sx #(
.XLEN(64)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.659199 |
module bextdep32sx (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_sx #(
.XLEN(32)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 7.51903 |
module bextdep_xlen_sx #(
parameter integer XLEN = 32
) (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [XLEN-1:0] din_value,
input [XLEN-1:0] din_mask,
output dout_valid,
input dout_ready,
output [XLEN-1:0] dout_result
);
reg bdep, running, ready;
reg [XLEN-1:0] c, m, msk, val;
wire [XLEN-1:0] b = msk & -msk;
assign din_ready = !running || (dout_valid && dout_ready);
assign dout_valid = running && ready;
assign dout_result = c;
always @(posedge clock) begin
if (dout_valid && dout_ready) begin
running <= 0;
ready <= 0;
end
if (reset) begin
running <= 0;
ready <= 0;
end else if (din_valid && din_ready) begin
c <= 0;
m <= 1;
running <= 1;
ready <= 0;
bdep <= din_mode[0];
val <= din_value;
msk <= din_mask;
end else if (running && !ready) begin
if (val & (bdep ? m : b)) c <= c | (bdep ? b : m);
msk <= msk & ~b;
ready <= !(msk & ~b);
m <= m << 1;
end
end
endmodule
| 7.252398 |
module bextdep64go (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_go #(
.XLEN(64),
.MAXK(6),
.MAXI(32)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 6.886903 |
module bextdep32go (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_go #(
.XLEN(32),
.MAXK(5),
.MAXI(16)
) core (
.clock (clock),
.reset (reset),
.din_valid (din_valid),
.din_ready (din_ready),
.din_mode (din_mode),
.din_value (din_value),
.din_mask (din_mask),
.dout_valid (dout_valid),
.dout_ready (dout_ready),
.dout_result(dout_result)
);
endmodule
| 6.727231 |
module bextdep_xlen_go #(
parameter integer XLEN = 32,
parameter integer MAXK = 5,
parameter integer MAXI = 16
) (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [XLEN-1:0] din_value,
input [XLEN-1:0] din_mask,
output reg dout_valid,
input dout_ready,
output reg [XLEN-1:0] dout_result
);
reg [XLEN-1:0] butterfly;
integer k, i;
always @* begin
butterfly = din_value;
for (k = 0; k < MAXK; k = k + 1)
for (i = 0; i < MAXI; i = i + 1)
if (din_mask[k])
{butterfly[
`bextdep_butterfly_idx_a(k, i)
], butterfly[
`bextdep_butterfly_idx_b(k, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(k, i)], butterfly[`bextdep_butterfly_idx_a(k, i)]
};
end
assign din_ready = !reset && !(dout_valid && !dout_ready);
always @(posedge clock) begin
if (reset) begin
dout_valid <= 0;
end else if (din_valid && din_ready) begin
dout_valid <= din_valid;
dout_result <= butterfly;
end else if (dout_ready) begin
dout_valid <= 0;
end
end
endmodule
| 7.252398 |
module bextdep_lrotcz #(
parameter integer N = 1,
parameter integer M = 1
) (
input [ 7:0] din,
output [M-1:0] dout
);
wire [2*M-1:0] mask = {M{1'b1}};
assign dout = (mask << din[N-1:0]) >> M;
endmodule
| 7.126218 |
module bextdep_butterfly_fwd #(
parameter integer XLEN = 32,
parameter integer FFSTAGE = 1
) (
input [ XLEN-1:0] din,
input [XLEN/2-1:0] s1,
s2,
s4,
s8,
s16,
s32,
output [ XLEN-1:0] dout
);
reg [XLEN-1:0] butterfly;
assign dout = butterfly;
integer k, i;
always @* begin
butterfly = din;
if (64 <= XLEN) begin
for (i = 0; i < XLEN / 2; i = i + 1)
if (s32[i])
{butterfly[
`bextdep_butterfly_idx_a(5, i)
], butterfly[
`bextdep_butterfly_idx_b(5, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(5, i)], butterfly[`bextdep_butterfly_idx_a(5, i)]
};
end
if (32 <= XLEN) begin
for (i = 0; i < XLEN / 2; i = i + 1)
if (s16[i])
{butterfly[
`bextdep_butterfly_idx_a(4, i)
], butterfly[
`bextdep_butterfly_idx_b(4, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(4, i)], butterfly[`bextdep_butterfly_idx_a(4, i)]
};
end
if (16 <= XLEN) begin
for (i = 0; i < XLEN / 2; i = i + 1)
if (s8[i])
{butterfly[
`bextdep_butterfly_idx_a(3, i)
], butterfly[
`bextdep_butterfly_idx_b(3, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(3, i)], butterfly[`bextdep_butterfly_idx_a(3, i)]
};
end
for (i = 0; i < XLEN / 2; i = i + 1)
if (s4[i])
{butterfly[
`bextdep_butterfly_idx_a(2, i)
], butterfly[
`bextdep_butterfly_idx_b(2, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(2, i)], butterfly[`bextdep_butterfly_idx_a(2, i)]
};
for (i = 0; i < XLEN / 2; i = i + 1)
if (s2[i])
{butterfly[
`bextdep_butterfly_idx_a(1, i)
], butterfly[
`bextdep_butterfly_idx_b(1, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(1, i)], butterfly[`bextdep_butterfly_idx_a(1, i)]
};
for (i = 0; i < XLEN / 2; i = i + 1)
if (s1[i])
{butterfly[
`bextdep_butterfly_idx_a(0, i)
], butterfly[
`bextdep_butterfly_idx_b(0, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(0, i)], butterfly[`bextdep_butterfly_idx_a(0, i)]
};
end
endmodule
| 7.237255 |
module bextdep_butterfly_bwd #(
parameter integer XLEN = 32,
parameter integer FFSTAGE = 1
) (
input [ XLEN-1:0] din,
input [XLEN/2-1:0] s1,
s2,
s4,
s8,
s16,
s32,
output [ XLEN-1:0] dout
);
reg [XLEN-1:0] butterfly;
assign dout = butterfly;
integer k, i;
always @* begin
butterfly = din;
for (i = 0; i < XLEN / 2; i = i + 1)
if (s1[i])
{butterfly[
`bextdep_butterfly_idx_a(0, i)
], butterfly[
`bextdep_butterfly_idx_b(0, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(0, i)], butterfly[`bextdep_butterfly_idx_a(0, i)]
};
for (i = 0; i < XLEN / 2; i = i + 1)
if (s2[i])
{butterfly[
`bextdep_butterfly_idx_a(1, i)
], butterfly[
`bextdep_butterfly_idx_b(1, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(1, i)], butterfly[`bextdep_butterfly_idx_a(1, i)]
};
for (i = 0; i < XLEN / 2; i = i + 1)
if (s4[i])
{butterfly[
`bextdep_butterfly_idx_a(2, i)
], butterfly[
`bextdep_butterfly_idx_b(2, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(2, i)], butterfly[`bextdep_butterfly_idx_a(2, i)]
};
if (16 <= XLEN) begin
for (i = 0; i < XLEN / 2; i = i + 1)
if (s8[i])
{butterfly[
`bextdep_butterfly_idx_a(3, i)
], butterfly[
`bextdep_butterfly_idx_b(3, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(3, i)], butterfly[`bextdep_butterfly_idx_a(3, i)]
};
end
if (32 <= XLEN) begin
for (i = 0; i < XLEN / 2; i = i + 1)
if (s16[i])
{butterfly[
`bextdep_butterfly_idx_a(4, i)
], butterfly[
`bextdep_butterfly_idx_b(4, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(4, i)], butterfly[`bextdep_butterfly_idx_a(4, i)]
};
end
if (64 <= XLEN) begin
for (i = 0; i < XLEN / 2; i = i + 1)
if (s32[i])
{butterfly[
`bextdep_butterfly_idx_a(5, i)
], butterfly[
`bextdep_butterfly_idx_b(5, i)
]} = {
butterfly[`bextdep_butterfly_idx_b(5, i)], butterfly[`bextdep_butterfly_idx_a(5, i)]
};
end
end
endmodule
| 7.237255 |
module bextdep_pps4 (
input [ 3:0] din,
output [31:0] dout
);
function [15:0] carry_save_add;
input [15:0] a, b;
reg [7:0] x, y;
begin
x = a[15:8] ^ a[7:0] ^ b[7:0];
y = ((a[15:8] & a[7:0]) | (a[15:8] & b[7:0]) | (a[7:0] & b[7:0])) << 1;
carry_save_add[7:0] = x ^ y ^ b[15:8];
carry_save_add[15:8] = ((x & y) | (x & b[15:8]) | (y & b[15:8])) << 1;
end
endfunction
function [7:0] carry_save_get;
input [15:0] a;
begin
carry_save_get = a[7:0] + a[15:8];
end
endfunction
// inputs
wire [15:0] e0s0 = {15'b0, din[0+:1]};
wire [15:0] e1s0 = {15'b0, din[1+:1]};
wire [15:0] e2s0 = {15'b0, din[2+:1]};
wire [15:0] e3s0 = {15'b0, din[3+:1]};
// forward pass
wire [15:0] e1s1 = carry_save_add(e1s0, e0s0);
wire [15:0] e3s1 = carry_save_add(e3s0, e2s0);
wire [15:0] e3s2 = carry_save_add(e3s1, e1s1);
// backward pass
wire [15:0] e2s3 = carry_save_add(e2s0, e1s1);
// outputs
assign dout[0+:8] = carry_save_get(e0s0);
assign dout[8+:8] = carry_save_get(e1s1);
assign dout[16+:8] = carry_save_get(e2s3);
assign dout[24+:8] = carry_save_get(e3s2);
endmodule
| 6.852607 |
module bextdep_pps8 (
input [ 7:0] din,
output [63:0] dout
);
function [15:0] carry_save_add;
input [15:0] a, b;
reg [7:0] x, y;
begin
x = a[15:8] ^ a[7:0] ^ b[7:0];
y = ((a[15:8] & a[7:0]) | (a[15:8] & b[7:0]) | (a[7:0] & b[7:0])) << 1;
carry_save_add[7:0] = x ^ y ^ b[15:8];
carry_save_add[15:8] = ((x & y) | (x & b[15:8]) | (y & b[15:8])) << 1;
end
endfunction
function [7:0] carry_save_get;
input [15:0] a;
begin
carry_save_get = a[7:0] + a[15:8];
end
endfunction
// inputs
wire [15:0] e0s0 = {15'b0, din[0+:1]};
wire [15:0] e1s0 = {15'b0, din[1+:1]};
wire [15:0] e2s0 = {15'b0, din[2+:1]};
wire [15:0] e3s0 = {15'b0, din[3+:1]};
wire [15:0] e4s0 = {15'b0, din[4+:1]};
wire [15:0] e5s0 = {15'b0, din[5+:1]};
wire [15:0] e6s0 = {15'b0, din[6+:1]};
wire [15:0] e7s0 = {15'b0, din[7+:1]};
// forward pass
wire [15:0] e1s1 = carry_save_add(e1s0, e0s0);
wire [15:0] e3s1 = carry_save_add(e3s0, e2s0);
wire [15:0] e5s1 = carry_save_add(e5s0, e4s0);
wire [15:0] e7s1 = carry_save_add(e7s0, e6s0);
wire [15:0] e3s2 = carry_save_add(e3s1, e1s1);
wire [15:0] e7s2 = carry_save_add(e7s1, e5s1);
wire [15:0] e7s3 = carry_save_add(e7s2, e3s2);
// backward pass
wire [15:0] e5s4 = carry_save_add(e5s1, e3s2);
wire [15:0] e2s5 = carry_save_add(e2s0, e1s1);
wire [15:0] e4s5 = carry_save_add(e4s0, e3s2);
wire [15:0] e6s5 = carry_save_add(e6s0, e5s4);
// outputs
assign dout[0+:8] = carry_save_get(e0s0);
assign dout[8+:8] = carry_save_get(e1s1);
assign dout[16+:8] = carry_save_get(e2s5);
assign dout[24+:8] = carry_save_get(e3s2);
assign dout[32+:8] = carry_save_get(e4s5);
assign dout[40+:8] = carry_save_get(e5s4);
assign dout[48+:8] = carry_save_get(e6s5);
assign dout[56+:8] = carry_save_get(e7s3);
endmodule
| 6.822596 |
module BF (
input a,
input b,
input c,
output out1,
output out2,
output out3,
output out4
);
assign out1 = ((~a) || (~b)) && (~c);
assign out2 = ~((a && b) || c);
assign out3 = ((~a) && (~b)) || (~c);
assign out4 = ~((a || b) && c);
endmodule
| 7.246855 |
module bf1 #(
parameter WIDTH = 17
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WIDTH-1:0] data_out_1_im
);
wire [WIDTH:0] re_0_w;
wire [WIDTH:0] im_0_w;
wire [WIDTH:0] re_1_w;
wire [WIDTH:0] im_1_w;
assign re_0_w = ({data_in_0_re[WIDTH-1], data_in_0_re} + {data_in_1_re[WIDTH-1], data_in_1_re});
assign data_out_0_re = {re_0_w[WIDTH], re_0_w[WIDTH-2:0]};
assign im_0_w = ({data_in_0_im[WIDTH-1], data_in_0_im} + {data_in_1_im[WIDTH-1], data_in_1_im});
assign data_out_0_im = {im_0_w[WIDTH], im_0_w[WIDTH-2:0]};
assign re_1_w = ({data_in_0_re[WIDTH-1], data_in_0_re} - {data_in_1_re[WIDTH-1], data_in_1_re});
assign data_out_1_re = {re_1_w[WIDTH], re_1_w[WIDTH-2:0]};
assign im_1_w = ({data_in_0_im[WIDTH-1], data_in_0_im} - {data_in_1_im[WIDTH-1], data_in_1_im});
assign data_out_1_im = {im_1_w[WIDTH], im_1_w[WIDTH-2:0]};
endmodule
| 7.073333 |
module bf16 #(
parameter WIDTH = 13
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WIDTH-1:0] data_out_1_im
);
assign data_out_0_re = data_in_0_re + data_in_1_re;
assign data_out_0_im = data_in_0_im + data_in_1_im;
assign data_out_1_re = data_in_0_re - data_in_1_re;
assign data_out_1_im = data_in_0_im - data_in_1_im;
endmodule
| 8.21675 |
module bf2 #(
parameter WIDTH = 17
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WIDTH-1:0] data_out_1_im
);
wire [WIDTH:0] re_0_w;
wire [WIDTH:0] im_0_w;
wire [WIDTH:0] re_1_w;
wire [WIDTH:0] im_1_w;
assign re_0_w = ({data_in_0_re[WIDTH-1], data_in_0_re} + {data_in_1_re[WIDTH-1], data_in_1_re});
assign data_out_0_re = {re_0_w[WIDTH], re_0_w[WIDTH-2:0]};
assign im_0_w = ({data_in_0_im[WIDTH-1], data_in_0_im} + {data_in_1_im[WIDTH-1], data_in_1_im});
assign data_out_0_im = {im_0_w[WIDTH], im_0_w[WIDTH-2:0]};
assign re_1_w = ({data_in_0_re[WIDTH-1], data_in_0_re} - {data_in_1_re[WIDTH-1], data_in_1_re});
assign data_out_1_re = {re_1_w[WIDTH], re_1_w[WIDTH-2:0]};
assign im_1_w = ({data_in_0_im[WIDTH-1], data_in_0_im} - {data_in_1_im[WIDTH-1], data_in_1_im});
assign data_out_1_im = {im_1_w[WIDTH], im_1_w[WIDTH-2:0]};
endmodule
| 7.01775 |
module tb ();
reg clk;
reg serial_in;
wire serial_out;
initial begin
$dumpfile("bf2hw.vcd");
$dumpvars;
clk <= 1'b0;
serial_in <= 1'b1;
#1000;
serial_in <= 1'b0;
#1041666;
serial_in <= 1'b1;
#15000000;
$finish;
end
always #20.67 clk = !clk;
bf2hw_top dut (
clk,
serial_in,
serial_out
);
endmodule
| 7.195167 |
module instantiating BAMBU generated hardware
//
module bf2hw_top(input clk12, input SERIAL_RX, output SERIAL_TX);
`define D_BAUD_FREQ 12'd4
`define D_BAUD_LIMIT 16'd621
wire TX_BUSY;
wire TX_WRITE;
wire RX_VALID;
wire [7:0] RX_DATA;
wire [7:0] TX_DATA;
wire TX_READY;
wire clock; // 24 MHz clock generated by the PLL
wire locked;
wire reset;
reg [2:0] reset_sync;
assign TX_READY = ~TX_BUSY;
pll the_pll (.clock_in(clk12), .clock_out(clock), .locked(locked));
assign reset = reset_sync[2];
initial begin
reset_sync <= 3'b11;
end
always @(posedge clock or negedge locked) begin
if (locked == 1'b0) begin
reset_sync <= 3'b11;
end else begin
reset_sync <= {reset_sync[1:0],1'b0};
end
end
uart_top uart (.clock(clock), .reset(reset),.ser_in(SERIAL_RX), .ser_out(SERIAL_TX),
.rx_data(RX_DATA), .new_rx_data(RX_VALID),
.tx_data(TX_DATA), .new_tx_data(TX_WRITE), .tx_busy(TX_BUSY),
.baud_freq(`D_BAUD_FREQ), .baud_limit(`D_BAUD_LIMIT),
.baud_clk()
);
main_minimal_interface main(.clock(clock), .reset(reset),
.start_port(1'b1), .RX_VALID(RX_VALID), .RX_DATA(RX_DATA),
.TX_READY(TX_READY), .done_port(), .return_port(),
.TX_ENABLE(TX_WRITE), .TX_DATA(TX_DATA));
endmodule
| 7.016079 |
module bf32 #(
parameter WIDTH = 11
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WIDTH-1:0] data_out_1_im
);
assign data_out_0_re = data_in_0_re + data_in_1_re;
assign data_out_0_im = data_in_0_im + data_in_1_im;
assign data_out_1_re = data_in_0_re - data_in_1_re;
assign data_out_1_im = data_in_0_im - data_in_1_im;
endmodule
| 7.547757 |
module bf4 #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WIDTH-1:0] data_out_1_im
);
wire [WIDTH:0] re_0_w;
wire [WIDTH:0] im_0_w;
wire [WIDTH:0] re_1_w;
wire [WIDTH:0] im_1_w;
assign re_0_w = ({data_in_0_re[WIDTH-1], data_in_0_re} + {data_in_1_re[WIDTH-1], data_in_1_re});
assign data_out_0_re = {re_0_w[WIDTH], re_0_w[WIDTH-2:0]};
assign im_0_w = ({data_in_0_im[WIDTH-1], data_in_0_im} + {data_in_1_im[WIDTH-1], data_in_1_im});
assign data_out_0_im = {im_0_w[WIDTH], im_0_w[WIDTH-2:0]};
assign re_1_w = ({data_in_0_re[WIDTH-1], data_in_0_re} - {data_in_1_re[WIDTH-1], data_in_1_re});
assign data_out_1_re = {re_1_w[WIDTH], re_1_w[WIDTH-2:0]};
assign im_1_w = ({data_in_0_im[WIDTH-1], data_in_0_im} - {data_in_1_im[WIDTH-1], data_in_1_im});
assign data_out_1_im = {im_1_w[WIDTH], im_1_w[WIDTH-2:0]};
endmodule
| 7.770008 |
module bf8 #(
parameter WIDTH = 14
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WIDTH-1:0] data_out_1_im
);
assign data_out_0_re = data_in_0_re + data_in_1_re;
assign data_out_0_im = data_in_0_im + data_in_1_im;
assign data_out_1_re = data_in_0_re - data_in_1_re;
assign data_out_1_im = data_in_0_im - data_in_1_im;
endmodule
| 8.680949 |
module BFA (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
assign cout = (a && b) || (b && cin) || (a && cin);
assign sum = a ^ b ^ cin;
endmodule
| 7.572097 |
module bfloat_adder_8 (
input clk,
input resetn,
input en,
input stall,
input [8-1:0] a,
input [8-1:0] b,
output reg [8-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en) out <= a + b;
end
endmodule
| 6.882044 |
module bfloat_mult_8 (
input clk,
input resetn,
input en,
input stall,
input [8-1:0] a,
input [8-1:0] b,
output reg [8-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en) out <= a * b;
end
endmodule
| 7.144967 |
module bfm ();
bit clk;
always #4 clk = ~clk;
import "DPI-C" context function void init();
export "DPI-C" function set_data;
import "DPI-C" context function void get_data();
export "DPI-C" function finalize;
import "DPI-C" context function void kill();
bit input_valid;
bit ready;
bit final_en;
initial begin
final_en = 0;
ready = 0;
input_valid = 0;
init();
@(posedge final_en) kill();
$finish;
end
always @(posedge clk) begin
if (input_valid == 1) begin
get_data();
input_valid = 0;
end
end
function set_data();
begin
$display("set_data()");
input_valid = 1;
end
endfunction
function finalize();
begin
//$display("finalize");
final_en = 1;
end
endfunction
endmodule
| 7.232006 |
module BFM_AHBSLAVE (
HCLK,
HRESETN,
HSEL,
HWRITE,
HADDR,
HWDATA,
HRDATA,
HREADYIN,
HREADYOUT,
HTRANS,
HSIZE,
HBURST,
HMASTLOCK,
HPROT,
HRESP
);
parameter AWIDTH = 10;
parameter DEPTH = 256;
parameter INITFILE = " ";
parameter ID = 0;
parameter ENFUNC = 0;
parameter TPD = 1;
parameter DEBUG = -1;
localparam ENFIFO = 0;
localparam EXT_SIZE = 2;
input HCLK;
input HRESETN;
input HSEL;
input HWRITE;
input [AWIDTH
-
1 : 0] HADDR;
input [31 : 0] HWDATA;
output [31 : 0] HRDATA;
input HREADYIN;
output HREADYOUT;
input [1 : 0] HTRANS;
input [2 : 0] HSIZE;
input [2 : 0] HBURST;
input HMASTLOCK;
input [3 : 0] HPROT;
output HRESP;
wire EXT_EN;
wire EXT_WR;
wire EXT_RD;
wire [AWIDTH
-
1 : 0] EXT_ADDR;
wire [31 : 0] EXT_DATA;
assign EXT_EN = 1'b0;
assign EXT_WR = 1'b0;
assign EXT_RD = 1'b0;
assign EXT_ADDR = 0;
assign EXT_DATA = {32{1'bz}};
BFM_AHBSLAVEEXT #(
.AWIDTH(AWIDTH),
.DEPTH(DEPTH),
.EXT_SIZE(EXT_SIZE),
.INITFILE(INITFILE),
.ID(ID),
.ENFUNC(ENFUNC),
.ENFIFO(ENFIFO),
.TPD(TPD),
.DEBUG(DEBUG)
) BFMA1OI1II (
.HCLK(HCLK),
.HRESETN(HRESETN),
.HSEL(HSEL),
.HWRITE(HWRITE),
.HADDR(HADDR),
.HWDATA(HWDATA),
.HRDATA(HRDATA),
.HREADYIN(HREADYIN),
.HREADYOUT(HREADYOUT),
.HTRANS(HTRANS),
.HSIZE(HSIZE),
.HBURST(HBURST),
.HMASTLOCK(HMASTLOCK),
.HPROT(HPROT),
.HRESP(HRESP),
.TXREADY(BFMA1II1II),
.RXREADY(BFMA1II1II),
.EXT_EN(EXT_EN),
.EXT_WR(EXT_WR),
.EXT_RD(EXT_RD),
.EXT_ADDR(EXT_ADDR),
.EXT_DATA(EXT_DATA)
);
endmodule
| 6.859666 |
module bfm_ahb (
input wire SYS_CLK_STABLE
, input wire SYS_CLK // master clock and goes to SL_PCLK
, output wire SYS_RST_N // by-pass of SL_RST_N
, input wire SL_RST_N
, output wire SL_CS_N
, output wire SL_PCLK // by-pass of SYS_CLK after phase shift
, output wire [ 1:0] SL_AD
, input wire SL_FLAGA // active-low empty (U2F)
, input wire SL_FLAGB // active-low almost-empty
, input wire SL_FLAGC // active-low full (F2U)
, input wire SL_FLAGD // active-low almost-full
, output wire SL_RD_N
, output wire SL_WR_N
, output wire SL_OE_N // when low, let FX3 drive data through SL_DT_I
, output wire SL_PKTEND_N
, input wire [31:0] SL_DT_I
, output wire [31:0] SL_DT_O
, output wire SL_DT_T
, input wire [ 1:0] SL_MODE
//-------------------------------------------------------------------------
, input wire HRESETn
, input wire HCLK
, output wire HBUSREQ
, input wire HGRANT
, output wire [31:0] HADDR
, output wire [ 3:0] HPROT
, output wire [ 1:0] HTRANS
, output wire HLOCK
, output wire HWRITE
, output wire [ 2:0] HSIZE
, output wire [ 2:0] HBURST
, output wire [31:0] HWDATA // non-justified data
, input wire [31:0] HRDATA // non-justified data
, input wire [ 1:0] HRESP
, input wire HREADY
, input wire IRQ // active-high interrupt
, input wire FIQ // active-high fast interrupt
, output wire [15:0] GPOUT
, input wire [15:0] GPIN
);
// synthesis attribute box_type bfm_ahb "black_box"
endmodule
| 7.135272 |
module bfm_apb_s1 #(
parameter P_ADDR_START0 = 16'h0000,
P_ADDR_SIZE0 = 16'h0010
) (
input wire PRESETn
, input wire PCLK
, output reg PSEL
, output reg [31:0] PADDR
, output reg PENABLE
, output reg PWRITE
, output reg [31:0] PWDATA
, input wire [31:0] PRDATA0
);
//----------------------------------------------------
`ifndef AMBA3
wire PREADY = 1'b1;
wire PSLVERR = 1'b0;
`endif
`ifndef AMBA4
reg [2:0] PPROT;
reg [3:0] PSTRB;
`endif
//----------------------------------------------------
reg [31:0] freq;
real stamp_x, stamp_y, delta;
initial begin
PSEL = 1'b0;
PADDR = ~32'h0;
PENABLE = 1'b0;
PWRITE = 1'b0;
PWDATA = ~32'h0;
PPROT = 3'h0;
PSTRB = 4'h0;
wait (PRESETn == 1'b0);
wait (PRESETn == 1'b1);
@(posedge PCLK);
@(posedge PCLK);
stamp_x = $time;
@(posedge PCLK);
stamp_y = $time;
delta = stamp_y - stamp_x;
@(negedge PCLK);
$display("%m PCLK %f nsec %f Mhz", delta, 1000.0 / delta);
freq = 1000000000 / delta;
repeat (3) @(posedge PCLK);
uart_test(freq, 115200);
repeat (5) @(posedge PCLK);
$finish(2);
end
//----------------------------------------------------
integer err;
//----------------------------------------------------
task uart_test;
input [31:0] freq;
input [31:0] baud;
reg [7:0] dat;
integer idx;
begin
err = 0;
//------------------------------------------------
init_uart(freq // input [31:0] frea;
, baud // input [31:0] baud
);
//------------------------------------------------
for (idx = "A"; idx <= "Z"; idx = idx + 1) begin
send_a_character(idx[7:0]);
receive_a_character(dat);
if (dat >= 8'h20 && dat <= 8'h7E) $display($time,, "%m 0x%x(%c) received!", dat, dat);
else $display($time,, "%m 0x%x received!", dat);
if (idx[7:0] !== dat) begin
err = err + 1;
$display($time,, "%m ERROR 0x%x received, but 0x%x expected", dat, idx[7:0]);
end
end
//------------------------------------------------
if (err == 0) $display($time,, "%m test OK");
end
endtask
//----------------------------------------------------
`include "bfm_apb_tasks_s1.v"
`include "uart_apb_tasks.v"
//----------------------------------------------------
endmodule
| 7.029573 |
module bfm_apb_s3
#(parameter P_DWIDTH=32
, P_STRB =(P_DWIDTH/8)
, P_NUM=3
, P_ADDR_START0 = 16'h0000, P_ADDR_SIZE0 = 16'h0010
, P_ADDR_START1 = 16'h1000, P_ADDR_SIZE1 = 16'h0010
, P_ADDR_START2 = 16'h2000, P_ADDR_SIZE2 = 16'h0010)
(
input wire PRESETn
, input wire PCLK
, output reg [P_NUM-1:0] PSEL
, output reg [31:0] PADDR
, output reg PENABLE
, output reg PWRITE
, output reg [P_DWIDTH-1:0] PWDATA
, input wire [P_DWIDTH-1:0] PRDATA0
, input wire [P_DWIDTH-1:0] PRDATA1
, input wire [P_DWIDTH-1:0] PRDATA2
`ifdef AMBA3
, input wire [P_NUM-1:0] PREADY
, input wire [P_NUM-1:0] PSLVERR
`endif
`ifdef AMBA4
, output reg [ 2:0] PPROT
, output reg [P_STRB-1:0] PSTRB
`endif
);
//----------------------------------------------------
`ifndef AMBA3
wire [P_NUM-1:0] PREADY = {P_NUM{1'b1}};
wire [P_NUM-1:0] PSLVERR = {P_NUM{1'b0}};
`endif
`ifndef AMBA4
reg [ 2:0] PPROT;
reg [P_STRB-1:0] PSTRB;
`endif
//----------------------------------------------------
initial begin
PSEL = {P_NUM{1'b0}};
PADDR = ~32'h0;
PENABLE = 1'b0;
PWRITE = 1'b0;
PWDATA = {P_DWIDTH{1'b1}};
PPROT = 3'h0;
PSTRB = {P_STRB{1'b0}};
wait (PRESETn==1'b0);
wait (PRESETn==1'b1);
repeat (3) @ (posedge PCLK);
memory_test({P_ADDR_START0,16'h0}, {P_ADDR_START0,16'h0}+32'h10-1, 4);
memory_test({P_ADDR_START1,16'h0}, {P_ADDR_START1,16'h0}+32'h10-1, 4);
memory_test({P_ADDR_START2,16'h0}, {P_ADDR_START2,16'h0}+32'h10-1, 4);
repeat (5) @ (posedge PCLK);
$finish(2);
end
//----------------------------------------------------
reg [P_DWIDTH-1:0] reposit[0:1023];
//----------------------------------------------------
task memory_test;
input [31:0] start ; // starting address
input [31:0] finish; // ending address, inclusive
input [ 2:0] size ; // num of byte to access
reg [P_DWIDTH-1:0] dataW, dataR;
integer a, b, err;
begin
err = 0;
//------------------------------------------------
// read-after-write test
for (a=start; a<=(finish-size); a=a+size) begin
dataW = $random;
apb_write(a, dataW, size);
apb_read (a, dataR, size);
if (dataR!==dataW) begin
err = err + 1;
$display($time,,"%m RAW error at A:0x%08x D:0x%x, but 0x%x expected",
a, dataR, dataW);
end
end
if (err==0) $display($time,,"%m RAW 0x%x-%x test OK", start, finish);
err = 0;
//------------------------------------------------
// read_all-after-write_all test
for (a=start; a<=(finish-size); a=a+size) begin
b = a - start;
reposit[b] = $random;
apb_write(a, reposit[b], size);
end
for (a=start; a<=(finish-size); a=a+size) begin
b = a - start;
apb_read(a, dataR, size);
if (dataR!==reposit[b]) begin
err = err + 1;
$display($time,,"%m RAAWA error at A:0x%08x D:0x%x, but 0x%x expected",
a, dataR, reposit[b]);
end
end
if (err==0) $display($time,,"%m RAAWA 0x%x-%x test OK", start, finish);
end
endtask
//----------------------------------------------------
`include "bfm_apb_tasks.v"
//----------------------------------------------------
endmodule
| 7.274574 |
module bfm_axi (
input wire SYS_CLK_STABLE
, input wire SYS_CLK // master clock and goes to SL_PCLK
, output wire SYS_RST_N // by-pass of SL_RST_N
, input wire SL_RST_N
, output wire SL_CS_N
, output wire SL_PCLK // by-pass of SYS_CLK after phase shift
, output wire [ 1:0] SL_AD
, input wire SL_FLAGA // active-low empty (U2F)
, input wire SL_FLAGB // active-low almost-empty
, input wire SL_FLAGC // active-low full (F2U)
, input wire SL_FLAGD // active-low almost-full
, output wire SL_RD_N
, output wire SL_WR_N
, output wire SL_OE_N // when low, let FX3 drive data through SL_DT_I
, output wire SL_PKTEND_N
, input wire [31:0] SL_DT_I
, output wire [31:0] SL_DT_O
, output wire SL_DT_T
, input wire [ 1:0] SL_MODE
//-------------------------------------------------------------------------
, input wire ARESETn
, input wire ACLK
, input wire [ 3:0] MID
//-------------------------------------------------------------------------
, output wire [ 3:0] AWID
, output wire [31:0] AWADDR
, output wire [ 7:0] AWLEN
, output wire AWLOCK
, output wire [ 2:0] AWSIZE
, output wire [ 1:0] AWBURST
//`ifdef AMBA_AXI_CACHE
//, output wire [ 3:0] AWCACHE
//`endif
//`ifdef AMBA_AXI_PROT
//, output wire [ 2:0] AWPROT
//`endif
, output wire AWVALID
, input wire AWREADY
, output wire [ 3:0] AWQOS
, output wire [ 3:0] AWREGION
//-------------------------------------------------------------------------
, output wire [ 3:0] WID
, output wire [31:0] WDATA
, output wire [ 3:0] WSTRB
, output wire WLAST
, output wire WVALID
, input wire WREADY
//-------------------------------------------------------------------------
, input wire [ 3:0] BID
, input wire [ 1:0] BRESP
, input wire BVALID
, output wire BREADY
//-------------------------------------------------------------------------
, output wire [ 3:0] ARID
, output wire [31:0] ARADDR
, output wire [ 7:0] ARLEN
, output wire ARLOCK
, output wire [ 2:0] ARSIZE
, output wire [ 1:0] ARBURST
//`ifdef AMBA_AXI_CACHE
//, output wire [ 3:0] ARCACHE
//`endif
//`ifdef AMBA_AXI_PROT
//, output wire [ 2:0] ARPROT
//`endif
, output wire ARVALID
, input wire ARREADY
, output wire [ 3:0] ARQOS
, output wire [ 3:0] ARREGION
//-------------------------------------------------------------------------
, input wire [ 3:0] RID
, input wire [31:0] RDATA
, input wire [ 1:0] RRESP
, input wire RLAST
, input wire RVALID
, output wire RREADY
//-------------------------------------------------------------------------
, input wire IRQ
, input wire FIQ
, output wire [15:0] GPOUT
, input wire [15:0] GPIN
);
// synthesis attribute box_type bfm_axi "black_box"
endmodule
| 6.53215 |
module bfm_axi (
input wire SYS_CLK_STABLE
, input wire SYS_CLK // master clock and goes to SL_PCLK
, output wire SYS_RST_N // by-pass of SL_RST_N
, input wire SL_RST_N
, output wire SL_CS_N
, output wire SL_PCLK // by-pass of SYS_CLK after phase shift
, output wire [ 1:0] SL_AD
, input wire SL_FLAGA // active-low empty (U2F)
, input wire SL_FLAGB // active-low almost-empty
, input wire SL_FLAGC // active-low full (F2U)
, input wire SL_FLAGD // active-low almost-full
, output wire SL_RD_N
, output wire SL_WR_N
, output wire SL_OE_N // when low, let FX3 drive data through SL_DT_I
, output wire SL_PKTEND_N
, input wire [31:0] SL_DT_I
, output wire [31:0] SL_DT_O
, output wire SL_DT_T
, input wire [ 1:0] SL_MODE
//-------------------------------------------------------------------------
, input wire ARESETn
, input wire ACLK
, input wire [ 3:0] MID
//-------------------------------------------------------------------------
, output wire [ 3:0] AWID
, output wire [31:0] AWADDR
, output wire [ 7:0] AWLEN
, output wire AWLOCK
, output wire [ 2:0] AWSIZE
, output wire [ 1:0] AWBURST
//`ifdef AMBA_AXI_CACHE
//, output wire [ 3:0] AWCACHE
//`endif
//`ifdef AMBA_AXI_PROT
//, output wire [ 2:0] AWPROT
//`endif
, output wire AWVALID
, input wire AWREADY
, output wire [ 3:0] AWQOS
, output wire [ 3:0] AWREGION
//-------------------------------------------------------------------------
, output wire [ 3:0] WID
, output wire [31:0] WDATA
, output wire [ 3:0] WSTRB
, output wire WLAST
, output wire WVALID
, input wire WREADY
//-------------------------------------------------------------------------
, input wire [ 3:0] BID
, input wire [ 1:0] BRESP
, input wire BVALID
, output wire BREADY
//-------------------------------------------------------------------------
, output wire [ 3:0] ARID
, output wire [31:0] ARADDR
, output wire [ 7:0] ARLEN
, output wire ARLOCK
, output wire [ 2:0] ARSIZE
, output wire [ 1:0] ARBURST
//`ifdef AMBA_AXI_CACHE
//, output wire [ 3:0] ARCACHE
//`endif
//`ifdef AMBA_AXI_PROT
//, output wire [ 2:0] ARPROT
//`endif
, output wire ARVALID
, input wire ARREADY
, output wire [ 3:0] ARQOS
, output wire [ 3:0] ARREGION
//-------------------------------------------------------------------------
, input wire [ 3:0] RID
, input wire [31:0] RDATA
, input wire [ 1:0] RRESP
, input wire RLAST
, input wire RVALID
, output wire RREADY
//-------------------------------------------------------------------------
, input wire IRQ
, input wire FIQ
, output wire [15:0] GPOUT
, input wire [15:0] GPIN
);
// synthesis attribute box_type bfm_axi "black_box"
endmodule
| 6.53215 |
module adder32 (
clk,
rst,
A,
B,
O
);
input [31:0] A, B;
input clk;
input rst;
output reg [31:0] O;
wire a_sign;
wire b_sign;
wire [7:0] a_exponent;
wire [7:0] b_exponent;
wire [23:0] a_mantissa; // plus one bit
wire [23:0] b_mantissa; // plus one bit
reg o_sign;
reg [7:0] o_exponent;
reg [24:0] o_mantissa; // plus two bits
reg [31:0] adder_a_in;
reg [31:0] adder_b_in;
wire [31:0] adder_out;
assign a_sign = A[31];
assign a_exponent[7:0] = A[30:23];
assign a_mantissa[23:0] = {1'b1, A[22:0]};
assign b_sign = B[31];
assign b_exponent[7:0] = B[30:23];
assign b_mantissa[23:0] = {1'b1, B[22:0]};
generalAdder gAdder (
.a (adder_a_in),
.b (adder_b_in),
.out(adder_out)
);
assign adder_a_in = A;
assign adder_b_in = B;
//covers corner cases and uses general adder logic
always @(posedge clk) begin
if (rst == 1'b1) begin
O = 32'd0;
end else begin
//If a is NaN or b is zero return a
if ((a_exponent == 255 && a_mantissa[22:0] != 0) || (b_exponent == 0) && (b_mantissa[22:0] == 0)) begin
o_sign = a_sign;
o_exponent = a_exponent;
o_mantissa = a_mantissa;
O = {o_sign, o_exponent, o_mantissa[22:0]};
//If b is NaN or a is zero return b
end else if ((b_exponent == 255 && b_mantissa[22:0] != 0) || (a_exponent == 0) && (a_mantissa[22:0] == 0)) begin
o_sign = b_sign;
o_exponent = b_exponent;
o_mantissa = b_mantissa;
O = {o_sign, o_exponent, o_mantissa[22:0]};
//if a and b is inf return inf
end else if ((a_exponent == 255) || (b_exponent == 255)) begin
o_sign = a_sign ^ b_sign;
o_exponent = 255;
o_mantissa = 0;
O = {o_sign, o_exponent, o_mantissa[22:0]};
end else begin // Passed all corner cases
//adder_a_in = A;
//adder_b_in = B;
o_sign = adder_out[31];
o_exponent = adder_out[30:23];
o_mantissa = adder_out[22:0];
O = {o_sign, o_exponent, o_mantissa[22:0]};
end
end
end
endmodule
| 8.194085 |
module generalAdder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
wire [31:0] out;
reg a_sign;
reg b_sign;
reg [7:0] a_exponent;
reg [7:0] b_exponent;
reg [23:0] a_mantissa;
reg [23:0] b_mantissa;
reg o_sign;
reg [7:0] o_exponent;
reg [24:0] o_mantissa;
reg [7:0] diff;
reg [23:0] tmp_mantissa;
reg [7:0] i_e;
reg [24:0] i_m;
wire [7:0] o_e;
wire [24:0] o_m;
addition_normaliser norm1 (
.in_e (i_e),
.in_m (i_m),
.out_e(o_e),
.out_m(o_m)
);
assign out[31] = o_sign;
assign out[30:23] = o_exponent;
assign out[22:0] = o_mantissa[22:0];
always @(*) begin
a_sign = a[31];
if (a[30:23] == 0) begin
a_exponent = 8'b00000001;
a_mantissa = {1'b0, a[22:0]};
end else begin
a_exponent = a[30:23];
a_mantissa = {1'b1, a[22:0]};
end
b_sign = b[31];
if (b[30:23] == 0) begin
b_exponent = 8'b00000001;
b_mantissa = {1'b0, b[22:0]};
end else begin
b_exponent = b[30:23];
b_mantissa = {1'b1, b[22:0]};
end
if (a_exponent == b_exponent) begin // Equal exponents
o_exponent = a_exponent;
if (a_sign == b_sign) begin // Equal signs = add
o_mantissa = a_mantissa + b_mantissa;
//Signify to shift
o_mantissa[24] = 1;
o_sign = a_sign;
end else begin // Opposite signs = subtract
if (a_mantissa > b_mantissa) begin
o_mantissa = a_mantissa - b_mantissa;
o_sign = a_sign;
end else begin
o_mantissa = b_mantissa - a_mantissa;
o_sign = b_sign;
end
end
end else begin //Unequal exponents
if (a_exponent > b_exponent) begin // A is bigger
o_exponent = a_exponent;
o_sign = a_sign;
diff = a_exponent - b_exponent;
tmp_mantissa = b_mantissa >> diff;
if (a_sign == b_sign) o_mantissa = a_mantissa + tmp_mantissa;
else o_mantissa = a_mantissa - tmp_mantissa;
end else if (a_exponent < b_exponent) begin // B is bigger
o_exponent = b_exponent;
o_sign = b_sign;
diff = b_exponent - a_exponent;
tmp_mantissa = a_mantissa >> diff;
if (a_sign == b_sign) o_mantissa = b_mantissa + tmp_mantissa;
else o_mantissa = b_mantissa - tmp_mantissa;
end
end
if (o_mantissa[24] == 1) begin
o_exponent = o_exponent + 1;
o_mantissa = o_mantissa >> 1;
end else if ((o_mantissa[23] != 1) && (o_exponent != 0)) begin
i_e = o_exponent;
i_m = o_mantissa;
o_exponent = o_e;
o_mantissa = o_m;
end
end
endmodule
| 7.143472 |
module bfproc #(
parameter W2 = 17, // Multiplier bit width
W1 = 9, // Bit width c+s sum
W = 8
) // Input bit width
(
input clk, // Clock for the output register
input signed [ W-1:0] Are_in,
Aim_in, // 8-bit inputs
input signed [ W-1:0] Bre_in,
Bim_in,
c_in, // 8-bit inputs
input signed [W1-1:0] cps_in,
cms_in, // coefficients
output reg signed [ W-1:0] Dre_out,
Dim_out, // registered
output signed [ W-1:0] Ere_out,
Eim_out
); // results
reg signed [W-1:0] dif_re, dif_im; // Bf out
reg signed [W-1:0] Are, Aim, Bre, Bim; // Inputs integer
reg signed [W-1:0] c; // Input
reg signed [W1-1:0] cps, cms; // Coefficient in
always @(posedge clk) // Compute the additions of the
begin // butterfly using integers
Are <= Are_in; // and store inputs
Aim <= Aim_in; // in flip-flops
Bre <= Bre_in;
Bim <= Bim_in;
c <= c_in; // Load from memory cos
cps <= cps_in; // Load from memory cos+sin
cms <= cms_in; // Load from memory cos-sin
Dre_out <= (Are >>> 1) + (Bre >>> 1); // Are/2 + Bre/2
Dim_out <= (Aim >>> 1) + (Bim >>> 1); // Aim/2 + Bim/2
end
// No FF because butterfly difference "diff" is not an
always @(*) // output port
begin
dif_re = (Are >>> 1) - (Bre >>> 1); //i.e. Are/2 - Bre/2
dif_im = (Aim >>> 1) - (Bim >>> 1); //i.e. Aim/2 - Bim/2
end
//*** Instantiate the complex twiddle factor multiplier
ccmul ccmul_1 // Multiply (x+jy)(c+js)
(
.clk(clk),
.x_in(dif_re),
.y_in(dif_im),
.c_in(c),
.cps_in(cps),
.cms_in(cms),
.r_out(Ere_out),
.i_out(Eim_out)
);
endmodule
| 6.841971 |
module info begin__
// name : krnl
// function :
// inputs : in_data, weight
// outputs : out_data
// document :
// __module info end__
module bfp_krnl
# (
// The parallism in channel direction
parameter pc = 64,
// The data width of input data
parameter in_data_width=8,
// The data width utilized for accumulated results
parameter out_data_width=32
)
(
input wire clk,
input wire rst_n,
// coefficients for the kernel, each in 8-bit unsigned int format
input wire [pc*in_data_width-1:0] coef,
output wire coef_rdy,
input wire coef_vld,
// up stram data input, one transaction per input pixel
input wire up_vld,
input wire [pc*in_data_width-1:0] up_dat,
output wire up_rdy,
// zero point of the weights
input wire [4:0] shift_bits,
// filter_finish signal which indicates the data transfer for one filter completes
input wire filter_finish_data,
// filter_finish signal which indicates the calculation for one filter completes
// also used for data buffer module to update bias
output wire filter_finish_cal,
input wire [32-1:0] bias_dat,
input wire bias_vld,
// accumulation finish signal which indicates the accumulation result valid
input wire acc_result_vld,
// down stream data output, one transaction per component of an output pixel
output wire dn_vld,
output wire [in_data_width-1:0] dn_dat,
input wire dn_rdy
);
wire ce_up_vld;
wire acc_result_vld_real;
wire ce_up_rdy;
assign acc_result_vld_real = acc_result_vld & up_vld & coef_vld;
// Only the up_vld is "&" with dn_rdy. But it is enough for SIF since only when
// both up_vld and coef_vld is high, the kernel will start compute, otherwise not.
// So controling up_vld is enough.
assign ce_up_vld = up_vld & dn_rdy;
assign up_rdy = ce_up_rdy & coef_vld & up_vld;
assign coef_rdy = up_rdy;
localparam PE = 4;
localparam ENABLE_8OUT = 1;
localparam LATENCY_ADD = 1;
localparam LATENCY_MUL = 2;
bfp_compute_engine #(
.pc(pc),
.pe(PE),
.in_data_width(in_data_width),
.out_data_width(out_data_width),
.latency_add(LATENCY_ADD),
.latency_mul(LATENCY_MUL),
.bias_data_width(32)
) u_compute_engine
(
.rst_n(rst_n),
.clk(clk),
.coef(coef),
.coef_vld(coef_vld),
.up_vld(ce_up_vld),
.up_dat(up_dat),
.up_rdy(ce_up_rdy),
.shift_bits(shift_bits),
.filter_finish_data(filter_finish_data),
.filter_finish_cal(filter_finish_cal),
.bias_dat(bias_dat),
.bias_vld(bias_vld),
.acc_result_vld(acc_result_vld_real),
.dn_vld(dn_vld),
.dn_dat(dn_dat),
.dn_rdy(dn_rdy)
);
endmodule
| 8.53714 |
module bfs_pipeline (
clk,
rst,
last_input_in,
word_in,
word_in_valid,
word_in_th,
control,
current_level,
last_input_out,
control_out,
word_out,
valid_out,
word_in_valid_out,
word_in_th_out
);
parameter ADDR_W = 4; // this value decides how many vertices in a BRAM
localparam DEPTH = (2 ** ADDR_W);
parameter stage_no = 2; // 2^stage_no=4 stages
localparam total_stages_in_ten = (2 ** stage_no);
parameter pipeline_id = 0;
input clk, rst;
input [511:0] word_in;
input [1:0] control;
input [7:0] current_level;
input [0:0] word_in_valid;
input [31:0] word_in_th;
input [0:0] last_input_in;
output [31:0] word_out;
output valid_out;
output [0:0] last_input_out;
output [1:0] control_out;
wire [ 31:0] word_out_wire [total_stages_in_ten-2:0];
wire valid_out_wire [total_stages_in_ten-2:0];
wire [511:0] word_in_out_wire [total_stages_in_ten-2:0];
wire [ 1:0] control_out_wire [total_stages_in_ten-2:0];
wire [ 0:0] last_input_wire [total_stages_in_ten-2:0];
wire [ 0:0] word_in_valid_wire[total_stages_in_ten-2:0];
wire [ 31:0] word_in_th_wire [total_stages_in_ten-2:0];
output reg [0:0] word_in_valid_out; // from afu-io
output reg [31:0] word_in_th_out; // from afu-core
pipeline_start #(
.ADDR_W(ADDR_W),
.stage_no(stage_no),
.pipeline_id(pipeline_id)
) p_start (
.clk(clk),
.rst(rst),
.last_input_in(last_input_in),
.word_in(word_in),
.word_in_valid(word_in_valid),
.word_in_th(word_in_th),
.control(control),
.current_level(current_level),
.control_out(control_out_wire[0]),
.word_in_out(word_in_out_wire[0]),
.last_input_out(last_input_wire[0]),
.word_out(word_out_wire[0]),
.valid_out(valid_out_wire[0]),
.word_in_valid_out(word_in_valid_wire[0]),
.word_in_th_out(word_in_th_wire[0])
);
genvar numstg;
generate
for (numstg = 1; numstg < total_stages_in_ten - 1; numstg = numstg + 1) begin : elements
pipeline_mid #(
.ADDR_W(ADDR_W),
.stage_no(stage_no),
.my_stage_id(numstg),
.pipeline_id(pipeline_id)
) p_mid (
.clk(clk),
.rst(rst),
.last_input_in(last_input_wire[numstg-1]),
.word_in(word_in_out_wire[numstg-1]),
.word_in_valid(word_in_valid_wire[numstg-1]),
.word_in_th(word_in_th_wire[numstg-1]),
.word_out_previous(word_out_wire[numstg-1]),
.valid_out_previous(valid_out_wire[numstg-1]),
.control(control_out_wire[numstg-1]),
.current_level(current_level),
.control_out(control_out_wire[numstg]),
.word_in_out(word_in_out_wire[numstg]),
.last_input_out(last_input_wire[numstg]),
.word_out(word_out_wire[numstg]),
.valid_out(valid_out_wire[numstg]),
.word_in_valid_out(word_in_valid_wire[numstg]),
.word_in_th_out(word_in_th_wire[numstg])
);
end
endgenerate
pipeline_end #(
.ADDR_W(ADDR_W),
.stage_no(stage_no),
.pipeline_id(pipeline_id)
) p_end (
.clk(clk),
.rst(rst),
.last_input_in(last_input_wire[total_stages_in_ten-2]),
.word_in(word_in_out_wire[total_stages_in_ten-2]),
.word_in_valid(word_in_valid_wire[total_stages_in_ten-2]),
.word_in_th(word_in_th_wire[total_stages_in_ten-2]),
.word_out_previous(word_out_wire[total_stages_in_ten-2]),
.valid_out_previous(valid_out_wire[total_stages_in_ten-2]),
.control(control_out_wire[total_stages_in_ten-2]),
.current_level(current_level),
.last_input_out(last_input_out),
.control_out(control_out),
.word_out(word_out),
.valid_out(valid_out),
.word_in_valid_out(word_in_valid_out),
.word_in_th_out(word_in_th_out)
);
endmodule
| 7.652256 |
module gen_nw32 #(
parameter num_leaves = 32,
parameter payload_sz = $clog2(num_leaves) + 4,
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr = 1'b0,
parameter level = 0
) (
input clk,
input reset,
input [p_sz*32-1:0] pe_interface,
output [p_sz*32-1:0] interface_pe,
output [32-1:0] resend
);
wire [4*p_sz-1:0] switch_left;
wire [4*p_sz-1:0] switch_right;
wire [4*p_sz-1:0] left_switch;
wire [4*p_sz-1:0] right_switch;
pi_cluster #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr(addr),
.level(level),
.p_sz(p_sz),
.num_switches(4)
) pi_lvl0 (
.clk (clk),
.reset(reset),
.l_bus_i(left_switch),
.r_bus_i(right_switch),
.l_bus_o(switch_left),
.r_bus_o(switch_right)
);
_2121subtree #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({1'b0}),
.p_sz(p_sz)
) subtree_left (
.clk(clk),
.reset(reset),
.bus_i(switch_left),
.bus_o(left_switch),
.pe_interface(pe_interface[p_sz*16-1:0]),
.interface_pe(interface_pe[p_sz*16-1:0]),
.resend(resend[16-1:0])
);
_2121subtree #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({1'b1}),
.p_sz(p_sz)
) subtree_right (
.clk(clk),
.reset(reset),
.bus_i(switch_right),
.bus_o(right_switch),
.pe_interface(pe_interface[p_sz*32-1:p_sz*16]),
.interface_pe(interface_pe[p_sz*32-1:p_sz*16]),
.resend(resend[32-1:16])
);
endmodule
| 8.389133 |
module _2121subtree #(
parameter num_leaves = 32,
parameter payload_sz = $clog2(num_leaves) + 4,
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr = 1'b0,
parameter level = 1
) (
input clk,
input reset,
input [p_sz*16-1:0] pe_interface,
output [p_sz*16-1:0] interface_pe,
output [16-1:0] resend,
input [1*4*p_sz-1:0] bus_i,
output [1*4*p_sz-1:0] bus_o
);
wire [4*p_sz-1:0] switch_left;
wire [4*p_sz-1:0] switch_right;
wire [4*p_sz-1:0] left_switch;
wire [4*p_sz-1:0] right_switch;
t_cluster #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr(addr),
.level(level),
.p_sz(p_sz),
.num_switches(4)
) t_lvl1 (
.clk(clk),
.reset(reset),
.u_bus_i(bus_i),
.u_bus_o(bus_o),
.l_bus_i(left_switch),
.r_bus_i(right_switch),
.l_bus_o(switch_left),
.r_bus_o(switch_right)
);
_212subtree #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({addr, 1'b0}),
.p_sz(p_sz)
) subtree_left (
.clk(clk),
.reset(reset),
.bus_i(switch_left),
.bus_o(left_switch),
.pe_interface(pe_interface[p_sz*8-1:0]),
.interface_pe(interface_pe[p_sz*8-1:0]),
.resend(resend[8-1:0])
);
_212subtree #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({addr, 1'b1}),
.p_sz(p_sz)
) subtree_right (
.clk(clk),
.reset(reset),
.bus_i(switch_right),
.bus_o(right_switch),
.pe_interface(pe_interface[p_sz*16-1:p_sz*8]),
.interface_pe(interface_pe[p_sz*16-1:p_sz*8]),
.resend(resend[16-1:8])
);
endmodule
| 7.335251 |
module _212subtree #(
parameter num_leaves = 32,
parameter payload_sz = $clog2(num_leaves) + 4,
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr = 2'b00,
parameter level = 2
) (
input clk,
input reset,
input [p_sz*8-1:0] pe_interface,
output [p_sz*8-1:0] interface_pe,
output [8-1:0] resend,
input [2*2*p_sz-1:0] bus_i,
output [2*2*p_sz-1:0] bus_o
);
wire [2*p_sz-1:0] switch_left;
wire [2*p_sz-1:0] switch_right;
wire [2*p_sz-1:0] left_switch;
wire [2*p_sz-1:0] right_switch;
pi_cluster #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr(addr),
.level(level),
.p_sz(p_sz),
.num_switches(2)
) pi_lvl2 (
.clk(clk),
.reset(reset),
.u_bus_i(bus_i),
.u_bus_o(bus_o),
.l_bus_i(left_switch),
.r_bus_i(right_switch),
.l_bus_o(switch_left),
.r_bus_o(switch_right)
);
_21subtree #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({addr, 1'b0}),
.p_sz(p_sz)
) subtree_left (
.clk(clk),
.reset(reset),
.bus_i(switch_left),
.bus_o(left_switch),
.pe_interface(pe_interface[p_sz*4-1:0]),
.interface_pe(interface_pe[p_sz*4-1:0]),
.resend(resend[4-1:0])
);
_21subtree #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({addr, 1'b1}),
.p_sz(p_sz)
) subtree_right (
.clk(clk),
.reset(reset),
.bus_i(switch_right),
.bus_o(right_switch),
.pe_interface(pe_interface[p_sz*8-1:p_sz*4]),
.interface_pe(interface_pe[p_sz*8-1:p_sz*4]),
.resend(resend[8-1:4])
);
endmodule
| 7.317172 |
module _21subtree #(
parameter num_leaves = 32,
parameter payload_sz = $clog2(num_leaves) + 4,
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr = 3'b000,
parameter level = 3
) (
input clk,
input reset,
input [p_sz*4-1:0] pe_interface,
output [p_sz*4-1:0] interface_pe,
output [4-1:0] resend,
input [1*2*p_sz-1:0] bus_i,
output [1*2*p_sz-1:0] bus_o
);
wire [2*p_sz-1:0] switch_left;
wire [2*p_sz-1:0] switch_right;
wire [2*p_sz-1:0] left_switch;
wire [2*p_sz-1:0] right_switch;
t_cluster #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr(addr),
.level(level),
.p_sz(p_sz),
.num_switches(2)
) t_lvl3 (
.clk(clk),
.reset(reset),
.u_bus_i(bus_i),
.u_bus_o(bus_o),
.l_bus_i(left_switch),
.r_bus_i(right_switch),
.l_bus_o(switch_left),
.r_bus_o(switch_right)
);
_2subtree #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({addr, 1'b0}),
.p_sz(p_sz)
) subtree_left (
.clk(clk),
.reset(reset),
.bus_i(switch_left),
.bus_o(left_switch),
.pe_interface(pe_interface[p_sz*2-1:0]),
.interface_pe(interface_pe[p_sz*2-1:0]),
.resend(resend[2-1:0])
);
_2subtree #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({addr, 1'b1}),
.p_sz(p_sz)
) subtree_right (
.clk(clk),
.reset(reset),
.bus_i(switch_right),
.bus_o(right_switch),
.pe_interface(pe_interface[p_sz*4-1:p_sz*2]),
.interface_pe(interface_pe[p_sz*4-1:p_sz*2]),
.resend(resend[4-1:2])
);
endmodule
| 6.97855 |
module _2subtree # (
parameter num_leaves= 32,
parameter payload_sz= $clog2(num_leaves) + 4,
parameter p_sz= 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr= 4'b0000,
parameter level= 4
) (
input clk,
input reset,
input [p_sz*2-1:0] pe_interface,
output [p_sz*2-1:0] interface_pe,
output [2-1:0] resend,
input [2*1*p_sz-1:0] bus_i,
output [2*1*p_sz-1:0] bus_o
);
wire [1*p_sz-1:0] switch_left;
wire [1*p_sz-1:0] switch_right;
wire [1*p_sz-1:0] left_switch;
wire [1*p_sz-1:0] right_switch;
pi_cluster #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr(addr),
.level(level),
.p_sz(p_sz),
.num_switches(1))
pi_lvl4(
.clk(clk),
.reset(reset),
.u_bus_i(bus_i),
.u_bus_o(bus_o),
.l_bus_i(left_switch),
.r_bus_i(right_switch),
.l_bus_o(switch_left),
.r_bus_o(switch_right));
interface #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({addr, 1'b0}),
.p_sz(p_sz))
subtree_left(
.clk(clk),
.reset(reset),
.bus_i(switch_left),
.bus_o(left_switch),
.pe_interface(pe_interface[p_sz*1-1:0]),
.interface_pe(interface_pe[p_sz*1-1:0]),
.resend(resend[1-1:0]));
interface #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr({addr, 1'b1}),
.p_sz(p_sz))
subtree_right(
.clk(clk),
.reset(reset),
.bus_i(switch_right),
.bus_o(right_switch),
.pe_interface(pe_interface[p_sz*2-1:p_sz*1]),
.interface_pe(interface_pe[p_sz*2-1:p_sz*1]),
.resend(resend[2-1:1]));
endmodule
| 7.423772 |
module pipe_ff (
input clk,
input reset,
input [data_width-1:0] din,
output reg [data_width-1:0] dout
);
parameter data_width = 2;
always @(posedge clk) begin
if (reset) dout <= 0;
else dout <= din;
end
endmodule
| 8.069914 |
module pi_cluster (
input clk,
input reset,
input [num_switches*p_sz-1:0] l_bus_i,
input [num_switches*p_sz-1:0] r_bus_i,
input [2*num_switches*p_sz-1:0] u_bus_i,
output [num_switches*p_sz-1:0] l_bus_o,
output [num_switches*p_sz-1:0] r_bus_o,
output [2*num_switches*p_sz-1:0] u_bus_o
);
// Override these values in top modules
parameter num_leaves = 2;
parameter payload_sz = 1;
parameter addr = 1'b0;
parameter level = 1; // only change if level == 0
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz; //packet size
parameter num_switches = 1;
wire [num_switches*p_sz-1:0] ul_bus_i;
wire [num_switches*p_sz-1:0] ur_bus_i;
wire [num_switches*p_sz-1:0] ul_bus_o;
wire [num_switches*p_sz-1:0] ur_bus_o;
assign {ul_bus_i, ur_bus_i} = u_bus_i;
assign u_bus_o = {ul_bus_o, ur_bus_o};
genvar i;
generate
for (i = 0; i < num_switches; i = i + 1) begin
pi_switch #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr(addr),
.level(level),
.p_sz(p_sz)
) ps (
.clk(clk),
.reset(reset),
.l_bus_i(l_bus_i[i*p_sz+:p_sz]),
.r_bus_i(r_bus_i[i*p_sz+:p_sz]),
.ul_bus_i(ul_bus_i[i*p_sz+:p_sz]),
.ur_bus_i(ur_bus_i[i*p_sz+:p_sz]),
.l_bus_o(l_bus_o[i*p_sz+:p_sz]),
.r_bus_o(r_bus_o[i*p_sz+:p_sz]),
.ul_bus_o(ul_bus_o[i*p_sz+:p_sz]),
.ur_bus_o(ur_bus_o[i*p_sz+:p_sz])
);
end
endgenerate
endmodule
| 8.597644 |
module pi_switch (
input clk,
input reset,
input [p_sz-1:0] l_bus_i,
input [p_sz-1:0] r_bus_i,
input [p_sz-1:0] ul_bus_i,
input [p_sz-1:0] ur_bus_i,
output reg [p_sz-1:0] l_bus_o,
output reg [p_sz-1:0] r_bus_o,
output reg [p_sz-1:0] ul_bus_o,
output reg [p_sz-1:0] ur_bus_o
);
// Override these values in top modules
parameter num_leaves = 2;
parameter payload_sz = 1;
parameter addr = 1'b0;
parameter level = 0; // only change if level == 0
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz; //packet size
// bus has following structure: 1 bit [valid], logN bits [dest_addr],
// M bits [payload]
wire [1:0] d_l;
wire [1:0] d_r;
wire [1:0] d_ul;
wire [1:0] d_ur;
wire [1:0] sel_l;
wire [1:0] sel_r;
wire [1:0] sel_ul;
wire [1:0] sel_ur;
reg random;
wire rand_gen;
direction_determiner #(
.num_leaves(num_leaves),
.addr(addr),
.level(level)
) dd_l (
.valid_i(l_bus_i[p_sz-1]),
.addr_i(l_bus_i[p_sz-2:payload_sz]),
.d(d_l)
);
direction_determiner #(
.num_leaves(num_leaves),
.addr(addr),
.level(level)
) dd_r (
.valid_i(r_bus_i[p_sz-1]),
.addr_i(r_bus_i[p_sz-2:payload_sz]),
.d(d_r)
);
direction_determiner #(
.num_leaves(num_leaves),
.addr(addr),
.level(level)
) dd_ul (
.valid_i(ul_bus_i[p_sz-1]),
.addr_i(ul_bus_i[p_sz-2:payload_sz]),
.d(d_ul)
);
direction_determiner #(
.num_leaves(num_leaves),
.addr(addr),
.level(level)
) dd_ur (
.valid_i(ur_bus_i[p_sz-1]),
.addr_i(ur_bus_i[p_sz-2:payload_sz]),
.d(d_ur)
);
always @(posedge clk)
if (reset) random <= 1'b0;
else if (rand_gen) random <= ~random;
pi_arbiter #(
.level(level)
) pi_a (
.d_l(d_l),
.d_r(d_r),
.d_ul(d_ul),
.d_ur(d_ur),
.sel_l(sel_l),
.sel_r(sel_r),
.sel_ul(sel_ul),
.sel_ur(sel_ur),
.random(random),
.rand_gen(rand_gen)
);
always @(posedge clk)
if (reset) {l_bus_o, r_bus_o, ul_bus_o, ur_bus_o} <= 0;
else begin
case (sel_l)
`LEFT: l_bus_o <= l_bus_i;
`RIGHT: l_bus_o <= r_bus_i;
`UPL: l_bus_o <= ul_bus_i;
`UPR: l_bus_o <= ur_bus_i;
endcase
case (sel_r)
`LEFT: r_bus_o <= l_bus_i;
`RIGHT: r_bus_o <= r_bus_i;
`UPL: r_bus_o <= ul_bus_i;
`UPR: r_bus_o <= ur_bus_i;
endcase
case (sel_ul)
`LEFT: ul_bus_o <= l_bus_i;
`RIGHT: ul_bus_o <= r_bus_i;
`UPL: ul_bus_o <= ul_bus_i;
`UPR: ul_bus_o <= ur_bus_i;
endcase
case (sel_ur)
`LEFT: ur_bus_o <= l_bus_i;
`RIGHT: ur_bus_o <= r_bus_i;
`UPL: ur_bus_o <= ul_bus_i;
`UPR: ur_bus_o <= ur_bus_i;
endcase
end
endmodule
| 8.128678 |
module t_arbiter(
input [1:0] d_l,
input [1:0] d_r,
input [1:0] d_u,
output reg [1:0] sel_l,
output reg [1:0] sel_r,
output reg [1:0] sel_u
);
parameter level= 1;
/*
* d_l, d_r, d_u designate where the specific packet from a certain
* direction would like to (ideally go).
* d_{l,r,u}=00, non-valid packet.
* d_{l,r,u}=01, packet should go left.
* d_{l,r,u}=10, packet should go right.
* d_{l,r,u}=11, packet should go up.
*/
generate
if (level == 0)
always @* begin
sel_l= `VOID;
sel_r= `VOID;
sel_u= `VOID;
if (d_l == `LEFT)
sel_l= `LEFT;
if (d_r == `RIGHT)
sel_r= `RIGHT;
if (sel_l == `VOID && d_r == `LEFT)
sel_l= `RIGHT;
if (sel_l == `LEFT && d_r == `LEFT)
sel_r= `RIGHT;
if (sel_r == `VOID && d_l == `RIGHT)
sel_r= `LEFT;
if (sel_r == `RIGHT && d_l == `RIGHT)
sel_l= `LEFT;
end
else
/*
* select lines are for the MUX's that actually route the packets to the
`UP* neighboring nodes.
*/
always @* begin
sel_l= `VOID;
sel_r= `VOID;
sel_u= `VOID;
// First Priority: Turnback (When a packet has already been deflected
// and needs to turn back within one level)
if (d_l == `LEFT)
sel_l= `LEFT;
if (d_r == `RIGHT)
sel_r= `RIGHT;
if (d_u == `UP)
sel_u= `UP;
// Second Priority: Downlinks (When a packet wants to go from Up to
// Left or Right-- must check if bus is already used by Turnbacked
// packets)
else if (d_u == `LEFT)
if (d_l != `LEFT)
sel_l= `UP;
// If left bus is already used by turnback packet, deflect up
// packet back up
else
sel_u= `UP;
else if (d_u == `RIGHT)
if (d_r != `RIGHT)
sel_r= `UP;
// If right bus is already used by turnback packet, deflect up
// packet back up
else
sel_u= `UP;
// Third Priority: `UP/Side Link
// Left to Right
if (d_l == `RIGHT)
// if right bus is not already used by either a turnback packet or
// a downlink packet, send left packet there
if (sel_r == `VOID)
sel_r= `LEFT;
// otherwise, deflect left packet
// If downlink is already using left bus, deflect packet up
else if (d_u == `LEFT)
sel_u= `LEFT;
// Last remaining option is deflection in direction of arrival
// (must be correct, via deduction)
else
sel_l= `LEFT;
// Left to Up
else if (d_l == `UP)
// if up bus is not occupied by turnback packet, send uplink up
if (sel_u == `VOID)
sel_u= `LEFT;
// otherwise, deflect left packet
// deflect back in direction of arrival if possible
else if (sel_l == `VOID)
sel_l= `LEFT;
// otherwise, deflect to the right
else
sel_r= `LEFT;
// Right to Left
if (d_r == `LEFT)
// if left bus is not occupied by turnback packet or downlink
// paket, send right packet there
if (sel_l == `VOID)
sel_l= `RIGHT;
// otherwise, deflect packet
else if (sel_r == `VOID)
sel_r= `RIGHT;
else
sel_u= `RIGHT;
// Right to Up
else if (d_r == `UP)
// if up bus is not occupied by turnback packet or other uplink
// packet, send right uplink packet up
if (sel_u == `VOID)
sel_u= `RIGHT;
// else deflect right packet
else if (sel_r == `VOID)
sel_r= `RIGHT;
// last possible option is to send packet to the left
else
sel_l= `RIGHT;
`ifdef OPTIMIZED
// Makes exception to when left and right packets swap, up packet gets
// deflected up
if (d_l == `RIGHT && d_r == `LEFT && d_u != `VOID) begin
sel_l= `RIGHT;
sel_r= `LEFT;
sel_u= `UP;
end
`endif
end
endgenerate
endmodule
| 7.262206 |
module t_cluster (
input clk,
input reset,
input [num_switches*p_sz-1:0] l_bus_i,
input [num_switches*p_sz-1:0] r_bus_i,
input [num_switches*p_sz-1:0] u_bus_i,
output [num_switches*p_sz-1:0] l_bus_o,
output [num_switches*p_sz-1:0] r_bus_o,
output [num_switches*p_sz-1:0] u_bus_o
);
// Override these values in top modules
parameter num_leaves = 2;
parameter payload_sz = 1;
parameter addr = 1'b0;
//parameter level= $bits(addr); // only change if level == 0
parameter level = 15;
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz; //packet size
parameter num_switches = 1;
genvar i;
generate
for (i = 0; i < num_switches; i = i + 1) begin
t_switch #(
.num_leaves(num_leaves),
.payload_sz(payload_sz),
.addr(addr),
.level(level),
.p_sz(p_sz)
) ts (
.clk(clk),
.reset(reset),
.l_bus_i(l_bus_i[i*p_sz+:p_sz]),
.r_bus_i(r_bus_i[i*p_sz+:p_sz]),
.u_bus_i(u_bus_i[i*p_sz+:p_sz]),
.l_bus_o(l_bus_o[i*p_sz+:p_sz]),
.r_bus_o(r_bus_o[i*p_sz+:p_sz]),
.u_bus_o(u_bus_o[i*p_sz+:p_sz])
);
end
endgenerate
endmodule
| 8.876029 |
module t_switch (
input clk,
input reset,
input [p_sz-1:0] l_bus_i,
input [p_sz-1:0] r_bus_i,
input [p_sz-1:0] u_bus_i,
output reg [p_sz-1:0] l_bus_o,
output reg [p_sz-1:0] r_bus_o,
output reg [p_sz-1:0] u_bus_o
);
// Override these values in top modules
parameter num_leaves = 2;
parameter payload_sz = 1;
parameter addr = 1'b0;
parameter level = 15; // only change if level == 0
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz; //packet size
// bus has following structure: 1 bit [valid], logN bits [dest_addr],
// M bits [payload]
wire [1:0] d_l;
wire [1:0] d_r;
wire [1:0] d_u;
wire [1:0] sel_l;
wire [1:0] sel_r;
wire [1:0] sel_u;
direction_determiner #(
.num_leaves(num_leaves),
.addr(addr),
.level(level)
) dd_l (
.valid_i(l_bus_i[p_sz-1]),
.addr_i(l_bus_i[p_sz-2:payload_sz]),
.d(d_l)
);
direction_determiner #(
.num_leaves(num_leaves),
.addr(addr),
.level(level)
) dd_r (
.valid_i(r_bus_i[p_sz-1]),
.addr_i(r_bus_i[p_sz-2:payload_sz]),
.d(d_r)
);
direction_determiner #(
.num_leaves(num_leaves),
.addr(addr),
.level(level)
) dd_u (
.valid_i(u_bus_i[p_sz-1]),
.addr_i(u_bus_i[p_sz-2:payload_sz]),
.d(d_u)
);
t_arbiter #(
.level(level)
) t_a (
d_l,
d_r,
d_u,
sel_l,
sel_r,
sel_u
);
always @(posedge clk)
if (reset) {l_bus_o, r_bus_o, u_bus_o} <= 0;
else begin
case (sel_l)
`VOID: l_bus_o <= 0;
`LEFT: l_bus_o <= l_bus_i;
`RIGHT: l_bus_o <= r_bus_i;
`UP: l_bus_o <= u_bus_i;
endcase
case (sel_r)
`VOID: r_bus_o <= 0;
`LEFT: r_bus_o <= l_bus_i;
`RIGHT: r_bus_o <= r_bus_i;
`UP: r_bus_o <= u_bus_i;
endcase
case (sel_u)
`VOID: u_bus_o <= 0;
`LEFT: u_bus_o <= l_bus_i;
`RIGHT: u_bus_o <= r_bus_i;
`UP: u_bus_o <= u_bus_i;
endcase
end
endmodule
| 7.748937 |
module bfu_model (
clk,
rstn,
in1,
in2,
gamma,
op,
p,
R_1,
mm_out_golden,
ms_out_golden,
ma_out_golden,
out1_golden,
out2_golden
);
input wire clk;
input wire rstn;
input wire [`datawidth-1:0] in1;
input wire [`datawidth-1:0] in2;
input wire [`datawidth-1:0] gamma;
input wire [1:0] op;
input wire [`datawidth-1:0] p;
input wire [`datawidth-1:0] R_1;
/* output wire [127:0] mm_out_golden;
output wire [127:0] ms_out_golden;
output wire [127:0] ma_out_golden; */
output reg [127:0] mm_out_golden;
output reg [127:0] ms_out_golden;
output reg [127:0] ma_out_golden;
output wire [127:0] out1_golden;
output wire [127:0] out2_golden;
//reg [127:0] mm_out_golden_;
//reg [127:0] ms_out_golden_;
//reg [127:0] ma_out_golden_;
reg [127:0] out1_golden_tmp;
reg [127:0] out2_golden_tmp;
always @(*) begin
if (op == 2'b00) begin
mm_out_golden = (in2 * gamma * R_1) % p;
ms_out_golden = (in1 - (in2 * gamma * R_1) % p + p) % p;
ma_out_golden = (in1 + (in2 * gamma * R_1) % p) % p;
out1_golden_tmp = (in1 + (in2 * gamma * R_1) % p) % p;
out2_golden_tmp = (in1 - (in2 * gamma * R_1) % p + p) % p;
end else if (op == 2'b01) begin
mm_out_golden = (((in2 - in1 + p) % p) * gamma * R_1) % p;
ms_out_golden = ((in2 - in1 + p) % p);
ma_out_golden = (in1 + in2) % p;
out1_golden_tmp = (in1 + in2) % p;
out2_golden_tmp = (((in2 - in1 + p) % p) * gamma * R_1) % p;
end else if (op == 2'b10) begin
mm_out_golden = (in1 * in2 * R_1) % p;
ms_out_golden = 'd0;
ma_out_golden = 'd0;
out1_golden_tmp = (in1 * in2 * R_1) % p;
out2_golden_tmp = 'd0;
end else if (op == 2'b11) begin
mm_out_golden = 'd0;
ms_out_golden = (in2 - in1 + p) % p;
ma_out_golden = (in1 + in2) % p;
out1_golden_tmp = (in1 + in2) % p;
out2_golden_tmp = (in2 - in1 + p) % p;
end
end
parameter PIPE_STAGE = 8;
reg [127:0] out1_golden_pipe[0:PIPE_STAGE-1];
reg [127:0] out2_golden_pipe[0:PIPE_STAGE-1];
generate
genvar cnt;
for (cnt = 0; cnt < PIPE_STAGE; cnt = cnt + 1) begin : gen_bcd_pipe
if (cnt == 0) begin
always @(posedge clk or negedge rstn)
if (~rstn) begin
out1_golden_pipe[cnt] <= 'd0;
out2_golden_pipe[cnt] <= 'd0;
end else begin
out1_golden_pipe[cnt] <= out1_golden_tmp;
out2_golden_pipe[cnt] <= out2_golden_tmp;
end
end else begin
always @(posedge clk or negedge rstn)
if (~rstn) begin
out1_golden_pipe[cnt] <= 'd0;
out2_golden_pipe[cnt] <= 'd0;
end else begin
out1_golden_pipe[cnt] <= out1_golden_pipe[cnt-1];
out2_golden_pipe[cnt] <= out2_golden_pipe[cnt-1];
end
end
end
endgenerate
assign out1_golden = out1_golden_pipe[PIPE_STAGE-1];
assign out2_golden = out2_golden_pipe[PIPE_STAGE-1];
endmodule
| 7.583505 |
module bfu_v1 (
input clk,
input rstn,
input [`datawidth-1:0] in1,
input [`datawidth-1:0] in2,
input [`datawidth-1:0] gamma, //required by BF
input op,
input [`datawidth-1:0] p,
input [`datawidth-1:0] _p,
input [`datawidth-1:0] mu, //required by mml
output [`datawidth-1:0] out1,
output [`datawidth-1:0] out2
);
wire [`datawidth-1:0] mux_mm1_in1_D;
wire [`datawidth-1:0] mux_mm1_in1_Q;
wire [`datawidth-1:0] mm1_out_D;
wire [`datawidth-1:0] mm1_out_Q;
wire [`datawidth-1:0] ms1_out;
assign mux_mm1_in1_D = op ? ms1_out : in2;
DFF #(
.datawidth(`datawidth)
) dff_muxmm1in1_1 (
.clk(clk),
.rstn(rstn),
.D(mux_mm1_in1_D),
.Q(mux_mm1_in1_Q)
);
wire [`datawidth-1:0] gamma_Q;
DFF #(
.datawidth(`datawidth)
) dff_gamma_1 (
.clk(clk),
.rstn(rstn),
.D(gamma),
.Q(gamma_Q)
);
km_mm mm1 (
.clk(clk),
.rstn(rstn),
.in1(mux_mm1_in1_Q),
.in2(gamma_Q),
.mu(mu),
.p(p),
._p(_p),
.out(mm1_out_D)
);
DFF #(
.datawidth(`datawidth)
) dff_mm1out_1 (
.clk(clk),
.rstn(rstn),
.D(mm1_out_D),
.Q(mm1_out_Q)
);
wire [`datawidth-1:0] in1_Q;
wire [`datawidth-1:0] in1_QQ;
wire [`datawidth-1:0] in1_QQQ;
wire [`datawidth-1:0] in1_QQQQ;
wire [`datawidth-1:0] in1_QQQQQ;
wire [`datawidth-1:0] in1_QQQQQQ;
wire [`datawidth-1:0] in1_QQQQQQQ;
wire [`datawidth-1:0] in1_QQQQQQQQ;
DFF #(
.datawidth(`datawidth)
) dff_in1_1 (
.clk(clk),
.rstn(rstn),
.D(in1),
.Q(in1_Q)
);
DFF #(
.datawidth(`datawidth)
) dff_in1_2 (
.clk(clk),
.rstn(rstn),
.D(in1_Q),
.Q(in1_QQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in1_3 (
.clk(clk),
.rstn(rstn),
.D(in1_QQ),
.Q(in1_QQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in1_4 (
.clk(clk),
.rstn(rstn),
.D(in1_QQQ),
.Q(in1_QQQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in1_5 (
.clk(clk),
.rstn(rstn),
.D(in1_QQQQ),
.Q(in1_QQQQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in1_6 (
.clk(clk),
.rstn(rstn),
.D(in1_QQQQQ),
.Q(in1_QQQQQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in1_7 (
.clk(clk),
.rstn(rstn),
.D(in1_QQQQQQ),
.Q(in1_QQQQQQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in1_8 (
.clk(clk),
.rstn(rstn),
.D(in1_QQQQQQQ),
.Q(in1_QQQQQQQQ)
);
wire [`datawidth-1:0] in2_Q;
wire [`datawidth-1:0] in2_QQ;
wire [`datawidth-1:0] in2_QQQ;
wire [`datawidth-1:0] in2_QQQQ;
wire [`datawidth-1:0] in2_QQQQQ;
wire [`datawidth-1:0] in2_QQQQQQ;
wire [`datawidth-1:0] in2_QQQQQQQ;
wire [`datawidth-1:0] in2_QQQQQQQQ;
DFF #(
.datawidth(`datawidth)
) dff_in2_1 (
.clk(clk),
.rstn(rstn),
.D(in2),
.Q(in2_Q)
);
DFF #(
.datawidth(`datawidth)
) dff_in2_2 (
.clk(clk),
.rstn(rstn),
.D(in2_Q),
.Q(in2_QQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in2_3 (
.clk(clk),
.rstn(rstn),
.D(in2_QQ),
.Q(in2_QQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in2_4 (
.clk(clk),
.rstn(rstn),
.D(in2_QQQ),
.Q(in2_QQQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in2_5 (
.clk(clk),
.rstn(rstn),
.D(in2_QQQQ),
.Q(in2_QQQQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in2_6 (
.clk(clk),
.rstn(rstn),
.D(in2_QQQQQ),
.Q(in2_QQQQQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in2_7 (
.clk(clk),
.rstn(rstn),
.D(in2_QQQQQQ),
.Q(in2_QQQQQQQ)
);
DFF #(
.datawidth(`datawidth)
) dff_in2_8 (
.clk(clk),
.rstn(rstn),
.D(in2_QQQQQQQ),
.Q(in2_QQQQQQQQ)
);
wire [`datawidth-1:0] mux_ma1_in2;
wire [`datawidth-1:0] ma1_out;
assign mux_ma1_in2 = op ? in2_QQQQQQQQ : mm1_out_Q;
mod_add ma1 (
.in1(in1_QQQQQQQQ),
.in2(mux_ma1_in2),
._p (_p),
.out(ma1_out)
);
wire [`datawidth-1:0] mux_ms1_in1;
wire [`datawidth-1:0] mux_ms1_in2;
assign mux_ms1_in1 = op ? in2 : in1_QQQQQQQQ;
assign mux_ms1_in2 = op ? in1 : mm1_out_Q;
mod_sub ms1 (
.in1(mux_ms1_in1),
.in2(mux_ms1_in2),
.p (p),
.out(ms1_out)
);
assign out1 = ma1_out;
assign out2 = op ? mm1_out_Q : ms1_out;
endmodule
| 6.885831 |
module bf_2_2_stage
# (
parameter DATA_WIDTH = 32,
STAGE_ORDER = 0, // 说明是第几级stage
IS_PIPED = 1
)
(
input wire clk,
// input wire rst,
input wire [DATA_WIDTH/2-1:0] config_data,
input wire [DATA_WIDTH-1:0] din,
output wire [DATA_WIDTH-1:0] dout
);
localparam SHIFT = 2**STAGE_ORDER ; //ibf网络的偏移量，
localparam REGION_NUM = (DATA_WIDTH/2)/SHIFT; // 完全一样的子蝶形网络的个数
localparam ELEMENT_NUM_PER_REGION = DATA_WIDTH/REGION_NUM;
wire [DATA_WIDTH-1:0] data_temp_wire ;
reg [DATA_WIDTH-1:0] data_temp_reg ;
genvar i,j;
for (i = 0;i<REGION_NUM ;i=i+1 ) begin
for (j = 0; j<ELEMENT_NUM_PER_REGION/2; j=j+1) begin
LUT6_2 #(
.INIT(64'b0000000000000000000000001010110000000000000000000000000011001010)
) LUT6_2_inst (
.O6(data_temp_wire[ELEMENT_NUM_PER_REGION*i+j+SHIFT]),
.O5(data_temp_wire[ELEMENT_NUM_PER_REGION*i+j]),
.I0(din[ELEMENT_NUM_PER_REGION*i+j]),
.I1(din[ELEMENT_NUM_PER_REGION*i+j+SHIFT]),
.I2(config_data[i*(ELEMENT_NUM_PER_REGION/2)+j]),
.I3(1'b0),
.I4(1'b0),
.I5(1'b1)
);
end
end
always @(posedge clk) begin
data_temp_reg <= data_temp_wire ;
end
assign dout = (IS_PIPED == 1'b1)?data_temp_reg:data_temp_wire;
endmodule
| 7.285304 |
module
//////////////////////////////////////////////////////////////////////////////////
module bf_addr(
input [3:0] layer_num,
input [7:0] bf_num,
output [8:0] addr_a,
output [8:0] addr_pair
);
reg [8:0] addr_a_reg, addr_pair_reg;
assign addr_a = addr_a_reg[8:0];
assign addr_pair = addr_pair_reg[8:0];
reg [8:0] offset;
// combinational block
always @(*) begin
offset = (bf_num >> (8-layer_num));
addr_a_reg = (({bf_num[7:0],1'd0} << layer_num) & 9'd511) + offset;
addr_pair_reg = (({bf_num[7:0],1'd1} << layer_num) & 9'd511) + offset;
end
endmodule
| 6.558648 |
module bf_buffer #(
parameter D_WL = 24,
parameter UNITS_NUM = 5
) (
input [7:0] addr,
output [UNITS_NUM*D_WL-1:0] w_o
);
//6*5=30；
wire [D_WL*UNITS_NUM-1:0] w_fix[0:5];
assign w_o = w_fix[addr];
assign w_fix[0] = 'h002f410042040062760057ed004aed;
assign w_fix[1] = 'h0043b4003a83002da5005625004b44;
assign w_fix[2] = 'h002c300039db003b6b0050f0003824;
assign w_fix[3] = 'h0038ea004863005a0e003bf4005cec;
assign w_fix[4] = 'h00390a004d8900778a004ddd0020b8;
assign w_fix[5] = 'h002d1f004ad4003ec50032a200456a;
endmodule
| 6.506043 |
module BF_decoder_3_bit (
output reg [7:0] D,
input [2:0] I,
input E
);
always @(I or E) begin
if (E == 1'b0)
case (I)
3'b000: D = 8'b00000001;
3'b001: D = 8'b00000010;
3'b010: D = 8'b00000100;
3'b011: D = 8'b00001000;
3'b100: D = 8'b00010000;
3'b101: D = 8'b00100000;
3'b110: D = 8'b01000000;
3'b111: D = 8'b10000000;
endcase
else if (E == 1'b1) D = 8'b00000000;
end
endmodule
| 7.478609 |
module BF_op #(
parameter MULT_WIDTH = 18
) (
input [2*MULT_WIDTH-1:0] ia,
input [2*MULT_WIDTH-1:0] ib,
output [2*MULT_WIDTH-1:0] oa,
output [2*MULT_WIDTH-1:0] ob
);
// `include "fft_inc.h"
localparam REAL_MSB = 2 * MULT_WIDTH - 1; // 35
localparam REAL_LSB = MULT_WIDTH; // 18
localparam IMGN_MSB = MULT_WIDTH - 1; // 17
localparam IMGN_LSB = 0; // 0
assign oa[REAL_MSB:REAL_LSB] = ia[REAL_MSB:REAL_LSB] + ib[REAL_MSB:REAL_LSB];
assign oa[IMGN_MSB:IMGN_LSB] = ia[IMGN_MSB:IMGN_LSB] + ib[IMGN_MSB:IMGN_LSB];
assign ob[REAL_MSB:REAL_LSB] = ia[REAL_MSB:REAL_LSB] - ib[REAL_MSB:REAL_LSB];
assign ob[IMGN_MSB:IMGN_LSB] = ia[IMGN_MSB:IMGN_LSB] - ib[IMGN_MSB:IMGN_LSB];
endmodule
| 7.753791 |
module BF_stg1 #(
parameter FFT_STG = 7,
parameter REAL_WIDTH = 18,
parameter IMGN_WIDTH = 18,
parameter TOTAL_STAGE = 11,
localparam CPLX_WIDTH = REAL_WIDTH + IMGN_WIDTH
) (
input iclk,
input rst_n,
input ien,
input [TOTAL_STAGE-1 : 0] iaddr,
input [CPLX_WIDTH -1 : 0] idata,
output oen,
output [TOTAL_STAGE-1 : 0] oaddr,
output [CPLX_WIDTH -1 : 0] odata
);
localparam TOTAL_ADDR_MAX = {TOTAL_STAGE{1'b1}};
localparam STG_MAX = {FFT_STG{1'b1}};
localparam STG_HALFMAX = (STG_MAX >> 1);
reg [CPLX_WIDTH - 1 : 0] r[STG_HALFMAX:0];
integer i;
initial begin
for (i = 0; i <= STG_HALFMAX; i = i + 1) begin
r[i] = 0;
end
end
reg dump = 0;
reg [FFT_STG - 1 : 0] dump_cnt = 0;
always @(posedge iclk) begin
if (iaddr[FFT_STG-1:0] == STG_MAX && ien) begin
dump <= 1'b1;
dump_cnt <= 0;
end else if (dump) begin
if (dump_cnt == STG_HALFMAX) dump <= 1'b0;
dump_cnt <= dump_cnt + 1'b1;
end
end
wire with_dump;
assign with_dump = dump;
wire [CPLX_WIDTH - 1 : 0] bf_ia;
wire [CPLX_WIDTH - 1 : 0] bf_ib;
wire [CPLX_WIDTH - 1 : 0] bf_oa;
wire [CPLX_WIDTH - 1 : 0] bf_ob;
assign bf_ia = r[STG_HALFMAX];
assign bf_ib = idata;
BF_op #(
.REAL_WIDTH(REAL_WIDTH),
.IMGN_WIDTH(IMGN_WIDTH)
) bf0 (
.ia(bf_ia),
.ib(bf_ib),
.oa(bf_oa),
.ob(bf_ob)
);
wire [CPLX_WIDTH - 1 : 0] wdata_in;
integer index;
always @(posedge iclk) begin
if (ien) r[0] <= wdata_in;
for (index = STG_HALFMAX; index > 0; index = index - 1) r[index] <= r[index-1];
end
reg oen_r = 0;
reg [TOTAL_STAGE-1 : 0] oaddr_r = 0;
reg [CPLX_WIDTH -1 : 0] odata_r = 0;
wire is_load;
wire is_calc;
assign is_load = ~iaddr[FFT_STG-1];
assign is_calc = iaddr[FFT_STG-1];
assign wdata_in = is_load ? idata : bf_ob;
always @(posedge iclk) begin
if (is_calc & ien) begin
odata_r <= bf_oa;
oaddr_r <= oaddr_r + 1'b1;
oen_r <= 1'b1;
end else if ((is_load | ~ien) & with_dump) begin
odata_r <= r[STG_HALFMAX];
oaddr_r <= oaddr_r + 1'b1;
oen_r <= 1'b1;
end else begin
odata_r <= 0;
oaddr_r <= TOTAL_ADDR_MAX;
oen_r <= 1'b0;
end
end
assign odata = odata_r;
assign oaddr = oaddr_r;
assign oen = oen_r;
endmodule
| 8.371965 |
module BF_stgX #(
parameter FFT_STG = 12,
TOTAL_STAGE_P = 10,
MULT_WIDTH_P = 18
) (
input iclk,
input rst_n,
input ien,
input [TOTAL_STAGE_P-1:0] iaddr,
input [2*MULT_WIDTH_P-1:0] idata,
output reg oen,
output reg [TOTAL_STAGE_P-1:0] oaddr,
output reg [2*MULT_WIDTH_P-1:0] odata
);
`include "fft_inc.h"
localparam TOTAL_ADDR_MAX = {TOTAL_STAGE_P{1'b1}};
localparam STG_MAX = {FFT_STG{1'b1}};
localparam STG_HALFMAX = (STG_MAX >> 1);
localparam CPLX_WIDTH = 2 * MULT_WIDTH_P;
wire [CPLX_WIDTH-1 : 0] bf_ia;
wire [CPLX_WIDTH-1 : 0] bf_ib;
wire [CPLX_WIDTH-1 : 0] bf_oa;
wire [CPLX_WIDTH-1 : 0] bf_ob;
wire is_load;
wire is_calc;
wire with_dump;
reg dump = 0;
reg [FFT_STG-2:0] dump_cnt = 0;
reg [CPLX_WIDTH-1 : 0] r[STG_HALFMAX : 0];
wire [CPLX_WIDTH-1 : 0] wdata_in;
wire [FFT_STG-2 : 0] waddr_in;
wire wen_in;
reg [CPLX_WIDTH-1 : 0] rdata = 0;
reg [CPLX_WIDTH-1 : 0] rdata_out = 0;
wire [FFT_STG-2 : 0] raddr_in;
assign is_load = ~iaddr[FFT_STG-1]; // iaddr[FFT_STG-1:0] <= STG_HALFMAX; // is_load = ~iaddr[FFT_STG-1];
assign is_calc = iaddr[FFT_STG-1]; // iaddr[FFT_STG-1:0] > STG_HALFMAX; // is_calc = iaddr[FFT_STG-1];
// for sync-ram: registered write port, unregistered read port
always @(posedge iclk) begin
if (wen_in) r[waddr_in] <= #SIM_DLY wdata_in;
rdata_out <= #SIM_DLY r[raddr_in];
end
always @(posedge iclk) begin
rdata <= #SIM_DLY rdata_out;
end
// ram wr sigal
assign waddr_in = iaddr[FFT_STG-2:0];
assign wdata_in = is_load ? idata : bf_ob;
assign wen_in = ien;
// ram rd signal
assign raddr_in = (with_dump ? dump_cnt : iaddr[FFT_STG-2:0]) + 2'b10;
// bufferfly
assign bf_ia = rdata;
assign bf_ib = idata;
always @(posedge iclk) begin
if(is_calc & ien) // actually started
begin
odata <= #SIM_DLY bf_oa;
oaddr <= #SIM_DLY oaddr + 1'b1;
oen <= #SIM_DLY 1'b1;
end else if ((is_load | ~ien) & with_dump) begin
odata <= #SIM_DLY rdata;
oaddr <= #SIM_DLY oaddr + 1'b1;
oen <= #SIM_DLY 1'b1;
end else // input address is big, but is not writing
begin
odata <= #SIM_DLY 0;
oaddr <= #SIM_DLY TOTAL_ADDR_MAX;
oen <= #SIM_DLY 1'b0;
end
end
always @(posedge iclk) begin
if (iaddr[FFT_STG-1:0] == STG_MAX && ien) begin
dump <= #SIM_DLY 1'b1;
dump_cnt <= #SIM_DLY 0;
end else if (dump) begin
if (dump_cnt == STG_HALFMAX) dump <= #SIM_DLY 1'b0;
dump_cnt <= #SIM_DLY dump_cnt + 1'b1;
end
end
assign with_dump = dump;
BF_op #(
.MULT_WIDTH(MULT_WIDTH_P)
) bf0 (
.ia(bf_ia),
.ib(bf_ib),
.oa(bf_oa), // ia + ib
.ob(bf_ob) // ia - ib
);
endmodule
| 6.865361 |
module can give a background 0 when recieved rst signal
module blanket_0(
output wire [3:0] dat_out,
output wire [7:0] addr_out,
output wire w_en_out,rst_done,
input wire clk,en_in, rev_in
);
//Counter variable
integer i;
//Registers to manipulate outputs - connected to output ports.
reg [7:0] w_addr;
reg [3:0] w_data;
reg w_en;
reg rst_d;
//Begin Process at rst recieved
//Write 0s in ascending order of rows
always @ (posedge clk)
begin
@(posedge clk)begin end
if (rev_in)
begin
w_data = 4'b1111;
i = 0;
end
else
begin
w_data = 4'b0000;
i = 0;
end
if (en_in)
begin
for (i =0; i<256 ; i=i+1)
begin
@ (posedge clk)
begin
w_addr = i;
w_data = (w_data) ;
w_en = 1;
end
end
//Output Rst_done when operation complete
@(posedge clk)
if(addr_out==255)
begin
rst_d = 1;
end
end
@(posedge clk) begin end
if (rst_d)
begin
w_en = 0;
w_addr = 0;
rst_d = 0;
end
end
//Continous assignments
assign w_en_out = w_en;
assign addr_out = w_addr;
assign dat_out = w_data;
assign rst_done = rst_d;
endmodule
| 6.964794 |
module bg0_tb;
wire [3:0] dat_out;
wire [7:0] addr_out;
wire w_en, rst_done;
reg clk, en_in, rev_in;
blanket_0 UUT (
.dat_out(dat_out),
.addr_out(addr_out),
.w_en_out(w_en),
.rst_done(rst_done),
.clk(clk),
.en_in(en_in),
.rev_in(rev_in)
);
initial begin
clk = 0;
en_in = 0;
rev_in = 0;
end
initial
@(posedge clk) begin
// Write Cycle
#100;
en_in = 1;
rev_in = 0;
#5000;
en_in = 0;
#20;
rev_in = 1;
en_in = 1;
#500 rev_in = 0;
en_in = 0;
end
// 20ns Clk
always begin
#10 clk = ~clk;
end
endmodule
| 6.590284 |
module BGCollisionDetector (
input btnU,
input [9:0] Hcount,
input [9:0] Vcount,
input Green,
output UpStop,
output DwStop,
output LeftStop,
output RightStop
);
assign UpStop = (~(Vcount == 10'b0000001000) & btnU & ~Green) |
(~(Vcount == 10'b0000001000) & btnU & Green) |
((Vcount == 10'b0000001000) & btnU & Green);
endmodule
| 7.030911 |
module delay5 (
clock,
d5_delay_in,
d5_delay_out
);
input clock;
input [`BITS-1:0] d5_delay_in;
output [`BITS-1:0] d5_delay_out;
//FIFO delay
reg [`BITS-1:0] d5_reg1;
/*
reg [`BITS-1:0] d5_reg2;
reg [`BITS-1:0] d5_reg3;
reg [`BITS-1:0] d5_reg4;
reg [`BITS-1:0] d5_reg5;
reg [`BITS-1:0] d5_reg6;
*/
assign d5_delay_out = d5_reg1;
always @(posedge clock) begin
d5_reg1 <= d5_delay_in;
/*
d5_reg2 <= d5_reg1;
d5_reg3 <= d5_reg2;
d5_reg4 <= d5_reg3;
d5_reg5 <= d5_reg4;
d5_reg6 <= d5_reg5;
*/
end
endmodule
| 6.609939 |
module delay_chain (
clock,
delay_in,
delay_out
);
input clock;
input [`BITS-1:0] delay_in;
output [`BITS-1:0] delay_out;
// wire [`BITS-1:0] delay_out;
wire [`BITS-1:0] delay44_out;
wire [`BITS-1:0] delay5_out1;
wire [`BITS-1:0] delay5_out2;
wire [`BITS-1:0] delay5_out3;
wire [`BITS-1:0] delay5_out4;
delay44 delay_c1 (
clock,
delay_in,
delay44_out
);
delay5 delay_c2 (
clock,
delay44_out,
delay5_out1
);
delay5 delay_c3 (
clock,
delay5_out1,
delay5_out2
);
delay5 delay_c4 (
clock,
delay5_out2,
delay5_out3
);
delay5 delay_c5 (
clock,
delay5_out3,
delay5_out4
);
assign delay_out = delay5_out4;
endmodule
| 6.555526 |
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [30:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
reg expa_ff, infa_f_r, qnan_r_a, snan_r_a;
reg expb_ff, infb_f_r, qnan_r_b, snan_r_b;
reg inf, ind, qnan, snan; // Output registers
reg opa_nan, opb_nan;
reg expa_00, expb_00, fracta_00, fractb_00;
reg opa_00, opb_00;
reg opa_inf, opb_inf;
reg opa_dn, opb_dn;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Determine if any of the input operators is a INF or NAN or any other special number
//
always @(posedge clk)
expa_ff <= &expa;
always @(posedge clk)
expb_ff <= &expb;
always @(posedge clk)
infa_f_r <= !(|fracta);
always @(posedge clk)
infb_f_r <= !(|fractb);
always @(posedge clk)
qnan_r_a <= fracta[22];
always @(posedge clk)
snan_r_a <= !fracta[22] & |fracta[21:0];
always @(posedge clk)
qnan_r_b <= fractb[22];
always @(posedge clk)
snan_r_b <= !fractb[22] & |fractb[21:0];
always @(posedge clk)
ind <= (expa_ff & infa_f_r) & (expb_ff & infb_f_r);
always @(posedge clk)
inf <= (expa_ff & infa_f_r) | (expb_ff & infb_f_r);
always @(posedge clk)
qnan <= (expa_ff & qnan_r_a) | (expb_ff & qnan_r_b);
always @(posedge clk)
snan <= (expa_ff & snan_r_a) | (expb_ff & snan_r_b);
always @(posedge clk)
opa_nan <= &expa & (|fracta[22:0]);
always @(posedge clk)
opb_nan <= &expb & (|fractb[22:0]);
always @(posedge clk)
opa_inf <= (expa_ff & infa_f_r);
always @(posedge clk)
opb_inf <= (expb_ff & infb_f_r);
always @(posedge clk)
expa_00 <= !(|expa);
always @(posedge clk)
expb_00 <= !(|expb);
always @(posedge clk)
fracta_00 <= !(|fracta);
always @(posedge clk)
fractb_00 <= !(|fractb);
always @(posedge clk)
opa_00 <= expa_00 & fracta_00;
always @(posedge clk)
opb_00 <= expb_00 & fractb_00;
always @(posedge clk)
opa_dn <= expa_00;
always @(posedge clk)
opb_dn <= expb_00;
endmodule
| 6.521738 |
module mul_r2 (
clk,
opa,
opb,
prod
);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk) prod1 <= opa * opb;
always @(posedge clk) prod <= prod1;
endmodule
| 6.757243 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module core =============================
module core (
inout va,
inout vb,
inout VSS,
inout VDD
);
wire vbneg, l6, l7, l8, l10, l11;
// supply0 ground;
cap_array C2 (
.Cin(va),
.Cout(VSS)
);
resistor R6 (
.rin(va),
.rout(l6)
);
resistor R7 (
.rin(l6),
.rout(l7)
);
resistor R8 (
.rin(l7),
.rout(l8)
);
resistor R10 (
.rin(l8),
.rout(l10)
);
resistor R11 (
.rin(l10),
.rout(l11)
);
sky130_asc_res_xhigh_po_2p85_2 R9 (
.Rin(l11),
.Rout(VSS)
);
sky130_asc_pnp_05v5_W3p40L3p40_1 pnp_va (
.Emitter(va),
.Base(VSS),
.Collector(VSS)
);
resistor R3 (
.rin(vb),
.rout(vbneg)
);
pnp_array pnp_vb (
.emitter(vbneg),
.base(VSS)
);
wire l1, l2, l4, l5, l12;
resistor R1 (
.rin(vb),
.rout(l1)
);
resistor R2 (
.rin(l1),
.rout(l2)
);
resistor R4 (
.rin(l2),
.rout(l4)
);
resistor R5 (
.rin(l4),
.rout(l5)
);
resistor R12 (
.rin(l5),
.rout(l12)
);
sky130_asc_res_xhigh_po_2p85_2 R13 (
.Rin(l12),
.Rout(VSS)
);
endmodule
| 6.816929 |
module bg_display (
input clk,
input clk2,
input vsync,
input blank,
output reg [11:0] pixel_out
);
reg [17:0] bg_addr = 0;
wire [ 7:0] bg_data;
blk_mem_gen_0 bg_mem (
.clka(clk2), // input wire clka
.addra(bg_addr), // input wire [17 : 0] addra
.douta(bg_data) // output wire [7 : 0] douta
);
reg [ 5:0] current_idx = 0;
reg [ 1:0] current_run_left = 0;
wire [11:0] pixel;
dist_mem_gen_1 bg_colors (
.a(current_idx), // input wire [5 : 0] addra
.spo(pixel) // output wire [11 : 0] douta
);
always @(posedge clk) begin
if (~blank) begin
if (current_run_left == 0) begin
bg_addr <= bg_addr + 1;
current_idx <= bg_data[5:0];
current_run_left <= bg_data[7:6];
end else begin
current_run_left <= current_run_left - 1;
end
pixel_out <= pixel;
end else pixel_out <= 12'b0;
if (~vsync) begin
bg_addr <= 0;
current_run_left <= 0;
current_idx <= 0;
end
end
/*
ila_0 lifesaver (
.clk(clk), // input wire clk
.probe0(hcount), // input wire [10:0] probe0
.probe1(vcount), // input wire [9:0] probe1
.probe2(blank), // input wire [0:0] probe2
.probe3(bg_addr), // input wire [17:0] probe3
.probe4(bg_data), // input wire [7:0] probe4
.probe5(pixel), // input wire [11:0] probe5
.probe6(current_idx), // input wire [1:0] probe6
.probe7(current_run_left) // input wire [0:0] probe7
);*/
endmodule
| 6.658027 |
module bg_gen #(
MEMFILE = "over.mem",
PALETTE = "over_palette.mem"
) (
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS, // horizontal sync output
output wire VGA_VS, // vertical sync output
output reg [3:0] VGA_R, // 4-bit VGA red output
output reg [3:0] VGA_G, // 4-bit VGA green output
output reg [3:0] VGA_B // 4-bit VGA blue output
);
wire rst = ~RST_BTN; // reset is active low on Arty & Nexys Video
// wire rst = RST_BTN; // reset is active high on Basys3 (BTNC)
// generate a 25 MHz pixel strobe
reg [15:0] cnt;
reg pix_stb;
always @(posedge CLK) {pix_stb, cnt} <= cnt + 16'h4000; // divide by 4: (2^16)/4 = 0x4000
wire [9:0] x; // current pixel x position: 10-bit value: 0-1023
wire [8:0] y; // current pixel y position: 9-bit value: 0-511
wire active; // high during active pixel drawing
vga640x480 display (
.i_clk(CLK),
.i_pix_stb(pix_stb),
.i_rst(rst),
.o_hs(VGA_HS),
.o_vs(VGA_VS),
.o_x(x),
.o_y(y),
.o_active(active)
);
// VRAM frame buffers (read-write)
localparam SCREEN_WIDTH = 640;
localparam SCREEN_HEIGHT = 480;
localparam VRAM_DEPTH = SCREEN_WIDTH * SCREEN_HEIGHT;
localparam VRAM_A_WIDTH = 18; // 2^19 > 640 x 480
localparam VRAM_D_WIDTH = 6; // colour bits per pixel
reg [VRAM_A_WIDTH-1:0] address;
wire [VRAM_D_WIDTH-1:0] dataout;
sram #(
.ADDR_WIDTH(VRAM_A_WIDTH),
.DATA_WIDTH(VRAM_D_WIDTH),
.DEPTH(VRAM_DEPTH),
.MEMFILE(MEMFILE)
) // bitmap to load
vram (
.i_addr(address),
.i_clk(CLK),
.i_write(0), // we're always reading
.i_data(0),
.o_data(dataout)
);
reg [11:0] palette[0:63]; // 64 x 12-bit colour palette entries
reg [11:0] colour;
initial begin
$display("Loading palette.");
$readmemh(PALETTE, palette); // bitmap palette to load
end
always @(posedge CLK) begin
address <= y * SCREEN_WIDTH + x;
if (active) colour <= palette[dataout];
else colour <= 0;
VGA_R <= colour[11:8];
VGA_G <= colour[7:4];
VGA_B <= colour[3:0];
end
endmodule
| 7.297259 |
module bg_rom (
clk,
video_on,
x,
y,
color
);
parameter ROM_WIDTH = 12;
parameter ROM_ADDR_BITS = 14;
(* rom_style="block" *)
reg [ROM_WIDTH-1:0] rom[(2**ROM_ADDR_BITS)-1:0];
input wire clk;
input wire video_on;
input wire [6:0] x;
input wire [6:0] y;
reg [ROM_ADDR_BITS-1:0] address;
output reg [ROM_WIDTH-1:0] color;
initial $readmemh("bg_rom.hex", rom);
always @(posedge clk)
if (video_on) begin
address <= {y, x};
color <= rom[address];
end
endmodule
| 6.68994 |
module bg_rom (
input clk,
input resetn,
input start,
output [7:0] x,
output [6:0] y,
output [2:0] c_out,
output done
);
wire ld_all, enable;
datapath_back d0 (
.clk(clk),
.resetn(resetn),
.ld_all(ld_all),
.enable(enable),
.x(x),
.y(y),
.c_out(c_out)
);
control_back c0 (
.clk(clk),
.resetn(resetn),
.start(start),
.ld_all(ld_all),
.enable(enable),
.done (done)
);
endmodule
| 6.68994 |
module datapath_back (
input clk,
input resetn,
input ld_all,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output reg [2:0] c_out
);
reg [7:0] x_hold;
reg [6:0] y_hold;
reg [2:0] c_hold;
reg [14:0] address;
reg [7:0] x_address;
reg [6:0] y_address;
reg double;
wire [2:0] colour;
// Registers x, y, c with respective input logic
always @(posedge clk) begin
if (!resetn) begin
x <= 8'd0;
y <= 7'd0;
c_out <= 3'd0;
end else if (enable) begin
x <= x_address;
y <= y_address;
c_out <= colour;
end
end
always @(posedge clk) begin : address_counter
if (!resetn | !enable) begin
x_address <= 8'd0;
y_address <= 7'd0;
address <= 15'd0;
double <= 1'd0;
end else if (enable) begin
if (double == 1'd1) begin
double <= 1'd0;
end else if (address == 15'd19199) begin
x_address <= 8'd0;
y_address <= 7'd0;
address <= 15'd0;
double <= 1'd1;
end else if (x_address == 8'd159) begin
x_address <= 8'd0;
y_address <= y_address + 1'd1;
address <= address + 1'd1;
double <= 1'd1;
end else begin
x_address <= x_address + 1'd1;
address <= address + 1'd1;
double <= 1'd1;
end
end
end // address
back_rom b0 (
.address(address),
.clock (clk),
.q(colour)
);
endmodule
| 6.991902 |
module control_back (
input clk,
input resetn,
input start,
output reg ld_all,
output reg enable,
output reg done
);
reg [4:0] current_state, next_state;
reg [15:0] counter;
wire wait_plot = (counter > 16'd40000);
localparam S_DRAW = 5'd0, S_DONE = 5'd1, S_INITIAL = 5'd2, S_START = 5'd3, S_START_WAIT = 5'd4;
// Next state logic aka our state table for plotting
always @(*) begin : state_table
case (current_state)
S_INITIAL: next_state = start ? S_DRAW : S_INITIAL; // Loads initial x position
S_START: next_state = start ? S_DRAW : S_START;
S_DRAW: next_state = wait_plot ? S_DONE : S_DRAW;
S_DONE: next_state = S_START;
default: next_state = S_INITIAL;
endcase
end // state_table
// Output logic aka all of our datapath control signals
always @(*) begin : enable_signals
// By default make all our signals 0
ld_all = 1'b0;
enable = 1'b0;
done = 1'b0;
case (current_state)
S_INITIAL: begin
ld_all = 1'b1;
end
S_DRAW: begin
enable = 1'b1;
end
S_DONE: begin
done = 1'b1;
end
default: enable = 1'b0;
endcase
end
always @(posedge clk) begin : sixteen_counter
if (!resetn | !enable) begin
counter <= 16'd0;
end else begin
counter <= counter + 16'd1;
end
end // counter
// current_state registers
always @(posedge clk) begin : state_FFs
if (!resetn) begin
current_state <= S_INITIAL;
end else begin
current_state <= next_state;
end
end // state_FFS
endmodule
| 8.162269 |
module bg_rom2 (
input clk,
input resetn,
input start,
output [7:0] x,
output [6:0] y,
output [2:0] c_out,
output done
);
wire ld_all, enable;
datapath_end d0 (
.clk(clk),
.resetn(resetn),
.ld_all(ld_all),
.enable(enable),
.x(x),
.y(y),
.c_out(c_out)
);
control_end c0 (
.clk(clk),
.resetn(resetn),
.start(start),
.ld_all(ld_all),
.enable(enable),
.done (done)
);
endmodule
| 6.7 |
module control_end (
input clk,
input resetn,
input start,
output reg ld_all,
output reg enable,
output reg done
);
reg [4:0] current_state, next_state;
reg [15:0] counter;
wire wait_plot = (counter > 16'd40000);
localparam S_DRAW = 5'd0, S_DONE = 5'd1, S_INITIAL = 5'd2, S_START = 5'd3, S_START_WAIT = 5'd4;
// Next state logic aka our state table for plotting
always @(*) begin : state_table
case (current_state)
S_INITIAL: next_state = start ? S_DRAW : S_INITIAL; // Loads initial x position
S_START: next_state = start ? S_DRAW : S_START;
S_DRAW: next_state = wait_plot ? S_DONE : S_DRAW;
S_DONE: next_state = S_START;
default: next_state = S_INITIAL;
endcase
end // state_table
// Output logic aka all of our datapath control signals
always @(*) begin : enable_signals
// By default make all our signals 0
ld_all = 1'b0;
enable = 1'b0;
done = 1'b0;
case (current_state)
S_INITIAL: begin
ld_all = 1'b1;
end
S_DRAW: begin
enable = 1'b1;
end
S_DONE: begin
done = 1'b1;
end
default: enable = 1'b0;
endcase
end
always @(posedge clk) begin : sixteen_counter
if (!resetn | !enable) begin
counter <= 16'd0;
end else begin
counter <= counter + 16'd1;
end
end // counter
// current_state registers
always @(posedge clk) begin : state_FFs
if (!resetn) begin
current_state <= S_INITIAL;
end else begin
current_state <= next_state;
end
end // state_FFS
endmodule
| 7.40965 |
module: four_beat_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_four_beat_generator;
// Inputs
reg clk;
reg rst;
// Outputs
wire [3:0] t;
// Instantiate the Unit Under Test (UUT)
four_beat_generator uut (
.clk(clk),
.rst(rst),
.t(t)
);
always #5 clk=~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
#1 rst=1;
#1 rst=0;
# 1000 $finish;
// Wait 100 ns for global rst to finis
// Add stimulus here
end
endmodule
| 7.080669 |
module
// Author: WangFW
// Created on 2020-11-6
//----------------------------------------------------------------
// Date: 2020-11-8
// Add read data part and led control
//----------------------------------------------------------------
module BH(
input sys_clk,
input sys_rst_n,
input key,
input uart_rxd,
output ATK_KEY,
output uart_txd,
output [3:0] led
);
//-----------------------------------------
// Parameters definition
//-----------------------------------------
wire enable;
wire [7:0] data;
wire [7:0] recv_data;
wire uart_done;
assign ATK_KEY = 1'b0;
//-----------------------------------------
// Module connect
//-----------------------------------------
uart_send_source src1(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.key(key),
.enable(enable),
.dout(data)
);
uart_send send1(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.uart_en(enable),
.uart_din(data),
.uart_txd(uart_txd)
);
uart_recv(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.uart_rxd(uart_rxd),
.uart_done(uart_done),
.uart_data(recv_data)
);
uart_led(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.data(recv_data),
.led(led)
);
endmodule
| 8.549649 |
module bhand_cycle_count # (
parameter DATA_WIDTH = 8,
parameter ENABLE_COUNT = 0,
parameter COUNT_WIDTH = 4
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] idata,
input wire idata_vld,
output wire idata_rdy,
output wire [DATA_WIDTH-1:0] odata,
output wire odata_vld,
input wire odata_rdy,
//Counting signals. Ignore these ports if ENABLE_COUNT == 0
input wire cnt_en,
input wire [COUNT_WIDTH-1:0] icount,
output wire [COUNT_WIDTH-1:0] ocount
);
//Some helper signals for neatening up the code
wire shift_in;
assign shift_in = idata_vld && idata_rdy;
wire shift_out;
assign shift_out = odata_vld && odata_rdy;
//Forward-declare this signal since extra_mem needs it
reg mem_vld = 0;
//Internal registers and signals for extra element
reg [DATA_WIDTH-1:0] extra_mem = 0;
reg extra_mem_vld = 0;
wire extra_mem_rdy;
//Unlike a regular FIFO, we are only ready if empty:
assign extra_mem_rdy = (extra_mem_vld == 0);
//We will enable writing into extra mem if a new element is shifting in AND
//mem is full AND mem will not be read on this cycle
wire extra_mem_en;
assign extra_mem_en = shift_in && mem_vld && !shift_out;
always @(posedge clk) begin
//extra_mem_vld's next value
if (rst) begin
extra_mem_vld <= 0;
end else begin
if (extra_mem_en) begin
extra_mem_vld <= 1;
end else if (shift_out) begin
extra_mem_vld <= 0;
end
end
//extra_mem's next value
if (extra_mem_en) begin
extra_mem <= idata;
end
end
//Internal registers and signals for FIFO element
reg [DATA_WIDTH-1:0] mem = 0;
//reg mem_vld = 0; //moved
wire mem_rdy;
//We are ready if FIFO is empty, or if the value is leaving on this cycle
assign mem_rdy = !mem_vld || (odata_vld && odata_rdy);
//We will enable writing into mem if it is ready, and if the input is valid
wire mem_en;
assign mem_en = mem_rdy && (idata_vld || extra_mem_vld);
always @(posedge clk) begin
//mem_vld's next value
if (rst) begin
mem_vld <= 0;
end else begin
if (mem_en) begin
mem_vld <= 1;
end else if (shift_out) begin
mem_vld <= 0;
end
end
//mem's next value
if (mem_en) begin
mem <= extra_mem_vld ? extra_mem : idata;
end
end
`genif(ENABLE_COUNT) begin
//Declare internal registers
reg [COUNT_WIDTH-1:0] extra_cnt_reg = 0;
reg [COUNT_WIDTH-1:0] cnt_reg = 0;
//extra_cnt_reg
always @(posedge clk) begin
if (rst) begin
extra_cnt_reg <= 0;
end else begin
if (extra_mem_en) begin
extra_cnt_reg <= icount + cnt_en;
end else begin
extra_cnt_reg <= extra_cnt_reg + cnt_en;
end
end
end
//cnt_reg
always @(posedge clk) begin
if (rst) begin
cnt_reg <= 0;
end else begin
if (mem_en) begin
cnt_reg <= extra_mem_vld ? extra_cnt_reg + cnt_en : icount + cnt_en;
end else begin
cnt_reg <= cnt_reg + cnt_en;
end
end
end
//Wire up outputs
assign ocount = cnt_reg;
`endgen
//Actually wire up module outputs
assign idata_rdy = extra_mem_rdy;
assign odata = mem;
assign odata_vld = mem_vld;
endmodule
| 7.221304 |
module BHT #(
parameter SET_LEN = 12,
parameter BITS = 2
) (
input clk,
rst,
input [31:0] PC_query,
PC_update,
input BR,
update,
output BHT_br
);
localparam SET_SIZE = 1 << SET_LEN;
localparam MAX_VAL = (1 << BITS) - 1;
localparam THRESHOD = MAX_VAL / 2;
reg [BITS-1 : 0] STATE[0 : SET_SIZE-1];
wire [SET_LEN-1 : 0] query_addr, update_addr;
assign query_addr = PC_query[SET_LEN-1 : 0];
assign update_addr = PC_update[SET_LEN-1 : 0];
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i = 0; i < SET_SIZE; i = i + 1) begin
STATE[i] <= 0;
end
end else begin
if (update) begin
if (BR == 1) begin
STATE[update_addr] <= (STATE[update_addr] == MAX_VAL) ? STATE[update_addr] : STATE[update_addr] + 1;
end else begin
STATE[update_addr] <= (STATE[update_addr] == 0) ? STATE[update_addr] : STATE[update_addr] - 1;
end
end
end
end
assign BHT_br = (STATE[query_addr] > THRESHOD) ? 1'b1 : 1'b0;
endmodule
| 7.276164 |
module BhtLRU (
clk,
rst_n,
touch_en,
touch_item,
lru_item
);
parameter NItem = 8;
input clk, rst_n, touch_en;
input [NItem - 1:0] touch_item;
output [NItem - 1:0] lru_item;
reg [NItem - 1:0] stack[NItem - 1:0];
wire [NItem - 1:1] hit;
assign lru_item = stack[NItem-1];
generate
genvar i;
for (i = 1; i < NItem; i = i + 1) begin
assign hit[i] = touch_item == stack[i];
end
always @(posedge clk, negedge rst_n) begin
if (!rst_n) stack[0] <= 1;
else if (touch_en) stack[0] <= touch_item;
end
for (i = 1; i < NItem; i = i + 1) begin
always @(posedge clk, negedge rst_n) begin
if (!rst_n) stack[i] <= 1 << i;
else if (touch_en && hit[NItem-1:i] != 0) stack[i] <= stack[i-1];
end
end
endgenerate
endmodule
| 6.958218 |
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