code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module beta_read_decode (
input wire clk,
input wire [2:0] read_select, //need to pipeline
input wire [31:0] ram_dout,
input wire [31:0] IO_dout,
input wire [31:0] shared_read_dout,
input wire [31:0] shared_write_dout,
output reg [31:0] beta_mdin = 0
);
reg [2:0] old_read_select = 0;
... | 8.210318 |
module ascii_input (
input clk25, // 25MHz clock
input rst, // active high reset
input enable, // active high reset
// I/O interface to virtual disk
input ioctl_download,
//output reg ioctl_wait,
output ioctl_wait,
input [ 7:0] ioctl_data,
input [13:0] ioctl... | 7.377676 |
module BET_FSM (
clk_50,
rst,
// ram (BET) ports
ram_addr,
ram_r,
ram_w,
ram_w_en,
// garbage collection ports
garbage_en,
garbage_state,
garbage_addr
);
parameter T = 100;
parameter BET_size = 8192;
parameter cmp_ratio = 3'd0,
cmp_flag_count = 3'd1,
... | 6.756887 |
module top (
input clk_i,
input rst_i,
output halt
);
if_wb rambus ();
if_wb cpubus ();
bexkat1p cpu0 (
.clk_i(clk_i),
.rst_i(rst_i),
.bus(cpubus.master),
.halt(halt),
.inter(inter),
.exception(exception),
.supervisor(supervisor),
.int_en(int_en)
);... | 7.233807 |
module bextdep64g3 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
... | 7.501649 |
module bextdep64p3 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
... | 7.449698 |
module bextdep64g2 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
... | 7.189357 |
module bextdep64p2 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
... | 7.21886 |
module bextdep64g1 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
... | 7.029467 |
module bextdep64p1 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_pipeline #(
... | 7.068791 |
module bextdep32g3 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
... | 7.234018 |
module bextdep32p3 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
... | 7.195055 |
module bextdep32g2 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
... | 6.84396 |
module bextdep32p2 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
... | 6.895214 |
module bextdep32g1 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
... | 6.703706 |
module bextdep32p1 (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_pipeline #(
... | 6.850681 |
module bextdep64sh (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_seq #(
... | 7.102412 |
module bextdep64sb (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_seq #(
... | 7.812095 |
module bextdep64sn (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_seq #(
... | 7.434055 |
module bextdep32sb (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_seq #(
... | 7.488141 |
module bextdep32sn (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_seq #(
... | 7.266771 |
module bextdep_xlen_seq #(
parameter integer XLEN = 32,
parameter integer STEPS = 2
) (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [XLEN-1:0] din_value,
input [XLEN-1:0] din_mask,
output do... | 7.252398 |
module bextdep_direct #(
parameter integer XLEN = 32,
parameter integer SUMBITS = 8
) (
input din_mode,
input [ XLEN-1:0] din_value,
input [ XLEN-1:0] din_mask,
output [ XLEN-1:0] dout_result,
output [SUMBITS-1:0] dout_sum
);
wire [XLEN/2-1:0] decoder_s1, decoder_s2,... | 6.960414 |
module bextdep64sx (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_sx #(
... | 7.659199 |
module bextdep32sx (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_sx #(
... | 7.51903 |
module bextdep_xlen_sx #(
parameter integer XLEN = 32
) (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [XLEN-1:0] din_value,
input [XLEN-1:0] din_mask,
output dout_valid,
input dou... | 7.252398 |
module bextdep64go (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [63:0] din_value,
input [63:0] din_mask,
output dout_valid,
input dout_ready,
output [63:0] dout_result
);
bextdep_xlen_go #(
... | 6.886903 |
module bextdep32go (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [31:0] din_value,
input [31:0] din_mask,
output dout_valid,
input dout_ready,
output [31:0] dout_result
);
bextdep_xlen_go #(
... | 6.727231 |
module bextdep_xlen_go #(
parameter integer XLEN = 32,
parameter integer MAXK = 5,
parameter integer MAXI = 16
) (
input clock,
input reset,
input din_valid,
output din_ready,
input [ 1:0] din_mode,
input [XLEN-1:0] din_value,
input [XLEN-1:0] din_m... | 7.252398 |
module bextdep_lrotcz #(
parameter integer N = 1,
parameter integer M = 1
) (
input [ 7:0] din,
output [M-1:0] dout
);
wire [2*M-1:0] mask = {M{1'b1}};
assign dout = (mask << din[N-1:0]) >> M;
endmodule
| 7.126218 |
module bextdep_butterfly_fwd #(
parameter integer XLEN = 32,
parameter integer FFSTAGE = 1
) (
input [ XLEN-1:0] din,
input [XLEN/2-1:0] s1,
s2,
s4,
s8,
s16,
s32,
output [ XLEN-1:0] dout
);
reg [XLEN-1:0] butterfly;
assign dout = butterfly;
integer k, i;
always @* be... | 7.237255 |
module bextdep_butterfly_bwd #(
parameter integer XLEN = 32,
parameter integer FFSTAGE = 1
) (
input [ XLEN-1:0] din,
input [XLEN/2-1:0] s1,
s2,
s4,
s8,
s16,
s32,
output [ XLEN-1:0] dout
);
reg [XLEN-1:0] butterfly;
assign dout = butterfly;
integer k, i;
always @* be... | 7.237255 |
module bextdep_pps4 (
input [ 3:0] din,
output [31:0] dout
);
function [15:0] carry_save_add;
input [15:0] a, b;
reg [7:0] x, y;
begin
x = a[15:8] ^ a[7:0] ^ b[7:0];
y = ((a[15:8] & a[7:0]) | (a[15:8] & b[7:0]) | (a[7:0] & b[7:0])) << 1;
carry_save_add[7:0] = x ^ y ^ b[15:8];
... | 6.852607 |
module bextdep_pps8 (
input [ 7:0] din,
output [63:0] dout
);
function [15:0] carry_save_add;
input [15:0] a, b;
reg [7:0] x, y;
begin
x = a[15:8] ^ a[7:0] ^ b[7:0];
y = ((a[15:8] & a[7:0]) | (a[15:8] & b[7:0]) | (a[7:0] & b[7:0])) << 1;
carry_save_add[7:0] = x ^ y ^ b[15:8];
... | 6.822596 |
module BF (
input a,
input b,
input c,
output out1,
output out2,
output out3,
output out4
);
assign out1 = ((~a) || (~b)) && (~c);
assign out2 = ~((a && b) || c);
assign out3 = ((~a) && (~b)) || (~c);
assign out4 = ~((a || b) && c);
endmodule
| 7.246855 |
module bf1 #(
parameter WIDTH = 17
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WID... | 7.073333 |
module bf16 #(
parameter WIDTH = 13
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WI... | 8.21675 |
module bf2 #(
parameter WIDTH = 17
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WID... | 7.01775 |
module tb ();
reg clk;
reg serial_in;
wire serial_out;
initial begin
$dumpfile("bf2hw.vcd");
$dumpvars;
clk <= 1'b0;
serial_in <= 1'b1;
#1000;
serial_in <= 1'b0;
#1041666;
serial_in <= 1'b1;
#15000000;
$finish;
end
always #20.67 clk = !clk;
bf2hw_top dut (
... | 7.195167 |
module instantiating BAMBU generated hardware
//
module bf2hw_top(input clk12, input SERIAL_RX, output SERIAL_TX);
`define D_BAUD_FREQ 12'd4
`define D_BAUD_LIMIT 16'd621
wire TX_BUSY;
wire TX_WRITE;
wire RX_VALID;
wire [7:0] RX_DATA;
wire [7:0] TX_DATA;
wire TX_READY;
... | 7.016079 |
module bf32 #(
parameter WIDTH = 11
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WI... | 7.547757 |
module bf4 #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WID... | 7.770008 |
module bf8 #(
parameter WIDTH = 14
) (
input [WIDTH-1:0] data_in_0_re,
input [WIDTH-1:0] data_in_0_im,
input [WIDTH-1:0] data_in_1_re,
input [WIDTH-1:0] data_in_1_im,
output [WIDTH-1:0] data_out_0_re,
output [WIDTH-1:0] data_out_0_im,
output [WIDTH-1:0] data_out_1_re,
output [WID... | 8.680949 |
module BFA (
a,
b,
cin,
sum,
cout
);
input a, b, cin;
output sum, cout;
assign cout = (a && b) || (b && cin) || (a && cin);
assign sum = a ^ b ^ cin;
endmodule
| 7.572097 |
module bfloat_adder_8 (
input clk,
input resetn,
input en,
input stall,
input [8-1:0] a,
input [8-1:0] b,
output reg [8-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en) out <= a + b;
end
endmodule
| 6.882044 |
module bfloat_mult_8 (
input clk,
input resetn,
input en,
input stall,
input [8-1:0] a,
input [8-1:0] b,
output reg [8-1:0] out
);
always @(posedge clk) begin
if (!resetn) out <= 'h0;
else if (en) out <= a * b;
end
endmodule
| 7.144967 |
module bfm ();
bit clk;
always #4 clk = ~clk;
import "DPI-C" context function void init();
export "DPI-C" function set_data;
import "DPI-C" context function void get_data();
export "DPI-C" function finalize;
import "DPI-C" context function void kill();
bit input_valid;
bit ready;
bit final_en;
... | 7.232006 |
module BFM_AHBSLAVE (
HCLK,
HRESETN,
HSEL,
HWRITE,
HADDR,
HWDATA,
HRDATA,
HREADYIN,
HREADYOUT,
HTRANS,
HSIZE,
HBURST,
HMASTLOCK,
HPROT,
HRESP
);
parameter AWIDTH = 10;
parameter DEPTH = 256;
parameter INITFILE = " ";
parameter ID = 0;
parameter ENFUN... | 6.859666 |
module bfm_ahb (
input wire SYS_CLK_STABLE
, input wire SYS_CLK // master clock and goes to SL_PCLK
, output wire SYS_RST_N // by-pass of SL_RST_N
, input wire SL_RST_N
, output wire SL_CS_N
, output wire SL_PCLK // by-pass of ... | 7.135272 |
module bfm_apb_s1 #(
parameter P_ADDR_START0 = 16'h0000,
P_ADDR_SIZE0 = 16'h0010
) (
input wire PRESETn
, input wire PCLK
, output reg PSEL
, output reg [31:0] PADDR
, output reg PENABLE
, output reg PWRITE
, output reg [31:0] PWDATA
, ... | 7.029573 |
module bfm_apb_s3
#(parameter P_DWIDTH=32
, P_STRB =(P_DWIDTH/8)
, P_NUM=3
, P_ADDR_START0 = 16'h0000, P_ADDR_SIZE0 = 16'h0010
, P_ADDR_START1 = 16'h1000, P_ADDR_SIZE1 = 16'h0010
, P_ADDR_START2 = 16'h2000, P_ADDR_SIZE2 = 16'h0010)
(
... | 7.274574 |
module bfm_axi (
input wire SYS_CLK_STABLE
, input wire SYS_CLK // master clock and goes to SL_PCLK
, output wire SYS_RST_N // by-pass of SL_RST_N
, input wire SL_RST_N
, output wire SL_CS_N
, output wire SL_PCLK // by-pass of ... | 6.53215 |
module bfm_axi (
input wire SYS_CLK_STABLE
, input wire SYS_CLK // master clock and goes to SL_PCLK
, output wire SYS_RST_N // by-pass of SL_RST_N
, input wire SL_RST_N
, output wire SL_CS_N
, output wire SL_PCLK // by-pass of ... | 6.53215 |
module adder32 (
clk,
rst,
A,
B,
O
);
input [31:0] A, B;
input clk;
input rst;
output reg [31:0] O;
wire a_sign;
wire b_sign;
wire [7:0] a_exponent;
wire [7:0] b_exponent;
wire [23:0] a_mantissa; // plus one bit
wire [23:0] b_mantissa; // plus one bit
reg o_sign;
reg [7... | 8.194085 |
module generalAdder (
a,
b,
out
);
input [31:0] a, b;
output [31:0] out;
wire [31:0] out;
reg a_sign;
reg b_sign;
reg [7:0] a_exponent;
reg [7:0] b_exponent;
reg [23:0] a_mantissa;
reg [23:0] b_mantissa;
reg o_sign;
reg [7:0] o_exponent;
reg [24:0] o_mantissa;
reg [7:0] diff;
... | 7.143472 |
module bfproc #(
parameter W2 = 17, // Multiplier bit width
W1 = 9, // Bit width c+s sum
W = 8
) // Input bit width
(
input clk, // Clock for the output register
input signed [ W-1:0] Are_in,
Aim_in, // 8-bit inputs
input signed [ W-1:0] Bre_in,
B... | 6.841971 |
module info begin__
// name : krnl
// function :
// inputs : in_data, weight
// outputs : out_data
// document :
// __module info end__
module bfp_krnl
# (
// The parallism in channel direction
parameter pc = 64,
// The data width of input data
parameter in_data_width=8,
// The data width utilized... | 8.53714 |
module bfs_pipeline (
clk,
rst,
last_input_in,
word_in,
word_in_valid,
word_in_th,
control,
current_level,
last_input_out,
control_out,
word_out,
valid_out,
word_in_valid_out,
word_in_th_out
);
parameter ADDR_W = 4; // this value decides how many vertices in a... | 7.652256 |
module gen_nw32 #(
parameter num_leaves = 32,
parameter payload_sz = $clog2(num_leaves) + 4,
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr = 1'b0,
parameter level = 0
) (
input clk,
input reset,
input [p_sz*32-1:0] pe_interface,
output [p_sz*32-1... | 8.389133 |
module _2121subtree #(
parameter num_leaves = 32,
parameter payload_sz = $clog2(num_leaves) + 4,
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr = 1'b0,
parameter level = 1
) (
input clk,
input reset,
input [p_sz*16-1:0] pe_interface,
output [p_sz*... | 7.335251 |
module _212subtree #(
parameter num_leaves = 32,
parameter payload_sz = $clog2(num_leaves) + 4,
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr = 2'b00,
parameter level = 2
) (
input clk,
input reset,
input [p_sz*8-1:0] pe_interface,
output [p_sz*8... | 7.317172 |
module _21subtree #(
parameter num_leaves = 32,
parameter payload_sz = $clog2(num_leaves) + 4,
parameter p_sz = 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr = 3'b000,
parameter level = 3
) (
input clk,
input reset,
input [p_sz*4-1:0] pe_interface,
output [p_sz*4... | 6.97855 |
module _2subtree # (
parameter num_leaves= 32,
parameter payload_sz= $clog2(num_leaves) + 4,
parameter p_sz= 1 + $clog2(num_leaves) + payload_sz, //packet size
parameter addr= 4'b0000,
parameter level= 4
) (
input clk,
input reset,
input [p_sz*2-1:0] pe_interface,
output [p_sz*2-1:0] interface_pe,
output [2-... | 7.423772 |
module pipe_ff (
input clk,
input reset,
input [data_width-1:0] din,
output reg [data_width-1:0] dout
);
parameter data_width = 2;
always @(posedge clk) begin
if (reset) dout <= 0;
else dout <= din;
end
endmodule
| 8.069914 |
module pi_cluster (
input clk,
input reset,
input [num_switches*p_sz-1:0] l_bus_i,
input [num_switches*p_sz-1:0] r_bus_i,
input [2*num_switches*p_sz-1:0] u_bus_i,
output [num_switches*p_sz-1:0] l_bus_o,
output [num_switches*p_sz-1:0] r_bus_o,
output [2*num_switches*p_sz-1:0] u_bus_o
);
... | 8.597644 |
module pi_switch (
input clk,
input reset,
input [p_sz-1:0] l_bus_i,
input [p_sz-1:0] r_bus_i,
input [p_sz-1:0] ul_bus_i,
input [p_sz-1:0] ur_bus_i,
output reg [p_sz-1:0] l_bus_o,
output reg [p_sz-1:0] r_bus_o,
output reg [p_sz-1:0] ul_bus_o,
output reg [p_sz-1:0] ur_bus_o
);
/... | 8.128678 |
module t_arbiter(
input [1:0] d_l,
input [1:0] d_r,
input [1:0] d_u,
output reg [1:0] sel_l,
output reg [1:0] sel_r,
output reg [1:0] sel_u
);
parameter level= 1;
/*
* d_l, d_r, d_u designate where the specific packet from a certain
* direction would like to (ideally go).
* d_{l,r,u}=00, non-valid packet.... | 7.262206 |
module t_cluster (
input clk,
input reset,
input [num_switches*p_sz-1:0] l_bus_i,
input [num_switches*p_sz-1:0] r_bus_i,
input [num_switches*p_sz-1:0] u_bus_i,
output [num_switches*p_sz-1:0] l_bus_o,
output [num_switches*p_sz-1:0] r_bus_o,
output [num_switches*p_sz-1:0] u_bus_o
);
// O... | 8.876029 |
module t_switch (
input clk,
input reset,
input [p_sz-1:0] l_bus_i,
input [p_sz-1:0] r_bus_i,
input [p_sz-1:0] u_bus_i,
output reg [p_sz-1:0] l_bus_o,
output reg [p_sz-1:0] r_bus_o,
output reg [p_sz-1:0] u_bus_o
);
// Override these values in top modules
parameter num_leaves = 2;
p... | 7.748937 |
module bfu_model (
clk,
rstn,
in1,
in2,
gamma,
op,
p,
R_1,
mm_out_golden,
ms_out_golden,
ma_out_golden,
out1_golden,
out2_golden
);
input wire clk;
input wire rstn;
input wire [`datawidth-1:0] in1;
input wire [`datawidth-1:0] in2;
input wire [`datawidth... | 7.583505 |
module bfu_v1 (
input clk,
input rstn,
input [`datawidth-1:0] in1,
input [`datawidth-1:0] in2,
input [`datawidth-1:0] gamma, //required by BF
input op,
input [`datawidth-1:0] p,
input [`datawidth-1:0] _p,
input [`datawidth-1:0] mu, //required by mml
output [`datawidth-1:0] o... | 6.885831 |
module bf_2_2_stage
# (
parameter DATA_WIDTH = 32,
STAGE_ORDER = 0, // 说明是第几级stage
IS_PIPED = 1
)
(
input wire clk,
// input wire rst,
input wire [DATA_WIDTH/2-1:0] ... | 7.285304 |
module
//////////////////////////////////////////////////////////////////////////////////
module bf_addr(
input [3:0] layer_num,
input [7:0] bf_num,
output [8:0] addr_a,
output [8:0] addr_pair
);
reg [8:0] addr_a_reg, addr_pair_reg;
assign addr_a = addr_a_reg[8:0];
assign addr_pai... | 6.558648 |
module bf_buffer #(
parameter D_WL = 24,
parameter UNITS_NUM = 5
) (
input [7:0] addr,
output [UNITS_NUM*D_WL-1:0] w_o
);
//6*5=30；
wire [D_WL*UNITS_NUM-1:0] w_fix[0:5];
assign w_o = w_fix[addr];
assign w_fix[0] = 'h002f410042040062760057ed004aed;
assign w_fix[1] = 'h0043b4003a83002da500562500... | 6.506043 |
module BF_decoder_3_bit (
output reg [7:0] D,
input [2:0] I,
input E
);
always @(I or E) begin
if (E == 1'b0)
case (I)
3'b000: D = 8'b00000001;
3'b001: D = 8'b00000010;
3'b010: D = 8'b00000100;
3'b011: D = 8'b00001000;
3'b100: D = 8'b00010000;
3'b... | 7.478609 |
module BF_op #(
parameter MULT_WIDTH = 18
) (
input [2*MULT_WIDTH-1:0] ia,
input [2*MULT_WIDTH-1:0] ib,
output [2*MULT_WIDTH-1:0] oa,
output [2*MULT_WIDTH-1:0] ob
);
// `include "fft_inc.h"
localparam REAL_MSB = 2 * MULT_WIDTH - 1; // 35
localparam REAL_LSB = MULT_WIDTH; // 18
localpara... | 7.753791 |
module BF_stg1 #(
parameter FFT_STG = 7,
parameter REAL_WIDTH = 18,
parameter IMGN_WIDTH = 18,
parameter TOTAL_STAGE = 11,
localparam CPLX_WIDTH = REAL_WIDTH + IMGN_WIDTH
) (
input iclk,
input rst_n,
input ien,
input [TOTAL_STAGE-1 : 0] iaddr,
input [CPLX_WID... | 8.371965 |
module BF_stgX #(
parameter FFT_STG = 12,
TOTAL_STAGE_P = 10,
MULT_WIDTH_P = 18
) (
input iclk,
input rst_n,
input ien,
input [TOTAL_STAGE_P-1:0] iaddr,
input [2*MULT_WIDTH_P-1:0] idata,
output reg oen,
output reg [TOTAL_STAGE_P-1:0] oaddr,
output reg [2*MULT_WIDTH_P-1:0] oda... | 6.865361 |
module can give a background 0 when recieved rst signal
module blanket_0(
output wire [3:0] dat_out,
output wire [7:0] addr_out,
output wire w_en_out,rst_done,
input wire clk,en_in, rev_in
);
//Counter variable
integer i;
//Registers to manipulate outputs - connected to output port... | 6.964794 |
module bg0_tb;
wire [3:0] dat_out;
wire [7:0] addr_out;
wire w_en, rst_done;
reg clk, en_in, rev_in;
blanket_0 UUT (
.dat_out(dat_out),
.addr_out(addr_out),
.w_en_out(w_en),
.rst_done(rst_done),
.clk(clk),
.en_in(en_in),
.rev_in(rev_in)
);
initial begin
... | 6.590284 |
module BGCollisionDetector (
input btnU,
input [9:0] Hcount,
input [9:0] Vcount,
input Green,
output UpStop,
output DwStop,
output LeftStop,
output RightStop
);
assign UpStop = (~(Vcount == 10'b0000001000) & btnU & ~Green) |
(~(Vcount == 10'b0000001000) & btnU & G... | 7.030911 |
module delay5 (
clock,
d5_delay_in,
d5_delay_out
);
input clock;
input [`BITS-1:0] d5_delay_in;
output [`BITS-1:0] d5_delay_out;
//FIFO delay
reg [`BITS-1:0] d5_reg1;
/*
reg [`BITS-1:0] d5_reg2;
reg [`BITS-1:0] d5_reg3;
reg [`BITS-1:0] d5_reg4;
reg [`BITS-1:0] d5_reg5;
reg [`BITS-1:0] d5_r... | 6.609939 |
module delay_chain (
clock,
delay_in,
delay_out
);
input clock;
input [`BITS-1:0] delay_in;
output [`BITS-1:0] delay_out;
// wire [`BITS-1:0] delay_out;
wire [`BITS-1:0] delay44_out;
wire [`BITS-1:0] delay5_out1;
wire [`BITS-1:0] delay5_out2;
wire [`BITS-1:0] delay5_out3;
wire [`BITS-1:0]... | 6.555526 |
module except( clk, opa, opb, inf, ind, qnan, snan, opa_nan, opb_nan,
opa_00, opb_00, opa_inf, opb_inf, opa_dn, opb_dn);
input clk;
input [30:0] opa, opb;
output inf, ind, qnan, snan, opa_nan, opb_nan;
output opa_00, opb_00;
output opa_inf, opb_inf;
output opa_dn;
output opb_dn;
///////////////////////////////... | 6.521738 |
module mul_r2 (
clk,
opa,
opb,
prod
);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk) prod1 <= opa * opb;
always @(posedge clk) prod <= prod1;
endmodule
| 6.757243 |
module add_sub27 (
add,
opa,
opb,
sum,
co
);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? ({1'b0, opa} + {1'b0, opb}) : ({1'b0, opa} - {1'b0, opb});
endmodule
| 6.628721 |
module core =============================
module core (
inout va,
inout vb,
inout VSS,
inout VDD
);
wire vbneg, l6, l7, l8, l10, l11;
// supply0 ground;
cap_array C2 (
.Cin(va),
.Cout(VSS)
);
resistor R6 (
.rin(va),
.rout(l6)
);
resistor R7 (
.rin(l6),
.rout(l7)
);... | 6.816929 |
module bg_display (
input clk,
input clk2,
input vsync,
input blank,
output reg [11:0] pixel_out
);
reg [17:0] bg_addr = 0;
wire [ 7:0] bg_data;
blk_mem_gen_0 bg_mem (
.clka(clk2), // input wire clka
.addra(bg_addr), // input wire [17 : 0] addra
.douta(bg_data) // output... | 6.658027 |
module bg_gen #(
MEMFILE = "over.mem",
PALETTE = "over_palette.mem"
) (
input wire CLK, // board clock: 100 MHz on Arty/Basys3/Nexys
input wire RST_BTN, // reset button
output wire VGA_HS, // horizontal sync output
output wire VGA_VS, // vertical sync output
... | 7.297259 |
module bg_rom (
clk,
video_on,
x,
y,
color
);
parameter ROM_WIDTH = 12;
parameter ROM_ADDR_BITS = 14;
(* rom_style="block" *)
reg [ROM_WIDTH-1:0] rom[(2**ROM_ADDR_BITS)-1:0];
input wire clk;
input wire video_on;
input wire [6:0] x;
input wire [6:0] y;
reg [ROM_ADDR_BITS-1:0] addre... | 6.68994 |
module bg_rom (
input clk,
input resetn,
input start,
output [7:0] x,
output [6:0] y,
output [2:0] c_out,
output done
);
wire ld_all, enable;
datapath_back d0 (
.clk(clk),
.resetn(resetn),
.ld_all(ld_all),
.enable(enable),
.x(x),
.y(y),
.c_o... | 6.68994 |
module datapath_back (
input clk,
input resetn,
input ld_all,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output reg [2:0] c_out
);
reg [7:0] x_hold;
reg [6:0] y_hold;
reg [2:0] c_hold;
reg [14:0] address;
reg [7:0] x_address;
reg [6:0] y_address;
reg double;
wire... | 6.991902 |
module control_back (
input clk,
input resetn,
input start,
output reg ld_all,
output reg enable,
output reg done
);
reg [4:0] current_state, next_state;
reg [15:0] counter;
wire wait_plot = (counter > 16'd40000);
localparam S_DRAW = 5'd0, S_DONE = 5'd1, S_INITIAL = 5'd2, S_START = 5... | 8.162269 |
module bg_rom2 (
input clk,
input resetn,
input start,
output [7:0] x,
output [6:0] y,
output [2:0] c_out,
output done
);
wire ld_all, enable;
datapath_end d0 (
.clk(clk),
.resetn(resetn),
.ld_all(ld_all),
.enable(enable),
.x(x),
.y(y),
.c_o... | 6.7 |
module control_end (
input clk,
input resetn,
input start,
output reg ld_all,
output reg enable,
output reg done
);
reg [4:0] current_state, next_state;
reg [15:0] counter;
wire wait_plot = (counter > 16'd40000);
localparam S_DRAW = 5'd0, S_DONE = 5'd1, S_INITIAL = 5'd2, S_START = 5'... | 7.40965 |
module: four_beat_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_four_beat_generator;
// Inputs
reg clk;
reg rst;
// Outputs
wire [3:0] t;
// Instantiate the... | 7.080669 |
module
// Author: WangFW
// Created on 2020-11-6
//----------------------------------------------------------------
// Date: 2020-11-8
// Add read data part and led control
//----------------------------------------------------------------
module BH(
input sys_clk,
input sys_rst_n,
input key,
input uart_rxd,
... | 8.549649 |
module bhand_cycle_count # (
parameter DATA_WIDTH = 8,
parameter ENABLE_COUNT = 0,
parameter COUNT_WIDTH = 4
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] idata,
input wire idata_vld,
output wire idata_rdy,
output wire [DATA_WIDTH-1:0] odata,
output wi... | 7.221304 |
module BHT #(
parameter SET_LEN = 12,
parameter BITS = 2
) (
input clk,
rst,
input [31:0] PC_query,
PC_update,
input BR,
update,
output BHT_br
);
localparam SET_SIZE = 1 << SET_LEN;
localparam MAX_VAL = (1 << BITS) - 1;
localparam THRESHOD = MAX_VAL / 2;
reg [BITS-1 : 0] STA... | 7.276164 |
module BhtLRU (
clk,
rst_n,
touch_en,
touch_item,
lru_item
);
parameter NItem = 8;
input clk, rst_n, touch_en;
input [NItem - 1:0] touch_item;
output [NItem - 1:0] lru_item;
reg [NItem - 1:0] stack[NItem - 1:0];
wire [NItem - 1:1] hit;
assign lru_item = stack[NItem-1];
generate
... | 6.958218 |
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