code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bhv_1w1r_sram #(
parameter WWORD = 32,
parameter WADDR = 5,
parameter DEPTH = 24
) (
input clka,
output reg [WWORD-1:0] qa,
input [WADDR-1:0] aa,
input cena,
input clkb,
input [WWORD-1:0] db,
input [WADDR-1:... | 6.769175 |
module bhv_1w1r_sram_wp #(
parameter WWORD = 32,
parameter WADDR = 5,
parameter DEPTH = 24,
parameter WP = 8
) (
input clka,
output reg [ WWORD-1:0] qa,
input [ WADDR-1:0] aa,
input cena,
input clkb,
input ... | 6.769175 |
module
// Author: WangFW
// Created on 2020-11-6
//----------------------------------------------------------------
module BH(
input sys_clk,
input sys_rst_n,
input key,
output ATK_KEY,
output uart_txd
);
//-----------------------------------------
// Parameters definition
//------------------------------... | 8.549649 |
module bh_send_tb ();
reg sys_clk;
reg sys_rst_n;
reg key;
wire uart_txd;
initial begin
sys_clk = 0;
sys_rst_n = 1;
key = 1;
#10 sys_rst_n = 0;
#10 sys_rst_n = 1;
work();
end
task work();
begin
@(posedge sys_clk) key = 1'b1;
@(posedge sys_clk) key = 1'b0;
... | 7.210562 |
module bh_to_bcd (
//----------------Input ports------------------------------
input wire [11:0] binary,
//----------------Output ports-----------------------------
output reg [ 3:0] hundreds,
output reg [ 3:0] tens,
output reg [ 3:0] ones
);
integer i;
always @(binary) begin
// se... | 6.581435 |
module bi2bcd (
din,
dout2,
dout1,
dout0
);
input [7:0] din;
output [6:0] dout0;
output [6:0] dout1;
output [6:0] dout2;
reg [ 3:0] counter = 3'b0;
reg [19:0] shifter = 20'd0;
decoder d0 (
.din (shifter[11:8]),
.dout(dout0)
);
decoder d1 (
.din (shifter[15:12]),
... | 6.642519 |
module bi2gray #(
parameter width = 4 + 1
) (
input [width-1:0] bin,
output [width-1:0] gray
);
assign gray = (bin >> 1) ^ bin;
endmodule
| 7.973747 |
module bias2 (
input clk,
input [3:0] ctrl,
step,
input signed [15:0] deltab2_1,
deltab2_2,
deltab2_3,
deltab2_4,
deltab2_5,
output signed [15:0] bias2_1,
bias2_2,
bias2_3,
bias2_4,
bias2_5
);
reg signed [15:0] bias2[0:4];
initial begin
$readmemb("b2.mem", b... | 7.392015 |
module bias3 (
input clk,
input [3:0] ctrl,
step,
input signed [15:0] deltab3_1,
deltab3_2,
deltab3_3,
deltab3_4,
output signed [15:0] bias3_1,
bias3_2,
bias3_3,
bias3_4
);
reg signed [15:0] bias3[0:3];
initial begin
$readmemb("b3.mem", bias3);
end
always @(pos... | 7.16416 |
module biasb_sram2p_wrapper (
clka,
ena,
wea,
be,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
parameter AW = 7;
parameter DW = 512;
localparam BW = DW / 8;
localparam DP = 2 ** AW;
input clka;
input ena;
input wea;
input [BW-1:0] be;
input [AW-1:0] addra;
input [D... | 6.689821 |
module BiasMux #(
parameter L2Conv0Bias = 22'b1,
parameter L2Conv1Bias = 22'b1,
parameter L2Conv2Bias = 22'b1,
parameter L2Conv3Bias = 22'b1,
parameter L2Conv4Bias = 22'b1,
parameter L2Conv5Bias = 22'b1,
parameter L2Conv6Bias = 22'b1,
parameter L2Conv7Bias = 22'b1
) (
input wire [ 2... | 6.881944 |
module bias_acc (
clk,
rst,
en,
i_d,
i_lr,
o
);
// parameters
parameter WIDTH = 32;
// input ports
input signed [WIDTH-1:0] i_d;
input signed [WIDTH-1:0] i_lr;
// common ports
input clk;
input rst;
// control ports
input en;
// register ports
reg signed [WIDTH-1:0]... | 6.578476 |
module bias_addr_gen #(
parameter ADDR_WIDTH = 8
) (
input i_clk,
input i_rst_n,
input [ 4:0] i_part_num,
input [ 7:0] i_addr_start_b,
input i_pe_out_en,
input i_... | 7.067447 |
module bias_addr_gen_Add2i1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_16Ux1U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_32Ux14U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [13:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_32Ux14U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [13:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_32Ux14U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [13:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_32Ux14U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [13:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_And_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_EqSubi1u16u16_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output out1;
wire asc001;
wire [16:0] asc003;
assign asc003 = +(in1) - (17'B00000000000000001);
assign asc001 = ({{5{asc003[16]}}, asc003} == in2);
assign out1 = asc001;
endmo... | 7.067447 |
module bias_addr_gen_Equal_17Sx16U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_MuxAdd2i1u16u16u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0... | 7.067447 |
module bias_addr_gen_Muxi0u16u1_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'... | 7.067447 |
module bias_addr_gen_Muxi0u16u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'... | 7.067447 |
module bias_addr_gen_Not_1U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_N_Mux_16_2_11_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.067447 |
module bias_addr_gen_N_Mux_16_2_11_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.067447 |
module bias_addr_gen_N_Mux_32_2_12_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.067447 |
module bias_addr_gen_N_Mux_32_2_12_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.067447 |
module bias_addr_gen_N_Mux_32_2_12_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.067447 |
module bias_addr_gen_Or_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Subi1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Sub_16Ux1U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module for the bias_addr_gen module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
***********... | 7.70779 |
module bias_add_Add2i1u2_1 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in1) + (2'B01);
assign out1 = asc001;
endmodule
| 7.287692 |
module bias_add_Add2i1u2_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in1) + (2'B01);
assign out1 = asc001;
endmodule
| 7.287692 |
module bias_add_Add2i1u2_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in1) + (2'B01);
assign out1 = asc001;
endmodule
| 7.287692 |
module bias_add_Add_2Ux1U_2U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_2Ux1U_2U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_2Ux1U_2U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_MuxAdd2i1u2u2u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001, asc002;
assign asc002 = +(in2) + (2'B01);
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc0... | 7.322415 |
module bias_add_MuxAdd2i1u2u2u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001, asc002;
assign asc002 = +(in2) + (2'B01);
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc0... | 7.322415 |
module bias_add_MuxAdd2i1u2u2u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001, asc002;
assign asc002 = +(in2) + (2'B01);
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or as... | 7.322415 |
module bias_add_MuxAdd2i1u2u2u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001, asc002;
assign asc002 = +(in2) + (2'B01);
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or as... | 7.322415 |
module bias_add_N_Mux_16_2_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: ... | 7.03398 |
module bias_add_N_Mux_16_2_4_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: ... | 7.03398 |
module bias_add_N_Mux_16_2_4_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1... | 7.03398 |
module bias_add_N_Mux_16_2_4_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1... | 7.03398 |
module bias_add_N_Mux_16_3_6_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3, in2;
input [1:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in3 or in2 or in4) begin
... | 7.03398 |
module bias_add_N_Mux_16_3_6_4 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3, in2;
input [1:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in3 or in2 or in4) begin
... | 7.03398 |
module bias_add_N_Mux_16_3_6_4_0 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3, in2;
input [1:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in3 or in2 or in4) begin
... | 7.03398 |
module bias_add_N_Mux_16_3_6_4_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3, in2;
input [1:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in3 or in2 or in4) begin
... | 7.03398 |
module bias_add_N_Mux_2_2_3_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001;
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc00... | 7.03398 |
module bias_add_N_Mux_2_2_3_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001;
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc00... | 7.03398 |
module bias_add_N_Mux_2_2_3_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001;
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc... | 7.03398 |
module bias_add_N_Mux_2_2_3_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001;
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc... | 7.03398 |
module bias_add_OrReduction_2U_1U_1 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.40847 |
module bias_add_OrReduction_2U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.40847 |
module bias_add_OrReduction_2U_1U_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.40847 |
module bias_add_OrReduction_2U_1U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.40847 |
module bias_add_tb;
/**
* Clock and control functions
*/
// Generate a clk
reg clk = 0;
always #1 clk = !clk;
// End of simulation event definition
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
// Display header information
initial #1 display_heade... | 7.617228 |
module for the bias_add module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
****************... | 7.70779 |
module bias_bram_top (
input clk,
input bias_bram_en,
input [6 : 0] bias_bram_addr,
output [31 : 0] bias_bram_dout,
output reg bias_bram_rd_vld
);
always @(posedge clk) begin
bias_bram_rd_vld <= bias_bram_en;
end
BIAS_BRAM u_bias_bram (
.clka (clk), // input wire clka
... | 6.927396 |
module bias_gen #(
parameter BANDWIDTH = 512,
BITWIDTH = 32
) (
input clk_data,
input rst_n,
input clk_calc,
input bias_in_vld,
input [BANDWIDTH-1:0] bias_in,
input data_acc_layer_finish,
output reg bias_load_done,
output [B... | 7.721726 |
module is bias reg array buffer for storing
* current convolution bias.
*
* parameter:
* FW: float width
* DW: data width from read_op module
* DL: register array len
*
* ports:
* clk_i : input clock
* rstn_i : negative actice global reset
* en_i : shift enable
* data_i : input bias data from read_op
* bi... | 7.142111 |
module is bias reg array buffer for storing
* current convolution bias.
*
* parameter:
* EW: exponent width for float
* MW: mantisa width for float
* FW: float width
* DW: data width from read_op module
* DL: register array len
*
* ports:
* clk_i : input clock
* rstn_i : negative actice global reset
* en_i... | 7.142111 |
module bibi (
clk,
rst,
Borrow,
Borrowf
);
//led for Alert
// input/ output
input clk, rst;
output [3:0] Borrow;
output [3:0] Borrowf;
// wiring
wire clk, rst;
// save value place
reg [3:0] Counterr = 0;
reg [3:0] Counterg = 15;
assign Borrow[3:0] = Counterr[3:0];
assign Borr... | 7.906747 |
module BiCubic (
input clk,
input rst_n,
input [8:0] coeffOne,
input [8:0] coeffHalf,
input [8:0] yBlend,
bi_a,
xBlend,
output [8:0] bi_y0,
bi_y1,
bi_y2,
bi_y3,
bi_x0,
bi_x1,
bi_x2,
bi_x3
);
BiCubic_y3 BiCubic_y3_inst (
.clk (clk... | 6.526083 |
module BiCubic_y2 (
input clk,
input rst_n,
input [8:0] coeffOne,
input [8:0] coeffHalf,
input [8:0] yBlend,
bi_a,
output [8:0] bi_y2
);
reg [9:0] mul_x, mul_4_a;
reg [9:0] mul_3_a;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
mul_4_a <= 10... | 6.645861 |
module bidin (
// Input Ports
clk6,
rst_n,
bidin_sync_in,
bidin_ena_in,
bidin_din,
ldpc_req,
ldpc_fin,
// Output Ports
bidin_rdy,
bidin_full,
bidin_ena_out,
bidin_dout
);
parameter WID = 6;
//Input ports declaration
input clk6, rst_n;
input bidin_sync_in;
... | 6.649959 |
module bidirec (
input wire oe,
input wire inp,
output wire outp,
output wire bidir
);
assign bidir = oe ? inp : 1'bZ;
assign outp = bidir;
endmodule
| 7.291187 |
module shift_register_bidirectional (
Q3,
Q2,
Q1,
Q0,
D3,
D2,
D1,
D0,
S1,
S0,
CLK
);
output Q3; // Register output most significant bit.
output Q2;
output Q1;
output Q0; // Register output least significant bit.
input D3; // Register input most significant bit.
... | 6.854847 |
module multiplexer_4_1 (
X,
A0,
A1,
A2,
A3,
S1,
S0
);
parameter WIDTH = 16; // How many bits wide are the lines
output [WIDTH-1:0] X; // The output line
input [WIDTH-1:0] A3; // Input line with id 2'b11
input [WIDTH-1:0] A2; // Input line with id 2'b10
input [WIDTH-1:0] A1; //... | 7.168392 |
module d_flip_flop_edge_triggered (
Q,
Qn,
C,
D
);
output Q;
output Qn;
input C;
input D;
wire Cn; // Control input to the D latch.
wire Cnn; // Control input to the SR latch.
wire DQ; // Output from the D latch, inputs to the gated SR latch.
wire DQn; // Output from the D latch, inp... | 7.348263 |
module d_latch (
Q,
Qn,
G,
D
);
output Q;
output Qn;
input G;
input D;
wire Dn;
wire D1;
wire Dn1;
not (Dn, D);
and (D1, G, D);
and (Dn1, G, Dn);
nor (Qn, D1, Q);
nor (Q, Dn1, Qn);
endmodule
| 6.881555 |
module bidirectional_io #(
parameter WIDTH = 16
) (
input output_enable,
input [WIDTH-1:0] data,
inout [WIDTH-1:0] bidir_variable,
output [WIDTH-1:0] read_buffer
);
// If we are using the bidir as an output, assign it an output value,
// otherwise assign it high-impedence
assign bidir_variab... | 8.762018 |
module bidir_data #(
parameter N = 8
) (
input en,
input clk,
inout [N-1:0] bidir
);
reg [N-1:0] temp;
assign bidir = en ? temp : 8'bz;
always @(posedge clk)
if (en) temp = bidir;
else temp = temp + 1;
endmodule
| 6.655626 |
module bidir_data #(
parameter N = 8
) (
input en,
input clk,
inout [N-1:0] bidir
);
reg [N-1:0] temp;
assign bidir = en ? temp : 8'bz;
always @(posedge clk)
if (en) temp = bidir;
else temp = temp + 1;
endmodule
| 6.655626 |
module bidir_pad (
in,
out,
io,
oen
);
input in, oen;
output out;
inout io;
assign io = !oen ? in : 1'bz; //input enabled, io working as an output
assign out = oen ? io : 1'bz; //output enable, io working as an input
endmodule
| 6.679273 |
module bidi_register (
RESET, // syncronous reset (active low)
CLOCK, // clock
RW, // high for read, low for write
ENABLE, // enable bus access (active high)
COUNT, // incriment register (active high)
DATA // data bus connection
);
// PARAMETERS
parameter BUS_WIDTH = 16;
parameter C... | 7.023944 |
module bidi_register_output (
RESET, // syncronous reset (active low)
CLOCK, // clock
RW, // high for read, low for write
ENABLE, // enable bus access (active high)
COUNT, // incriment register (active high)
DATA, // data bus connection
OUTPUT // wire that constantly outputs register... | 7.023944 |
module bidi_reg_tb ();
wire RESET;
wire CLOCK;
wire RW;
wire ENABLE;
wire COUNT;
wire [15:0] DATA;
bidi_reg_stim my_stim (
.RESET(RESET),
.CLOCK(CLOCK),
.RW(RW),
.ENABLE(ENABLE),
.COUNT(COUNT),
.DATA_OUT(DATA),
.DATA_IN(DATA)
);
bidi_register my_register (
... | 6.573153 |
module RS (
output wire Q,
output wire NQ,
input wire R,
input wire S
);
nor (Q, R, NQ);
nor (NQ, S, Q);
endmodule
| 7.891872 |
module D (
output reg Q,
input wire D,
input wire C
);
initial Q = 0;
always @(negedge C) Q = D;
endmodule
| 7.927017 |
module testD;
reg [1:0] CD;
wire Q;
D d (
Q,
CD[0],
CD[1]
);
always #7 CD[1] = ~CD[1];
initial begin
$monitor($time, " | | C: %b, D: %b, Q: %b", CD[1], CD[0], Q);
$dumpfile("saluda.dmp");
$dumpvars;
CD[1] = 0;
CD[0] = 0;
#5 CD[0] = 1;
#15 CD[0] = 0;
#5 ... | 7.380768 |
module D (
output reg Q,
input wire D,
input wire C,
input wire nCLR
);
initial Q = 0;
always @(negedge C) if (nCLR) Q = #1 D;
always @(nCLR) if (!nCLR) Q = 0;
endmodule
| 7.927017 |
module SISO4bits (
output wire O,
input wire I,
input wire C,
input wire nCLR
);
wire d3s, d2s, d1s;
D d0 (
O,
d1s,
C,
nCLR
);
D d1 (
d1s,
d2s,
C,
nCLR
);
D d2 (
d2s,
d3s,
C,
nCLR
);
D d3 (
d3s,
I,
... | 7.295984 |
module testD;
reg [1:0] CD;
reg nClear;
wire Q;
SISO4bits d (
Q,
CD[0],
CD[1],
nClear
);
always #7 CD[1] = ~CD[1];
initial begin
$monitor($time, " | | %b%b%b%b | C: %b, I: %b, nCLR: %b, Q: %b", d.d3.Q, d.d2.Q, d.d1.Q,
d.d0.Q, CD[1], CD[0], nClear, Q);
$dump... | 7.380768 |
module D (
output reg Q,
input wire D,
input wire C,
input wire nCLR
);
initial Q = 0;
always @(negedge C) if (nCLR) Q = #1 D;
always @(nCLR) if (!nCLR) Q = 0;
endmodule
| 7.927017 |
module SIPO4bits (
output wire [3:0] O,
input wire I,
input wire C,
input wire nCLR
);
wire d3s, d2s, d1s;
D d0 (
O[0],
O[1],
C,
nCLR
);
D d1 (
O[1],
O[2],
C,
nCLR
);
D d2 (
O[2],
O[3],
C,
nCLR
);
D d3 (
O[3]... | 7.2239 |
module testD;
reg [1:0] CD;
reg nClear;
wire [3:0] Q;
SIPO4bits d (
Q,
CD[0],
CD[1],
nClear
);
always #7 CD[1] = ~CD[1];
initial begin
$monitor($time, " | | %b%b%b%b | C: %b, I: %b, nCLR: %b, Q: %b", d.d3.Q, d.d2.Q, d.d1.Q,
d.d0.Q, CD[1], CD[0], nClear, Q);
... | 7.380768 |
module JKUp (
output reg Q,
output wire NQ,
input wire J,
input wire K,
input wire C,
input wire nPRESET,
input wire nCLEAR
);
not (NQ, Q);
initial Q = 0;
always @(posedge C) begin
if (nPRESET && nCLEAR)
case ({
J, K
})
2'b01: Q = 0; // RESET
... | 7.971081 |
module RS (
output reg Q,
output wire NQ,
input wire R,
input wire S,
input wire C,
input wire nCLR
);
initial Q = 0;
not (NQ, Q);
always @(negedge C)
if (nCLR)
case ({
R, S
})
2'b01: Q = #1 1;
2'b10: Q = #1 0;
endcase
always @(nCLR) i... | 7.891872 |
module RS1bit (
output wire O,
input wire SP,
input wire Is,
input wire Ip,
input wire C,
input wire nCLR
);
wire nI, IsSP, IpNsp, nsp1, I;
not (nsp1, SP);
and (IsSP, Is, SP);
and (IpNsp, Ip, nsp1);
nor (nI, IsSP, IpNsp);
not (I, nI);
RS rs1 (
O
,,
nI,
... | 8.659726 |
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