code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bhv_1w1r_sram #(
parameter WWORD = 32,
parameter WADDR = 5,
parameter DEPTH = 24
) (
input clka,
output reg [WWORD-1:0] qa,
input [WADDR-1:0] aa,
input cena,
input clkb,
input [WWORD-1:0] db,
input [WADDR-1:0] ab,
input cenb
);
reg [WWORD-1:0] mem[0:((1<<WADDR)-1)];
always @(posedge clka) if (!cena) qa <= #0.5 mem[aa];
always @(posedge clkb) if (!cenb && ab < DEPTH) mem[ab] <= #0.5 db;
endmodule
| 6.769175 |
module bhv_1w1r_sram_wp #(
parameter WWORD = 32,
parameter WADDR = 5,
parameter DEPTH = 24,
parameter WP = 8
) (
input clka,
output reg [ WWORD-1:0] qa,
input [ WADDR-1:0] aa,
input cena,
input clkb,
input [ WWORD-1:0] db,
input [ WADDR-1:0] ab,
input [WWORD/WP-1:0] wenb,
input cenb
);
reg [WWORD-1:0] mem[0:((1<<WADDR)-1)];
always @(posedge clka) if (!cena) qa <= #0.5 mem[aa];
genvar i;
generate
for (i = 0; i < WWORD / WP; i = i + 1) begin
always @(posedge clkb)
if (!cenb && !wenb[i] && ab < DEPTH)
mem[ab][WP*i+:WP] <= #0.5 db[WP*i+:WP];
end
endgenerate
endmodule
| 6.769175 |
module
// Author: WangFW
// Created on 2020-11-6
//----------------------------------------------------------------
module BH(
input sys_clk,
input sys_rst_n,
input key,
output ATK_KEY,
output uart_txd
);
//-----------------------------------------
// Parameters definition
//-----------------------------------------
wire enable;
wire [7:0] data;
assign ATK_KEY = 1'b0;
//-----------------------------------------
// Module connect
//-----------------------------------------
uart_send_source src1(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.key(key),
.enable(enable),
.dout(data)
);
uart_send send1(
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.uart_en(enable),
.uart_din(data),
.uart_txd(uart_txd)
);
endmodule
| 8.549649 |
module bh_send_tb ();
reg sys_clk;
reg sys_rst_n;
reg key;
wire uart_txd;
initial begin
sys_clk = 0;
sys_rst_n = 1;
key = 1;
#10 sys_rst_n = 0;
#10 sys_rst_n = 1;
work();
end
task work();
begin
@(posedge sys_clk) key = 1'b1;
@(posedge sys_clk) key = 1'b0;
@(posedge sys_clk) key = 1'b0;
@(posedge sys_clk) key = 1'b1;
end
endtask
always #2 sys_clk <= ~sys_clk;
bh_send dut (
.sys_clk(sys_clk),
.sys_rst_n(sys_rst_n),
.key(key),
.uart_txd(uart_txd)
);
endmodule
| 7.210562 |
module bh_to_bcd (
//----------------Input ports------------------------------
input wire [11:0] binary,
//----------------Output ports-----------------------------
output reg [ 3:0] hundreds,
output reg [ 3:0] tens,
output reg [ 3:0] ones
);
integer i;
always @(binary) begin
// set 100's, 10's, and 1's to zero
hundreds = 4'd0;
tens = 4'd0;
ones = 4'd0;
for (i = 11; i >= 0; i = i - 1) begin
// add 3 to columns >= 5
if (hundreds >= 5) hundreds = hundreds + 3;
if (tens >= 5) tens = tens + 3;
if (ones >= 5) ones = ones + 3;
// shift left one
hundreds = hundreds << 1;
hundreds[0] = tens[3];
tens = tens << 1;
tens[0] = ones[3];
ones = ones << 1;
ones[0] = binary[i];
end
end
endmodule
| 6.581435 |
module bi2bcd (
din,
dout2,
dout1,
dout0
);
input [7:0] din;
output [6:0] dout0;
output [6:0] dout1;
output [6:0] dout2;
reg [ 3:0] counter = 3'b0;
reg [19:0] shifter = 20'd0;
decoder d0 (
.din (shifter[11:8]),
.dout(dout0)
);
decoder d1 (
.din (shifter[15:12]),
.dout(dout1)
);
decoder d2 (
.din (shifter[19:16]),
.dout(dout2)
);
always @(din) begin
shifter[7:0] = din;
shifter[19:8] = 12'b0;
for (counter = 4'd0; counter < 4'd8; counter = counter + 1) begin
if (shifter[11:8] > 4'd4) begin
shifter[11:8] = shifter[11:8] + 4'd3;
end
if (shifter[15:12] > 4'd4) begin
shifter[15:12] = shifter[15:12] + 4'd3;
end
if (shifter[19:16] > 4'd4) begin
shifter[19:16] = shifter[19:16] + 4'd3;
end
shifter = shifter << 1;
end
end
endmodule
| 6.642519 |
module bi2gray #(
parameter width = 4 + 1
) (
input [width-1:0] bin,
output [width-1:0] gray
);
assign gray = (bin >> 1) ^ bin;
endmodule
| 7.973747 |
module bias2 (
input clk,
input [3:0] ctrl,
step,
input signed [15:0] deltab2_1,
deltab2_2,
deltab2_3,
deltab2_4,
deltab2_5,
output signed [15:0] bias2_1,
bias2_2,
bias2_3,
bias2_4,
bias2_5
);
reg signed [15:0] bias2[0:4];
initial begin
$readmemb("b2.mem", bias2);
end
always @(posedge clk) begin
if (step != 4'b0000) begin
if (ctrl == 4'b0001) begin
bias2[0] <= bias2[0] + deltab2_1;
bias2[1] <= bias2[1] + deltab2_2;
bias2[2] <= bias2[2] + deltab2_3;
bias2[3] <= bias2[3] + deltab2_4;
bias2[4] <= bias2[4] + deltab2_5;
end else begin
bias2[0] <= bias2[0];
bias2[1] <= bias2[1];
bias2[2] <= bias2[2];
bias2[3] <= bias2[3];
bias2[4] <= bias2[4];
end
end else begin
bias2[0] <= bias2[0];
bias2[1] <= bias2[1];
bias2[2] <= bias2[2];
bias2[3] <= bias2[3];
bias2[4] <= bias2[4];
end
end
assign bias2_1 = bias2[0];
assign bias2_2 = bias2[1];
assign bias2_3 = bias2[2];
assign bias2_4 = bias2[3];
assign bias2_5 = bias2[4];
endmodule
| 7.392015 |
module bias3 (
input clk,
input [3:0] ctrl,
step,
input signed [15:0] deltab3_1,
deltab3_2,
deltab3_3,
deltab3_4,
output signed [15:0] bias3_1,
bias3_2,
bias3_3,
bias3_4
);
reg signed [15:0] bias3[0:3];
initial begin
$readmemb("b3.mem", bias3);
end
always @(posedge clk) begin
if (step != 4'b0000) begin
if (ctrl == 4'b0011) begin
bias3[0] <= bias3[0] + deltab3_1;
bias3[1] <= bias3[1] + deltab3_2;
bias3[2] <= bias3[2] + deltab3_3;
bias3[3] <= bias3[3] + deltab3_4;
end else begin
bias3[0] <= bias3[0];
bias3[1] <= bias3[1];
bias3[2] <= bias3[2];
bias3[3] <= bias3[3];
end
end else begin
bias3[0] <= bias3[0];
bias3[1] <= bias3[1];
bias3[2] <= bias3[2];
bias3[3] <= bias3[3];
end
end
assign bias3_1 = bias3[0];
assign bias3_2 = bias3[1];
assign bias3_3 = bias3[2];
assign bias3_4 = bias3[3];
endmodule
| 7.16416 |
module biasb_sram2p_wrapper (
clka,
ena,
wea,
be,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
parameter AW = 7;
parameter DW = 512;
localparam BW = DW / 8;
localparam DP = 2 ** AW;
input clka;
input ena;
input wea;
input [BW-1:0] be;
input [AW-1:0] addra;
input [DW-1:0] dina;
input clkb;
input enb;
input [AW-1:0] addrb;
output [DW-1:0] doutb;
`ifdef FPGA
wire [BW-1:0] ram_wea;
assign ram_wea = {BW{wea}} & be;
simple_dual_port_ram512x128 iob_ram (
.clka (clka),
.ena (ena),
.wea (ram_wea),
.addra(addra),
.dina (dina),
.clkb (clkb),
.enb (enb),
.addrb(addrb),
.doutb(doutb)
);
`else
`endif
endmodule
| 6.689821 |
module BiasMux #(
parameter L2Conv0Bias = 22'b1,
parameter L2Conv1Bias = 22'b1,
parameter L2Conv2Bias = 22'b1,
parameter L2Conv3Bias = 22'b1,
parameter L2Conv4Bias = 22'b1,
parameter L2Conv5Bias = 22'b1,
parameter L2Conv6Bias = 22'b1,
parameter L2Conv7Bias = 22'b1
) (
input wire [ 2:0] Sel_i,
output wire [21:0] Bias_o
);
assign Bias_o = Sel_i == 4'h0 ? L2Conv0Bias : (
Sel_i == 4'h1 ? L2Conv1Bias : (
Sel_i == 4'h2 ? L2Conv2Bias : (
Sel_i == 4'h3 ? L2Conv3Bias : (
Sel_i == 4'h4 ? L2Conv4Bias : (
Sel_i == 4'h5 ? L2Conv5Bias : (
Sel_i == 4'h6 ? L2Conv6Bias : L2Conv7Bias))))));
endmodule
| 6.881944 |
module bias_acc (
clk,
rst,
en,
i_d,
i_lr,
o
);
// parameters
parameter WIDTH = 32;
// input ports
input signed [WIDTH-1:0] i_d;
input signed [WIDTH-1:0] i_lr;
// common ports
input clk;
input rst;
// control ports
input en;
// register ports
reg signed [WIDTH-1:0] reg_adder;
// output ports
output signed [WIDTH-1:0] o;
wire signed [WIDTH-1:0] adder;
wire signed [WIDTH-1:0] outmult;
wire signed [WIDTH-1:0] outmux;
mult_2in #(
.WIDTH(WIDTH),
.FRAC (24)
) mult (
.i_a(i_d),
.i_b(i_lr),
.o (outmult)
);
multiplexer #(
.WIDTH(WIDTH)
) mux (
.i_a(32'h0),
.i_b(outmult),
.sel(en),
.o (outmux)
);
assign adder = reg_adder + outmux;
always @(posedge clk or posedge rst) begin
if (rst) begin
reg_adder <= 32'd0;
end else reg_adder <= adder;
end
assign o = reg_adder;
endmodule
| 6.578476 |
module bias_addr_gen #(
parameter ADDR_WIDTH = 8
) (
input i_clk,
input i_rst_n,
input [ 4:0] i_part_num,
input [ 7:0] i_addr_start_b,
input i_pe_out_en,
input i_calc_en,
input [ 7:0] i_output_layers,
input i_AddrEn,
// input i_npe_dat_vld,
output reg [ADDR_WIDTH - 1:0] o_ram_addr,
output o_ram_rd_en
);
reg [4:0] r_part_num;
reg [8:0] r_cur_outlayers;
// reg r_ram_rd_en;
wire c_outlayerEn;
wire c_addr_En;
reg first_part_zero;
assign c_outlayerEn = ((r_part_num == i_part_num)&& i_pe_out_en) || (first_part_zero&&i_pe_out_en);
assign o_ram_rd_en = c_outlayerEn;
assign c_addr_En = c_outlayerEn && (r_cur_outlayers == i_output_layers);
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) r_part_num <= 5'h0;
else if (i_calc_en) r_part_num <= 5'h0;
else if (i_pe_out_en && i_AddrEn)
if (r_part_num == i_part_num) r_part_num <= 5'h1;
else r_part_num <= r_part_num + 1;
else r_part_num <= r_part_num;
end
//用来修改第一次的r_part计数器
always @(posedge i_clk or negedge i_rst_n) begin
if (~i_rst_n) begin
first_part_zero <= 0;
end else if (i_calc_en) first_part_zero <= 1'b1;
else if (i_pe_out_en && first_part_zero) first_part_zero <= 1'b0;
else first_part_zero <= first_part_zero;
end
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) r_cur_outlayers <= 8'h0;
else if (i_calc_en) r_cur_outlayers <= 8'h1;
else if (c_outlayerEn & i_AddrEn)
if (r_cur_outlayers == i_output_layers) r_cur_outlayers <= 8'h1;
else r_cur_outlayers <= r_cur_outlayers + 1;
else r_cur_outlayers <= r_cur_outlayers;
end
always @(posedge i_clk or negedge i_rst_n) begin
if (!i_rst_n) o_ram_addr <= {ADDR_WIDTH{1'b0}};
else if (i_calc_en)
// o_ram_addr <= {ADDR_WIDTH{1'b0}};
o_ram_addr <= i_addr_start_b;
//else if(c_outlayerEn &i_AddrEn)
else if (o_ram_rd_en & i_AddrEn)
if (c_addr_En) o_ram_addr <= i_addr_start_b;
else o_ram_addr <= o_ram_addr + 1;
else o_ram_addr <= o_ram_addr;
end
endmodule
| 7.067447 |
module bias_addr_gen_Add2i1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in1) + (16'B0000000000000001);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_16Ux1U_16U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [15:0] out1;
wire [15:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_32Ux14U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [13:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_32Ux14U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [13:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_32Ux14U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [13:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Add_32Ux14U_32U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [13:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_And_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) & (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_EqSubi1u16u16_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2, in1;
output out1;
wire asc001;
wire [16:0] asc003;
assign asc003 = +(in1) - (17'B00000000000000001);
assign asc001 = ({{5{asc003[16]}}, asc003} == in2);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Equal_17Sx16U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [16:0] in2;
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == {{5{in2[16]}}, in2});
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_MuxAdd2i1u16u16u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001, asc002;
assign asc002 = +(in2) + (16'B0000000000000001);
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Muxi0u16u1_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Muxi0u16u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 16'B0000000000000000;
default: asc001_tmp_0 = in2;
endcase
end
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Not_1U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_N_Mux_16_2_11_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_N_Mux_16_2_11_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_N_Mux_32_2_12_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_N_Mux_32_2_12_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_N_Mux_32_2_12_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Or_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Subi1u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in1) - (17'B00000000000000001);
assign out1 = asc001;
endmodule
| 7.067447 |
module bias_addr_gen_Sub_16Ux1U_17S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input in1;
output [16:0] out1;
wire [16:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 7.067447 |
module for the bias_addr_gen module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
****************************************************************************/
`timescale 1 ps / 1 ps
module bias_addr_gen_vlwrapper(
clk,
rstn,
init,
out_feature_width,
out_feature_height,
out_feature_channel,
bias_read_base_addr,
bias_en,
start_rising,
data_en,
bias_addr,
bias_addr_valid
);
input clk;
input rstn;
input init;
input [15:0] out_feature_width;
input [15:0] out_feature_height;
input [15:0] out_feature_channel;
input [31:0] bias_read_base_addr;
input bias_en;
input start_rising;
input data_en;
output [31:0] bias_addr;
reg[31:0] bias_addr;
wire [31:0] m_bias_addr;
output bias_addr_valid;
reg bias_addr_valid;
wire m_bias_addr_valid;
// Instantiate the Verilog module that instantiates the SystemC module
bias_addr_gen_type_wrapper bias_addr_gen_sc(
.clk(clk),
.rstn(rstn),
.init(init),
.out_feature_width(out_feature_width),
.out_feature_height(out_feature_height),
.out_feature_channel(out_feature_channel),
.bias_read_base_addr(bias_read_base_addr),
.bias_en(bias_en),
.start_rising(start_rising),
.data_en(data_en),
.bias_addr(m_bias_addr),
.bias_addr_valid(m_bias_addr_valid)
);
// Always blocks for non-blocking assignments of type_wrapper outputs to
// Verilog Verificatoin wrapper outputs.
always @(m_bias_addr)
begin
bias_addr <= m_bias_addr;
end
always @(m_bias_addr_valid)
begin
bias_addr_valid <= m_bias_addr_valid;
end
endmodule
| 7.70779 |
module bias_add_Add2i1u2_1 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in1) + (2'B01);
assign out1 = asc001;
endmodule
| 7.287692 |
module bias_add_Add2i1u2_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in1) + (2'B01);
assign out1 = asc001;
endmodule
| 7.287692 |
module bias_add_Add2i1u2_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in1) + (2'B01);
assign out1 = asc001;
endmodule
| 7.287692 |
module bias_add_Add_2Ux1U_2U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_2Ux1U_2U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_2Ux1U_2U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [1:0] in2;
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_Add_32Ux16S_32S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [15:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + ({{16{in1[15]}}, in1});
assign out1 = asc001;
endmodule
| 7.294518 |
module bias_add_MuxAdd2i1u2u2u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001, asc002;
assign asc002 = +(in2) + (2'B01);
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.322415 |
module bias_add_MuxAdd2i1u2u2u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001, asc002;
assign asc002 = +(in2) + (2'B01);
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.322415 |
module bias_add_MuxAdd2i1u2u2u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001, asc002;
assign asc002 = +(in2) + (2'B01);
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.322415 |
module bias_add_MuxAdd2i1u2u2u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001, asc002;
assign asc002 = +(in2) + (2'B01);
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or asc002 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = asc002;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.322415 |
module bias_add_N_Mux_16_2_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_16_2_4_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_16_2_4_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_16_2_4_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in3, in2;
input ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_16_3_6_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3, in2;
input [1:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in3 or in2 or in4) begin
case (ctrl1)
2'B10: asc001_tmp_0 = in3;
2'B01: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_16_3_6_4 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3, in2;
input [1:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in3 or in2 or in4) begin
case (ctrl1)
2'B10: asc001_tmp_0 = in3;
2'B01: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_16_3_6_4_0 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3, in2;
input [1:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in3 or in2 or in4) begin
case (ctrl1)
2'B10: asc001_tmp_0 = in3;
2'B01: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_16_3_6_4_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [15:0] in4, in3, in2;
input [1:0] ctrl1;
output [15:0] out1;
wire [15:0] asc001;
reg [15:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in3 or in2 or in4) begin
case (ctrl1)
2'B10: asc001_tmp_0 = in3;
2'B01: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in4;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_2_2_3_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001;
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_2_2_3_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001;
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_2_2_3_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001;
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_N_Mux_2_2_3_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [1:0] in3, in2;
input ctrl1;
output [1:0] out1;
wire [1:0] asc001;
reg [1:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.03398 |
module bias_add_OrReduction_2U_1U_1 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.40847 |
module bias_add_OrReduction_2U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.40847 |
module bias_add_OrReduction_2U_1U_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.40847 |
module bias_add_OrReduction_2U_1U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.40847 |
module bias_add_tb;
/**
* Clock and control functions
*/
// Generate a clk
reg clk = 0;
always #1 clk = !clk;
// End of simulation event definition
event end_trigger;
always @(end_trigger) $finish;
`ifdef TB_VERBOSE
// Display header information
initial #1 display_header();
always @(end_trigger) display_header();
// And strobe signals at each clk
always @(posedge clk) display_signals();
`endif
// initial begin
// $dumpfile("result.vcd"); // Waveform file
// $dumpvars;
// end
/**
* Local parameters
*/
localparam NUM_WIDTH = 16;
localparam NUM_POINT = 8;
// transform signed fixed point representation to real
function real num_f2r;
input signed [NUM_WIDTH-1:0] value;
begin
num_f2r = value / ((1<<NUM_POINT) * 1.0);
end
endfunction
// transform real to signed fixed point representation
function signed [NUM_WIDTH-1:0] num_r2f;
input real value;
begin
num_r2f = value * (1<<(NUM_POINT));
end
endfunction
`ifdef TB_VERBOSE
initial begin
$display("Testbench for 'bias_add'");
end
`endif
/**
* signals, registers and wires
*/
reg [NUM_WIDTH-1:0] bias;
reg [NUM_WIDTH-1:0] up_data;
wire signed [NUM_WIDTH-1:0] dn_data;
reg up_valid;
reg dn_valid;
/**
* Unit under test
*/
bias_add #(
.NUM_WIDTH (NUM_WIDTH))
uut (
.clk (clk),
.bias (bias),
.up_data (up_data),
.dn_data (dn_data)
);
// one pipeline depth
always @(posedge clk)
dn_valid <= up_valid;
/**
* Wave form display
*/
task display_signals;
$display(
"%d",
$time,
"\t<bias> %f",
num_f2r(bias),
"\t<up> %b %f ",
up_valid,
num_f2r(up_data),
"\t<dn> %b %f",
dn_valid,
num_f2r(dn_data),
);
endtask // display_signals
task display_header;
$display(
"\t\ttime",
"\t\tbias",
"\t\tup",
"\t\t\tdn",
);
endtask
/**
* Testbench program
*/
initial begin
// init values
bias = num_r2f(2.5);
up_data = 'b0;
up_valid = 1'b0;
//end init
repeat(5) @(negedge clk);
`ifdef TB_VERBOSE
$display("send data");
`endif
@(negedge clk);
repeat(20) begin
up_valid <= 1'b1;
up_data <= num_r2f(num_f2r(up_data)+1.0);
@(negedge clk);
end
up_valid <= 1'b0;
up_data <= 'b0;
repeat(10) @(negedge clk);
`ifdef TB_VERBOSE
$display("END");
`endif
-> end_trigger;
end
endmodule
| 7.617228 |
module for the bias_add module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
****************************************************************************/
`timescale 1 ps / 1 ps
module bias_add_vlwrapper(
clk,
rstn,
enable,
src_valid,
src_0,
src_1,
src_2,
src_3,
src_4,
src_5,
src_6,
src_7,
bias_data,
dst_valid,
dst_0,
dst_1,
dst_2,
dst_3,
dst_4,
dst_5,
dst_6,
dst_7
);
input clk;
input rstn;
input enable;
input src_valid;
input [31:0] src_0;
input [31:0] src_1;
input [31:0] src_2;
input [31:0] src_3;
input [31:0] src_4;
input [31:0] src_5;
input [31:0] src_6;
input [31:0] src_7;
input [511:0] bias_data;
output dst_valid;
reg dst_valid;
wire m_dst_valid;
output [31:0] dst_0;
output [31:0] dst_1;
output [31:0] dst_2;
output [31:0] dst_3;
output [31:0] dst_4;
output [31:0] dst_5;
output [31:0] dst_6;
output [31:0] dst_7;
reg[31:0] dst_0;
wire [31:0] m_dst_0;
reg[31:0] dst_1;
wire [31:0] m_dst_1;
reg[31:0] dst_2;
wire [31:0] m_dst_2;
reg[31:0] dst_3;
wire [31:0] m_dst_3;
reg[31:0] dst_4;
wire [31:0] m_dst_4;
reg[31:0] dst_5;
wire [31:0] m_dst_5;
reg[31:0] dst_6;
wire [31:0] m_dst_6;
reg[31:0] dst_7;
wire [31:0] m_dst_7;
// Instantiate the Verilog module that instantiates the SystemC module
bias_add_type_wrapper bias_add_sc(
.clk(clk),
.rstn(rstn),
.enable(enable),
.src_valid(src_valid),
.src_0(src_0),
.src_1(src_1),
.src_2(src_2),
.src_3(src_3),
.src_4(src_4),
.src_5(src_5),
.src_6(src_6),
.src_7(src_7),
.bias_data(bias_data),
.dst_valid(m_dst_valid),
.dst_0(m_dst_0),
.dst_1(m_dst_1),
.dst_2(m_dst_2),
.dst_3(m_dst_3),
.dst_4(m_dst_4),
.dst_5(m_dst_5),
.dst_6(m_dst_6),
.dst_7(m_dst_7)
);
// Always blocks for non-blocking assignments of type_wrapper outputs to
// Verilog Verificatoin wrapper outputs.
always @(m_dst_valid)
begin
dst_valid <= m_dst_valid;
end
always @(m_dst_0)
begin
dst_0 <= m_dst_0;
end
always @(m_dst_1)
begin
dst_1 <= m_dst_1;
end
always @(m_dst_2)
begin
dst_2 <= m_dst_2;
end
always @(m_dst_3)
begin
dst_3 <= m_dst_3;
end
always @(m_dst_4)
begin
dst_4 <= m_dst_4;
end
always @(m_dst_5)
begin
dst_5 <= m_dst_5;
end
always @(m_dst_6)
begin
dst_6 <= m_dst_6;
end
always @(m_dst_7)
begin
dst_7 <= m_dst_7;
end
endmodule
| 7.70779 |
module bias_bram_top (
input clk,
input bias_bram_en,
input [6 : 0] bias_bram_addr,
output [31 : 0] bias_bram_dout,
output reg bias_bram_rd_vld
);
always @(posedge clk) begin
bias_bram_rd_vld <= bias_bram_en;
end
BIAS_BRAM u_bias_bram (
.clka (clk), // input wire clka
.ena (bias_bram_en), // input wire ena
.addra(bias_bram_addr), // input wire [6 : 0] addra
.douta(bias_bram_dout) // output wire [31 : 0] douta
);
endmodule
| 6.927396 |
module bias_gen #(
parameter BANDWIDTH = 512,
BITWIDTH = 32
) (
input clk_data,
input rst_n,
input clk_calc,
input bias_in_vld,
input [BANDWIDTH-1:0] bias_in,
input data_acc_layer_finish,
output reg bias_load_done,
output [BITWIDTH*16-1:0] bias_out
);
wire fifo_wr_en;
wire [BANDWIDTH-1:0] fifo_wr_data;
bias_ctrl bias_ctrl (
.clk_data (clk_data),
.rst_n (rst_n),
.bias_in_vld (bias_in_vld),
.bias_in (bias_in),
.fifo_wr_en (fifo_wr_en),
.fifo_wr_data(fifo_wr_data)
);
wire fifo_empty;
wire fifo_rd_en;
fifo_bias_gen fifo_bias_gen_inst (
.wrclk (clk_data),
.wrreq (fifo_wr_en),
.wrfull (),
.data (fifo_wr_data),
.rdclk (clk_calc),
.aclr (~rst_n),
.rdreq (fifo_rd_en),
.rdempty(fifo_empty),
.q (bias_out)
);
wire bias_first_load;
reg bias_first_load_reg1;
reg bias_first_load_reg2;
wire bias_load;
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
bias_first_load_reg1 <= 1'b0;
bias_first_load_reg2 <= 1'b0;
end else if (fifo_empty == 1'b0) begin
bias_first_load_reg1 <= 1'b1;
bias_first_load_reg2 <= bias_first_load_reg1;
end else begin
bias_first_load_reg1 <= bias_first_load_reg1;
bias_first_load_reg2 <= bias_first_load_reg2;
end
end
assign bias_first_load = bias_first_load_reg1 ^ bias_first_load_reg2;
reg bias_wait_load;
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
bias_wait_load <= 1'b0;
end else if (data_acc_layer_finish == 1'b1 && fifo_empty == 1'b1) begin
bias_wait_load <= 1'b1;
end else if (fifo_empty == 1'b0 && bias_load == 1'b1) begin
bias_wait_load <= 1'b0;
end else begin
bias_wait_load <= bias_wait_load;
end
end
assign bias_load = bias_first_load | data_acc_layer_finish | bias_wait_load;
reg fifo_rd_en_p;
reg [14:0] fifo_rd_en_r;
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
fifo_rd_en_p <= 1'b0;
bias_load_done <= 1'b0;
end else if (fifo_empty == 1'b0 && bias_load == 1'b1) begin
fifo_rd_en_p <= 1'b1;
bias_load_done <= 1'b1;
end else begin
fifo_rd_en_p <= 1'b0;
bias_load_done <= 1'b0;
end
end
always @(posedge clk_calc or negedge rst_n) begin
if (!rst_n) begin
fifo_rd_en_r <= 15'b0;
end else begin
fifo_rd_en_r <= {fifo_rd_en_r[13:0], fifo_rd_en_p};
end
end
assign fifo_rd_en = fifo_rd_en_r[14];
endmodule
| 7.721726 |
module is bias reg array buffer for storing
* current convolution bias.
*
* parameter:
* FW: float width
* DW: data width from read_op module
* DL: register array len
*
* ports:
* clk_i : input clock
* rstn_i : negative actice global reset
* en_i : shift enable
* data_i : input bias data from read_op
* bias_o : bias output
--------------------------------------------------*/
`timescale 1 ns/1 ns
module bias_reg_array
#(
parameter FW = 32,
parameter DW = 512,
parameter RL = 512
)
(
input clk_i,
input rstn_i,
input en_i,
input last_data_i,
input [ DW-1:0 ] data_i,
output [ RL*FW-1:0 ] bias_o
);
localparam PACKAGE_LEN = DW / FW; // data number in one input data data_i
localparam PACKAGE_NUM = RL / PACKAGE_LEN;
/*
* internal register and wire
*/
reg [ FW-1:0 ] bias_[ 0:RL-1 ]; // bias register array
reg [ PACKAGE_NUM-1:0 ] receive_en;
always @( negedge rstn_i or posedge clk_i )
begin
if( rstn_i == 1'b0 )
begin
receive_en <= {1'b1,{(PACKAGE_NUM-1){1'b0}} };
end
else if( last_data_i == 1'b1 )
begin
receive_en <= { en_i, {(PACKAGE_NUM-1){1'b0}} };
end
else if( en_i == 1'b1 )
begin
receive_en <= receive_en >> 1;
end
end
genvar i;
generate
for( i = 0; i < PACKAGE_NUM; i = i + 1)
begin
always @( negedge rstn_i or posedge clk_i )
begin
if( rstn_i == 1'b0 )
begin
bias_[ i*PACKAGE_LEN + 0 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 1 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 2 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 3 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 4 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 5 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 6 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 7 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 8 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 9 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 10 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 11 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 12 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 13 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 14 ] <= {FW{1'b0}};
bias_[ i*PACKAGE_LEN + 15 ] <= {FW{1'b0}};
end
else if( receive_en[ i ] == 1'b1 && en_i == 1'b1 )
begin
bias_[ i*PACKAGE_LEN + 0 ] <= data_i[ 1*FW-1:0*FW ];
bias_[ i*PACKAGE_LEN + 1 ] <= data_i[ 2*FW-1:1*FW ];
bias_[ i*PACKAGE_LEN + 2 ] <= data_i[ 3*FW-1:2*FW ];
bias_[ i*PACKAGE_LEN + 3 ] <= data_i[ 4*FW-1:3*FW ];
bias_[ i*PACKAGE_LEN + 4 ] <= data_i[ 5*FW-1:4*FW ];
bias_[ i*PACKAGE_LEN + 5 ] <= data_i[ 6*FW-1:5*FW ];
bias_[ i*PACKAGE_LEN + 6 ] <= data_i[ 7*FW-1:6*FW ];
bias_[ i*PACKAGE_LEN + 7 ] <= data_i[ 8*FW-1:7*FW ];
bias_[ i*PACKAGE_LEN + 8 ] <= data_i[ 9*FW-1:8*FW ];
bias_[ i*PACKAGE_LEN + 9 ] <= data_i[ 10*FW-1:9*FW ];
bias_[ i*PACKAGE_LEN + 10 ] <= data_i[ 11*FW-1:10*FW ];
bias_[ i*PACKAGE_LEN + 11 ] <= data_i[ 12*FW-1:11*FW ];
bias_[ i*PACKAGE_LEN + 12 ] <= data_i[ 13*FW-1:12*FW ];
bias_[ i*PACKAGE_LEN + 13 ] <= data_i[ 14*FW-1:13*FW ];
bias_[ i*PACKAGE_LEN + 14 ] <= data_i[ 15*FW-1:14*FW ];
bias_[ i*PACKAGE_LEN + 15 ] <= data_i[ 16*FW-1:15*FW ];
end
end
end
endgenerate
/*
* output
*/
generate
for( i = 0; i < RL; i = i + 1)
begin:pack_out
assign bias_o[ (i+1)*FW-1:i*FW ] = bias_[ i ];
end // end pack_out
endgenerate
endmodule
| 7.142111 |
module is bias reg array buffer for storing
* current convolution bias.
*
* parameter:
* EW: exponent width for float
* MW: mantisa width for float
* FW: float width
* DW: data width from read_op module
* DL: register array len
*
* ports:
* clk_i : input clock
* rstn_i : negative actice global reset
* en_i : shift enable
* data_i : input bias data from read_op
* bias_o : bias output
--------------------------------------------------*/
`timescale 1 ns/1 ns
module bias_reg_array_case
#(
parameter EW = 8,
parameter MW = 23,
parameter FW = 32,
parameter DW = 512,
parameter RL = 512
)
(
input clk_i,
input rstn_i,
input en_i,
input [ 5-1:0 ] addr_i,
input [ DW-1:0 ] data_i,
output [ RL*FW-1:0 ] bias_o
);
localparam PACKAGE_LEN = DW / FW; // data number in one input data data_i
localparam PACKAGE_NUM = RL / PACKAGE_LEN;
/*
* internal register and wire
*/
reg [ DW-1:0 ] bias_[ 0:PACKAGE_NUM-1 ]; // bias register array
always @( negedge rstn_i or posedge clk_i )
begin
if( rstn_i == 1'b0 )
begin
bias_[ 0 ] <= {DW{1'b0}};
bias_[ 1 ] <= {DW{1'b0}};
bias_[ 2 ] <= {DW{1'b0}};
bias_[ 3 ] <= {DW{1'b0}};
bias_[ 4 ] <= {DW{1'b0}};
bias_[ 5 ] <= {DW{1'b0}};
bias_[ 6 ] <= {DW{1'b0}};
bias_[ 7 ] <= {DW{1'b0}};
bias_[ 8 ] <= {DW{1'b0}};
bias_[ 9 ] <= {DW{1'b0}};
bias_[ 10 ] <= {DW{1'b0}};
bias_[ 11 ] <= {DW{1'b0}};
bias_[ 12 ] <= {DW{1'b0}};
bias_[ 13 ] <= {DW{1'b0}};
bias_[ 14 ] <= {DW{1'b0}};
bias_[ 15 ] <= {DW{1'b0}};
bias_[ 16 ] <= {DW{1'b0}};
bias_[ 17 ] <= {DW{1'b0}};
bias_[ 18 ] <= {DW{1'b0}};
bias_[ 19 ] <= {DW{1'b0}};
bias_[ 20 ] <= {DW{1'b0}};
bias_[ 21 ] <= {DW{1'b0}};
bias_[ 22 ] <= {DW{1'b0}};
bias_[ 23 ] <= {DW{1'b0}};
bias_[ 24 ] <= {DW{1'b0}};
bias_[ 25 ] <= {DW{1'b0}};
bias_[ 26 ] <= {DW{1'b0}};
bias_[ 27 ] <= {DW{1'b0}};
bias_[ 28 ] <= {DW{1'b0}};
bias_[ 29 ] <= {DW{1'b0}};
bias_[ 30 ] <= {DW{1'b0}};
bias_[ 31 ] <= {DW{1'b0}};
end
else if( en_i == 1'b1 )
case( addr_i )
5'd0:
begin
bias_[ 0 ] <= data_i;
end
5'd1:
begin
bias_[ 1 ] <= data_i;
end
5'd2:
begin
bias_[ 2 ] <= data_i;
end
5'd3:
begin
bias_[ 3 ] <= data_i;
end
5'd4:
begin
bias_[ 4 ] <= data_i;
end
5'd5:
begin
bias_[ 5 ] <= data_i;
end
5'd6:
begin
bias_[ 6 ] <= data_i;
end
5'd7:
begin
bias_[ 7 ] <= data_i;
end
5'd8:
begin
bias_[ 8 ] <= data_i;
end
5'd9:
begin
bias_[ 9 ] <= data_i;
end
5'd10:
begin
bias_[ 10 ] <= data_i;
end
5'd11:
begin
bias_[ 11 ] <= data_i;
end
5'd12:
begin
bias_[ 12 ] <= data_i;
end
5'd13:
begin
bias_[ 13 ] <= data_i;
end
5'd14:
begin
bias_[ 14 ] <= data_i;
end
5'd15:
begin
bias_[ 15 ] <= data_i;
end
5'd16:
begin
bias_[ 16 ] <= data_i;
end
5'd17:
begin
bias_[ 17 ] <= data_i;
end
5'd18:
begin
bias_[ 18 ] <= data_i;
end
5'd19:
begin
bias_[ 19 ] <= data_i;
end
5'd20:
begin
bias_[ 20 ] <= data_i;
end
5'd21:
begin
bias_[ 21 ] <= data_i;
end
5'd22:
begin
bias_[ 22 ] <= data_i;
end
5'd23:
begin
bias_[ 23 ] <= data_i;
end
5'd24:
begin
bias_[ 24 ] <= data_i;
end
5'd25:
begin
bias_[ 25 ] <= data_i;
end
5'd26:
begin
bias_[ 26 ] <= data_i;
end
5'd27:
begin
bias_[ 27 ] <= data_i;
end
5'd28:
begin
bias_[ 28 ] <= data_i;
end
5'd29:
begin
bias_[ 29 ] <= data_i;
end
5'd30:
begin
bias_[ 30 ] <= data_i;
end
5'd31:
begin
bias_[ 31 ] <= data_i;
end
endcase
end
/*
* output
*/
genvar i;
generate
for( i = 0; i < PACKAGE_NUM; i = i + 1)
begin:pack_out
assign bias_o[ (i+1)*DW-1:i*DW ] = bias_[ i ];
end // end pack_out
endgenerate
endmodule
| 7.142111 |
module bibi (
clk,
rst,
Borrow,
Borrowf
);
//led for Alert
// input/ output
input clk, rst;
output [3:0] Borrow;
output [3:0] Borrowf;
// wiring
wire clk, rst;
// save value place
reg [3:0] Counterr = 0;
reg [3:0] Counterg = 15;
assign Borrow[3:0] = Counterr[3:0];
assign Borrowf[3:0] = Counterg[3:0];
always @(posedge clk or posedge ~rst) begin
if (rst == 0) begin
Counterg = 15;
Counterr = 0;
end else begin
Counterr = ~Counterg;
Counterg = ~Counterg;
end
end
endmodule
| 7.906747 |
module BiCubic (
input clk,
input rst_n,
input [8:0] coeffOne,
input [8:0] coeffHalf,
input [8:0] yBlend,
bi_a,
xBlend,
output [8:0] bi_y0,
bi_y1,
bi_y2,
bi_y3,
bi_x0,
bi_x1,
bi_x2,
bi_x3
);
BiCubic_y3 BiCubic_y3_inst (
.clk (clk),
.rst_n (rst_n),
.coeffOne (coeffOne),
.coeffHalf(coeffHalf),
.yBlend (yBlend),
.bi_a (bi_a),
.bi_y3 (bi_y3)
);
BiCubic_y2 BiCubic_y2_inst (
.clk (clk),
.rst_n (rst_n),
.coeffOne (coeffOne),
.coeffHalf(coeffHalf),
.yBlend (yBlend),
.bi_a (bi_a),
.bi_y2 (bi_y2)
);
BiCubic_y1 BiCubic_y1_inst (
.clk (clk),
.rst_n (rst_n),
.coeffHalf(coeffHalf),
.yBlend (yBlend),
.bi_a (bi_a),
.bi_y1 (bi_y1)
);
BiCubic_y0 BiCubic_y0_inst (
.clk (clk),
.rst_n (rst_n),
.coeffOne (coeffOne),
.coeffHalf(coeffHalf),
.yBlend (yBlend),
.bi_a (bi_a),
.bi_y0 (bi_y0)
);
///////////////////////////////////////////////
BiCubic_x3 BiCubic_x3_inst (
.clk (clk),
.rst_n (rst_n),
.coeffOne (coeffOne),
.coeffHalf(coeffHalf),
.xBlend (xBlend),
.bi_a (bi_a),
.bi_x3 (bi_x3)
);
BiCubic_x2 BiCubic_x2_inst (
.clk (clk),
.rst_n (rst_n),
.coeffOne (coeffOne),
.coeffHalf(coeffHalf),
.xBlend (xBlend),
.bi_a (bi_a),
.bi_x2 (bi_x2)
);
BiCubic_x1 BiCubic_x1_inst (
.clk (clk),
.rst_n (rst_n),
.coeffHalf(coeffHalf),
.xBlend (xBlend),
.bi_a (bi_a),
.bi_x1 (bi_x1)
);
BiCubic_x0 BiCubic_x0_inst (
.clk (clk),
.rst_n (rst_n),
.coeffOne (coeffOne),
.coeffHalf(coeffHalf),
.xBlend (xBlend),
.bi_a (bi_a),
.bi_x0 (bi_x0)
);
endmodule
| 6.526083 |
module BiCubic_y2 (
input clk,
input rst_n,
input [8:0] coeffOne,
input [8:0] coeffHalf,
input [8:0] yBlend,
bi_a,
output [8:0] bi_y2
);
reg [9:0] mul_x, mul_4_a;
reg [9:0] mul_3_a;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
mul_4_a <= 10'd0;
mul_3_a <= 10'd0;
mul_x <= 10'd0;
end else begin
mul_4_a <= (2 << 8) - bi_a;
mul_3_a <= (3 << 8) - bi_a;
mul_x <= coeffOne - yBlend;
end
end
wire [39:0] BiCubic_1_4;
mul_4 mul_4_y2_inst (
.clk (clk),
.rst_n (rst_n),
.a (mul_4_a),
.b (mul_x),
.c (mul_x),
.d (mul_x),
.result(BiCubic_1_4)
);
wire [37:0] BiCubic_1_3;
mul_3 mul_3_y2_inst (
.clk (clk),
.rst_n (rst_n),
.a ({8'd0, mul_3_a}),
.b (mul_x),
.c (mul_x),
.result(BiCubic_1_3)
);
mul_add_1 mul_add_1_y2_inst (
.clk (clk),
.rst_n (rst_n),
.a (BiCubic_1_4),
.b (BiCubic_1_3),
.c (1'b1),
.coeffHalf(coeffHalf),
.result (bi_y2)
);
endmodule
| 6.645861 |
module bidin (
// Input Ports
clk6,
rst_n,
bidin_sync_in,
bidin_ena_in,
bidin_din,
ldpc_req,
ldpc_fin,
// Output Ports
bidin_rdy,
bidin_full,
bidin_ena_out,
bidin_dout
);
parameter WID = 6;
//Input ports declaration
input clk6, rst_n;
input bidin_sync_in;
input bidin_ena_in;
input [WID-1:0] bidin_din;
input ldpc_req;
input ldpc_fin;
//Output ports declaration
output bidin_rdy;
output bidin_ena_out;
output [WID-1:0] bidin_dout;
output bidin_full;
////////////////////////////////////////////////
//signal declaration
//
wire [ 17:0] main_addr;
wire [WID-1:0] main_data_i;
wire [WID-1:0] main_data_o;
wire main_en;
wire main_wr;
main_man u_main_man (
.clk (clk6),
.rst_n (rst_n),
.bidin_sync_in(bidin_sync_in),
.bidin_ena_in (bidin_ena_in),
.bidin_din (bidin_din),
.ldpc_req (ldpc_req),
.ldpc_fin (ldpc_fin),
.bidin_rdy (bidin_rdy),
.bidin_full (bidin_full),
.bidin_ena_out(bidin_ena_out),
.bidin_dout (bidin_dout),
.main_addr (main_addr),
.main_data_i(main_data_i),
.main_data_o(main_data_o),
.main_en (main_en),
.main_wr (main_wr)
);
sram146880x6 u_sram146880x6 (
.A (main_addr),
.CLK(clk6),
.D (main_data_i),
.Q (),
.CEN(!main_en),
.WEN(!main_wr)
);
/*
sram146880x6 u_sram146880x6(
.addr (main_addr ),
.clk (clk6 ),
.din (main_data_i),
.dout (main_data_o),
.en (main_en ),
.we (main_wr )
);
*/
sram147456x6 u1 (
.A (main_addr),
.CLK(clk6),
.D (main_data_i),
.Q (main_data_o),
.CE (main_en),
.WE (main_wr)
);
endmodule
| 6.649959 |
module bidirec (
input wire oe,
input wire inp,
output wire outp,
output wire bidir
);
assign bidir = oe ? inp : 1'bZ;
assign outp = bidir;
endmodule
| 7.291187 |
module shift_register_bidirectional (
Q3,
Q2,
Q1,
Q0,
D3,
D2,
D1,
D0,
S1,
S0,
CLK
);
output Q3; // Register output most significant bit.
output Q2;
output Q1;
output Q0; // Register output least significant bit.
input D3; // Register input most significant bit.
input D2;
input D1;
input D0; // Register input least significant bit.
input S1; // MUX selector most significant bit.
input S0; // MUX selector least significant bit.
input CLK;
wire Q3n, Q2n, Q1n, Q0n;
wire X3, X2, X1, X0;
multiplexer_4_1 #(1) mux0 (
X0,
Q3,
Q1,
Q0,
D0,
S1,
S0
);
d_flip_flop_edge_triggered dff0 (
Q0,
Q0n,
CLK,
X0
);
multiplexer_4_1 #(1) mux1 (
X1,
Q0,
Q2,
Q1,
D1,
S1,
S0
);
d_flip_flop_edge_triggered dff1 (
Q1,
Q1n,
CLK,
X1
);
multiplexer_4_1 #(1) mux2 (
X2,
Q1,
Q3,
Q2,
D2,
S1,
S0
);
d_flip_flop_edge_triggered dff2 (
Q2,
Q2n,
CLK,
X2
);
multiplexer_4_1 #(1) mux3 (
X3,
Q2,
Q0,
Q3,
D3,
S1,
S0
);
d_flip_flop_edge_triggered dff3 (
Q3,
Q3n,
CLK,
X3
);
endmodule
| 6.854847 |
module multiplexer_4_1 (
X,
A0,
A1,
A2,
A3,
S1,
S0
);
parameter WIDTH = 16; // How many bits wide are the lines
output [WIDTH-1:0] X; // The output line
input [WIDTH-1:0] A3; // Input line with id 2'b11
input [WIDTH-1:0] A2; // Input line with id 2'b10
input [WIDTH-1:0] A1; // Input line with id 2'b01
input [WIDTH-1:0] A0; // Input line with id 2'b00
input S0; // Least significant selection bit
input S1; // Most significant selection bit
assign X = (S1 == 0 ? (S0 == 0 ? A0 // {S1,S0} = 2'b00
: A1) // {S1,S0} = 2'b01
: (S0 == 0 ? A2 // {S1,S0} = 2'b10
: A3)); // {S1,S0} = 2'b11
endmodule
| 7.168392 |
module d_flip_flop_edge_triggered (
Q,
Qn,
C,
D
);
output Q;
output Qn;
input C;
input D;
wire Cn; // Control input to the D latch.
wire Cnn; // Control input to the SR latch.
wire DQ; // Output from the D latch, inputs to the gated SR latch.
wire DQn; // Output from the D latch, inputs to the gated SR latch.
not (Cn, C);
not (Cnn, Cn);
d_latch dl (
DQ,
DQn,
Cn,
D
);
sr_latch_gated sr (
Q,
Qn,
Cnn,
DQ,
DQn
);
endmodule
| 7.348263 |
module d_latch (
Q,
Qn,
G,
D
);
output Q;
output Qn;
input G;
input D;
wire Dn;
wire D1;
wire Dn1;
not (Dn, D);
and (D1, G, D);
and (Dn1, G, Dn);
nor (Qn, D1, Q);
nor (Q, Dn1, Qn);
endmodule
| 6.881555 |
module bidirectional_io #(
parameter WIDTH = 16
) (
input output_enable,
input [WIDTH-1:0] data,
inout [WIDTH-1:0] bidir_variable,
output [WIDTH-1:0] read_buffer
);
// If we are using the bidir as an output, assign it an output value,
// otherwise assign it high-impedence
assign bidir_variable = (output_enable ? data : {WIDTH{1'bz}});
// Read in the current value of the bidir port, which comes either
// from the input or from the previous assignment.
assign read_buffer = bidir_variable;
endmodule
| 8.762018 |
module bidir_data #(
parameter N = 8
) (
input en,
input clk,
inout [N-1:0] bidir
);
reg [N-1:0] temp;
assign bidir = en ? temp : 8'bz;
always @(posedge clk)
if (en) temp = bidir;
else temp = temp + 1;
endmodule
| 6.655626 |
module bidir_data #(
parameter N = 8
) (
input en,
input clk,
inout [N-1:0] bidir
);
reg [N-1:0] temp;
assign bidir = en ? temp : 8'bz;
always @(posedge clk)
if (en) temp = bidir;
else temp = temp + 1;
endmodule
| 6.655626 |
module bidir_pad (
in,
out,
io,
oen
);
input in, oen;
output out;
inout io;
assign io = !oen ? in : 1'bz; //input enabled, io working as an output
assign out = oen ? io : 1'bz; //output enable, io working as an input
endmodule
| 6.679273 |
module bidi_register (
RESET, // syncronous reset (active low)
CLOCK, // clock
RW, // high for read, low for write
ENABLE, // enable bus access (active high)
COUNT, // incriment register (active high)
DATA // data bus connection
);
// PARAMETERS
parameter BUS_WIDTH = 16;
parameter COUNT_EN = 1;
// INPUTS
input wire RESET;
input wire CLOCK;
input wire RW;
input wire ENABLE;
input wire COUNT;
// OUTPUT
inout wire [BUS_WIDTH-1:0] DATA;
reg [BUS_WIDTH-1:0] INTERNAL_DATA;
always @(posedge CLOCK) begin
if (!RESET) begin
// set the internal bus to 0
INTERNAL_DATA <= {BUS_WIDTH{1'b0}};
end // only increment if the functionality is enabled and we are not reading
// in data from the bus and the count operation is specified
else if (ENABLE && RW == 0) begin
INTERNAL_DATA <= DATA;
end else if ((!ENABLE || ENABLE && !RW) && COUNT_EN && COUNT) begin
INTERNAL_DATA <= INTERNAL_DATA + 1;
end
end
assign DATA = (ENABLE && RW == 1) ? INTERNAL_DATA : {BUS_WIDTH{1'bz}};
endmodule
| 7.023944 |
module bidi_register_output (
RESET, // syncronous reset (active low)
CLOCK, // clock
RW, // high for read, low for write
ENABLE, // enable bus access (active high)
COUNT, // incriment register (active high)
DATA, // data bus connection
OUTPUT // wire that constantly outputs register contents
);
// PARAMETERS
parameter BUS_WIDTH = 16;
parameter COUNT_EN = 1;
// INPUTS
input wire RESET;
input wire CLOCK;
input wire RW;
input wire ENABLE;
input wire COUNT;
// OUTPUT
inout wire [BUS_WIDTH-1:0] DATA;
output wire [BUS_WIDTH-1:0] OUTPUT;
reg [BUS_WIDTH-1:0] INTERNAL_DATA;
always @(posedge CLOCK) begin
if (!RESET) begin
// set the internal bus to 0
INTERNAL_DATA <= {BUS_WIDTH{1'b0}};
end // only increment if the functionality is enabled and we are not reading
// in data from the bus and the count operation is specified
else if (ENABLE && RW == 0) begin
INTERNAL_DATA <= DATA;
end else if ((!ENABLE || ENABLE && !RW) && COUNT_EN && COUNT) begin
INTERNAL_DATA <= INTERNAL_DATA + 1;
end
end
assign DATA = (ENABLE && RW == 1) ? INTERNAL_DATA : {BUS_WIDTH{1'bz}};
assign OUTPUT = INTERNAL_DATA;
endmodule
| 7.023944 |
module bidi_reg_tb ();
wire RESET;
wire CLOCK;
wire RW;
wire ENABLE;
wire COUNT;
wire [15:0] DATA;
bidi_reg_stim my_stim (
.RESET(RESET),
.CLOCK(CLOCK),
.RW(RW),
.ENABLE(ENABLE),
.COUNT(COUNT),
.DATA_OUT(DATA),
.DATA_IN(DATA)
);
bidi_register my_register (
.RESET(RESET),
.CLOCK(CLOCK),
.RW(RW),
.ENABLE(ENABLE),
.COUNT(COUNT),
.DATA(DATA)
);
endmodule
| 6.573153 |
module RS (
output wire Q,
output wire NQ,
input wire R,
input wire S
);
nor (Q, R, NQ);
nor (NQ, S, Q);
endmodule
| 7.891872 |
module D (
output reg Q,
input wire D,
input wire C
);
initial Q = 0;
always @(negedge C) Q = D;
endmodule
| 7.927017 |
module testD;
reg [1:0] CD;
wire Q;
D d (
Q,
CD[0],
CD[1]
);
always #7 CD[1] = ~CD[1];
initial begin
$monitor($time, " | | C: %b, D: %b, Q: %b", CD[1], CD[0], Q);
$dumpfile("saluda.dmp");
$dumpvars;
CD[1] = 0;
CD[0] = 0;
#5 CD[0] = 1;
#15 CD[0] = 0;
#5 CD[0] = 1;
#15 CD[0] = 0;
#30 #15 CD[0] = 1;
#15 CD[0] = 0;
$dumpoff;
$finish;
end
endmodule
| 7.380768 |
module D (
output reg Q,
input wire D,
input wire C,
input wire nCLR
);
initial Q = 0;
always @(negedge C) if (nCLR) Q = #1 D;
always @(nCLR) if (!nCLR) Q = 0;
endmodule
| 7.927017 |
module SISO4bits (
output wire O,
input wire I,
input wire C,
input wire nCLR
);
wire d3s, d2s, d1s;
D d0 (
O,
d1s,
C,
nCLR
);
D d1 (
d1s,
d2s,
C,
nCLR
);
D d2 (
d2s,
d3s,
C,
nCLR
);
D d3 (
d3s,
I,
C,
nCLR
);
endmodule
| 7.295984 |
module testD;
reg [1:0] CD;
reg nClear;
wire Q;
SISO4bits d (
Q,
CD[0],
CD[1],
nClear
);
always #7 CD[1] = ~CD[1];
initial begin
$monitor($time, " | | %b%b%b%b | C: %b, I: %b, nCLR: %b, Q: %b", d.d3.Q, d.d2.Q, d.d1.Q,
d.d0.Q, CD[1], CD[0], nClear, Q);
$dumpfile("salida.dmp");
$dumpvars;
CD[1] = 0;
CD[0] = 0;
nClear = 1;
#5 CD[0] = 1;
#30 #5 nClear = 0;
#5 nClear = 1;
#15 CD[0] = 1;
#15 CD[0] = 0;
#65 nClear = 0;
CD[0] = 1;
#12 nClear = 1;
#14 CD[0] = 0;
#14 CD[0] = 1;
#14 CD[0] = 0;
#14 CD[0] = 1;
#14 CD[0] = 1;
#14 CD[0] = 1;
#14 CD[0] = 0;
#14 CD[0] = 0;
#15 $dumpoff;
$finish;
end
endmodule
| 7.380768 |
module D (
output reg Q,
input wire D,
input wire C,
input wire nCLR
);
initial Q = 0;
always @(negedge C) if (nCLR) Q = #1 D;
always @(nCLR) if (!nCLR) Q = 0;
endmodule
| 7.927017 |
module SIPO4bits (
output wire [3:0] O,
input wire I,
input wire C,
input wire nCLR
);
wire d3s, d2s, d1s;
D d0 (
O[0],
O[1],
C,
nCLR
);
D d1 (
O[1],
O[2],
C,
nCLR
);
D d2 (
O[2],
O[3],
C,
nCLR
);
D d3 (
O[3],
I,
C,
nCLR
);
endmodule
| 7.2239 |
module testD;
reg [1:0] CD;
reg nClear;
wire [3:0] Q;
SIPO4bits d (
Q,
CD[0],
CD[1],
nClear
);
always #7 CD[1] = ~CD[1];
initial begin
$monitor($time, " | | %b%b%b%b | C: %b, I: %b, nCLR: %b, Q: %b", d.d3.Q, d.d2.Q, d.d1.Q,
d.d0.Q, CD[1], CD[0], nClear, Q);
$dumpfile("salida.dmp");
$dumpvars;
CD[1] = 0;
CD[0] = 0;
nClear = 1;
#5 CD[0] = 1;
#30 #5 nClear = 0;
#5 nClear = 1;
#15 CD[0] = 1;
#15 CD[0] = 0;
#65 nClear = 0;
CD[0] = 1;
#12 nClear = 1;
#14 CD[0] = 0;
#14 CD[0] = 1;
#14 CD[0] = 0;
#14 CD[0] = 1;
#14 CD[0] = 1;
#14 CD[0] = 1;
#14 CD[0] = 0;
#14 CD[0] = 0;
#15 $dumpoff;
$finish;
end
endmodule
| 7.380768 |
module JKUp (
output reg Q,
output wire NQ,
input wire J,
input wire K,
input wire C,
input wire nPRESET,
input wire nCLEAR
);
not (NQ, Q);
initial Q = 0;
always @(posedge C) begin
if (nPRESET && nCLEAR)
case ({
J, K
})
2'b01: Q = 0; // RESET
2'b10: Q = 1; // SET
2'b11: Q = ~Q; // Complemento
endcase
end
always @(nPRESET, nCLEAR)
case ({
nPRESET, nCLEAR
})
2'b01: Q = 1;
2'b10: Q = 0;
endcase
endmodule
| 7.971081 |
module RS (
output reg Q,
output wire NQ,
input wire R,
input wire S,
input wire C,
input wire nCLR
);
initial Q = 0;
not (NQ, Q);
always @(negedge C)
if (nCLR)
case ({
R, S
})
2'b01: Q = #1 1;
2'b10: Q = #1 0;
endcase
always @(nCLR) if (!nCLR) Q = 0;
endmodule
| 7.891872 |
module RS1bit (
output wire O,
input wire SP,
input wire Is,
input wire Ip,
input wire C,
input wire nCLR
);
wire nI, IsSP, IpNsp, nsp1, I;
not (nsp1, SP);
and (IsSP, Is, SP);
and (IpNsp, Ip, nsp1);
nor (nI, IsSP, IpNsp);
not (I, nI);
RS rs1 (
O
,,
nI,
I,
C,
nCLR
);
endmodule
| 8.659726 |
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