code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux1 (
select,
I,
O
);
input [1:0] select;
input [3:0] I;
output O;
reg O;
wire [1:0] select;
wire [3:0] I;
always @(I or select) begin
O = I[select];
end
endmodule
| 7.278164 |
module encoderBehavioural4x1 (
D,
A,
B,
V
);
input [3:0] D;
wire [3:0] D;
output A, B, V;
reg A, B, V;
always @(D) begin
if (D[3] == 1) begin
{A, B, V} = 3'b111;
end else if (D[2] == 1) begin
{A, B, V} = 3'b101;
end else if (D[1] == 1) begin
{A, B, V} = 3'b011;
... | 6.924855 |
module behavioural_alu (
X,
Y,
op_code,
Z,
zero,
overflow,
equal
);
//port definitions
input wire [31:0] X, Y;
input wire [3:0] op_code;
output reg [31:0] Z;
output reg overflow;
output wire zero, equal;
assign zero = Z == 0;
assign equal = X == Y;
wire signed [31:0] X_... | 8.107612 |
module behavioural_example (
input a,
input b,
input c,
input d,
output reg out // Behavioral modelling requires the use of registers but doesn't always synthesize any registers
);
// Any values set within a procedural block like below must be registers
always @(a, b, c, d) begin // The procedu... | 7.58543 |
module mem_ext (
input W0_clk,
input [24:0] W0_addr,
input W0_en,
input [63:0] W0_data,
input [7:0] W0_mask,
input R0_clk,
input [24:0] R0_addr,
input R0_en,
output [63:0] R0_data
);
reg [24:0] reg_R0_addr;
reg [63:0] ram[33554431:0];
`ifdef RANDOMIZE
integer initvar;
initia... | 6.504032 |
module Beha_BitStream_ram (
clk,
BitStream_ram_ren,
BitStream_ram_addr,
BitStream_ram_data
);
input clk;
input BitStream_ram_ren;
input [16:0] BitStream_ram_addr;
output [15:0] BitStream_ram_data;
reg [15:0] BitStream_ram_data;
reg [15:0] BitStream_ram[0:`Beha_Bitstream_ram_size];
initi... | 7.240745 |
module rvdff (
din,
clk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
output reg [WIDTH - 1:0] dout;
generate
if (SHORT == 1) begin
wire [WIDTH:1] sv2v_tmp_70387;
assign sv2v_tmp_70387 = din;
... | 6.770624 |
module rvdffs (
din,
en,
clk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
generate
if (SHORT == 1) begin : genblock
assign dout = din;
end else be... | 7.528373 |
module rvdffsc (
din,
en,
clear,
clk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clear;
input wire clk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
wire [WIDTH - 1:0] din_new;
generate
if (SHORT =... | 6.896162 |
module rvdff_fpga (
din,
clk,
clken,
rawclk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire clken;
input wire rawclk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
generate
if (SHORT == 1) begin
as... | 6.743502 |
module rvdffs_fpga (
din,
en,
clk,
clken,
rawclk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clk;
input wire clken;
input wire rawclk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
generate
if (... | 7.21158 |
module rvdffsc_fpga (
din,
en,
clear,
clk,
clken,
rawclk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clear;
input wire clk;
input wire clken;
input wire rawclk;
input wire rst_l;
output wire [WIDTH ... | 6.900591 |
module rvdffe (
din,
en,
clk,
rst_l,
scan_mode,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
parameter OVERRIDE = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clk;
input wire rst_l;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
wire l1clk;
generat... | 6.889647 |
module rvdffpcie (
din,
clk,
rst_l,
en,
scan_mode,
dout
);
parameter WIDTH = 31;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire en;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
generate
if (WIDTH == 31) begin : genblock
rvdffs #(WIDT... | 7.019589 |
module rvdfflie (
din,
clk,
rst_l,
en,
scan_mode,
dout
);
parameter WIDTH = 16;
parameter LEFT = 8;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire en;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
localparam EXTRA = WIDTH - LEFT;
localparam... | 7.809887 |
module rvdffppe (
din,
clk,
rst_l,
en,
scan_mode,
dout
);
parameter WIDTH = 32;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire en;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
localparam RIGHT = 31;
localparam LEFT = WIDTH - RIGHT;
localpa... | 7.61669 |
module rvdffie (
din,
clk,
rst_l,
scan_mode,
dout
);
parameter WIDTH = 1;
parameter OVERRIDE = 0;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
wire l1clk;
wire en;
generate
if ((WIDTH >= 8) || (OVERRIDE ... | 7.531107 |
module rvdffiee (
din,
clk,
rst_l,
scan_mode,
en,
dout
);
parameter WIDTH = 1;
parameter OVERRIDE = 0;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire scan_mode;
input wire en;
output wire [WIDTH - 1:0] dout;
wire l1clk;
wire final_en;
generate
... | 7.373131 |
module rvsyncss (
clk,
rst_l,
din,
dout
);
parameter WIDTH = 251;
input wire clk;
input wire rst_l;
input wire [WIDTH - 1:0] din;
output wire [WIDTH - 1:0] dout;
wire [WIDTH - 1:0] din_ff1;
rvdff #(WIDTH) sync_ff1 (
.clk (clk),
.rst_l(rst_l),
.din (din[WIDTH-1:0]),
... | 7.513657 |
module rvsyncss_fpga (
gw_clk,
rawclk,
clken,
rst_l,
din,
dout
);
parameter WIDTH = 251;
input wire gw_clk;
input wire rawclk;
input wire clken;
input wire rst_l;
input wire [WIDTH - 1:0] din;
output wire [WIDTH - 1:0] dout;
wire [WIDTH - 1:0] din_ff1;
rvdff_fpga #(WIDTH) sync_... | 6.689062 |
module rvbradder (
pc,
offset,
dout
);
input [31:1] pc;
input [12:1] offset;
output [31:1] dout;
wire cout;
wire sign;
wire [31:13] pc_inc;
wire [31:13] pc_dec;
assign {cout, dout[12:1]} = {1'b0, pc[12:1]} + {1'b0, offset[12:1]};
assign pc_inc[31:13] = pc[31:13] + 1;
assign pc_dec[31:13]... | 6.926817 |
module rvmaskandmatch (
mask,
data,
masken,
match
);
parameter WIDTH = 32;
input wire [WIDTH - 1:0] mask;
input wire [WIDTH - 1:0] data;
input wire masken;
output wire match;
wire [WIDTH - 1:0] matchvec;
wire masken_or_fullmask;
assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]);
... | 6.789232 |
module rveven_paritygen (
data_in,
parity_out
);
parameter WIDTH = 16;
input wire [WIDTH - 1:0] data_in;
output wire parity_out;
assign parity_out = ^data_in[WIDTH-1:0];
endmodule
| 7.582388 |
module rveven_paritycheck (
data_in,
parity_in,
parity_err
);
parameter WIDTH = 16;
input wire [WIDTH - 1:0] data_in;
input wire parity_in;
output wire parity_err;
assign parity_err = ^data_in[WIDTH-1:0] ^ parity_in;
endmodule
| 7.582388 |
module rvecc_encode (
din,
ecc_out
);
input [31:0] din;
output [6:0] ecc_out;
wire [5:0] ecc_out_temp;
assign ecc_out_temp[0] = ((((((((((((((((din[0] ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ di... | 6.742612 |
module rvecc_decode (
en,
din,
ecc_in,
sed_ded,
dout,
ecc_out,
single_ecc_error,
double_ecc_error
);
input en;
input [31:0] din;
input [6:0] ecc_in;
input sed_ded;
output [31:0] dout;
output [6:0] ecc_out;
output single_ecc_error;
output double_ecc_error;
wire [ 6:0] ec... | 7.998635 |
module rvecc_decode_64 (
en,
din,
ecc_in,
ecc_error
);
input en;
input [63:0] din;
input [6:0] ecc_in;
output ecc_error;
wire [6:0] ecc_check;
assign ecc_check[0] = ((((((((((((((((((((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^... | 7.152969 |
module rvoclkhdr (
en,
clk,
scan_mode,
l1clk
);
input wire en;
input wire clk;
input wire scan_mode;
output wire l1clk;
wire SE;
assign SE = 0;
assign l1clk = clk;
endmodule
| 6.621004 |
module belfft (
clk_i,
rst_i,
m_address,
m_readdata,
m_writedata,
m_read,
m_write,
m_waitrequest,
m_readdatavalid,
s_address,
s_readdata,
s_writedata,
s_read,
s_write,
s_byteenable,
s_waitrequest,
s_readdatavalid,
int_o
);
input clk_i;
inpu... | 6.558375 |
module belfft_twiddle_roms (
clk_i,
rst_i,
adr_i,
rd_i,
dat_o,
cfg_sel_i
);
parameter word_width = 16;
parameter config_num = 1;
parameter max_awidth = 6;
parameter size = 256;
parameter awidth = 6;
parameter file_name = "bel_rom_twiddles.dat";
parameter size2 = 256;
parameter... | 7.191166 |
module bel_avl_ram (
clk_i,
rst_i,
address,
readdata,
writedata,
read,
write,
readdatavalid
);
parameter size = 64;
parameter adr_width = 6;
parameter input_file_name = "bel_avl_ram_in.dat";
parameter output_file_name = "bel_avl_ram_out.dat";
parameter log_file_name = "bel_wb_... | 7.563028 |
module bel_cadd (
a_re_i,
a_im_i,
b_re_i,
b_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
input signed [word_width - 1:0] b_re_i;
input signed [word_width - 1:0] b_im_i;
output signed [word_width -... | 6.706295 |
module bel_caddsub (
a_re_i,
a_im_i,
b_re_i,
b_im_i,
x_re_o,
x_im_o,
inv_i
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
input signed [word_width - 1:0] b_re_i;
input signed [word_width - 1:0] b_im_i;
output signed... | 6.884033 |
module bel_cdiv2 (
a_re_i,
a_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
output signed [word_width - 1:0] x_re_o;
output signed [word_width - 1:0] x_im_o;
assign x_re_o = (a_re_i + 1) >>> 1;
assign x_... | 6.832418 |
module bel_cdiv4 (
a_re_i,
a_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
output signed [word_width - 1:0] x_re_o;
output signed [word_width - 1:0] x_im_o;
assign x_re_o = (a_re_i + 2) >>> 2;
assign x_... | 7.14204 |
module bel_cmac (
a_re_i,
a_im_i,
b_re_i,
b_im_i,
c_re_i,
c_im_i,
x_re_o,
x_im_o
);
input signed [15:0] a_re_i;
input signed [15:0] a_im_i;
input signed [15:0] b_re_i;
input signed [15:0] b_im_i;
input signed [15:0] c_re_i;
input signed [15:0] c_im_i;
output signed [15:0] ... | 6.662693 |
module bel_cmul (
clk_i,
pipe_halt,
a_re_i,
a_im_i,
b_re_i,
b_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input clk_i;
input pipe_halt;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
input signed [word_width - 1:0] b_re_i;
input sig... | 7.168749 |
module bel_csub (
a_re_i,
a_im_i,
b_re_i,
b_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
input signed [word_width - 1:0] b_re_i;
input signed [word_width - 1:0] b_im_i;
output signed [word_width -... | 7.162353 |
module bel_fft_avl_sif (
clk_i,
rst_i,
address,
readdata,
writedata,
read,
write,
byteenable,
waitrequest,
readdatavalid,
adr_o,
dat_i,
dat_o,
bsel_o,
wr_o,
rd_o,
ack_i,
err_i
);
input clk_i;
input rst_i;
input [`BEL_FFT_SIF_AWIDTH - 1:0]... | 7.399401 |
module bemicro_cva9_jtaguart (
input CLK_24MHZ,
output [7:0] USER_LED
);
wire clock = CLK_24MHZ;
wire reset = 0;
reg tx_valid = 1;
wire tx_ready;
reg [ 7:0] tx_data = 8'd65;
wire rx_valid;
wire rx_ready = 1;
wire [ 7:0] rx_data;
reg [28:0... | 6.964646 |
module clk_div (
input clk_in,
output reg clk_div
);
reg [32:0] counter;
always @(posedge clk_in) begin
counter <= counter + 1;
if (counter >= 3) begin
counter <= 0;
clk_div <= ~clk_div;
end
end
endmodule
| 7.520262 |
module testbench;
parameter pmem_width = 11;
parameter dmem_width = 13;
// navre inputs
reg clk;
reg rst;
reg [15:0] pmem_d;
reg [7:0] dmem_di;
reg [7:0] io_di;
reg [7:0] irq;
// navre outputs
wire pmem_ce;
wire [pmem_width-1:0] pmem_a;
wire dmem_we;
wire [dmem_width-1:0] dmem_a;
wire [... | 7.015571 |
module TestBench ();
reg Clk = 0;
Mips_CPU cpu (Clk);
always #1 Clk = ~Clk;
endmodule
| 7.747207 |
module bench_closure;
reg clk, reset;
localparam width = 8;
localparam depth = 7;
localparam usz = $clog2(depth + 1);
initial clk = 0;
always #10 clk = ~clk;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [width-1:0] chk_data; // From closure of sd_... | 6.548193 |
module bench_qnr_top();
//
// internal wires
//
reg clk;
reg rst;
reg dstrb;
reg [11:0] din;
wire den;
wire [10:0] dout;
reg [ 7:0] qnt_val;
integer z, d;
integer err_cnt;
//
// QNR unit
//
jpeg_qnr #(12) dut (
.clk(clk),
.ena(1'b1),
.rst(rst),
.dstrb(dstrb),
.din(din),
.qnt_val(qnt_v... | 6.566055 |
module input_switch #(
parameter WIDTH = 16
) (
y,
z,
in
);
output [WIDTH-1:0] y, z;
input [WIDTH-1:0] in;
assign y = in;
assign z = in;
endmodule
| 8.723474 |
module output_switch #(
parameter WIDTH = 16
) (
y,
in0,
in1,
sel
);
output [WIDTH-1:0] y;
input [WIDTH-1:0] in0, in1;
input sel;
// If select is 0, output from horizontal
// If select is 1, output from diagonal
benes_mux #(
.W(WIDTH)
) mux0 (
.o (y),
.a (in0),
... | 9.44405 |
module switch #(
parameter WIDTH = 16
) (
y,
z,
in0,
in1,
sel0,
sel1
);
output [WIDTH-1:0] y, z;
input [WIDTH-1:0] in0, in1;
input sel0, sel1;
// If select is 0, then pass input from horizontal
// If select is 1, then pass input from diagonal
// y output goes to horizontal
//... | 9.51356 |
module benes_mux #(
parameter W = 16
) (
o,
a,
b,
sel
);
output reg [W-1:0] o;
input [W-1:0] a, b;
input sel;
always @(sel or a or b) begin
o = sel ? b : a;
end
endmodule
| 6.982245 |
module benja (
input clk,
input [7:0] in,
output reg signal
);
always @(posedge clk) begin
case (in)
8'b0001000011: signal = 1'b0;
8'b0001001011: signal = 1'b0;
8'b0001001001: signal = 1'b0;
8'b0001010011: signal = 1'b0;
8'b0001010001: signal = 1'b0;
8'b0001011011: ... | 6.914128 |
module BENLogic (
input clk,
input [2:0] IR11to9,
input N,
input Zero,
input P,
output reg BEN
);
wire BENResult;
assign BENResult = (IR11to9[2] & N) | (IR11to9[1] & Zero) | (IR11to9[0] & P);
always @(posedge clk) begin
BEN <= BENResult;
end
endmodule
| 6.644731 |
module BEQ_Detection (
Branch_i,
RS1data_i,
RS2data_i,
BranchTaken_o
);
input Branch_i;
input [31:0] RS1data_i;
input [31:0] RS2data_i;
output BranchTaken_o;
assign BranchTaken_o = (RS1data_i == RS2data_i) & Branch_i;
endmodule
| 7.262378 |
module ber_prbsnoise (
input clock,
input reset,
input [1:0] select_gen,
input [1:0] noise_gen,
output prbs_out
);
//variable declaration
//-------------- prbsnoise generaration variables
//for generation
reg [22:0] shiftreg;
reg feedback;
reg prbsbuffer;
//for error generation
int... | 6.97924 |
module best_lap_time_char_rom (
input wire [15:0] char_xy,
input wire [15:0] best_lap_time,
output reg [ 6:0] char_code // pixels of the character line
);
wire [3:0] bcd0, bcd1, bcd2, bcd3, minutes;
bin2bcd(
.bin(best_lap_time), .bcd0(bcd0), .bcd1(bcd1), .bcd2(bcd2), .bcd3(bcd3), .minut... | 7.705629 |
module best_score_handler (
clk,
current_highscore,
alltime_highscore,
startGameEn
);
input clk; // default 50mhz clock on de2 board
input startGameEn; // FSM reset signal to reset everything
input [7:0] current_highscore; // 8 bit register containing user's current score
output reg [7:0] all... | 7.433003 |
module Beta (
input wire RESET,
input wire IRQ
);
reg CLK;
//PC_Signals
wire [31:0] INS;
wire [2:0] PCSEL;
wire [31:0] PC;
wire [31:0] PC_INC;
wire [31:0] PC_SXT;
//CTL_Signalss
wire ASEL;
wire BSEL;
wire RA2SEL;
wire WASEL;
wire [1:0] WDSEL;
wire WEREF;
//REGFILE
wire [4:0] RA1 ... | 6.808938 |
module beta_15 (
input clk,
input [0:0] game_rst,
input rst,
input [6:0] button_press,
input [0:0] board_sel,
input [0:0] board_en,
input [0:0] level_en,
input [0:0] asel,
input [1:0] bsel,
input [5:0] alufn,
output reg [0:0] allon,
output reg [15:0] boardout,
output ... | 7.122739 |
module beta_addr_decode (
input wire [31:0] addr,
output reg sel_ram = 0,
output reg sel_IO = 0,
output reg sel_read_shared = 0,
output reg sel_write_shared = 0,
output reg [2:0] read_select = 0
);
always @(*) begin
//remove the supervisor bit dummy
case (addr[30:16])
0: begin ... | 7.069586 |
module auto_reset (
hs2_in,
end_in,
rst,
clk,
reset_out,
hs1_in
);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* s... | 6.651811 |
module difference (
pixel_in,
predic_in,
\pixel_in$1 ,
\predic_in$2 ,
end_in,
rst,
clk,
val_out,
\val_out$3 ,
\val_out$4 ,
\val_out$5 ,
valid_out,
end_out,
valid_in
);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
wire [13:0] \$15 ;
wire [12:0... | 7.532482 |
module force_end (
allowed_cycles,
rst,
clk,
fend,
valid_in
);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] \$next\fsm_state ;
... | 6.812464 |
module lj92_pipeline_fifo (
enc_in,
enc_in_ctr,
in_end,
latch_output,
rst,
clk,
valid_out,
enc_out,
enc_out_ctr,
out_end,
close_full,
valid_in
);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "lj92_pipeline_fifo.py:60" *)
reg... | 6.698238 |
module register_file (
full_clk,
width,
height,
allowed_cycles,
full_rst
);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(* src = "register_file.py:36" *)
reg [15:0] \$next\height ;
(* src ... | 6.605344 |
module.integration_3.integration_2.integration_1.merge.anonymous" *)
(* generator = "nMigen" *)
module \anonymous$4 (enc_in_ctr1, enc_in_ctr2, enc_in1, enc_in2, end_in, rst, clk, enc_out_ctr, enc_out, valid_out, end_out, valid_in);
wire [5:0] \$1 ;
wire [58:0] \$3 ;
wire [58:0] \$4 ;
wire [58:0] \$6 ;
(* src ... | 6.65974 |
module.auto_reset" *)
(* generator = "nMigen" *)
module auto_reset(hs2_in, end_in, rst, clk, reset_out, hs1_in);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "auto_reset.py:34" *)
... | 6.823562 |
module.integration_3.integration_2.converter_fifo" *)
(* generator = "nMigen" *)
module converter_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "converter_fifo.py:61" *)
reg \$next\close_full ;
(* src = "converter_fi... | 6.65974 |
module.integration_3.integration_2.integration_1.difference" *)
(* generator = "nMigen" *)
module difference(pixel_in, predic_in, \pixel_in$1 , \predic_in$2 , end_in, rst, clk, val_out, \val_out$3 , \val_out$4 , \val_out$5 , valid_out, end_out, valid_in);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
... | 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo.fifo" *)
(* generator = "nMigen" *)
module fifo(we, re, rst, clk, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [62:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:... | 6.65974 |
module.integration_3.integration_2.converter_fifo.fifo" *)
(* generator = "nMigen" *)
module \fifo$5 (we, re, rst, clk, writable, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [35:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)... | 6.65974 |
module.integration_3.integration_2.integration_1.force_end" *)
(* generator = "nMigen" *)
module force_end(allowed_cycles, rst, clk, fend, valid_in);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(... | 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo" *)
(* generator = "nMigen" *)
module lj92_pipeline_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "... | 6.65974 |
module.integration_3.integration_2.integration_1.merge" *)
(* generator = "nMigen" *)
module merge(enc_in_ctr, valid_in, end_in, \enc_in$1 , \enc_in_ctr$2 , rst, clk, enc_out, enc_out_ctr, valid_out, end_out, enc_in);
(* src = "merge.py:43" *)
reg [27:0] \$next\enc_in1 ;
(* src = "merge.py:46" *)
reg [27:0] \$n... | 6.65974 |
module.integration_3.integration_2.integration_1.register_file" *)
(* generator = "nMigen" *)
module register_file(full_clk, width, height, allowed_cycles, full_rst);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(... | 6.65974 |
module.integration_3.integration_2.integration_1.merge.anonymous" *)
(* generator = "nMigen" *)
module \anonymous$4 (enc_in_ctr1, enc_in_ctr2, enc_in1, enc_in2, end_in, rst, clk, enc_out_ctr, enc_out, valid_out, end_out, valid_in);
wire [5:0] \$1 ;
wire [58:0] \$3 ;
wire [58:0] \$4 ;
wire [58:0] \$6 ;
(* src ... | 6.65974 |
module.auto_reset" *)
(* generator = "nMigen" *)
module auto_reset(hs2_in, end_in, rst, clk, reset_out, hs1_in);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "auto_reset.py:34" *)
... | 6.823562 |
module.integration_3.integration_2.converter_fifo" *)
(* generator = "nMigen" *)
module converter_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "converter_fifo.py:61" *)
reg \$next\close_full ;
(* src = "converter_fi... | 6.65974 |
module.integration_3.integration_2.integration_1.difference" *)
(* generator = "nMigen" *)
module difference(pixel_in, predic_in, \pixel_in$1 , \predic_in$2 , end_in, rst, clk, val_out, \val_out$3 , \val_out$4 , \val_out$5 , valid_out, end_out, valid_in);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
... | 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo.fifo" *)
(* generator = "nMigen" *)
module fifo(we, re, rst, clk, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [62:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:... | 6.65974 |
module.integration_3.integration_2.converter_fifo.fifo" *)
(* generator = "nMigen" *)
module \fifo$5 (we, re, rst, clk, writable, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [35:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)... | 6.65974 |
module.integration_3.integration_2.integration_1.force_end" *)
(* generator = "nMigen" *)
module force_end(allowed_cycles, rst, clk, fend, valid_in);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(... | 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo" *)
(* generator = "nMigen" *)
module lj92_pipeline_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "... | 6.65974 |
module.integration_3.integration_2.integration_1.merge" *)
(* generator = "nMigen" *)
module merge(enc_in_ctr, valid_in, end_in, \enc_in$1 , \enc_in_ctr$2 , rst, clk, enc_out, enc_out_ctr, valid_out, end_out, enc_in);
(* src = "merge.py:43" *)
reg [27:0] \$next\enc_in1 ;
(* src = "merge.py:46" *)
reg [27:0] \$n... | 6.65974 |
module.integration_3.integration_2.integration_1.register_file" *)
(* generator = "nMigen" *)
module register_file(full_clk, width, height, allowed_cycles, full_rst);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(... | 6.65974 |
module.integration_3.integration_2.integration_1.merge.anonymous" *)
(* generator = "nMigen" *)
module \anonymous$4 (enc_in_ctr1, enc_in_ctr2, enc_in1, enc_in2, end_in, rst, clk, enc_out_ctr, enc_out, valid_out, end_out, valid_in);
wire [5:0] \$1 ;
wire [58:0] \$3 ;
wire [58:0] \$4 ;
wire [58:0] \$6 ;
(* src ... | 6.65974 |
module.auto_reset" *)
(* generator = "nMigen" *)
module auto_reset(hs2_in, end_in, rst, clk, reset_out, hs1_in);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "auto_reset.py:34" *)
... | 6.823562 |
module.integration_3.integration_2.converter_fifo" *)
(* generator = "nMigen" *)
module converter_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "converter_fifo.py:61" *)
reg \$next\close_full ;
(* src = "converter_fi... | 6.65974 |
module.integration_3.integration_2.integration_1.difference" *)
(* generator = "nMigen" *)
module difference(pixel_in, predic_in, \pixel_in$1 , \predic_in$2 , end_in, rst, clk, val_out, \val_out$3 , \val_out$4 , \val_out$5 , valid_out, end_out, valid_in);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
... | 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo.fifo" *)
(* generator = "nMigen" *)
module fifo(we, re, rst, clk, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [62:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:... | 6.65974 |
module.integration_3.integration_2.converter_fifo.fifo" *)
(* generator = "nMigen" *)
module \fifo$5 (we, re, rst, clk, writable, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [35:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)... | 6.65974 |
module.integration_3.integration_2.integration_1.force_end" *)
(* generator = "nMigen" *)
module force_end(allowed_cycles, rst, clk, fend, valid_in);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(... | 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo" *)
(* generator = "nMigen" *)
module lj92_pipeline_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "... | 6.65974 |
module.integration_3.integration_2.integration_1.merge" *)
(* generator = "nMigen" *)
module merge(enc_in_ctr, valid_in, end_in, \enc_in$1 , \enc_in_ctr$2 , rst, clk, enc_out, enc_out_ctr, valid_out, end_out, enc_in);
(* src = "merge.py:43" *)
reg [27:0] \$next\enc_in1 ;
(* src = "merge.py:46" *)
reg [27:0] \$n... | 6.65974 |
module.integration_3.integration_2.integration_1.register_file" *)
(* generator = "nMigen" *)
module register_file(full_clk, width, height, allowed_cycles, full_rst);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(... | 6.65974 |
module address_gen_read (
address_latch,
rst,
clk,
address_o,
address_valid,
starting_address
);
wire [32:0] \$1 ;
wire [32:0] \$2 ;
wire [32:0] \$4 ;
wire [32:0] \$5 ;
(* src = "address_generator.py:35" *)
reg [31:0] \$next\address_o ;
(* src = "address_generator.py:36" *)
reg \... | 6.681018 |
module address_gen_write (
address_latch,
rst,
clk,
address_o,
address_valid,
starting_address
);
wire [32:0] \$1 ;
wire [32:0] \$2 ;
wire [32:0] \$4 ;
wire [32:0] \$5 ;
(* src = "address_generator.py:35" *)
reg [31:0] \$next\address_o ;
(* src = "address_generator.py:36" *)
reg ... | 6.824106 |
module auto_reset (
hs2_in,
end_in,
rst,
clk,
reset_out,
hs1_in
);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:160" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* ... | 6.651811 |
module difference (
pixel_in,
predic_in,
\pixel_in$1 ,
\predic_in$2 ,
end_in,
rst,
clk,
val_out,
\val_out$3 ,
\val_out$4 ,
\val_out$5 ,
valid_out,
end_out,
valid_in
);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
wire [13:0] \$15 ;
wire [12:0... | 7.532482 |
module force_end (
allowed_cycles,
rst,
clk,
fend,
valid_in
);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] \$next\fsm_state ;
... | 6.812464 |
module lj92_pipeline_fifo (
enc_in,
enc_in_ctr,
in_end,
latch_output,
rst,
clk,
valid_out,
enc_out,
enc_out_ctr,
out_end,
close_full,
valid_in
);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "lj92_pipeline_fifo.py:60" *)
reg... | 6.698238 |
module register_file (
full_clk,
width,
height,
allowed_cycles,
full_rst
);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(* src = "register_file.py:36" *)
reg [15:0] \$next\height ;
(* src ... | 6.605344 |
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