code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module mux1 (
select,
I,
O
);
input [1:0] select;
input [3:0] I;
output O;
reg O;
wire [1:0] select;
wire [3:0] I;
always @(I or select) begin
O = I[select];
end
endmodule
| 7.278164 |
module encoderBehavioural4x1 (
D,
A,
B,
V
);
input [3:0] D;
wire [3:0] D;
output A, B, V;
reg A, B, V;
always @(D) begin
if (D[3] == 1) begin
{A, B, V} = 3'b111;
end else if (D[2] == 1) begin
{A, B, V} = 3'b101;
end else if (D[1] == 1) begin
{A, B, V} = 3'b011;
end else if (D[0] == 1) begin
{A, B, V} = 3'b001;
end else begin
{A, B, V} = 3'b000;
end
end
endmodule
| 6.924855 |
module behavioural_alu (
X,
Y,
op_code,
Z,
zero,
overflow,
equal
);
//port definitions
input wire [31:0] X, Y;
input wire [3:0] op_code;
output reg [31:0] Z;
output reg overflow;
output wire zero, equal;
assign zero = Z == 0;
assign equal = X == Y;
wire signed [31:0] X_s, Y_s, sra;
assign X_s = X;
assign Y_s = Y;
assign sra = Y_s >>> X_s;
always @(*) begin
case (op_code)
`OP_AND: Z = X & Y;
`OP_OR: Z = X | Y;
`OP_XOR: Z = X ^ Y;
`OP_NOR: Z = ~(X | Y);
`OP_ADD: Z = X_s + Y_s;
`OP_SUB: Z = X_s - Y_s;
`OP_SLT: Z = {31'b0, (X_s < Y_s)};
`OP_SRL: Z = Y >> X;
`OP_SLL: Z = Y << X;
`OP_SRA: Z = (|X[31:5]) ? 32'h0 : sra;
default: Z = 0;
endcase
end
reg signed [31:0] sum_diff;
always @(*) begin
case (op_code)
`OP_ADD: begin
sum_diff = X + Y;
case ({
X[31], Y[31]
})
2'b00: overflow = sum_diff[31];
2'b01: overflow = 1'b0;
2'b10: overflow = 1'b0;
2'b11: overflow = ~sum_diff[31];
endcase
end
`OP_SUB: begin
sum_diff = X - Y;
case ({
X[31], Y[31]
})
2'b00: overflow = 1'b0;
2'b01: overflow = sum_diff[31];
2'b10: overflow = ~sum_diff[31];
2'b11: overflow = 1'b0;
endcase
end
default: begin
overflow = 0;
end
endcase
end
endmodule
| 8.107612 |
module behavioural_example (
input a,
input b,
input c,
input d,
output reg out // Behavioral modelling requires the use of registers but doesn't always synthesize any registers
);
// Any values set within a procedural block like below must be registers
always @(a, b, c, d) begin // The procedural block declaration, notice the begin & end statements
out = ~(((a & b) | (~c)) & d); // Looks very similar to data-flow
end
endmodule
| 7.58543 |
module mem_ext (
input W0_clk,
input [24:0] W0_addr,
input W0_en,
input [63:0] W0_data,
input [7:0] W0_mask,
input R0_clk,
input [24:0] R0_addr,
input R0_en,
output [63:0] R0_data
);
reg [24:0] reg_R0_addr;
reg [63:0] ram[33554431:0];
`ifdef RANDOMIZE
integer initvar;
initial begin
#0.002 begin
end
for (initvar = 0; initvar < 33554432; initvar = initvar + 1) ram[initvar] = {2{$random}};
reg_R0_addr = {1{$random}};
end
`endif
integer i;
always @(posedge R0_clk) if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][7:0] <= W0_data[7:0];
if (W0_mask[1]) ram[W0_addr][15:8] <= W0_data[15:8];
if (W0_mask[2]) ram[W0_addr][23:16] <= W0_data[23:16];
if (W0_mask[3]) ram[W0_addr][31:24] <= W0_data[31:24];
if (W0_mask[4]) ram[W0_addr][39:32] <= W0_data[39:32];
if (W0_mask[5]) ram[W0_addr][47:40] <= W0_data[47:40];
if (W0_mask[6]) ram[W0_addr][55:48] <= W0_data[55:48];
if (W0_mask[7]) ram[W0_addr][63:56] <= W0_data[63:56];
end
assign R0_data = ram[reg_R0_addr];
endmodule
| 6.504032 |
module Beha_BitStream_ram (
clk,
BitStream_ram_ren,
BitStream_ram_addr,
BitStream_ram_data
);
input clk;
input BitStream_ram_ren;
input [16:0] BitStream_ram_addr;
output [15:0] BitStream_ram_data;
reg [15:0] BitStream_ram_data;
reg [15:0] BitStream_ram[0:`Beha_Bitstream_ram_size];
initial begin
$readmemh("D:/nova_opencores/bin2hex/akiyo300_1ref.txt", BitStream_ram);
end
always @(posedge clk)
if (BitStream_ram_ren == 0)
BitStream_ram_data <= #2 BitStream_ram[BitStream_ram_addr];
endmodule
| 7.240745 |
module rvdff (
din,
clk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
output reg [WIDTH - 1:0] dout;
generate
if (SHORT == 1) begin
wire [WIDTH:1] sv2v_tmp_70387;
assign sv2v_tmp_70387 = din;
always @(*) dout = sv2v_tmp_70387;
end else
always @(posedge clk or negedge rst_l)
if (rst_l == 0) dout[WIDTH-1:0] <= {WIDTH{1'b0}};
else dout[WIDTH-1:0] <= din[WIDTH-1:0];
endgenerate
endmodule
| 6.770624 |
module rvdffs (
din,
en,
clk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
generate
if (SHORT == 1) begin : genblock
assign dout = din;
end else begin : genblock
rvdff #(WIDTH) dffs (
.din ((en ? din[WIDTH-1:0] : dout[WIDTH-1:0])),
.clk (clk),
.rst_l(rst_l),
.dout (dout)
);
end
endgenerate
endmodule
| 7.528373 |
module rvdffsc (
din,
en,
clear,
clk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clear;
input wire clk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
wire [WIDTH - 1:0] din_new;
generate
if (SHORT == 1) begin
assign dout = din;
end else begin
assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);
rvdff #(WIDTH) dffsc (
.din (din_new[WIDTH-1:0]),
.clk (clk),
.rst_l(rst_l),
.dout (dout)
);
end
endgenerate
endmodule
| 6.896162 |
module rvdff_fpga (
din,
clk,
clken,
rawclk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire clken;
input wire rawclk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
generate
if (SHORT == 1) begin
assign dout = din;
end else
rvdffs #(WIDTH) dffs (
.clk(rawclk),
.en(clken),
.din(din),
.rst_l(rst_l),
.dout(dout)
);
endgenerate
endmodule
| 6.743502 |
module rvdffs_fpga (
din,
en,
clk,
clken,
rawclk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clk;
input wire clken;
input wire rawclk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
generate
if (SHORT == 1) begin : genblock
assign dout = din;
end else begin : genblock
rvdffs #(WIDTH) dffs (
.clk(rawclk),
.en(clken & en),
.din(din),
.rst_l(rst_l),
.dout(dout)
);
end
endgenerate
endmodule
| 7.21158 |
module rvdffsc_fpga (
din,
en,
clear,
clk,
clken,
rawclk,
rst_l,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clear;
input wire clk;
input wire clken;
input wire rawclk;
input wire rst_l;
output wire [WIDTH - 1:0] dout;
wire [WIDTH - 1:0] din_new;
generate
if (SHORT == 1) begin
assign dout = din;
end else
rvdffs #(WIDTH) dffs (
.clk(rawclk),
.din(din[WIDTH-1:0] & {WIDTH{~clear}}),
.en((en | clear) & clken),
.rst_l(rst_l),
.dout(dout)
);
endgenerate
endmodule
| 6.900591 |
module rvdffe (
din,
en,
clk,
rst_l,
scan_mode,
dout
);
parameter WIDTH = 1;
parameter SHORT = 0;
parameter OVERRIDE = 0;
input wire [WIDTH - 1:0] din;
input wire en;
input wire clk;
input wire rst_l;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
wire l1clk;
generate
if (SHORT == 1) begin
assign dout = din;
end else begin
if ((WIDTH >= 8) || (OVERRIDE == 1)) begin
rvdffs #(WIDTH) dff (
.din(din),
.en(en),
.clk(clk),
.rst_l(rst_l),
.dout(dout)
);
end
end
endgenerate
endmodule
| 6.889647 |
module rvdffpcie (
din,
clk,
rst_l,
en,
scan_mode,
dout
);
parameter WIDTH = 31;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire en;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
generate
if (WIDTH == 31) begin : genblock
rvdffs #(WIDTH) dff (
.din(din),
.en(en),
.clk(clk),
.rst_l(rst_l),
.dout(dout)
);
end
endgenerate
endmodule
| 7.019589 |
module rvdfflie (
din,
clk,
rst_l,
en,
scan_mode,
dout
);
parameter WIDTH = 16;
parameter LEFT = 8;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire en;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
localparam EXTRA = WIDTH - LEFT;
localparam LMSB = WIDTH - 1;
localparam LLSB = (LMSB - LEFT) + 1;
localparam XMSB = LLSB - 1;
localparam XLSB = LLSB - EXTRA;
generate
if (((WIDTH >= 16) && (LEFT >= 8)) && (EXTRA >= 8)) begin : genblock
rvdffs #(WIDTH) dff (
.din(din),
.en(en),
.clk(clk),
.rst_l(rst_l),
.dout(dout)
);
end
endgenerate
endmodule
| 7.809887 |
module rvdffppe (
din,
clk,
rst_l,
en,
scan_mode,
dout
);
parameter WIDTH = 32;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire en;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
localparam RIGHT = 31;
localparam LEFT = WIDTH - RIGHT;
localparam LMSB = WIDTH - 1;
localparam LLSB = (LMSB - LEFT) + 1;
localparam RMSB = LLSB - 1;
localparam RLSB = LLSB - RIGHT;
generate
if (((WIDTH >= 32) && (LEFT >= 8)) && 1'd1) begin : genblock
rvdffs #(WIDTH) dff (
.din(din),
.en(en),
.clk(clk),
.rst_l(rst_l),
.dout(dout)
);
end
endgenerate
endmodule
| 7.61669 |
module rvdffie (
din,
clk,
rst_l,
scan_mode,
dout
);
parameter WIDTH = 1;
parameter OVERRIDE = 0;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire scan_mode;
output wire [WIDTH - 1:0] dout;
wire l1clk;
wire en;
generate
if ((WIDTH >= 8) || (OVERRIDE == 1)) begin : genblock
assign en = |(din ^ dout);
rvdffs #(WIDTH) dff (
.din(din),
.en(en),
.clk(clk),
.rst_l(rst_l),
.dout(dout)
);
end
endgenerate
endmodule
| 7.531107 |
module rvdffiee (
din,
clk,
rst_l,
scan_mode,
en,
dout
);
parameter WIDTH = 1;
parameter OVERRIDE = 0;
input wire [WIDTH - 1:0] din;
input wire clk;
input wire rst_l;
input wire scan_mode;
input wire en;
output wire [WIDTH - 1:0] dout;
wire l1clk;
wire final_en;
generate
if ((WIDTH >= 8) || (OVERRIDE == 1)) begin : genblock
assign final_en = |(din ^ dout) & en;
rvdffs #(WIDTH) dff (
.din(din),
.clk(clk),
.rst_l(rst_l),
.dout(dout),
.en(final_en)
);
end
endgenerate
endmodule
| 7.373131 |
module rvsyncss (
clk,
rst_l,
din,
dout
);
parameter WIDTH = 251;
input wire clk;
input wire rst_l;
input wire [WIDTH - 1:0] din;
output wire [WIDTH - 1:0] dout;
wire [WIDTH - 1:0] din_ff1;
rvdff #(WIDTH) sync_ff1 (
.clk (clk),
.rst_l(rst_l),
.din (din[WIDTH-1:0]),
.dout (din_ff1[WIDTH-1:0])
);
rvdff #(WIDTH) sync_ff2 (
.clk (clk),
.rst_l(rst_l),
.din (din_ff1[WIDTH-1:0]),
.dout (dout[WIDTH-1:0])
);
endmodule
| 7.513657 |
module rvsyncss_fpga (
gw_clk,
rawclk,
clken,
rst_l,
din,
dout
);
parameter WIDTH = 251;
input wire gw_clk;
input wire rawclk;
input wire clken;
input wire rst_l;
input wire [WIDTH - 1:0] din;
output wire [WIDTH - 1:0] dout;
wire [WIDTH - 1:0] din_ff1;
rvdff_fpga #(WIDTH) sync_ff1 (
.rst_l(rst_l),
.clk(gw_clk),
.rawclk(rawclk),
.clken(clken),
.din(din[WIDTH-1:0]),
.dout(din_ff1[WIDTH-1:0])
);
rvdff_fpga #(WIDTH) sync_ff2 (
.rst_l(rst_l),
.clk(gw_clk),
.rawclk(rawclk),
.clken(clken),
.din(din_ff1[WIDTH-1:0]),
.dout(dout[WIDTH-1:0])
);
endmodule
| 6.689062 |
module rvbradder (
pc,
offset,
dout
);
input [31:1] pc;
input [12:1] offset;
output [31:1] dout;
wire cout;
wire sign;
wire [31:13] pc_inc;
wire [31:13] pc_dec;
assign {cout, dout[12:1]} = {1'b0, pc[12:1]} + {1'b0, offset[12:1]};
assign pc_inc[31:13] = pc[31:13] + 1;
assign pc_dec[31:13] = pc[31:13] - 1;
assign sign = offset[12];
assign dout[31:13] = (({19 {sign ~^ cout}} & pc[31:13]) | ({19 {~sign & cout}} & pc_inc[31:13])) | ({19 {sign & ~cout}} & pc_dec[31:13]);
endmodule
| 6.926817 |
module rvmaskandmatch (
mask,
data,
masken,
match
);
parameter WIDTH = 32;
input wire [WIDTH - 1:0] mask;
input wire [WIDTH - 1:0] data;
input wire masken;
output wire match;
wire [WIDTH - 1:0] matchvec;
wire masken_or_fullmask;
assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]);
assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
genvar i;
generate
for (i = 1; i < WIDTH; i = i + 1) begin : match_after_first_zero
assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask ? 1'b1 : mask[i] == data[i]);
end
endgenerate
assign match = &matchvec[WIDTH-1:0];
endmodule
| 6.789232 |
module rveven_paritygen (
data_in,
parity_out
);
parameter WIDTH = 16;
input wire [WIDTH - 1:0] data_in;
output wire parity_out;
assign parity_out = ^data_in[WIDTH-1:0];
endmodule
| 7.582388 |
module rveven_paritycheck (
data_in,
parity_in,
parity_err
);
parameter WIDTH = 16;
input wire [WIDTH - 1:0] data_in;
input wire parity_in;
output wire parity_err;
assign parity_err = ^data_in[WIDTH-1:0] ^ parity_in;
endmodule
| 7.582388 |
module rvecc_encode (
din,
ecc_out
);
input [31:0] din;
output [6:0] ecc_out;
wire [5:0] ecc_out_temp;
assign ecc_out_temp[0] = ((((((((((((((((din[0] ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30];
assign ecc_out_temp[1] = ((((((((((((((((din[0] ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31];
assign ecc_out_temp[2] = ((((((((((((((((din[1] ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31];
assign ecc_out_temp[3] = (((((((((((((din[4] ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
assign ecc_out_temp[4] = (((((((((((((din[11] ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
assign ecc_out_temp[5] = ((((din[26] ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31];
assign ecc_out[6:0] = {^din[31:0] ^ ^ecc_out_temp[5:0], ecc_out_temp[5:0]};
endmodule
| 6.742612 |
module rvecc_decode (
en,
din,
ecc_in,
sed_ded,
dout,
ecc_out,
single_ecc_error,
double_ecc_error
);
input en;
input [31:0] din;
input [6:0] ecc_in;
input sed_ded;
output [31:0] dout;
output [6:0] ecc_out;
output single_ecc_error;
output double_ecc_error;
wire [ 6:0] ecc_check;
wire [38:0] error_mask;
wire [38:0] din_plus_parity;
wire [38:0] dout_plus_parity;
assign ecc_check[0] = (((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30];
assign ecc_check[1] = (((((((((((((((((ecc_in[1] ^ din[0]) ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31];
assign ecc_check[2] = (((((((((((((((((ecc_in[2] ^ din[1]) ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31];
assign ecc_check[3] = ((((((((((((((ecc_in[3] ^ din[4]) ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
assign ecc_check[4] = ((((((((((((((ecc_in[4] ^ din[11]) ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25];
assign ecc_check[5] = (((((ecc_in[5] ^ din[26]) ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31];
assign ecc_check[6] = (^din[31:0] ^ ^ecc_in[6:0]) & ~sed_ded;
assign single_ecc_error = (en & (ecc_check[6:0] != 0)) & ecc_check[6];
assign double_ecc_error = (en & (ecc_check[6:0] != 0)) & ~ecc_check[6];
generate
genvar i;
for (i = 1; i < 40; i = i + 1) assign error_mask[i-1] = ecc_check[5:0] == i;
endgenerate
assign din_plus_parity[38:0] = {
ecc_in[6],
din[31:26],
ecc_in[5],
din[25:11],
ecc_in[4],
din[10:4],
ecc_in[3],
din[3:1],
ecc_in[2],
din[0],
ecc_in[1:0]
};
assign dout_plus_parity[38:0] = (single_ecc_error ? error_mask[38:0] ^ din_plus_parity[38:0] : din_plus_parity[38:0]);
assign dout[31:0] = {
dout_plus_parity[37:32],
dout_plus_parity[30:16],
dout_plus_parity[14:8],
dout_plus_parity[6:4],
dout_plus_parity[2]
};
assign ecc_out[6:0] = {
dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000),
dout_plus_parity[31],
dout_plus_parity[15],
dout_plus_parity[7],
dout_plus_parity[3],
dout_plus_parity[1:0]
};
endmodule
| 7.998635 |
module rvecc_decode_64 (
en,
din,
ecc_in,
ecc_error
);
input en;
input [63:0] din;
input [6:0] ecc_in;
output ecc_error;
wire [6:0] ecc_check;
assign ecc_check[0] = ((((((((((((((((((((((((((((((((((ecc_in[0] ^ din[0]) ^ din[1]) ^ din[3]) ^ din[4]) ^ din[6]) ^ din[8]) ^ din[10]) ^ din[11]) ^ din[13]) ^ din[15]) ^ din[17]) ^ din[19]) ^ din[21]) ^ din[23]) ^ din[25]) ^ din[26]) ^ din[28]) ^ din[30]) ^ din[32]) ^ din[34]) ^ din[36]) ^ din[38]) ^ din[40]) ^ din[42]) ^ din[44]) ^ din[46]) ^ din[48]) ^ din[50]) ^ din[52]) ^ din[54]) ^ din[56]) ^ din[57]) ^ din[59]) ^ din[61]) ^ din[63];
assign ecc_check[1] = ((((((((((((((((((((((((((((((((((ecc_in[1] ^ din[0]) ^ din[2]) ^ din[3]) ^ din[5]) ^ din[6]) ^ din[9]) ^ din[10]) ^ din[12]) ^ din[13]) ^ din[16]) ^ din[17]) ^ din[20]) ^ din[21]) ^ din[24]) ^ din[25]) ^ din[27]) ^ din[28]) ^ din[31]) ^ din[32]) ^ din[35]) ^ din[36]) ^ din[39]) ^ din[40]) ^ din[43]) ^ din[44]) ^ din[47]) ^ din[48]) ^ din[51]) ^ din[52]) ^ din[55]) ^ din[56]) ^ din[58]) ^ din[59]) ^ din[62]) ^ din[63];
assign ecc_check[2] = ((((((((((((((((((((((((((((((((((ecc_in[2] ^ din[1]) ^ din[2]) ^ din[3]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
assign ecc_check[3] = ((((((((((((((((((((((((((((((ecc_in[3] ^ din[4]) ^ din[5]) ^ din[6]) ^ din[7]) ^ din[8]) ^ din[9]) ^ din[10]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
assign ecc_check[4] = ((((((((((((((((((((((((((((((ecc_in[4] ^ din[11]) ^ din[12]) ^ din[13]) ^ din[14]) ^ din[15]) ^ din[16]) ^ din[17]) ^ din[18]) ^ din[19]) ^ din[20]) ^ din[21]) ^ din[22]) ^ din[23]) ^ din[24]) ^ din[25]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
assign ecc_check[5] = ((((((((((((((((((((((((((((((ecc_in[5] ^ din[26]) ^ din[27]) ^ din[28]) ^ din[29]) ^ din[30]) ^ din[31]) ^ din[32]) ^ din[33]) ^ din[34]) ^ din[35]) ^ din[36]) ^ din[37]) ^ din[38]) ^ din[39]) ^ din[40]) ^ din[41]) ^ din[42]) ^ din[43]) ^ din[44]) ^ din[45]) ^ din[46]) ^ din[47]) ^ din[48]) ^ din[49]) ^ din[50]) ^ din[51]) ^ din[52]) ^ din[53]) ^ din[54]) ^ din[55]) ^ din[56];
assign ecc_check[6] = ((((((ecc_in[6] ^ din[57]) ^ din[58]) ^ din[59]) ^ din[60]) ^ din[61]) ^ din[62]) ^ din[63];
assign ecc_error = en & (ecc_check[6:0] != 0);
endmodule
| 7.152969 |
module rvoclkhdr (
en,
clk,
scan_mode,
l1clk
);
input wire en;
input wire clk;
input wire scan_mode;
output wire l1clk;
wire SE;
assign SE = 0;
assign l1clk = clk;
endmodule
| 6.621004 |
module belfft (
clk_i,
rst_i,
m_address,
m_readdata,
m_writedata,
m_read,
m_write,
m_waitrequest,
m_readdatavalid,
s_address,
s_readdata,
s_writedata,
s_read,
s_write,
s_byteenable,
s_waitrequest,
s_readdatavalid,
int_o
);
input clk_i;
input rst_i;
output [`BEL_FFT_MIF_AWIDTH - 1:0] m_address;
input [`BEL_FFT_DWIDTH - 1:0] m_readdata;
output [`BEL_FFT_DWIDTH - 1:0] m_writedata;
output m_read;
output m_write;
input m_waitrequest;
input m_readdatavalid;
input [`BEL_FFT_SIF_AWIDTH - 1:0] s_address;
output [`BEL_FFT_DWIDTH - 1:0] s_readdata;
input [`BEL_FFT_DWIDTH - 1:0] s_writedata;
input s_read;
input s_write;
input [`BEL_FFT_BCNT - 1:0] s_byteenable;
output s_waitrequest;
output s_readdatavalid;
output int_o;
wire [7 - 1:0] tw_adr;
wire tw_rd;
wire [32 - 1:0] tw_re;
wire [32 - 1:0] tw_im;
wire [1 - 1:0] tw_cfg_sel;
bel_fft_avl #(
.word_width(32),
.config_num(1),
.stage_num(4),
.twiddle_rom_max_awidth(7),
.fft_size(128),
.fft_size1(0),
.fft_size2(0),
.fft_size3(0),
.has_butterfly2(1)
) u_core (
.clk_i(clk_i),
.rst_i(rst_i),
.m_address(m_address),
.m_readdata(m_readdata),
.m_writedata(m_writedata),
.m_read(m_read),
.m_write(m_write),
.m_waitrequest(m_waitrequest),
.m_readdatavalid(m_readdatavalid),
.s_address(s_address),
.s_readdata(s_readdata),
.s_writedata(s_writedata),
.s_read(s_read),
.s_write(s_write),
.s_byteenable(s_byteenable),
.s_waitrequest(s_waitrequest),
.s_readdatavalid(s_readdatavalid),
.tw_adr(tw_adr),
.tw_rd(tw_rd),
.tw_re(tw_re),
.tw_im(tw_im),
.tw_cfg_sel(tw_cfg_sel),
.int_o(int_o)
);
belfft_twiddle_roms #(
.word_width(32),
.config_num(1),
.max_awidth(7),
.size(128),
.awidth(7),
.file_name("belfft_twiddle_rom0.dat"),
.size2(0),
.awidth2(0),
.file_name2(""),
.size3(0),
.awidth3(0),
.file_name3(""),
.size4(0),
.awidth4(0),
.file_name4("")
) u_twiddles (
.clk_i(clk_i),
.rst_i(rst_i),
.adr_i(tw_adr),
.rd_i(tw_rd),
.dat_o({tw_re, tw_im}),
.cfg_sel_i(tw_cfg_sel)
);
endmodule
| 6.558375 |
module belfft_twiddle_roms (
clk_i,
rst_i,
adr_i,
rd_i,
dat_o,
cfg_sel_i
);
parameter word_width = 16;
parameter config_num = 1;
parameter max_awidth = 6;
parameter size = 256;
parameter awidth = 6;
parameter file_name = "bel_rom_twiddles.dat";
parameter size2 = 256;
parameter awidth2 = 6;
parameter file_name2 = "bel_rom_twiddles2.dat";
parameter size3 = 256;
parameter awidth3 = 6;
parameter file_name3 = "bel_rom_twiddles3.dat";
parameter size4 = 256;
parameter awidth4 = 6;
parameter file_name4 = "bel_rom_twiddles4.dat";
input clk_i;
input rst_i;
input [max_awidth - 1:0] adr_i;
input rd_i;
output [word_width * 2 - 1:0] dat_o;
input [config_num - 1:0] cfg_sel_i;
reg [word_width * 2 - 1:0] dat_o;
wire [word_width * 2 - 1:0] dat;
wire [word_width * 2 - 1:0] dat2;
wire [word_width * 2 - 1:0] dat3;
wire [word_width * 2 - 1:0] dat4;
belfft_twiddle_rom0 rom (
.address(adr_i[awidth-1:0]),
.clken(rd_i & cfg_sel_i[0]),
.clock(clk_i),
.q(dat)
);
generate
if (config_num > 1) begin
belfft_twiddle_rom1 rom2 (
.address(adr_i[awidth2-1:0]),
.clken(rd_i & cfg_sel_i[1]),
.clock(clk_i),
.q(dat2)
);
if (config_num > 2) begin
belfft_twiddle_rom2 rom3 (
.address(adr_i[awidth3-1:0]),
.clken(rd_i & cfg_sel_i[2]),
.clock(clk_i),
.q(dat3)
);
if (config_num > 3) begin
belfft_twiddle_rom3 rom4 (
.address(adr_i[awidth4-1:0]),
.clken(rd_i & cfg_sel_i[3]),
.clock(clk_i),
.q(dat4)
);
always @(cfg_sel_i or dat or dat2 or dat3 or dat4) begin
case (cfg_sel_i)
4'b1000: begin
dat_o = dat4;
end
4'b0100: begin
dat_o = dat3;
end
4'b0010: begin
dat_o = dat2;
end
default: begin
dat_o = dat;
end
endcase
end
end else begin
always @(cfg_sel_i or dat or dat2 or dat3) begin
case (cfg_sel_i)
3'b100: begin
dat_o = dat3;
end
3'b010: begin
dat_o = dat2;
end
default: begin
dat_o = dat;
end
endcase
end
end
end else begin
always @(cfg_sel_i or dat or dat2) begin
case (cfg_sel_i)
2'b10: begin
dat_o = dat2;
end
default: begin
dat_o = dat;
end
endcase
end
end
end else begin
always @(dat) dat_o = dat;
end
endgenerate
endmodule
| 7.191166 |
module bel_avl_ram (
clk_i,
rst_i,
address,
readdata,
writedata,
read,
write,
readdatavalid
);
parameter size = 64;
parameter adr_width = 6;
parameter input_file_name = "bel_avl_ram_in.dat";
parameter output_file_name = "bel_avl_ram_out.dat";
parameter log_file_name = "bel_wb_ram.log";
input clk_i;
input rst_i;
input [adr_width - 1:0] address;
output [`BEL_FFT_DWIDTH - 1:0] readdata;
input [`BEL_FFT_DWIDTH - 1:0] writedata;
input read;
input write;
output readdatavalid;
reg [`BEL_FFT_DWIDTH-1:0] ram[0:size-1];
reg [adr_width-1:0] adr;
reg readdatavalid;
integer log_f;
task init_memory;
integer i;
for (i = 0; i < size; i = i + 1) begin
ram[i] = {`BEL_FFT_DWIDTH{16'hDEAD}};
end
endtask
initial begin
init_memory;
log_f = 0;
$readmemh(input_file_name, ram);
end
task open_logfile;
begin
log_f = $fopen(log_file_name);
end
endtask
task close_logfile;
begin
$fclose(log_f);
end
endtask
task dump;
integer f;
integer i;
begin
f = $fopen(output_file_name);
for (i = 0; i < size; i = i + 1) begin
$fwrite(f, "@%X %X\n", i, ram[i]);
end
$fclose(f);
end
endtask
always @(posedge rst_i or posedge clk_i) begin
if (rst_i) begin
adr <= 0;
readdatavalid <= 1'b0;
end else begin
if (read | write) begin
adr <= address;
end
if (write) begin
if (log_f != 0) begin
$fwrite(log_f, "%d: Write %8X - %8X\n", $time, address, writedata);
end
ram[address] <= writedata;
end
if (read) begin
if (log_f != 0) begin
$fwrite(log_f, "%d: Read %8X - %8X\n", $time, address, ram[address]);
end
readdatavalid <= 1'b1;
end else begin
readdatavalid <= 1'b0;
end
end
end
assign readdata = ram[adr];
endmodule
| 7.563028 |
module bel_cadd (
a_re_i,
a_im_i,
b_re_i,
b_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
input signed [word_width - 1:0] b_re_i;
input signed [word_width - 1:0] b_im_i;
output signed [word_width - 1:0] x_re_o;
output signed [word_width - 1:0] x_im_o;
assign x_re_o = a_re_i + b_re_i;
assign x_im_o = a_im_i + b_im_i;
endmodule
| 6.706295 |
module bel_caddsub (
a_re_i,
a_im_i,
b_re_i,
b_im_i,
x_re_o,
x_im_o,
inv_i
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
input signed [word_width - 1:0] b_re_i;
input signed [word_width - 1:0] b_im_i;
output signed [word_width - 1:0] x_re_o;
output signed [word_width - 1:0] x_im_o;
input inv_i;
assign x_re_o = (inv_i) ? a_re_i - b_im_i : a_re_i + b_im_i;
assign x_im_o = (inv_i) ? a_im_i + b_re_i : a_im_i - b_re_i;
endmodule
| 6.884033 |
module bel_cdiv2 (
a_re_i,
a_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
output signed [word_width - 1:0] x_re_o;
output signed [word_width - 1:0] x_im_o;
assign x_re_o = (a_re_i + 1) >>> 1;
assign x_im_o = (a_im_i + 1) >>> 1;
endmodule
| 6.832418 |
module bel_cdiv4 (
a_re_i,
a_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
output signed [word_width - 1:0] x_re_o;
output signed [word_width - 1:0] x_im_o;
assign x_re_o = (a_re_i + 2) >>> 2;
assign x_im_o = (a_im_i + 2) >>> 2;
endmodule
| 7.14204 |
module bel_cmac (
a_re_i,
a_im_i,
b_re_i,
b_im_i,
c_re_i,
c_im_i,
x_re_o,
x_im_o
);
input signed [15:0] a_re_i;
input signed [15:0] a_im_i;
input signed [15:0] b_re_i;
input signed [15:0] b_im_i;
input signed [15:0] c_re_i;
input signed [15:0] c_im_i;
output signed [15:0] x_re_o;
output signed [15:0] x_im_o;
wire signed [31:0] scratch0;
wire signed [31:0] scratch1;
wire signed [31:0] scratch2;
wire signed [31:0] scratch3;
assign scratch0 = b_re_i * c_re_i;
assign scratch1 = b_re_i * c_im_i;
assign scratch2 = b_im_i * c_re_i;
assign scratch3 = b_im_i * c_im_i;
// assign scratch4 = scratch0 - scratch3;
// assign scratch5 = scratch1 + scratch2;
assign x_re_o = (scratch0 - scratch3 + a_re_i * 32768 + 16384) / 32768;
assign x_im_o = (scratch1 + scratch2 + a_im_i * 32768 + 16384) / 32768;
// assign x_re_o = ((a_re_i * b_re_i - a_im_i * b_im_i) + ( 1 << 14)) >> 15;
// assign x_im_o = ((a_re_i * b_im_i + a_im_i * b_im_i) + ( 1 << 14)) >> 15;
endmodule
| 6.662693 |
module bel_cmul (
clk_i,
pipe_halt,
a_re_i,
a_im_i,
b_re_i,
b_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input clk_i;
input pipe_halt;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
input signed [word_width - 1:0] b_re_i;
input signed [word_width - 1:0] b_im_i;
output signed [word_width - 1:0] x_re_o;
output signed [word_width - 1:0] x_im_o;
reg signed [word_width * 2 - 1:0] scratch0;
reg signed [word_width * 2 - 1:0] scratch1;
reg signed [word_width * 2 - 1:0] scratch2;
reg signed [word_width * 2 - 1:0] scratch3;
wire signed [word_width * 2 - 1:0] scratch4;
reg signed [word_width * 2 - 1:0] scratch5;
reg signed [word_width * 2 - 1:0] scratch6;
wire signed [word_width * 2 - 1:0] x_re;
wire signed [word_width * 2 - 1:0] x_im;
always @(posedge clk_i) begin
if (~pipe_halt) begin
scratch0 <= a_re_i * b_re_i;
scratch1 <= a_re_i * b_im_i;
scratch2 <= a_im_i * b_re_i;
scratch3 <= a_im_i * b_im_i;
scratch5 <= scratch0 - scratch3;
scratch6 <= scratch1 + scratch2;
end
end
assign scratch4 = 1 << (word_width - 2);
assign x_re = (scratch5 + scratch4) >>> (word_width - 1);
assign x_im = (scratch6 + scratch4) >>> (word_width - 1);
assign x_re_o = x_re[word_width-1:0];
assign x_im_o = x_im[word_width-1:0];
endmodule
| 7.168749 |
module bel_csub (
a_re_i,
a_im_i,
b_re_i,
b_im_i,
x_re_o,
x_im_o
);
parameter word_width = 16;
input signed [word_width - 1:0] a_re_i;
input signed [word_width - 1:0] a_im_i;
input signed [word_width - 1:0] b_re_i;
input signed [word_width - 1:0] b_im_i;
output signed [word_width - 1:0] x_re_o;
output signed [word_width - 1:0] x_im_o;
assign x_re_o = a_re_i - b_re_i;
assign x_im_o = a_im_i - b_im_i;
endmodule
| 7.162353 |
module bel_fft_avl_sif (
clk_i,
rst_i,
address,
readdata,
writedata,
read,
write,
byteenable,
waitrequest,
readdatavalid,
adr_o,
dat_i,
dat_o,
bsel_o,
wr_o,
rd_o,
ack_i,
err_i
);
input clk_i;
input rst_i;
input [`BEL_FFT_SIF_AWIDTH - 1:0] address;
output [`BEL_FFT_DWIDTH - 1:0] readdata;
input [`BEL_FFT_DWIDTH - 1:0] writedata;
input read;
input write;
input [`BEL_FFT_BCNT - 1:0] byteenable;
output waitrequest;
output readdatavalid;
output [`BEL_FFT_SIF_AWIDTH-1:0] adr_o;
input [`BEL_FFT_DWIDTH-1:0] dat_i;
output [`BEL_FFT_DWIDTH-1:0] dat_o;
output [`BEL_FFT_BCNT - 1:0] bsel_o;
output wr_o;
output rd_o;
input ack_i;
input err_i;
reg last_read;
always @(posedge rst_i or posedge clk_i) begin
if (rst_i) begin
last_read <= 1'b0;
end else begin
last_read <= read;
end
end
assign adr_o = address;
assign readdata = dat_i;
assign dat_o = writedata;
assign wr_o = write;
assign rd_o = read;
assign readdatavalid = (last_read) ? ack_i : 1'b0;
assign waitrequest = 1'b0;
assign bsel_o = byteenable;
endmodule
| 7.399401 |
module bemicro_cva9_jtaguart (
input CLK_24MHZ,
output [7:0] USER_LED
);
wire clock = CLK_24MHZ;
wire reset = 0;
reg tx_valid = 1;
wire tx_ready;
reg [ 7:0] tx_data = 8'd65;
wire rx_valid;
wire rx_ready = 1;
wire [ 7:0] rx_data;
reg [28:0] sample_period = 1'd0;
reg [28:0] count_tx = 1'd0;
reg [ 7:0] spedometer = 8'd0;
/* Counting bytes for one seconds gives us B/s, thus counting bytes
for one us (1e-3) gives us kB/s. At 24 MHz, we get one ms every
24,000 ticks.
To average it out a bit, we run for 1024*24,000 cycles and shift
the result down.
Meassured with
nios2-terminal |dd of=/dev/null status=progress bs=65536
I see ~ 53.0 kB/s
*/
always @(posedge clock) begin
if (tx_valid & tx_ready) begin
tx_data <= tx_data == 8'd127 ? 8'd32 : tx_data + 8'd1;
count_tx <= count_tx + 1'd1;
end
if (sample_period[28]) begin
spedometer <= count_tx[28:18] ? ~0 : count_tx[17:10];
count_tx <= 0;
sample_period <= 1024 * 24000 - 2;
end else sample_period <= sample_period - 1'd1;
if (rx_valid) begin
// XXX Technically isn't allowed. Should only lower valid once
// ready is asserted
tx_valid <= !tx_valid;
end
end
axi_jtaguart axi_jtaguart_inst (
.clock(clock)
, .reset(reset)
, .tx_ready(tx_ready)
, .tx_valid(tx_valid)
, .tx_data (tx_data)
, .rx_ready(rx_ready)
, .rx_valid(rx_valid)
, .rx_data (rx_data)
);
assign {
USER_LED[0],
USER_LED[1],
USER_LED[2],
USER_LED[3],
USER_LED[4],
USER_LED[5],
USER_LED[6],
USER_LED[7]
} = tx_valid ? ~spedometer : 0;
endmodule
| 6.964646 |
module clk_div (
input clk_in,
output reg clk_div
);
reg [32:0] counter;
always @(posedge clk_in) begin
counter <= counter + 1;
if (counter >= 3) begin
counter <= 0;
clk_div <= ~clk_div;
end
end
endmodule
| 7.520262 |
module testbench;
parameter pmem_width = 11;
parameter dmem_width = 13;
// navre inputs
reg clk;
reg rst;
reg [15:0] pmem_d;
reg [7:0] dmem_di;
reg [7:0] io_di;
reg [7:0] irq;
// navre outputs
wire pmem_ce;
wire [pmem_width-1:0] pmem_a;
wire dmem_we;
wire [dmem_width-1:0] dmem_a;
wire [7:0] dmem_do;
wire io_re;
wire io_we;
wire [5:0] io_a;
wire [7:0] io_do;
wire [7:0] irq_ack;
wire [pmem_width-1:0] dbg_pc;
softusb_navre #(pmem_width, dmem_width) UUT (
clk,
rst,
pmem_ce,
pmem_a,
pmem_d,
dmem_we,
dmem_a,
dmem_di,
dmem_do,
io_re,
io_we,
io_a,
io_do,
io_di,
irq,
irq_ack,
dbg_pc
);
integer cycles;
initial begin
clk <= 1;
rst <= 1;
cycles = 0;
while (cycles < 8) begin
#50;
clk <= ~clk;
cycles = cycles + 1;
#50;
clk <= ~clk;
end
rst <= #20 0;
forever begin
#50;
clk <= ~clk;
cycles = cycles + 1;
#50;
clk <= ~clk;
if (cycles == 10000) begin
$display("Reached limit of 10000 cpu cycles.");
$finish;
end
end
end
reg [15:0] addr;
reg [15:0] pmem[2**pmem_width-1:0];
reg [7:0] dmem[2**dmem_width-1:0];
integer output_idx;
reg [7:0] output_buf[1023:0];
event output_eof;
integer i;
initial begin
for (i = 0; i < 2 ** pmem_width; i = i + 1) begin
pmem[i] = 0;
end
for (i = 0; i < 2 ** dmem_width; i = i + 1) begin
dmem[i] = 0;
end
`include "sieve.v"
output_idx = 0;
end
always @(posedge clk) begin
if (rst) begin
pmem_d <= 0;
irq <= 0;
end else if (pmem_ce) begin
addr = pmem_a * 2;
$display("+LOG+ %t PR @%x %x", $time, addr, pmem[pmem_a]);
pmem_d <= pmem[pmem_a];
end
if (dmem_we) begin
addr = dmem_a;
$display("+LOG+ %t DW @%x %x", $time, addr, dmem_do);
dmem[dmem_a] <= dmem_do;
end
if (io_we && io_a == 42) begin
addr = io_a;
$display("+LOG+ %t IO @%x %x <---", $time, addr, io_do);
if (io_do == 0) begin
->output_eof;
end else begin
output_buf[output_idx] = io_do;
output_idx = output_idx + 1;
end
end
dmem_di <= dmem[dmem_a];
io_di <= 0;
end
always @(output_eof) begin
#1001;
$display("Got EOF marker on IO port.");
for (i = 0; i < output_idx; i = i + 1) begin
$display("+OUT+ %t %d", $time, output_buf[i]);
end
$finish;
end
initial begin
// $dumpfile("bench.vcd");
// $dumpvars(0, testbench);
end
endmodule
| 7.015571 |
module TestBench ();
reg Clk = 0;
Mips_CPU cpu (Clk);
always #1 Clk = ~Clk;
endmodule
| 7.747207 |
module bench_closure;
reg clk, reset;
localparam width = 8;
localparam depth = 7;
localparam usz = $clog2(depth + 1);
initial clk = 0;
always #10 clk = ~clk;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [width-1:0] chk_data; // From closure of sd_pipeline.v
wire chk_drdy; // From chk of sd_seq_check.v
wire chk_srdy; // From closure of sd_pipeline.v
wire [width-1:0] gen_data; // From gen of sd_seq_gen.v
wire gen_drdy; // From closure of sd_pipeline.v
wire gen_srdy; // From gen of sd_seq_gen.v
// End of automatics
/* sd_seq_gen AUTO_TEMPLATE
(
.p_\(.*\) (gen_\1[]),
);
*/
sd_seq_gen gen ( /*AUTOINST*/
// Outputs
.p_srdy(gen_srdy), // Templated
.p_data(gen_data[width-1:0]), // Templated
// Inputs
.clk (clk),
.reset (reset),
.p_drdy(gen_drdy)
); // Templated
/* sd_seq_check AUTO_TEMPLATE
(
.c_\(.*\) (chk_\1[]),
);
*/
sd_seq_check #(
.width(width)
) chk ( /*AUTOINST*/
// Outputs
.c_drdy(chk_drdy), // Templated
// Inputs
.clk (clk),
.reset (reset),
.c_srdy(chk_srdy), // Templated
.c_data(chk_data[width-1:0])
); // Templated
/* sd_pipeline AUTO_TEMPLATE
(
.p_\(.*\) (chk_\1[]),
.c_\(.*\) (gen_\1[]),
);
*/
sd_pipeline #(
.width(width)
) closure ( /*AUTOINST*/
// Outputs
.c_drdy(gen_drdy), // Templated
.p_data(chk_data[width-1:0]), // Templated
.p_srdy(chk_srdy), // Templated
// Inputs
.c_data(gen_data[width-1:0]), // Templated
.c_srdy(gen_srdy), // Templated
.clk (clk),
.p_drdy(chk_drdy), // Templated
.reset (reset)
);
initial begin
$dumpfile("closure.vcd");
$dumpvars;
reset = 1;
#100;
reset = 0;
gen.rep_count = 9000;
// burst normal data for 20 cycles
repeat (20) @(posedge clk);
gen.srdy_pat = 8'h5A;
repeat (20) @(posedge clk);
chk.drdy_pat = 8'hA5;
repeat (40) @(posedge clk);
// check FIFO overflow
gen.srdy_pat = 8'hFD;
chk.drdy_pat = 8'h03;
repeat (100) @(posedge clk);
// check FIFO underflow
gen.srdy_pat = 8'h11;
chk.drdy_pat = 8'hEE;
repeat (100) @(posedge clk);
// Run out the remainder of the repeat count
fork
begin : runout
while (gen.rep_count > 0) begin
gen.srdy_pat = {$random} | (1 << ($random % 8));
chk.drdy_pat = {$random} | (1 << ($random % 8));
repeat (16) @(posedge clk);
end
end
begin : timeout
repeat (10000) @(posedge clk);
disable runout;
end
join
if (chk.ok_cnt >= 1000) $display("----- TEST PASSED -----");
else begin
$display("***** TEST FAILED *****");
$display("Ok count=%4d", chk.ok_cnt);
end
#5000;
$finish;
end
endmodule
| 6.548193 |
module bench_qnr_top();
//
// internal wires
//
reg clk;
reg rst;
reg dstrb;
reg [11:0] din;
wire den;
wire [10:0] dout;
reg [ 7:0] qnt_val;
integer z, d;
integer err_cnt;
//
// QNR unit
//
jpeg_qnr #(12) dut (
.clk(clk),
.ena(1'b1),
.rst(rst),
.dstrb(dstrb),
.din(din),
.qnt_val(qnt_val),
.qnt_cnt(),
.dout(dout),
.douten(den)
);
// hookup value checker
chk_val checker(
.clk(clk),
.ena(1'b1),
.den(den),
.din(dout)
);
//
// testbench body
//
// generate clock
always #2.5 clk <= ~clk;
// initial statements
initial
begin
clk = 0; // start with low-level clock
rst = 0; // reset system
dstrb = 1'b0;
rst = #17 1'b1;
// wait a while
repeat(20) @(posedge clk);
// present dstrb
dstrb = #1 1'b1;
@(posedge clk)
dstrb = #1 1'b0;
for(z = -(1<<11); z < (1<<11); z = z +1)
for(d = 1; d <= 255; d = d +1)
begin
din = #1 z;
qnt_val = #1 d;
@(posedge clk);
end
end
endmodule
| 6.566055 |
module input_switch #(
parameter WIDTH = 16
) (
y,
z,
in
);
output [WIDTH-1:0] y, z;
input [WIDTH-1:0] in;
assign y = in;
assign z = in;
endmodule
| 8.723474 |
module output_switch #(
parameter WIDTH = 16
) (
y,
in0,
in1,
sel
);
output [WIDTH-1:0] y;
input [WIDTH-1:0] in0, in1;
input sel;
// If select is 0, output from horizontal
// If select is 1, output from diagonal
benes_mux #(
.W(WIDTH)
) mux0 (
.o (y),
.a (in0),
.b (in1),
.sel(sel)
);
endmodule
| 9.44405 |
module switch #(
parameter WIDTH = 16
) (
y,
z,
in0,
in1,
sel0,
sel1
);
output [WIDTH-1:0] y, z;
input [WIDTH-1:0] in0, in1;
input sel0, sel1;
// If select is 0, then pass input from horizontal
// If select is 1, then pass input from diagonal
// y output goes to horizontal
// z output goes to diagonal
benes_mux #(
.W(WIDTH)
) mux0 (
.o (y),
.a (in0),
.b (in1),
.sel(sel0)
); // y output is horizontal
benes_mux #(
.W(WIDTH)
) mux1 (
.o (z),
.a (in0),
.b (in1),
.sel(sel1)
); // z output is diagonal
endmodule
| 9.51356 |
module benes_mux #(
parameter W = 16
) (
o,
a,
b,
sel
);
output reg [W-1:0] o;
input [W-1:0] a, b;
input sel;
always @(sel or a or b) begin
o = sel ? b : a;
end
endmodule
| 6.982245 |
module benja (
input clk,
input [7:0] in,
output reg signal
);
always @(posedge clk) begin
case (in)
8'b0001000011: signal = 1'b0;
8'b0001001011: signal = 1'b0;
8'b0001001001: signal = 1'b0;
8'b0001010011: signal = 1'b0;
8'b0001010001: signal = 1'b0;
8'b0001011011: signal = 1'b0;
8'b0101001011: signal = 1'b0;
8'b0101001101: signal = 1'b0;
8'b0101000011: signal = 1'b1;
8'b0101000101: signal = 1'b1;
8'b0101001001: signal = 1'b0;
8'b0101010011: signal = 1'b0;
8'b0101010101: signal = 1'b0;
8'b1001010011: signal = 1'b0;
8'b1001010101: signal = 1'b0;
8'b1001001011: signal = 1'b1;
8'b1001001101: signal = 1'b1;
8'b1001001001: signal = 1'b1;
8'b1001000011: signal = 1'b1;
8'b1001000101: signal = 1'b1;
8'b1101011011: signal = 1'b0;
8'b1101011101: signal = 1'b0;
8'b1101010011: signal = 1'b1;
8'b1101010101: signal = 1'b1;
8'b1101010001: signal = 1'b1;
8'b1101001011: signal = 1'b1;
8'b1101001101: signal = 1'b1;
8'b1101001001: signal = 1'b1;
8'b1101000011: signal = 1'b1;
8'b0110001011: signal = 1'b0;
8'b0110001101: signal = 1'b0;
8'b0110000011: signal = 1'b1;
8'b0110000101: signal = 1'b1;
8'b0110001001: signal = 1'b0;
8'b0110010011: signal = 1'b0;
8'b0110010101: signal = 1'b0;
8'b1010010011: signal = 1'b1;
8'b1010010101: signal = 1'b1;
8'b1010001011: signal = 1'b1;
8'b1010001101: signal = 1'b1;
8'b1010001001: signal = 1'b1;
8'b1010000011: signal = 1'b1;
8'b1010000101: signal = 1'b1;
8'b1110011011: signal = 1'b1;
8'b1110011101: signal = 1'b1;
8'b1110010011: signal = 1'b1;
8'b1110010101: signal = 1'b1;
8'b1110010001: signal = 1'b1;
8'b1110001011: signal = 1'b1;
8'b1110001101: signal = 1'b1;
8'b1110001001: signal = 1'b1;
8'b1110000011: signal = 1'b1;
8'b0101010001: signal = 1'b0;
8'b0101011011: signal = 1'b0;
8'b0001001101: signal = 1'b0;
8'b0001000101: signal = 1'b0;
8'b0001010101: signal = 1'b0;
8'b1001011011: signal = 1'b0;
8'b1001011101: signal = 1'b0;
8'b1001010001: signal = 1'b0;
8'b0100000011: signal = 1'b1;
8'b0100001011: signal = 1'b0;
8'b0100001001: signal = 1'b0;
8'b0100010011: signal = 1'b0;
8'b0100010001: signal = 1'b0;
8'b0100011011: signal = 1'b0;
8'b1010011011: signal = 1'b1;
8'b1010011101: signal = 1'b1;
8'b1010010001: signal = 1'b1;
8'b0100010101: signal = 1'b0;
8'b0100001101: signal = 1'b0;
8'b0100000101: signal = 1'b1;
8'b1000011011: signal = 1'b1;
8'b1000011101: signal = 1'b1;
8'b1000010011: signal = 1'b1;
8'b1000010101: signal = 1'b1;
8'b1000010001: signal = 1'b1;
8'b1000001011: signal = 1'b1;
8'b1000001101: signal = 1'b1;
8'b1000001001: signal = 1'b1;
8'b1000000011: signal = 1'b1;
8'b0010001011: signal = 1'b1;
8'b0010001101: signal = 1'b1;
8'b0010000011: signal = 1'b1;
8'b0010000101: signal = 1'b1;
8'b0010001001: signal = 1'b1;
8'b0010010011: signal = 1'b1;
8'b0010010101: signal = 1'b1;
8'b0101011101: signal = 1'b0;
8'b0110011011: signal = 1'b0;
8'b0110011101: signal = 1'b0;
8'b0110010001: signal = 1'b0;
8'b0100011101: signal = 1'b0;
8'b0001011101: signal = 1'b0;
endcase
end
endmodule
| 6.914128 |
module BENLogic (
input clk,
input [2:0] IR11to9,
input N,
input Zero,
input P,
output reg BEN
);
wire BENResult;
assign BENResult = (IR11to9[2] & N) | (IR11to9[1] & Zero) | (IR11to9[0] & P);
always @(posedge clk) begin
BEN <= BENResult;
end
endmodule
| 6.644731 |
module BEQ_Detection (
Branch_i,
RS1data_i,
RS2data_i,
BranchTaken_o
);
input Branch_i;
input [31:0] RS1data_i;
input [31:0] RS2data_i;
output BranchTaken_o;
assign BranchTaken_o = (RS1data_i == RS2data_i) & Branch_i;
endmodule
| 7.262378 |
module ber_prbsnoise (
input clock,
input reset,
input [1:0] select_gen,
input [1:0] noise_gen,
output prbs_out
);
//variable declaration
//-------------- prbsnoise generaration variables
//for generation
reg [22:0] shiftreg;
reg feedback;
reg prbsbuffer;
//for error generation
integer noise_counter = 0;
reg counteroverflow_gen;
reg [15:0] counterlimit;
//program logic
//---------------generation block--------------------
//prbs sequence generation
always@(posedge clock)//load or shift register (for generation
begin
if (reset == 1'b1) shiftreg = 23'hffffff;
else shiftreg = {shiftreg[21:0], feedback};
end
always @* // calculate feedback based on the case selected
case (select_gen)
2'b00: feedback = shiftreg[6] ^ shiftreg[5];
2'b01: feedback = shiftreg[14] ^ shiftreg[13];
2'b10: feedback = shiftreg[19] ^ shiftreg[16];
2'b11: feedback = shiftreg[22] ^ shiftreg[17];
default feedback = 1'bx;
endcase
always @* //calculate output register based on sequence selected
case (select_gen)
2'b00: prbsbuffer = shiftreg[6];
2'b01: prbsbuffer = shiftreg[14];
2'b10: prbsbuffer = shiftreg[19];
2'b11: prbsbuffer = shiftreg[22];
default prbsbuffer = 1'bx;
endcase
// noise or error insertion
always @* begin
case (noise_gen)
2'b00: counterlimit = 1'b0;
2'b01: counterlimit = 16'd100;
2'b10: counterlimit = 16'd1000;
2'b11: counterlimit = 16'd10000;
endcase
end
always @(posedge clock)
//count upto a value&set counteroverflow if value reached
if (noise_gen == 2'b00)
counteroverflow_gen = 1'b0;
else begin
if (reset | counterlimit == noise_counter) begin
noise_counter = 0;
counteroverflow_gen = 1;
end else begin
noise_counter = noise_counter + 1;
counteroverflow_gen = 0;
end
end
//xor the noise(counteroverflow) and prbs output to induce 1 error in every x bits
assign prbs_out = prbsbuffer ^ counteroverflow_gen;
endmodule
| 6.97924 |
module best_lap_time_char_rom (
input wire [15:0] char_xy,
input wire [15:0] best_lap_time,
output reg [ 6:0] char_code // pixels of the character line
);
wire [3:0] bcd0, bcd1, bcd2, bcd3, minutes;
bin2bcd(
.bin(best_lap_time), .bcd0(bcd0), .bcd1(bcd1), .bcd2(bcd2), .bcd3(bcd3), .minutes(minutes)
);
reg [7:0] char_code_0, char_code_1, char_code_2, char_code_3, char_code_4;
always @* begin
char_code_0 = 7'h00;
char_code_1 = 7'h00;
char_code_2 = 7'h00;
char_code_3 = 7'h00;
char_code_4 = 7'h00;
case (bcd0)
4'b0000: char_code_0 = 7'h30;
4'b0001: char_code_0 = 7'h31;
4'b0010: char_code_0 = 7'h32;
4'b0011: char_code_0 = 7'h33;
4'b0100: char_code_0 = 7'h34;
4'b0101: char_code_0 = 7'h35;
4'b0110: char_code_0 = 7'h36;
4'b0111: char_code_0 = 7'h37;
4'b1000: char_code_0 = 7'h38;
4'b1001: char_code_0 = 7'h39;
default: char_code_0 = 7'h00;
endcase
case (bcd1)
4'b0000: char_code_1 = 7'h30;
4'b0001: char_code_1 = 7'h31;
4'b0010: char_code_1 = 7'h32;
4'b0011: char_code_1 = 7'h33;
4'b0100: char_code_1 = 7'h34;
4'b0101: char_code_1 = 7'h35;
4'b0110: char_code_1 = 7'h36;
4'b0111: char_code_1 = 7'h37;
4'b1000: char_code_1 = 7'h38;
4'b1001: char_code_1 = 7'h39;
default: char_code_1 = 7'h00;
endcase
case (bcd2)
4'b0000: char_code_2 = 7'h30;
4'b0001: char_code_2 = 7'h31;
4'b0010: char_code_2 = 7'h32;
4'b0011: char_code_2 = 7'h33;
4'b0100: char_code_2 = 7'h34;
4'b0101: char_code_2 = 7'h35;
4'b0110: char_code_2 = 7'h36;
4'b0111: char_code_2 = 7'h37;
4'b1000: char_code_2 = 7'h38;
4'b1001: char_code_2 = 7'h39;
default: char_code_2 = 7'h00;
endcase
case (bcd3)
4'b0000: char_code_3 = 7'h30;
4'b0001: char_code_3 = 7'h31;
4'b0010: char_code_3 = 7'h32;
4'b0011: char_code_3 = 7'h33;
4'b0100: char_code_3 = 7'h34;
4'b0101: char_code_3 = 7'h35;
4'b0110: char_code_3 = 7'h36;
4'b0111: char_code_3 = 7'h37;
4'b1000: char_code_3 = 7'h38;
4'b1001: char_code_3 = 7'h39;
default: char_code_3 = 7'h00;
endcase
case (minutes)
4'b0000: char_code_4 = 7'h30;
4'b0001: char_code_4 = 7'h31;
4'b0010: char_code_4 = 7'h32;
4'b0011: char_code_4 = 7'h33;
4'b0100: char_code_4 = 7'h34;
4'b0101: char_code_4 = 7'h35;
4'b0110: char_code_4 = 7'h36;
4'b0111: char_code_4 = 7'h37;
4'b1000: char_code_4 = 7'h38;
4'b1001: char_code_4 = 7'h39;
default: char_code_4 = 7'h00;
endcase
end
always @* begin
case (char_xy)
16'h0000: char_code = 7'h42; //B
16'h0100: char_code = 7'h45; //E
16'h0200: char_code = 7'h53; //S
16'h0300: char_code = 7'h54; //T
16'h0400: char_code = 7'h20; //
16'h0500: char_code = 7'h4c; //L
16'h0600: char_code = 7'h41; //A
16'h0700: char_code = 7'h50; //P
16'h0800: char_code = 7'h20; //
16'h0900: char_code = 7'h54; //T
16'h0a00: char_code = 7'h49; //I
16'h0b00: char_code = 7'h4d; //M
16'h0c00: char_code = 7'h45; //E
16'h0d00: char_code = 7'h3a; //:
16'h0e00: char_code = 7'h00; //
16'h0f00: char_code = char_code_3;
16'h1000: char_code = char_code_2;
16'h1100: char_code = 7'h3a; //:
16'h1200: char_code = char_code_1;
16'h1300: char_code = char_code_0;
default: char_code = 0;
endcase
end
endmodule
| 7.705629 |
module best_score_handler (
clk,
current_highscore,
alltime_highscore,
startGameEn
);
input clk; // default 50mhz clock on de2 board
input startGameEn; // FSM reset signal to reset everything
input [7:0] current_highscore; // 8 bit register containing user's current score
output reg [7:0] alltime_highscore; // 8 bit register containing the best high score overall
always @(posedge clk) begin
if (current_highscore > alltime_highscore) begin
alltime_highscore <= current_highscore;
end
end
endmodule
| 7.433003 |
module Beta (
input wire RESET,
input wire IRQ
);
reg CLK;
//PC_Signals
wire [31:0] INS;
wire [2:0] PCSEL;
wire [31:0] PC;
wire [31:0] PC_INC;
wire [31:0] PC_SXT;
//CTL_Signalss
wire ASEL;
wire BSEL;
wire RA2SEL;
wire WASEL;
wire [1:0] WDSEL;
wire WEREF;
//REGFILE
wire [4:0] RA1 = INS[20:16];
wire [4:0] RA2;
wire [4:0] WA;
wire [31:0] WD;
wire WERF;
wire [31:0] RD1;
wire [31:0] RD2;
//ALU
wire [5:0] FN;
wire [31:0] RA;
wire [31:0] RB;
wire [31:0] RC;
wire Z;
//Beta_DATAMEM
wire [31:0] MWD;
wire MWR;
wire MOE;
wire [31:0] MA;
wire [31:0] MRD;
PC BetaPC (
RD1, /*input wire[31:0]*/
INS[15:0], /*input wire[15:0]*/
PCSEL, /*input wire[3:0]*/
CLK, /*input wire*/
RESET, /*input wire*/
PC, /*output reg[31:0]*/
PC_INC, /*output reg[31:0]*/
PC_SXT /*output reg[31:0]*/
);
INSMEM BetaINSMEM (
PC, //input wire[31:0]
INS, //output reg[31:0]
CLK //input wire
);
CTL BetaCTL (
INS, //input wire[31:0]
Z, //input wire
IRQ, //input wire
RESET, //input wire
FN, //output reg[5:0]
ASEL, //output reg
BSEL, //output reg
MOE, //output reg
MWR, //output reg
PCSEL, //output reg[2:0]
RA2SEL, //output reg
WASEL, //output reg
WDSEL, //output reg[1:0]
WEREF //output reg
);
assign RA2 = (RA2SEL) ? INS[25:21] : INS[15:11];
assign WA = (WASEL) ? 30 : INS[15:11];
assign RA = (ASEL) ? PC_SXT : RD1;
assign RB = (BSEL) ? INS[15:0] : RD2;
assign WD = (WDSEL[0] == 0) ? (WDSEL[1] == 1) ? MRD : PC_INC : RC;
REGFILE BetaREGFILE (
RA1, //input wire[4:0]
RA2, //input wire[4:0]
WA, //input wire[4:0]
WD, //input wire[31:0]
WERF, //input wire
RD1, //output reg[31:0]
RD2 // output reg[31:0]
);
ALU BetaALU (
FN, //input wire[5:0]
RA, //input wire[31:0]
RB, //input wire[31:0]
RC, //output wire[31:0]
Z //output wire
);
DATAMEM Beta_DATAMEM (
RD2, //input wire[31:0]
MWR, //input wire
MOE, //input wire
RC, //input wire[31:0]
MRD //output reg[31:0]
);
endmodule
| 6.808938 |
module beta_15 (
input clk,
input [0:0] game_rst,
input rst,
input [6:0] button_press,
input [0:0] board_sel,
input [0:0] board_en,
input [0:0] level_en,
input [0:0] asel,
input [1:0] bsel,
input [5:0] alufn,
output reg [0:0] allon,
output reg [15:0] boardout,
output reg [15:0] levelout
);
wire [16-1:0] M_levels_mux_out;
reg [ 3-1:0] M_levels_mux_levels_sel;
levels_mux_37 levels_mux (
.levels_sel(M_levels_mux_levels_sel),
.out(M_levels_mux_out)
);
wire [16-1:0] M_alu_out;
wire [ 1-1:0] M_alu_z;
wire [ 1-1:0] M_alu_v;
wire [ 1-1:0] M_alu_n;
reg [ 6-1:0] M_alu_io_dip;
reg [16-1:0] M_alu_a;
reg [16-1:0] M_alu_b;
alu_38 alu (
.io_dip(M_alu_io_dip),
.a(M_alu_a),
.b(M_alu_b),
.out(M_alu_out),
.z(M_alu_z),
.v(M_alu_v),
.n(M_alu_n)
);
wire [16-1:0] M_buttons_mux_out;
reg [ 7-1:0] M_buttons_mux_buttons_sel;
buttons_mux_39 buttons_mux (
.buttons_sel(M_buttons_mux_buttons_sel),
.out(M_buttons_mux_out)
);
wire [16-1:0] M_board_out;
reg [ 1-1:0] M_board_en;
reg [16-1:0] M_board_data;
register_40 board (
.clk (clk),
.rst (rst),
.en (M_board_en),
.data(M_board_data),
.out (M_board_out)
);
wire [16-1:0] M_level_out;
reg [ 1-1:0] M_level_en;
reg [16-1:0] M_level_data;
register_40 level (
.clk (clk),
.rst (rst),
.en (M_level_en),
.data(M_level_data),
.out (M_level_out)
);
always @* begin
M_alu_io_dip = alufn;
M_board_en = board_en;
M_level_en = level_en;
M_level_data = M_alu_out;
M_buttons_mux_buttons_sel = button_press;
M_levels_mux_levels_sel = M_level_out[3+2-:3];
boardout = M_board_out;
allon = M_alu_out[0+0-:1];
levelout = M_level_out;
if (game_rst == 1'h1) begin
M_level_data = 1'h0;
M_level_en = 1'h1;
end
if (asel == 1'h0) begin
M_alu_a = M_board_out;
end else begin
M_alu_a = M_level_out;
end
if (bsel == 1'h0) begin
M_alu_b = M_buttons_mux_out;
end else begin
if (bsel == 1'h1) begin
M_alu_b = 16'h0fff;
end else begin
M_alu_b = 16'h0001;
end
end
if (board_sel == 1'h0) begin
M_board_data = M_alu_out;
end else begin
M_board_data = M_levels_mux_out;
end
end
endmodule
| 7.122739 |
module beta_addr_decode (
input wire [31:0] addr,
output reg sel_ram = 0,
output reg sel_IO = 0,
output reg sel_read_shared = 0,
output reg sel_write_shared = 0,
output reg [2:0] read_select = 0
);
always @(*) begin
//remove the supervisor bit dummy
case (addr[30:16])
0: begin //RAM select
sel_ram <= 1;
sel_IO <= 0;
sel_read_shared <= 0;
sel_write_shared <= 0;
read_select <= 0;
end
1: begin //Memory mapped IO select
sel_ram <= 0;
sel_IO <= 1;
sel_read_shared <= 0;
sel_write_shared <= 0;
read_select <= 1;
end
2: begin //read block select
sel_ram <= 0;
sel_IO <= 0;
sel_read_shared <= 1;
sel_write_shared <= 0;
read_select <= 2;
end
3: begin //write block select
sel_ram <= 0;
sel_IO <= 0;
sel_read_shared <= 0;
sel_write_shared <= 1;
read_select <= 3;
end
default: begin //this should never happen
sel_ram <= 1; //read from main mem? I could trigger error IRQ
sel_IO <= 0;
sel_read_shared <= 0;
sel_write_shared <= 0;
read_select <= 0;
end
endcase
end
endmodule
| 7.069586 |
module auto_reset (
hs2_in,
end_in,
rst,
clk,
reset_out,
hs1_in
);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* src = "auto_reset.py:37" *)
input hs1_in;
(* src = "auto_reset.py:40" *)
input hs2_in;
(* init = 1'h0 *) (* src = "auto_reset.py:43" *)
output reset_out;
reg reset_out = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
assign \$9 = \$5 & (* src = "auto_reset.py:54" *) \$7 ;
assign \$1 = hs1_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$3 = hs2_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$5 = \$1 & (* src = "auto_reset.py:54" *) \$3 ;
assign \$7 = end_in == (* src = "auto_reset.py:54" *) 1'h1;
always @(posedge clk) reset_out <= \$next\reset_out ;
always @* begin
\$next\reset_out = reset_out;
casez (\$9 )
1'h1: \$next\reset_out = 1'h1;
endcase
casez (rst)
1'h1: \$next\reset_out = 1'h0;
endcase
end
endmodule
| 6.651811 |
module difference (
pixel_in,
predic_in,
\pixel_in$1 ,
\predic_in$2 ,
end_in,
rst,
clk,
val_out,
\val_out$3 ,
\val_out$4 ,
\val_out$5 ,
valid_out,
end_out,
valid_in
);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
wire [13:0] \$15 ;
wire [12:0] \$16 ;
wire [13:0] \$18 ;
wire [12:0] \$6 ;
wire [12:0] \$8 ;
(* src = "difference.py:72" *)
reg \$next\end_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out$3 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$4 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$5 ;
(* src = "difference.py:68" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "difference.py:71" *)
input end_in;
(* init = 1'h0 *) (* src = "difference.py:72" *)
output end_out;
reg end_out = 1'h0;
(* src = "difference.py:55" *)
input [11:0] pixel_in;
(* src = "difference.py:55" *)
input [11:0] \pixel_in$1 ;
(* src = "difference.py:58" *)
input [11:0] predic_in;
(* src = "difference.py:58" *)
input [11:0] \predic_in$2 ;
(* src = "clk_domains.py:5" *)
input rst;
(* init = 13'h0000 *) (* src = "difference.py:61" *)
output [12:0] val_out;
reg [12:0] val_out = 13'h0000;
(* init = 13'h0000 *) (* src = "difference.py:61" *)
output [12:0] \val_out$3 ;
reg [12:0] \val_out$3 = 13'h0000;
(* init = 13'h0000 *) (* src = "difference.py:64" *)
output [12:0] \val_out$4 ;
reg [12:0] \val_out$4 = 13'h0000;
(* init = 13'h0000 *) (* src = "difference.py:64" *)
output [12:0] \val_out$5 ;
reg [12:0] \val_out$5 = 13'h0000;
(* src = "difference.py:67" *)
input valid_in;
(* init = 1'h0 *) (* src = "difference.py:68" *)
output valid_out;
reg valid_out = 1'h0;
assign \$11 = pixel_in - (* src = "difference.py:90" *) predic_in;
assign \$13 = \$11 - (* src = "difference.py:90" *) 1'h1;
assign \$16 = \pixel_in$1 - (* src = "difference.py:90" *) \predic_in$2 ;
assign \$18 = \$16 - (* src = "difference.py:90" *) 1'h1;
assign \$6 = pixel_in - (* src = "difference.py:89" *) predic_in;
assign \$8 = \pixel_in$1 - (* src = "difference.py:89" *) \predic_in$2 ;
always @(posedge clk) end_out <= \$next\end_out ;
always @(posedge clk) valid_out <= \$next\valid_out ;
always @(posedge clk) \val_out$5 <= \$next\val_out$5 ;
always @(posedge clk) \val_out$4 <= \$next\val_out$4 ;
always @(posedge clk) \val_out$3 <= \$next\val_out$3 ;
always @(posedge clk) val_out <= \$next\val_out ;
always @* begin
\$next\val_out = val_out;
casez (valid_in)
1'h1: \$next\val_out = \$6 ;
endcase
casez (rst)
1'h1: \$next\val_out = 13'h0000;
endcase
end
always @* begin
\$next\val_out$3 = \val_out$3 ;
casez (valid_in)
1'h1: \$next\val_out$3 = \$8 ;
endcase
casez (rst)
1'h1: \$next\val_out$3 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$4 = \val_out$4 ;
casez (valid_in)
1'h1: \$next\val_out$4 = \$10 [12:0];
endcase
casez (rst)
1'h1: \$next\val_out$4 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$5 = \val_out$5 ;
casez (valid_in)
1'h1: \$next\val_out$5 = \$15 [12:0];
endcase
casez (rst)
1'h1: \$next\val_out$5 = 13'h0000;
endcase
end
always @* begin
\$next\valid_out = valid_out;
\$next\valid_out = valid_in;
casez (rst)
1'h1: \$next\valid_out = 1'h0;
endcase
end
always @* begin
\$next\end_out = end_out;
\$next\end_out = end_in;
casez (rst)
1'h1: \$next\end_out = 1'h0;
endcase
end
assign \$10 = \$13 ;
assign \$15 = \$18 ;
endmodule
| 7.532482 |
module force_end (
allowed_cycles,
rst,
clk,
fend,
valid_in
);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] \$next\fsm_state ;
(* src = "force_end.py:39" *)
input [23:0] allowed_cycles;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 25'h0000000 *) (* src = "force_end.py:51" *)
reg [24:0] counter = 25'h0000000;
(* init = 1'h0 *) (* src = "force_end.py:41" *)
output fend;
reg fend = 1'h0;
(* init = 2'h0 *) (* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] fsm_state = 2'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "force_end.py:38" *)
input valid_in;
assign \$1 = counter == (* src = "force_end.py:61" *) allowed_cycles;
assign \$4 = counter + (* src = "force_end.py:60" *) 1'h1;
always @(posedge clk) fend <= \$next\fend ;
always @(posedge clk) counter <= \$next\counter ;
always @(posedge clk) fsm_state <= \$next\fsm_state ;
always @* begin
\$next\fsm_state = fsm_state;
casez (fsm_state)
2'h0:
casez (valid_in)
1'h1: \$next\fsm_state = 2'h1;
endcase
2'h1:
casez (\$1 )
1'h1: \$next\fsm_state = 2'h2;
endcase
endcase
casez (rst)
1'h1: \$next\fsm_state = 2'h0;
endcase
end
always @* begin
\$next\counter = counter;
casez (fsm_state)
2'h1: \$next\counter = \$3 [24:0];
endcase
casez (rst)
1'h1: \$next\counter = 25'h0000000;
endcase
end
always @* begin
\$next\fend = fend;
casez (fsm_state)
2'h2: \$next\fend = 1'h1;
endcase
casez (rst)
1'h1: \$next\fend = 1'h0;
endcase
end
assign \$3 = \$4 ;
endmodule
| 6.812464 |
module lj92_pipeline_fifo (
enc_in,
enc_in_ctr,
in_end,
latch_output,
rst,
clk,
valid_out,
enc_out,
enc_out_ctr,
out_end,
close_full,
valid_in
);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "lj92_pipeline_fifo.py:60" *)
reg [55:0] \$next\enc_out ;
(* src = "lj92_pipeline_fifo.py:61" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [62:0] \$next\fifo_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\fifo_re ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\fifo_we ;
(* src = "lj92_pipeline_fifo.py:62" *)
reg \$next\out_end ;
(* src = "lj92_pipeline_fifo.py:63" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 1'h0 *) (* src = "lj92_pipeline_fifo.py:67" *)
output close_full;
reg close_full = 1'h0;
(* src = "lj92_pipeline_fifo.py:54" *)
input [55:0] enc_in;
(* src = "lj92_pipeline_fifo.py:55" *)
input [5:0] enc_in_ctr;
(* src = "lj92_pipeline_fifo.py:60" *)
output [55:0] enc_out;
(* src = "lj92_pipeline_fifo.py:61" *)
output [5:0] enc_out_ctr;
(* src = "nmigen/lib/fifo.py:65" *)
wire [62:0] fifo_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [62:0] fifo_dout;
(* src = "nmigen/lib/fifo.py:238" *)
wire [9:0] fifo_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire fifo_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire fifo_readable;
(* src = "nmigen/lib/fifo.py:67" *)
wire fifo_we;
(* src = "lj92_pipeline_fifo.py:56" *)
input in_end;
(* src = "lj92_pipeline_fifo.py:59" *)
input latch_output;
(* src = "lj92_pipeline_fifo.py:62" *)
output out_end;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "lj92_pipeline_fifo.py:57" *)
input valid_in;
(* src = "lj92_pipeline_fifo.py:63" *)
output valid_out;
assign \$1 = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 9'h1f6;
always @(posedge clk) close_full <= \$next\close_full ;
fifo fifo (
.clk(clk),
.din(fifo_din),
.dout(fifo_dout),
.level(fifo_level),
.re(fifo_re),
.readable(fifo_readable),
.rst(rst),
.we(fifo_we)
);
always @* begin
\$next\fifo_we = 1'h0;
\$next\fifo_we = valid_in;
end
always @* begin
\$next\fifo_din = 63'h0000000000000000;
\$next\fifo_din = {in_end, enc_in_ctr, enc_in};
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = fifo_readable;
end
always @* begin
\$next\enc_out = 56'h00000000000000;
\$next\enc_out = fifo_dout[55:0];
end
always @* begin
\$next\enc_out_ctr = 6'h00;
\$next\enc_out_ctr = fifo_dout[61:56];
end
always @* begin
\$next\out_end = 1'h0;
\$next\out_end = fifo_dout[62];
end
always @* begin
\$next\fifo_re = 1'h0;
\$next\fifo_re = latch_output;
end
always @* begin
\$next\close_full = close_full;
\$next\close_full = \$1 ;
casez (rst)
1'h1: \$next\close_full = 1'h0;
endcase
end
assign fifo_re = \$next\fifo_re ;
assign out_end = \$next\out_end ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign valid_out = \$next\valid_out ;
assign fifo_din = \$next\fifo_din ;
assign fifo_we = \$next\fifo_we ;
endmodule
| 6.698238 |
module register_file (
full_clk,
width,
height,
allowed_cycles,
full_rst
);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(* src = "register_file.py:36" *)
reg [15:0] \$next\height ;
(* src = "register_file.py:51" *)
reg [15:0] \$next\height_reg ;
(* src = "register_file.py:37" *)
reg [15:0] \$next\width ;
(* src = "register_file.py:50" *)
reg [15:0] \$next\width_reg ;
(* src = "register_file.py:38" *)
output [23:0] allowed_cycles;
(* init = 24'h000000 *) (* src = "register_file.py:52" *)
reg [23:0] allowed_cycles_reg = 24'h000000;
(* src = "clk_domains.py:4" *)
input full_clk;
(* src = "clk_domains.py:4" *)
input full_rst;
(* src = "register_file.py:36" *)
output [15:0] height;
(* init = 16'h0000 *) (* src = "register_file.py:51" *)
reg [15:0] height_reg = 16'h0000;
(* src = "register_file.py:37" *)
output [15:0] width;
(* init = 16'h0000 *) (* src = "register_file.py:50" *)
reg [15:0] width_reg = 16'h0000;
always @(posedge full_clk) allowed_cycles_reg <= \$next\allowed_cycles_reg ;
always @(posedge full_clk) height_reg <= \$next\height_reg ;
always @(posedge full_clk) width_reg <= \$next\width_reg ;
always @* begin
\$next\width_reg = width_reg;
\$next\width_reg = 16'h1000;
casez (full_rst)
1'h1: \$next\width_reg = 16'h0000;
endcase
end
always @* begin
\$next\height_reg = height_reg;
\$next\height_reg = 16'h0c00;
casez (full_rst)
1'h1: \$next\height_reg = 16'h0000;
endcase
end
always @* begin
\$next\allowed_cycles_reg = allowed_cycles_reg;
\$next\allowed_cycles_reg = 24'h65b710;
casez (full_rst)
1'h1: \$next\allowed_cycles_reg = 24'h000000;
endcase
end
always @* begin
\$next\width = 16'h0000;
\$next\width = width_reg;
end
always @* begin
\$next\height = 16'h0000;
\$next\height = height_reg;
end
always @* begin
\$next\allowed_cycles = 24'h000000;
\$next\allowed_cycles = allowed_cycles_reg;
end
assign allowed_cycles = \$next\allowed_cycles ;
assign height = \$next\height ;
assign width = \$next\width ;
endmodule
| 6.605344 |
module.integration_3.integration_2.integration_1.merge.anonymous" *)
(* generator = "nMigen" *)
module \anonymous$4 (enc_in_ctr1, enc_in_ctr2, enc_in1, enc_in2, end_in, rst, clk, enc_out_ctr, enc_out, valid_out, end_out, valid_in);
wire [5:0] \$1 ;
wire [58:0] \$3 ;
wire [58:0] \$4 ;
wire [58:0] \$6 ;
(* src = "merge.py:49" *)
reg [55:0] \$next\enc_out ;
(* src = "merge.py:50" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "merge.py:58" *)
reg \$next\end_out ;
(* src = "merge.py:54" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "merge.py:43" *)
input [27:0] enc_in1;
(* src = "merge.py:46" *)
input [27:0] enc_in2;
(* src = "merge.py:44" *)
input [4:0] enc_in_ctr1;
(* src = "merge.py:47" *)
input [4:0] enc_in_ctr2;
(* init = 56'h00000000000000 *)
(* src = "merge.py:49" *)
output [55:0] enc_out;
reg [55:0] enc_out = 56'h00000000000000;
(* init = 6'h00 *)
(* src = "merge.py:50" *)
output [5:0] enc_out_ctr;
reg [5:0] enc_out_ctr = 6'h00;
(* src = "merge.py:57" *)
input end_in;
(* init = 1'h0 *)
(* src = "merge.py:58" *)
output end_out;
reg end_out = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "merge.py:53" *)
input valid_in;
(* init = 1'h0 *)
(* src = "merge.py:54" *)
output valid_out;
reg valid_out = 1'h0;
assign \$1 = enc_in_ctr1 + (* src = "merge.py:74" *) enc_in_ctr2;
assign \$4 = enc_in1 <<< (* src = "merge.py:75" *) enc_in_ctr2;
assign \$6 = \$4 | (* src = "merge.py:75" *) enc_in2;
always @(posedge clk)
end_out <= \$next\end_out ;
always @(posedge clk)
valid_out <= \$next\valid_out ;
always @(posedge clk)
enc_out <= \$next\enc_out ;
always @(posedge clk)
enc_out_ctr <= \$next\enc_out_ctr ;
always @* begin
\$next\enc_out_ctr = enc_out_ctr;
casez (valid_in)
1'h1:
\$next\enc_out_ctr = \$1 ;
endcase
casez (rst)
1'h1:
\$next\enc_out_ctr = 6'h00;
endcase
end
always @* begin
\$next\enc_out = enc_out;
casez (valid_in)
1'h1:
\$next\enc_out = \$3 [55:0];
endcase
casez (rst)
1'h1:
\$next\enc_out = 56'h00000000000000;
endcase
end
always @* begin
\$next\valid_out = valid_out;
\$next\valid_out = valid_in;
casez (rst)
1'h1:
\$next\valid_out = 1'h0;
endcase
end
always @* begin
\$next\end_out = end_out;
\$next\end_out = end_in;
casez (rst)
1'h1:
\$next\end_out = 1'h0;
endcase
end
assign \$3 = \$6 ;
endmodule
| 6.65974 |
module.auto_reset" *)
(* generator = "nMigen" *)
module auto_reset(hs2_in, end_in, rst, clk, reset_out, hs1_in);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* src = "auto_reset.py:37" *)
input hs1_in;
(* src = "auto_reset.py:40" *)
input hs2_in;
(* init = 1'h0 *)
(* src = "auto_reset.py:43" *)
output reset_out;
reg reset_out = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
assign \$9 = \$5 & (* src = "auto_reset.py:54" *) \$7 ;
assign \$1 = hs1_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$3 = hs2_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$5 = \$1 & (* src = "auto_reset.py:54" *) \$3 ;
assign \$7 = end_in == (* src = "auto_reset.py:54" *) 1'h1;
always @(posedge clk)
reset_out <= \$next\reset_out ;
always @* begin
\$next\reset_out = reset_out;
casez (\$9 )
1'h1:
\$next\reset_out = 1'h1;
endcase
casez (rst)
1'h1:
\$next\reset_out = 1'h0;
endcase
end
endmodule
| 6.823562 |
module.integration_3.integration_2.converter_fifo" *)
(* generator = "nMigen" *)
module converter_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "converter_fifo.py:61" *)
reg \$next\close_full ;
(* src = "converter_fifo.py:65" *)
reg [29:0] \$next\enc_out ;
(* src = "converter_fifo.py:66" *)
reg [4:0] \$next\enc_out_ctr ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [35:0] \$next\fifo_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\fifo_re ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\fifo_we ;
(* src = "converter_fifo.py:67" *)
reg \$next\out_end ;
(* src = "converter_fifo.py:68" *)
reg \$next\valid_out ;
(* src = "converter_fifo.py:60" *)
reg \$next\writable ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 1'h0 *)
(* src = "converter_fifo.py:61" *)
output close_full;
reg close_full = 1'h0;
(* src = "converter_fifo.py:56" *)
input [29:0] enc_in;
(* src = "converter_fifo.py:57" *)
input [4:0] enc_in_ctr;
(* src = "converter_fifo.py:65" *)
output [29:0] enc_out;
(* src = "converter_fifo.py:66" *)
output [4:0] enc_out_ctr;
(* src = "nmigen/lib/fifo.py:65" *)
wire [35:0] fifo_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [35:0] fifo_dout;
(* src = "nmigen/lib/fifo.py:238" *)
wire [9:0] fifo_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire fifo_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire fifo_readable;
(* src = "nmigen/lib/fifo.py:67" *)
wire fifo_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire fifo_writable;
(* src = "converter_fifo.py:58" *)
input in_end;
(* src = "converter_fifo.py:64" *)
input latch_output;
(* src = "converter_fifo.py:67" *)
output out_end;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "converter_fifo.py:59" *)
input valid_in;
(* src = "converter_fifo.py:68" *)
output valid_out;
(* src = "converter_fifo.py:60" *)
wire writable;
assign \$1 = fifo_level >= (* src = "converter_fifo.py:100" *) 9'h1fb;
always @(posedge clk)
close_full <= \$next\close_full ;
\fifo$5 fifo (
.clk(clk),
.din(fifo_din),
.dout(fifo_dout),
.level(fifo_level),
.re(fifo_re),
.readable(fifo_readable),
.rst(rst),
.we(fifo_we),
.writable(fifo_writable)
);
always @* begin
\$next\fifo_we = 1'h0;
\$next\fifo_we = valid_in;
end
always @* begin
\$next\fifo_din = 36'h000000000;
\$next\fifo_din = { in_end, enc_in_ctr, enc_in };
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = fifo_writable;
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = fifo_readable;
end
always @* begin
\$next\enc_out = 30'h00000000;
\$next\enc_out = fifo_dout[29:0];
end
always @* begin
\$next\enc_out_ctr = 5'h00;
\$next\enc_out_ctr = fifo_dout[34:30];
end
always @* begin
\$next\out_end = 1'h0;
\$next\out_end = fifo_dout[35];
end
always @* begin
\$next\fifo_re = 1'h0;
\$next\fifo_re = latch_output;
end
always @* begin
\$next\close_full = close_full;
\$next\close_full = \$1 ;
casez (rst)
1'h1:
\$next\close_full = 1'h0;
endcase
end
assign fifo_re = \$next\fifo_re ;
assign out_end = \$next\out_end ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign valid_out = \$next\valid_out ;
assign writable = \$next\writable ;
assign fifo_din = \$next\fifo_din ;
assign fifo_we = \$next\fifo_we ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.difference" *)
(* generator = "nMigen" *)
module difference(pixel_in, predic_in, \pixel_in$1 , \predic_in$2 , end_in, rst, clk, val_out, \val_out$3 , \val_out$4 , \val_out$5 , valid_out, end_out, valid_in);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
wire [13:0] \$15 ;
wire [12:0] \$16 ;
wire [13:0] \$18 ;
wire [12:0] \$6 ;
wire [12:0] \$8 ;
(* src = "difference.py:72" *)
reg \$next\end_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out$3 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$4 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$5 ;
(* src = "difference.py:68" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "difference.py:71" *)
input end_in;
(* init = 1'h0 *)
(* src = "difference.py:72" *)
output end_out;
reg end_out = 1'h0;
(* src = "difference.py:55" *)
input [11:0] pixel_in;
(* src = "difference.py:55" *)
input [11:0] \pixel_in$1 ;
(* src = "difference.py:58" *)
input [11:0] predic_in;
(* src = "difference.py:58" *)
input [11:0] \predic_in$2 ;
(* src = "clk_domains.py:5" *)
input rst;
(* init = 13'h0000 *)
(* src = "difference.py:61" *)
output [12:0] val_out;
reg [12:0] val_out = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:61" *)
output [12:0] \val_out$3 ;
reg [12:0] \val_out$3 = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:64" *)
output [12:0] \val_out$4 ;
reg [12:0] \val_out$4 = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:64" *)
output [12:0] \val_out$5 ;
reg [12:0] \val_out$5 = 13'h0000;
(* src = "difference.py:67" *)
input valid_in;
(* init = 1'h0 *)
(* src = "difference.py:68" *)
output valid_out;
reg valid_out = 1'h0;
assign \$11 = pixel_in - (* src = "difference.py:90" *) predic_in;
assign \$13 = \$11 - (* src = "difference.py:90" *) 1'h1;
assign \$16 = \pixel_in$1 - (* src = "difference.py:90" *) \predic_in$2 ;
assign \$18 = \$16 - (* src = "difference.py:90" *) 1'h1;
assign \$6 = pixel_in - (* src = "difference.py:89" *) predic_in;
assign \$8 = \pixel_in$1 - (* src = "difference.py:89" *) \predic_in$2 ;
always @(posedge clk)
end_out <= \$next\end_out ;
always @(posedge clk)
valid_out <= \$next\valid_out ;
always @(posedge clk)
\val_out$5 <= \$next\val_out$5 ;
always @(posedge clk)
\val_out$4 <= \$next\val_out$4 ;
always @(posedge clk)
\val_out$3 <= \$next\val_out$3 ;
always @(posedge clk)
val_out <= \$next\val_out ;
always @* begin
\$next\val_out = val_out;
casez (valid_in)
1'h1:
\$next\val_out = \$6 ;
endcase
casez (rst)
1'h1:
\$next\val_out = 13'h0000;
endcase
end
always @* begin
\$next\val_out$3 = \val_out$3 ;
casez (valid_in)
1'h1:
\$next\val_out$3 = \$8 ;
endcase
casez (rst)
1'h1:
\$next\val_out$3 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$4 = \val_out$4 ;
casez (valid_in)
1'h1:
\$next\val_out$4 = \$10 [12:0];
endcase
casez (rst)
1'h1:
\$next\val_out$4 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$5 = \val_out$5 ;
casez (valid_in)
1'h1:
\$next\val_out$5 = \$15 [12:0];
endcase
casez (rst)
1'h1:
\$next\val_out$5 = 13'h0000;
endcase
end
always @* begin
\$next\valid_out = valid_out;
\$next\valid_out = valid_in;
casez (rst)
1'h1:
\$next\valid_out = 1'h0;
endcase
end
always @* begin
\$next\end_out = end_out;
\$next\end_out = end_in;
casez (rst)
1'h1:
\$next\end_out = 1'h0;
endcase
end
assign \$10 = \$13 ;
assign \$15 = \$18 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo.fifo" *)
(* generator = "nMigen" *)
module fifo(we, re, rst, clk, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [62:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:0] \$next\level ;
(* src = "nmigen/lib/fifo.py:70" *)
reg \$next\readable ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [62:0] \$next\unbuffered_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\unbuffered_re ;
(* src = "nmigen/lib/fifo.py:139" *)
reg \$next\unbuffered_replace ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\unbuffered_we ;
(* src = "nmigen/lib/fifo.py:66" *)
reg \$next\writable ;
(* init = 1'h0 *)
reg \$verilog_initial_trigger = 1'h0;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "nmigen/lib/fifo.py:65" *)
input [62:0] din;
(* src = "nmigen/lib/fifo.py:69" *)
output [62:0] dout;
(* src = "nmigen/lib/fifo.py:238" *)
output [9:0] level;
(* src = "nmigen/lib/fifo.py:71" *)
input re;
(* init = 1'h0 *)
(* src = "nmigen/lib/fifo.py:70" *)
output readable;
reg readable = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "nmigen/lib/fifo.py:65" *)
wire [62:0] unbuffered_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [62:0] unbuffered_dout;
(* src = "nmigen/lib/fifo.py:138" *)
wire [8:0] unbuffered_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire unbuffered_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire unbuffered_readable;
(* src = "nmigen/lib/fifo.py:139" *)
wire unbuffered_replace;
(* src = "nmigen/lib/fifo.py:67" *)
wire unbuffered_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire unbuffered_writable;
(* src = "nmigen/lib/fifo.py:67" *)
input we;
(* src = "nmigen/lib/fifo.py:66" *)
wire writable;
assign \$1 = ~ (* src = "nmigen/lib/fifo.py:256" *) readable;
assign \$3 = \$1 | (* src = "nmigen/lib/fifo.py:256" *) re;
assign \$5 = unbuffered_readable & (* src = "nmigen/lib/fifo.py:256" *) \$3 ;
assign \$7 = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;
always @(posedge clk)
readable <= \$next\readable ;
unbuffered unbuffered (
.clk(clk),
.din(unbuffered_din),
.dout(unbuffered_dout),
.level(unbuffered_level),
.re(unbuffered_re),
.readable(unbuffered_readable),
.replace(unbuffered_replace),
.rst(rst),
.we(unbuffered_we),
.writable(unbuffered_writable)
);
always @* begin
\$next\unbuffered_din = 63'h0000000000000000;
\$next\unbuffered_din = din;
end
always @* begin
\$next\unbuffered_we = 1'h0;
\$next\unbuffered_we = we;
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = unbuffered_writable;
end
always @* begin
\$next\unbuffered_replace = 1'h0;
\$next\unbuffered_replace = 1'h0;
\$verilog_initial_trigger = \$verilog_initial_trigger ;
end
always @* begin
\$next\dout = 63'h0000000000000000;
\$next\dout = unbuffered_dout;
end
always @* begin
\$next\unbuffered_re = 1'h0;
\$next\unbuffered_re = \$5 ;
end
always @* begin
\$next\readable = readable;
casez ({ re, unbuffered_re })
2'bz1:
\$next\readable = 1'h1;
2'b1z:
\$next\readable = 1'h0;
endcase
casez (rst)
1'h1:
\$next\readable = 1'h0;
endcase
end
always @* begin
\$next\level = 10'h000;
\$next\level = \$7 ;
end
assign level = \$next\level ;
assign unbuffered_re = \$next\unbuffered_re ;
assign dout = \$next\dout ;
assign unbuffered_replace = \$next\unbuffered_replace ;
assign writable = \$next\writable ;
assign unbuffered_we = \$next\unbuffered_we ;
assign unbuffered_din = \$next\unbuffered_din ;
endmodule
| 6.65974 |
module.integration_3.integration_2.converter_fifo.fifo" *)
(* generator = "nMigen" *)
module \fifo$5 (we, re, rst, clk, writable, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [35:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:0] \$next\level ;
(* src = "nmigen/lib/fifo.py:70" *)
reg \$next\readable ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [35:0] \$next\unbuffered_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\unbuffered_re ;
(* src = "nmigen/lib/fifo.py:139" *)
reg \$next\unbuffered_replace ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\unbuffered_we ;
(* src = "nmigen/lib/fifo.py:66" *)
reg \$next\writable ;
(* init = 1'h0 *)
reg \$verilog_initial_trigger = 1'h0;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "nmigen/lib/fifo.py:65" *)
input [35:0] din;
(* src = "nmigen/lib/fifo.py:69" *)
output [35:0] dout;
(* src = "nmigen/lib/fifo.py:238" *)
output [9:0] level;
(* src = "nmigen/lib/fifo.py:71" *)
input re;
(* init = 1'h0 *)
(* src = "nmigen/lib/fifo.py:70" *)
output readable;
reg readable = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "nmigen/lib/fifo.py:65" *)
wire [35:0] unbuffered_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [35:0] unbuffered_dout;
(* src = "nmigen/lib/fifo.py:138" *)
wire [8:0] unbuffered_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire unbuffered_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire unbuffered_readable;
(* src = "nmigen/lib/fifo.py:139" *)
wire unbuffered_replace;
(* src = "nmigen/lib/fifo.py:67" *)
wire unbuffered_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire unbuffered_writable;
(* src = "nmigen/lib/fifo.py:67" *)
input we;
(* src = "nmigen/lib/fifo.py:66" *)
output writable;
assign \$1 = ~ (* src = "nmigen/lib/fifo.py:256" *) readable;
assign \$3 = \$1 | (* src = "nmigen/lib/fifo.py:256" *) re;
assign \$5 = unbuffered_readable & (* src = "nmigen/lib/fifo.py:256" *) \$3 ;
assign \$7 = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;
always @(posedge clk)
readable <= \$next\readable ;
\unbuffered$6 unbuffered (
.clk(clk),
.din(unbuffered_din),
.dout(unbuffered_dout),
.level(unbuffered_level),
.re(unbuffered_re),
.readable(unbuffered_readable),
.replace(unbuffered_replace),
.rst(rst),
.we(unbuffered_we),
.writable(unbuffered_writable)
);
always @* begin
\$next\unbuffered_din = 36'h000000000;
\$next\unbuffered_din = din;
end
always @* begin
\$next\unbuffered_we = 1'h0;
\$next\unbuffered_we = we;
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = unbuffered_writable;
end
always @* begin
\$next\unbuffered_replace = 1'h0;
\$next\unbuffered_replace = 1'h0;
\$verilog_initial_trigger = \$verilog_initial_trigger ;
end
always @* begin
\$next\dout = 36'h000000000;
\$next\dout = unbuffered_dout;
end
always @* begin
\$next\unbuffered_re = 1'h0;
\$next\unbuffered_re = \$5 ;
end
always @* begin
\$next\readable = readable;
casez ({ re, unbuffered_re })
2'bz1:
\$next\readable = 1'h1;
2'b1z:
\$next\readable = 1'h0;
endcase
casez (rst)
1'h1:
\$next\readable = 1'h0;
endcase
end
always @* begin
\$next\level = 10'h000;
\$next\level = \$7 ;
end
assign level = \$next\level ;
assign unbuffered_re = \$next\unbuffered_re ;
assign dout = \$next\dout ;
assign unbuffered_replace = \$next\unbuffered_replace ;
assign writable = \$next\writable ;
assign unbuffered_we = \$next\unbuffered_we ;
assign unbuffered_din = \$next\unbuffered_din ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.force_end" *)
(* generator = "nMigen" *)
module force_end(allowed_cycles, rst, clk, fend, valid_in);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] \$next\fsm_state ;
(* src = "force_end.py:39" *)
input [23:0] allowed_cycles;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 25'h0000000 *)
(* src = "force_end.py:51" *)
reg [24:0] counter = 25'h0000000;
(* init = 1'h0 *)
(* src = "force_end.py:41" *)
output fend;
reg fend = 1'h0;
(* init = 2'h0 *)
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] fsm_state = 2'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "force_end.py:38" *)
input valid_in;
assign \$1 = counter == (* src = "force_end.py:61" *) allowed_cycles;
assign \$4 = counter + (* src = "force_end.py:60" *) 1'h1;
always @(posedge clk)
fend <= \$next\fend ;
always @(posedge clk)
counter <= \$next\counter ;
always @(posedge clk)
fsm_state <= \$next\fsm_state ;
always @* begin
\$next\fsm_state = fsm_state;
casez (fsm_state)
2'h0:
casez (valid_in)
1'h1:
\$next\fsm_state = 2'h1;
endcase
2'h1:
casez (\$1 )
1'h1:
\$next\fsm_state = 2'h2;
endcase
endcase
casez (rst)
1'h1:
\$next\fsm_state = 2'h0;
endcase
end
always @* begin
\$next\counter = counter;
casez (fsm_state)
2'h1:
\$next\counter = \$3 [24:0];
endcase
casez (rst)
1'h1:
\$next\counter = 25'h0000000;
endcase
end
always @* begin
\$next\fend = fend;
casez (fsm_state)
2'h2:
\$next\fend = 1'h1;
endcase
casez (rst)
1'h1:
\$next\fend = 1'h0;
endcase
end
assign \$3 = \$4 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo" *)
(* generator = "nMigen" *)
module lj92_pipeline_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "lj92_pipeline_fifo.py:60" *)
reg [55:0] \$next\enc_out ;
(* src = "lj92_pipeline_fifo.py:61" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [62:0] \$next\fifo_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\fifo_re ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\fifo_we ;
(* src = "lj92_pipeline_fifo.py:62" *)
reg \$next\out_end ;
(* src = "lj92_pipeline_fifo.py:63" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 1'h0 *)
(* src = "lj92_pipeline_fifo.py:67" *)
output close_full;
reg close_full = 1'h0;
(* src = "lj92_pipeline_fifo.py:54" *)
input [55:0] enc_in;
(* src = "lj92_pipeline_fifo.py:55" *)
input [5:0] enc_in_ctr;
(* src = "lj92_pipeline_fifo.py:60" *)
output [55:0] enc_out;
(* src = "lj92_pipeline_fifo.py:61" *)
output [5:0] enc_out_ctr;
(* src = "nmigen/lib/fifo.py:65" *)
wire [62:0] fifo_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [62:0] fifo_dout;
(* src = "nmigen/lib/fifo.py:238" *)
wire [9:0] fifo_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire fifo_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire fifo_readable;
(* src = "nmigen/lib/fifo.py:67" *)
wire fifo_we;
(* src = "lj92_pipeline_fifo.py:56" *)
input in_end;
(* src = "lj92_pipeline_fifo.py:59" *)
input latch_output;
(* src = "lj92_pipeline_fifo.py:62" *)
output out_end;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "lj92_pipeline_fifo.py:57" *)
input valid_in;
(* src = "lj92_pipeline_fifo.py:63" *)
output valid_out;
assign \$1 = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 9'h1f6;
always @(posedge clk)
close_full <= \$next\close_full ;
fifo fifo (
.clk(clk),
.din(fifo_din),
.dout(fifo_dout),
.level(fifo_level),
.re(fifo_re),
.readable(fifo_readable),
.rst(rst),
.we(fifo_we)
);
always @* begin
\$next\fifo_we = 1'h0;
\$next\fifo_we = valid_in;
end
always @* begin
\$next\fifo_din = 63'h0000000000000000;
\$next\fifo_din = { in_end, enc_in_ctr, enc_in };
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = fifo_readable;
end
always @* begin
\$next\enc_out = 56'h00000000000000;
\$next\enc_out = fifo_dout[55:0];
end
always @* begin
\$next\enc_out_ctr = 6'h00;
\$next\enc_out_ctr = fifo_dout[61:56];
end
always @* begin
\$next\out_end = 1'h0;
\$next\out_end = fifo_dout[62];
end
always @* begin
\$next\fifo_re = 1'h0;
\$next\fifo_re = latch_output;
end
always @* begin
\$next\close_full = close_full;
\$next\close_full = \$1 ;
casez (rst)
1'h1:
\$next\close_full = 1'h0;
endcase
end
assign fifo_re = \$next\fifo_re ;
assign out_end = \$next\out_end ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign valid_out = \$next\valid_out ;
assign fifo_din = \$next\fifo_din ;
assign fifo_we = \$next\fifo_we ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.merge" *)
(* generator = "nMigen" *)
module merge(enc_in_ctr, valid_in, end_in, \enc_in$1 , \enc_in_ctr$2 , rst, clk, enc_out, enc_out_ctr, valid_out, end_out, enc_in);
(* src = "merge.py:43" *)
reg [27:0] \$next\enc_in1 ;
(* src = "merge.py:46" *)
reg [27:0] \$next\enc_in2 ;
(* src = "merge.py:44" *)
reg [4:0] \$next\enc_in_ctr1 ;
(* src = "merge.py:47" *)
reg [4:0] \$next\enc_in_ctr2 ;
(* src = "merge.py:112" *)
reg [55:0] \$next\enc_out ;
(* src = "merge.py:113" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "merge.py:57" *)
reg \$next\end_in$4 ;
(* src = "merge.py:121" *)
reg \$next\end_out ;
(* src = "merge.py:53" *)
reg \$next\valid_in$3 ;
(* src = "merge.py:117" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "merge.py:109" *)
input [27:0] enc_in;
(* src = "merge.py:109" *)
input [27:0] \enc_in$1 ;
(* src = "merge.py:43" *)
wire [27:0] enc_in1;
(* src = "merge.py:46" *)
wire [27:0] enc_in2;
(* src = "merge.py:110" *)
input [4:0] enc_in_ctr;
(* src = "merge.py:110" *)
input [4:0] \enc_in_ctr$2 ;
(* src = "merge.py:44" *)
wire [4:0] enc_in_ctr1;
(* src = "merge.py:47" *)
wire [4:0] enc_in_ctr2;
(* src = "merge.py:112" *)
output [55:0] enc_out;
(* src = "merge.py:49" *)
wire [55:0] \enc_out$6 ;
(* src = "merge.py:113" *)
output [5:0] enc_out_ctr;
(* src = "merge.py:50" *)
wire [5:0] \enc_out_ctr$5 ;
(* src = "merge.py:120" *)
input end_in;
(* src = "merge.py:57" *)
wire \end_in$4 ;
(* src = "merge.py:121" *)
output end_out;
(* src = "merge.py:58" *)
wire \end_out$8 ;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "merge.py:116" *)
input valid_in;
(* src = "merge.py:53" *)
wire \valid_in$3 ;
(* src = "merge.py:117" *)
output valid_out;
(* src = "merge.py:54" *)
wire \valid_out$7 ;
\anonymous$4 \$9 (
.clk(clk),
.enc_in1(enc_in1),
.enc_in2(enc_in2),
.enc_in_ctr1(enc_in_ctr1),
.enc_in_ctr2(enc_in_ctr2),
.enc_out(\enc_out$6 ),
.enc_out_ctr(\enc_out_ctr$5 ),
.end_in(\end_in$4 ),
.end_out(\end_out$8 ),
.rst(rst),
.valid_in(\valid_in$3 ),
.valid_out(\valid_out$7 )
);
always @* begin
\$next\enc_in1 = 28'h0000000;
\$next\enc_in1 = enc_in;
end
always @* begin
\$next\enc_in_ctr1 = 5'h00;
\$next\enc_in_ctr1 = enc_in_ctr;
end
always @* begin
\$next\valid_in$3 = 1'h0;
\$next\valid_in$3 = valid_in;
end
always @* begin
\$next\end_in$4 = 1'h0;
\$next\end_in$4 = end_in;
end
always @* begin
\$next\enc_in2 = 28'h0000000;
\$next\enc_in2 = \enc_in$1 ;
end
always @* begin
\$next\enc_in_ctr2 = 5'h00;
\$next\enc_in_ctr2 = \enc_in_ctr$2 ;
end
always @* begin
\$next\enc_out = 56'h00000000000000;
\$next\enc_out = \enc_out$6 ;
end
always @* begin
\$next\enc_out_ctr = 6'h00;
\$next\enc_out_ctr = \enc_out_ctr$5 ;
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = \valid_out$7 ;
end
always @* begin
\$next\end_out = 1'h0;
\$next\end_out = \end_out$8 ;
end
assign end_out = \$next\end_out ;
assign valid_out = \$next\valid_out ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign enc_in_ctr2 = \$next\enc_in_ctr2 ;
assign enc_in2 = \$next\enc_in2 ;
assign \end_in$4 = \$next\end_in$4 ;
assign \valid_in$3 = \$next\valid_in$3 ;
assign enc_in_ctr1 = \$next\enc_in_ctr1 ;
assign enc_in1 = \$next\enc_in1 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.register_file" *)
(* generator = "nMigen" *)
module register_file(full_clk, width, height, allowed_cycles, full_rst);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(* src = "register_file.py:36" *)
reg [15:0] \$next\height ;
(* src = "register_file.py:51" *)
reg [15:0] \$next\height_reg ;
(* src = "register_file.py:37" *)
reg [15:0] \$next\width ;
(* src = "register_file.py:50" *)
reg [15:0] \$next\width_reg ;
(* src = "register_file.py:38" *)
output [23:0] allowed_cycles;
(* init = 24'h000000 *)
(* src = "register_file.py:52" *)
reg [23:0] allowed_cycles_reg = 24'h000000;
(* src = "clk_domains.py:4" *)
input full_clk;
(* src = "clk_domains.py:4" *)
input full_rst;
(* src = "register_file.py:36" *)
output [15:0] height;
(* init = 16'h0000 *)
(* src = "register_file.py:51" *)
reg [15:0] height_reg = 16'h0000;
(* src = "register_file.py:37" *)
output [15:0] width;
(* init = 16'h0000 *)
(* src = "register_file.py:50" *)
reg [15:0] width_reg = 16'h0000;
always @(posedge full_clk)
allowed_cycles_reg <= \$next\allowed_cycles_reg ;
always @(posedge full_clk)
height_reg <= \$next\height_reg ;
always @(posedge full_clk)
width_reg <= \$next\width_reg ;
always @* begin
\$next\width_reg = width_reg;
\$next\width_reg = 16'h1000;
casez (full_rst)
1'h1:
\$next\width_reg = 16'h0000;
endcase
end
always @* begin
\$next\height_reg = height_reg;
\$next\height_reg = 16'h0c00;
casez (full_rst)
1'h1:
\$next\height_reg = 16'h0000;
endcase
end
always @* begin
\$next\allowed_cycles_reg = allowed_cycles_reg;
\$next\allowed_cycles_reg = 24'h65b710;
casez (full_rst)
1'h1:
\$next\allowed_cycles_reg = 24'h000000;
endcase
end
always @* begin
\$next\width = 16'h0000;
\$next\width = width_reg;
end
always @* begin
\$next\height = 16'h0000;
\$next\height = height_reg;
end
always @* begin
\$next\allowed_cycles = 24'h000000;
\$next\allowed_cycles = allowed_cycles_reg;
end
assign allowed_cycles = \$next\allowed_cycles ;
assign height = \$next\height ;
assign width = \$next\width ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.merge.anonymous" *)
(* generator = "nMigen" *)
module \anonymous$4 (enc_in_ctr1, enc_in_ctr2, enc_in1, enc_in2, end_in, rst, clk, enc_out_ctr, enc_out, valid_out, end_out, valid_in);
wire [5:0] \$1 ;
wire [58:0] \$3 ;
wire [58:0] \$4 ;
wire [58:0] \$6 ;
(* src = "merge.py:49" *)
reg [55:0] \$next\enc_out ;
(* src = "merge.py:50" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "merge.py:58" *)
reg \$next\end_out ;
(* src = "merge.py:54" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "merge.py:43" *)
input [27:0] enc_in1;
(* src = "merge.py:46" *)
input [27:0] enc_in2;
(* src = "merge.py:44" *)
input [4:0] enc_in_ctr1;
(* src = "merge.py:47" *)
input [4:0] enc_in_ctr2;
(* init = 56'h00000000000000 *)
(* src = "merge.py:49" *)
output [55:0] enc_out;
reg [55:0] enc_out = 56'h00000000000000;
(* init = 6'h00 *)
(* src = "merge.py:50" *)
output [5:0] enc_out_ctr;
reg [5:0] enc_out_ctr = 6'h00;
(* src = "merge.py:57" *)
input end_in;
(* init = 1'h0 *)
(* src = "merge.py:58" *)
output end_out;
reg end_out = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "merge.py:53" *)
input valid_in;
(* init = 1'h0 *)
(* src = "merge.py:54" *)
output valid_out;
reg valid_out = 1'h0;
assign \$1 = enc_in_ctr1 + (* src = "merge.py:74" *) enc_in_ctr2;
assign \$4 = enc_in1 <<< (* src = "merge.py:75" *) enc_in_ctr2;
assign \$6 = \$4 | (* src = "merge.py:75" *) enc_in2;
always @(posedge clk)
end_out <= \$next\end_out ;
always @(posedge clk)
valid_out <= \$next\valid_out ;
always @(posedge clk)
enc_out <= \$next\enc_out ;
always @(posedge clk)
enc_out_ctr <= \$next\enc_out_ctr ;
always @* begin
\$next\enc_out_ctr = enc_out_ctr;
casez (valid_in)
1'h1:
\$next\enc_out_ctr = \$1 ;
endcase
casez (rst)
1'h1:
\$next\enc_out_ctr = 6'h00;
endcase
end
always @* begin
\$next\enc_out = enc_out;
casez (valid_in)
1'h1:
\$next\enc_out = \$3 [55:0];
endcase
casez (rst)
1'h1:
\$next\enc_out = 56'h00000000000000;
endcase
end
always @* begin
\$next\valid_out = valid_out;
\$next\valid_out = valid_in;
casez (rst)
1'h1:
\$next\valid_out = 1'h0;
endcase
end
always @* begin
\$next\end_out = end_out;
\$next\end_out = end_in;
casez (rst)
1'h1:
\$next\end_out = 1'h0;
endcase
end
assign \$3 = \$6 ;
endmodule
| 6.65974 |
module.auto_reset" *)
(* generator = "nMigen" *)
module auto_reset(hs2_in, end_in, rst, clk, reset_out, hs1_in);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* src = "auto_reset.py:37" *)
input hs1_in;
(* src = "auto_reset.py:40" *)
input hs2_in;
(* init = 1'h0 *)
(* src = "auto_reset.py:43" *)
output reset_out;
reg reset_out = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
assign \$9 = \$5 & (* src = "auto_reset.py:54" *) \$7 ;
assign \$1 = hs1_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$3 = hs2_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$5 = \$1 & (* src = "auto_reset.py:54" *) \$3 ;
assign \$7 = end_in == (* src = "auto_reset.py:54" *) 1'h1;
always @(posedge clk)
reset_out <= \$next\reset_out ;
always @* begin
\$next\reset_out = reset_out;
casez (\$9 )
1'h1:
\$next\reset_out = 1'h1;
endcase
casez (rst)
1'h1:
\$next\reset_out = 1'h0;
endcase
end
endmodule
| 6.823562 |
module.integration_3.integration_2.converter_fifo" *)
(* generator = "nMigen" *)
module converter_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "converter_fifo.py:61" *)
reg \$next\close_full ;
(* src = "converter_fifo.py:65" *)
reg [29:0] \$next\enc_out ;
(* src = "converter_fifo.py:66" *)
reg [4:0] \$next\enc_out_ctr ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [35:0] \$next\fifo_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\fifo_re ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\fifo_we ;
(* src = "converter_fifo.py:67" *)
reg \$next\out_end ;
(* src = "converter_fifo.py:68" *)
reg \$next\valid_out ;
(* src = "converter_fifo.py:60" *)
reg \$next\writable ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 1'h0 *)
(* src = "converter_fifo.py:61" *)
output close_full;
reg close_full = 1'h0;
(* src = "converter_fifo.py:56" *)
input [29:0] enc_in;
(* src = "converter_fifo.py:57" *)
input [4:0] enc_in_ctr;
(* src = "converter_fifo.py:65" *)
output [29:0] enc_out;
(* src = "converter_fifo.py:66" *)
output [4:0] enc_out_ctr;
(* src = "nmigen/lib/fifo.py:65" *)
wire [35:0] fifo_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [35:0] fifo_dout;
(* src = "nmigen/lib/fifo.py:238" *)
wire [9:0] fifo_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire fifo_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire fifo_readable;
(* src = "nmigen/lib/fifo.py:67" *)
wire fifo_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire fifo_writable;
(* src = "converter_fifo.py:58" *)
input in_end;
(* src = "converter_fifo.py:64" *)
input latch_output;
(* src = "converter_fifo.py:67" *)
output out_end;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "converter_fifo.py:59" *)
input valid_in;
(* src = "converter_fifo.py:68" *)
output valid_out;
(* src = "converter_fifo.py:60" *)
wire writable;
assign \$1 = fifo_level >= (* src = "converter_fifo.py:100" *) 9'h1fb;
always @(posedge clk)
close_full <= \$next\close_full ;
\fifo$5 fifo (
.clk(clk),
.din(fifo_din),
.dout(fifo_dout),
.level(fifo_level),
.re(fifo_re),
.readable(fifo_readable),
.rst(rst),
.we(fifo_we),
.writable(fifo_writable)
);
always @* begin
\$next\fifo_we = 1'h0;
\$next\fifo_we = valid_in;
end
always @* begin
\$next\fifo_din = 36'h000000000;
\$next\fifo_din = { in_end, enc_in_ctr, enc_in };
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = fifo_writable;
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = fifo_readable;
end
always @* begin
\$next\enc_out = 30'h00000000;
\$next\enc_out = fifo_dout[29:0];
end
always @* begin
\$next\enc_out_ctr = 5'h00;
\$next\enc_out_ctr = fifo_dout[34:30];
end
always @* begin
\$next\out_end = 1'h0;
\$next\out_end = fifo_dout[35];
end
always @* begin
\$next\fifo_re = 1'h0;
\$next\fifo_re = latch_output;
end
always @* begin
\$next\close_full = close_full;
\$next\close_full = \$1 ;
casez (rst)
1'h1:
\$next\close_full = 1'h0;
endcase
end
assign fifo_re = \$next\fifo_re ;
assign out_end = \$next\out_end ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign valid_out = \$next\valid_out ;
assign writable = \$next\writable ;
assign fifo_din = \$next\fifo_din ;
assign fifo_we = \$next\fifo_we ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.difference" *)
(* generator = "nMigen" *)
module difference(pixel_in, predic_in, \pixel_in$1 , \predic_in$2 , end_in, rst, clk, val_out, \val_out$3 , \val_out$4 , \val_out$5 , valid_out, end_out, valid_in);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
wire [13:0] \$15 ;
wire [12:0] \$16 ;
wire [13:0] \$18 ;
wire [12:0] \$6 ;
wire [12:0] \$8 ;
(* src = "difference.py:72" *)
reg \$next\end_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out$3 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$4 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$5 ;
(* src = "difference.py:68" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "difference.py:71" *)
input end_in;
(* init = 1'h0 *)
(* src = "difference.py:72" *)
output end_out;
reg end_out = 1'h0;
(* src = "difference.py:55" *)
input [11:0] pixel_in;
(* src = "difference.py:55" *)
input [11:0] \pixel_in$1 ;
(* src = "difference.py:58" *)
input [11:0] predic_in;
(* src = "difference.py:58" *)
input [11:0] \predic_in$2 ;
(* src = "clk_domains.py:5" *)
input rst;
(* init = 13'h0000 *)
(* src = "difference.py:61" *)
output [12:0] val_out;
reg [12:0] val_out = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:61" *)
output [12:0] \val_out$3 ;
reg [12:0] \val_out$3 = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:64" *)
output [12:0] \val_out$4 ;
reg [12:0] \val_out$4 = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:64" *)
output [12:0] \val_out$5 ;
reg [12:0] \val_out$5 = 13'h0000;
(* src = "difference.py:67" *)
input valid_in;
(* init = 1'h0 *)
(* src = "difference.py:68" *)
output valid_out;
reg valid_out = 1'h0;
assign \$11 = pixel_in - (* src = "difference.py:90" *) predic_in;
assign \$13 = \$11 - (* src = "difference.py:90" *) 1'h1;
assign \$16 = \pixel_in$1 - (* src = "difference.py:90" *) \predic_in$2 ;
assign \$18 = \$16 - (* src = "difference.py:90" *) 1'h1;
assign \$6 = pixel_in - (* src = "difference.py:89" *) predic_in;
assign \$8 = \pixel_in$1 - (* src = "difference.py:89" *) \predic_in$2 ;
always @(posedge clk)
end_out <= \$next\end_out ;
always @(posedge clk)
valid_out <= \$next\valid_out ;
always @(posedge clk)
\val_out$5 <= \$next\val_out$5 ;
always @(posedge clk)
\val_out$4 <= \$next\val_out$4 ;
always @(posedge clk)
\val_out$3 <= \$next\val_out$3 ;
always @(posedge clk)
val_out <= \$next\val_out ;
always @* begin
\$next\val_out = val_out;
casez (valid_in)
1'h1:
\$next\val_out = \$6 ;
endcase
casez (rst)
1'h1:
\$next\val_out = 13'h0000;
endcase
end
always @* begin
\$next\val_out$3 = \val_out$3 ;
casez (valid_in)
1'h1:
\$next\val_out$3 = \$8 ;
endcase
casez (rst)
1'h1:
\$next\val_out$3 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$4 = \val_out$4 ;
casez (valid_in)
1'h1:
\$next\val_out$4 = \$10 [12:0];
endcase
casez (rst)
1'h1:
\$next\val_out$4 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$5 = \val_out$5 ;
casez (valid_in)
1'h1:
\$next\val_out$5 = \$15 [12:0];
endcase
casez (rst)
1'h1:
\$next\val_out$5 = 13'h0000;
endcase
end
always @* begin
\$next\valid_out = valid_out;
\$next\valid_out = valid_in;
casez (rst)
1'h1:
\$next\valid_out = 1'h0;
endcase
end
always @* begin
\$next\end_out = end_out;
\$next\end_out = end_in;
casez (rst)
1'h1:
\$next\end_out = 1'h0;
endcase
end
assign \$10 = \$13 ;
assign \$15 = \$18 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo.fifo" *)
(* generator = "nMigen" *)
module fifo(we, re, rst, clk, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [62:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:0] \$next\level ;
(* src = "nmigen/lib/fifo.py:70" *)
reg \$next\readable ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [62:0] \$next\unbuffered_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\unbuffered_re ;
(* src = "nmigen/lib/fifo.py:139" *)
reg \$next\unbuffered_replace ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\unbuffered_we ;
(* src = "nmigen/lib/fifo.py:66" *)
reg \$next\writable ;
(* init = 1'h0 *)
reg \$verilog_initial_trigger = 1'h0;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "nmigen/lib/fifo.py:65" *)
input [62:0] din;
(* src = "nmigen/lib/fifo.py:69" *)
output [62:0] dout;
(* src = "nmigen/lib/fifo.py:238" *)
output [9:0] level;
(* src = "nmigen/lib/fifo.py:71" *)
input re;
(* init = 1'h0 *)
(* src = "nmigen/lib/fifo.py:70" *)
output readable;
reg readable = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "nmigen/lib/fifo.py:65" *)
wire [62:0] unbuffered_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [62:0] unbuffered_dout;
(* src = "nmigen/lib/fifo.py:138" *)
wire [8:0] unbuffered_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire unbuffered_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire unbuffered_readable;
(* src = "nmigen/lib/fifo.py:139" *)
wire unbuffered_replace;
(* src = "nmigen/lib/fifo.py:67" *)
wire unbuffered_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire unbuffered_writable;
(* src = "nmigen/lib/fifo.py:67" *)
input we;
(* src = "nmigen/lib/fifo.py:66" *)
wire writable;
assign \$1 = ~ (* src = "nmigen/lib/fifo.py:256" *) readable;
assign \$3 = \$1 | (* src = "nmigen/lib/fifo.py:256" *) re;
assign \$5 = unbuffered_readable & (* src = "nmigen/lib/fifo.py:256" *) \$3 ;
assign \$7 = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;
always @(posedge clk)
readable <= \$next\readable ;
unbuffered unbuffered (
.clk(clk),
.din(unbuffered_din),
.dout(unbuffered_dout),
.level(unbuffered_level),
.re(unbuffered_re),
.readable(unbuffered_readable),
.replace(unbuffered_replace),
.rst(rst),
.we(unbuffered_we),
.writable(unbuffered_writable)
);
always @* begin
\$next\unbuffered_din = 63'h0000000000000000;
\$next\unbuffered_din = din;
end
always @* begin
\$next\unbuffered_we = 1'h0;
\$next\unbuffered_we = we;
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = unbuffered_writable;
end
always @* begin
\$next\unbuffered_replace = 1'h0;
\$next\unbuffered_replace = 1'h0;
\$verilog_initial_trigger = \$verilog_initial_trigger ;
end
always @* begin
\$next\dout = 63'h0000000000000000;
\$next\dout = unbuffered_dout;
end
always @* begin
\$next\unbuffered_re = 1'h0;
\$next\unbuffered_re = \$5 ;
end
always @* begin
\$next\readable = readable;
casez ({ re, unbuffered_re })
2'bz1:
\$next\readable = 1'h1;
2'b1z:
\$next\readable = 1'h0;
endcase
casez (rst)
1'h1:
\$next\readable = 1'h0;
endcase
end
always @* begin
\$next\level = 10'h000;
\$next\level = \$7 ;
end
assign level = \$next\level ;
assign unbuffered_re = \$next\unbuffered_re ;
assign dout = \$next\dout ;
assign unbuffered_replace = \$next\unbuffered_replace ;
assign writable = \$next\writable ;
assign unbuffered_we = \$next\unbuffered_we ;
assign unbuffered_din = \$next\unbuffered_din ;
endmodule
| 6.65974 |
module.integration_3.integration_2.converter_fifo.fifo" *)
(* generator = "nMigen" *)
module \fifo$5 (we, re, rst, clk, writable, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [35:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:0] \$next\level ;
(* src = "nmigen/lib/fifo.py:70" *)
reg \$next\readable ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [35:0] \$next\unbuffered_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\unbuffered_re ;
(* src = "nmigen/lib/fifo.py:139" *)
reg \$next\unbuffered_replace ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\unbuffered_we ;
(* src = "nmigen/lib/fifo.py:66" *)
reg \$next\writable ;
(* init = 1'h0 *)
reg \$verilog_initial_trigger = 1'h0;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "nmigen/lib/fifo.py:65" *)
input [35:0] din;
(* src = "nmigen/lib/fifo.py:69" *)
output [35:0] dout;
(* src = "nmigen/lib/fifo.py:238" *)
output [9:0] level;
(* src = "nmigen/lib/fifo.py:71" *)
input re;
(* init = 1'h0 *)
(* src = "nmigen/lib/fifo.py:70" *)
output readable;
reg readable = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "nmigen/lib/fifo.py:65" *)
wire [35:0] unbuffered_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [35:0] unbuffered_dout;
(* src = "nmigen/lib/fifo.py:138" *)
wire [8:0] unbuffered_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire unbuffered_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire unbuffered_readable;
(* src = "nmigen/lib/fifo.py:139" *)
wire unbuffered_replace;
(* src = "nmigen/lib/fifo.py:67" *)
wire unbuffered_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire unbuffered_writable;
(* src = "nmigen/lib/fifo.py:67" *)
input we;
(* src = "nmigen/lib/fifo.py:66" *)
output writable;
assign \$1 = ~ (* src = "nmigen/lib/fifo.py:256" *) readable;
assign \$3 = \$1 | (* src = "nmigen/lib/fifo.py:256" *) re;
assign \$5 = unbuffered_readable & (* src = "nmigen/lib/fifo.py:256" *) \$3 ;
assign \$7 = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;
always @(posedge clk)
readable <= \$next\readable ;
\unbuffered$6 unbuffered (
.clk(clk),
.din(unbuffered_din),
.dout(unbuffered_dout),
.level(unbuffered_level),
.re(unbuffered_re),
.readable(unbuffered_readable),
.replace(unbuffered_replace),
.rst(rst),
.we(unbuffered_we),
.writable(unbuffered_writable)
);
always @* begin
\$next\unbuffered_din = 36'h000000000;
\$next\unbuffered_din = din;
end
always @* begin
\$next\unbuffered_we = 1'h0;
\$next\unbuffered_we = we;
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = unbuffered_writable;
end
always @* begin
\$next\unbuffered_replace = 1'h0;
\$next\unbuffered_replace = 1'h0;
\$verilog_initial_trigger = \$verilog_initial_trigger ;
end
always @* begin
\$next\dout = 36'h000000000;
\$next\dout = unbuffered_dout;
end
always @* begin
\$next\unbuffered_re = 1'h0;
\$next\unbuffered_re = \$5 ;
end
always @* begin
\$next\readable = readable;
casez ({ re, unbuffered_re })
2'bz1:
\$next\readable = 1'h1;
2'b1z:
\$next\readable = 1'h0;
endcase
casez (rst)
1'h1:
\$next\readable = 1'h0;
endcase
end
always @* begin
\$next\level = 10'h000;
\$next\level = \$7 ;
end
assign level = \$next\level ;
assign unbuffered_re = \$next\unbuffered_re ;
assign dout = \$next\dout ;
assign unbuffered_replace = \$next\unbuffered_replace ;
assign writable = \$next\writable ;
assign unbuffered_we = \$next\unbuffered_we ;
assign unbuffered_din = \$next\unbuffered_din ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.force_end" *)
(* generator = "nMigen" *)
module force_end(allowed_cycles, rst, clk, fend, valid_in);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] \$next\fsm_state ;
(* src = "force_end.py:39" *)
input [23:0] allowed_cycles;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 25'h0000000 *)
(* src = "force_end.py:51" *)
reg [24:0] counter = 25'h0000000;
(* init = 1'h0 *)
(* src = "force_end.py:41" *)
output fend;
reg fend = 1'h0;
(* init = 2'h0 *)
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] fsm_state = 2'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "force_end.py:38" *)
input valid_in;
assign \$1 = counter == (* src = "force_end.py:61" *) allowed_cycles;
assign \$4 = counter + (* src = "force_end.py:60" *) 1'h1;
always @(posedge clk)
fend <= \$next\fend ;
always @(posedge clk)
counter <= \$next\counter ;
always @(posedge clk)
fsm_state <= \$next\fsm_state ;
always @* begin
\$next\fsm_state = fsm_state;
casez (fsm_state)
2'h0:
casez (valid_in)
1'h1:
\$next\fsm_state = 2'h1;
endcase
2'h1:
casez (\$1 )
1'h1:
\$next\fsm_state = 2'h2;
endcase
endcase
casez (rst)
1'h1:
\$next\fsm_state = 2'h0;
endcase
end
always @* begin
\$next\counter = counter;
casez (fsm_state)
2'h1:
\$next\counter = \$3 [24:0];
endcase
casez (rst)
1'h1:
\$next\counter = 25'h0000000;
endcase
end
always @* begin
\$next\fend = fend;
casez (fsm_state)
2'h2:
\$next\fend = 1'h1;
endcase
casez (rst)
1'h1:
\$next\fend = 1'h0;
endcase
end
assign \$3 = \$4 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo" *)
(* generator = "nMigen" *)
module lj92_pipeline_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "lj92_pipeline_fifo.py:60" *)
reg [55:0] \$next\enc_out ;
(* src = "lj92_pipeline_fifo.py:61" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [62:0] \$next\fifo_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\fifo_re ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\fifo_we ;
(* src = "lj92_pipeline_fifo.py:62" *)
reg \$next\out_end ;
(* src = "lj92_pipeline_fifo.py:63" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 1'h0 *)
(* src = "lj92_pipeline_fifo.py:67" *)
output close_full;
reg close_full = 1'h0;
(* src = "lj92_pipeline_fifo.py:54" *)
input [55:0] enc_in;
(* src = "lj92_pipeline_fifo.py:55" *)
input [5:0] enc_in_ctr;
(* src = "lj92_pipeline_fifo.py:60" *)
output [55:0] enc_out;
(* src = "lj92_pipeline_fifo.py:61" *)
output [5:0] enc_out_ctr;
(* src = "nmigen/lib/fifo.py:65" *)
wire [62:0] fifo_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [62:0] fifo_dout;
(* src = "nmigen/lib/fifo.py:238" *)
wire [9:0] fifo_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire fifo_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire fifo_readable;
(* src = "nmigen/lib/fifo.py:67" *)
wire fifo_we;
(* src = "lj92_pipeline_fifo.py:56" *)
input in_end;
(* src = "lj92_pipeline_fifo.py:59" *)
input latch_output;
(* src = "lj92_pipeline_fifo.py:62" *)
output out_end;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "lj92_pipeline_fifo.py:57" *)
input valid_in;
(* src = "lj92_pipeline_fifo.py:63" *)
output valid_out;
assign \$1 = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 9'h1f6;
always @(posedge clk)
close_full <= \$next\close_full ;
fifo fifo (
.clk(clk),
.din(fifo_din),
.dout(fifo_dout),
.level(fifo_level),
.re(fifo_re),
.readable(fifo_readable),
.rst(rst),
.we(fifo_we)
);
always @* begin
\$next\fifo_we = 1'h0;
\$next\fifo_we = valid_in;
end
always @* begin
\$next\fifo_din = 63'h0000000000000000;
\$next\fifo_din = { in_end, enc_in_ctr, enc_in };
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = fifo_readable;
end
always @* begin
\$next\enc_out = 56'h00000000000000;
\$next\enc_out = fifo_dout[55:0];
end
always @* begin
\$next\enc_out_ctr = 6'h00;
\$next\enc_out_ctr = fifo_dout[61:56];
end
always @* begin
\$next\out_end = 1'h0;
\$next\out_end = fifo_dout[62];
end
always @* begin
\$next\fifo_re = 1'h0;
\$next\fifo_re = latch_output;
end
always @* begin
\$next\close_full = close_full;
\$next\close_full = \$1 ;
casez (rst)
1'h1:
\$next\close_full = 1'h0;
endcase
end
assign fifo_re = \$next\fifo_re ;
assign out_end = \$next\out_end ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign valid_out = \$next\valid_out ;
assign fifo_din = \$next\fifo_din ;
assign fifo_we = \$next\fifo_we ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.merge" *)
(* generator = "nMigen" *)
module merge(enc_in_ctr, valid_in, end_in, \enc_in$1 , \enc_in_ctr$2 , rst, clk, enc_out, enc_out_ctr, valid_out, end_out, enc_in);
(* src = "merge.py:43" *)
reg [27:0] \$next\enc_in1 ;
(* src = "merge.py:46" *)
reg [27:0] \$next\enc_in2 ;
(* src = "merge.py:44" *)
reg [4:0] \$next\enc_in_ctr1 ;
(* src = "merge.py:47" *)
reg [4:0] \$next\enc_in_ctr2 ;
(* src = "merge.py:112" *)
reg [55:0] \$next\enc_out ;
(* src = "merge.py:113" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "merge.py:57" *)
reg \$next\end_in$4 ;
(* src = "merge.py:121" *)
reg \$next\end_out ;
(* src = "merge.py:53" *)
reg \$next\valid_in$3 ;
(* src = "merge.py:117" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "merge.py:109" *)
input [27:0] enc_in;
(* src = "merge.py:109" *)
input [27:0] \enc_in$1 ;
(* src = "merge.py:43" *)
wire [27:0] enc_in1;
(* src = "merge.py:46" *)
wire [27:0] enc_in2;
(* src = "merge.py:110" *)
input [4:0] enc_in_ctr;
(* src = "merge.py:110" *)
input [4:0] \enc_in_ctr$2 ;
(* src = "merge.py:44" *)
wire [4:0] enc_in_ctr1;
(* src = "merge.py:47" *)
wire [4:0] enc_in_ctr2;
(* src = "merge.py:112" *)
output [55:0] enc_out;
(* src = "merge.py:49" *)
wire [55:0] \enc_out$6 ;
(* src = "merge.py:113" *)
output [5:0] enc_out_ctr;
(* src = "merge.py:50" *)
wire [5:0] \enc_out_ctr$5 ;
(* src = "merge.py:120" *)
input end_in;
(* src = "merge.py:57" *)
wire \end_in$4 ;
(* src = "merge.py:121" *)
output end_out;
(* src = "merge.py:58" *)
wire \end_out$8 ;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "merge.py:116" *)
input valid_in;
(* src = "merge.py:53" *)
wire \valid_in$3 ;
(* src = "merge.py:117" *)
output valid_out;
(* src = "merge.py:54" *)
wire \valid_out$7 ;
\anonymous$4 \$9 (
.clk(clk),
.enc_in1(enc_in1),
.enc_in2(enc_in2),
.enc_in_ctr1(enc_in_ctr1),
.enc_in_ctr2(enc_in_ctr2),
.enc_out(\enc_out$6 ),
.enc_out_ctr(\enc_out_ctr$5 ),
.end_in(\end_in$4 ),
.end_out(\end_out$8 ),
.rst(rst),
.valid_in(\valid_in$3 ),
.valid_out(\valid_out$7 )
);
always @* begin
\$next\enc_in1 = 28'h0000000;
\$next\enc_in1 = enc_in;
end
always @* begin
\$next\enc_in_ctr1 = 5'h00;
\$next\enc_in_ctr1 = enc_in_ctr;
end
always @* begin
\$next\valid_in$3 = 1'h0;
\$next\valid_in$3 = valid_in;
end
always @* begin
\$next\end_in$4 = 1'h0;
\$next\end_in$4 = end_in;
end
always @* begin
\$next\enc_in2 = 28'h0000000;
\$next\enc_in2 = \enc_in$1 ;
end
always @* begin
\$next\enc_in_ctr2 = 5'h00;
\$next\enc_in_ctr2 = \enc_in_ctr$2 ;
end
always @* begin
\$next\enc_out = 56'h00000000000000;
\$next\enc_out = \enc_out$6 ;
end
always @* begin
\$next\enc_out_ctr = 6'h00;
\$next\enc_out_ctr = \enc_out_ctr$5 ;
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = \valid_out$7 ;
end
always @* begin
\$next\end_out = 1'h0;
\$next\end_out = \end_out$8 ;
end
assign end_out = \$next\end_out ;
assign valid_out = \$next\valid_out ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign enc_in_ctr2 = \$next\enc_in_ctr2 ;
assign enc_in2 = \$next\enc_in2 ;
assign \end_in$4 = \$next\end_in$4 ;
assign \valid_in$3 = \$next\valid_in$3 ;
assign enc_in_ctr1 = \$next\enc_in_ctr1 ;
assign enc_in1 = \$next\enc_in1 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.register_file" *)
(* generator = "nMigen" *)
module register_file(full_clk, width, height, allowed_cycles, full_rst);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(* src = "register_file.py:36" *)
reg [15:0] \$next\height ;
(* src = "register_file.py:51" *)
reg [15:0] \$next\height_reg ;
(* src = "register_file.py:37" *)
reg [15:0] \$next\width ;
(* src = "register_file.py:50" *)
reg [15:0] \$next\width_reg ;
(* src = "register_file.py:38" *)
output [23:0] allowed_cycles;
(* init = 24'h000000 *)
(* src = "register_file.py:52" *)
reg [23:0] allowed_cycles_reg = 24'h000000;
(* src = "clk_domains.py:4" *)
input full_clk;
(* src = "clk_domains.py:4" *)
input full_rst;
(* src = "register_file.py:36" *)
output [15:0] height;
(* init = 16'h0000 *)
(* src = "register_file.py:51" *)
reg [15:0] height_reg = 16'h0000;
(* src = "register_file.py:37" *)
output [15:0] width;
(* init = 16'h0000 *)
(* src = "register_file.py:50" *)
reg [15:0] width_reg = 16'h0000;
always @(posedge full_clk)
allowed_cycles_reg <= \$next\allowed_cycles_reg ;
always @(posedge full_clk)
height_reg <= \$next\height_reg ;
always @(posedge full_clk)
width_reg <= \$next\width_reg ;
always @* begin
\$next\width_reg = width_reg;
\$next\width_reg = 16'h1000;
casez (full_rst)
1'h1:
\$next\width_reg = 16'h0000;
endcase
end
always @* begin
\$next\height_reg = height_reg;
\$next\height_reg = 16'h0c00;
casez (full_rst)
1'h1:
\$next\height_reg = 16'h0000;
endcase
end
always @* begin
\$next\allowed_cycles_reg = allowed_cycles_reg;
\$next\allowed_cycles_reg = 24'h65b710;
casez (full_rst)
1'h1:
\$next\allowed_cycles_reg = 24'h000000;
endcase
end
always @* begin
\$next\width = 16'h0000;
\$next\width = width_reg;
end
always @* begin
\$next\height = 16'h0000;
\$next\height = height_reg;
end
always @* begin
\$next\allowed_cycles = 24'h000000;
\$next\allowed_cycles = allowed_cycles_reg;
end
assign allowed_cycles = \$next\allowed_cycles ;
assign height = \$next\height ;
assign width = \$next\width ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.merge.anonymous" *)
(* generator = "nMigen" *)
module \anonymous$4 (enc_in_ctr1, enc_in_ctr2, enc_in1, enc_in2, end_in, rst, clk, enc_out_ctr, enc_out, valid_out, end_out, valid_in);
wire [5:0] \$1 ;
wire [58:0] \$3 ;
wire [58:0] \$4 ;
wire [58:0] \$6 ;
(* src = "merge.py:49" *)
reg [55:0] \$next\enc_out ;
(* src = "merge.py:50" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "merge.py:58" *)
reg \$next\end_out ;
(* src = "merge.py:54" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "merge.py:43" *)
input [27:0] enc_in1;
(* src = "merge.py:46" *)
input [27:0] enc_in2;
(* src = "merge.py:44" *)
input [4:0] enc_in_ctr1;
(* src = "merge.py:47" *)
input [4:0] enc_in_ctr2;
(* init = 56'h00000000000000 *)
(* src = "merge.py:49" *)
output [55:0] enc_out;
reg [55:0] enc_out = 56'h00000000000000;
(* init = 6'h00 *)
(* src = "merge.py:50" *)
output [5:0] enc_out_ctr;
reg [5:0] enc_out_ctr = 6'h00;
(* src = "merge.py:57" *)
input end_in;
(* init = 1'h0 *)
(* src = "merge.py:58" *)
output end_out;
reg end_out = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "merge.py:53" *)
input valid_in;
(* init = 1'h0 *)
(* src = "merge.py:54" *)
output valid_out;
reg valid_out = 1'h0;
assign \$1 = enc_in_ctr1 + (* src = "merge.py:74" *) enc_in_ctr2;
assign \$4 = enc_in1 <<< (* src = "merge.py:75" *) enc_in_ctr2;
assign \$6 = \$4 | (* src = "merge.py:75" *) enc_in2;
always @(posedge clk)
valid_out <= \$next\valid_out ;
always @(posedge clk)
enc_out <= \$next\enc_out ;
always @(posedge clk)
enc_out_ctr <= \$next\enc_out_ctr ;
always @(posedge clk)
end_out <= \$next\end_out ;
always @* begin
\$next\enc_out_ctr = enc_out_ctr;
casez (valid_in)
1'h1:
\$next\enc_out_ctr = \$1 ;
endcase
casez (rst)
1'h1:
\$next\enc_out_ctr = 6'h00;
endcase
end
always @* begin
\$next\enc_out = enc_out;
casez (valid_in)
1'h1:
\$next\enc_out = \$3 [55:0];
endcase
casez (rst)
1'h1:
\$next\enc_out = 56'h00000000000000;
endcase
end
always @* begin
\$next\valid_out = valid_out;
\$next\valid_out = valid_in;
casez (rst)
1'h1:
\$next\valid_out = 1'h0;
endcase
end
always @* begin
\$next\end_out = end_out;
\$next\end_out = end_in;
casez (rst)
1'h1:
\$next\end_out = 1'h0;
endcase
end
assign \$3 = \$6 ;
endmodule
| 6.65974 |
module.auto_reset" *)
(* generator = "nMigen" *)
module auto_reset(hs2_in, end_in, rst, clk, reset_out, hs1_in);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* src = "auto_reset.py:37" *)
input hs1_in;
(* src = "auto_reset.py:40" *)
input hs2_in;
(* init = 1'h0 *)
(* src = "auto_reset.py:43" *)
output reset_out;
reg reset_out = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
assign \$9 = \$5 & (* src = "auto_reset.py:54" *) \$7 ;
assign \$1 = hs1_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$3 = hs2_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$5 = \$1 & (* src = "auto_reset.py:54" *) \$3 ;
assign \$7 = end_in == (* src = "auto_reset.py:54" *) 1'h1;
always @(posedge clk)
reset_out <= \$next\reset_out ;
always @* begin
\$next\reset_out = reset_out;
casez (\$9 )
1'h1:
\$next\reset_out = 1'h1;
endcase
casez (rst)
1'h1:
\$next\reset_out = 1'h0;
endcase
end
endmodule
| 6.823562 |
module.integration_3.integration_2.converter_fifo" *)
(* generator = "nMigen" *)
module converter_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "converter_fifo.py:61" *)
reg \$next\close_full ;
(* src = "converter_fifo.py:65" *)
reg [29:0] \$next\enc_out ;
(* src = "converter_fifo.py:66" *)
reg [4:0] \$next\enc_out_ctr ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [35:0] \$next\fifo_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\fifo_re ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\fifo_we ;
(* src = "converter_fifo.py:67" *)
reg \$next\out_end ;
(* src = "converter_fifo.py:68" *)
reg \$next\valid_out ;
(* src = "converter_fifo.py:60" *)
reg \$next\writable ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 1'h0 *)
(* src = "converter_fifo.py:61" *)
output close_full;
reg close_full = 1'h0;
(* src = "converter_fifo.py:56" *)
input [29:0] enc_in;
(* src = "converter_fifo.py:57" *)
input [4:0] enc_in_ctr;
(* src = "converter_fifo.py:65" *)
output [29:0] enc_out;
(* src = "converter_fifo.py:66" *)
output [4:0] enc_out_ctr;
(* src = "nmigen/lib/fifo.py:65" *)
wire [35:0] fifo_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [35:0] fifo_dout;
(* src = "nmigen/lib/fifo.py:238" *)
wire [9:0] fifo_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire fifo_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire fifo_readable;
(* src = "nmigen/lib/fifo.py:67" *)
wire fifo_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire fifo_writable;
(* src = "converter_fifo.py:58" *)
input in_end;
(* src = "converter_fifo.py:64" *)
input latch_output;
(* src = "converter_fifo.py:67" *)
output out_end;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "converter_fifo.py:59" *)
input valid_in;
(* src = "converter_fifo.py:68" *)
output valid_out;
(* src = "converter_fifo.py:60" *)
wire writable;
assign \$1 = fifo_level >= (* src = "converter_fifo.py:100" *) 9'h1fb;
always @(posedge clk)
close_full <= \$next\close_full ;
\fifo$5 fifo (
.clk(clk),
.din(fifo_din),
.dout(fifo_dout),
.level(fifo_level),
.re(fifo_re),
.readable(fifo_readable),
.rst(rst),
.we(fifo_we),
.writable(fifo_writable)
);
always @* begin
\$next\fifo_we = 1'h0;
\$next\fifo_we = valid_in;
end
always @* begin
\$next\fifo_din = 36'h000000000;
\$next\fifo_din = { in_end, enc_in_ctr, enc_in };
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = fifo_writable;
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = fifo_readable;
end
always @* begin
\$next\enc_out = 30'h00000000;
\$next\enc_out = fifo_dout[29:0];
end
always @* begin
\$next\enc_out_ctr = 5'h00;
\$next\enc_out_ctr = fifo_dout[34:30];
end
always @* begin
\$next\out_end = 1'h0;
\$next\out_end = fifo_dout[35];
end
always @* begin
\$next\fifo_re = 1'h0;
\$next\fifo_re = latch_output;
end
always @* begin
\$next\close_full = close_full;
\$next\close_full = \$1 ;
casez (rst)
1'h1:
\$next\close_full = 1'h0;
endcase
end
assign fifo_re = \$next\fifo_re ;
assign out_end = \$next\out_end ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign valid_out = \$next\valid_out ;
assign writable = \$next\writable ;
assign fifo_din = \$next\fifo_din ;
assign fifo_we = \$next\fifo_we ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.difference" *)
(* generator = "nMigen" *)
module difference(pixel_in, predic_in, \pixel_in$1 , \predic_in$2 , end_in, rst, clk, val_out, \val_out$3 , \val_out$4 , \val_out$5 , valid_out, end_out, valid_in);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
wire [13:0] \$15 ;
wire [12:0] \$16 ;
wire [13:0] \$18 ;
wire [12:0] \$6 ;
wire [12:0] \$8 ;
(* src = "difference.py:72" *)
reg \$next\end_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out$3 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$4 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$5 ;
(* src = "difference.py:68" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "difference.py:71" *)
input end_in;
(* init = 1'h0 *)
(* src = "difference.py:72" *)
output end_out;
reg end_out = 1'h0;
(* src = "difference.py:55" *)
input [11:0] pixel_in;
(* src = "difference.py:55" *)
input [11:0] \pixel_in$1 ;
(* src = "difference.py:58" *)
input [11:0] predic_in;
(* src = "difference.py:58" *)
input [11:0] \predic_in$2 ;
(* src = "clk_domains.py:5" *)
input rst;
(* init = 13'h0000 *)
(* src = "difference.py:61" *)
output [12:0] val_out;
reg [12:0] val_out = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:61" *)
output [12:0] \val_out$3 ;
reg [12:0] \val_out$3 = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:64" *)
output [12:0] \val_out$4 ;
reg [12:0] \val_out$4 = 13'h0000;
(* init = 13'h0000 *)
(* src = "difference.py:64" *)
output [12:0] \val_out$5 ;
reg [12:0] \val_out$5 = 13'h0000;
(* src = "difference.py:67" *)
input valid_in;
(* init = 1'h0 *)
(* src = "difference.py:68" *)
output valid_out;
reg valid_out = 1'h0;
assign \$11 = pixel_in - (* src = "difference.py:90" *) predic_in;
assign \$13 = \$11 - (* src = "difference.py:90" *) 1'h1;
assign \$16 = \pixel_in$1 - (* src = "difference.py:90" *) \predic_in$2 ;
assign \$18 = \$16 - (* src = "difference.py:90" *) 1'h1;
assign \$6 = pixel_in - (* src = "difference.py:89" *) predic_in;
assign \$8 = \pixel_in$1 - (* src = "difference.py:89" *) \predic_in$2 ;
always @(posedge clk)
end_out <= \$next\end_out ;
always @(posedge clk)
valid_out <= \$next\valid_out ;
always @(posedge clk)
\val_out$5 <= \$next\val_out$5 ;
always @(posedge clk)
\val_out$4 <= \$next\val_out$4 ;
always @(posedge clk)
\val_out$3 <= \$next\val_out$3 ;
always @(posedge clk)
val_out <= \$next\val_out ;
always @* begin
\$next\val_out = val_out;
casez (valid_in)
1'h1:
\$next\val_out = \$6 ;
endcase
casez (rst)
1'h1:
\$next\val_out = 13'h0000;
endcase
end
always @* begin
\$next\val_out$3 = \val_out$3 ;
casez (valid_in)
1'h1:
\$next\val_out$3 = \$8 ;
endcase
casez (rst)
1'h1:
\$next\val_out$3 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$4 = \val_out$4 ;
casez (valid_in)
1'h1:
\$next\val_out$4 = \$10 [12:0];
endcase
casez (rst)
1'h1:
\$next\val_out$4 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$5 = \val_out$5 ;
casez (valid_in)
1'h1:
\$next\val_out$5 = \$15 [12:0];
endcase
casez (rst)
1'h1:
\$next\val_out$5 = 13'h0000;
endcase
end
always @* begin
\$next\valid_out = valid_out;
\$next\valid_out = valid_in;
casez (rst)
1'h1:
\$next\valid_out = 1'h0;
endcase
end
always @* begin
\$next\end_out = end_out;
\$next\end_out = end_in;
casez (rst)
1'h1:
\$next\end_out = 1'h0;
endcase
end
assign \$10 = \$13 ;
assign \$15 = \$18 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo.fifo" *)
(* generator = "nMigen" *)
module fifo(we, re, rst, clk, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [62:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:0] \$next\level ;
(* src = "nmigen/lib/fifo.py:70" *)
reg \$next\readable ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [62:0] \$next\unbuffered_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\unbuffered_re ;
(* src = "nmigen/lib/fifo.py:139" *)
reg \$next\unbuffered_replace ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\unbuffered_we ;
(* src = "nmigen/lib/fifo.py:66" *)
reg \$next\writable ;
(* init = 1'h0 *)
reg \$verilog_initial_trigger = 1'h0;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "nmigen/lib/fifo.py:65" *)
input [62:0] din;
(* src = "nmigen/lib/fifo.py:69" *)
output [62:0] dout;
(* src = "nmigen/lib/fifo.py:238" *)
output [9:0] level;
(* src = "nmigen/lib/fifo.py:71" *)
input re;
(* init = 1'h0 *)
(* src = "nmigen/lib/fifo.py:70" *)
output readable;
reg readable = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "nmigen/lib/fifo.py:65" *)
wire [62:0] unbuffered_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [62:0] unbuffered_dout;
(* src = "nmigen/lib/fifo.py:138" *)
wire [8:0] unbuffered_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire unbuffered_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire unbuffered_readable;
(* src = "nmigen/lib/fifo.py:139" *)
wire unbuffered_replace;
(* src = "nmigen/lib/fifo.py:67" *)
wire unbuffered_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire unbuffered_writable;
(* src = "nmigen/lib/fifo.py:67" *)
input we;
(* src = "nmigen/lib/fifo.py:66" *)
wire writable;
assign \$1 = ~ (* src = "nmigen/lib/fifo.py:256" *) readable;
assign \$3 = \$1 | (* src = "nmigen/lib/fifo.py:256" *) re;
assign \$5 = unbuffered_readable & (* src = "nmigen/lib/fifo.py:256" *) \$3 ;
assign \$7 = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;
always @(posedge clk)
readable <= \$next\readable ;
unbuffered unbuffered (
.clk(clk),
.din(unbuffered_din),
.dout(unbuffered_dout),
.level(unbuffered_level),
.re(unbuffered_re),
.readable(unbuffered_readable),
.replace(unbuffered_replace),
.rst(rst),
.we(unbuffered_we),
.writable(unbuffered_writable)
);
always @* begin
\$next\unbuffered_din = 63'h0000000000000000;
\$next\unbuffered_din = din;
end
always @* begin
\$next\unbuffered_we = 1'h0;
\$next\unbuffered_we = we;
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = unbuffered_writable;
end
always @* begin
\$next\unbuffered_replace = 1'h0;
\$next\unbuffered_replace = 1'h0;
\$verilog_initial_trigger = \$verilog_initial_trigger ;
end
always @* begin
\$next\dout = 63'h0000000000000000;
\$next\dout = unbuffered_dout;
end
always @* begin
\$next\unbuffered_re = 1'h0;
\$next\unbuffered_re = \$5 ;
end
always @* begin
\$next\readable = readable;
casez ({ re, unbuffered_re })
2'bz1:
\$next\readable = 1'h1;
2'b1z:
\$next\readable = 1'h0;
endcase
casez (rst)
1'h1:
\$next\readable = 1'h0;
endcase
end
always @* begin
\$next\level = 10'h000;
\$next\level = \$7 ;
end
assign level = \$next\level ;
assign unbuffered_re = \$next\unbuffered_re ;
assign dout = \$next\dout ;
assign unbuffered_replace = \$next\unbuffered_replace ;
assign writable = \$next\writable ;
assign unbuffered_we = \$next\unbuffered_we ;
assign unbuffered_din = \$next\unbuffered_din ;
endmodule
| 6.65974 |
module.integration_3.integration_2.converter_fifo.fifo" *)
(* generator = "nMigen" *)
module \fifo$5 (we, re, rst, clk, writable, dout, readable, level, din);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire [9:0] \$7 ;
(* src = "nmigen/lib/fifo.py:69" *)
reg [35:0] \$next\dout ;
(* src = "nmigen/lib/fifo.py:238" *)
reg [9:0] \$next\level ;
(* src = "nmigen/lib/fifo.py:70" *)
reg \$next\readable ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [35:0] \$next\unbuffered_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\unbuffered_re ;
(* src = "nmigen/lib/fifo.py:139" *)
reg \$next\unbuffered_replace ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\unbuffered_we ;
(* src = "nmigen/lib/fifo.py:66" *)
reg \$next\writable ;
(* init = 1'h0 *)
reg \$verilog_initial_trigger = 1'h0;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "nmigen/lib/fifo.py:65" *)
input [35:0] din;
(* src = "nmigen/lib/fifo.py:69" *)
output [35:0] dout;
(* src = "nmigen/lib/fifo.py:238" *)
output [9:0] level;
(* src = "nmigen/lib/fifo.py:71" *)
input re;
(* init = 1'h0 *)
(* src = "nmigen/lib/fifo.py:70" *)
output readable;
reg readable = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "nmigen/lib/fifo.py:65" *)
wire [35:0] unbuffered_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [35:0] unbuffered_dout;
(* src = "nmigen/lib/fifo.py:138" *)
wire [8:0] unbuffered_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire unbuffered_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire unbuffered_readable;
(* src = "nmigen/lib/fifo.py:139" *)
wire unbuffered_replace;
(* src = "nmigen/lib/fifo.py:67" *)
wire unbuffered_we;
(* src = "nmigen/lib/fifo.py:66" *)
wire unbuffered_writable;
(* src = "nmigen/lib/fifo.py:67" *)
input we;
(* src = "nmigen/lib/fifo.py:66" *)
output writable;
assign \$1 = ~ (* src = "nmigen/lib/fifo.py:256" *) readable;
assign \$3 = \$1 | (* src = "nmigen/lib/fifo.py:256" *) re;
assign \$5 = unbuffered_readable & (* src = "nmigen/lib/fifo.py:256" *) \$3 ;
assign \$7 = unbuffered_level + (* src = "nmigen/lib/fifo.py:263" *) readable;
always @(posedge clk)
readable <= \$next\readable ;
\unbuffered$6 unbuffered (
.clk(clk),
.din(unbuffered_din),
.dout(unbuffered_dout),
.level(unbuffered_level),
.re(unbuffered_re),
.readable(unbuffered_readable),
.replace(unbuffered_replace),
.rst(rst),
.we(unbuffered_we),
.writable(unbuffered_writable)
);
always @* begin
\$next\unbuffered_din = 36'h000000000;
\$next\unbuffered_din = din;
end
always @* begin
\$next\unbuffered_we = 1'h0;
\$next\unbuffered_we = we;
end
always @* begin
\$next\writable = 1'h0;
\$next\writable = unbuffered_writable;
end
always @* begin
\$next\unbuffered_replace = 1'h0;
\$next\unbuffered_replace = 1'h0;
\$verilog_initial_trigger = \$verilog_initial_trigger ;
end
always @* begin
\$next\dout = 36'h000000000;
\$next\dout = unbuffered_dout;
end
always @* begin
\$next\unbuffered_re = 1'h0;
\$next\unbuffered_re = \$5 ;
end
always @* begin
\$next\readable = readable;
casez ({ re, unbuffered_re })
2'bz1:
\$next\readable = 1'h1;
2'b1z:
\$next\readable = 1'h0;
endcase
casez (rst)
1'h1:
\$next\readable = 1'h0;
endcase
end
always @* begin
\$next\level = 10'h000;
\$next\level = \$7 ;
end
assign level = \$next\level ;
assign unbuffered_re = \$next\unbuffered_re ;
assign dout = \$next\dout ;
assign unbuffered_replace = \$next\unbuffered_replace ;
assign writable = \$next\writable ;
assign unbuffered_we = \$next\unbuffered_we ;
assign unbuffered_din = \$next\unbuffered_din ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.force_end" *)
(* generator = "nMigen" *)
module force_end(allowed_cycles, rst, clk, fend, valid_in);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] \$next\fsm_state ;
(* src = "force_end.py:39" *)
input [23:0] allowed_cycles;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 25'h0000000 *)
(* src = "force_end.py:51" *)
reg [24:0] counter = 25'h0000000;
(* init = 1'h0 *)
(* src = "force_end.py:41" *)
output fend;
reg fend = 1'h0;
(* init = 2'h0 *)
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] fsm_state = 2'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "force_end.py:38" *)
input valid_in;
assign \$1 = counter == (* src = "force_end.py:61" *) allowed_cycles;
assign \$4 = counter + (* src = "force_end.py:60" *) 1'h1;
always @(posedge clk)
fend <= \$next\fend ;
always @(posedge clk)
counter <= \$next\counter ;
always @(posedge clk)
fsm_state <= \$next\fsm_state ;
always @* begin
\$next\fsm_state = fsm_state;
casez (fsm_state)
2'h0:
casez (valid_in)
1'h1:
\$next\fsm_state = 2'h1;
endcase
2'h1:
casez (\$1 )
1'h1:
\$next\fsm_state = 2'h2;
endcase
endcase
casez (rst)
1'h1:
\$next\fsm_state = 2'h0;
endcase
end
always @* begin
\$next\counter = counter;
casez (fsm_state)
2'h1:
\$next\counter = \$3 [24:0];
endcase
casez (rst)
1'h1:
\$next\counter = 25'h0000000;
endcase
end
always @* begin
\$next\fend = fend;
casez (fsm_state)
2'h2:
\$next\fend = 1'h1;
endcase
casez (rst)
1'h1:
\$next\fend = 1'h0;
endcase
end
assign \$3 = \$4 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.lj92_pipeline_fifo" *)
(* generator = "nMigen" *)
module lj92_pipeline_fifo(enc_in, enc_in_ctr, in_end, latch_output, rst, clk, valid_out, enc_out, enc_out_ctr, out_end, close_full, valid_in);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "lj92_pipeline_fifo.py:60" *)
reg [55:0] \$next\enc_out ;
(* src = "lj92_pipeline_fifo.py:61" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [62:0] \$next\fifo_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\fifo_re ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\fifo_we ;
(* src = "lj92_pipeline_fifo.py:62" *)
reg \$next\out_end ;
(* src = "lj92_pipeline_fifo.py:63" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* init = 1'h0 *)
(* src = "lj92_pipeline_fifo.py:67" *)
output close_full;
reg close_full = 1'h0;
(* src = "lj92_pipeline_fifo.py:54" *)
input [55:0] enc_in;
(* src = "lj92_pipeline_fifo.py:55" *)
input [5:0] enc_in_ctr;
(* src = "lj92_pipeline_fifo.py:60" *)
output [55:0] enc_out;
(* src = "lj92_pipeline_fifo.py:61" *)
output [5:0] enc_out_ctr;
(* src = "nmigen/lib/fifo.py:65" *)
wire [62:0] fifo_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [62:0] fifo_dout;
(* src = "nmigen/lib/fifo.py:238" *)
wire [9:0] fifo_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire fifo_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire fifo_readable;
(* src = "nmigen/lib/fifo.py:67" *)
wire fifo_we;
(* src = "lj92_pipeline_fifo.py:56" *)
input in_end;
(* src = "lj92_pipeline_fifo.py:59" *)
input latch_output;
(* src = "lj92_pipeline_fifo.py:62" *)
output out_end;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "lj92_pipeline_fifo.py:57" *)
input valid_in;
(* src = "lj92_pipeline_fifo.py:63" *)
output valid_out;
assign \$1 = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 9'h1f6;
always @(posedge clk)
close_full <= \$next\close_full ;
fifo fifo (
.clk(clk),
.din(fifo_din),
.dout(fifo_dout),
.level(fifo_level),
.re(fifo_re),
.readable(fifo_readable),
.rst(rst),
.we(fifo_we)
);
always @* begin
\$next\fifo_we = 1'h0;
\$next\fifo_we = valid_in;
end
always @* begin
\$next\fifo_din = 63'h0000000000000000;
\$next\fifo_din = { in_end, enc_in_ctr, enc_in };
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = fifo_readable;
end
always @* begin
\$next\enc_out = 56'h00000000000000;
\$next\enc_out = fifo_dout[55:0];
end
always @* begin
\$next\enc_out_ctr = 6'h00;
\$next\enc_out_ctr = fifo_dout[61:56];
end
always @* begin
\$next\out_end = 1'h0;
\$next\out_end = fifo_dout[62];
end
always @* begin
\$next\fifo_re = 1'h0;
\$next\fifo_re = latch_output;
end
always @* begin
\$next\close_full = close_full;
\$next\close_full = \$1 ;
casez (rst)
1'h1:
\$next\close_full = 1'h0;
endcase
end
assign fifo_re = \$next\fifo_re ;
assign out_end = \$next\out_end ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign valid_out = \$next\valid_out ;
assign fifo_din = \$next\fifo_din ;
assign fifo_we = \$next\fifo_we ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.merge" *)
(* generator = "nMigen" *)
module merge(enc_in_ctr, valid_in, end_in, \enc_in$1 , \enc_in_ctr$2 , rst, clk, enc_out, enc_out_ctr, valid_out, end_out, enc_in);
(* src = "merge.py:43" *)
reg [27:0] \$next\enc_in1 ;
(* src = "merge.py:46" *)
reg [27:0] \$next\enc_in2 ;
(* src = "merge.py:44" *)
reg [4:0] \$next\enc_in_ctr1 ;
(* src = "merge.py:47" *)
reg [4:0] \$next\enc_in_ctr2 ;
(* src = "merge.py:112" *)
reg [55:0] \$next\enc_out ;
(* src = "merge.py:113" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "merge.py:57" *)
reg \$next\end_in$4 ;
(* src = "merge.py:121" *)
reg \$next\end_out ;
(* src = "merge.py:53" *)
reg \$next\valid_in$3 ;
(* src = "merge.py:117" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:97" *)
input clk;
(* src = "merge.py:109" *)
input [27:0] enc_in;
(* src = "merge.py:109" *)
input [27:0] \enc_in$1 ;
(* src = "merge.py:43" *)
wire [27:0] enc_in1;
(* src = "merge.py:46" *)
wire [27:0] enc_in2;
(* src = "merge.py:110" *)
input [4:0] enc_in_ctr;
(* src = "merge.py:110" *)
input [4:0] \enc_in_ctr$2 ;
(* src = "merge.py:44" *)
wire [4:0] enc_in_ctr1;
(* src = "merge.py:47" *)
wire [4:0] enc_in_ctr2;
(* src = "merge.py:112" *)
output [55:0] enc_out;
(* src = "merge.py:49" *)
wire [55:0] \enc_out$6 ;
(* src = "merge.py:113" *)
output [5:0] enc_out_ctr;
(* src = "merge.py:50" *)
wire [5:0] \enc_out_ctr$5 ;
(* src = "merge.py:120" *)
input end_in;
(* src = "merge.py:57" *)
wire \end_in$4 ;
(* src = "merge.py:121" *)
output end_out;
(* src = "merge.py:58" *)
wire \end_out$8 ;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "merge.py:116" *)
input valid_in;
(* src = "merge.py:53" *)
wire \valid_in$3 ;
(* src = "merge.py:117" *)
output valid_out;
(* src = "merge.py:54" *)
wire \valid_out$7 ;
\anonymous$4 \$9 (
.clk(clk),
.enc_in1(enc_in1),
.enc_in2(enc_in2),
.enc_in_ctr1(enc_in_ctr1),
.enc_in_ctr2(enc_in_ctr2),
.enc_out(\enc_out$6 ),
.enc_out_ctr(\enc_out_ctr$5 ),
.end_in(\end_in$4 ),
.end_out(\end_out$8 ),
.rst(rst),
.valid_in(\valid_in$3 ),
.valid_out(\valid_out$7 )
);
always @* begin
\$next\enc_in1 = 28'h0000000;
\$next\enc_in1 = enc_in;
end
always @* begin
\$next\enc_in_ctr1 = 5'h00;
\$next\enc_in_ctr1 = enc_in_ctr;
end
always @* begin
\$next\valid_in$3 = 1'h0;
\$next\valid_in$3 = valid_in;
end
always @* begin
\$next\end_in$4 = 1'h0;
\$next\end_in$4 = end_in;
end
always @* begin
\$next\enc_in2 = 28'h0000000;
\$next\enc_in2 = \enc_in$1 ;
end
always @* begin
\$next\enc_in_ctr2 = 5'h00;
\$next\enc_in_ctr2 = \enc_in_ctr$2 ;
end
always @* begin
\$next\enc_out = 56'h00000000000000;
\$next\enc_out = \enc_out$6 ;
end
always @* begin
\$next\enc_out_ctr = 6'h00;
\$next\enc_out_ctr = \enc_out_ctr$5 ;
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = \valid_out$7 ;
end
always @* begin
\$next\end_out = 1'h0;
\$next\end_out = \end_out$8 ;
end
assign end_out = \$next\end_out ;
assign valid_out = \$next\valid_out ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign enc_in_ctr2 = \$next\enc_in_ctr2 ;
assign enc_in2 = \$next\enc_in2 ;
assign \end_in$4 = \$next\end_in$4 ;
assign \valid_in$3 = \$next\valid_in$3 ;
assign enc_in_ctr1 = \$next\enc_in_ctr1 ;
assign enc_in1 = \$next\enc_in1 ;
endmodule
| 6.65974 |
module.integration_3.integration_2.integration_1.register_file" *)
(* generator = "nMigen" *)
module register_file(full_clk, width, height, allowed_cycles, full_rst);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(* src = "register_file.py:36" *)
reg [15:0] \$next\height ;
(* src = "register_file.py:51" *)
reg [15:0] \$next\height_reg ;
(* src = "register_file.py:37" *)
reg [15:0] \$next\width ;
(* src = "register_file.py:50" *)
reg [15:0] \$next\width_reg ;
(* src = "register_file.py:38" *)
output [23:0] allowed_cycles;
(* init = 24'h000000 *)
(* src = "register_file.py:52" *)
reg [23:0] allowed_cycles_reg = 24'h000000;
(* src = "clk_domains.py:4" *)
input full_clk;
(* src = "clk_domains.py:4" *)
input full_rst;
(* src = "register_file.py:36" *)
output [15:0] height;
(* init = 16'h0000 *)
(* src = "register_file.py:51" *)
reg [15:0] height_reg = 16'h0000;
(* src = "register_file.py:37" *)
output [15:0] width;
(* init = 16'h0000 *)
(* src = "register_file.py:50" *)
reg [15:0] width_reg = 16'h0000;
always @(posedge full_clk)
allowed_cycles_reg <= \$next\allowed_cycles_reg ;
always @(posedge full_clk)
height_reg <= \$next\height_reg ;
always @(posedge full_clk)
width_reg <= \$next\width_reg ;
always @* begin
\$next\width_reg = width_reg;
\$next\width_reg = 16'h1000;
casez (full_rst)
1'h1:
\$next\width_reg = 16'h0000;
endcase
end
always @* begin
\$next\height_reg = height_reg;
\$next\height_reg = 16'h0c00;
casez (full_rst)
1'h1:
\$next\height_reg = 16'h0000;
endcase
end
always @* begin
\$next\allowed_cycles_reg = allowed_cycles_reg;
\$next\allowed_cycles_reg = 24'h65b710;
casez (full_rst)
1'h1:
\$next\allowed_cycles_reg = 24'h000000;
endcase
end
always @* begin
\$next\width = 16'h0000;
\$next\width = width_reg;
end
always @* begin
\$next\height = 16'h0000;
\$next\height = height_reg;
end
always @* begin
\$next\allowed_cycles = 24'h000000;
\$next\allowed_cycles = allowed_cycles_reg;
end
assign allowed_cycles = \$next\allowed_cycles ;
assign height = \$next\height ;
assign width = \$next\width ;
endmodule
| 6.65974 |
module address_gen_read (
address_latch,
rst,
clk,
address_o,
address_valid,
starting_address
);
wire [32:0] \$1 ;
wire [32:0] \$2 ;
wire [32:0] \$4 ;
wire [32:0] \$5 ;
(* src = "address_generator.py:35" *)
reg [31:0] \$next\address_o ;
(* src = "address_generator.py:36" *)
reg \$next\address_valid ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg \$next\fsm_state ;
(* src = "address_generator.py:37" *)
input address_latch;
(* init = 32'd0 *) (* src = "address_generator.py:35" *)
output [31:0] address_o;
reg [31:0] address_o = 32'd0;
(* init = 1'h0 *) (* src = "address_generator.py:36" *)
output address_valid;
reg address_valid = 1'h0;
(* src = "nmigen/hdl/mem.py:160" *)
input clk;
(* init = 1'h0 *) (* src = "nmigen/hdl/dsl.py:244" *)
reg fsm_state = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "address_generator.py:39" *)
input [31:0] starting_address;
assign \$2 = address_o + (* src = "address_generator.py:58" *) 8'h80;
assign \$5 = address_o + (* src = "address_generator.py:64" *) 8'h80;
always @(posedge clk) fsm_state <= \$next\fsm_state ;
always @(posedge clk) address_valid <= \$next\address_valid ;
always @(posedge clk) address_o <= \$next\address_o ;
always @* begin
\$next\address_o = address_o;
casez (fsm_state)
1'h0: begin
\$next\address_o = starting_address;
casez (address_latch)
1'h1: \$next\address_o = \$1 [31:0];
endcase
end
1'h1:
casez (address_latch)
1'h1: \$next\address_o = \$4 [31:0];
endcase
endcase
casez (rst)
1'h1: \$next\address_o = 32'd0;
endcase
end
always @* begin
\$next\address_valid = address_valid;
casez (fsm_state)
1'h0: \$next\address_valid = 1'h1;
endcase
casez (rst)
1'h1: \$next\address_valid = 1'h0;
endcase
end
always @* begin
\$next\fsm_state = fsm_state;
casez (fsm_state)
1'h0:
casez (address_latch)
1'h1: \$next\fsm_state = 1'h1;
endcase
endcase
casez (rst)
1'h1: \$next\fsm_state = 1'h0;
endcase
end
assign \$1 = \$2 ;
assign \$4 = \$5 ;
endmodule
| 6.681018 |
module address_gen_write (
address_latch,
rst,
clk,
address_o,
address_valid,
starting_address
);
wire [32:0] \$1 ;
wire [32:0] \$2 ;
wire [32:0] \$4 ;
wire [32:0] \$5 ;
(* src = "address_generator.py:35" *)
reg [31:0] \$next\address_o ;
(* src = "address_generator.py:36" *)
reg \$next\address_valid ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg \$next\fsm_state ;
(* src = "address_generator.py:37" *)
input address_latch;
(* init = 32'd0 *) (* src = "address_generator.py:35" *)
output [31:0] address_o;
reg [31:0] address_o = 32'd0;
(* init = 1'h0 *) (* src = "address_generator.py:36" *)
output address_valid;
reg address_valid = 1'h0;
(* src = "nmigen/hdl/mem.py:160" *)
input clk;
(* init = 1'h0 *) (* src = "nmigen/hdl/dsl.py:244" *)
reg fsm_state = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "address_generator.py:39" *)
input [31:0] starting_address;
assign \$2 = address_o + (* src = "address_generator.py:58" *) 8'h80;
assign \$5 = address_o + (* src = "address_generator.py:64" *) 8'h80;
always @(posedge clk) fsm_state <= \$next\fsm_state ;
always @(posedge clk) address_valid <= \$next\address_valid ;
always @(posedge clk) address_o <= \$next\address_o ;
always @* begin
\$next\address_o = address_o;
casez (fsm_state)
1'h0: begin
\$next\address_o = starting_address;
casez (address_latch)
1'h1: \$next\address_o = \$1 [31:0];
endcase
end
1'h1:
casez (address_latch)
1'h1: \$next\address_o = \$4 [31:0];
endcase
endcase
casez (rst)
1'h1: \$next\address_o = 32'd0;
endcase
end
always @* begin
\$next\address_valid = address_valid;
casez (fsm_state)
1'h0: \$next\address_valid = 1'h1;
endcase
casez (rst)
1'h1: \$next\address_valid = 1'h0;
endcase
end
always @* begin
\$next\fsm_state = fsm_state;
casez (fsm_state)
1'h0:
casez (address_latch)
1'h1: \$next\fsm_state = 1'h1;
endcase
endcase
casez (rst)
1'h1: \$next\fsm_state = 1'h0;
endcase
end
assign \$1 = \$2 ;
assign \$4 = \$5 ;
endmodule
| 6.824106 |
module auto_reset (
hs2_in,
end_in,
rst,
clk,
reset_out,
hs1_in
);
wire \$1 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
(* src = "auto_reset.py:43" *)
reg \$next\reset_out ;
(* src = "nmigen/hdl/mem.py:160" *)
input clk;
(* src = "auto_reset.py:34" *)
input end_in;
(* src = "auto_reset.py:37" *)
input hs1_in;
(* src = "auto_reset.py:40" *)
input hs2_in;
(* init = 1'h0 *) (* src = "auto_reset.py:43" *)
output reset_out;
reg reset_out = 1'h0;
(* src = "clk_domains.py:5" *)
input rst;
assign \$9 = \$5 & (* src = "auto_reset.py:54" *) \$7 ;
assign \$1 = hs1_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$3 = hs2_in == (* src = "auto_reset.py:54" *) 1'h1;
assign \$5 = \$1 & (* src = "auto_reset.py:54" *) \$3 ;
assign \$7 = end_in == (* src = "auto_reset.py:54" *) 1'h1;
always @(posedge clk) reset_out <= \$next\reset_out ;
always @* begin
\$next\reset_out = reset_out;
casez (\$9 )
1'h1: \$next\reset_out = 1'h1;
endcase
casez (rst)
1'h1: \$next\reset_out = 1'h0;
endcase
end
endmodule
| 6.651811 |
module difference (
pixel_in,
predic_in,
\pixel_in$1 ,
\predic_in$2 ,
end_in,
rst,
clk,
val_out,
\val_out$3 ,
\val_out$4 ,
\val_out$5 ,
valid_out,
end_out,
valid_in
);
wire [13:0] \$10 ;
wire [12:0] \$11 ;
wire [13:0] \$13 ;
wire [13:0] \$15 ;
wire [12:0] \$16 ;
wire [13:0] \$18 ;
wire [12:0] \$6 ;
wire [12:0] \$8 ;
(* src = "difference.py:72" *)
reg \$next\end_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out ;
(* src = "difference.py:61" *)
reg [12:0] \$next\val_out$3 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$4 ;
(* src = "difference.py:64" *)
reg [12:0] \$next\val_out$5 ;
(* src = "difference.py:68" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:160" *)
input clk;
(* src = "difference.py:71" *)
input end_in;
(* init = 1'h0 *) (* src = "difference.py:72" *)
output end_out;
reg end_out = 1'h0;
(* src = "difference.py:55" *)
input [11:0] pixel_in;
(* src = "difference.py:55" *)
input [11:0] \pixel_in$1 ;
(* src = "difference.py:58" *)
input [11:0] predic_in;
(* src = "difference.py:58" *)
input [11:0] \predic_in$2 ;
(* src = "clk_domains.py:5" *)
input rst;
(* init = 13'h0000 *) (* src = "difference.py:61" *)
output [12:0] val_out;
reg [12:0] val_out = 13'h0000;
(* init = 13'h0000 *) (* src = "difference.py:61" *)
output [12:0] \val_out$3 ;
reg [12:0] \val_out$3 = 13'h0000;
(* init = 13'h0000 *) (* src = "difference.py:64" *)
output [12:0] \val_out$4 ;
reg [12:0] \val_out$4 = 13'h0000;
(* init = 13'h0000 *) (* src = "difference.py:64" *)
output [12:0] \val_out$5 ;
reg [12:0] \val_out$5 = 13'h0000;
(* src = "difference.py:67" *)
input valid_in;
(* init = 1'h0 *) (* src = "difference.py:68" *)
output valid_out;
reg valid_out = 1'h0;
assign \$11 = pixel_in - (* src = "difference.py:90" *) predic_in;
assign \$13 = \$11 - (* src = "difference.py:90" *) 1'h1;
assign \$16 = \pixel_in$1 - (* src = "difference.py:90" *) \predic_in$2 ;
assign \$18 = \$16 - (* src = "difference.py:90" *) 1'h1;
assign \$6 = pixel_in - (* src = "difference.py:89" *) predic_in;
assign \$8 = \pixel_in$1 - (* src = "difference.py:89" *) \predic_in$2 ;
always @(posedge clk) end_out <= \$next\end_out ;
always @(posedge clk) valid_out <= \$next\valid_out ;
always @(posedge clk) \val_out$5 <= \$next\val_out$5 ;
always @(posedge clk) \val_out$4 <= \$next\val_out$4 ;
always @(posedge clk) \val_out$3 <= \$next\val_out$3 ;
always @(posedge clk) val_out <= \$next\val_out ;
always @* begin
\$next\val_out = val_out;
casez (valid_in)
1'h1: \$next\val_out = \$6 ;
endcase
casez (rst)
1'h1: \$next\val_out = 13'h0000;
endcase
end
always @* begin
\$next\val_out$3 = \val_out$3 ;
casez (valid_in)
1'h1: \$next\val_out$3 = \$8 ;
endcase
casez (rst)
1'h1: \$next\val_out$3 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$4 = \val_out$4 ;
casez (valid_in)
1'h1: \$next\val_out$4 = \$10 [12:0];
endcase
casez (rst)
1'h1: \$next\val_out$4 = 13'h0000;
endcase
end
always @* begin
\$next\val_out$5 = \val_out$5 ;
casez (valid_in)
1'h1: \$next\val_out$5 = \$15 [12:0];
endcase
casez (rst)
1'h1: \$next\val_out$5 = 13'h0000;
endcase
end
always @* begin
\$next\valid_out = valid_out;
\$next\valid_out = valid_in;
casez (rst)
1'h1: \$next\valid_out = 1'h0;
endcase
end
always @* begin
\$next\end_out = end_out;
\$next\end_out = end_in;
casez (rst)
1'h1: \$next\end_out = 1'h0;
endcase
end
assign \$10 = \$13 ;
assign \$15 = \$18 ;
endmodule
| 7.532482 |
module force_end (
allowed_cycles,
rst,
clk,
fend,
valid_in
);
wire \$1 ;
wire [25:0] \$3 ;
wire [25:0] \$4 ;
(* src = "force_end.py:51" *)
reg [24:0] \$next\counter ;
(* src = "force_end.py:41" *)
reg \$next\fend ;
(* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] \$next\fsm_state ;
(* src = "force_end.py:39" *)
input [23:0] allowed_cycles;
(* src = "nmigen/hdl/mem.py:160" *)
input clk;
(* init = 25'h0000000 *) (* src = "force_end.py:51" *)
reg [24:0] counter = 25'h0000000;
(* init = 1'h0 *) (* src = "force_end.py:41" *)
output fend;
reg fend = 1'h0;
(* init = 2'h0 *) (* src = "nmigen/hdl/dsl.py:244" *)
reg [1:0] fsm_state = 2'h0;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "force_end.py:38" *)
input valid_in;
assign \$1 = counter == (* src = "force_end.py:61" *) allowed_cycles;
assign \$4 = counter + (* src = "force_end.py:60" *) 1'h1;
always @(posedge clk) fend <= \$next\fend ;
always @(posedge clk) counter <= \$next\counter ;
always @(posedge clk) fsm_state <= \$next\fsm_state ;
always @* begin
\$next\fsm_state = fsm_state;
casez (fsm_state)
2'h0:
casez (valid_in)
1'h1: \$next\fsm_state = 2'h1;
endcase
2'h1:
casez (\$1 )
1'h1: \$next\fsm_state = 2'h2;
endcase
endcase
casez (rst)
1'h1: \$next\fsm_state = 2'h0;
endcase
end
always @* begin
\$next\counter = counter;
casez (fsm_state)
2'h1: \$next\counter = \$3 [24:0];
endcase
casez (rst)
1'h1: \$next\counter = 25'h0000000;
endcase
end
always @* begin
\$next\fend = fend;
casez (fsm_state)
2'h2: \$next\fend = 1'h1;
endcase
casez (rst)
1'h1: \$next\fend = 1'h0;
endcase
end
assign \$3 = \$4 ;
endmodule
| 6.812464 |
module lj92_pipeline_fifo (
enc_in,
enc_in_ctr,
in_end,
latch_output,
rst,
clk,
valid_out,
enc_out,
enc_out_ctr,
out_end,
close_full,
valid_in
);
wire \$1 ;
(* src = "lj92_pipeline_fifo.py:67" *)
reg \$next\close_full ;
(* src = "lj92_pipeline_fifo.py:60" *)
reg [55:0] \$next\enc_out ;
(* src = "lj92_pipeline_fifo.py:61" *)
reg [5:0] \$next\enc_out_ctr ;
(* src = "nmigen/lib/fifo.py:65" *)
reg [62:0] \$next\fifo_din ;
(* src = "nmigen/lib/fifo.py:71" *)
reg \$next\fifo_re ;
(* src = "nmigen/lib/fifo.py:67" *)
reg \$next\fifo_we ;
(* src = "lj92_pipeline_fifo.py:62" *)
reg \$next\out_end ;
(* src = "lj92_pipeline_fifo.py:63" *)
reg \$next\valid_out ;
(* src = "nmigen/hdl/mem.py:160" *)
input clk;
(* init = 1'h0 *) (* src = "lj92_pipeline_fifo.py:67" *)
output close_full;
reg close_full = 1'h0;
(* src = "lj92_pipeline_fifo.py:54" *)
input [55:0] enc_in;
(* src = "lj92_pipeline_fifo.py:55" *)
input [5:0] enc_in_ctr;
(* src = "lj92_pipeline_fifo.py:60" *)
output [55:0] enc_out;
(* src = "lj92_pipeline_fifo.py:61" *)
output [5:0] enc_out_ctr;
(* src = "nmigen/lib/fifo.py:65" *)
wire [62:0] fifo_din;
(* src = "nmigen/lib/fifo.py:69" *)
wire [62:0] fifo_dout;
(* src = "nmigen/lib/fifo.py:238" *)
wire [9:0] fifo_level;
(* src = "nmigen/lib/fifo.py:71" *)
wire fifo_re;
(* src = "nmigen/lib/fifo.py:70" *)
wire fifo_readable;
(* src = "nmigen/lib/fifo.py:67" *)
wire fifo_we;
(* src = "lj92_pipeline_fifo.py:56" *)
input in_end;
(* src = "lj92_pipeline_fifo.py:59" *)
input latch_output;
(* src = "lj92_pipeline_fifo.py:62" *)
output out_end;
(* src = "clk_domains.py:5" *)
input rst;
(* src = "lj92_pipeline_fifo.py:57" *)
input valid_in;
(* src = "lj92_pipeline_fifo.py:63" *)
output valid_out;
assign \$1 = fifo_level >= (* src = "lj92_pipeline_fifo.py:99" *) 9'h1f6;
always @(posedge clk) close_full <= \$next\close_full ;
fifo fifo (
.clk(clk),
.din(fifo_din),
.dout(fifo_dout),
.level(fifo_level),
.re(fifo_re),
.readable(fifo_readable),
.rst(rst),
.we(fifo_we)
);
always @* begin
\$next\fifo_we = 1'h0;
\$next\fifo_we = valid_in;
end
always @* begin
\$next\fifo_din = 63'h0000000000000000;
\$next\fifo_din = {in_end, enc_in_ctr, enc_in};
end
always @* begin
\$next\valid_out = 1'h0;
\$next\valid_out = fifo_readable;
end
always @* begin
\$next\enc_out = 56'h00000000000000;
\$next\enc_out = fifo_dout[55:0];
end
always @* begin
\$next\enc_out_ctr = 6'h00;
\$next\enc_out_ctr = fifo_dout[61:56];
end
always @* begin
\$next\out_end = 1'h0;
\$next\out_end = fifo_dout[62];
end
always @* begin
\$next\fifo_re = 1'h0;
\$next\fifo_re = latch_output;
end
always @* begin
\$next\close_full = close_full;
\$next\close_full = \$1 ;
casez (rst)
1'h1: \$next\close_full = 1'h0;
endcase
end
assign fifo_re = \$next\fifo_re ;
assign out_end = \$next\out_end ;
assign enc_out_ctr = \$next\enc_out_ctr ;
assign enc_out = \$next\enc_out ;
assign valid_out = \$next\valid_out ;
assign fifo_din = \$next\fifo_din ;
assign fifo_we = \$next\fifo_we ;
endmodule
| 6.698238 |
module register_file (
full_clk,
width,
height,
allowed_cycles,
full_rst
);
(* src = "register_file.py:38" *)
reg [23:0] \$next\allowed_cycles ;
(* src = "register_file.py:52" *)
reg [23:0] \$next\allowed_cycles_reg ;
(* src = "register_file.py:36" *)
reg [15:0] \$next\height ;
(* src = "register_file.py:51" *)
reg [15:0] \$next\height_reg ;
(* src = "register_file.py:37" *)
reg [15:0] \$next\width ;
(* src = "register_file.py:50" *)
reg [15:0] \$next\width_reg ;
(* src = "register_file.py:38" *)
output [23:0] allowed_cycles;
(* init = 24'h000000 *) (* src = "register_file.py:52" *)
reg [23:0] allowed_cycles_reg = 24'h000000;
(* src = "clk_domains.py:4" *)
input full_clk;
(* src = "clk_domains.py:4" *)
input full_rst;
(* src = "register_file.py:36" *)
output [15:0] height;
(* init = 16'h0000 *) (* src = "register_file.py:51" *)
reg [15:0] height_reg = 16'h0000;
(* src = "register_file.py:37" *)
output [15:0] width;
(* init = 16'h0000 *) (* src = "register_file.py:50" *)
reg [15:0] width_reg = 16'h0000;
always @(posedge full_clk) allowed_cycles_reg <= \$next\allowed_cycles_reg ;
always @(posedge full_clk) height_reg <= \$next\height_reg ;
always @(posedge full_clk) width_reg <= \$next\width_reg ;
always @* begin
\$next\width_reg = width_reg;
\$next\width_reg = 16'h1000;
casez (full_rst)
1'h1: \$next\width_reg = 16'h0000;
endcase
end
always @* begin
\$next\height_reg = height_reg;
\$next\height_reg = 16'h0c00;
casez (full_rst)
1'h1: \$next\height_reg = 16'h0000;
endcase
end
always @* begin
\$next\allowed_cycles_reg = allowed_cycles_reg;
\$next\allowed_cycles_reg = 24'h65b710;
casez (full_rst)
1'h1: \$next\allowed_cycles_reg = 24'h000000;
endcase
end
always @* begin
\$next\width = 16'h0000;
\$next\width = width_reg;
end
always @* begin
\$next\height = 16'h0000;
\$next\height = height_reg;
end
always @* begin
\$next\allowed_cycles = 24'h000000;
\$next\allowed_cycles = allowed_cycles_reg;
end
assign allowed_cycles = \$next\allowed_cycles ;
assign height = \$next\height ;
assign width = \$next\width ;
endmodule
| 6.605344 |
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