code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BCU (
input wire zf,
input wire cf,
input wire sf,
input wire vf,
input [`IR_funct3] funct3,
input branchSignal,
output PCSrc
);
reg result;
always @(*) begin
result = 1'b0;
case (funct3)
`BR_BEQ: if (zf) result = 1'b1;
`BR_BNE: if (!zf) result = 1'b1;
`BR_BLT: if (sf != vf) result = 1'b1;
`BR_BGE: if (sf == vf) result = 1'b1;
`BR_BLTU: if (!cf) result = 1'b1;
`BR_BGEU: if (cf) result = 1'b1;
default: result = 1'b0;
endcase
end
assign PCSrc = result & branchSignal;
endmodule
| 7.108586 |
module - all inputs and outputs must be "real" - that is,
// they need to come from somewhere, like the FPGA physical connections.
// Part of the job of the XDC file is to lay out what connections go to
// what names, and what sort of signal needs to be driven or accepted.
module BCUNXSMinerTop(
input wire SYSCLK1_300_N,
input wire SYSCLK1_300_P,
input wire UART_TXD_IN,
output wire UART_RXD_OUT
);
wire clk; // Main clock signal. See below.
wire NonceFound; // Goes high when a new nonce has been found
wire [63:0] NonceOut; // Nonce outputted by hash core
// Structure/size of data:
// 10 x 64-bit words for remainder of block header (input to FirstSkeinRound as InState, 640 bits.)
// 17 x 64-bit words for midstate (input to FirstSkeinRound as InKey, 1088 bits.)
// 1088 + 640 = 1728 bits = 216 bytes
// (17 + 10) * 8 * 8 = 1728 bits = 216 bytes
wire [1727:0] InData; // Signals for our incoming data;
wire ReceivedFullInput; // Signal to indicate 216 whole bytes have been read.
reg OutputReady = 1'b0; // Signal to indicate we have our output data ready.
reg DataValid = 1'b0; // Someplace to store a 1 if we ever get valid input.
reg nHashRst = 1'b0; // Active-low reset signal to cause work reload.
reg [1727:0] InDataReg; // Someplace to store the data we get.
reg [63:0] OutDataReg; // Someplace to hold data for output.
// Convert differential 600Mhz clock into single-ended 600Mhz clock we can use...
//MMCM650 MainMMCM(.clk_out1(clk), .clk_in1_p(SYSCLK0_200_P), .clk_in1_n(SYSCLK0_200_N));
IBUFDS MufIBUF(.O(clk), .I(SYSCLK1_300_P), .IB(SYSCLK1_300_N));
// Here, we instantiate the RX and TX modules used for communications logic.
USBSerial_RX InputReader(.clk(clk), .UART_TXD_IN(UART_TXD_IN), .OutData(InData), .ReadCompletedSig(ReceivedFullInput));
USBSerial_TX OutputTransmitter(.clk(clk), .NewValidInput(OutputReady), .OutData(OutDataReg), .UART_RXD_OUT(UART_RXD_OUT));
//USBSerial SerialTransciever(.clk(clk), .RX(UART_TXD_IN), .TX(UART_RXD_OUT), .BlkHdr(InData), .BlkHdrValid(ReceivedFullInput), .OutData(OutDataReg), .OutDataValid(OutputReady));
always @(posedge clk)
begin
// This goes high, store the work, and note that we received
// valid data to work on.
if(ReceivedFullInput)
begin
InDataReg <= InData;
// Unlike most of our signals, this one remains high
// once we've gotten valid data at least once.
// Technically, it should be pulled low on work exhaustion,
// but we're never gonna exhaust 2^64 possibles...
DataValid <= 1'b1;
end
// Reset the hash core so it will pick up the new work
nHashRst <= ~ReceivedFullInput;
OutDataReg <= NonceOut;
OutputReady <= NonceFound;
end
NexusHashTransform NexusMinerCore(NonceOut, NonceFound, clk, nHashRst, InDataReg, 64'b0);
endmodule
| 6.524326 |
module bc_counter #(
parameter BITS = 12
) (
input wire CLK,
input wire RST,
output wire [BITS-1:0] BC
);
reg [BITS-1:0] BC_reg;
always @(posedge CLK) begin
if (RST) begin
BC_reg <= 0;
end else begin
BC_reg <= BC_reg + 1'b1;
end
end
assign BC = BC_reg;
endmodule
| 8.458587 |
module clk_div (
input clk,
output sclk
);
integer MAX_COUNT = 2200;
integer div_cnt = 0;
reg tmp_clk = 0;
always @(posedge clk) begin
if (div_cnt == MAX_COUNT) begin
tmp_clk = ~tmp_clk;
div_cnt = 0;
end else div_cnt = div_cnt + 1;
end
assign sclk = tmp_clk;
endmodule
| 7.520262 |
module clk_div2 (
input clk,
output disp_clk
);
integer MAX_COUNT = 10000000;
integer div_cnt = 0;
reg tmp_clk = 0;
always @(posedge clk) begin
if (div_cnt == MAX_COUNT) begin
tmp_clk = ~tmp_clk;
div_cnt = 0;
end else div_cnt = div_cnt + 1;
end
assign disp_clk = tmp_clk;
endmodule
| 6.65618 |
module bc_fifo16x8(clk, wr, wa, ra, di, do);
input clk;
input wr;
input [3:0] wa, ra;
input [7:0] di;
output [7:0] do;
reg [7:0] mem [15:0];
always @(posedge clk) begin
if (wr)
mem[wa] <= di;
end
assign do = mem[ra];
endmodule
| 6.669506 |
module bc_mac_b4 (
input clk,
input rst_n,
input [3:0] act0,
input [3:0] act1,
input [3:0] act2,
input [3:0] act3,
input [3:0] act4,
input [3:0] act5,
input [3:0] act6,
input [3:0] act7,
input [7:0] weight,
input [5:0] yi,
input sft_en,
input sft_in,
input trun_in,
input [3:0] gin,
output [5:0] yo,
output [3:0] gout,
output reg [3:0] sumout
//, output reg [3:0] trunout
);
// PPG, AND gate
wire [7:0] ppg0, ppg1, ppg2, ppg3;
assign ppg0 = {
weight[0] & act0[0],
weight[1] & act1[0],
weight[2] & act2[0],
weight[3] & act3[0],
weight[4] & act4[0],
weight[5] & act5[0],
weight[6] & act6[0],
weight[7] & act7[0]
};
assign ppg1 = {
weight[0] & act0[1],
weight[1] & act1[1],
weight[2] & act2[1],
weight[3] & act3[1],
weight[4] & act4[1],
weight[5] & act5[1],
weight[6] & act6[1],
weight[7] & act7[1]
};
assign ppg2 = {
weight[0] & act0[2],
weight[1] & act1[2],
weight[2] & act2[2],
weight[3] & act3[2],
weight[4] & act4[2],
weight[5] & act5[2],
weight[6] & act6[2],
weight[7] & act7[2]
};
assign ppg3 = {
weight[0] & act0[3],
weight[1] & act1[3],
weight[2] & act2[3],
weight[3] & act3[3],
weight[4] & act4[3],
weight[5] & act5[3],
weight[6] & act6[3],
weight[7] & act7[3]
};
// PPA, bit4 8-2 compressor
wire [1:0] I0_out, I1_out, I2_out, I3_out;
wire [4:0] I0_yo, I1_yo, I2_yo;
cprs_8_2 I0 (
.in (ppg0),
.yi (yi[4:0]),
.out(I0_out),
.yo (I0_yo)
);
cprs_8_2 I1 (
.in (ppg1),
.yi (I0_yo),
.out(I1_out),
.yo (I1_yo)
);
cprs_8_2 I2 (
.in (ppg2),
.yi (I1_yo),
.out(I2_out),
.yo (I2_yo)
);
cprs_8_2 I3 (
.in (ppg3),
.yi (I2_yo),
.out(I3_out),
.yo (yo[4:0])
);
// save compressed data, 8-2 results
reg [1:0] I0_out_r1, I1_out_r1, I2_out_r1, I3_out_r1;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
I0_out_r1 <= 2'b00;
I1_out_r1 <= 2'b00;
I2_out_r1 <= 2'b00;
I3_out_r1 <= 2'b00;
end else begin
I0_out_r1 <= I0_out;
I1_out_r1 <= I1_out;
I2_out_r1 <= I2_out;
I3_out_r1 <= I3_out;
end
end
// segmented final addition with G,G4,G8,G12
// three inputs: cin,I0_out_r1[0],sum_sft
// output reg
wire [3:0] sft_out;
assign sft_out = (sft_en == 1'b1) ? {sft_in, sumout[3:1]} : sumout[3:0];
wire [1:0] I4_out, I5_out, I6_out, I7_out;
cprs_3_2 I4 (
.in ({yi[5], I0_out_r1[0], sft_out[0]}),
.out(I4_out)
);
cprs_3_2 I5 (
.in ({I0_out_r1[1], I1_out_r1[0], sft_out[1]}),
.out(I5_out)
);
cprs_3_2 I6 (
.in ({I1_out_r1[1], I2_out_r1[0], sft_out[2]}),
.out(I6_out)
);
cprs_3_2 I7 (
.in ({I2_out_r1[1], I3_out_r1[0], sft_out[3]}),
.out(I7_out)
);
assign yo[5] = I3_out_r1[1];
assign yo[6] = I7_out[1];
wire [3:0] sum, in1, in2;
assign in1 = {I7_out[0], I6_out[0], I5_out[0], I4_out[0]};
assign in2 = {I6_out[1], I5_out[1], I4_out[1], yi[6]};
// group carry-out
group_pg I8 (
.in1 (in1),
.in2 (in2),
.gin (gin),
.gout(gout)
);
assign cin = gin[0]; // cin should can be any bit from gin
//assign {cout,sum} = in1 + in2 + cin;
//DW01_add #(4) I9 (.A(in1), .B(in2), .CI(cin), .SUM(sum), .CO(cout));
adder4 I9 (
.in1 (in1),
.in2 (in2),
.cin (cin),
.sum (sum),
.cout(cout)
);
// sum register
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
sumout <= 4'b0;
end else begin
sumout <= sum;
end
end
// // truncted register
// always @ (posedge clk or negedge rst_n) begin
// if (rst_n == 1'b0) begin
// trunout <= 4'b0;
// end else if(sft_en == 1'b1) begin
// trunout <= {trun_in,trunout[3:1]};
// end
// end
endmodule
| 6.82408 |
module adder4 (
input [3:0] in1,
input [3:0] in2,
input cin,
output [3:0] sum,
output cout
);
DW01_add #(4) I0 (
.A (in1),
.B (in2),
.CI (cin),
.SUM(sum),
.CO (cout)
);
endmodule
| 6.582965 |
module cprs_8_2 (
input [7:0] in,
input [4:0] yi,
output [1:0] out,
output [4:0] yo
);
wire I0_out, I1_out, I2_out, I3_out, I4_out;
wire I0_err, I1_err, I2_err, I3_err, I4_err;
cprs_4_2 I0 (
.in (in[7:4]),
.out({yo[0], I0_out}),
.err(I0_err)
);
cprs_4_2 I1 (
.in (in[3:0]),
.out({yo[1], I1_out}),
.err(I1_err)
);
cprs_3_2 I2 (
.in ({{I0_out, I0_err, yi[0]}}),
.out({yo[2], I2_out})
);
cprs_3_2 I3 (
.in ({{I1_out, I1_err, yi[1]}}),
.out({yo[3], I3_out})
);
cprs_4_2 I4 (
.in ({I2_out, I3_out, yi[3:2]}),
.out({yo[4], I4_out}),
.err(I4_err)
);
cprs_3_2 I5 (
.in ({I4_out, I4_err, yi[4]}),
.out(out[1:0])
);
endmodule
| 6.871141 |
module cprs_3_2 (
in,
out
);
input [2:0] in;
output [1:0] out;
wire in0_xor_in1, in0_and_in1;
assign in0_xor_in1 = in[0] ^ in[1];
assign in0_and_in1 = in[0] & in[1];
assign out[1] = in0_xor_in1 & in[2] | in0_and_in1;
assign out[0] = in0_xor_in1 ^ in[2];
endmodule
| 6.841716 |
module cprs_4_2 (
in,
out,
err
);
input [3:0] in;
output [1:0] out;
output err;
wire in0_and_in1, in0_or_in1, in0_xor_in1;
assign in0_and_in1 = in[0] & in[1];
assign in0_or_in1 = in[0] | in[1];
assign in0_xor_in1 = in[0] ^ in[1];
wire in2_or_in3, in2_xor_in3;
assign in2_or_in3 = in[2] | in[3];
assign in2_xor_in3 = in[2] ^ in[3];
assign out[0] = in0_xor_in1 ^ in2_or_in3;
assign out[1] = (in0_or_in1 & in2_or_in3) | in0_and_in1;
assign err = in[2] & in[3];
endmodule
| 7.077964 |
module group_pg (
input [3:0] in1,
input [3:0] in2,
input [3:0] gin,
output [3:0] gout
);
wire [3:0] carry_g, carry_p, carry;
assign carry_g = {in1[3] & in2[3], in1[2] & in2[2], in1[1] & in2[1], in1[0] & in2[0]};
assign carry_p = {in1[3] | in2[3], in1[2] | in2[2], in1[1] | in2[1], in1[0] | in2[0]};
assign carry[0] = carry_g[0];
assign carry[1] = carry_g[1] + carry_p[1] * carry[0];
assign carry[2] = carry_g[2] + carry_p[2] * carry[1];
assign carry[3] = carry_g[3] + carry_p[3] * carry[2];
wire prop;
assign prop = carry_p[0] & carry_p[1] & carry_p[2] & carry_p[3];
assign gout[0] = carry[3];
assign gout[1] = gout[0] + prop * gin[0];
assign gout[2] = gout[0] + prop * gin[1];
assign gout[3] = gout[0] + prop * gin[2];
endmodule
| 6.527222 |
module bc_mac_b4_trun (
input clk,
input rst_n,
input [3:0] act0,
input [3:0] act1,
input [3:0] act2,
input [3:0] act3,
input [3:0] act4,
input [3:0] act5,
input [3:0] act6,
input [3:0] act7,
input [7:0] weight,
input [5:0] yi,
input sft_en,
input sft_in,
input trun_in,
input [3:0] gin,
output [5:0] yo,
output [3:0] gout,
output reg [3:0] sumout,
output reg [3:0] trunout
);
// PPG, AND gate
wire [7:0] ppg0, ppg1, ppg2, ppg3;
assign ppg0 = {
weight[0] & act0[0],
weight[1] & act1[0],
weight[2] & act2[0],
weight[3] & act3[0],
weight[4] & act4[0],
weight[5] & act5[0],
weight[6] & act6[0],
weight[7] & act7[0]
};
assign ppg1 = {
weight[0] & act0[1],
weight[1] & act1[1],
weight[2] & act2[1],
weight[3] & act3[1],
weight[4] & act4[1],
weight[5] & act5[1],
weight[6] & act6[1],
weight[7] & act7[1]
};
assign ppg2 = {
weight[0] & act0[2],
weight[1] & act1[2],
weight[2] & act2[2],
weight[3] & act3[2],
weight[4] & act4[2],
weight[5] & act5[2],
weight[6] & act6[2],
weight[7] & act7[2]
};
assign ppg3 = {
weight[0] & act0[3],
weight[1] & act1[3],
weight[2] & act2[3],
weight[3] & act3[3],
weight[4] & act4[3],
weight[5] & act5[3],
weight[6] & act6[3],
weight[7] & act7[3]
};
// PPA, bit4 8-2 compressor
wire [1:0] I0_out, I1_out, I2_out, I3_out;
wire [4:0] I0_yo, I1_yo, I2_yo;
cprs_8_2 I0 (
.in (ppg0),
.yi (yi[4:0]),
.out(I0_out),
.yo (I0_yo)
);
cprs_8_2 I1 (
.in (ppg1),
.yi (I0_yo),
.out(I1_out),
.yo (I1_yo)
);
cprs_8_2 I2 (
.in (ppg2),
.yi (I1_yo),
.out(I2_out),
.yo (I2_yo)
);
cprs_8_2 I3 (
.in (ppg3),
.yi (I2_yo),
.out(I3_out),
.yo (yo[4:0])
);
// save compressed data, 8-2 results
reg [1:0] I0_out_r1, I1_out_r1, I2_out_r1, I3_out_r1;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
I0_out_r1 <= 2'b00;
I1_out_r1 <= 2'b00;
I2_out_r1 <= 2'b00;
I3_out_r1 <= 2'b00;
end else begin
I0_out_r1 <= I0_out;
I1_out_r1 <= I1_out;
I2_out_r1 <= I2_out;
I3_out_r1 <= I3_out;
end
end
// segmented final addition with G,G4,G8,G12
// three inputs: cin,I0_out_r1[0],sum_sft
// output reg
wire [3:0] sft_out;
assign sft_out = (sft_en == 1'b1) ? {sft_in, sumout[3:1]} : sumout[3:0];
wire [1:0] I4_out, I5_out, I6_out, I7_out;
cprs_3_2 I4 (
.in ({yi[5], I0_out_r1[0], sft_out[0]}),
.out(I4_out)
);
cprs_3_2 I5 (
.in ({I0_out_r1[1], I1_out_r1[0], sft_out[1]}),
.out(I5_out)
);
cprs_3_2 I6 (
.in ({I1_out_r1[1], I2_out_r1[0], sft_out[2]}),
.out(I6_out)
);
cprs_3_2 I7 (
.in ({I2_out_r1[1], I3_out_r1[0], sft_out[3]}),
.out(I7_out)
);
assign yo[5] = I3_out_r1[1];
assign yo[6] = I7_out[1];
wire [3:0] sum, in1, in2;
assign in1 = {I7_out[0], I6_out[0], I5_out[0], I4_out[0]};
assign in2 = {I6_out[1], I5_out[1], I4_out[1], yi[6]};
// group carry-out
group_pg I8 (
.in1 (in1),
.in2 (in2),
.gin (gin),
.gout(gout)
);
assign cin = gin[0]; // cin should can be any bit from gin
//assign {cout,sum} = in1 + in2 + cin;
//DW01_add #(4) I9 (.A(in1), .B(in2), .CI(cin), .SUM(sum), .CO(cout));
adder4 I9 (
.in1 (in1),
.in2 (in2),
.cin (cin),
.sum (sum),
.cout(cout)
);
// sum register
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
sumout <= 4'b0;
end else begin
sumout <= sum;
end
end
// truncted register
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
trunout <= 4'b0;
end else if (sft_en == 1'b1) begin
trunout <= {trun_in, trunout[3:1]};
end
end
endmodule
| 7.204343 |
module adder4 (
input [3:0] in1,
input [3:0] in2,
input cin,
output [3:0] sum,
output cout
);
DW01_add #(4) I0 (
.A (in1),
.B (in2),
.CI (cin),
.SUM(sum),
.CO (cout)
);
endmodule
| 6.582965 |
module cprs_8_2 (
input [7:0] in,
input [4:0] yi,
output [1:0] out,
output [4:0] yo
);
wire I0_out, I1_out, I2_out, I3_out, I4_out;
wire I0_err, I1_err, I2_err, I3_err, I4_err;
cprs_4_2 I0 (
.in (in[7:4]),
.out({yo[0], I0_out}),
.err(I0_err)
);
cprs_4_2 I1 (
.in (in[3:0]),
.out({yo[1], I1_out}),
.err(I1_err)
);
cprs_3_2 I2 (
.in ({{I0_out, I0_err, yi[0]}}),
.out({yo[2], I2_out})
);
cprs_3_2 I3 (
.in ({{I1_out, I1_err, yi[1]}}),
.out({yo[3], I3_out})
);
cprs_4_2 I4 (
.in ({I2_out, I3_out, yi[3:2]}),
.out({yo[4], I4_out}),
.err(I4_err)
);
cprs_3_2 I5 (
.in ({I4_out, I4_err, yi[4]}),
.out(out[1:0])
);
endmodule
| 6.871141 |
module cprs_3_2 (
in,
out
);
input [2:0] in;
output [1:0] out;
wire in0_xor_in1, in0_and_in1;
assign in0_xor_in1 = in[0] ^ in[1];
assign in0_and_in1 = in[0] & in[1];
assign out[1] = in0_xor_in1 & in[2] | in0_and_in1;
assign out[0] = in0_xor_in1 ^ in[2];
endmodule
| 6.841716 |
module cprs_4_2 (
in,
out,
err
);
input [3:0] in;
output [1:0] out;
output err;
wire in0_and_in1, in0_or_in1, in0_xor_in1;
assign in0_and_in1 = in[0] & in[1];
assign in0_or_in1 = in[0] | in[1];
assign in0_xor_in1 = in[0] ^ in[1];
wire in2_or_in3, in2_xor_in3;
assign in2_or_in3 = in[2] | in[3];
assign in2_xor_in3 = in[2] ^ in[3];
assign out[0] = in0_xor_in1 ^ in2_or_in3;
assign out[1] = (in0_or_in1 & in2_or_in3) | in0_and_in1;
assign err = in[2] & in[3];
endmodule
| 7.077964 |
module group_pg (
input [3:0] in1,
input [3:0] in2,
input [3:0] gin,
output [3:0] gout
);
wire [3:0] carry_g, carry_p, carry;
assign carry_g = {in1[3] & in2[3], in1[2] & in2[2], in1[1] & in2[1], in1[0] & in2[0]};
assign carry_p = {in1[3] | in2[3], in1[2] | in2[2], in1[1] | in2[1], in1[0] | in2[0]};
assign carry[0] = carry_g[0];
assign carry[1] = carry_g[1] + carry_p[1] * carry[0];
assign carry[2] = carry_g[2] + carry_p[2] * carry[1];
assign carry[3] = carry_g[3] + carry_p[3] * carry[2];
wire prop;
assign prop = carry_p[0] & carry_p[1] & carry_p[2] & carry_p[3];
assign gout[0] = carry[3];
assign gout[1] = gout[0] + prop * gin[0];
assign gout[2] = gout[0] + prop * gin[1];
assign gout[3] = gout[0] + prop * gin[2];
endmodule
| 6.527222 |
module bc_uart(reset, clk, ce, cs, rd, wr, a, di, do, irq,
cts, rts, sin, sout);
input reset;
input clk; // eg 100.7MHz
input ce; // eg 25.175MHz enable
input cs; // circuit select
input rd; // 1 = read
input wr; // 1 = write
input [2:0] a; // register address
input [7:0] di; // data input bus
output [7:0] do; // data output bus
reg [7:0] do;
output irq; // interrupt request
input cts; // clear to send (flow control)
output rts; // request to send (flow control)
reg rts;
input sin; // serial data in
output sout; // serial data out
reg [15:0] c; // current count
reg pcmsb; // previous value of count msb
reg [15:0] ck_mul; // baud rate clock multiplier
wire data_present;
wire rx_full, tx_empty, tx_full;
wire [7:0] dout;
wire baud16 = c[15] & ~pcmsb; // edge detector (active one cycle only!)
reg cts1; // cts sampling
reg rx_full_ie; // interrupt enable flags
reg rx_present_ie;
reg tx_empty_ie;
wire clear = wr && a==3'd3 && ce && cs;
wire frame_err; // receiver char framing error
wire over_run; // receiver over run
assign irq = (rx_full & rx_full_ie) |
(data_present & rx_present_ie) |
(tx_empty & tx_empty_ie);
wire [7:0] rx_do;
bc_uart_rx uart_rx0(.reset(reset), .clk(clk), .baud16x_ce(baud16),
.rd(rd & cs & a[2:0]==3'b000 & ce), .clear(clear), .do(rx_do),
.sin(sin), .data_present(data_present), .full(rx_full),
.frame_err(frame_err), .over_run(over_run) );
bc_uart_tx uart_tx0(.reset(reset), .clk(clk),. baud16x_ce(baud16),
.wr(wr & cs & a[2:0]==3'b000 & ce), .clear(clear), .di(di),
.sout(sout), .full(tx_full), .empty(tx_empty) );
// mux the reg outputs
always @(a or rx_do or irq or data_present or rx_full or tx_full
or tx_empty or rx_present_ie or rx_full_ie or tx_empty_ie
or cts1 or rts or ck_mul or over_run or frame_err) begin
case(a)
3'd0: do <= rx_do;
3'd1: do <= {irq, data_present, rx_full, tx_empty, tx_full,2'b0,cts1};
3'd2: do <= {1'b0, rx_present_ie, rx_full_ie, tx_empty_ie, 2'b0, rts, 1'b0};
3'd3: do <= {over_run, frame_err, 6'b0};
3'd4: do <= ck_mul[15:0];
3'd5: do <= ck_mul[7:0];
3'd6,3'd7: do <= 8'b0;
endcase
end
// Note: baud clock should pulse high for only a single
// cycle!
always @(posedge clk) begin
if (reset) begin
c <= 16'd0;
pcmsb <= 1'b0;
end
else begin
c <= c + ck_mul;
// for detecting an edge on the msb
pcmsb <= c[15];
cts1 <= cts;
end
end
// register updates
always @(posedge clk) begin
if (reset) begin
rts <= 1'b0;
rx_present_ie <= 1'b0;
rx_full_ie <= 1'b0;
tx_empty_ie <= 1'b0;
// 19200 baud=800 with 25 MHZ clock
// 19200 baud=1007 with 20 MHZ clock
ck_mul <= 16'd1007;
end
else begin
if (ce & wr & cs) begin
case (a)
3'd2: begin
rx_present_ie <= di[6];
rx_full_ie <= di[5];
tx_empty_ie <= di[4];
rts <= di[1];
end
3'd4: ck_mul[15:8] <= di;
3'd5: ck_mul[7:0] <= di;
default:
;
endcase
end
end
end
endmodule
| 6.871016 |
module bc_uart_tx (
reset,
clk,
baud16x_ce,
wr,
clear,
di,
sout,
full,
empty
);
input reset;
input clk;
input baud16x_ce; // baud rate clock enable
input wr; // write transmitter
input clear; // clear transmitter
input [7:0] di; // fifo data in
output sout; // external serial output
output full; // fifo is full
output empty; // fifo is empty
reg [9:0] tx_data; // transmit data working reg (raw)
assign sout = tx_data[0];
reg [1:0] state; // state machine state
reg [3:0] wa; // fifo write address
reg [3:0] ra; // fifo read address
reg [3:0] pra; // previous fifo read address
assign empty = wa == ra;
assign full = wa == pra;
wire [7:0] fdo; // fifo data output
reg [3:0] cnt; // baud clock counter
reg [3:0] bit_cnt; // bit counter
bc_fifo16x8 fifo0 (
.clk(clk),
.wr (wr),
.wa (wa),
.ra (ra),
.di (di),
.do (fdo)
);
always @(posedge clk) begin
if (reset) begin
state <= `IDLE;
cnt <= 4'd15;
bit_cnt <= 4'd0;
ra <= 4'd0;
wa <= 4'd0;
pra <= 4'd15;
end else begin
// On a write, advance the fifo write address. If the
// fifo is full we will overwrite chars.
if (wr) wa <= wa + 1;
if (clear) begin
state <= `IDLE;
cnt <= 4'd15;
bit_cnt <= 4'd0;
ra <= 4'd0;
wa <= 4'd0;
pra <= 4'd15;
end
if (baud16x_ce) begin
cnt <= cnt + 1;
case (state)
// If we're in the idle state then look and see if
// there are any characters in the fifo to be
// transmitted.
`IDLE: begin
bit_cnt <= 4'd0;
cnt <= 4'd0;
if (!empty) begin
tx_data <= {1'b1, fdo, 1'b0};
ra <= ra + 1;
pra <= ra;
state <= `CNT;
end
end
// We simply sit in the count state until we've
// counted enough baud clocks to be ready to shift.
`CNT: begin
if (cnt == 4'd15) state <= `SHIFT;
end
// Shift the data out. LSB first.
`SHIFT: begin
tx_data <= {1'b1, tx_data[9:1]};
bit_cnt <= bit_cnt + 1;
if (bit_cnt == 4'd9) state <= `IDLE;
else state <= `CNT;
end
default: state <= `IDLE;
endcase
end
end
end
endmodule
| 7.825002 |
module BD3 (
input INPT,
output OUTPT
);
assign #5 OUTPT = INPT;
endmodule
| 7.247055 |
module implements a complete brushed DC motor channel with 16 bit quadrature tach counter,
// tach filtering, tach phase inversion, 8 bit pwm with current limit, and pwm output polarity selection.
module bdcmotorchannel(
// Tach counter low byte
output [7:0] countl,
// Tach counter high byte
output [7:0] counth,
// Complmentary pwm signals out
output [1:0] pwmout,
// 4 bit pwm signals out
output [3:0] pwmout4,
// System clock in
input clk,
// Clock enable for tach filter shift register
input filterce,
// Freeze tach counter ( used during reads)
input freeze,
// Invert tach counter phase
input invphase,
// PWM count enable (used to control PWM frequency)
input pwmcntce,
// Load a PWM value on the wrtdata bus into the PWM logic
input pwmldce,
// Invert the PWM outputs
input invertpwm,
// Enable the PWM outputs
input enablepwm,
// Run or send the brake signal to the pwm outputs
input run,
// Force early termination of the PWM cycle
input currentlimit,
// Quadrature tach inputs
input [1:0] tach,
// Write data bus
input [7:0] wrtdata);
tachcounter tc(
.clk(clk),
.tach(tach),
.filterce(filterce),
.freeze(freeze),
.invphase(invphase),
.countl(countl),
.counth(counth));
pwm8 pwm(
.clk(clk),
.pwmcntce(pwmcntce),
.pwmldce(pwmldce),
.invertpwm(invertpwm),
.enablepwm(enablepwm),
.run(run),
.currentlimit(currentlimit),
.wrtdata(wrtdata),
.pwmout(pwmout),
.pwmout4(pwmout4));
endmodule
| 6.904081 |
module bdiff_image (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [0:0] data;
input [16:0] rdaddress;
input rdclock;
input [16:0] wraddress;
input wrclock;
input wren;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire0;
wire [0:0] q = sub_wire0[0:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (wrclock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.clock1 (rdclock),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = "../rams/image.mono.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 76800,
altsyncram_component.numwords_b = 76800,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK1",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 17,
altsyncram_component.widthad_b = 17,
altsyncram_component.width_a = 1,
altsyncram_component.width_b = 1,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.763588 |
module bdiff_image (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [0:0] data;
input [16:0] rdaddress;
input rdclock;
input [16:0] wraddress;
input wrclock;
input wren;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.763588 |
module BDR (
input CLK,
input [31:0] DataIn,
output reg [31:0] DataOut
);
always @(negedge CLK) DataOut <= DataIn;
endmodule
| 7.304538 |
module accepts transmitter data from the GMII style
// interface from the attached client MAC. At 1 Gbps, this
// GMII transmitter data will be valid on evey clock cycle
// of the 125MHz reference clock; at 100Mbps, this data
// will be repeated for a ten clock period duration of the
// 125MHz reference clock; at 10Mbps, this data will be
// repeated for a hundred clock period duration of the
// 125MHz reference clock.
//
// This module will sample the input transmitter GMII data
// synchronously to the 125MHz reference clock. This
// sampled data can then be connected direcly to the input
// GMII- style interface of the Ethernet 1000BASE-X PCS/PMA
// or SGMII LogiCORE.
`timescale 1 ps/1 ps
module bd_929b_pcs_pma_0_tx_rate_adapt
(
input reset, // Synchronous reset.
input clk125m, // Reference 125MHz transmitter clock.
input sgmii_clk_en, // Clock enable pulse for the transmitter logic
input [7:0] gmii_txd_in, // Transmit data from client MAC.
input gmii_tx_en_in, // Transmit data valid signal from client MAC.
input gmii_tx_er_in, // Transmit error signal from client MAC.
output reg [7:0] gmii_txd_out, // Transmit data from client MAC.
output reg gmii_tx_en_out, // Transmit data valid signal from client MAC.
output reg gmii_tx_er_out // Transmit error signal from client MAC.
);
initial //initialize all outputs to 0 at startup
begin
gmii_txd_out = 8'b00000000;
gmii_tx_en_out = 1'b0;
gmii_tx_er_out = 1'b0;
end
// At 1Gbps speeds, sgmii_clk_en is permantly tied to logic 1
// and the input data will be sampled on every clock cycle. At 10Mbs
// and 100Mbps speeds, sgmii_clk_en will be at logic 1 only only one clock
// cycle in ten, or one clock cycle in a hundred, respectively.
// The sampled output GMII transmitter data is sent directly into the
// 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE synchronously to the
// 125MHz reference clock.
always @(posedge clk125m)
begin
if (reset == 1'b1) begin
gmii_txd_out <= 8'b0;
gmii_tx_en_out <= 1'b0;
gmii_tx_er_out <= 1'b0;
end
else if (sgmii_clk_en == 1'b1) begin
gmii_txd_out <= gmii_txd_in;
gmii_tx_en_out <= gmii_tx_en_in;
gmii_tx_er_out <= gmii_tx_er_in;
end
end
endmodule
| 8.196517 |
module bd_axis_custom_dct_wrapper (
aclk,
aresetn
);
input aclk;
input aresetn;
wire aclk;
wire aresetn;
bd_axis_custom_dct bd_axis_custom_dct_i (
.aclk(aclk),
.aresetn(aresetn)
);
endmodule
| 7.149217 |
module_ref:bootrom_wrapper:1.0
// IP Revision: 1
(* X_CORE_INFO = "bootrom_wrapper,Vivado 2019.2" *)
(* CHECK_LICENSE_TYPE = "BD_bootrom_wrapper_0_0,bootrom_wrapper,{}" *)
(* CORE_GENERATION_INFO = "BD_bootrom_wrapper_0_0,bootrom_wrapper,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=bootrom_wrapper,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED}" *)
(* IP_DEFINITION_SOURCE = "module_ref" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module BD_bootrom_wrapper_0_0 (
i_clk,
i_rst,
i_wb_adr,
i_wb_dat,
i_wb_sel,
i_wb_we,
i_wb_cyc,
i_wb_stb,
o_wb_ack,
o_wb_rdt
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_clk, ASSOCIATED_RESET i_rst, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN BD_clk_0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 i_clk CLK" *)
input wire i_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME i_rst, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 i_rst RST" *)
input wire i_rst;
input wire [31 : 0] i_wb_adr;
input wire [31 : 0] i_wb_dat;
input wire [3 : 0] i_wb_sel;
input wire i_wb_we;
input wire i_wb_cyc;
input wire i_wb_stb;
output wire o_wb_ack;
output wire [31 : 0] o_wb_rdt;
bootrom_wrapper inst (
.i_clk(i_clk),
.i_rst(i_rst),
.i_wb_adr(i_wb_adr),
.i_wb_dat(i_wb_dat),
.i_wb_sel(i_wb_sel),
.i_wb_we(i_wb_we),
.i_wb_cyc(i_wb_cyc),
.i_wb_stb(i_wb_stb),
.o_wb_ack(o_wb_ack),
.o_wb_rdt(o_wb_rdt)
);
endmodule
| 7.182352 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module bd_efdb_0_xpcs_0_ff_synchronizer #(
parameter C_NUM_SYNC_REGS = 3
)
(
input wire clk,
input wire data_in,
output reg data_out = 1'b0
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{1'b0}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk) begin
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
always @(posedge clk) begin
data_out = sync1_r[C_NUM_SYNC_REGS-1];
end
endmodule
| 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module bd_efdb_0_xpcs_0_ff_synchronizer_rst #(
parameter C_NUM_SYNC_REGS = 3,
parameter C_RVAL = 1'b0
)
(
input wire clk,
input wire rst,
input wire data_in,
output reg data_out = 1'b0
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{C_RVAL}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk or posedge rst) begin
if(rst)
sync1_r <= {C_NUM_SYNC_REGS{C_RVAL}};
else
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
always @(posedge clk)
begin
data_out <= sync1_r[C_NUM_SYNC_REGS-1];
end
endmodule
| 9.028271 |
module beacon_tb ();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable, bit_in;
wire bit_out, debit_out;
wire [6:0] state_out;
wire [6:0] destate_out;
//wire bit_out;
integer i, j;
reg [7:0] data[128:0];
reg [7:0] databyte;
// Initialize all variables
initial begin
$dumpfile("beacon_tb.vcd");
$dumpvars(0, clock, reset, enable, bit_in, bit_out, debit_out, state_out, destate_out);
$readmemh("beacon.hex", data);
$display("time\t clk reset enable in en de state destate");
$monitor("%g\t %b %b %b %b %b %b %b %b", $time, clock, reset, enable, bit_in,
bit_out, debit_out, state_out, destate_out);
clock = 1; // initial value of clock
reset = 0; // initial value of reset
enable = 0; // initial value of enable
bit_in = 1;
#5 reset = 1; // Assert the reset
#10 reset = 0; // De-assert the reset
#10 enable = 1; // Assert enable
for (i = 0; i < 128; i = i + 1) begin
databyte = data[i];
$display("Byte %g %h=%b", i, data[i], data[i]);
for (j = 0; j < 8; j = j + 1) begin
$display("Bit %g, %b", j, databyte[j]);
bit_in <= databyte[j];
#10;
end
end
#20000 enable = 0; // De-assert enable
#5 $finish; // Terminate simulation
end
// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
scrambler U_scrambler (
clock,
reset,
enable,
state_out,
bit_in,
bit_out
);
descrambler U_descrambler (
clock,
reset,
enable,
destate_out,
bit_out,
debit_out
);
endmodule
| 8.208077 |
module when building for development on the BeagleWire
// ICE40 development board. See beaglewire.pcf for information on what
// peripherals are used in this mode.
module top(
input clk_100M,
input reset,
output disp_clk,
output disp_hsync,
output disp_vsync,
output disp_de,
output [3:0] disp_b,
output [3:0] disp_g,
output [3:0] disp_r,
output int_vblank,
output [12:0] vram_addr,
inout [7:0] vram_data,
output [1:0] vram_bank,
output vram_clk,
output vram_cke,
output vram_we,
output vram_cs,
output vram_dqm,
output vram_ras,
output vram_cas,
inout [15:0] gpmc_ad,
input gpmc_advn,
input gpmc_csn1,
input gpmc_wein,
input gpmc_oen,
input gpmc_clk,
output [3:0] led
);
wire pixel_clk;
reg [31:0] count = 0;
assign led = { 0, 0, disp_de };
// Our video RAM (SDRAM) clock is just our 100MHz input clock, unmodified.
assign vram_clk = clk_100M;
// PLL to generate our pixel clock from the 100MHz clk_100M input clock
// icepll -i 100 -o 74.25
// Given input frequency: 100.000 MHz
// Requested output frequency: 74.250 MHz
// Achieved output frequency: 73.750 MHz
// F_OUT = (F_REF * (DIVF + 1)) / ((2^DIVQ) * (DIVR+1))
// = (100 * (58 + 1)) / ((2 ^ 3) * (9 + 1))
// = 73.75 MHz
SB_PLL40_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DIVR(4'b1001), // DIVR = 9
.DIVF(7'b0111010), // DIVF = 58
.DIVQ(3'b011), // DIVQ = 3
.FILTER_RANGE(3'b001), // FILTER_RANGE = 1
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
.FDA_FEEDBACK(4'b0000),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.FDA_RELATIVE(4'b0000),
.SHIFTREG_DIV_MODE(2'b00),
.PLLOUT_SELECT("GENCLK"),
.ENABLE_ICEGATE(1'b0)
) pixel_clock (
.REFERENCECLK(clk_100M),
.PLLOUTCORE(pixel_clk),
.EXTFEEDBACK(),
.RESETB(1'b1),
.BYPASS(1'b0),
.LATCHINPUTVALUE()
);
wire data_can_write;
wire [11:0] pixel_data;
wire pixel_data_ready;
testpattern pattern(
.clk(vram_clk),
.reset(reset),
.can_write(data_can_write),
.write_data(pixel_data),
.write_ready(pixel_data_ready)
);
main main(
.pixel_clk(pixel_clk),
.reset(reset),
.data_clk(vram_clk),
.data_can_write(data_can_write),
.data_in(pixel_data),
.data_write(pixel_data_ready),
.disp_clk(disp_clk),
.disp_hsync(disp_hsync),
.disp_vsync(disp_vsync),
.disp_de(disp_de),
.disp_b(disp_b),
.disp_g(disp_g),
.disp_r(disp_r),
);
endmodule
| 7.224168 |
module beam_tb;
reg clk;
reg reset;
integer cc;
reg trace;
`ifdef SIMULATE
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("beam.vcd");
$dumpvars(5, beam_tb);
end
trace = $test$plusargs("trace");
reset = 0;
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 1500; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
$display("PASS");
$finish(0);
end
`endif // `ifdef SIMULATE
// Beam pulse rate = 1300 MHz / 1400 = 928.57 kHz
// Clock rate = 1320 MHz / 14 = 94.286 MHz
// 13 beam pulses = 1320 clocks = 14 us
reg [11:0] phase_step = 12'd13;
reg [11:0] modulo = -12'd1320;
wire [11:0] pulse;
beam dut (
.clk(clk),
.ena(1'b1),
.reset(reset),
.pulse(pulse),
.phase_step(phase_step),
.modulo(modulo),
.phase_init(12'b0)
);
`ifdef SIMULATE
always @(posedge clk) begin
#1;
if (trace && (pulse != 0)) $display(cc, pulse);
end
// Keep from having to look at 3000 boring cycles at the beginning
// of a simulation
initial begin
#1;
dut.phase = -26;
end
`endif
endmodule
| 6.841491 |
module beatCounter (
clk,
startCounterEn,
reset,
process,
started,
pixelCounter
);
parameter INITCOUNT = 2'b00, COUNT0 = 2'b01, COUNT1 = 2'b10, //States for state machine.
MINPIXEL = 0,//MIN + MAX PIXEL start and stop position for pixel counter, counting through image,
MAXPIXEL = 255,
BEATS = 4,//pattern for process where BEATS = 4 and PAUSE = 1 this is 1111011110....
PAUSE = 1,
COUNTSTEP = 1,
SKIPROW = 0,
PIXELCOUNTERWIDTH = 20;//Corresponding to image address width
input clk, startCounterEn, reset;
output process, started;
output [PIXELCOUNTERWIDTH-1:0] pixelCounter;
wire [PIXELCOUNTERWIDTH-1:0] pixelCounter;
wire clk, startCounterEn, reset;
reg [PIXELCOUNTERWIDTH-1:0] pixelCount;
reg [1:0] countCase = INITCOUNT;
reg [7:0] pauseLenth;
reg [7:0] count; //method to define length of count to number of bits in BEATS
assign pixelCounter = pixelCount;
assign process = (countCase == COUNT0);
assign started = (countCase != INITCOUNT);
always @(posedge clk) begin
if (reset == 1) countCase = INITCOUNT;
case (countCase)
INITCOUNT: begin
pixelCount <= MINPIXEL;
if (startCounterEn) begin
pauseLenth <= 0;
count <= 0;
countCase <= COUNT0;
end
end
COUNT0: begin
if ((count != (BEATS - 1)) && (pixelCount != MAXPIXEL)) begin
count <= count + 1;
//pixelCount = pixelCount +1;
countCase <= COUNT0;
end else if (pixelCount == MAXPIXEL) begin
countCase <= INITCOUNT;
end else if (pauseLenth == PAUSE) begin
pauseLenth <= 0;
count <= 0;
end else begin
//pauseLenth = pauseLenth + 1;
countCase <= COUNT1;
end
end
COUNT1:
if (pauseLenth == (PAUSE - 1)) begin
pauseLenth <= 0;
count <= 0;
countCase <= COUNT0;
pixelCount <= pixelCount + COUNTSTEP;
end else begin
pauseLenth <= pauseLenth + COUNTSTEP;
end
default: countCase <= INITCOUNT;
endcase
end
endmodule
| 7.087684 |
module beatcounterTB ();
reg clk, startCounterEn;
wire process, started;
wire [19:0] pixelCounter;
beatCounter #(
.MINPIXEL(4),
.MAXPIXEL(128)
) beatCounterBlock (
clk,
startCounterEn,
process,
started,
pixelCounter
);
initial begin
clk = 1;
startCounterEn = 0;
#1;
startCounterEn = 1;
#10;
startCounterEn = 0;
#10000;
$stop;
$finish;
end
always begin
clk = #5 !clk; //100mHz clock
end
initial begin
$dumpfile("test1.vcd");
$dumpvars(0, beatcounterTB);
end
endmodule
| 6.598338 |
module BEAT_Clock (
CLOCK_50,
BEAT_CLOCK,
BEAT_PRESCALER
);
input CLOCK_50;
input [4:0] BEAT_PRESCALER;
wire CLOCK_50;
output BEAT_CLOCK;
reg beat_clock;
reg [12:0] ticks;
parameter prescaler = 27'd500000;
wire [26:0] PRESCALER = prescaler;
initial begin
beat_clock = 0;
count = 0;
end
reg [26:0] count;
wire CLOCK_X;
// note: this will half the frequency with a prescaler of 0
// with a prescaler of 1 etc works
always @(posedge CLOCK_X) begin
if (count >= BEAT_PRESCALER) begin
beat_clock <= ~beat_clock;
count <= 0;
end else begin
count <= count + 1'b1;
end
end
PRESCALER beat_pre (
CLOCK_50,
CLOCK_X,
PRESCALER
);
assign BEAT_CLOCK = beat_clock;
endmodule
| 6.858074 |
module beat_generator (
input clk,
input reset,
input en,
output wire beat
);
parameter WIDTH = 10;
parameter STOP = 1000;
wire [WIDTH-1:0] count;
dffre #(WIDTH) counter (
.clk(clk),
.en (en),
.r (reset | (count == STOP)),
.d (count + 1'b1),
.q (count)
);
assign beat = (count == STOP);
endmodule
| 7.93844 |
module BECtrl (
input [ 5:0] OP,
input [31:0] addr,
output reg [ 3:0] BE,
output reg [11:0] fakeAddr,
output reg MemReadSigned
);
always @(*) begin
fakeAddr = addr[11:0];
//$display("BECtrl: fakeAddr %b", fakeAddr[11:0]);
case (OP)
`OP_LBU, `OP_LHU: MemReadSigned = 0;
default: MemReadSigned = 1;
endcase
case (OP)
`OP_LB, `OP_LBU, `OP_SB:
case (addr[1:0])
2'b00: BE = 4'b0001;
2'b01: BE = 4'b0010;
2'b10: BE = 4'b0100;
2'b11: BE = 4'b1000;
default: BE = 4'b0001;
endcase
`OP_LH, `OP_LHU, `OP_SH:
case (addr[1:0])
2'b00: BE = 4'b0011;
2'b10: BE = 4'b1100;
default: BE = 4'b0011;
endcase
`OP_LW, `OP_SW: BE = 4'b1111;
default: BE = 4'b1111;
endcase
end
endmodule
| 7.118908 |
module bec_5 (
x,
y
);
input [4:0] x;
output [4:0] y;
assign y[0] = ~x[0];
assign y[1] = x[1] ^ x[0];
assign y[2] = x[2] ^ (x[1] & x[0]);
assign y[3] = x[3] ^ (x[2] & x[1] & x[0]);
assign y[4] = x[4] ^ (x[3] & x[2] & x[1] & x[0]);
endmodule
| 6.935618 |
module bec_6 (
x,
y
);
input [5:0] x;
output [5:0] y;
assign y[0] = ~x[0];
assign y[1] = x[1] ^ x[0];
assign y[2] = x[2] ^ (x[1] & x[0]);
assign y[3] = x[3] ^ (x[2] & x[1] & x[0]);
assign y[4] = x[4] ^ (x[3] & x[2] & x[1] & x[0]);
assign y[5] = x[5] ^ (x[4] & x[3] & x[2] & x[1] & x[0]);
endmodule
| 6.590231 |
module beeb_accelerator_tb ();
reg clock = 'b0;
reg PhiIn = 'b0;
reg Res_n = 'b1;
wire [15:0] Addr;
wire [ 1:0] R_W_n;
wire [ 7:0] Data;
reg [ 7:0] ext_memory [0:65535];
reg [ 7:0] mem_out;
wire RnW = R_W_n[0];
wire Phi2Out;
wire Sync;
integer i;
initial $readmemh("../src/ram.mem", ext_memory);
always #10 clock = !clock;
always #250 PhiIn = !PhiIn;
initial begin
$dumpvars();
@(negedge PhiIn);
Res_n = 'b0;
@(negedge PhiIn);
@(negedge PhiIn);
@(negedge PhiIn);
@(negedge PhiIn);
@(negedge PhiIn);
Res_n = 'b1;
for (i = 0; i < 200000; i = i + 1) @(negedge PhiIn);
$finish();
end
always @(negedge PhiIn)
if (Addr != 16'hFFFF)
if (RnW) $display("Rd: %04x = %02x", Addr, Data);
else $display("Wr: %04x = %02x", Addr, Data);
always @(negedge PhiIn) if (!RnW) ext_memory[Addr] <= Data;
assign Data = (!RnW || !Phi2Out) ? 8'hZZ :
(Addr[15:8] >= 8'hfc) && (Addr[15:8] <= 8'hfe) ? 8'h00 : ext_memory[Addr];
beeb_accelerator DUT (
.clock(clock),
// 6502 Signals
.PhiIn(PhiIn),
.Phi1Out(),
.Phi2Out(Phi2Out),
.IRQ_n(1'b1),
.NMI_n(1'b1),
.Sync(Sync),
.Addr(Addr),
.R_W_n(R_W_n),
.Data(Data),
.SO_n(1'b0),
.Res_n(Res_n),
.Rdy(1'b1),
// 65C02 Signals
.BE (1'b1),
.ML_n(),
.VP_n(),
// Level Shifter Controls
.OERW_n(),
.OEAH_n(),
.OEAL_n(),
.OED_n (),
.DIRD (),
// External trigger inputs
.trig(2'b0),
// ID/mode inputs
.mode(1'b0),
.id (4'b0),
// Serial Console
.avr_RxD(1'b0),
.avr_TxD(),
// Switches
.sw1(1'b0),
.sw2(1'b0),
// LEDs
.led1(),
.led2(),
.led3()
);
endmodule
| 6.523838 |
module fifo #(
parameter width = 1,
logsize = 6,
lut = 1
) (
input clk,
input [width-1:0] din,
input rd_en,
input rst,
input wr_en,
output [width-1:0] dout,
output empty,
output full
);
localparam SIZE = 1 << logsize;
reg [logsize-1:0] ra, wa, count;
assign full = (count > (SIZE - 4));
assign empty = (count == 0);
always @(posedge clk) begin
if (rst) count <= 0;
else if (rd_en & ~wr_en) count <= count - 1;
else if (wr_en & ~rd_en) count <= count + 1;
end
wire [logsize-1:0] next_ra = rst ? 0 : rd_en ? ra + 1 : ra;
always @(posedge clk) begin
ra <= next_ra;
end
always @(posedge clk) begin
if (rst) wa <= 0;
else if (wr_en) wa <= wa + 1;
end
generate
if (logsize <= 6) begin
(* ram_style = "distributed" *)
reg [width-1:0] qram[SIZE-1:0];
reg [logsize-1:0] qramAddr;
always @(posedge clk) begin
qramAddr <= next_ra;
if (wr_en) qram[wa] <= din;
end
assign dout = qram[qramAddr];
end else begin
(* ram_style = "block" *)
reg [width-1:0] qram[SIZE-1:0];
reg [logsize-1:0] qramAddr;
always @(posedge clk) begin
qramAddr <= next_ra;
if (wr_en) qram[wa] <= din;
end
assign dout = qram[qramAddr];
end
endgenerate
endmodule
| 8.01468 |
module d_line(//input
pulse_clk,
sys_rst_l,
Xe,
Ye,
change_readyH,
//output
X_acc,
Y_acc,
X_dec,
Y_dec,
draw_overH
);
module Beeline_DDA(pulse_clk,
sys_rst_l,
Xe,
Ye,
X_acc,
Y_acc,
X_dec,
Y_dec,
r_start);
input pulse_clk;
input sys_rst_l;
input [31:0] Xe;
input [31:0] Ye;
output X_acc;
output Y_acc;
output X_dec;
output Y_dec;
output r_start;
reg X_acc;
reg Y_acc;
reg X_dec;
reg Y_dec;
reg r_start;
reg r_Sx;
reg r_fSx;
reg r_Sy;
reg r_fSy;
integer i_Xe;
integer i_Ye;
reg r_Sx;
reg r_fSx;
reg r_Sy;
reg r_fSy;
integer i_Xe;
integer i_Ye;
reg [30:0] r31_Xe_abs;
reg [30:0] r31_Ye_abs;
reg [31:0] r32_Max;
integer i_Xe_sign;
integer i_Ye_sign;
integer i_bitNum;
reg [31:0] r32_n;
reg [31:0] r32_Xr;
reg [31:0] r32_Yr;
reg r_start1;
always @(posedge pulse_clk or negedge pulse_clk or posedge sys_rst_l)
begin
if(sys_rst_l==1'b1)
begin
X_acc<=1'b0;
X_dec<=1'b0;
end
else if(pulse_clk==1'b1)
begin
if(r_start1==1'b1)
begin
if((r32_Xr+r31_Xe_abs)>=r32_n)
begin
r32_Xr<=r32_Xr+r31_Xe_abs-r32_n;
X_acc<=r_Sx;
X_dec<=r_fSx;
end
else
r32_Xr<=r32_Xr+r31_Xe_abs;
end
end
else if(pulse_clk==1'b0)
begin
X_acc<=1'b0;
X_dec<=1'b0;
end
end
always @(posedge pulse_clk or negedge pulse_clk or posedge sys_rst_l)
begin
if(sys_rst_l==1'b1)
begin
Y_acc<=1'b0;
Y_dec<=1'b0;
end
else if(pulse_clk==1'b1)
begin
if(r_start1==1'b1)
begin
if((r32_Yr+r31_Ye_abs)>=r32_n)
begin
r32_Yr<=r32_Yr+r31_Ye_abs-r32_n;
Y_acc<=r_Sy;
Y_dec<=r_fSy;
end
else
r32_Yr<=r32_Yr+r31_Ye_abs;
end
end
else if(pulse_clk==1'b0)
begin
Y_acc<=1'b0;
Y_dec<=1'b0;
end
end
always @(posedge pulse_clk)
begin
if(r_start1==1'b1)
r32_Max<=r32_Max-32'b1;
end
always @(posedge pulse_clk or posedge sys_rst_l)
begin
if(sys_rst_l==1'b1)
r_start1<=1'b1;
else if(r32_Max<=32'b1)
r_start1<=1'b0;
end
always @(posedge pulse_clk or sys_rst_l)
begin
if(sys_rst_l==1'b1)
r_start<=1'b1;
else
r_start<=r_start1;
end
endmodule
| 6.819986 |
module beep (
input wire clk,
output wire buzzer
);
// Variaveis: Contador e estado do buzzer
reg beep_r;
reg [27:0] count;
// Bloco always, executado nas bordas de subida do clock, que inplementa 'count'
always @(posedge clk) begin
// Incrementar 'count'
count <= count + 1'b1;
end
// Bloco always executado a cada mudanca de estado do 10 bit de "count"
always @(count[9]) begin
beep_r = !(count[13] & count[24] & count[27]);
end
// Atribuicao para o buzzer
assign buzzer = beep_r;
endmodule
| 7.542508 |
module beepdiv (
input inclk,
output outclk
);
reg [35:0] q;
initial q <= 36'b0;
always @(posedge inclk) q <= q + 1;
//beep
assign outclk = q[26]; //around 1Hz
endmodule
| 6.695405 |
module beeper #(
parameter t = 1,
parameter intensity = 50
) (
input clk,
input rst_n,
output reg beep
);
wire clkout;
frequency_divider #(intensity) fd (
clk,
rst_n,
clkout
);
//maximium cnt is 1048576 beeps
reg [19:0] cnt = 0;
parameter total = 2 * t * intensity;
always @(posedge clkout or negedge rst_n) begin
if (!rst_n) cnt <= 20'b0;
else if (cnt < total) cnt <= cnt + 1'b1;
end
always @(posedge clkout or negedge rst_n) begin
if (!rst_n) beep <= 0;
else if (cnt < total) beep <= ~beep;
end
endmodule
| 6.882218 |
module beep_clk (
input clk,
input rst_n,
input [2:0] pitch,
output reg output_clk
);
parameter clk_freq = 50_000_000 / 2;
localparam
c5 = clk_freq / 523,
d5 = clk_freq / 587,
e5 = clk_freq / 659,
f5 = clk_freq / 698,
g5 = clk_freq / 783,
a5 = clk_freq / 880,
b5 = clk_freq / 987,
a4 = clk_freq / 440;
reg [31:0] div;
reg [31:0] cnt;
always @(posedge clk or negedge rst_n) begin
// div freq
if (!rst_n) begin
cnt <= 0;
output_clk <= 0;
end else if (cnt >= div) begin
output_clk <= ~output_clk;
cnt <= 0;
end else begin
cnt <= cnt + 1;
end
case (pitch)
4'd0: div <= a4;
4'd1: div <= c5;
4'd2: div <= d5;
4'd3: div <= e5;
4'd4: div <= f5;
4'd5: div <= g5;
4'd6: div <= a5;
4'd7: div <= b5;
default: begin
cnt <= 0;
output_clk <= 0;
end
endcase
end
endmodule
| 6.799895 |
module beep_dirve (
input wire clk,
input wire rst_n,
input wire beep_vld,
input wire data_vld,
input wire [23:0] distance_data,
output reg beep
);
parameter MAX_DISTANCE = 20;
parameter MIN_DISTANCE = 10;
parameter MAX_TIME = 50_000_000;
reg [27:0] cnt;
wire [27:0] delay;
wire [19:0] distance;
reg [23:0] distance_data_r;
// wire [ 19:0 ] distance_r ;
//寄存数据
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
distance_data_r <= 0;
end else if (data_vld) begin
distance_data_r <= distance_data;
end
end
// 根据距离设置翻转频率
assign distance = distance_data_r[11:8] + distance_data_r[15:12] * 10 + distance_data_r[19:16] * 100 + distance_data_r[23:20] *1000;
assign delay = ((distance) + 1) * 200_000;
// // led
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 0;
end else if (cnt >= delay) begin
cnt <= 0;
end else begin
cnt <= cnt + 1;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
beep <= 1;
end else if (~beep_vld) begin
beep <= 1;
end else if (distance <= MAX_DISTANCE && distance >= MIN_DISTANCE && cnt == 1 && beep_vld) begin
beep <= ~beep;
end else if (distance < MIN_DISTANCE && beep_vld) begin
beep <= 0;
end else if (distance > MAX_DISTANCE) begin
beep <= 1;
end else begin
beep <= beep;
end
end
endmodule
| 7.420197 |
module BeeSprite (
input wire [9:0] xx, // current x position
input wire [9:0] yy, // current y position
input wire aactive, // high during active pixel drawing
output reg BSpriteOn, // 1=on, 0=off
output wire [7:0] dataout, // 8 bit pixel value from Bee.mem
input wire BR, // right button
input wire BL, // left button
input wire gameover,
input wire i_reset,
input wire Pclk, // 25MHz pixel clock
output reg [9:0] beeXOUT,
output reg [9:0] beeYOUT,
input wire [8:0] xm,
input wire m_done_tick
);
wire sx = xm[8];
wire [8:0] ndx = sx ? {1'b0, ~xm[7:0]} + 1 : {1'b0, xm[7:0]};
// instantiate BeeRom code
reg [9:0] address; // 2^10 or 1024, need 34 x 27 = 918
BeeRom BeeVRom (
.i_addr(address),
.i_clk2(Pclk),
.o_data(dataout)
);
// setup character positions and sizes
reg [9:0] BeeX = 297; // Bee X start position
reg [8:0] BeeY = 433; // Bee Y start position
localparam BeeWidth = 28; // Bee width in pixels
localparam BeeHeight = 16; // Bee height in pixels
localparam ShipSpeed = 5;
always @(posedge Pclk) begin
if (i_reset == 1) begin
BeeX <= 297;
BeeY <= 433;
end else if (xx == 639 && yy == 479) begin // check for left or right button pressed
// if ((BR == 1 || > 0) && BeeX<640-BeeWidth-2)
// BeeX<=BeeX+ShipSpeed;
// if ((BL == 1 || xm < 0) && BeeX>2)
// BeeX<=BeeX-ShipSpeed;
BeeX <= (ndx > 2 && ndx < 100) ? (sx ? (BeeX>2+ndx ? BeeX - ndx : 2)
: (BeeX < 640-BeeWidth-2-ndx) ? BeeX+ndx : 640-BeeWidth-2) : BeeX;
end
if (aactive) begin // check if xx,yy are within the confines of the Bee character
if (xx == BeeX - 1 && yy == BeeY && gameover == 0) begin
address <= 0;
BSpriteOn <= 1;
end
if ((xx>BeeX-1) && (xx<BeeX+BeeWidth) && (yy>BeeY-1) && (yy<BeeY+BeeHeight) && gameover == 0)
begin
address <= address + 1;
BSpriteOn <= 1;
end else BSpriteOn <= 0;
end
beeXOUT <= BeeX;
beeYOUT <= BeeY;
end
endmodule
| 6.626962 |
module for generating new item list
* List Format:
* At most 30 items in the list
* 0 - 9 : golds
* 10 - 19 ：stones
* 20 - 29 : diamonds
* For item n:
d[n << 5 + 31 : n << 5 + 19] >> 4 == left when drawing
d[n << 5 + 18 : n << 5 + 8] >> 4 == top
d[n << 5] moved?
d[n << 5 + 1] visible?
d[n << 5 + 7 : n << 5 + 2] extendable data, not in
*
* INPUT:
* clock
* resetn: syn low active reset
* quantity
* item
*
* PARAMETER:
*
* OUTPUT:
* [17:0] item
* Author: Yucan Wu
* Version: 0.0.1
* Created: Nov 17, 2018
* Last Updated: Nov 17, 2018, just started
* Tested: init
**/
module Rand(
input clock, resetn, enable,
output reg [8 : 0] out
);
parameter SEED = 16'd163;
parameter parA = 16'd43;
parameter parB = 16'd181;
wire[40: 0] temp;
reg [5: 0] counter;
assign temp = counter * out + parB;
always @(posedge clock) begin
if (!resetn) begin
out = SEED;
counter = 1;
end
else if (enable) begin
out <= temp % 457;
counter = counter + temp[5:2];
end
end
endmodule
| 7.402579 |
module ItemMap(
clock,
resetn,
generateEn,
// quantity,
size,
data,
counter,
moveEn,
moveIndex,
moveX, //please multiple by << 4
moveY,
moveState,
visible,
);
parameter MAX_SIZE = 576; //576
input clock, resetn, generateEn;
// input [4:0] quantity;
input [5:0] size;
output reg [MAX_SIZE - 1: 0] data;
input moveEn;
input [5:0]moveIndex;
input [10:0]moveX; //please multiple by << 4
input [10:0]moveY;
input moveState, visible;
output reg [5:0] counter;
reg regO[31:0];
wire [4:0]x;
wire [3:0]y;
Rand rand_gen(
.clock(clock),
.resetn(resetn),
.enable(generateEn),
.out({x,y})
);
wire [13:0] tempX, tempY;
integer index;
integer k;
reg isCovered;
reg isMoving;
reg [25:0] usedData [31:0];
reg [13:0] testX, testY;
reg [25:0] tempData, tempOld;
always @(posedge clock, negedge generateEn) begin
if (!generateEn) begin
counter = 0;
end
if (!resetn) begin
data = 0;
counter = 0;
isMoving = 0;
end
else if (generateEn) begin
isCovered <= 0;
testX <= x % 20;
testY <= y % 10;
tempData <= ((x%20) << 21) + ((y%10) << 9);
for (index = 0; index < counter; index = index + 1) begin
tempOld = usedData[index];
if (tempOld[25:0] == tempData[25:0]) isCovered <= 1;
end
if (!isCovered) begin
usedData[counter] <= tempData;
data <= data + (tempData << (counter * 26));
counter <= counter + 1;
end
end
else if (moveEn) begin
isMoving = 1;
data[moveIndex * 26] <= moveState;
data <= data + (moveX[10]? -1: 1) * ((moveX[9:0] >> 0) << (moveIndex * 26 + 13)) +
(moveY[10]? -1: 1) * ((moveY >> 0) << (moveIndex * 26 + 1));
end
end
assign tempX = (data[moveIndex * 26 + 25] << 12) +
(data[moveIndex * 26 + 24] << 11) +
(data[moveIndex * 26 + 23] << 10) +
(data[moveIndex * 26 + 22] << 9) +
(data[moveIndex * 26 + 21] << 8) +
(data[moveIndex * 26 + 20] << 7) +
(data[moveIndex * 26 + 19] << 6) +
(data[moveIndex * 26 + 18] << 5) +
(data[moveIndex * 26 + 17] << 4) +
(data[moveIndex * 26 + 16] << 3) +
(data[moveIndex * 26 + 15] << 2) +
(data[moveIndex * 26 + 14] << 1) +
(data[moveIndex * 26 + 13] << 0);
assign tempY = (data[moveIndex * 26 + 12] << 11) +
(data[moveIndex * 26 + 11] << 10) +
(data[moveIndex * 26 + 10] << 9) +
(data[moveIndex * 26 + 9] << 8) +
(data[moveIndex * 26 + 8] << 7) +
(data[moveIndex * 26 + 7] << 6) +
(data[moveIndex * 26 + 6] << 5) +
(data[moveIndex * 26 + 5] << 4) +
(data[moveIndex * 26 + 4] << 3) +
(data[moveIndex * 26 + 3] << 2) +
(data[moveIndex * 26 + 2] << 1) +
(data[moveIndex * 26 + 1] << 0);
endmodule
| 6.706677 |
module before_car_enter (
input clk,
input rst,
input [4:0] bt_out,
input [2:0] view,
output reg [2:0] choose_parking,
output reg [2:0] state,
input [15:0] key_out
);
wire left_bt_in, right_bt_in, mid_bt_in;
assign left_bt_in = bt_out[1];
assign right_bt_in = bt_out[0];
assign mid_bt_in = bt_out[3];
reg ispressed;
reg [4:0] change_time = 5'd0;
always @(posedge clk) begin
if (!left_bt_in && !right_bt_in && !mid_bt_in) begin
ispressed = 0;
end
if (rst) begin
state <= 1;
end else begin
if (view == 0) begin
if (left_bt_in && !ispressed) begin
ispressed = 1;
if (state == 1) state <= 2;
else state <= state - 1;
end else if (right_bt_in && !ispressed) begin
ispressed = 1;
if (state == 2) state <= 1;
else state <= state + 1;
end
case (key_out[11:10])
2'b01: state <= 1;
2'b10: state <= 2;
endcase
end
end
end
endmodule
| 6.92177 |
module BeginLine (
DisLine,
FallLine,
start,
level,
clk,
Ascii,
h_addr,
ready,
led0,
clra,
w_addr
);
input [7:0] Ascii;
input [9:0] h_addr;
input [0:479] DisLine;
input clk;
input clra;
output reg [0:479] FallLine;
output reg ready;
output reg start;
output reg [2:0] level;
output reg led0;
output reg [9:0] w_addr;
reg [2:0] anslevel;
//start = 1 begin game
integer i = 0;
reg [7:0] State;
reg [7:0] DownState;
reg over;
wire [12:0] ArrowLine;
wire [12:0] ArrowHang[3:0];
wire [143:0] Font;
wire signed [479:0] tem1;
wire [479:0] tem2;
wire [479:0] Right1;
wire [479:0] Right2;
wire [15:0] FontLine[8:0];
initial begin
State <= 0;
DownState <= 0;
over <= 0;
level <= 0;
anslevel <= 0;
start <= 0;
led0 <= 0;
// 32 inter
end
assign ArrowLine = 270;
assign ArrowHang[0] = 192;
assign ArrowHang[1] = 224;
assign ArrowHang[2] = 256;
assign ArrowHang[3] = 288;
//192-304
assign Font = 144'h0000010001000100054007C0038001000000;
assign FontLine[0] = Font[143:128];
assign FontLine[1] = Font[127:112];
assign FontLine[2] = Font[111:96];
assign FontLine[3] = Font[95:80];
assign FontLine[4] = Font[79:64];
assign FontLine[5] = Font[63:48];
assign FontLine[6] = Font[47:32];
assign FontLine[7] = Font[31:16];
assign FontLine[8] = Font[15:0];
always @(posedge clk) begin
if (over) begin
i <= i;
end else if (i == 2500000) begin
if (State) begin
if (State == 10) begin
State <= 0;
ready <= 0;
i <= 0;
end else if (h_addr == ArrowLine + State - 1) begin
ready <= 1;
State <= State + 1'b1;
w_addr <= h_addr;
case (level)
0: begin
FallLine <= {DisLine[0:191], FontLine[(State-1'b1)], 96'b0, DisLine[304:479]};
end
1: begin
FallLine <= {DisLine[0:191], 32'b0, FontLine[(State-1'b1)], 64'b0, DisLine[304:479]};
end
2: begin
FallLine <= {DisLine[0:191], 64'b0, FontLine[(State-1'b1)], 32'b0, DisLine[304:479]};
end
3: begin
FallLine <= {DisLine[0:191], 96'b0, FontLine[(State-1'b1)], DisLine[304:479]};
end
default: begin
FallLine <= DisLine;
end
endcase
end else ready <= 0;
end
else if(Ascii==8'h77&&!clra)//w
begin
led0 <= !led0;
anslevel <= level;
if (level == 0) level <= 3;
else level <= level - 1'b1;
State <= 1;
end
else if(Ascii==8'h73&&!clra)//s
begin
led0 <= !led0;
anslevel <= level;
if (level == 3) level <= 0;
else level <= level + 1'b1;
State <= 1;
end
else if(Ascii==8'h0d&&!clra)//enter
begin
led0 <= !led0;
State <= 0;
over <= 1;
start <= 1;
end else i <= 0;
end else i <= i + 1'b1;
end
endmodule
| 7.256828 |
module to see the flow of control in nested begin-end and
//>fork-join block.
module begin_end_fork_join (
);
reg x, y, a, b, p, m;
initial begin
x= 1'b0; $display($time,"x \n");
#5 y= 1'b1; $display($time,"y \n");
fork
#20 a=x;
#20 $display($time,"a \n");
#15 b=y;
#15 $display($time,"b \n");
join
#40 x= 1'b1; $display($time,"x \n");
fork
#10 p=x;
#10$display($time,"p \n");
begin
#10 a=y; $display($time,"a \n");
#30 b=x; $display($time,"b \n");
end
#5 m=y;
#5 $display($time,"m \n");
join
end
endmodule
| 7.3835 |
module
module divide1(input X, input [1:0] Yin, output Z, output [1:0] f);
reg Z;
reg [2:0] out;
wire [2:0] Yout;
reg [1:0] f;
assign Yout[2:1]=Yin[1:0];
assign Yout[0]=X;
always@(*)
begin
out=Yout;
if(out>=3)
begin
Z=1;
out=out-3;
end
else
Z=0;
f=out[1:0];
end
endmodule
| 7.587156 |
module
module divideN #(parameter integer WIDTH=4)
(input [WIDTH-1:0] X, input [1:0] in, output [WIDTH-1:0] Z, output [1:0] out);
wire [WIDTH-1:0] [1:0] Yin,Yout;
divide1 g1 [WIDTH-1:0] (X,Yin,Z,Yout);
assign Yin[WIDTH-1]=in;
assign Yin[WIDTH-2:0]=Yout[WIDTH-1:1];
assign out=Yout[0];
endmodule
| 7.587156 |
module tb;
parameter integer WIDTH = 6;
reg [WIDTH-1:0] X = 6'b0;
reg [1:0] in = 2'b0;
wire [WIDTH-1:0] Z;
wire [1:0] out;
divideN #(
.WIDTH(WIDTH)
) g1 (
X,
in,
Z,
out
);
initial begin
repeat (63) #15 X = X + 1;
end
initial $monitor("X=%d, quotient=%d, remainder=%d @ time=%d", X, Z, out, $time);
endmodule
| 6.612288 |
module behave1p_mem #(
parameter width = 8,
parameter depth = 256,
parameter addr_sz = 8
) //log2(depth))
( /*AUTOARG*/
// Outputs
d_out,
// Inputs
wr_en,
rd_en,
clk,
d_in,
addr
);
input wr_en, rd_en, clk;
input [width-1:0] d_in;
input [addr_sz-1:0] addr;
output [width-1:0] d_out;
reg [addr_sz-1:0] r_addr;
reg [ width-1:0] array [0:depth-1];
always @(posedge clk) begin
if (wr_en) begin
array[addr] <= #1 d_in;
end else if (rd_en) begin
r_addr <= #1 addr;
end
end // always @ (posedge clk)
assign d_out = array[r_addr];
endmodule
| 7.24158 |
module behave2p_mem #(
parameter width = 8,
parameter depth = 256,
parameter addr_sz = $clog2(depth)
) ( /*AUTOARG*/
// Outputs
d_out,
// Inputs
wr_en,
rd_en,
wr_clk,
rd_clk,
d_in,
rd_addr,
wr_addr
);
input wr_en, rd_en, wr_clk;
input rd_clk;
input [width-1:0] d_in;
input [addr_sz-1:0] rd_addr, wr_addr;
output [width-1:0] d_out;
reg [addr_sz-1:0] r_addr;
reg [ width-1:0] array [0:depth-1];
always @(posedge wr_clk) begin
if (wr_en) begin
array[wr_addr] <= #1 d_in;
end
end
always @(posedge rd_clk) begin
if (rd_en) begin
r_addr <= #1 rd_addr;
end
end // always @ (posedge clk)
assign d_out = array[r_addr];
endmodule
| 7.03544 |
module HA (
a,
b,
sum,
carry
);
input a, b;
output sum, carry;
reg sum, carry;
always @(a or b) begin
sum = a ^ b; // ^ stands for XOR
carry = a & b; // & stands for AND
end
endmodule
| 7.123396 |
module FA (
x,
y,
c_in,
sum,
c_out
);
input x, y, c_in;
output sum, c_out;
reg sum, c_out;
wire a, b, c;
always @(x or y or c_in) begin
{c_out, sum} = x + y + c_in; //{cout , sum} 當作兩個 bits
end
endmodule
| 7.58914 |
module main (
input clock,
input reset,
input [7:0] a,
input [7:0] b,
output [7:0] y
);
assign y = a + b;
endmodule
| 7.081372 |
module main (
clock,
reset,
a,
b,
y
);
input clock;
input reset;
input [7:0] a;
input [7:0] b;
output [7:0] y;
wire [7:0] a;
wire [7:0] b;
wire [7:0] y;
wire \y[4]_INST_0_i_1_n_0 ;
wire \y[7]_INST_0_i_1_n_0 ;
wire \y[7]_INST_0_i_2_n_0 ;
LUT2 #(
.INIT(4'h6)
) \y[0]_INST_0 (
.I0(a[0]),
.I1(b[0]),
.O (y[0])
);
LUT4 #(
.INIT(16'h8778)
) \y[1]_INST_0 (
.I0(a[0]),
.I1(b[0]),
.I2(b[1]),
.I3(a[1]),
.O (y[1])
);
LUT6 #(
.INIT(64'hF880077F077FF880)
) \y[2]_INST_0 (
.I0(b[0]),
.I1(a[0]),
.I2(a[1]),
.I3(b[1]),
.I4(b[2]),
.I5(a[2]),
.O (y[2])
);
LUT3 #(
.INIT(8'h96)
) \y[3]_INST_0 (
.I0(\y[4]_INST_0_i_1_n_0 ),
.I1(b[3]),
.I2(a[3]),
.O (y[3])
);
LUT5 #(
.INIT(32'hE81717E8)
) \y[4]_INST_0 (
.I0(\y[4]_INST_0_i_1_n_0 ),
.I1(a[3]),
.I2(b[3]),
.I3(b[4]),
.I4(a[4]),
.O (y[4])
);
LUT6 #(
.INIT(64'hEEEEE888E8888888)
) \y[4]_INST_0_i_1 (
.I0(b[2]),
.I1(a[2]),
.I2(b[0]),
.I3(a[0]),
.I4(a[1]),
.I5(b[1]),
.O (\y[4]_INST_0_i_1_n_0 )
);
LUT3 #(
.INIT(8'h96)
) \y[5]_INST_0 (
.I0(\y[7]_INST_0_i_1_n_0 ),
.I1(b[5]),
.I2(a[5]),
.O (y[5])
);
LUT5 #(
.INIT(32'hE81717E8)
) \y[6]_INST_0 (
.I0(\y[7]_INST_0_i_1_n_0 ),
.I1(a[5]),
.I2(b[5]),
.I3(b[6]),
.I4(a[6]),
.O (y[6])
);
LUT6 #(
.INIT(64'h001717FFFFE8E800)
) \y[7]_INST_0 (
.I0(b[5]),
.I1(a[5]),
.I2(\y[7]_INST_0_i_1_n_0 ),
.I3(a[6]),
.I4(b[6]),
.I5(\y[7]_INST_0_i_2_n_0 ),
.O (y[7])
);
LUT5 #(
.INIT(32'hEEE8E888)
) \y[7]_INST_0_i_1 (
.I0(b[4]),
.I1(a[4]),
.I2(\y[4]_INST_0_i_1_n_0 ),
.I3(a[3]),
.I4(b[3]),
.O (\y[7]_INST_0_i_1_n_0 )
);
LUT2 #(
.INIT(4'h6)
) \y[7]_INST_0_i_2 (
.I0(a[7]),
.I1(b[7]),
.O (\y[7]_INST_0_i_2_n_0 )
);
endmodule
| 7.779865 |
module main (
input clock,
input reset,
input [7:0] a,
input [7:0] b,
output [7:0] y
);
logic [7:0] r;
logic [7:0] s;
assign s = a + b;
always_ff @(posedge clock) begin
if (reset) begin
r <= 8'b0;
end else begin
r <= s;
end
end
assign y = r;
endmodule
| 7.081372 |
module main (
clock,
reset,
a,
b,
y
);
input clock;
input reset;
input [7:0] a;
input [7:0] b;
output [7:0] y;
wire \<const0> ;
wire \<const1> ;
wire GND_2;
wire [7:0] a;
wire [7:0] b;
wire clock;
wire \r[7]_i_2_n_0 ;
wire \r[7]_i_3_n_0 ;
wire \r[7]_i_4_n_0 ;
wire \r[7]_i_5_n_0 ;
wire \r[7]_i_6_n_0 ;
wire \r[7]_i_7_n_0 ;
wire \r[7]_i_8_n_0 ;
wire \r[7]_i_9_n_0 ;
wire \r_reg[7]_i_1_n_1 ;
wire \r_reg[7]_i_1_n_2 ;
wire \r_reg[7]_i_1_n_3 ;
wire \r_reg[7]_i_1_n_4 ;
wire \r_reg[7]_i_1_n_5 ;
wire \r_reg[7]_i_1_n_6 ;
wire \r_reg[7]_i_1_n_7 ;
wire reset;
wire [7:0] s;
wire [7:0] y;
GND GND (.G(\<const0> ));
GND GND_1 (.G(GND_2));
VCC VCC (.P(\<const1> ));
LUT2 #(
.INIT(4'h6)
) \r[7]_i_2 (
.I0(a[7]),
.I1(b[7]),
.O (\r[7]_i_2_n_0 )
);
LUT2 #(
.INIT(4'h6)
) \r[7]_i_3 (
.I0(a[6]),
.I1(b[6]),
.O (\r[7]_i_3_n_0 )
);
LUT2 #(
.INIT(4'h6)
) \r[7]_i_4 (
.I0(a[5]),
.I1(b[5]),
.O (\r[7]_i_4_n_0 )
);
LUT2 #(
.INIT(4'h6)
) \r[7]_i_5 (
.I0(a[4]),
.I1(b[4]),
.O (\r[7]_i_5_n_0 )
);
LUT2 #(
.INIT(4'h6)
) \r[7]_i_6 (
.I0(a[3]),
.I1(b[3]),
.O (\r[7]_i_6_n_0 )
);
LUT2 #(
.INIT(4'h6)
) \r[7]_i_7 (
.I0(a[2]),
.I1(b[2]),
.O (\r[7]_i_7_n_0 )
);
LUT2 #(
.INIT(4'h6)
) \r[7]_i_8 (
.I0(a[1]),
.I1(b[1]),
.O (\r[7]_i_8_n_0 )
);
LUT2 #(
.INIT(4'h6)
) \r[7]_i_9 (
.I0(a[0]),
.I1(b[0]),
.O (\r[7]_i_9_n_0 )
);
FDRE \r_reg[0] (
.C (clock),
.CE(\<const1> ),
.D (s[0]),
.Q (y[0]),
.R (reset)
);
FDRE \r_reg[1] (
.C (clock),
.CE(\<const1> ),
.D (s[1]),
.Q (y[1]),
.R (reset)
);
FDRE \r_reg[2] (
.C (clock),
.CE(\<const1> ),
.D (s[2]),
.Q (y[2]),
.R (reset)
);
FDRE \r_reg[3] (
.C (clock),
.CE(\<const1> ),
.D (s[3]),
.Q (y[3]),
.R (reset)
);
FDRE \r_reg[4] (
.C (clock),
.CE(\<const1> ),
.D (s[4]),
.Q (y[4]),
.R (reset)
);
FDRE \r_reg[5] (
.C (clock),
.CE(\<const1> ),
.D (s[5]),
.Q (y[5]),
.R (reset)
);
FDRE \r_reg[6] (
.C (clock),
.CE(\<const1> ),
.D (s[6]),
.Q (y[6]),
.R (reset)
);
FDRE \r_reg[7] (
.C (clock),
.CE(\<const1> ),
.D (s[7]),
.Q (y[7]),
.R (reset)
);
(* ADDER_THRESHOLD = "35" *)
CARRY8 \r_reg[7]_i_1 (
.CI(\<const0> ),
.CI_TOP(GND_2),
.CO({
\r_reg[7]_i_1_n_1 ,
\r_reg[7]_i_1_n_2 ,
\r_reg[7]_i_1_n_3 ,
\r_reg[7]_i_1_n_4 ,
\r_reg[7]_i_1_n_5 ,
\r_reg[7]_i_1_n_6 ,
\r_reg[7]_i_1_n_7
}),
.DI({\<const0> , a[6:0]}),
.O(s),
.S({
\r[7]_i_2_n_0 ,
\r[7]_i_3_n_0 ,
\r[7]_i_4_n_0 ,
\r[7]_i_5_n_0 ,
\r[7]_i_6_n_0 ,
\r[7]_i_7_n_0 ,
\r[7]_i_8_n_0 ,
\r[7]_i_9_n_0
})
);
endmodule
| 7.779865 |
module mux_2to1(
input [1:0] in,
input sel,
output o,
);
always @(*) begin
if (sel)
o = in[0]; // blocking assignment
else
o = in[1];
end
endmodule
| 8.149822 |
module mux_4to1(
input [3:0] in, // Input Set: 2-bit wire
input [1:0] sel, // Select: 2-bit wire
output o, // 1-bit output
);
always @(*) begin
if (sel == 2'b00)
o = in[0];
else if (sel == 2'b01)
o = in[1];
else if (sel == 2'b10)
o = in[2];
else if (sel == 2'b11)
o = in[2];
else
o = 1'bx; // catch bugs: mux is not well defined for any other input
end
endmodule
| 7.104041 |
module mux_4to1(
input [3:0] in, // Input Set: 4-bit wire
input [1:0] sel, // Select: 2-bit wire
output o, // 1-bit output
);
always @(*) begin
case(sel)
2'b00: o = in[0];
2'b01: o = in[1];
2'b10: o = in[2];
2'b11: o = in[3];
default: o = 1'bx; // catch bugs
endcase
end
endmodule
| 7.104041 |
module mux_4to1(
input [7:0] in, // Input Set @in: choose from 8 bits (bit 0-7)
input [2:0] sel, // Select @sel: 2^3 = 8 possible values
output o // Output @o: single bit from @in
);
// 2 muxes will output the option for the
wire msb_is_0, msb_is_1; // MSB of the bit number (0-7)
// this mux choses from options 3'b000, 3'b001, 3'b010, 3'b011
mux_4to1 in30 (.in(in[3:0], .sel(in[1:0]), .o(msb_is_0));
// this mux choses from options 3'b100, 3'b101, 3'b110, 3'b111
mux_4to1 in74 (.in(in[7:4], .sel(in[1:0]), .o(msb_is_1));
always @(*) begin
if (sel[2] == 1'b0)
o = msb_is_0;
else if (sel[2] == 1'b1)
o = msb_is_1;
else
o = 1'bx;
end
endmodule
| 7.104041 |
module behavioral_adder (
input [7:0] a,
input [7:0] b,
output [8:0] sum
);
assign sum = a + b;
endmodule
| 7.284129 |
module behavioral_full_adder_64 (
input [63:0] A,
input [63:0] B,
output [64:0] SUM
);
assign SUM = (A + B);
endmodule
| 7.075084 |
module behavioral_full_adder_test;
// Inputs
reg [63:0] A;
reg [63:0] B;
// Outputs
wire [64:0] SUM;
// Instantiate two counter variables for the test loop
integer count;
integer count2;
// Instantiate the Unit Under Test (UUT)
behavioral_full_adder_64 uut (
.A (A),
.B (B),
.SUM(SUM)
);
initial begin
$monitor("%d + %d = %d", A, B, SUM);
// Iterate through all possible combination of 0-32
count = 0;
count2 = 0;
A = 0;
B = 0;
// Loops over the possible combinations for the inputs A and B
for (count = 0; count <= 32; count = count + 1) begin
{A} = count;
for (count2 = 0; count2 <= 32; count2 = count2 + 1) begin
{B} = count2;
#1;
end
end
end
initial #4000 $finish; // The test will run for a total interval of 4000 nanoseconds
endmodule
| 7.075084 |
module buffer (
Y,
A
);
output Y;
input A;
assign Y = A;
endmodule
| 6.861394 |
module nand2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(A & B);
endmodule
| 9.113032 |
module nor2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(A | B);
endmodule
| 8.297456 |
module and2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = A & B;
endmodule
| 7.107954 |
module or2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = A | B;
endmodule
| 7.637076 |
module nand3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
assign Y = ~(A & B & C);
endmodule
| 8.175282 |
module nor3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
assign Y = ~(A | B | C);
endmodule
| 7.681855 |
module and3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
assign Y = A & B & C;
endmodule
| 6.818889 |
module or3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
assign Y = A | B | C;
endmodule
| 7.391653 |
module nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
assign Y = ~(A & B & C & D);
endmodule
| 8.989501 |
module nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
assign Y = ~(A | B | C | D);
endmodule
| 7.13519 |
module and4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
assign Y = A & B & C & D;
endmodule
| 7.001422 |
module or4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
assign Y = A | B | C | D;
endmodule
| 7.381621 |
module nand2b (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(~A & B);
endmodule
| 6.603018 |
module nor2b (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(~A | B);
endmodule
| 6.703764 |
module aoi21 (
Y,
A0,
A1,
B0
);
output Y;
input A0, A1, B0;
assign Y = ~((A0 & A1) | B0);
endmodule
| 6.591789 |
module oai21 (
Y,
A0,
A1,
B0
);
output Y;
input A0, A1, B0;
assign Y = ~((A0 | A1) & B0);
endmodule
| 6.561625 |
module aoi22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0, A1, B0, B1;
assign Y = ~((A0 & A1) | (B0 & B1));
endmodule
| 6.668353 |
module oai22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0, A1, B0, B1;
assign Y = ~((A0 | A1) & (B0 | B1));
endmodule
| 6.579044 |
module xor2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = A ^ B;
endmodule
| 7.788927 |
module xnor2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(A ^ B);
endmodule
| 6.713225 |
module mux2 (
Y,
S,
A,
B
);
output Y;
input S, A, B;
assign Y = S ? B : A;
endmodule
| 6.809767 |
module muxi2 (
Y,
S,
A,
B
);
output Y;
input S, A, B;
assign Y = ~(S ? B : A);
endmodule
| 7.147146 |
module behavioral_UART_tx //UART spoofer
#(
parameter bit_time = 104000
) // nanoseconds
(
output reg line
);
initial line = 1'b1; // line idles true
task send(input [7:0] data);
reg [9:0] uart_frame;
begin
// construct the whole frame with start and stop bit
// STOP data START
uart_frame = {1'b1, data, 1'b0};
repeat (10) // number of bit-symbols to send
begin
line = uart_frame[0]; // drive line to correct level
uart_frame = uart_frame >> 1; // prepare next bit
#(bit_time); // hold output for one bit time
end
end
endtask
endmodule
| 7.785543 |
module runway_select (
d,
A,
B,
clk,
en,
signal
);
/********************************************
Inputs :
1) d-signifies direction of travel bits
00-East,10-West,01-South,11-North
2) Clock
3) Enable pin
Ouputs :
1) signal-signifies the output generated by
the curcuit
Other Variables:
1) a-signifies the current state of runway a
2) b-signifies the current state of runway
3) counta-counter for runway a, counts till 15
and clears the runway after that
4) countb-counter for runway b, counts till 15
and clears the runway after that
********************************************/
input [1:0] d;
input A, B;
input clk;
input en;
output reg [3:0] signal;
reg a = 1'b0;
reg b = 1'b0;
integer counta = 0;
integer countb = 0;
//The en signal is used to represent that an input has been given to the circuit. It is negative edge triggererd,
//any change in the value signifies a new input and hence a new set of computations is carried out.
always @(negedge en) begin
if (d == 2'b00) //Plane is heading in E-W Direction
if(b == 0) //Runway B is free
begin
signal = 4'b1011; //Land on Runway B
b = 1'b1; //Make Runway B occupied for next set of inputs
end
else if(a == 0) //Runway A is free
begin
signal = 4'b1010; //Land on Runway A
a = 1'b1; //Make Runway A occupied for next set of inputs
end else signal = 4'b1101; //If none of the runways are available send the wait signal
if (d == 2'b01) //Plane is heading in W-E Direction
if(a == 0) //Runway A is free
begin
signal = 4'b1010; //Land on Runway A
a = 1'b1; //Make Runway A occupied for next set of inputs
end
else if(b == 0) //Runway B is free
begin
signal = 4'b1011; //Land on Runway B
b = 1'b1; //Make Runway B occupied for next set of inputs
end else signal = 4'b1101; //If none of the runways are available send the wait signal
if (d == 2'b10) //Plane is heading in N-S Direction
if(b == 0) //Runway B is free
begin
signal = 4'b1011; //Land on Runway B
b = 1'b1; //Make Runway B occupied for next set of inputs
end
else if(a == 0) //Runway A is free
begin
signal = 4'b1010; //Land on Runway A
a = 1'b1; //Make Runway A occupied for next set of inputs
end else signal = 4'b1101; //If none of the runways are available send the wait signal
if (d == 2'b11) //Plane is heading in S-N Direction
if(a == 0) //Runway A is free
begin
signal = 4'b1010; //Land on Runway A
a = 1'b1; //Make Runway A occupied for next set of inputs
end
else if(b == 0) //Runway B is free
begin
signal = 4'b1011; //Land on Runway B
b = 1'b1; //Make Runway B occupied for next set of inputs
end else signal = 4'b1101; //If none of the runways are available send the wait signal
end
//The below is an implementation of a counter that counts till 15, if a is occupied the timer for a starts likewise, if b is
//occupied timer for b starts. The timers reset and the runways are made free once the count reaches 15.
always @(posedge clk) begin
if (a == 1) counta = counta + 1;
if (b == 1) countb = countb + 1;
if (counta == 15) a = 0;
if (countb == 15) b = 0;
end
endmodule
| 6.7696 |
module behaviorProcessor (
servo_en,
motor_en,
empty,
sipo_en,
piso_en,
sipo_done,
rd_en,
clk,
rst
);
input empty;
output reg rd_en;
input clk, rst;
output reg sipo_en;
input piso_en;
input sipo_done;
input servo_en, motor_en;
always @(posedge clk) begin
if (rst) begin
sipo_en <= 0;
rd_en <= 0;
end else begin
if (empty && piso_en || empty && motor_en || empty && servo_en) begin
rd_en <= 1;
sipo_en <= 1;
end
if (sipo_done) begin
rd_en <= 0;
sipo_en <= 0;
end
end
end
endmodule
| 6.554959 |
module behavior_model (
clk,
srstn,
load,
encrypt,
crypt_mode,
load_idx,
code_in,
code_out,
code_valid
);
input clk; //clock input
input srstn; //synchronous reset (active low)
input load; //load control signal (level sensitive). 0/1: inactive/active
//effective in IDLE and LOAD states
input encrypt; //encrypt control signal (level sensitive). 0/1: inactive/active
//effective in READY state
input crypt_mode; //0: encrypt; 1:decrypt
input [8-1:0] load_idx; //index of rotor table to be loaded; A:0~63; B:64~127; C:128~191;
input [6-1:0] code_in; //When load is active,
//rotorA[load_idx[5:0]] <= code_in if load_idx[7:6]==2'b00
//rotorB[load_idx[5:0]] <= code_in if load_idx[7:6]==2'b01
//rotorC[load_idx[5:0]] <= code_in if load_idx[7:6]==2'b10
output reg [6-1:0] code_out; //encrypted code word (register output)
output reg code_valid; //0: non-valid code_out; 1: valid code_out (register output)
parameter IDLE = 0, LOAD = 1, READY = 2;
integer i, k;
reg [1:0] state, n_state;
reg [6-1:0] rotorA_table[0:64-1];
reg [6-1:0] reflector_table[0:64-1];
reg [6-1:0] rotA_o;
reg [6-1:0] ref_o;
reg [6-1:0] last_A;
/// FSM ///
always @* begin
if (~srstn) state = IDLE;
case (state)
IDLE: if (load) @(posedge clk) state = LOAD;
LOAD: begin
if (load) begin
@(posedge clk) state = LOAD;
end else begin
@(posedge clk) state = READY;
end
end
READY: state = READY;
endcase
for (i = 0; i < 64; i = i + 1) begin
reflector_table[i] = 63 - i;
end
end
initial begin
// Load Table
$readmemh("../sim/rotor/rotorA.dat", rotorA_table);
wait (encrypt);
for (k = 0; k < 24; k = k + 1) begin
@(posedge clk) rotA_o = rotorA_table[code_in];
ref_o = reflector_table[rotA_o];
for (i = 0; i < 64; i = i + 1) begin
if (rotorA_table[i] == ref_o) begin
code_out = i;
end
end
code_valid = 1;
last_A = rotorA_table[63];
for (i = 62; i >= 0; i = i - 1) begin
rotorA_table[i+1] = rotorA_table[i];
end
rotorA_table[0] = last_A;
end
end
endmodule
| 7.098337 |
module sn74151 (
P1,
P2,
P3,
P4,
P5,
P6,
P7,
P8,
P9,
P10,
P11,
P12,
P13,
P14,
P15,
P16
);
input wire P4, P3, P2, P1, P15, P14, P13, P12, P7, P11, P10, P9, P8, P16;
// I0 I1 I2 I3 I4 I5 I6 I7 E S0 S1 S2 GND VCC
output reg P5; // Z
output wire P6; // Z_BAR
assign P6 = ~P5;
always @(P1, P2, P3, P4, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16) begin
if ((P16 == 1'b1) && (P8 == 1'b0) && (P7 == 1'b0)) begin
case ({
P11, P10, P9
})
3'b000: P5 = P4;
3'b001: P5 = P3;
3'b010: P5 = P2;
3'b011: P5 = P1;
3'b100: P5 = P15;
3'b101: P5 = P14;
3'b110: P5 = P13;
3'b111: P5 = P12;
endcase
end
end
endmodule
| 6.7752 |
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