code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BCU (
input wire zf,
input wire cf,
input wire sf,
input wire vf,
input [`IR_funct3] funct3,
input branchSignal,
output PCSrc
);
reg result;
always @(*) begin
result = 1'b0;
case (funct3)
`BR_BEQ: if (zf) result = 1'b1;
`BR_BNE: if (!zf) result = 1'b1;
... | 7.108586 |
module - all inputs and outputs must be "real" - that is,
// they need to come from somewhere, like the FPGA physical connections.
// Part of the job of the XDC file is to lay out what connections go to
// what names, and what sort of signal needs to be driven or accepted.
module BCUNXSMinerTop(
input wire SYSCL... | 6.524326 |
module bc_counter #(
parameter BITS = 12
) (
input wire CLK,
input wire RST,
output wire [BITS-1:0] BC
);
reg [BITS-1:0] BC_reg;
always @(posedge CLK) begin
if (RST) begin
BC_reg <= 0;
end else begin
BC_reg <= BC_reg + 1'b1;
end
end
assign BC = BC_reg;
endmodule
| 8.458587 |
module clk_div (
input clk,
output sclk
);
integer MAX_COUNT = 2200;
integer div_cnt = 0;
reg tmp_clk = 0;
always @(posedge clk) begin
if (div_cnt == MAX_COUNT) begin
tmp_clk = ~tmp_clk;
div_cnt = 0;
end else div_cnt = div_cnt + 1;
end
assign sclk = tmp_clk;
endmodule
| 7.520262 |
module clk_div2 (
input clk,
output disp_clk
);
integer MAX_COUNT = 10000000;
integer div_cnt = 0;
reg tmp_clk = 0;
always @(posedge clk) begin
if (div_cnt == MAX_COUNT) begin
tmp_clk = ~tmp_clk;
div_cnt = 0;
end else div_cnt = div_cnt + 1;
end
assign disp_clk = tmp_clk;
endmo... | 6.65618 |
module bc_fifo16x8(clk, wr, wa, ra, di, do);
input clk;
input wr;
input [3:0] wa, ra;
input [7:0] di;
output [7:0] do;
reg [7:0] mem [15:0];
always @(posedge clk) begin
if (wr)
mem[wa] <= di;
end
assign do = mem[ra];
endmodule
| 6.669506 |
module bc_mac_b4 (
input clk,
input rst_n,
input [3:0] act0,
input [3:0] act1,
input [3:0] act2,
input [3:0] act3,
input [3:0] act4,
input [3:0] act5,
input [3:0] act6,
input [3:0] act7,
input [7:0] weight,
input [5:0] yi,
input sft_en,
input sft_in,
input tru... | 6.82408 |
module adder4 (
input [3:0] in1,
input [3:0] in2,
input cin,
output [3:0] sum,
output cout
);
DW01_add #(4) I0 (
.A (in1),
.B (in2),
.CI (cin),
.SUM(sum),
.CO (cout)
);
endmodule
| 6.582965 |
module cprs_8_2 (
input [7:0] in,
input [4:0] yi,
output [1:0] out,
output [4:0] yo
);
wire I0_out, I1_out, I2_out, I3_out, I4_out;
wire I0_err, I1_err, I2_err, I3_err, I4_err;
cprs_4_2 I0 (
.in (in[7:4]),
.out({yo[0], I0_out}),
.err(I0_err)
);
cprs_4_2 I1 (
.in (in... | 6.871141 |
module cprs_3_2 (
in,
out
);
input [2:0] in;
output [1:0] out;
wire in0_xor_in1, in0_and_in1;
assign in0_xor_in1 = in[0] ^ in[1];
assign in0_and_in1 = in[0] & in[1];
assign out[1] = in0_xor_in1 & in[2] | in0_and_in1;
assign out[0] = in0_xor_in1 ^ in[2];
endmodule
| 6.841716 |
module cprs_4_2 (
in,
out,
err
);
input [3:0] in;
output [1:0] out;
output err;
wire in0_and_in1, in0_or_in1, in0_xor_in1;
assign in0_and_in1 = in[0] & in[1];
assign in0_or_in1 = in[0] | in[1];
assign in0_xor_in1 = in[0] ^ in[1];
wire in2_or_in3, in2_xor_in3;
assign in2_or_in3 = in[2]... | 7.077964 |
module group_pg (
input [3:0] in1,
input [3:0] in2,
input [3:0] gin,
output [3:0] gout
);
wire [3:0] carry_g, carry_p, carry;
assign carry_g = {in1[3] & in2[3], in1[2] & in2[2], in1[1] & in2[1], in1[0] & in2[0]};
assign carry_p = {in1[3] | in2[3], in1[2] | in2[2], in1[1] | in2[1], in1[0] | i... | 6.527222 |
module bc_mac_b4_trun (
input clk,
input rst_n,
input [3:0] act0,
input [3:0] act1,
input [3:0] act2,
input [3:0] act3,
input [3:0] act4,
input [3:0] act5,
input [3:0] act6,
input [3:0] act7,
input [7:0] weight,
input [5:0] yi,
input sft_en,
input sft_in,
inpu... | 7.204343 |
module adder4 (
input [3:0] in1,
input [3:0] in2,
input cin,
output [3:0] sum,
output cout
);
DW01_add #(4) I0 (
.A (in1),
.B (in2),
.CI (cin),
.SUM(sum),
.CO (cout)
);
endmodule
| 6.582965 |
module cprs_8_2 (
input [7:0] in,
input [4:0] yi,
output [1:0] out,
output [4:0] yo
);
wire I0_out, I1_out, I2_out, I3_out, I4_out;
wire I0_err, I1_err, I2_err, I3_err, I4_err;
cprs_4_2 I0 (
.in (in[7:4]),
.out({yo[0], I0_out}),
.err(I0_err)
);
cprs_4_2 I1 (
.in (in... | 6.871141 |
module cprs_3_2 (
in,
out
);
input [2:0] in;
output [1:0] out;
wire in0_xor_in1, in0_and_in1;
assign in0_xor_in1 = in[0] ^ in[1];
assign in0_and_in1 = in[0] & in[1];
assign out[1] = in0_xor_in1 & in[2] | in0_and_in1;
assign out[0] = in0_xor_in1 ^ in[2];
endmodule
| 6.841716 |
module cprs_4_2 (
in,
out,
err
);
input [3:0] in;
output [1:0] out;
output err;
wire in0_and_in1, in0_or_in1, in0_xor_in1;
assign in0_and_in1 = in[0] & in[1];
assign in0_or_in1 = in[0] | in[1];
assign in0_xor_in1 = in[0] ^ in[1];
wire in2_or_in3, in2_xor_in3;
assign in2_or_in3 = in[2]... | 7.077964 |
module group_pg (
input [3:0] in1,
input [3:0] in2,
input [3:0] gin,
output [3:0] gout
);
wire [3:0] carry_g, carry_p, carry;
assign carry_g = {in1[3] & in2[3], in1[2] & in2[2], in1[1] & in2[1], in1[0] & in2[0]};
assign carry_p = {in1[3] | in2[3], in1[2] | in2[2], in1[1] | in2[1], in1[0] | i... | 6.527222 |
module bc_uart(reset, clk, ce, cs, rd, wr, a, di, do, irq,
cts, rts, sin, sout);
input reset;
input clk; // eg 100.7MHz
input ce; // eg 25.175MHz enable
input cs; // circuit select
input rd; // 1 = read
input wr; // 1 = write
input [2:0] a; // register address
input [7:0] di; // data input bus
output [7:... | 6.871016 |
module bc_uart_tx (
reset,
clk,
baud16x_ce,
wr,
clear,
di,
sout,
full,
empty
);
input reset;
input clk;
input baud16x_ce; // baud rate clock enable
input wr; // write transmitter
input clear; // clear transmitter
input [7:0] di; // fifo data in
output sout; // exte... | 7.825002 |
module BD3 (
input INPT,
output OUTPT
);
assign #5 OUTPT = INPT;
endmodule
| 7.247055 |
module implements a complete brushed DC motor channel with 16 bit quadrature tach counter,
// tach filtering, tach phase inversion, 8 bit pwm with current limit, and pwm output polarity selection.
module bdcmotorchannel(
// Tach counter low byte
output [7:0] countl,
// Tach counter high byte
output [7:0] ... | 6.904081 |
module bdiff_image (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [0:0] data;
input [16:0] rdaddress;
input rdclock;
input [16:0] wraddress;
input wrclock;
input wren;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`i... | 6.763588 |
module bdiff_image (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [0:0] data;
input [16:0] rdaddress;
input rdclock;
input [16:0] wraddress;
input wrclock;
input wren;
output [0:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclo... | 6.763588 |
module BDR (
input CLK,
input [31:0] DataIn,
output reg [31:0] DataOut
);
always @(negedge CLK) DataOut <= DataIn;
endmodule
| 7.304538 |
module accepts transmitter data from the GMII style
// interface from the attached client MAC. At 1 Gbps, this
// GMII transmitter data will be valid on evey clock cycle
// of the 125MHz reference clock; at 100Mbps, this data
// will be repeated for a ten clock perio... | 8.196517 |
module bd_axis_custom_dct_wrapper (
aclk,
aresetn
);
input aclk;
input aresetn;
wire aclk;
wire aresetn;
bd_axis_custom_dct bd_axis_custom_dct_i (
.aclk(aclk),
.aresetn(aresetn)
);
endmodule
| 7.149217 |
module_ref:bootrom_wrapper:1.0
// IP Revision: 1
(* X_CORE_INFO = "bootrom_wrapper,Vivado 2019.2" *)
(* CHECK_LICENSE_TYPE = "BD_bootrom_wrapper_0_0,bootrom_wrapper,{}" *)
(* CORE_GENERATION_INFO = "BD_bootrom_wrapper_0_0,bootrom_wrapper,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=... | 7.182352 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// ... | 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//-----------------------------------------------... | 9.028271 |
module beacon_tb ();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable, bit_in;
wire bit_out, debit_out;
wire [6:0] state_out;
wire [6:0] destate_out;
//wire bit_out;
integer i, j;
reg [7:0] data[128:0];
reg [7:0] databyte;
// Initialize all variables
initial begin
$du... | 8.208077 |
module when building for development on the BeagleWire
// ICE40 development board. See beaglewire.pcf for information on what
// peripherals are used in this mode.
module top(
input clk_100M,
input reset,
output disp_clk,
output disp_hsync,
output disp_vsync,
output disp_de,
output [3:0] d... | 7.224168 |
module beam_tb;
reg clk;
reg reset;
integer cc;
reg trace;
`ifdef SIMULATE
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("beam.vcd");
$dumpvars(5, beam_tb);
end
trace = $test$plusargs("trace");
reset = 0;
$display("Non-checking testbench. Will always PASS");
fo... | 6.841491 |
module beatCounter (
clk,
startCounterEn,
reset,
process,
started,
pixelCounter
);
parameter INITCOUNT = 2'b00, COUNT0 = 2'b01, COUNT1 = 2'b10, //States for state machine.
MINPIXEL = 0,//MIN + MAX PIXEL start and stop position for pixel counter, counting through image,
MAXPIXEL = 255,... | 7.087684 |
module beatcounterTB ();
reg clk, startCounterEn;
wire process, started;
wire [19:0] pixelCounter;
beatCounter #(
.MINPIXEL(4),
.MAXPIXEL(128)
) beatCounterBlock (
clk,
startCounterEn,
process,
started,
pixelCounter
);
initial begin
clk = 1;
startCount... | 6.598338 |
module BEAT_Clock (
CLOCK_50,
BEAT_CLOCK,
BEAT_PRESCALER
);
input CLOCK_50;
input [4:0] BEAT_PRESCALER;
wire CLOCK_50;
output BEAT_CLOCK;
reg beat_clock;
reg [12:0] ticks;
parameter prescaler = 27'd500000;
wire [26:0] PRESCALER = prescaler;
initial begin
beat_clock = 0;
count =... | 6.858074 |
module beat_generator (
input clk,
input reset,
input en,
output wire beat
);
parameter WIDTH = 10;
parameter STOP = 1000;
wire [WIDTH-1:0] count;
dffre #(WIDTH) counter (
.clk(clk),
.en (en),
.r (reset | (count == STOP)),
.d (count + 1'b1),
.q (count)
);
a... | 7.93844 |
module BECtrl (
input [ 5:0] OP,
input [31:0] addr,
output reg [ 3:0] BE,
output reg [11:0] fakeAddr,
output reg MemReadSigned
);
always @(*) begin
fakeAddr = addr[11:0];
//$display("BECtrl: fakeAddr %b", fakeAddr[11:0]);
case (OP)
`OP_LBU, `OP_LHU: MemReadSigned = 0;
... | 7.118908 |
module bec_5 (
x,
y
);
input [4:0] x;
output [4:0] y;
assign y[0] = ~x[0];
assign y[1] = x[1] ^ x[0];
assign y[2] = x[2] ^ (x[1] & x[0]);
assign y[3] = x[3] ^ (x[2] & x[1] & x[0]);
assign y[4] = x[4] ^ (x[3] & x[2] & x[1] & x[0]);
endmodule
| 6.935618 |
module bec_6 (
x,
y
);
input [5:0] x;
output [5:0] y;
assign y[0] = ~x[0];
assign y[1] = x[1] ^ x[0];
assign y[2] = x[2] ^ (x[1] & x[0]);
assign y[3] = x[3] ^ (x[2] & x[1] & x[0]);
assign y[4] = x[4] ^ (x[3] & x[2] & x[1] & x[0]);
assign y[5] = x[5] ^ (x[4] & x[3] & x[2] & x[1] & x[0]);
endmo... | 6.590231 |
module beeb_accelerator_tb ();
reg clock = 'b0;
reg PhiIn = 'b0;
reg Res_n = 'b1;
wire [15:0] Addr;
wire [ 1:0] R_W_n;
wire [ 7:0] Data;
reg [ 7:0] ext_memory [0:65535];
reg [ 7:0] mem_out;
wire RnW = R_W_n[0];
wire Phi2Ou... | 6.523838 |
module fifo #(
parameter width = 1,
logsize = 6,
lut = 1
) (
input clk,
input [width-1:0] din,
input rd_en,
input rst,
input wr_en,
output [width-1:0] dout,
output empty,
output full
);
localparam SIZE = 1 << logsize;
reg [logsize-1:0] ra, wa, count;
assign full = (... | 8.01468 |
module d_line(//input
pulse_clk,
sys_rst_l,
Xe,
Ye,
change_readyH,
//output
X_acc,
Y_acc,
X_dec,
Y_dec,
draw_overH
);
module Beeline_DDA(pulse_clk,
sys_rst_l,
Xe,
Ye,
X_acc,
Y_acc,
X_dec,
Y_dec,
r_start);
input pulse_clk;
input sys_rst_l;
input [31:0] X... | 6.819986 |
module beep (
input wire clk,
output wire buzzer
);
// Variaveis: Contador e estado do buzzer
reg beep_r;
reg [27:0] count;
// Bloco always, executado nas bordas de subida do clock, que inplementa 'count'
always @(posedge clk) begin
// Incrementar 'count'
count <= count + 1'b1;
end
// B... | 7.542508 |
module beepdiv (
input inclk,
output outclk
);
reg [35:0] q;
initial q <= 36'b0;
always @(posedge inclk) q <= q + 1;
//beep
assign outclk = q[26]; //around 1Hz
endmodule
| 6.695405 |
module beeper #(
parameter t = 1,
parameter intensity = 50
) (
input clk,
input rst_n,
output reg beep
);
wire clkout;
frequency_divider #(intensity) fd (
clk,
rst_n,
clkout
);
//maximium cnt is 1048576 beeps
reg [19:0] cnt = 0;
parameter total = 2 * t * intensity;
... | 6.882218 |
module beep_clk (
input clk,
input rst_n,
input [2:0] pitch,
output reg output_clk
);
parameter clk_freq = 50_000_000 / 2;
localparam
c5 = clk_freq / 523,
d5 = clk_freq / 587,
e5 = clk_freq / 659,
f5 = clk_freq / 698,
g5 = clk_freq / 783,
a5 = clk_freq / 880,
b5 = clk_freq / 987,
a4 = clk_... | 6.799895 |
module beep_dirve (
input wire clk,
input wire rst_n,
input wire beep_vld,
input wire data_vld,
input wire [23:0] distance_data,
output reg beep
);
parameter MAX_DISTANCE = 20;
parameter MIN_DISTANCE = 10;
parameter MAX_TIME = 50_000_000;
reg [2... | 7.420197 |
module BeeSprite (
input wire [9:0] xx, // current x position
input wire [9:0] yy, // current y position
input wire aactive, // high during active pixel drawing
output reg BSpriteOn, // 1=on, 0=off
output wire [7:0] dataout, // 8 bit pixel value from Bee.mem
input wire BR, // right button
... | 6.626962 |
module for generating new item list
* List Format:
* At most 30 items in the list
* 0 - 9 : golds
* 10 - 19 ：stones
* 20 - 29 : diamonds
* For item n:
d[n << 5 + 31 : n << 5 + 19] >> 4 == left when drawing
d[n << 5 + 18 : n << 5 + 8] >> 4 == top
d... | 7.402579 |
module ItemMap(
clock,
resetn,
generateEn,
// quantity,
size,
data,
counter,
moveEn,
moveIndex,
moveX, //please multiple by << 4
moveY,
moveState,
visible,
);
parameter MAX_SIZE = 576; //576
input clock, resetn, generateEn;
// input [4:... | 6.706677 |
module before_car_enter (
input clk,
input rst,
input [4:0] bt_out,
input [2:0] view,
output reg [2:0] choose_parking,
output reg [2:0] state,
input [15:0] key_out
);
wire left_bt_in, right_bt_in, mid_bt_in;
assign left_bt_in = bt_out[1];
assign right_bt_in = bt_out[0];
assign mid_b... | 6.92177 |
module BeginLine (
DisLine,
FallLine,
start,
level,
clk,
Ascii,
h_addr,
ready,
led0,
clra,
w_addr
);
input [7:0] Ascii;
input [9:0] h_addr;
input [0:479] DisLine;
input clk;
input clra;
output reg [0:479] FallLine;
output reg ready;
output reg start;
output ... | 7.256828 |
module to see the flow of control in nested begin-end and
//>fork-join block.
module begin_end_fork_join (
);
reg x, y, a, b, p, m;
initial begin
x= 1'b0; $display($time,"x \n");
#5 y= 1'b1; $display($time,"y \n");
fork
#20 a=x;
#20 $display($time,"a \n");
#15 b=y;
... | 7.3835 |
module
module divide1(input X, input [1:0] Yin, output Z, output [1:0] f);
reg Z;
reg [2:0] out;
wire [2:0] Yout;
reg [1:0] f;
assign Yout[2:1]=Yin[1:0];
assign Yout[0]=X;
always@(*)
begin
out=Yout;
if(out>=3)
begin
Z=1;
out=out-3;
end
else
Z=0;
f=out[1:... | 7.587156 |
module
module divideN #(parameter integer WIDTH=4)
(input [WIDTH-1:0] X, input [1:0] in, output [WIDTH-1:0] Z, output [1:0] out);
wire [WIDTH-1:0] [1:0] Yin,Yout;
divide1 g1 [WIDTH-1:0] (X,Yin,Z,Yout);
assign Yin[WIDTH-1]=in;
assign Yin[WIDTH-2:0]=Yout[WIDTH-1:1];
assign out=Yout[0];
endmodule
| 7.587156 |
module tb;
parameter integer WIDTH = 6;
reg [WIDTH-1:0] X = 6'b0;
reg [1:0] in = 2'b0;
wire [WIDTH-1:0] Z;
wire [1:0] out;
divideN #(
.WIDTH(WIDTH)
) g1 (
X,
in,
Z,
out
);
initial begin
repeat (63) #15 X = X + 1;
end
initial $monitor("X=%d, quotient=%d, remainde... | 6.612288 |
module behave1p_mem #(
parameter width = 8,
parameter depth = 256,
parameter addr_sz = 8
) //log2(depth))
( /*AUTOARG*/
// Outputs
d_out,
// Inputs
wr_en,
rd_en,
clk,
d_in,
addr
);
input wr_en, rd_en, clk;
input [width-1:0] d_in;
input [addr_sz-1:0] addr;
outpu... | 7.24158 |
module behave2p_mem #(
parameter width = 8,
parameter depth = 256,
parameter addr_sz = $clog2(depth)
) ( /*AUTOARG*/
// Outputs
d_out,
// Inputs
wr_en,
rd_en,
wr_clk,
rd_clk,
d_in,
rd_addr,
wr_addr
);
input wr_en, rd_en, wr_clk;
input rd_clk;
input [width-1... | 7.03544 |
module HA (
a,
b,
sum,
carry
);
input a, b;
output sum, carry;
reg sum, carry;
always @(a or b) begin
sum = a ^ b; // ^ stands for XOR
carry = a & b; // & stands for AND
end
endmodule
| 7.123396 |
module FA (
x,
y,
c_in,
sum,
c_out
);
input x, y, c_in;
output sum, c_out;
reg sum, c_out;
wire a, b, c;
always @(x or y or c_in) begin
{c_out, sum} = x + y + c_in; //{cout , sum} 當作兩個 bits
end
endmodule
| 7.58914 |
module main (
input clock,
input reset,
input [7:0] a,
input [7:0] b,
output [7:0] y
);
assign y = a + b;
endmodule
| 7.081372 |
module main (
clock,
reset,
a,
b,
y
);
input clock;
input reset;
input [7:0] a;
input [7:0] b;
output [7:0] y;
wire [7:0] a;
wire [7:0] b;
wire [7:0] y;
wire \y[4]_INST_0_i_1_n_0 ;
wire \y[7]_INST_0_i_1_n_0 ;
wire \y[7]_INST_0_i_2_n_0 ;
LUT2 #(
.INIT(4'h6)
) \y[0]_I... | 7.779865 |
module main (
input clock,
input reset,
input [7:0] a,
input [7:0] b,
output [7:0] y
);
logic [7:0] r;
logic [7:0] s;
assign s = a + b;
always_ff @(posedge clock) begin
if (reset) begin
r <= 8'b0;
end else begin
r <= s;
end
end
assign y = r;
endmodule
| 7.081372 |
module main (
clock,
reset,
a,
b,
y
);
input clock;
input reset;
input [7:0] a;
input [7:0] b;
output [7:0] y;
wire \<const0> ;
wire \<const1> ;
wire GND_2;
wire [7:0] a;
wire [7:0] b;
wire clock;
wire \r[7]_i_2_n_0 ;
wire \r[7]_i_3_n_0 ;
wire \r[7]_i_4_n_0 ;
wire \r[7... | 7.779865 |
module mux_2to1(
input [1:0] in,
input sel,
output o,
);
always @(*) begin
if (sel)
o = in[0]; // blocking assignment
else
o = in[1];
end
endmodule
| 8.149822 |
module mux_4to1(
input [3:0] in, // Input Set: 2-bit wire
input [1:0] sel, // Select: 2-bit wire
output o, // 1-bit output
);
always @(*) begin
if (sel == 2'b00)
o = in[0];
else if (sel == 2'b01)
o = in[1];
else if (sel == 2'b10)
o = in[2];
else if (sel == 2'b11)... | 7.104041 |
module mux_4to1(
input [3:0] in, // Input Set: 4-bit wire
input [1:0] sel, // Select: 2-bit wire
output o, // 1-bit output
);
always @(*) begin
case(sel)
2'b00: o = in[0];
2'b01: o = in[1];
2'b10: o = in[2];
2'b11: o = in[3];
default: o = 1'bx; //... | 7.104041 |
module mux_4to1(
input [7:0] in, // Input Set @in: choose from 8 bits (bit 0-7)
input [2:0] sel, // Select @sel: 2^3 = 8 possible values
output o // Output @o: single bit from @in
);
// 2 muxes will output the option for the
wire msb_is_0, msb_is_1; // MSB of the bit number (0-7)
// this mux c... | 7.104041 |
module behavioral_adder (
input [7:0] a,
input [7:0] b,
output [8:0] sum
);
assign sum = a + b;
endmodule
| 7.284129 |
module behavioral_full_adder_64 (
input [63:0] A,
input [63:0] B,
output [64:0] SUM
);
assign SUM = (A + B);
endmodule
| 7.075084 |
module behavioral_full_adder_test;
// Inputs
reg [63:0] A;
reg [63:0] B;
// Outputs
wire [64:0] SUM;
// Instantiate two counter variables for the test loop
integer count;
integer count2;
// Instantiate the Unit Under Test (UUT)
behavioral_full_adder_64 uut (
.A (A),
.B (B),
.... | 7.075084 |
module buffer (
Y,
A
);
output Y;
input A;
assign Y = A;
endmodule
| 6.861394 |
module nand2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(A & B);
endmodule
| 9.113032 |
module nor2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(A | B);
endmodule
| 8.297456 |
module and2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = A & B;
endmodule
| 7.107954 |
module or2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = A | B;
endmodule
| 7.637076 |
module nand3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
assign Y = ~(A & B & C);
endmodule
| 8.175282 |
module nor3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
assign Y = ~(A | B | C);
endmodule
| 7.681855 |
module and3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
assign Y = A & B & C;
endmodule
| 6.818889 |
module or3 (
Y,
A,
B,
C
);
output Y;
input A, B, C;
assign Y = A | B | C;
endmodule
| 7.391653 |
module nand4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
assign Y = ~(A & B & C & D);
endmodule
| 8.989501 |
module nor4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
assign Y = ~(A | B | C | D);
endmodule
| 7.13519 |
module and4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
assign Y = A & B & C & D;
endmodule
| 7.001422 |
module or4 (
Y,
A,
B,
C,
D
);
output Y;
input A, B, C, D;
assign Y = A | B | C | D;
endmodule
| 7.381621 |
module nand2b (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(~A & B);
endmodule
| 6.603018 |
module nor2b (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(~A | B);
endmodule
| 6.703764 |
module aoi21 (
Y,
A0,
A1,
B0
);
output Y;
input A0, A1, B0;
assign Y = ~((A0 & A1) | B0);
endmodule
| 6.591789 |
module oai21 (
Y,
A0,
A1,
B0
);
output Y;
input A0, A1, B0;
assign Y = ~((A0 | A1) & B0);
endmodule
| 6.561625 |
module aoi22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0, A1, B0, B1;
assign Y = ~((A0 & A1) | (B0 & B1));
endmodule
| 6.668353 |
module oai22 (
Y,
A0,
A1,
B0,
B1
);
output Y;
input A0, A1, B0, B1;
assign Y = ~((A0 | A1) & (B0 | B1));
endmodule
| 6.579044 |
module xor2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = A ^ B;
endmodule
| 7.788927 |
module xnor2 (
Y,
A,
B
);
output Y;
input A, B;
assign Y = ~(A ^ B);
endmodule
| 6.713225 |
module mux2 (
Y,
S,
A,
B
);
output Y;
input S, A, B;
assign Y = S ? B : A;
endmodule
| 6.809767 |
module muxi2 (
Y,
S,
A,
B
);
output Y;
input S, A, B;
assign Y = ~(S ? B : A);
endmodule
| 7.147146 |
module behavioral_UART_tx //UART spoofer
#(
parameter bit_time = 104000
) // nanoseconds
(
output reg line
);
initial line = 1'b1; // line idles true
task send(input [7:0] data);
reg [9:0] uart_frame;
begin
// construct the whole frame with start and stop bit
// STOP data START
... | 7.785543 |
module runway_select (
d,
A,
B,
clk,
en,
signal
);
/********************************************
Inputs :
1) d-signifies direction of travel bits
00-East,10-West,01-South,11-North
2) Clock
3) Enable pin
Ouputs :
1) signal-signifies the output generated by
the curcuit
Other Variables:
... | 6.7696 |
module behaviorProcessor (
servo_en,
motor_en,
empty,
sipo_en,
piso_en,
sipo_done,
rd_en,
clk,
rst
);
input empty;
output reg rd_en;
input clk, rst;
output reg sipo_en;
input piso_en;
input sipo_done;
input servo_en, motor_en;
always @(posedge clk) begin
if (rst... | 6.554959 |
module behavior_model (
clk,
srstn,
load,
encrypt,
crypt_mode,
load_idx,
code_in,
code_out,
code_valid
);
input clk; //clock input
input srstn; //synchronous reset (active low)
input load; //load control signal (level sensitive). 0/1: inactive/active
//effecti... | 7.098337 |
module sn74151 (
P1,
P2,
P3,
P4,
P5,
P6,
P7,
P8,
P9,
P10,
P11,
P12,
P13,
P14,
P15,
P16
);
input wire P4, P3, P2, P1, P15, P14, P13, P12, P7, P11, P10, P9, P8, P16;
// I0 I1 I2 I3 I4 I5 I6 I7 E S0 S1 S2 GND VCC
output reg P... | 6.7752 |
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