code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module baud_of_verifla (
sys_clk,
sys_rst_l,
baud_clk_posedge
);
`include "config_verifla.v"
input sys_clk;
input sys_rst_l;
output baud_clk_posedge;
reg baud_clk;
reg baud_clk_posedge;
reg [BAUD_COUNTER_SIZE-1:0] counter = 0; //{BAUD_COUNTER_SIZE{1'b0}};
always @(posedge sys_clk or n... | 6.999396 |
module baud_rate #(
parameter FREQ_MHZ = 50, // 输入时钟(clk)频率（MHz）
parameter RATE_BPS = 9600, // 要产生的波特率（bps）
parameter CNT_WIDTH = 32 // 任意分频方式（每次递增INCREASE）的计数器最大位宽，越大则精度越高
) (
input wire clk,
input wire rst_n,
input wire start_en, // 有效(1)开始产生波特... | 7.193386 |
module baud_rate_gen (
input wire clk_50m,
output wire rxclk_en,
output wire txclk_en
);
parameter RX_ACC_MAX = 50000000 / (115200 * 16);
parameter TX_ACC_MAX = 50000000 / 115200;
parameter RX_ACC_WIDTH = $clog2(RX_ACC_MAX);
parameter TX_ACC_WIDTH = $clog2(TX_ACC_MAX);
reg [RX_ACC_WIDTH - 1:0] r... | 7.957018 |
module baud_rate_generator (
input clk_i,
input rst_i,
output tx_tick_o,
input [15:0] baud_div_i
);
reg tx_tick_o_r;
assign tx_tick_o = tx_tick_o_r;
wire [15:0] max_t_clock;
assign max_t_clock = baud_div_i;
reg [15:0] tx_counter;
always @(posedge clk_i) begin
... | 7.957018 |
module baud_rate_gen_tb ();
reg stm_clk, stm_rst, stm_sel_low, stm_sel_high;
reg [7:0] data;
wire en_mon;
baud_rate_gen baud0 (
.clk(stm_clk),
.rst(stm_rst),
.sel_low(stm_sel_low),
.sel_high(stm_sel_high),
.data(data),
.en(en_mon)
);
always begin
#5 stm_clk <= ~s... | 7.957018 |
module.
// -------------------------------------------------------------------
// NAME: baud rate stub
// TYPE: stub file
// -------------------------------------------------------------------
// PURPOSE: inputs and outputs declaration of baud rate module.
// ------------------------------------------------------------... | 7.355308 |
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 100000000; //100MHz
parameter Baud = 9600;
parameter Oversampling = 1;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end
endfunc... | 7.045903 |
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 100000000; //100MHz
parameter Baud = 9600;
parameter Oversampling = 1;
function integer log2(input integer v);
... | 7.045903 |
module baud_tx (
input wire clk,
input wire load,
output wire tx
);
//115200 baud
parameter BAUD = 104;
wire clk_baud;
//Generate a pulse to the specified baud frequency
divM #(BAUD) BAUD0 (
.clk_in (clk),
.clk_out(clk_baud)
);
//Holds the 10 bit value that we'll pass
reg [... | 7.709635 |
module baud_tx_cont (
input wire clk,
input wire load,
output wire tx
);
//115200
parameter BAUD = 104;
wire clk_baud;
divM #(BAUD) BAUD0 (
.clk_in (clk),
.clk_out(clk_baud)
);
reg [9:0] shifter;
always @(posedge clk_baud) begin
shifter <= (load == 0) ? {"K", 2'b01} : {s... | 7.294646 |
module HA (
s,
c,
a,
b
);
input a, b;
output s, c;
assign s = a ^ b;
assign c = a & b;
endmodule
| 7.846756 |
module FA (
sum,
car,
a,
b,
c
);
input a, b, c;
output sum, car;
assign sum = (a ^ b ^ c);
assign car = ((a & b) | (b & c) | (c & a));
endmodule
| 7.114161 |
module d_ff (
q,
d,
clk,
rst
);
input d, clk, rst;
output reg q;
always @(posedge clk) begin
if (rst == 1'b1) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module Bayer_LineBuffer #(
parameter VIDEO_W = 800
) (
aclr,
clken,
clock,
shiftin,
shiftout,
taps
);
input aclr;
input clken;
input clock;
input [11:0] shiftin;
output [11:0] shiftout;
output [35:0] taps;
wire [11:0] sub_wire0;
wire [35:0] sub_wire1;
wire [11:0] shiftout... | 7.030713 |
module BayertoRGB #(
parameter IM_X = 1280,
parameter IM_Y = 720
) (
input wire rst_n,
input wire clk,
input wire [7:0] raw_data,
input wire data_valid,
input wire out_ready,
output wire in_ready,
output reg [7:0] R,
G,
B,
output reg ... | 8.120816 |
module bayesian_coord (
clk,
rst,
nd,
us_rfd,
v1_x,
v1_y,
v2_x,
v2_y,
v3_x,
v3_y,
p_x,
p_y,
ds_rfd,
rdy,
b_u,
b_v,
b_w
);
input clk;
input rst;
input nd;
output us_rfd;
input [15:0] v1_x, v1_y;
input [15:0] v2_x, v2_y;
input [15:0] v3_x,... | 8.116874 |
module: bayesian_coord
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bayesian_coord_tb;
// Inputs
reg clk;
reg rst;
reg nd;
reg [15:0] v1_x;
reg [15:0] v1_y;
reg [15:0] v2_... | 6.649926 |
module BB4 (
A,
B,
cin,
z,
cout
);
input [3:0] A, B;
input cin;
output [3:0] z;
output cout;
assign {cout, z} = A + B + cin;
endmodule
| 7.147472 |
module tb;
reg in, rst, clk;
wire out;
fsm dut (
in,
rst,
clk,
out
);
always begin
#5 clk = 0;
#5 clk = 1;
end
initial begin
rst = 1'b1;
#15 rst = 1'b0;
repeat (600) begin
@(posedge clk); //check why only this delay is working and why not others
... | 6.904149 |
module tb;
reg in, rst, clk;
wire out;
fsm dut (
in,
rst,
clk,
out
);
always begin
#5 clk = 0;
#5 clk = 1;
end
initial begin
rst = 1'b1;
#15 rst = 1'b0;
repeat (600) begin
@(posedge clk); //check why only this delay is working and why not others
... | 6.904149 |
module LockingRRArbiter (
output io_in_0_ready,
input io_in_0_valid,
input [21:0] io_in_0_bits_address,
input [31:0] io_in_0_bits_data,
input [ 9:0] io_in_0_bits_taskID,
input io_out_ready,
output io_out_valid,
output [21:0] io_out_bits_address,
outpu... | 7.257641 |
module Demux (
input io_en,
input [31:0] io_input_data,
input [ 7:0] io_input_tag,
input io_sel,
output io_outputs_0_valid,
output [31:0] io_outputs_0_data,
output [ 7:0] io_outputs_0_tag,
output io_outputs_1_valid,
output [31:0] io_outputs_1_data,
... | 7.252853 |
module LockingRRArbiter_1 (
input clock,
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_RouteID,
input [31:0] io_in_0_bits_address,
input [ 9:0] io_in_0_bits_taskID,
input [ 7:0] io_in_0_bits_Typ,
output io_in_1_ready,
input ... | 7.257641 |
module Demux_3 (
input io_en,
input [15:0] io_input_RouteID,
input [31:0] io_input_data,
input io_sel,
output io_outputs_0_valid,
output [15:0] io_outputs_0_RouteID,
output [31:0] io_outputs_0_data,
output io_outputs_1_valid,
output [15:0] io_outputs_1... | 6.596027 |
module UALU (
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire [ 8:0] _T_21; // @[Alu.scala 108:45]
wire [542:0] _GEN_0; // @[Alu.scala 108:36]
wire [542:0] _T_22; // @[Alu.scala 108:36]
assign _T_21 = io_in2[8:0]; // @[Alu.scala 108:45]
assign _GEN_0 = {{511'd0}, io_... | 7.066942 |
module UALU_1 (
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire [32:0] _T_11; // @[Alu.scala 102:30]
assign _T_11 = io_in1 + io_in2; // @[Alu.scala 102:30]
assign io_out = io_in1 + io_in2; // @[Alu.scala 123:10]
endmodule
| 6.945381 |
module UCMP (
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire _T_11; // @[Comparision.scala 81:32]
assign _T_11 = io_in1 == io_in2; // @[Comparision.scala 81:32]
assign io_out = {{31'd0}, _T_11}; // @[Comparision.scala 90:10]
endmodule
| 7.424837 |
module UCMP_3 (
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire _T_15; // @[Comparision.scala 85:33]
assign _T_15 = io_in1 < io_in2; // @[Comparision.scala 85:33]
assign io_out = {{31'd0}, _T_15}; // @[Comparision.scala 90:10]
endmodule
| 7.192147 |
module bb_3X3 (
input clk,
input rst_n,
input [2:0] in1,
input [2:0] in2,
output [5:0] out
);
reg [5:0] out;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
out <= 6'b0;
end else begin
out <= in1 * in2;
end
end
endmodule
| 6.554004 |
module bb_c (
change,
forward,
forward1,
forward2,
back,
back1,
back2,
df,
df1,
df2
);
input change;
output forward;
output back;
output df;
input forward1;
input forward2;
input back1;
input back2;
input df1;
input df2;
assign forward = (!change) ? forw... | 7.693606 |
module bb_iq_generator #(
parameter DATA_SIZE = 7200, // i/q data size restore in BROM
parameter ADDR_WIDTH = 13 // addr width depends on DATA_SIZE
) (
input rst,
input clk,
(*mark_debug = "true"*) output reg [11:0] i_path,
(*mark_debug = "true"*) output reg [11:0] q_path
);
wire [ADDR_W... | 7.293523 |
module bb_new (
reset,
clkin,
load,
halfdata,
forward,
back,
dumpoff_ctrl
);
input clkin;
input reset;
input load;
input [5:0] halfdata;
output forward;
output back;
output dumpoff_ctrl;
reg forward;
reg back;
reg dumpoff_ctrl;
reg [5:0] half_reg;
reg [5:0] count;
... | 6.613683 |
module BB_SYSTEM (
//////////// OUTPUTS ////////////
BB_SYSTEM_MISO_Out,
BB_SYSTEM_newData_Out,
BB_SYSTEM_data_Out,
//////////// INPUTS ////////////
BB_SYSTEM_CLOCK_50,
BB_SYSTEM_RESET_InHigh,
BB_SYSTEM_SS_InLow,
BB_SYSTEM_MOSI_In,
BB_SYSTEM_SCK_In,
BB_SYSTEM_data_In
);
//... | 6.747229 |
module dp_group0 (
ir,
a_reg,
x_reg,
y_reg,
d,
ni,
vi,
zi,
ci,
n,
v,
z,
c
);
parameter DBW = 8;
input [DBW-1:0] ir;
input [DBW-1:0] a_reg;
input [DBW-1:0] x_reg;
input [DBW-1:0] y_reg;
input [DBW-1:0] d;
input ni, vi, zi, ci;
output n, v, z, c;
wire... | 6.819885 |
module dp_group2 (
ir,
ldx,
stxx,
d,
ci,
ni,
zi,
c,
n,
z,
o
);
parameter DBW = 8;
input [7:0] ir;
input ldx;
input stxx;
input [DBW-1:0] d;
input ci, ni, zi;
output c, n, z;
output [DBW-1:0] o;
reg [DBW-1:0] o;
reg sc; // shift carry
wire d_shift = ~ir... | 6.613757 |
module bc6502_tb();
reg clk;
reg reset;
reg nmi;
wire irq = 1'b0;
wire rdy = 1'b1;
wire sync;
wire rw;
tri [7:0] d;
wire [7:0] di, do;
wire [15:0] a;
initial begin
clk = 1;
reset = 0;
nmi = 0;
#100 reset = 1;
#100 reset = 0;
#1000 nmi = 1;
#1500 nmi = 0;
#2000 ... | 6.788351 |
module is a functional model, with no timing, and
is only suitable for simulation, not synthesis.
--------------------------------------------------------------- */
`timescale 1ns / 100ps
module rom8Kx8(ce, oe, addr, d);
input ce; // active low chip enable
input oe; // active low output enable
input [1... | 7.911783 |
module is a functional model, with no timing, and
is only suitable for simulation, not synthesis.
--------------------------------------------------------------- */
`timescale 1ns / 100ps
module ram32Kx8(clk, ce, oe, we, addr, d);
input clk;
input ce; // active low chip enable
input oe; // active l... | 7.911783 |
module bcache (
clock,
reset,
enable_bcache,
current_pc,
target_pc,
do_branch,
opcode,
do_flush_REG1,
xREG1_do_hit_bcache,
bcache_opc,
bcache_pc,
do_hit_bcache,
do_bcache
);
input clock;
input reset;
input enable_bcache;
input [31:0] current_pc;
input [31:0]... | 6.516888 |
module bcam_reg #(
parameter CDEP = 32, // CAM depth
parameter PWID = 32, // pattern width
parameter REGO = 1
) // register output
(
input clk, // clock
input rst, // global registers reset
input wEn, // write enable
input ... | 7.511239 |
module bcast_net #(
parameter BCAST_WIDTH = -1,
parameter N_NODES = -1,
parameter [8*N_NODES-1 : 0] NODES_CONF = 0
) (
input CLK,
input en,
// entry to the network
input [BCAST_WIDTH-1 : 0] in,
// output from nodes
output [N_NODES*BCAST_WIDTH-1 : 0] out
);
// Node #0 is the entry ... | 7.72818 |
module BCD_Counter (
input clk,
rst,
output [3:0] Q
);
jkfflop first (
1'b1,
1'b1,
clk,
rst,
Q[0]
);
jkfflop second (
~Q[3],
~Q[3],
Q[0],
rst,
Q[1]
);
jkfflop third (
1'b1,
1'b1,
Q[1],
rst,
Q[2]
);
jk... | 6.966103 |
module bcd_adder(sum,output_carry,addend,augend,carry_in);
output [3:0] sum; output output_carry; input [3:0] addend; input [3:0] augend; input carry_in;
wire [3:0] z_addend;
wire carry_out;
wire c_out;
wire [3:0] z_sum;
adder_4bit m0(carry_out,z_sum,addend,augend,carry_in);
and (w1,z_sum[3],z_sum[2]);
and (w2,z_sum[3... | 7.752773 |
module adder_4bit (
carry,
sum,
a,
b,
cin
);
output carry;
input [3:0] sum;
input [3:0] a, b;
input c_in;
assign {carry, sum} = a + b + cin;
endmodule
| 9.041993 |
module: CounterBCD
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BCD20counter_tb;
// Inputs
reg CLK;
reg LOAD;
reg CLR;
reg [3:0] DATA;
reg ENP;
reg ENT;
// Outputs
wire... | 6.85619 |
module BCD27SEG (
input [3:0] bcd_in,
output reg [6:0] seg_o
);
always @(bcd_in) begin //BCD to 7-segments decoder
case (bcd_in)
4'h0: seg_o <= 7'b0000001;
4'h1: seg_o <= 7'b1001111;
4'h2: seg_o <= 7'b0010010;
4'h3: seg_o <= 7'b0000110;
4'h4: seg_o <= 7'b1001100;
4'h5:... | 7.407344 |
module translate bcd number into ascii code.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: using Verilog-2001 syntax.
//
// The `timescale directive specifies what the
// simulation time units are (1 ns here) and what
// the simulator time step should be (1 ps her... | 6.785091 |
module bcd2bin (
input wire clk,
reset,
input wire start,
input wire [3:0] bcd1,
bcd0,
output reg ready,
done_tick,
output wire [6:0] bin
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, op = 2'b01, done = 2'b10;
// signal declaration
reg [1... | 6.700276 |
module bcd2bin_test (
input wire clk,
reset,
input wire btn,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] sseg,
output wire [7:0] led
);
// signal declaration
wire start;
wire [3:0] bcd1, bcd0;
assign bcd1 = sw[7:4];
assign bcd0 = sw[3:0];
// inst... | 7.56131 |
module bcd2sevenseg (
input [3:0] bcd,
output reg [6:0] seg
);
always @(bcd) begin
case (bcd)
0: seg <= 7'b1111110;
1: seg <= 7'b0110000;
2: seg <= 7'b1101101;
3: seg <= 7'b1111001;
4: seg <= 7'b0110011;
5: seg <= 7'b1011011;
6: seg <= 7'b1011111;
7: seg <= ... | 7.408274 |
module bcd2driver (
in,
out0,
out1,
gt99
);
input [6:0] in;
output [6:0] out0, out1;
output gt99;
reg [6:0] out0, out1;
reg gt99;
parameter ZERO = 7'b100_0000;
parameter ONE = 7'b111_1001;
parameter TWO = 7'b010_0100;
parameter THREE = 7'b011_0000;
parameter FOUR = 7'b001_1001;
... | 6.634004 |
module bcd2driverTOP (
//////////// CLOCK //////////
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
//////////// SEG7 //////////
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
//////////// ... | 6.752062 |
module for BCD to Gray Code Converter
module testbench;
reg [3:0] b;
wire [3:0] g;
bcd2gray_df bcd_df(b, g);
initial
begin
$monitor(,$time," b = %b, g = %b",b,g);
#5 b=4'b0000;
#5 b=4'b0001;
#5 b=4'b0010;
#5 b=4'b0011;
#5 b=4'b0100;
#5 b=4'b0101;
#5 b=4'b0110;
#5 b=4'b0111;
#5 b=... | 6.733174 |
module bcd2seg (
sin,
sout
);
input wire [3:0] sin;
output wire [6:0] sout;
assign sout = (sin==4'h0) ? 7'b0111111 :
(sin==4'h1) ? 7'b0000110 :
(sin==4'h2) ? 7'b1011011 :
(sin==4'h3) ? 7'b1001111 :
(sin==4'h4) ? 7'b1100110 :
(sin==4'h5... | 7.857628 |
module bcd2seg0_2 (
sin,
sout
);
input wire [1:0] sin;
output wire [6:0] sout;
reg [6:0] SEG_buf;
always @(sin) begin
case (sin)
2'h0: SEG_buf <= 7'b0111111;
2'h1: SEG_buf <= 7'b0000110;
2'h2: SEG_buf <= 7'b1011011;
default: SEG_buf <= 7'b0000000;
endcase
end
assign... | 7.307736 |
module bcd2seg0_5 (
sin,
sout
);
input wire [2:0] sin;
output wire [6:0] sout;
reg [6:0] SEG_buf;
always @(sin) begin
case (sin)
3'h0: SEG_buf <= 7'b0111111;
3'h1: SEG_buf <= 7'b0000110;
3'h2: SEG_buf <= 7'b1011011;
3'h3: SEG_buf <= 7'b1001111;
3'h4: SEG_buf <= 7'b1100... | 7.542989 |
module bcd2seg0_9 (
sin,
sout
);
input wire [3:0] sin;
output wire [6:0] sout;
reg [6:0] SEG_buf;
always @(sin) begin
case (sin)
4'h0: SEG_buf <= 7'b0111111;
4'h1: SEG_buf <= 7'b0000110;
4'h2: SEG_buf <= 7'b1011011;
4'h3: SEG_buf <= 7'b1001111;
4'h4: SEG_buf <= 7'b1100... | 6.727232 |
module.
module segment7(bcd, seg);
//Input and output signals.
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
// always block for a bcd to 7-segment convertor circuit
// It will generate a combination circuit for the conversion.
always @(bcd)
begin
case (bcd) //case... | 7.849566 |
module BCD2sevenSeg (
A,
B,
S,
C,
SEG_SEL,
SEG_DATA
);
input [1:0] A, B, S;
input C;
wire [3:0] out;
output [4:0] SEG_SEL;
output [7:0] SEG_DATA;
reg [7:0] SEG_DATA;
sevensegment_calculator res (
A,
B,
S,
C,
out
);
always @(out) begin
case (... | 7.088722 |
module bcd2seven_seg (
a,
b,
cin,
SEG_SEL,
SEG_DATA,
mux_out
);
input [1:0] a;
input [1:0] b;
input cin;
input [2:0] mux_out;
output [4:0] SEG_SEL;
output [7:0] SEG_DATA;
reg [7:0] SEG_DATA;
always @(mux_out) begin
case (mux_out)
0: SEG_DATA = 8'b00111111;
1: SE... | 6.591284 |
module BCD2SSD (
output reg [6:0] SSDOut, //% 7 segment display (G-A) output vector
input [3:0] BCDIn //% BCD number input
);
always @(BCDIn)
case (BCDIn)
4'h0: SSDOut <= 7'h3F;
4'h1: SSDOut <= 7'h06;
4'h2: SSDOut <= 7'h5B;
4'h3: SSDOut <= 7'h4F;
4'h4: SSDOut <= 7'h6... | 7.952828 |
module bcd2sseg (
output reg [6:0] sseg,
input [3:0] bcd
);
always @(bcd)
case (bcd)
// x: a b c d e f g
0: sseg = 7'b1111110;
1: sseg = 7'b0110000;
2: sseg = 7'b1101101;
3: sseg = 7'b1111001;
4: sseg = 7'b0110011;
5: sseg = 7'b1011011;
6: sseg = 7'b1011111... | 6.85487 |
module bcd2vga (
input [3:0] min0,
min1,
sec0,
sec1,
output reg [7:0] bcd1,
bcd2,
bcd3,
bcd4
);
parameter ZERO = 8'b00111111, //to display 0
ONE = 8'b00000110, //to display 1
TWO = 8'b01011011, //to display 2
THREE = 8'b01001111, //to display 3
FOUR = 8'b01100110, //to... | 6.728699 |
module BCD4bitsWreg (
input [3:0] dat1, //datos de entrada
input [3:0] dat2, //datos de entrada
input clk,
output [0:6] sseg, //salida para el sseg
output reg [3:0] an, //elige el display sseg
input rst
);
reg [3:0] bcd = 0;
BCDtoSSeg bcdtosseg (
.BCD (bcd),
.SSeg(sseg)
... | 7.374903 |
module: bcd4digit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bcd4digit_t;
// Inputs
reg clk;
reg rst;
reg [13:0] value;
reg start;
// Outputs
w... | 6.753391 |
module BCD7 (
digit,
cathodes
);
input [3:0] digit;
output reg [7:0] cathodes;
always @(*) begin
case (digit)
0: begin
cathodes <= 8'b0111_1110;
end
1: begin
cathodes <= 8'b0000_1100;
end
2: begin
cathodes <= 8'b1011_0110;
end
3: begin... | 6.622019 |
module BCD7segment (
input [3:0] IN,
input select,
output reg [6:0] OUT
);
always @(IN or select) begin
if (select) begin
case (IN)
0: OUT = 7'b0000001;
1: OUT = 7'b1001111;
2: OUT = 7'b0010010;
3: OUT = 7'b0000110;
4: OUT = 7'b1001100;
5: ... | 6.704488 |
module BCDA (
A,
B,
cin,
S,
cout_2
);
input [3:0] A, B;
input cin;
wire [3:0] Z, temp;
wire y, cout;
output [3:0] S;
output cout_2;
assign {y, Z} = A + B + cin;
assign cout = (Z[3] && Z[2]) || (Z[3] && Z[1]) || (y);
assign temp[0] = 0;
assign temp[1] = cout;
assign temp[2] =... | 7.224024 |
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] coutw;
bcd_fadd fadd1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.cout(coutw[0]),
.sum(sum[3:0])
);
genvar i;
generate
for (i = 1; i < 100; i = i + 1) begin : te... | 7.203305 |
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire [2:0] carry;
bcd_fadd u_bcd_fadd_1 (
a[3:0],
b[3:0],
cin,
carry[0],
sum[3:0]
);
bcd_fadd u_bcd_fadd_2 (
a[7:4],
b[7:4],
carry[0],
carry[1],
s... | 7.203305 |
module bcd_adder (
a,
b,
cin,
reset,
sum,
cout,
co
);
input [3:0] a, b;
input cin, reset;
output cout, co;
output [3:0] sum;
wire [3:0] v;
wire [2:0] w, c;
full_add fa1 (
v,
w[0],
a,
b,
cin
);
and a1 (w[1], v[2], v[3]);
and a2 (w[2], v[1], ... | 6.697199 |
module BCDandSEG (
Switch,
SEG
);
//输入端口
input [3:0] Switch;
//输出端口
output [8:0] SEG;
reg [8:0] SEGLED;
always @(Switch) begin
case (Switch)
4'b0000: SEGLED = 9'h3f;
4'b0001: SEGLED = 9'h06;
4'b0010: SEGLED = 9'h5b;
4'b0011: SEGLED = 9'h4f;
4'b0100: SEGLED = 9'h6... | 7.061282 |
module BCDcount (
Clock,
Reset,
Enable,
BCD1,
BCD0,
BCDCombine
);
input Clock, Reset, Enable;
output reg [3:0] BCD1, BCD0;
output reg [6:0] BCDCombine;
always @(posedge Clock) begin
if (Reset) begin
BCD1 <= 0;
BCD0 <= 0;
end else if (Enable)
if (BCD0 == 4'b1001... | 7.123108 |
module bcdCounter (
clkIn,
BCD
);
// Define inputs and outputs
input clkIn;
output reg [2:0] BCD;
reg [2:0] count;
initial begin
count = 0;
end
always @(posedge clkIn) begin
if (count < 6) begin
BCD <= count;
count <= count + 1;
end else begin
BCD <= 6;
... | 7.03096 |
module BCDCounter_mod10_tb;
parameter HALF_PERIOD = 0.5;
reg clk, clr, load, en;
reg [3:0] data;
wire [3:0] out;
wire tc, zero;
initial begin
clk = 0;
end
always #HALF_PERIOD clk = ~clk;
BCDCounter_mod10 ct_1 (
.clrn(clr),
.loadn(load),
.en(en),
.clk(clk),
.data(d... | 7.220593 |
module BCDCounter_mod10 (
input wire clrn,
loadn,
en,
clk,
input wire [3:0] data,
output reg [3:0] out,
output reg tc,
zero
);
reg [3:0] curr_state;
always @(posedge clk, negedge loadn, negedge clrn) begin
if (~clrn) begin
curr_state <= 0;
end else if (~loadn) begin
... | 7.220593 |
module BCDCounter_mod6_tb;
parameter HALF_PERIOD = 0.5;
reg clk, clr, load, en;
reg [3:0] data;
wire [3:0] out;
wire tc, zero;
initial begin
clk = 0;
end
always #HALF_PERIOD clk = ~clk;
BCDCounter_mod6 ct_1 (
.clrn(clr),
.loadn(load),
.en(en),
.clk(clk),
.data(dat... | 7.220593 |
module BCDCounter_mod6 (
input wire clrn,
loadn,
en,
clk,
input wire [3:0] data,
output reg [3:0] out,
output reg tc,
zero
);
reg [3:0] curr_state;
always @(posedge clk, negedge loadn, negedge clrn) begin
if (~clrn) begin
curr_state <= 0;
end else if (~loadn) begin
... | 7.220593 |
module BCDpara7segmentos (
input [3:0] bcd,
output a,
b,
c,
d,
e,
f,
g
);
reg [6:0] seteSegmentos;
assign {a, b, c, d, e, f, g} = seteSegmentos;
always @(*) begin
case (bcd)
4'b0000: seteSegmentos = 7'b0000001;
4'b0001: seteSegmentos = 7'b1001111;
4'b0010: ... | 7.338196 |
module: BCDto7cathod
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BCDto7cathod_tb;
// Inputs
reg [3:0] IN;
reg LAMP_TEST;
reg RBI;
// Outputs
wire a;
wire b;
wire c;
wi... | 6.624466 |
module BCDto7LED (
LED4,
LED3,
LED2,
LED1,
data,
en
);
output reg [6:0] LED4, LED3, LED2, LED1;
input [15:0] data;
input en;
reg [4:0] i;
always @(*) begin
if (!en) LED4 <= 7'b1111111; // No display
else
case (data[15:12])
4'b0000: LED4 <= 7'b0000001; // 0
... | 6.860618 |
module bcdto7seg (
input [3:0] bcd,
output reg [6:0] seg
);
always @(bcd) begin
case (bcd)
4'd0: seg <= 7'b1000000;
4'd1: seg <= 7'b1111001;
4'd2: seg <= 7'b0100100;
4'd3: seg <= 7'b0110000;
4'd4: seg <= 7'b0011001;
4'd5: seg <= 7'b0010010;
4'd6: seg <= 7'b000001... | 7.041565 |
module bcdto7segen (
bcd,
seg
);
input [9:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd) begin
case (bcd)
10'b1000000000: seg = 7'b1111110;
10'b0100000000: seg = 7'b0110000;
10'b0010000000: seg = 7'b1101101;
10'b0001000000: seg = 7'b1111001;
10'b0000100000: se... | 7.76346 |
module bcdto7segment (
bcd,
seg
);
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd) begin
case (bcd) //case statement
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
... | 7.120176 |
module bcdto7segment_dataflow (
input [3:0] x,
output reg [6:0] seg
);
always @(x) begin
case (x)
4'b0000: seg <= 7'b1000000;
4'b0001: seg <= 7'b1111001;
4'b0010: seg <= 7'b0100100;
4'b0011: seg <= 7'b0110000;
4'b0100: seg <= 7'b0011001;
4'b0101: seg <= 7'b0010010;
... | 7.120176 |
module bcdto7segment_tb;
reg [3:0] bcd;
wire [6:0] seg;
integer i;
// Instantiate the Unit Under Test (UUT)
bcdto7segment uut (
.bcd(bcd),
.seg(seg)
);
//Apply inputs
initial begin
for (
i = 0; i < 16; i = i + 1
) //run loop for 0 to 15.
begin
bcd = i;
... | 7.120176 |
module BCDto7SegsVHDL (
Entrada,
Saida
);
input [3:0] Entrada;
output reg [6:0] Saida;
always @(*) begin
case (Entrada)
4'b0000: Saida = 7'b0000001;
4'b0001: Saida = 7'b1001111;
4'b0010: Saida = 7'b0010010;
4'b0011: Saida = 7'b0000110;
4'b0100: Saida = 7'b1001100;
4... | 7.640758 |
module bcdto8segment_dataflow (
input [3:0] x,
output reg [7:0] seg
);
always @(x) begin
case (x)
4'b0000: seg <= 8'b11000000;
4'b0001: seg <= 8'b11111001;
4'b0010: seg <= 8'b10100100;
4'b0011: seg <= 8'b10110000;
4'b0100: seg <= 8'b10011001;
4'b0101: seg <= 8'b1001001... | 8.06751 |
module BCDtoDisplay (
In,
Out
);
input [3:0] In;
output reg [6:0] Out;
always @(*)
case (In)
4'b0000: Out = ~7'b0111111;
4'b0001: Out = ~7'b0000110;
4'b0010: Out = ~7'b1011011;
4'b0011: Out = ~7'b1001111;
4'b0100: Out = ~7'b1100110;
4'b0101: Out = ~7'b1101101;
... | 8.555888 |
module bcdToGray_beh (
Out,
In
);
input [3:0] In;
integer i;
output [3:0] Out;
reg [3:0] Out;
always @(In) begin
Out[3] = In[3];
for (i = 3; i > 0; i = i - 1) Out[i-1] = In[i] ^ In[i-1];
end
endmodule
| 6.888905 |
module bcdToGray_df (
Out,
In
);
input [3:0] In;
output [3:0] Out;
assign Out[3] = In[3];
//assign Out[2]=In[3]^In[2];
//assign Out[1]=In[2]^In[1];
//assign Out[0]=In[0]^In[1];
assign Out[2:0] = In[3:1] ^ In[2:0];
endmodule
| 6.589685 |
module bcdToGray_gate (
Out,
In
);
input [3:0] In;
output [3:0] Out;
buf b1 (Out[3], In[3]);
xor x1 (Out[2], In[3], In[2]);
xor x2 (Out[1], In[2], In[1]);
xor x3 (Out[0], In[1], In[0]);
endmodule
| 6.602988 |
module BCDToLED (
input [3:0] x, // binary input
output [6:0] seg // segments
//output [3:0] an // display specific anodes
);
//reg [6:0] seg;
assign seg[0] = x[2] & ~x[1] & ~x[0] | ~x[3] & ~x[2] & ~x[1] & x[0];
assign seg[1] = x[2] & ~x[1] & x[0] | x[2] & x[1] & ~x[0];
assign seg[2] = ~x[2] & x... | 7.007072 |
module BCDToSeg7_32bit (
input [31:0] bcd,
output reg [47:0] x
);
always @* begin
x[47:0] = 48'b0;
x[3:0] = bcd[3:0];
x[9:6] = bcd[7:4];
x[15:12] = bcd[11:8];
x[21:18] = bcd[15:12];
x[27:24] = bcd[19:16];
x[33:30] = bcd[23:20];
x[39:36] = bcd[27:24];
x[45:42] = bcd[31:... | 6.917862 |
module BCDToSeg7_8bit (
input [7:0] bcd,
output reg [11:0] x
);
always @* begin
x[11:0] = 12'b0;
x[3:0] = bcd[3:0];
x[9:6] = bcd[7:4];
end
endmodule
| 7.025009 |
module BCDtoSSeg (
BCD,
SSeg
);
input [3:0] BCD;
output reg [6:0] SSeg;
always @(*) begin
case (BCD)
4'b0000: SSeg = 7'b0000001; // "0"
4'b0001: SSeg = 7'b1001111; // "1"
4'b0010: SSeg = 7'b0010010; // "2"
4'b0011: SSeg = 7'b0000110; // "3"
4'b0100: SSeg = 7'b10... | 6.819202 |
module translate bcd word into ascii code.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: using Verilog-2001 syntax.
//
// The `timescale directive specifies what the
// simulation time units are (1 ns here) and what
// the simulator time step should be (1 ps here)... | 6.785091 |
module bcd_2_7seg (
data_in,
data_out
);
input [3:0] data_in;
output [6:0] data_out;
//secuence :a-b-c-d-e-f-g-h // pin plan to (MSB)HEX[0]-HEX[1]-HEX[2]-HEX[3]-HEX[4]-HEX[5]-HEX[6]-HEX[7](LSB)
assign data_out = (data_in == 4'b0000) ? 7'b1000000 : //0 segments
(data_in == 4'b0001) ? 7'b1111001... | 7.046268 |
module bcd_bit (
input wire [3:0] a,
b,
output wire [3:0] c,
input wire cin,
output wire cout
);
wire [4:0] t;
assign t = {1'b0, a} + {1'b0, b} + {4'b0, cin};
assign {cout, c} = (t > 5'd9) ? t + 5'd6 : t;
endmodule
| 7.027446 |
module bcd_adder (
input wire [11:0] a,
b,
output wire [11:0] c
);
wire [1:0] out;
bcd_bit bcd0 (
.a(a[3:0]),
.b(b[3:0]),
.c(c[3:0]),
.cin(1'b0),
.cout(out[0])
);
bcd_bit bcd1 (
.a(a[7:4]),
.b(b[7:4]),
.c(c[7:4]),
.cin(out[0]),
.cout(out[... | 6.697199 |
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