code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module baud_of_verifla (
sys_clk,
sys_rst_l,
baud_clk_posedge
);
`include "config_verifla.v"
input sys_clk;
input sys_rst_l;
output baud_clk_posedge;
reg baud_clk;
reg baud_clk_posedge;
reg [BAUD_COUNTER_SIZE-1:0] counter = 0; //{BAUD_COUNTER_SIZE{1'b0}};
always @(posedge sys_clk or negedge sys_rst_l) begin
if (~sys_rst_l) begin
baud_clk <= 0;
baud_clk_posedge <= 0;
counter <= 0;
end else if (counter < T2_div_T1_div_2) begin
counter <= counter + 1;
baud_clk <= baud_clk;
baud_clk_posedge <= 0;
end else begin
if (~baud_clk) // baud_clk will become 1
baud_clk_posedge <= 1;
counter <= 0;
baud_clk <= ~baud_clk;
end
end
/*
reg [2:0] baud_vec=3'b000;
always @(posedge clk) baud_vec = {baud_vec[1:0], baud_clk};
wire baud_clk_posedge=(baud_vec[2:1]=2'b01;
wire baud_clk_negedge=(baud_vec[2:1]=2'b10;
*/
endmodule
| 6.999396 |
module baud_rate #(
parameter FREQ_MHZ = 50, // 输入时钟(clk)频率（MHz）
parameter RATE_BPS = 9600, // 要产生的波特率（bps）
parameter CNT_WIDTH = 32 // 任意分频方式（每次递增INCREASE）的计数器最大位宽，越大则精度越高
) (
input wire clk,
input wire rst_n,
input wire start_en, // 有效(1)开始产生波特率
output wire rate_en // 输出波特率有效（用于采样或发送），一个时钟周期有效(1)
);
localparam INCREASE = (2**(CNT_WIDTH-2))/(10**4) * RATE_BPS/((FREQ_MHZ*10**2)/4); // 计数器每次递增值,计算的中间值也不能大于2**31(integer位32位有符号数)，所以CNT_WIDTH-2且FREQ_MHZ/4;另外先做除法在*RATE_BPS
// localparam INCREASE = 824634;
// localparam INCREASE = (2**(CNT_WIDTH-2))/(FREQ_MHZ/4)/(10**4) * RATE_BPS; // just for test
//**任意分频计数器
//**每次递增INCREASE计数器
reg [CNT_WIDTH-1:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
cnt <= #1{CNT_WIDTH{1'b0}};
end else begin
if(start_en == 1'b1) // 开始就一直循环计数
begin
cnt <= #1 cnt + INCREASE;
end else // 没有开始使能就归0等待开始
begin
cnt <= #1{CNT_WIDTH{1'b0}};
end
end
end
//**任意分频波形产生
//**由计数器产生的波特率相同频率的波形
reg div_clk;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
div_clk <= #1 1'b0;
end else begin
if(cnt < {1'b0,{(CNT_WIDTH-1){1'b1}}}) // 小于最大计数的1/2
begin
div_clk <= #1 1'b0;
end else begin
div_clk <= #1 1'b1;
end
end
end
//**分频后时钟上升沿采样
//**用于一周期波特率使能输出
reg div_clk_r;
assign rate_en = ((~div_clk_r) & div_clk);
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
div_clk_r <= #1 1'b0;
end else begin
div_clk_r <= #1 div_clk;
end
end
endmodule
| 7.193386 |
module baud_rate_gen (
input wire clk_50m,
output wire rxclk_en,
output wire txclk_en
);
parameter RX_ACC_MAX = 50000000 / (115200 * 16);
parameter TX_ACC_MAX = 50000000 / 115200;
parameter RX_ACC_WIDTH = $clog2(RX_ACC_MAX);
parameter TX_ACC_WIDTH = $clog2(TX_ACC_MAX);
reg [RX_ACC_WIDTH - 1:0] rx_acc = 0;
reg [TX_ACC_WIDTH - 1:0] tx_acc = 0;
assign rxclk_en = (rx_acc == 5'd0);
assign txclk_en = (tx_acc == 9'd0);
always @(posedge clk_50m) begin
if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH-1:0]) rx_acc <= 0;
else rx_acc <= rx_acc + 5'b1;
end
always @(posedge clk_50m) begin
if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH-1:0]) tx_acc <= 0;
else tx_acc <= tx_acc + 9'b1;
end
endmodule
| 7.957018 |
module baud_rate_generator (
input clk_i,
input rst_i,
output tx_tick_o,
input [15:0] baud_div_i
);
reg tx_tick_o_r;
assign tx_tick_o = tx_tick_o_r;
wire [15:0] max_t_clock;
assign max_t_clock = baud_div_i;
reg [15:0] tx_counter;
always @(posedge clk_i) begin
if (!rst_i) begin // rst_i == 0 ise resetlenecek
tx_counter <= 32'd0;
tx_tick_o_r <= 1'b0;
end else begin
// tx clock
if (tx_counter == (max_t_clock - 1'b1)) begin
tx_counter <= 32'd0;
tx_tick_o_r <= 1'b1;
end else if (tx_counter > (max_t_clock - 1'b1)) begin
tx_counter <= 32'd0;
tx_tick_o_r <= 1'b0;
end else begin
tx_counter <= tx_counter + 1'b1;
tx_tick_o_r <= 1'b0;
end
end
end
endmodule
| 7.957018 |
module baud_rate_gen_tb ();
reg stm_clk, stm_rst, stm_sel_low, stm_sel_high;
reg [7:0] data;
wire en_mon;
baud_rate_gen baud0 (
.clk(stm_clk),
.rst(stm_rst),
.sel_low(stm_sel_low),
.sel_high(stm_sel_high),
.data(data),
.en(en_mon)
);
always begin
#5 stm_clk <= ~stm_clk;
end
initial begin
stm_rst = 1;
stm_clk = 0;
stm_sel_low = 0;
stm_sel_high = 0;
data = 0;
@(posedge stm_clk);
stm_rst = 0;
stm_sel_low = 1;
data = 8'hc0;
@(posedge stm_clk);
stm_sel_low = 0;
stm_sel_high = 1;
data = 8'h12;
@(posedge stm_clk);
stm_sel_high = 0;
repeat (16) @(posedge en_mon);
$stop();
end
endmodule
| 7.957018 |
module.
// -------------------------------------------------------------------
// NAME: baud rate stub
// TYPE: stub file
// -------------------------------------------------------------------
// PURPOSE: inputs and outputs declaration of baud rate module.
// -------------------------------------------------------------------
// PARAMETERS
// PARAM_NAME : RANGE : DESCRIPTION : DEFAULT : UNITS :
// n.a. : n.a. : n.a. : n.a. : n.a. :
// -------------------------------------------------------------------
module baud_rate (
system_clk_i,
system_rst_i_b,
baud_rate_scon_sm0_i,
baud_rate_scon_sm1_i,
baud_rate_scon_sm2_i,
baud_rate_pcon_smod_i,
baud_rate_pcon_bps_i,
baud_rate_start_cm_i,
baud_rate_start_clean_counter_i,
baud_rate_cm_o,
baud_rate_br_trans_o,
baud_rate_br_o
);
input wire system_clk_i; // main system clock
input wire system_rst_i_b; // system reset
input wire baud_rate_scon_sm0_i; // serial mode
input wire baud_rate_scon_sm1_i; // communication rate in RS232 mode
input wire baud_rate_scon_sm2_i; // communication rate in RS232 mode
input wire baud_rate_pcon_smod_i; // baud rate duplicator
input wire baud_rate_pcon_bps_i; // RS232 mode
input wire baud_rate_start_cm_i; // start cycle machine
input wire baud_rate_start_clean_counter_i; // reset baud-rate in mode 2
output reg baud_rate_cm_o; // cycle machine output
output reg baud_rate_br_trans_o; // output baud rate 16 times faster of br output, in mode 2
output reg baud_rate_br_o; // output baud rate
endmodule
| 7.355308 |
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 100000000; //100MHz
parameter Baud = 9600;
parameter Oversampling = 1;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end
endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth));
// this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))...
...+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
| 7.045903 |
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 100000000; //100MHz
parameter Baud = 9600;
parameter Oversampling = 1;
function integer log2(input integer v);
begin log2=0;
while(v>>log2)
log2=log2+1;
end
endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth));
// this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))...
...+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk) if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0]; else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
| 7.045903 |
module baud_tx (
input wire clk,
input wire load,
output wire tx
);
//115200 baud
parameter BAUD = 104;
wire clk_baud;
//Generate a pulse to the specified baud frequency
divM #(BAUD) BAUD0 (
.clk_in (clk),
.clk_out(clk_baud)
);
//Holds the 10 bit value that we'll pass
reg [9:0] shifter;
always @(posedge clk_baud) begin
if (load == 0)
//Don't transmit. Set value to send (shifter) to "K" 01001011 + 01
shifter <= {
"K", 2'b01
};
else
//Transmission is activated. Shift to the left (leftmost bit to the first and shift the other 9 to left)
shifter <= {
shifter[0], shifter[9:1]
};
end
assign tx = (load) ? shifter[0] : 1;
endmodule
| 7.709635 |
module baud_tx_cont (
input wire clk,
input wire load,
output wire tx
);
//115200
parameter BAUD = 104;
wire clk_baud;
divM #(BAUD) BAUD0 (
.clk_in (clk),
.clk_out(clk_baud)
);
reg [9:0] shifter;
always @(posedge clk_baud) begin
shifter <= (load == 0) ? {"K", 2'b01} : {shifter[0], shifter[9:1]};
end
assign tx = (load) ? shifter[0] : 1;
endmodule
| 7.294646 |
module HA (
s,
c,
a,
b
);
input a, b;
output s, c;
assign s = a ^ b;
assign c = a & b;
endmodule
| 7.846756 |
module FA (
sum,
car,
a,
b,
c
);
input a, b, c;
output sum, car;
assign sum = (a ^ b ^ c);
assign car = ((a & b) | (b & c) | (c & a));
endmodule
| 7.114161 |
module d_ff (
q,
d,
clk,
rst
);
input d, clk, rst;
output reg q;
always @(posedge clk) begin
if (rst == 1'b1) q <= 1'b0;
else q <= d;
end
endmodule
| 7.310086 |
module Bayer_LineBuffer #(
parameter VIDEO_W = 800
) (
aclr,
clken,
clock,
shiftin,
shiftout,
taps
);
input aclr;
input clken;
input clock;
input [11:0] shiftin;
output [11:0] shiftout;
output [35:0] taps;
wire [11:0] sub_wire0;
wire [35:0] sub_wire1;
wire [11:0] shiftout = sub_wire0[11:0];
wire [35:0] taps = sub_wire1[35:0];
altshift_taps ALTSHIFT_TAPS_component (
.aclr(aclr),
.clock(clock),
.clken(clken),
.shiftin(shiftin),
.shiftout(sub_wire0),
.taps(sub_wire1)
);
defparam ALTSHIFT_TAPS_component.intended_device_family = "Cyclone IV E",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M4K", ALTSHIFT_TAPS_component.lpm_type =
"altshift_taps", ALTSHIFT_TAPS_component.number_of_taps = 3,
ALTSHIFT_TAPS_component.power_up_state = "CLEARED",
// ALTSHIFT_TAPS_component.tap_distance = 800,
ALTSHIFT_TAPS_component.tap_distance = VIDEO_W, // ##Lou mod
ALTSHIFT_TAPS_component.width = 12;
endmodule
| 7.030713 |
module BayertoRGB #(
parameter IM_X = 1280,
parameter IM_Y = 720
) (
input wire rst_n,
input wire clk,
input wire [7:0] raw_data,
input wire data_valid,
input wire out_ready,
output wire in_ready,
output reg [7:0] R,
G,
B,
output reg pixel_valid
);
localparam XBITS = $clog2(IM_X);
localparam YBITS = $clog2(IM_Y);
reg [XBITS - 1:0] cnt_x;
reg [YBITS - 1:0] cnt_y;
reg [15:0] firstline_px, secondline_px;
reg even_line, second_byte, start_proc;
reg [7:0] Red, Blue;
reg [8:0] Green;
wire [XBITS - 1:0] usedw;
wire fifo_full, fifo_empty;
wire [7:0] fifo_data;
wire last_row = (cnt_y == IM_Y - 0);
wire rd_fifo;
reg rd_fifo_r;
assign in_ready = !fifo_full;
always @(posedge clk or negedge rst_n)
if (!rst_n) cnt_x <= 0;
else if ((out_ready && data_valid) || last_row) cnt_x <= cnt_x + 1'b1;
else if (cnt_x == IM_X) cnt_x <= 0;
always @(posedge clk or negedge rst_n)
if (!rst_n) cnt_y <= 0;
else if ((cnt_x == IM_X - 0) && !fifo_empty) cnt_y <= cnt_y + 1'b1;
else if ((cnt_y == IM_Y - 0) && (!rd_fifo_r)) cnt_y <= 0;
//second line shift reg
always @(posedge clk or negedge rst_n)
if (!rst_n) secondline_px <= 0;
else if (out_ready && data_valid) begin
secondline_px[15:8] <= secondline_px[7:0];
secondline_px[7:0] <= last_row ? 0 : raw_data;
end
//pix buffer
raw_data_fifo #(
.ADDR_W(XBITS)
) raw_data_fifo_inst (
.clk(clk),
.rst_n(rst_n),
.rdreq(rd_fifo),
.wrreq(in_ready && out_ready && data_valid),
.data_in(raw_data),
.data_out(fifo_data),
.empty(fifo_empty),
.full(fifo_full),
.usedw(usedw)
);
//first line shift reg
always @(posedge clk or negedge rst_n)
if (!rst_n) firstline_px <= 0;
else if (rd_fifo_r) begin
firstline_px[15:8] <= firstline_px[7:0];
firstline_px[7:0] <= fifo_data;
end
//read fifo
assign rd_fifo = ((usedw == IM_X - 1) || (last_row && !fifo_empty));
always @(posedge clk or negedge rst_n)
if (!rst_n) rd_fifo_r <= 0;
else rd_fifo_r <= rd_fifo;
//processing
always @(posedge clk or negedge rst_n)
if (!rst_n) second_byte <= 0;
else if (start_proc) second_byte <= ~second_byte;
always @(posedge clk or negedge rst_n)
if (!rst_n) even_line <= 0;
else if (start_proc && ((cnt_x == IM_X - 0) || fifo_empty)) even_line <= ~even_line;
always @(posedge clk or negedge rst_n)
if (!rst_n) start_proc <= 0;
else if ((cnt_x == 'd1) && (usedw == IM_X - 1)) start_proc <= 1'b1;
else if (!rd_fifo && !last_row) start_proc <= 0;
always @(*) begin
case ({
even_line, second_byte
})
2'b00: begin
Blue = firstline_px[15:8];
Green = firstline_px[7:0] + secondline_px[15:8];
Red = secondline_px[7:0];
end
2'b01: begin
Blue = firstline_px[7:0];
Green = firstline_px[15:8] + secondline_px[7:0];
Red = secondline_px[15:8];
end
2'b10: begin
Blue = secondline_px[15:8];
Green = firstline_px[15:8] + secondline_px[7:0];
Red = firstline_px[7:0];
end
2'b11: begin
Blue = secondline_px[7:0];
Green = firstline_px[7:0] + secondline_px[15:8];
Red = firstline_px[15:8];
end
default: begin
Blue = 0;
Green = 0;
Red = 0;
end
endcase
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
R <= 0;
G <= 0;
B <= 0;
pixel_valid <= 0;
end else if (start_proc) begin
B <= Blue;
G <= Green[8:1];
R <= Red;
pixel_valid <= 1;
end else begin
B <= 0;
G <= 0;
R <= 0;
pixel_valid <= 0;
end
reg [15:0] val_cnt_x;
always @(posedge clk or negedge rst_n)
if (!rst_n) val_cnt_x <= 0;
else if (pixel_valid) val_cnt_x <= val_cnt_x + 1'b1;
else val_cnt_x <= 0;
reg [15:0] val_cnt_y;
always @(posedge clk or negedge rst_n)
if (!rst_n) val_cnt_y <= 0;
else if (val_cnt_x == IM_X - 1) val_cnt_y <= val_cnt_y + 1'b1;
endmodule
| 8.120816 |
module bayesian_coord (
clk,
rst,
nd,
us_rfd,
v1_x,
v1_y,
v2_x,
v2_y,
v3_x,
v3_y,
p_x,
p_y,
ds_rfd,
rdy,
b_u,
b_v,
b_w
);
input clk;
input rst;
input nd;
output us_rfd;
input [15:0] v1_x, v1_y;
input [15:0] v2_x, v2_y;
input [15:0] v3_x, v3_y;
input [15:0] p_x, p_y;
input ds_rfd;
output rdy;
output [15:0] b_u;
output [15:0] b_v;
output [15:0] b_w;
wire ta_a_rfd, ta_a_rdy;
wire [15:0] area_a;
wire ta_b_rfd, ta_b_rdy;
wire [15:0] area_b;
wire ta_c_rfd, ta_c_rdy;
wire [15:0] area_c;
wire sum_ab_rfd, sum_abc_rfd;
wire sum_ab_rdy, sum_abc_rdy;
triangle_area ta_a (
.clk(clk),
.rst(rst),
.nd(nd),
.us_rfd(ta_a_rfd),
.a_x(v3_x),
.a_y(v3_y),
.b_x(v2_x),
.b_y(v2_y),
.p_x(p_x),
.p_y(p_y),
.ds_rfd(sum_ab_rfd),
.rdy(ta_a_rdy),
.area(area_a)
);
triangle_area ta_b (
.clk(clk),
.rst(rst),
.nd(nd),
.us_rfd(ta_b_rfd),
.a_x(v1_x),
.a_y(v1_y),
.b_x(v3_x),
.b_y(v3_y),
.p_x(p_x),
.p_y(p_y),
.ds_rfd(sum_ab_rfd),
.rdy(ta_b_rdy),
.area(area_b)
);
triangle_area ta_c (
.clk(clk),
.rst(rst),
.nd(nd),
.us_rfd(ta_c_rfd),
.a_x(v2_x),
.a_y(v2_y),
.b_x(v1_x),
.b_y(v1_y),
.p_x(p_x),
.p_y(p_y),
.ds_rfd(sum_ab_rfd),
.rdy(ta_c_rdy),
.area(area_c)
);
// Delay for 1st level
reg [15:0] area_a2, area_b2, area_c2;
wire [15:0] abs_area_a = {1'b0, area_a[14:0]};
wire [15:0] abs_area_b = {1'b0, area_b[14:0]};
wire [15:0] abs_area_c = {1'b0, area_c[14:0]};
always @(posedge clk) begin
if (rst) begin
area_a2 <= 0;
area_b2 <= 0;
area_c2 <= 0;
end else begin
area_a2 <= abs_area_a;
area_b2 <= abs_area_b;
area_c2 <= abs_area_c;
end
end
// Sum all areas
wire [15:0] sum_ab, sum_abc;
fp_add_micro add_ab (
.a(abs_area_a),
.b(abs_area_b),
.operation_nd(ta_a_rdy & ta_b_rdy),
.operation_rfd(sum_ab_rfd),
.clk(clk),
.sclr(rst),
.ce(sum_abc_rfd),
.result(sum_ab),
.rdy(sum_ab_rdy)
);
fp_add_micro add_abc (
.a(sum_ab),
.b(abs_area_c),
.operation_nd(sum_ab_rdy),
.operation_rfd(sum_abc_rfd),
.clk(clk),
.sclr(rst),
.ce(div_u_rdy | div_v_rdy | div_w_rdy),
.result(sum_abc),
.rdy(sum_abc_rdy)
);
// Normalize areas
fp_div_micro div_u (
.a(area_a2),
.b(sum_abc),
.operation_nd(sum_abc_rdy),
.operation_rfd(div_u_rdy),
.clk(clk),
.sclr(rst),
.ce(ds_rfd),
.result(b_u),
.rdy(u_rdy)
);
fp_div_micro div_v (
.a(area_b2),
.b(sum_abc),
.operation_nd(sum_abc_rdy),
.operation_rfd(div_v_rdy),
.clk(clk),
.sclr(rst),
.ce(ds_rfd),
.result(b_v),
.rdy(v_rdy)
);
fp_div_micro div_w (
.a(area_c2),
.b(sum_abc),
.operation_nd(sum_abc_rdy),
.operation_rfd(div_w_rdy),
.clk(clk),
.sclr(rst),
.ce(ds_rfd),
.result(b_w),
.rdy(w_rdy)
);
assign us_rfd = ta_a_rfd & ta_b_rfd & ta_c_rfd;
assign rdy = u_rdy & v_rdy & w_rdy;
endmodule
| 8.116874 |
module: bayesian_coord
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bayesian_coord_tb;
// Inputs
reg clk;
reg rst;
reg nd;
reg [15:0] v1_x;
reg [15:0] v1_y;
reg [15:0] v2_x;
reg [15:0] v2_y;
reg [15:0] v3_x;
reg [15:0] v3_y;
reg [15:0] p_x;
reg [15:0] p_y;
reg ds_rfd;
// Outputs
wire us_rfd;
wire rdy;
wire [15:0] b_u;
wire [15:0] b_v;
wire [15:0] b_w;
// Instantiate the Unit Under Test (UUT)
bayesian_coord uut (
.clk(clk),
.rst(rst),
.nd(nd),
.us_rfd(us_rfd),
.v1_x(v1_x),
.v1_y(v1_y),
.v2_x(v2_x),
.v2_y(v2_y),
.v3_x(v3_x),
.v3_y(v3_y),
.p_x(p_x),
.p_y(p_y),
.ds_rfd(ds_rfd),
.rdy(rdy),
.b_u(b_u),
.b_v(b_v),
.b_w(b_w)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
nd = 0;
v1_x = 0;
v1_y = 0;
v2_x = 0;
v2_y = 0;
v3_x = 0;
v3_y = 0;
p_x = 0;
p_y = 0;
ds_rfd = 0;
// Wait 100 ns for global reset to finish
#100;
repeat(4)
#5 clk = ~clk;
rst = 0;
forever
#5 clk = ~clk;
end
initial begin
#120;
ds_rfd = 1'b1;
#80;
nd = 1'b1;
v1_x = 16'h0000; // 0.0
v1_y = 16'h3C00; // 1.0
v2_x = 16'h0000; // 0.0
v2_y = 16'h0000; // 0.0
v3_x = 16'h3C00; // 1.0
v3_y = 16'h0000; // 0.0
p_x = 16'h3800; // 0.5
p_y = 16'h3400; // 0.25
#10;
nd = 1'b0;
#10;
nd = 1'b1;
v1_x = 16'h0000; // 0.0
v1_y = 16'h3C00; // 1.0
v2_x = 16'h0000; // 0.0
v2_y = 16'h0000; // 0.0
v3_x = 16'h3C00; // 1.0
v3_y = 16'h0000; // 0.0
p_x = 16'hB800; // -0.5
p_y = 16'h3400; // 0.25
#10;
nd = 1'b0;
#200;
$finish;
end
endmodule
| 6.649926 |
module BB4 (
A,
B,
cin,
z,
cout
);
input [3:0] A, B;
input cin;
output [3:0] z;
output cout;
assign {cout, z} = A + B + cin;
endmodule
| 7.147472 |
module tb;
reg in, rst, clk;
wire out;
fsm dut (
in,
rst,
clk,
out
);
always begin
#5 clk = 0;
#5 clk = 1;
end
initial begin
rst = 1'b1;
#15 rst = 1'b0;
repeat (600) begin
@(posedge clk); //check why only this delay is working and why not others
in = $random;
end
#50;
$finish;
end
initial begin
$dumpfile("1.vcd");
$dumpvars();
end
endmodule
| 6.904149 |
module tb;
reg in, rst, clk;
wire out;
fsm dut (
in,
rst,
clk,
out
);
always begin
#5 clk = 0;
#5 clk = 1;
end
initial begin
rst = 1'b1;
#15 rst = 1'b0;
repeat (600) begin
@(posedge clk); //check why only this delay is working and why not others
in = $random;
end
#50;
$finish;
end
initial begin
$dumpfile("1.vcd");
$dumpvars();
end
endmodule
| 6.904149 |
module LockingRRArbiter (
output io_in_0_ready,
input io_in_0_valid,
input [21:0] io_in_0_bits_address,
input [31:0] io_in_0_bits_data,
input [ 9:0] io_in_0_bits_taskID,
input io_out_ready,
output io_out_valid,
output [21:0] io_out_bits_address,
output [31:0] io_out_bits_data,
output [ 9:0] io_out_bits_taskID,
output [ 7:0] io_out_bits_Typ,
output io_chosen
);
assign io_in_0_ready = io_out_ready; // @[Arbiter.scala 60:16]
assign io_out_valid = io_chosen ? 1'h0 : io_in_0_valid; // @[Arbiter.scala 41:16]
assign io_out_bits_address = io_chosen ? 22'h0 : io_in_0_bits_address; // @[Arbiter.scala 42:15]
assign io_out_bits_data = io_chosen ? 32'h0 : io_in_0_bits_data; // @[Arbiter.scala 42:15]
assign io_out_bits_taskID = io_chosen ? 10'h0 : io_in_0_bits_taskID; // @[Arbiter.scala 42:15]
assign io_out_bits_Typ = io_chosen ? 8'h0 : 8'h3; // @[Arbiter.scala 42:15]
assign io_chosen = io_in_0_valid ? 1'h0 : 1'h1; // @[Arbiter.scala 40:13]
endmodule
| 7.257641 |
module Demux (
input io_en,
input [31:0] io_input_data,
input [ 7:0] io_input_tag,
input io_sel,
output io_outputs_0_valid,
output [31:0] io_outputs_0_data,
output [ 7:0] io_outputs_0_tag,
output io_outputs_1_valid,
output [31:0] io_outputs_1_data,
output [ 7:0] io_outputs_1_tag
);
wire _GEN_0; // @[Muxes.scala 29:25]
assign _GEN_0 = 1'h0 == io_sel; // @[Muxes.scala 29:25]
assign io_outputs_0_valid = io_en ? _GEN_0 : 1'h0; // @[Muxes.scala 23:19 Muxes.scala 27:27 Muxes.scala 29:25 Muxes.scala 32:27]
assign io_outputs_0_data = io_input_data; // @[Muxes.scala 23:19]
assign io_outputs_0_tag = io_input_tag; // @[Muxes.scala 23:19]
assign io_outputs_1_valid = io_en ? io_sel : 1'h0; // @[Muxes.scala 23:19 Muxes.scala 27:27 Muxes.scala 29:25 Muxes.scala 32:27]
assign io_outputs_1_data = io_input_data; // @[Muxes.scala 23:19]
assign io_outputs_1_tag = io_input_tag; // @[Muxes.scala 23:19]
endmodule
| 7.252853 |
module LockingRRArbiter_1 (
input clock,
output io_in_0_ready,
input io_in_0_valid,
input [15:0] io_in_0_bits_RouteID,
input [31:0] io_in_0_bits_address,
input [ 9:0] io_in_0_bits_taskID,
input [ 7:0] io_in_0_bits_Typ,
output io_in_1_ready,
input io_in_1_valid,
input [15:0] io_in_1_bits_RouteID,
input [31:0] io_in_1_bits_address,
input [ 9:0] io_in_1_bits_taskID,
input [ 7:0] io_in_1_bits_Typ,
input io_out_ready,
output io_out_valid,
output [15:0] io_out_bits_RouteID,
output [31:0] io_out_bits_address,
output [ 9:0] io_out_bits_taskID,
output [ 7:0] io_out_bits_Typ,
output io_chosen
);
wire _T_79; // @[Decoupled.scala 37:37]
reg _T_81; // @[Reg.scala 11:16]
reg [31:0] _RAND_0;
wire _T_84; // @[Arbiter.scala 67:57]
wire _T_86; // @[Arbiter.scala 68:83]
wire _T_89; // @[Arbiter.scala 31:68]
wire _T_93; // @[Arbiter.scala 31:78]
wire _T_95; // @[Arbiter.scala 31:78]
wire _T_99; // @[Arbiter.scala 72:50]
wire _GEN_13; // @[Arbiter.scala 77:27]
assign _T_79 = io_out_ready & io_out_valid; // @[Decoupled.scala 37:37]
assign _T_84 = 1'h1 > _T_81; // @[Arbiter.scala 67:57]
assign _T_86 = io_in_1_valid & _T_84; // @[Arbiter.scala 68:83]
assign _T_89 = _T_86 | io_in_0_valid; // @[Arbiter.scala 31:68]
assign _T_93 = _T_86 == 1'h0; // @[Arbiter.scala 31:78]
assign _T_95 = _T_89 == 1'h0; // @[Arbiter.scala 31:78]
assign _T_99 = _T_84 | _T_95; // @[Arbiter.scala 72:50]
assign _GEN_13 = io_in_0_valid ? 1'h0 : 1'h1; // @[Arbiter.scala 77:27]
assign io_in_0_ready = _T_93 & io_out_ready; // @[Arbiter.scala 60:16]
assign io_in_1_ready = _T_99 & io_out_ready; // @[Arbiter.scala 60:16]
assign io_out_valid = io_chosen ? io_in_1_valid : io_in_0_valid; // @[Arbiter.scala 41:16]
assign io_out_bits_RouteID = io_chosen ? io_in_1_bits_RouteID : io_in_0_bits_RouteID; // @[Arbiter.scala 42:15]
assign io_out_bits_address = io_chosen ? io_in_1_bits_address : io_in_0_bits_address; // @[Arbiter.scala 42:15]
assign io_out_bits_taskID = io_chosen ? io_in_1_bits_taskID : io_in_0_bits_taskID; // @[Arbiter.scala 42:15]
assign io_out_bits_Typ = io_chosen ? io_in_1_bits_Typ : io_in_0_bits_Typ; // @[Arbiter.scala 42:15]
assign io_chosen = _T_86 ? 1'h1 : _GEN_13; // @[Arbiter.scala 40:13]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE
integer initvar;
initial begin
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
#0.002 begin
end
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_81 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
end
`endif // RANDOMIZE
always @(posedge clock) begin
if (_T_79) begin
_T_81 <= io_chosen;
end
end
endmodule
| 7.257641 |
module Demux_3 (
input io_en,
input [15:0] io_input_RouteID,
input [31:0] io_input_data,
input io_sel,
output io_outputs_0_valid,
output [15:0] io_outputs_0_RouteID,
output [31:0] io_outputs_0_data,
output io_outputs_1_valid,
output [15:0] io_outputs_1_RouteID,
output [31:0] io_outputs_1_data
);
wire _GEN_0; // @[Muxes.scala 29:25]
assign _GEN_0 = 1'h0 == io_sel; // @[Muxes.scala 29:25]
assign io_outputs_0_valid = io_en ? _GEN_0 : 1'h0; // @[Muxes.scala 23:19 Muxes.scala 27:27 Muxes.scala 29:25 Muxes.scala 32:27]
assign io_outputs_0_RouteID = io_input_RouteID; // @[Muxes.scala 23:19]
assign io_outputs_0_data = io_input_data; // @[Muxes.scala 23:19]
assign io_outputs_1_valid = io_en ? io_sel : 1'h0; // @[Muxes.scala 23:19 Muxes.scala 27:27 Muxes.scala 29:25 Muxes.scala 32:27]
assign io_outputs_1_RouteID = io_input_RouteID; // @[Muxes.scala 23:19]
assign io_outputs_1_data = io_input_data; // @[Muxes.scala 23:19]
endmodule
| 6.596027 |
module UALU (
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire [ 8:0] _T_21; // @[Alu.scala 108:45]
wire [542:0] _GEN_0; // @[Alu.scala 108:36]
wire [542:0] _T_22; // @[Alu.scala 108:36]
assign _T_21 = io_in2[8:0]; // @[Alu.scala 108:45]
assign _GEN_0 = {{511'd0}, io_in1}; // @[Alu.scala 108:36]
assign _T_22 = _GEN_0 << _T_21; // @[Alu.scala 108:36]
assign io_out = _T_22[31:0]; // @[Alu.scala 123:10]
endmodule
| 7.066942 |
module UALU_1 (
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire [32:0] _T_11; // @[Alu.scala 102:30]
assign _T_11 = io_in1 + io_in2; // @[Alu.scala 102:30]
assign io_out = io_in1 + io_in2; // @[Alu.scala 123:10]
endmodule
| 6.945381 |
module UCMP (
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire _T_11; // @[Comparision.scala 81:32]
assign _T_11 = io_in1 == io_in2; // @[Comparision.scala 81:32]
assign io_out = {{31'd0}, _T_11}; // @[Comparision.scala 90:10]
endmodule
| 7.424837 |
module UCMP_3 (
input [31:0] io_in1,
input [31:0] io_in2,
output [31:0] io_out
);
wire _T_15; // @[Comparision.scala 85:33]
assign _T_15 = io_in1 < io_in2; // @[Comparision.scala 85:33]
assign io_out = {{31'd0}, _T_15}; // @[Comparision.scala 90:10]
endmodule
| 7.192147 |
module bb_3X3 (
input clk,
input rst_n,
input [2:0] in1,
input [2:0] in2,
output [5:0] out
);
reg [5:0] out;
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
out <= 6'b0;
end else begin
out <= in1 * in2;
end
end
endmodule
| 6.554004 |
module bb_c (
change,
forward,
forward1,
forward2,
back,
back1,
back2,
df,
df1,
df2
);
input change;
output forward;
output back;
output df;
input forward1;
input forward2;
input back1;
input back2;
input df1;
input df2;
assign forward = (!change) ? forward1 : forward2;
assign back = (!change) ? back1 : back2;
assign df = (!change) ? df1 : df2;
endmodule
| 7.693606 |
module bb_iq_generator #(
parameter DATA_SIZE = 7200, // i/q data size restore in BROM
parameter ADDR_WIDTH = 13 // addr width depends on DATA_SIZE
) (
input rst,
input clk,
(*mark_debug = "true"*) output reg [11:0] i_path,
(*mark_debug = "true"*) output reg [11:0] q_path
);
wire [ADDR_WIDTH-1:0] addra;
reg [ADDR_WIDTH-1:0] addr;
wire [ 11:0] dout_i;
wire [ 11:0] dout_q;
assign addra = addr;
ipath_generator i_path_inst (
.clka (clk), // input wire clka
.rsta (rst), // input wire rsta
.addra(addra), // input wire [ADDR_WIDTH-1 : 0] addra
.douta(dout_i) // output wire [ADDR_WIDTH-1 : 0] douta
);
qpath_generator q_path_inst (
.clka (clk), // input wire clka
.rsta (rst), // input wire rsta
.addra(addra), // input wire [ADDR_WIDTH-1 : 0] addra
.douta(dout_q) // output wire [ADDR_WIDTH-1 : 0] douta
);
integer delay_cnt;
/*build addr timing*/
always @(posedge clk) begin
if (rst) begin
addr <= 0;
delay_cnt <= 0;
end else begin
if (delay_cnt == 0 && addr != DATA_SIZE - 1) begin
addr <= addr + 1;
delay_cnt <= delay_cnt + 1;
end else if (delay_cnt == 1) begin
delay_cnt <= 0;
end else begin
addr <= 0;
end
end
end
always @(posedge clk) begin
if (rst) begin
i_path <= 0;
q_path <= 0;
end else begin
i_path <= dout_i;
q_path <= dout_q;
end
end
endmodule
| 7.293523 |
module bb_new (
reset,
clkin,
load,
halfdata,
forward,
back,
dumpoff_ctrl
);
input clkin;
input reset;
input load;
input [5:0] halfdata;
output forward;
output back;
output dumpoff_ctrl;
reg forward;
reg back;
reg dumpoff_ctrl;
reg [5:0] half_reg;
reg [5:0] count;
always @(posedge load) begin
half_reg <= halfdata;
end
always @(posedge reset or posedge clkin) begin
if (reset) begin
count <= 0;
forward <= 0;
back <= 0;
dumpoff_ctrl <= 0;
end else begin
if (count == 0) begin
count <= count + 1;
end else begin
if (count <= half_reg) begin
count <= count + 1;
if (count % 8 == 1) begin
forward <= 1;
back <= 0;
end else if (count % 8 == 3) begin
forward <= 0;
end else if (count % 8 == 7) begin
back <= 1;
dumpoff_ctrl <= 0;
end else if (count % 8 == 5) begin
if (count == 5) begin
dumpoff_ctrl <= 1;
end
end
end else begin
if (count == half_reg + 1) begin
forward <= 1;
back <= 0;
count <= half_reg + 2;
end else if (count == half_reg + 2) begin
forward <= 0;
count <= half_reg + 3;
end else if (count == half_reg + 3) begin
back <= 1;
count <= half_reg + 4;
end else if (count == half_reg + 4) begin
back <= 0;
count <= half_reg + 1;
end
end
end
end
end
endmodule
| 6.613683 |
module BB_SYSTEM (
//////////// OUTPUTS ////////////
BB_SYSTEM_MISO_Out,
BB_SYSTEM_newData_Out,
BB_SYSTEM_data_Out,
//////////// INPUTS ////////////
BB_SYSTEM_CLOCK_50,
BB_SYSTEM_RESET_InHigh,
BB_SYSTEM_SS_InLow,
BB_SYSTEM_MOSI_In,
BB_SYSTEM_SCK_In,
BB_SYSTEM_data_In
);
//===========================================================================
// PARAMETER Declarations
//===========================================================================
// Data width of the imput bus
parameter DATAWIDTH_BUS = 8;
// Size for the states needed into the protocol
parameter STATE_SIZE = 3;
//===========================================================================
// PORT Declarations
//===========================================================================
//////////// OUTPUTS ////////////
output BB_SYSTEM_MISO_Out;
output BB_SYSTEM_newData_Out;
output [DATAWIDTH_BUS-1:0] BB_SYSTEM_data_Out;
//////////// INPUTS ////////////
input BB_SYSTEM_CLOCK_50;
input BB_SYSTEM_RESET_InHigh;
input BB_SYSTEM_SS_InLow;
input BB_SYSTEM_MOSI_In;
input BB_SYSTEM_SCK_In;
input [DATAWIDTH_BUS-1:0] BB_SYSTEM_data_In;
//===========================================================================
// REG/WIRE Declarations
//===========================================================================
//===========================================================================
// STRUCTURAL Coding
//===========================================================================
SPI_SLAVE #(
.DATAWIDTH_BUS(DATAWIDTH_BUS),
.STATE_SIZE(STATE_SIZE)
) SPI_SLAVE_u0 (
// Port map - connection between master ports and signals/registers
//////////// OUTPUTS ////////////
.SPI_SLAVE_MISO_Out(BB_SYSTEM_MISO_Out),
.SPI_SLAVE_newData_Out(BB_SYSTEM_newData_Out),
.SPI_SLAVE_data_Out(BB_SYSTEM_data_Out),
//////////// INPUTS ////////////
.SPI_SLAVE_CLOCK_50(BB_SYSTEM_CLOCK_50),
.SPI_SLAVE_RESET_InHigh(BB_SYSTEM_RESET_InHigh),
.SPI_SLAVE_SS_InLow(BB_SYSTEM_SS_InLow),
.SPI_SLAVE_MOSI_In(BB_SYSTEM_MOSI_In),
.SPI_SLAVE_SCK_In(BB_SYSTEM_SCK_In),
.SPI_SLAVE_data_In(BB_SYSTEM_data_In)
);
endmodule
| 6.747229 |
module dp_group0 (
ir,
a_reg,
x_reg,
y_reg,
d,
ni,
vi,
zi,
ci,
n,
v,
z,
c
);
parameter DBW = 8;
input [DBW-1:0] ir;
input [DBW-1:0] a_reg;
input [DBW-1:0] x_reg;
input [DBW-1:0] y_reg;
input [DBW-1:0] d;
input ni, vi, zi, ci;
output n, v, z, c;
wire [DBW-1:0] w_bit = a_reg & d;
wire [DBW:0] w_cpy = y_reg - d;
wire [DBW:0] w_cpx = x_reg - d;
reg [DBW-1:0] res;
wire ldy = ir[7:5] == `LDY;
wire cpy = ir[7:5] == `CPY;
wire cpx = ir[7:5] == `CPX;
wire bitt = ir[7:5] == `BIT;
always @(ir or w_cpx or w_cpy or w_bit or d) begin
case (ir[7:5])
`CPX: res <= w_cpx[DBW-1:0];
`CPY: res <= w_cpy[DBW-1:0];
`BIT: res <= w_bit;
default: res <= d;
endcase
end
assign n = cpy | cpx | ldy ? res[DBW-1] : bitt ? d[7] : ni;
assign z = cpy | cpx | bitt | ldy ? res == 0 : zi;
assign v = bitt ? d[DBW-2] : vi;
assign c = cpy ? ~w_cpy[DBW] : cpx ? ~w_cpx[DBW] : ci;
endmodule
| 6.819885 |
module dp_group2 (
ir,
ldx,
stxx,
d,
ci,
ni,
zi,
c,
n,
z,
o
);
parameter DBW = 8;
input [7:0] ir;
input ldx;
input stxx;
input [DBW-1:0] d;
input ci, ni, zi;
output c, n, z;
output [DBW-1:0] o;
reg [DBW-1:0] o;
reg sc; // shift carry
wire d_shift = ~ir[7];
always @(ir or d or ci) begin
case (ir[7:5])
`ASL: begin
o <= {d[DBW-2:0], 1'b0};
sc <= d[DBW-1];
end
`ROL: begin
o <= {d[DBW-2:0], ci};
sc <= d[DBW-1];
end
`LSR: begin
o <= {1'b0, d[DBW-1:1]};
sc <= d[0];
end
`ROR: begin
o <= {ci, d[DBW-1:1]};
sc <= d[0];
end
// A store does not affect the flags so the output can
// be set to anything.
`STX: o <= d;
// Output needs to be set on a load so the flags can
// be set.
`LDX: o <= d;
`DEC: o <= d - 8'd1;
`INC: o <= d + 8'd1;
endcase
end
assign c = d_shift ? sc : ci; // cf set only for shifts
assign n = stxx ? ni : o[DBW-1];
assign z = stxx ? zi : o == 0;
endmodule
| 6.613757 |
module bc6502_tb();
reg clk;
reg reset;
reg nmi;
wire irq = 1'b0;
wire rdy = 1'b1;
wire sync;
wire rw;
tri [7:0] d;
wire [7:0] di, do;
wire [15:0] a;
initial begin
clk = 1;
reset = 0;
nmi = 0;
#100 reset = 1;
#100 reset = 0;
#1000 nmi = 1;
#1500 nmi = 0;
#2000 $finish;
end
reg [4095:0] vcdfile;
initial begin
if ($value$plusargs("vcd=%s", vcdfile)) begin
$dumpfile(vcdfile);
$dumpvars(0, bc6502_tb);
end
end
always #17.45 clk = ~clk; // 28.636 MHz
wire ramcs = a[15];
wire romcs = ~a[15];
assign d = ~rw ? do : 8'bz;
assign di = rw ? d : 8'b0;
rom8Kx8 rom0(.ce(romcs), .oe(~rw), .addr(a[12:0]), .d(d));
ram32Kx8 ram0(.clk(clk), .ce(ramcs), .oe(~rw), .we(rw), .addr(a[14:0]), .d(d));
bc6502 cpu0(.reset(reset), .clk(clk), .nmi(nmi), .irq(irq),
.rdy(rdy), .di(di), .do(do), .rw(rw), .ma(a), .sync(sync) );
always @(posedge clk) begin
$display($time,,"\n");
$display("sync=%b rdy=%b romcs=%b ramcs=%b rw=%b\n", sync, rdy, romcs, ramcs, rw);
$display("\tpc=%h a=%h x=%h y=%h sp=%h\n", cpu0.pc_reg, cpu0.a_reg, cpu0.x_reg, cpu0.y_reg, cpu0.sp_reg);
$display("\tir=%h ma=%h d=%h cpu.ma=%h cpu.ma_nxt=%h cpu.pc_nxt=%h cpu.tmp=%h cpu.taken=%b\n", cpu0.ir, a, d, cpu0.ma, cpu0.ma_nxt, cpu0.pc_nxt, cpu0.tmp, cpu0.taken);
$display("\tflags: n=%b v=%b z=%b c=%b im=%b d=%b b=%b", cpu0.nf, cpu0.vf, cpu0.zf, cpu0.cf, cpu0.im, cpu0.df, cpu0.bf);
end
endmodule
| 6.788351 |
module is a functional model, with no timing, and
is only suitable for simulation, not synthesis.
--------------------------------------------------------------- */
`timescale 1ns / 100ps
module rom8Kx8(ce, oe, addr, d);
input ce; // active low chip enable
input oe; // active low output enable
input [12:0] addr; // byte address
output [7:0] d; // tri-state data I/O
tri [7:0] d;
reg [7:0] mem [0:8191];
initial begin
$readmemh ("rom8kx8.mem", mem);
$display ("Loaded rom8kx8.mem");
$display (" 000000: %h %h %h %h %h %h %h %h",
mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7]);
end
assign d = (~oe & ~ce) ? mem[addr] : 8'bz;
always @(oe or ce or addr) begin
$display (" 000000: %h %h %h %h %h %h %h %h %h %h",
mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7], mem[8], mem[9]);
$display (" read %h: %h", addr, mem[addr]);
end
endmodule
| 7.911783 |
module is a functional model, with no timing, and
is only suitable for simulation, not synthesis.
--------------------------------------------------------------- */
`timescale 1ns / 100ps
module ram32Kx8(clk, ce, oe, we, addr, d);
input clk;
input ce; // active low chip enable
input oe; // active low output enable
input we; // active low write enable
input [14:0] addr; // byte address
output [7:0] d; // tri-state data I/O
tri [7:0] d;
reg [7:0] mem [0:32767];
integer nn;
initial begin
for (nn = 0; nn < 32768; nn = nn + 1)
mem[nn] <= 8'b0;
end
assign d = (~oe & ~ce & we) ? mem[addr] : 8'bz;
always @(posedge clk) begin
if (clk) begin
if (~ce & ~we) begin
mem[addr] <= d;
$display (" wrote: %h with %h", addr, d);
end
end
end
always @(we or oe or ce or addr) begin
$display (" 000000: %h %h %h %h %h %h %h %h %h %h",
mem[0], mem[1], mem[2], mem[3], mem[4], mem[5], mem[6], mem[7], mem[8], mem[9]);
end
endmodule
| 7.911783 |
module bcache (
clock,
reset,
enable_bcache,
current_pc,
target_pc,
do_branch,
opcode,
do_flush_REG1,
xREG1_do_hit_bcache,
bcache_opc,
bcache_pc,
do_hit_bcache,
do_bcache
);
input clock;
input reset;
input enable_bcache;
input [31:0] current_pc;
input [31:0] target_pc;
input do_branch;
input [5:0] opcode;
input do_flush_REG1;
input xREG1_do_hit_bcache;
output [31:0] bcache_opc;
output [31:0] bcache_pc;
output do_hit_bcache;
output do_bcache;
wire [31:0] hit_addr;
wire [31:0] hit_target;
wire hit_branch;
wire hit;
wire [31:0] bcache_opc = hit_addr[31:0];
wire [31:0] bcache_pc = hit_target[31:0];
wire do_hit_bcache = hit;
wire do_bcache = (hit) ? hit_branch : 1'b0;
reg do_write;
ram_pc RAM_PC (
.clock(clock),
.reset(reset),
.enable_ram(enable_bcache),
.do_write(do_write),
.current_pc(current_pc),
.target_pc(target_pc),
.do_branch(do_branch),
.sub_op_j(),
.do_flush_REG1(do_flush_REG1),
.hit_addr(hit_addr),
.hit_target(hit_target),
.hit_branch(hit_branch),
.hit_link(),
.hit(hit)
);
always @(posedge clock) begin
if (reset) begin
do_write <= 1'b0;
end else if ((opcode == `TY_B || opcode == `TY_BZ) && (!xREG1_do_hit_bcache)) begin
do_write <= 1'b1;
end else begin
do_write <= 1'b0;
end
end
endmodule
| 6.516888 |
module bcam_reg #(
parameter CDEP = 32, // CAM depth
parameter PWID = 32, // pattern width
parameter REGO = 1
) // register output
(
input clk, // clock
input rst, // global registers reset
input wEn, // write enable
input [ PWID -1:0] wPatt, // write pattern
input [`log2(CDEP)-1:0] wAddr, // write address
input [ PWID -1:0] mPatt, // patern to match
output match, // match indicator
output [`log2(CDEP)-1:0] mAddr
); // match address
// local parameters
localparam AWID = `log2(CDEP);
// local variables
reg [CDEP-1:0] vld; // valid pattern for each address
reg [CDEP-1:0] indc; // match indicators for each address
reg [PWID-1:0] pat[0:CDEP-1]; // CDEP patterns, each PWID bits width
integer ai; // address index
// register pattern and set valid bit for written pattern
always @(posedge clk, posedge rst)
for (ai = 0; ai < CDEP; ai = ai + 1)
if (rst) {vld[ai], pat[ai]} <= {1'b0, {PWID{1'b0}}};
else if (wEn && (wAddr == ai)) {vld[ai], pat[ai]} <= {1'b1, wPatt};
// computer match indicators
always @(*) for (ai = 0; ai < CDEP; ai = ai + 1) indc[ai] = vld[ai] && (mPatt == pat[ai]);
wire matchI; // match / internal
assign matchI = |indc;
// one-hot to binary encoding
// two addresses cannot hold the same pattern
reg [AWID-1:0] mAddrI; // match address / internal
always @(*) begin
mAddrI = {AWID{1'b0}};
for (ai = 0; ai < CDEP; ai = ai + 1) mAddrI = mAddrI | ({AWID{indc[ai]}} & ai[AWID-1:0]);
end
// register outputs
reg [AWID-1:0] mAddrR; // match address / registered
reg matchR; // match / registered
always @(posedge clk, posedge rst)
if (rst) {matchR, mAddrR} <= {1'b0, {AWID{1'b0}}};
else {matchR, mAddrR} <= {matchI, mAddrI};
// select registered or not registered outputs
assign mAddr = REGO ? mAddrR : mAddrI;
assign match = REGO ? matchR : matchI;
endmodule
| 7.511239 |
module bcast_net #(
parameter BCAST_WIDTH = -1,
parameter N_NODES = -1,
parameter [8*N_NODES-1 : 0] NODES_CONF = 0
) (
input CLK,
input en,
// entry to the network
input [BCAST_WIDTH-1 : 0] in,
// output from nodes
output [N_NODES*BCAST_WIDTH-1 : 0] out
);
// Node #0 is the entry to the network (unregistered)
assign out[0+:BCAST_WIDTH] = in;
wire [N_NODES-1:0] in_en;
assign in_en[0] = en;
genvar i;
generate
for (i = 1; i < N_NODES; i = i + 1) begin : node
localparam UPPER_NODE = NODES_CONF[8*i+:8];
(* SHREG_EXTRACT="no", EQUIVALENT_REGISTER_REMOVAL="no" *)
reg [1 + BCAST_WIDTH-1 : 0] r; // +1 for 'en'
assign out[i*BCAST_WIDTH+:BCAST_WIDTH] = r[BCAST_WIDTH-1 : 0];
assign in_en[i] = r[BCAST_WIDTH];
always @(posedge CLK) begin
r[BCAST_WIDTH] <= in_en[UPPER_NODE];
if (in_en[UPPER_NODE]) r[BCAST_WIDTH-1 : 0] <= out[UPPER_NODE*BCAST_WIDTH+:BCAST_WIDTH];
end
end
endgenerate
endmodule
| 7.72818 |
module BCD_Counter (
input clk,
rst,
output [3:0] Q
);
jkfflop first (
1'b1,
1'b1,
clk,
rst,
Q[0]
);
jkfflop second (
~Q[3],
~Q[3],
Q[0],
rst,
Q[1]
);
jkfflop third (
1'b1,
1'b1,
Q[1],
rst,
Q[2]
);
jkfflop fourth (
Q[1] & Q[2],
Q[3],
Q[0],
rst,
Q[3]
);
endmodule
| 6.966103 |
module bcd_adder(sum,output_carry,addend,augend,carry_in);
output [3:0] sum; output output_carry; input [3:0] addend; input [3:0] augend; input carry_in;
wire [3:0] z_addend;
wire carry_out;
wire c_out;
wire [3:0] z_sum;
adder_4bit m0(carry_out,z_sum,addend,augend,carry_in);
and (w1,z_sum[3],z_sum[2]);
and (w2,z_sum[3],z_sum[1]);
assign z_addend={1’b0,output_carry,output_carry,1’b0); or(output_carry,carry_out,w1,w2); adder_4bit(c_out,sum,z_addend,z_sum,1’b0); or(c_out,carry_out,c_out);
endmodule
| 7.752773 |
module adder_4bit (
carry,
sum,
a,
b,
cin
);
output carry;
input [3:0] sum;
input [3:0] a, b;
input c_in;
assign {carry, sum} = a + b + cin;
endmodule
| 9.041993 |
module: CounterBCD
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BCD20counter_tb;
// Inputs
reg CLK;
reg LOAD;
reg CLR;
reg [3:0] DATA;
reg ENP;
reg ENT;
// Outputs
wire [3:0] Q0;
wire [3:0] Q1;
wire [7:0] Q;
wire RCO1;
wire RCO2;
// Instantiate the Unit Under Test (UUT)
CounterBCD uut (
.CLK(CLK),
.LOAD(LOAD),
.CLR(CLR),
.DATA(DATA),
.ENP(ENP),
.ENT(ENT),
.Q0(Q0),
.Q1(Q1),
.Q(Q),
.RCO1(RCO1),
.RCO2(RCO2)
);
initial begin
// Initialize Inputs
CLK = 0;
LOAD = 0;
CLR = 0;
DATA = 0;
ENP = 0;
ENT = 0;
// Wait 100 ns for global reset to finish
#100;
CLR=1;
LOAD=1;
#10;
CLR=0;
DATA=4'b0000;
#20;
LOAD=0;
ENP=1;
#150;
ENT=1;
#250;
ENP=1;
#300;
end
always #10 CLK=!CLK;
endmodule
| 6.85619 |
module BCD27SEG (
input [3:0] bcd_in,
output reg [6:0] seg_o
);
always @(bcd_in) begin //BCD to 7-segments decoder
case (bcd_in)
4'h0: seg_o <= 7'b0000001;
4'h1: seg_o <= 7'b1001111;
4'h2: seg_o <= 7'b0010010;
4'h3: seg_o <= 7'b0000110;
4'h4: seg_o <= 7'b1001100;
4'h5: seg_o <= 7'b0100100;
4'h6: seg_o <= 7'b0100000;
4'h7: seg_o <= 7'b0001111;
4'h8: seg_o <= 7'b0000000;
4'h9: seg_o <= 7'b0000100;
4'hA: seg_o <= 7'b0001000;
4'hB: seg_o <= 7'b1100000;
4'hC: seg_o <= 7'b0110001;
4'hD: seg_o <= 7'b1000010;
4'hE: seg_o <= 7'b0110000;
4'hF: seg_o <= 7'b0111000;
default: seg_o <= 7'b1111111;
endcase
end
endmodule
| 7.407344 |
module translate bcd number into ascii code.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: using Verilog-2001 syntax.
//
// The `timescale directive specifies what the
// simulation time units are (1 ns here) and what
// the simulator time step should be (1 ps here).
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module bcd2ascii1_4
(
input wire clk,
input wire rst,
input wire [3:0] bcd,
output reg [6:0] ascii
);
// signal declaration
reg [6:0] ascii_nxt;
// body
always @(posedge clk) begin
if(rst)
ascii <= 7'h00;
else
ascii <= ascii_nxt;
end
always @(*) begin
case (bcd)
0: ascii_nxt = 7'b011_0000;
1: ascii_nxt = 7'b011_0001;
2: ascii_nxt = 7'b011_0010;
3: ascii_nxt = 7'b011_0011;
4: ascii_nxt = 7'b011_0100;
5: ascii_nxt = 7'b011_0101;
6: ascii_nxt = 7'b011_0110;
7: ascii_nxt = 7'b011_0111;
8: ascii_nxt = 7'b011_1000;
9: ascii_nxt = 7'b011_1001;
default:ascii_nxt = 7'b111_1111;
endcase
end
endmodule
| 6.785091 |
module bcd2bin (
input wire clk,
reset,
input wire start,
input wire [3:0] bcd1,
bcd0,
output reg ready,
done_tick,
output wire [6:0] bin
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, op = 2'b01, done = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [11:0] bcd2b_reg, bcd2b_next;
reg [2:0] n_reg, n_next;
// body
// FSMD state & data registers
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= idle;
bcd2b_reg <= 0;
n_reg <= 0;
end else begin
state_reg <= state_next;
bcd2b_reg <= bcd2b_next;
n_reg <= n_next;
end
// FSMD next-state logic
always @* begin
// defaults
state_next = state_reg;
bcd2b_next = bcd2b_reg;
n_next = n_reg;
ready = 1'b0;
done_tick = 1'b0;
case (state_reg)
idle: begin
ready = 1'b1;
if (start) begin
n_next = 4;
state_next = op;
bcd2b_next = {bcd1, bcd0, 4'b0};
end
end
op: begin
// shift one right
bcd2b_next = bcd2b_reg >> 1;
if (bcd2b_reg[8]) // lsb of bcd1
// bcd0: shift then sum 5, eq. to sum 10 then shift
bcd2b_next[7:4] = {1'b0, bcd2b_reg[7:5]} + 4'b0101;
n_next = n_reg - 1;
if (n_next == 0) state_next = done;
end
done: begin
done_tick = 1'b1;
state_next = idle;
end
default: state_next = idle;
endcase
end
// output
assign bin = bcd2b_reg[6:0];
endmodule
| 6.700276 |
module bcd2bin_test (
input wire clk,
reset,
input wire btn,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] sseg,
output wire [7:0] led
);
// signal declaration
wire start;
wire [3:0] bcd1, bcd0;
assign bcd1 = sw[7:4];
assign bcd0 = sw[3:0];
// instance of debouncer
debounce db_unit (
.clk(clk),
.reset(reset),
.sw(btn),
.db_level(),
.db_tick(start)
);
// instance of bcd-to-binary converter
bcd2bin bcd2bin_unit (
.clk(clk),
.reset(reset),
.start(start),
.bin(led[6:0]),
.ready(led[7]),
.done_tick(),
.bcd1(bcd1),
.bcd0(bcd0)
);
// instance of display unit
disp_hex_mux disp_unit (
.clk(clk),
.reset(reset),
.hex3(4'b0000),
.hex2(4'b0000),
.hex1(bcd1),
.hex0(bcd0),
.dp_in(4'b1111),
.an(an),
.sseg(sseg)
);
endmodule
| 7.56131 |
module bcd2sevenseg (
input [3:0] bcd,
output reg [6:0] seg
);
always @(bcd) begin
case (bcd)
0: seg <= 7'b1111110;
1: seg <= 7'b0110000;
2: seg <= 7'b1101101;
3: seg <= 7'b1111001;
4: seg <= 7'b0110011;
5: seg <= 7'b1011011;
6: seg <= 7'b1011111;
7: seg <= 7'b1110000;
8: seg <= 7'b1111111;
9: seg <= 7'b1111011;
10: seg <= 7'b1110111;
11: seg <= 7'b0011111;
12: seg <= 7'b1001110;
13: seg <= 7'b0111101;
14: seg <= 7'b1001111;
15: seg <= 7'b1000111;
default: seg <= 7'b0000000;
endcase
end
endmodule
| 7.408274 |
module bcd2driver (
in,
out0,
out1,
gt99
);
input [6:0] in;
output [6:0] out0, out1;
output gt99;
reg [6:0] out0, out1;
reg gt99;
parameter ZERO = 7'b100_0000;
parameter ONE = 7'b111_1001;
parameter TWO = 7'b010_0100;
parameter THREE = 7'b011_0000;
parameter FOUR = 7'b001_1001;
parameter FIVE = 7'b001_0010;
parameter SIX = 7'b000_0010;
parameter SEVEN = 7'b111_1000;
parameter EIGHT = 7'b000_0000;
parameter NINE = 7'b001_1000;
parameter DASH = 7'b011_1111;
always @(in) begin
if (in > 7'd099) begin
//display dashes
out0 = DASH;
out1 = DASH;
//greater than 99
gt99 = 1'b1;
end else begin
//not greater than 99
gt99 = 1'b0;
//ones digit
case (in % 7'd010)
7'd000: begin //zero
out0 = ZERO;
end
7'd001: begin //one
out0 = ONE;
end
7'd002: begin //two
out0 = TWO;
end
7'd003: begin //three
out0 = THREE;
end
7'd004: begin //four
out0 = FOUR;
end
7'd005: begin //five
out0 = FIVE;
end
7'd006: begin //six
out0 = SIX;
end
7'd007: begin //seven
out0 = SEVEN;
end
7'd008: begin //eight
out0 = EIGHT;
end
7'd009: begin //nine
out0 = NINE;
end
default: begin
out0 = ZERO;
end
endcase
//tens digit
case ((in / 7'd010) % 7'd010)
7'd000: begin //zero
out1 = ZERO;
end
7'd001: begin //one
out1 = ONE;
end
7'd002: begin //two
out1 = TWO;
end
7'd003: begin //three
out1 = THREE;
end
7'd004: begin //four
out1 = FOUR;
end
7'd005: begin //five
out1 = FIVE;
end
7'd006: begin //six
out1 = SIX;
end
7'd007: begin //seven
out1 = SEVEN;
end
7'd008: begin //eight
out1 = EIGHT;
end
7'd009: begin //nine
out1 = NINE;
end
default: begin
out1 = ZERO;
end
endcase
end
end
endmodule
| 6.634004 |
module bcd2driverTOP (
//////////// CLOCK //////////
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
//////////// SEG7 //////////
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [7:0] HEX3,
output [7:0] HEX4,
output [7:0] HEX5,
//////////// LED //////////
output [9:0] LEDR,
//////////// SW //////////
input [9:0] SW
);
//=======================================================
// REG/WIRE declarations
//=======================================================
bcd2driver bcd2driver (
.in (SW[6:0]),
.out0(HEX0),
.out1(HEX1),
.gt99(LEDR[0])
);
//=======================================================
// Structural coding
//=======================================================
assign HEX0[7] = 1'b1;
assign HEX1[7] = 1'b1;
assign HEX2 = 8'hff;
assign HEX3 = 8'hff;
assign HEX4 = 8'hff;
assign HEX5 = 8'hff;
endmodule
| 6.752062 |
module for BCD to Gray Code Converter
module testbench;
reg [3:0] b;
wire [3:0] g;
bcd2gray_df bcd_df(b, g);
initial
begin
$monitor(,$time," b = %b, g = %b",b,g);
#5 b=4'b0000;
#5 b=4'b0001;
#5 b=4'b0010;
#5 b=4'b0011;
#5 b=4'b0100;
#5 b=4'b0101;
#5 b=4'b0110;
#5 b=4'b0111;
#5 b=4'b1000;
#5 b=4'b1001;
#5 $finish;
end
endmodule
| 6.733174 |
module bcd2seg (
sin,
sout
);
input wire [3:0] sin;
output wire [6:0] sout;
assign sout = (sin==4'h0) ? 7'b0111111 :
(sin==4'h1) ? 7'b0000110 :
(sin==4'h2) ? 7'b1011011 :
(sin==4'h3) ? 7'b1001111 :
(sin==4'h4) ? 7'b1100110 :
(sin==4'h5) ? 7'b1101101 :
(sin==4'h6) ? 7'b1111101 :
(sin==4'h7) ? 7'b0000111 :
(sin==4'h8) ? 7'b1111111 :
(sin==4'h9) ? 7'b1101111 : 7'b0000000;
endmodule
| 7.857628 |
module bcd2seg0_2 (
sin,
sout
);
input wire [1:0] sin;
output wire [6:0] sout;
reg [6:0] SEG_buf;
always @(sin) begin
case (sin)
2'h0: SEG_buf <= 7'b0111111;
2'h1: SEG_buf <= 7'b0000110;
2'h2: SEG_buf <= 7'b1011011;
default: SEG_buf <= 7'b0000000;
endcase
end
assign sout = SEG_buf;
endmodule
| 7.307736 |
module bcd2seg0_5 (
sin,
sout
);
input wire [2:0] sin;
output wire [6:0] sout;
reg [6:0] SEG_buf;
always @(sin) begin
case (sin)
3'h0: SEG_buf <= 7'b0111111;
3'h1: SEG_buf <= 7'b0000110;
3'h2: SEG_buf <= 7'b1011011;
3'h3: SEG_buf <= 7'b1001111;
3'h4: SEG_buf <= 7'b1100110;
3'h5: SEG_buf <= 7'b1101101;
default: SEG_buf <= 7'b0000000;
endcase
end
assign sout = SEG_buf;
endmodule
| 7.542989 |
module bcd2seg0_9 (
sin,
sout
);
input wire [3:0] sin;
output wire [6:0] sout;
reg [6:0] SEG_buf;
always @(sin) begin
case (sin)
4'h0: SEG_buf <= 7'b0111111;
4'h1: SEG_buf <= 7'b0000110;
4'h2: SEG_buf <= 7'b1011011;
4'h3: SEG_buf <= 7'b1001111;
4'h4: SEG_buf <= 7'b1100110;
4'h5: SEG_buf <= 7'b1101101;
4'h6: SEG_buf <= 7'b1111101;
4'h7: SEG_buf <= 7'b0000111;
4'h8: SEG_buf <= 7'b1111111;
4'h9: SEG_buf <= 7'b1101111;
default: SEG_buf <= 7'b0000000;
endcase
end
assign sout = SEG_buf;
endmodule
| 6.727232 |
module.
module segment7(bcd, seg);
//Input and output signals.
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
// always block for a bcd to 7-segment convertor circuit
// It will generate a combination circuit for the conversion.
always @(bcd)
begin
case (bcd) //case statement
0 : seg = 7'b0000001;
1 : seg = 7'b1001111;
2 : seg = 7'b0010010;
3 : seg = 7'b0000110;
4 : seg = 7'b1001100;
5 : seg = 7'b0100100;
6 : seg = 7'b0100000;
7 : seg = 7'b0001111;
8 : seg = 7'b0000000;
9 : seg = 7'b0000100;
//switch off 7 segment character when the bcd digit is not a decimal number.
default : seg = 7'b1111111;
endcase
end
endmodule
| 7.849566 |
module BCD2sevenSeg (
A,
B,
S,
C,
SEG_SEL,
SEG_DATA
);
input [1:0] A, B, S;
input C;
wire [3:0] out;
output [4:0] SEG_SEL;
output [7:0] SEG_DATA;
reg [7:0] SEG_DATA;
sevensegment_calculator res (
A,
B,
S,
C,
out
);
always @(out) begin
case (out)
0: SEG_DATA = 8'b00111111;
1: SEG_DATA = 8'b00000110;
2: SEG_DATA = 8'b01011011;
3: SEG_DATA = 8'b01001111;
4: SEG_DATA = 8'b01100110;
5: SEG_DATA = 8'b01101101;
6: SEG_DATA = 8'b01111101;
7: SEG_DATA = 8'b00000111;
8: SEG_DATA = 8'b01111111;
9: SEG_DATA = 8'b01101111;
default: SEG_DATA = 8'b01111001;
endcase
end
assign SEG_SEL = 5'b00001;
endmodule
| 7.088722 |
module bcd2seven_seg (
a,
b,
cin,
SEG_SEL,
SEG_DATA,
mux_out
);
input [1:0] a;
input [1:0] b;
input cin;
input [2:0] mux_out;
output [4:0] SEG_SEL;
output [7:0] SEG_DATA;
reg [7:0] SEG_DATA;
always @(mux_out) begin
case (mux_out)
0: SEG_DATA = 8'b00111111;
1: SEG_DATA = 8'b00000110;
2: SEG_DATA = 8'b01011011;
3: SEG_DATA = 8'b01001111;
4: SEG_DATA = 8'b01100110;
5: SEG_DATA = 8'b01101101;
6: SEG_DATA = 8'b01111101;
7: SEG_DATA = 8'b00000111;
endcase
end
assign SEG_SEL = 5'b00001;
endmodule
| 6.591284 |
module BCD2SSD (
output reg [6:0] SSDOut, //% 7 segment display (G-A) output vector
input [3:0] BCDIn //% BCD number input
);
always @(BCDIn)
case (BCDIn)
4'h0: SSDOut <= 7'h3F;
4'h1: SSDOut <= 7'h06;
4'h2: SSDOut <= 7'h5B;
4'h3: SSDOut <= 7'h4F;
4'h4: SSDOut <= 7'h66;
4'h5: SSDOut <= 7'h6D;
4'h6: SSDOut <= 7'h7D;
4'h7: SSDOut <= 7'h07;
4'h8: SSDOut <= 7'h7F;
4'h9: SSDOut <= 7'h6F;
4'hA: SSDOut <= 7'h77;
4'hB: SSDOut <= 7'h7C;
4'hC: SSDOut <= 7'h39;
4'hD: SSDOut <= 7'h5E;
4'hE: SSDOut <= 7'h79;
4'hF: SSDOut <= 7'h71;
default: SSDOut <= 7'h00;
endcase
endmodule
| 7.952828 |
module bcd2sseg (
output reg [6:0] sseg,
input [3:0] bcd
);
always @(bcd)
case (bcd)
// x: a b c d e f g
0: sseg = 7'b1111110;
1: sseg = 7'b0110000;
2: sseg = 7'b1101101;
3: sseg = 7'b1111001;
4: sseg = 7'b0110011;
5: sseg = 7'b1011011;
6: sseg = 7'b1011111;
7: sseg = 7'b1110000;
8: sseg = 7'b1111111;
9: sseg = 7'b1111011;
10: sseg = 7'b1110111; // a
11: sseg = 7'b0011111; // b
12: sseg = 7'b0001101; // c
13: sseg = 7'b0111101; // d
14: sseg = 7'b1001111; // e
15: sseg = 7'b1000111; // f
default: sseg = 7'b0000000;
endcase
endmodule
| 6.85487 |
module bcd2vga (
input [3:0] min0,
min1,
sec0,
sec1,
output reg [7:0] bcd1,
bcd2,
bcd3,
bcd4
);
parameter ZERO = 8'b00111111, //to display 0
ONE = 8'b00000110, //to display 1
TWO = 8'b01011011, //to display 2
THREE = 8'b01001111, //to display 3
FOUR = 8'b01100110, //to display 4
FIVE = 8'b01101101, //to display 5
SIX = 8'b01111101, //to display 6
SEVEN = 8'b00000111, //to display 7
EIGHT = 8'b01111111, //to display 8
NINE = 8'b01101111, //to display 9
DASH = 8'b00111111; // display dash
always @(min0) begin
case (min0)
4'd0: bcd1 = ZERO; //to display 0
4'd1: bcd1 = ONE; //to display 1
4'd2: bcd1 = TWO; //to display 2
4'd3: bcd1 = THREE; //to display 3
4'd4: bcd1 = FOUR; //to display 4
4'd5: bcd1 = FIVE; //to display 5
4'd6: bcd1 = SIX; //to display 6
4'd7: bcd1 = SEVEN; //to display 7
4'd8: bcd1 = EIGHT; //to display 8
4'd9: bcd1 = NINE; //to display 9
default: bcd1 = ZERO; //dash
endcase
end
always @(min1) begin
case (min1)
4'd0: bcd2 = ZERO; //to display 0
4'd1: bcd2 = ONE; //to display 1
4'd2: bcd2 = TWO; //to display 2
4'd3: bcd2 = THREE; //to display 3
4'd4: bcd2 = FOUR; //to display 4
4'd5: bcd2 = FIVE; //to display 5
4'd6: bcd2 = SIX; //to display 6
4'd7: bcd2 = SEVEN; //to display 7
4'd8: bcd2 = EIGHT; //to display 8
4'd9: bcd2 = NINE; //to display 9
default: bcd2 = ZERO; //dash
endcase
end
always @(sec0) begin
case (sec0)
4'd0: bcd3 = ZERO; //to display 0
4'd1: bcd3 = ONE; //to display 1
4'd2: bcd3 = TWO; //to display 2
4'd3: bcd3 = THREE; //to display 3
4'd4: bcd3 = FOUR; //to display 4
4'd5: bcd3 = FIVE; //to display 5
4'd6: bcd3 = SIX; //to display 6
4'd7: bcd3 = SEVEN; //to display 7
4'd8: bcd3 = EIGHT; //to display 8
4'd9: bcd3 = NINE; //to display 9
default: bcd3 = ZERO; //dash
endcase
end
always @(sec1) begin
case (sec1)
4'd0: bcd4 = ZERO; //to display 0
4'd1: bcd4 = ONE; //to display 1
4'd2: bcd4 = TWO; //to display 2
4'd3: bcd4 = THREE; //to display 3
4'd4: bcd4 = FOUR; //to display 4
4'd5: bcd4 = FIVE; //to display 5
4'd6: bcd4 = SIX; //to display 6
4'd7: bcd4 = SEVEN; //to display 7
4'd8: bcd4 = EIGHT; //to display 8
4'd9: bcd4 = NINE; //to display 9
default: bcd4 = ZERO; //dash
endcase
end
endmodule
| 6.728699 |
module BCD4bitsWreg (
input [3:0] dat1, //datos de entrada
input [3:0] dat2, //datos de entrada
input clk,
output [0:6] sseg, //salida para el sseg
output reg [3:0] an, //elige el display sseg
input rst
);
reg [3:0] bcd = 0;
BCDtoSSeg bcdtosseg (
.BCD (bcd),
.SSeg(sseg)
); //instanciamiento-documento lab02
reg [26:0] cfreq = 0;
wire enable; //Enable: define el funcionamiento (on/off)
// Divisor de frecuecia
assign enable = cfreq[16];
always @(posedge clk) begin
if (rst == 0) begin
cfreq <= 0;
end else begin
cfreq <= cfreq + 1;
end
end
reg [1:0] count = 0;
always @(posedge enable) begin //ciclo- funciona en el flanco del reloj
if (rst == 0) begin
count <= 0;
an <= 4'b1111;
end else begin
count <= count + 1;
an <= 4'b1101;
//según la entrada de num 1 se hace cada registro
case (dat1)
4'ha:
case (count)
2'h2: begin
bcd <= 4'h0;
an <= 4'b1011;
end
2'h3: begin
bcd <= 4'h1;
an <= 4'b0111;
end
endcase
4'hb:
case (count)
2'h2: begin
bcd <= 4'h1;
an <= 4'b1011;
end
2'h3: begin
bcd <= 4'h1;
an <= 4'b0111;
end
endcase
4'hc:
case (count)
2'h2: begin
bcd <= 4'h2;
an <= 4'b1011;
end
2'h3: begin
bcd <= 4'h1;
an <= 4'b0111;
end
endcase
4'hd:
case (count)
2'h2: begin
bcd <= 4'h3;
an <= 4'b1011;
end
2'h3: begin
bcd <= 4'h1;
an <= 4'b0111;
end
endcase
4'he:
case (count)
2'h2: begin
bcd <= 4'h4;
an <= 4'b1011;
end
2'h3: begin
bcd <= 4'h1;
an <= 4'b0111;
end
endcase
4'hf:
case (count)
2'h2: begin
bcd <= 4'h5;
an <= 4'b1011;
end
2'h3: begin
bcd <= 4'h1;
an <= 4'b0111;
end
endcase
default:
case (count)
2'h2: begin
bcd <= dat1[3:0];
an <= 4'b1011;
end
2'h3: begin
bcd <= 4'b0000;
an <= 4'b0111;
end
endcase
endcase
//según la entrada de dat2 se hace el registro
case (dat2)
4'ha:
case (count)
2'h0: begin
bcd <= 4'h0;
an <= 4'b1110;
end
2'h1: begin
bcd <= 4'h1;
an <= 4'b1101;
end
endcase
4'hb:
case (count)
2'h0: begin
bcd <= 4'h1;
an <= 4'b1110;
end
2'h1: begin
bcd <= 4'h1;
an <= 4'b1101;
end
endcase
4'hc:
case (count)
2'h0: begin
bcd <= 4'h2;
an <= 4'b1110;
end
2'h1: begin
bcd <= 4'h1;
an <= 4'b1101;
end
endcase
4'hd:
case (count)
2'h0: begin
bcd <= 4'h3;
an <= 4'b1110;
end
2'h1: begin
bcd <= 4'h1;
an <= 4'b1101;
end
endcase
4'he:
case (count)
2'h0: begin
bcd <= 4'h4;
an <= 4'b1110;
end
2'h1: begin
bcd <= 4'h1;
an <= 4'b1101;
end
endcase
4'hf:
case (count)
2'h0: begin
bcd <= 4'h5;
an <= 4'b1110;
end
2'h1: begin
bcd <= 4'h1;
an <= 4'b1101;
end
endcase
default:
case (count)
2'h0: begin
bcd <= dat2[3:0];
an <= 4'b1110;
end
2'h1: begin
bcd <= 4'b0000;
an <= 4'b1101;
end
endcase
endcase
end
end
endmodule
| 7.374903 |
module: bcd4digit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bcd4digit_t;
// Inputs
reg clk;
reg rst;
reg [13:0] value;
reg start;
// Outputs
wire ready;
wire [3:0] A;
wire [3:0] B;
wire [3:0] C;
wire [3:0] D;
// Instantiate the Unit Under Test (UUT)
bcd4digit uut (
.ready(ready),
.A(A),
.B(B),
.C(C),
.D(D),
.clk(clk),
.rst(rst),
.value(value),
.start(start)
);
always #50
clk = ~clk;
// always #100 begin
// $display("%14b %4d %14b %10b %3d %1b %1b %1b",
// uut.dividend, uut.dividend, uut.divisor, quotient, quotient, uut.run, uut.fit, ready);
// end
//
// always @( posedge ready ) begin
// #200;
// $finish;
// end
initial begin
// $display("\n dividend divisor quotient run fit ready");
// Initialize Inputs
clk = 1;
rst = 0;
value = 0;
start = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst = 1;
start = 1; #100;
start = 0;
end
endmodule
| 6.753391 |
module BCD7 (
digit,
cathodes
);
input [3:0] digit;
output reg [7:0] cathodes;
always @(*) begin
case (digit)
0: begin
cathodes <= 8'b0111_1110;
end
1: begin
cathodes <= 8'b0000_1100;
end
2: begin
cathodes <= 8'b1011_0110;
end
3: begin
cathodes <= 8'b1001_1110;
end
4: begin
cathodes <= 8'b1100_1100;
end
5: begin
cathodes <= 8'b1101_1010;
end
6: begin
cathodes <= 8'b1111_1010;
end
7: begin
cathodes <= 8'b0000_1110;
end
8: begin
cathodes <= 8'b1111_1110;
end
9: begin
cathodes <= 8'b1101_1110;
end
10: begin
cathodes <= 8'b1110_1110;
end
11: begin
cathodes <= 8'b1111_1000;
end
12: begin
cathodes <= 8'b1011_0000;
end
13: begin
cathodes <= 8'b1011_1100;
end
14: begin
cathodes <= 8'b1111_0010;
end
15: begin
cathodes <= 8'b1110_0010;
end
default: begin
cathodes <= 8'b0000_0000;
end
endcase
end
endmodule
| 6.622019 |
module BCD7segment (
input [3:0] IN,
input select,
output reg [6:0] OUT
);
always @(IN or select) begin
if (select) begin
case (IN)
0: OUT = 7'b0000001;
1: OUT = 7'b1001111;
2: OUT = 7'b0010010;
3: OUT = 7'b0000110;
4: OUT = 7'b1001100;
5: OUT = 7'b0100100;
6: OUT = 7'b0100000;
7: OUT = 7'b0001111;
8: OUT = 7'b0000000;
9: OUT = 7'b0000100;
10: OUT = 7'b0001000;
11: OUT = 7'b0000000;
12: OUT = 7'b0110001;
13: OUT = 7'b0000001;
14: OUT = 7'b0110000;
15: OUT = 7'b0111000;
endcase
end else OUT = 7'b1111110;
end
// 4 enable switches //
endmodule
| 6.704488 |
module BCDA (
A,
B,
cin,
S,
cout_2
);
input [3:0] A, B;
input cin;
wire [3:0] Z, temp;
wire y, cout;
output [3:0] S;
output cout_2;
assign {y, Z} = A + B + cin;
assign cout = (Z[3] && Z[2]) || (Z[3] && Z[1]) || (y);
assign temp[0] = 0;
assign temp[1] = cout;
assign temp[2] = cout;
assign temp[3] = 0;
assign {cout_2, S} = Z + temp;
endmodule
| 7.224024 |
module top_module (
input [399:0] a,
b,
input cin,
output cout,
output [399:0] sum
);
wire [99:0] coutw;
bcd_fadd fadd1 (
.a(a[3:0]),
.b(b[3:0]),
.cin(cin),
.cout(coutw[0]),
.sum(sum[3:0])
);
genvar i;
generate
for (i = 1; i < 100; i = i + 1) begin : test
bcd_fadd faddi (
.a(a[4*i+3:4*i]),
.b(b[4*i+3:4*i]),
.cin(coutw[i-1]),
.cout(coutw[i]),
.sum(sum[4*i+3:4*i])
);
end
endgenerate
assign cout = coutw[99];
endmodule
| 7.203305 |
module top_module (
input [15:0] a,
b,
input cin,
output cout,
output [15:0] sum
);
wire [2:0] carry;
bcd_fadd u_bcd_fadd_1 (
a[3:0],
b[3:0],
cin,
carry[0],
sum[3:0]
);
bcd_fadd u_bcd_fadd_2 (
a[7:4],
b[7:4],
carry[0],
carry[1],
sum[7:4]
);
bcd_fadd u_bcd_fadd_3 (
a[11:8],
b[11:8],
carry[1],
carry[2],
sum[11:8]
);
bcd_fadd u_bcd_fadd_4 (
a[15:12],
b[15:12],
carry[2],
cout,
sum[15:12]
);
endmodule
| 7.203305 |
module bcd_adder (
a,
b,
cin,
reset,
sum,
cout,
co
);
input [3:0] a, b;
input cin, reset;
output cout, co;
output [3:0] sum;
wire [3:0] v;
wire [2:0] w, c;
full_add fa1 (
v,
w[0],
a,
b,
cin
);
and a1 (w[1], v[2], v[3]);
and a2 (w[2], v[1], v[3]);
or o1 (cout, w[0], w[1], w[2]);
adderfull_1bit fa2 (
sum[0],
c[0],
v[0],
reset,
reset
);
adderfull_1bit fa3 (
sum[1],
c[1],
v[1],
cout,
c[0]
);
adderfull_1bit fa4 (
sum[2],
c[2],
v[2],
cout,
c[1]
);
adderfull_1bit fa5 (
sum[3],
co,
v[3],
reset,
c[2]
);
endmodule
| 6.697199 |
module BCDandSEG (
Switch,
SEG
);
//输入端口
input [3:0] Switch;
//输出端口
output [8:0] SEG;
reg [8:0] SEGLED;
always @(Switch) begin
case (Switch)
4'b0000: SEGLED = 9'h3f;
4'b0001: SEGLED = 9'h06;
4'b0010: SEGLED = 9'h5b;
4'b0011: SEGLED = 9'h4f;
4'b0100: SEGLED = 9'h66;
4'b0101: SEGLED = 9'h6d;
4'b0110: SEGLED = 9'h7d;
4'b0111: SEGLED = 9'h07;
4'b1000: SEGLED = 9'h7f;
4'b1001: SEGLED = 9'h6f;
default: SEGLED = 9'h3f;
endcase
end
assign SEG = SEGLED;
endmodule
| 7.061282 |
module BCDcount (
Clock,
Reset,
Enable,
BCD1,
BCD0,
BCDCombine
);
input Clock, Reset, Enable;
output reg [3:0] BCD1, BCD0;
output reg [6:0] BCDCombine;
always @(posedge Clock) begin
if (Reset) begin
BCD1 <= 0;
BCD0 <= 0;
end else if (Enable)
if (BCD0 == 4'b1001) begin //if 9 seconds na, i zero niya then i increment si tens
BCD0 <= 0;
if (BCD1 == 4'b1001) //if 99 seconds na, i zero niya si tens then i increment si minutes
BCD1 <= 0;
else BCD1 <= BCD1 + 1;
end else BCD0 <= BCD0 + 1;
BCDCombine <= BCD1 * 10 + BCD0;
end
endmodule
| 7.123108 |
module bcdCounter (
clkIn,
BCD
);
// Define inputs and outputs
input clkIn;
output reg [2:0] BCD;
reg [2:0] count;
initial begin
count = 0;
end
always @(posedge clkIn) begin
if (count < 6) begin
BCD <= count;
count <= count + 1;
end else begin
BCD <= 6;
count <= 0;
end
end
endmodule
| 7.03096 |
module BCDCounter_mod10_tb;
parameter HALF_PERIOD = 0.5;
reg clk, clr, load, en;
reg [3:0] data;
wire [3:0] out;
wire tc, zero;
initial begin
clk = 0;
end
always #HALF_PERIOD clk = ~clk;
BCDCounter_mod10 ct_1 (
.clrn(clr),
.loadn(load),
.en(en),
.clk(clk),
.data(data),
.out(out),
.tc(tc),
.zero(zero)
);
initial begin
$dumpfile("BCDCounter_mod10.vcd");
$dumpvars(0, BCDCounter_mod10_tb);
end
initial begin
// reset
clr = 0;
en = 0;
load = 1;
data = 4'd0;
#15;
// muda valor para 4
clr = 1;
en = 0;
load = 0;
data = 4'd4;
#10;
// contar até 2
clr = 1;
en = 1;
load = 1;
#20;
// pausa
clr = 1;
en = 0;
load = 1;
#10;
// reset
clr = 0;
en = 0;
load = 1;
#10;
// muda valor para 5
clr = 1;
en = 0;
load = 0;
data = 4'd5;
#10;
// contagem
clr = 1;
en = 1;
load = 1;
#50;
// muda valor para 0
clr = 1;
en = 0;
load = 0;
data = 4'd0;
#10;
// contagem
clr = 1;
en = 1;
load = 1;
#10;
$finish();
end
endmodule
| 7.220593 |
module BCDCounter_mod10 (
input wire clrn,
loadn,
en,
clk,
input wire [3:0] data,
output reg [3:0] out,
output reg tc,
zero
);
reg [3:0] curr_state;
always @(posedge clk, negedge loadn, negedge clrn) begin
if (~clrn) begin
curr_state <= 0;
end else if (~loadn) begin
curr_state <= data;
end else if (en) begin
curr_state <= (curr_state == 0) ? 9 : curr_state - 1;
end
zero = (curr_state == 0) ? 1 : 0;
out = curr_state;
end
always @(posedge clk, posedge en) begin
tc = (en && curr_state == 0);
end
endmodule
| 7.220593 |
module BCDCounter_mod6_tb;
parameter HALF_PERIOD = 0.5;
reg clk, clr, load, en;
reg [3:0] data;
wire [3:0] out;
wire tc, zero;
initial begin
clk = 0;
end
always #HALF_PERIOD clk = ~clk;
BCDCounter_mod6 ct_1 (
.clrn(clr),
.loadn(load),
.en(en),
.clk(clk),
.data(data),
.out(out),
.tc(tc),
.zero(zero)
);
initial begin
$dumpfile("BCDCounter_mod6.vcd");
$dumpvars(0, BCDCounter_mod6_tb);
end
initial begin
// reset
clr = 0;
en = 0;
load = 1;
data = 4'd0;
#15;
// muda valor para 4
clr = 1;
en = 0;
load = 0;
data = 4'd4;
#10;
// contar até 2
clr = 1;
en = 1;
load = 1;
#20;
// pausa
clr = 1;
en = 0;
load = 1;
#10;
// reset
clr = 0;
en = 0;
load = 1;
#10;
// muda valor para 5
clr = 1;
en = 0;
load = 0;
data = 4'd5;
#10;
// contagem
clr = 1;
en = 1;
load = 1;
#50;
// muda valor para 0
clr = 1;
en = 0;
load = 0;
data = 4'd0;
#10;
// contagem
clr = 1;
en = 1;
load = 1;
#10;
$finish();
end
endmodule
| 7.220593 |
module BCDCounter_mod6 (
input wire clrn,
loadn,
en,
clk,
input wire [3:0] data,
output reg [3:0] out,
output reg tc,
zero
);
reg [3:0] curr_state;
always @(posedge clk, negedge loadn, negedge clrn) begin
if (~clrn) begin
curr_state <= 0;
end else if (~loadn) begin
curr_state <= data;
end else if (en) begin
curr_state <= (curr_state == 0) ? 5 : curr_state - 1;
end
zero = (curr_state == 0) ? 1 : 0;
out = curr_state;
end
always @(posedge clk, posedge en) begin
tc = (en && curr_state == 0);
end
endmodule
| 7.220593 |
module BCDpara7segmentos (
input [3:0] bcd,
output a,
b,
c,
d,
e,
f,
g
);
reg [6:0] seteSegmentos;
assign {a, b, c, d, e, f, g} = seteSegmentos;
always @(*) begin
case (bcd)
4'b0000: seteSegmentos = 7'b0000001;
4'b0001: seteSegmentos = 7'b1001111;
4'b0010: seteSegmentos = 7'b0010010;
4'b0011: seteSegmentos = 7'b0000110;
4'b0100: seteSegmentos = 7'b1001100;
4'b0101: seteSegmentos = 7'b0100100;
4'b0110: seteSegmentos = 7'b1100000;
4'b0111: seteSegmentos = 7'b0001111;
4'b1000: seteSegmentos = 7'b0000000;
4'b1001: seteSegmentos = 7'b0001100;
default: seteSegmentos = 7'b1111111;
endcase
end
endmodule
| 7.338196 |
module: BCDto7cathod
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BCDto7cathod_tb;
// Inputs
reg [3:0] IN;
reg LAMP_TEST;
reg RBI;
// Outputs
wire a;
wire b;
wire c;
wire d;
wire e;
wire f;
wire g;
// Instantiate the Unit Under Test (UUT)
BCDto7cathod uut (
.IN(IN),
.LAMP_TEST(LAMP_TEST),
.RBI(RBI),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g)
);
initial begin
// Initialize Inputs
IN = 0;;
LAMP_TEST = 1;
RBI = 1;
// Wait 100 ns for global reset to finish
#100;
IN = 4'b0101;;
LAMP_TEST = 0;
#100;
IN = 4'b0100;;
LAMP_TEST = 0;
#100;
IN = 4'b0111;
LAMP_TEST = 0;
#100;
end
endmodule
| 6.624466 |
module BCDto7LED (
LED4,
LED3,
LED2,
LED1,
data,
en
);
output reg [6:0] LED4, LED3, LED2, LED1;
input [15:0] data;
input en;
reg [4:0] i;
always @(*) begin
if (!en) LED4 <= 7'b1111111; // No display
else
case (data[15:12])
4'b0000: LED4 <= 7'b0000001; // 0
4'b0001: LED4 <= 7'b1001111; // 1
4'b0010: LED4 <= 7'b0010010; // 2
4'b0011: LED4 <= 7'b0000110; // 3
4'b0100: LED4 <= 7'b1001100; // 4
4'b0101: LED4 <= 7'b0100100; // 5
4'b0110: LED4 <= 7'b0100000; // 6
4'b0111: LED4 <= 7'b0001111; // 7
4'b1000: LED4 <= 7'b0000000; // 8
default: LED4 <= 7'b0000100; // 9
endcase
if (!en) LED3 <= 7'b1111111; // No display
else
case (data[11:8])
4'b0000: LED3 <= 7'b0000001; // 0
4'b0001: LED3 <= 7'b1001111; // 1
4'b0010: LED3 <= 7'b0010010; // 2
4'b0011: LED3 <= 7'b0000110; // 3
4'b0100: LED3 <= 7'b1001100; // 4
4'b0101: LED3 <= 7'b0100100; // 5
4'b0110: LED3 <= 7'b0100000; // 6
4'b0111: LED3 <= 7'b0001111; // 7
4'b1000: LED3 <= 7'b0000000; // 8
default: LED3 <= 7'b0000100; // 9
endcase
if (!en) LED2 <= 7'b1111111; // No display
else
case (data[7:4])
4'b0000: LED2 <= 7'b0000001; // 0
4'b0001: LED2 <= 7'b1001111; // 1
4'b0010: LED2 <= 7'b0010010; // 2
4'b0011: LED2 <= 7'b0000110; // 3
4'b0100: LED2 <= 7'b1001100; // 4
4'b0101: LED2 <= 7'b0100100; // 5
4'b0110: LED2 <= 7'b0100000; // 6
4'b0111: LED2 <= 7'b0001111; // 7
4'b1000: LED2 <= 7'b0000000; // 8
default: LED2 <= 7'b0000100; // 9
endcase
if (!en) LED1 <= 7'b1111111; // No display
else
case (data[3:0])
4'b0000: LED1 <= 7'b0000001; // 0
4'b0001: LED1 <= 7'b1001111; // 1
4'b0010: LED1 <= 7'b0010010; // 2
4'b0011: LED1 <= 7'b0000110; // 3
4'b0100: LED1 <= 7'b1001100; // 4
4'b0101: LED1 <= 7'b0100100; // 5
4'b0110: LED1 <= 7'b0100000; // 6
4'b0111: LED1 <= 7'b0001111; // 7
4'b1000: LED1 <= 7'b0000000; // 8
default: LED1 <= 7'b0000100; // 9
endcase
end
endmodule
| 6.860618 |
module bcdto7seg (
input [3:0] bcd,
output reg [6:0] seg
);
always @(bcd) begin
case (bcd)
4'd0: seg <= 7'b1000000;
4'd1: seg <= 7'b1111001;
4'd2: seg <= 7'b0100100;
4'd3: seg <= 7'b0110000;
4'd4: seg <= 7'b0011001;
4'd5: seg <= 7'b0010010;
4'd6: seg <= 7'b0000010;
4'd7: seg <= 7'b1111000;
4'd8: seg <= 7'b0000000;
4'd9: seg <= 7'b0010000;
default: seg <= 7'b0000110;
endcase
end
endmodule
| 7.041565 |
module bcdto7segen (
bcd,
seg
);
input [9:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd) begin
case (bcd)
10'b1000000000: seg = 7'b1111110;
10'b0100000000: seg = 7'b0110000;
10'b0010000000: seg = 7'b1101101;
10'b0001000000: seg = 7'b1111001;
10'b0000100000: seg = 7'b0110011;
10'b0000010000: seg = 7'b1011011;
10'b0000001000: seg = 7'b1011111;
10'b0000000100: seg = 7'b1110000;
10'b0000000010: seg = 7'b1111111;
10'b0000000001: seg = 7'b1111011;
default: seg = 7'b0000000;
endcase
end
endmodule
| 7.76346 |
module bcdto7segment (
bcd,
seg
);
input [3:0] bcd;
output [6:0] seg;
reg [6:0] seg;
always @(bcd) begin
case (bcd) //case statement
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
6: seg = 7'b0100000;
7: seg = 7'b0001111;
8: seg = 7'b0000000;
9: seg = 7'b0000100;
//switch off 7 segment character when the bcd digit is not a decimal number.
default: seg = 7'b1111111;
endcase
end
endmodule
| 7.120176 |
module bcdto7segment_dataflow (
input [3:0] x,
output reg [6:0] seg
);
always @(x) begin
case (x)
4'b0000: seg <= 7'b1000000;
4'b0001: seg <= 7'b1111001;
4'b0010: seg <= 7'b0100100;
4'b0011: seg <= 7'b0110000;
4'b0100: seg <= 7'b0011001;
4'b0101: seg <= 7'b0010010;
4'b0110: seg <= 7'b0000010;
4'b0111: seg <= 7'b1111000;
4'b1000: seg <= 7'b0000000;
4'b1001: seg <= 7'b0011000;
4'b1010: seg <= 7'b0001000;
4'b1011: seg <= 7'b0000011;
4'b1100: seg <= 7'b1000110;
4'b1101: seg <= 7'b0100001;
4'b1110: seg <= 7'b0000110;
4'b1111: seg <= 7'b0001110;
endcase
end
endmodule
| 7.120176 |
module bcdto7segment_tb;
reg [3:0] bcd;
wire [6:0] seg;
integer i;
// Instantiate the Unit Under Test (UUT)
bcdto7segment uut (
.bcd(bcd),
.seg(seg)
);
//Apply inputs
initial begin
for (
i = 0; i < 16; i = i + 1
) //run loop for 0 to 15.
begin
bcd = i;
#10; //wait for 10 ns
end
end
endmodule
| 7.120176 |
module BCDto7SegsVHDL (
Entrada,
Saida
);
input [3:0] Entrada;
output reg [6:0] Saida;
always @(*) begin
case (Entrada)
4'b0000: Saida = 7'b0000001;
4'b0001: Saida = 7'b1001111;
4'b0010: Saida = 7'b0010010;
4'b0011: Saida = 7'b0000110;
4'b0100: Saida = 7'b1001100;
4'b0101: Saida = 7'b0100100;
4'b0110: Saida = 7'b1100000;
4'b0111: Saida = 7'b0001111;
4'b1000: Saida = 7'b0000000;
4'b1001: Saida = 7'b0001100;
default: Saida = 7'b1111111;
endcase
end
endmodule
| 7.640758 |
module bcdto8segment_dataflow (
input [3:0] x,
output reg [7:0] seg
);
always @(x) begin
case (x)
4'b0000: seg <= 8'b11000000;
4'b0001: seg <= 8'b11111001;
4'b0010: seg <= 8'b10100100;
4'b0011: seg <= 8'b10110000;
4'b0100: seg <= 8'b10011001;
4'b0101: seg <= 8'b10010010;
4'b0110: seg <= 8'b10000010;
4'b0111: seg <= 8'b11111000;
4'b1000: seg <= 8'b10000000;
4'b1001: seg <= 8'b10010000;
default: seg <= 8'b1xxxxxxx;
endcase
end
endmodule
| 8.06751 |
module BCDtoDisplay (
In,
Out
);
input [3:0] In;
output reg [6:0] Out;
always @(*)
case (In)
4'b0000: Out = ~7'b0111111;
4'b0001: Out = ~7'b0000110;
4'b0010: Out = ~7'b1011011;
4'b0011: Out = ~7'b1001111;
4'b0100: Out = ~7'b1100110;
4'b0101: Out = ~7'b1101101;
4'b0110: Out = ~7'b1111101;
4'b0111: Out = ~7'b0000111;
4'b1000: Out = ~7'b1111111;
4'b1001: Out = ~7'b1101111;
4'b1010: Out = ~7'b1110111;
4'b1011: Out = ~7'b1111100;
4'b1100: Out = ~7'b0111001;
4'b1101: Out = ~7'b1011110;
4'b1110: Out = ~7'b1111001;
4'b1111: Out = ~7'b1110001;
default: Out = ~7'b0000000;
endcase
endmodule
| 8.555888 |
module bcdToGray_beh (
Out,
In
);
input [3:0] In;
integer i;
output [3:0] Out;
reg [3:0] Out;
always @(In) begin
Out[3] = In[3];
for (i = 3; i > 0; i = i - 1) Out[i-1] = In[i] ^ In[i-1];
end
endmodule
| 6.888905 |
module bcdToGray_df (
Out,
In
);
input [3:0] In;
output [3:0] Out;
assign Out[3] = In[3];
//assign Out[2]=In[3]^In[2];
//assign Out[1]=In[2]^In[1];
//assign Out[0]=In[0]^In[1];
assign Out[2:0] = In[3:1] ^ In[2:0];
endmodule
| 6.589685 |
module bcdToGray_gate (
Out,
In
);
input [3:0] In;
output [3:0] Out;
buf b1 (Out[3], In[3]);
xor x1 (Out[2], In[3], In[2]);
xor x2 (Out[1], In[2], In[1]);
xor x3 (Out[0], In[1], In[0]);
endmodule
| 6.602988 |
module BCDToLED (
input [3:0] x, // binary input
output [6:0] seg // segments
//output [3:0] an // display specific anodes
);
//reg [6:0] seg;
assign seg[0] = x[2] & ~x[1] & ~x[0] | ~x[3] & ~x[2] & ~x[1] & x[0];
assign seg[1] = x[2] & ~x[1] & x[0] | x[2] & x[1] & ~x[0];
assign seg[2] = ~x[2] & x[1] & ~x[0];
assign seg[3] = x[2] & ~x[1] & ~x[0] | x[2] & x[1] & x[0] | ~x[3] & ~x[2] & ~x[1] & x[0];
assign seg[4] = x[2] & ~x[1] | x[0];
assign seg[5] = x[1] & x[0] | ~x[2] & x[1] | ~x[3] & ~x[2] & x[0];
assign seg[6] = x[2] & x[1] & x[0] | ~x[3] & ~x[1] & ~x[2];
//assign an=4'h1;
endmodule
| 7.007072 |
module BCDToSeg7_32bit (
input [31:0] bcd,
output reg [47:0] x
);
always @* begin
x[47:0] = 48'b0;
x[3:0] = bcd[3:0];
x[9:6] = bcd[7:4];
x[15:12] = bcd[11:8];
x[21:18] = bcd[15:12];
x[27:24] = bcd[19:16];
x[33:30] = bcd[23:20];
x[39:36] = bcd[27:24];
x[45:42] = bcd[31:28];
end
endmodule
| 6.917862 |
module BCDToSeg7_8bit (
input [7:0] bcd,
output reg [11:0] x
);
always @* begin
x[11:0] = 12'b0;
x[3:0] = bcd[3:0];
x[9:6] = bcd[7:4];
end
endmodule
| 7.025009 |
module BCDtoSSeg (
BCD,
SSeg
);
input [3:0] BCD;
output reg [6:0] SSeg;
always @(*) begin
case (BCD)
4'b0000: SSeg = 7'b0000001; // "0"
4'b0001: SSeg = 7'b1001111; // "1"
4'b0010: SSeg = 7'b0010010; // "2"
4'b0011: SSeg = 7'b0000110; // "3"
4'b0100: SSeg = 7'b1001100; // "4"
4'b0101: SSeg = 7'b0100100; // "5"
4'b0110: SSeg = 7'b0100000; // "6"
4'b0111: SSeg = 7'b0001111; // "7"
4'b1000: SSeg = 7'b0000000; // "8"
4'b1001: SSeg = 7'b0000100; // "9"
4'ha: SSeg = 7'b0001000;
4'hb: SSeg = 7'b1100000;
4'hc: SSeg = 7'b0110001;
4'hd: SSeg = 7'b1000010;
4'he: SSeg = 7'b0110000;
4'hf: SSeg = 7'b0111000;
default: SSeg = 0;
endcase
end
endmodule
| 6.819202 |
module translate bcd word into ascii code.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: using Verilog-2001 syntax.
//
// The `timescale directive specifies what the
// simulation time units are (1 ns here) and what
// the simulator time step should be (1 ps here).
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module bcdword2ascii1_16
(
input wire clk,
input wire rst,
input wire [15:0] bcd_word,
output wire [27:0] ascii_word
);
wire [3:0] bcd_word_arr [0:3];
wire [6:0] ascii_word_arr [0:3];
assign {bcd_word_arr[3],bcd_word_arr[2],bcd_word_arr[1],bcd_word_arr[0]} = bcd_word;
assign ascii_word = {ascii_word_arr[3],ascii_word_arr[2],ascii_word_arr[1],ascii_word_arr[0]};
genvar i;
generate
for (i = 0; i < 4 ; i = i + 1 ) begin
bcd2ascii1_4 my_bcd2ascii1_4
(
.clk(clk),
.rst(rst),
.bcd(bcd_word_arr[i]),
.ascii(ascii_word_arr[i])
);
end
endgenerate
endmodule
| 6.785091 |
module bcd_2_7seg (
data_in,
data_out
);
input [3:0] data_in;
output [6:0] data_out;
//secuence :a-b-c-d-e-f-g-h // pin plan to (MSB)HEX[0]-HEX[1]-HEX[2]-HEX[3]-HEX[4]-HEX[5]-HEX[6]-HEX[7](LSB)
assign data_out = (data_in == 4'b0000) ? 7'b1000000 : //0 segments
(data_in == 4'b0001) ? 7'b1111001 : //1 segments
(data_in == 4'b0010) ? 7'b0100100 : //2 segments
(data_in == 4'b0011) ? 7'b0110000 : //3 segments
(data_in == 4'b0100) ? 7'b0011001 : //4 segments
(data_in == 4'b0101) ? 7'b0010010 : //5 segments
(data_in == 4'b0110) ? 7'b0000010 : //6 segments
(data_in == 4'b0111) ? 7'b1111000 : //7 segments
(data_in == 4'b1000) ? 7'b0000000 : //8 segments
(data_in == 4'b1001) ? 7'b0010000 : //9 segments
7'b0000110;
endmodule
| 7.046268 |
module bcd_bit (
input wire [3:0] a,
b,
output wire [3:0] c,
input wire cin,
output wire cout
);
wire [4:0] t;
assign t = {1'b0, a} + {1'b0, b} + {4'b0, cin};
assign {cout, c} = (t > 5'd9) ? t + 5'd6 : t;
endmodule
| 7.027446 |
module bcd_adder (
input wire [11:0] a,
b,
output wire [11:0] c
);
wire [1:0] out;
bcd_bit bcd0 (
.a(a[3:0]),
.b(b[3:0]),
.c(c[3:0]),
.cin(1'b0),
.cout(out[0])
);
bcd_bit bcd1 (
.a(a[7:4]),
.b(b[7:4]),
.c(c[7:4]),
.cin(out[0]),
.cout(out[1])
);
bcd_bit bcd2 (
.a (a[11:8]),
.b (b[11:8]),
.c (c[11:8]),
.cin(out[1])
);
endmodule
| 6.697199 |
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