code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module barrel (
bs_opsel,
shift_amount,
data_in,
result
);
input [`OPSEL_WIDTH-1:0] bs_opsel;
input [`SA_WIDTH-1:0] shift_amount;
input [`REG_WIDTH-1:0] data_in;
output reg [`REG_WIDTH-1:0] result;
wire [`REG_WIDTH*2-1:0] temp1, temp2;
wire arithm, is_arithm_shift;
assign is_arithm_shift = bs_opsel[2];
assign arithm = data_in[`REG_WIDTH-1] & is_arithm_shift;
assign temp1 = {data_in, data_in} << shift_amount;
assign temp2 = $signed({arithm, data_in, data_in}) >>> shift_amount;
always @* begin
casez (bs_opsel)
`SLL: result = temp1[`REG_WIDTH-1:0];
`SRL: result = temp2[`REG_WIDTH*2-1:`REG_WIDTH];
`ROR: result = temp2[`REG_WIDTH-1:0];
`ROL: result = temp1[`REG_WIDTH*2-1:`REG_WIDTH];
`SRA: result = temp2[`REG_WIDTH*2-1:`REG_WIDTH];
endcase
end
endmodule
| 7.311845 |
module barrel_shifter_stage (
input wire [7:0] a,
input wire [2:0] amt,
output wire [7:0] y
);
// signal declaration
wire [7:0] s0, s1;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[7:1]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[1:0], s0[7:2]} : s0;
// stage 2, shift 0 or 4 bits
assign y = amt[2] ? {s1[3:0], s1[7:4]} : s1;
endmodule
| 8.606549 |
module barrel_shifter_stage (
input wire [3:0] a,
input wire [1:0] amt,
output wire [3:0] y
);
//signal declaration
wire [3:0] s0; //, s1;
//body
//stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[3:1]} : a;
//stage 1, shift 0 or 2 bits
assign y = amt[1] ? {s0[1:0], s0[3:2]} : s0;
//assign s1 = amt[1] ? {s0[1:0], s0[3:2]} : s0;
//stage 2, shift 0 or 4 bits
//assign y = amt[2] ? {s1[3:0], s1[7:4]} : s1;
endmodule
| 8.606549 |
module barrel_shifter_stage_l (
input wire [7:0] a,
input wire [2:0] amt,
output wire [7:0] y
);
// signal declaration
wire [7:0] s0, s1;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[6:0], a[7]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[5:0], s0[7:6]} : s0;
// stage 2, shift 0 or 4 bits
assign y = amt[2] ? {s1[3:0], s1[7:4]} : s1;
endmodule
| 8.606549 |
module barrel_shifter_stage_r (
input wire [7:0] a,
input wire [2:0] amt,
output wire [7:0] y
);
// signal declaration
wire [7:0] s0, s1;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[7:1]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[1:0], s0[7:2]} : s0;
// stage 2, shift 0 or 4 bits
assign y = amt[2] ? {s1[3:0], s1[7:4]} : s1;
endmodule
| 8.606549 |
module barrel_shifter_stage_r_16b (
input wire [15:0] a,
input wire [ 3:0] amt,
output wire [15:0] y
);
// signal declaration
wire [15:0] s0, s1, s2;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[15:1]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[1:0], s0[15:2]} : s0;
// stage 2, shift 0 or 4 bits
assign s2 = amt[2] ? {s1[3:0], s1[15:4]} : s1;
// stage 3, shift 0 or 8 bits
assign y = amt[3] ? {s2[7:0], s2[15:8]} : s2;
endmodule
| 8.606549 |
module barrel_shifter_stage_r_32b (
input wire [31:0] a,
input wire [ 4:0] amt,
output wire [31:0] y
);
// signal declaration
wire [31:0] s0, s1, s2, s3;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[31:1]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[1:0], s0[31:2]} : s0;
// stage 2, shift 0 or 4 bits
assign s2 = amt[2] ? {s1[3:0], s1[31:4]} : s1;
// stage 3, shift 0 or 8 bits
assign s3 = amt[3] ? {s2[7:0], s2[31:8]} : s2;
// stage 4, shift 0 or 16 bits
assign y = amt[4] ? {s3[15:0], s3[31:16]} : s3;
endmodule
| 8.606549 |
module barrel_shifter_tb;
reg [ 2:0] bs_opsel_sig;
reg [ 4:0] shift_amount_sig;
reg [31:0] data_in_sig;
wire [31:0] result_sig;
barrel_shifter barrel_shifter_inst (
.bs_opsel(bs_opsel_sig), // input [2:0] bs_opsel_sig
.shift_amount(shift_amount_sig), // input [31:0] shift_amount_sig
.data_in(data_in_sig), // input [31:0] data_in_sig
.result(result_sig) // output [31:0] result_sig
);
initial begin
data_in_sig = 32'habcd1234;
shift_amount_sig = 5'h4;
bs_opsel_sig = 3'b000; //shift left logical
#10 bs_opsel_sig = 3'b001; //rotate left
#10 bs_opsel_sig = 3'b010; //shift right logical
#10 bs_opsel_sig = 3'b011; //rotate right
#10 bs_opsel_sig = 3'b111; //shift right arithmetical]
end
initial begin
#50 $stop();
end
endmodule
| 8.606549 |
module barrel_shifter_tb2;
reg [31:0] D;
reg [31:0] S;
reg LnR;
wire [31:0] Y;
SHIFT32 shift32 (
.Y (Y),
.D (D),
.S (S),
.LnR(LnR)
);
initial begin
S = 32'h0;
D = 32'h1;
LnR = 1'b1;
#5 S = 32'h1;
#5 S = 32'h2;
#5 S = 32'h3;
#5 S = 32'h4;
#5 S = 32'h5;
#5 S = 32'h6;
#5 S = 32'h7;
#5 S = 32'h8;
#5 S = 32'h9;
#5 S = 32'ha;
#5 S = 32'hb;
#5 S = 32'hc;
#5 S = 32'hd;
#5 S = 32'he;
#5 S = 32'hf;
#5 S = 32'h10;
#5 S = 32'h11;
#5 S = 32'h12;
#5 S = 32'h13;
#5 S = 32'h14;
#5 S = 32'h15;
#5 S = 32'h16;
#5 S = 32'h17;
#5 S = 32'h18;
#5 S = 32'h19;
#5 S = 32'h1a;
#5 S = 32'h1b;
#5 S = 32'h1c;
#5 S = 32'h1d;
#5 S = 32'h1e;
#5 S = 32'h1f;
#5 S = 32'h0;
D = 32'h8000_0000;
LnR = 1'b0;
#5 S = 32'h1;
#5 S = 32'h2;
#5 S = 32'h3;
#5 S = 32'h4;
#5 S = 32'h5;
#5 S = 32'h6;
#5 S = 32'h7;
#5 S = 32'h8;
#5 S = 32'h9;
#5 S = 32'ha;
#5 S = 32'hb;
#5 S = 32'hc;
#5 S = 32'hd;
#5 S = 32'he;
#5 S = 32'hf;
#5 S = 32'h10;
#5 S = 32'h11;
#5 S = 32'h12;
#5 S = 32'h13;
#5 S = 32'h14;
#5 S = 32'h15;
#5 S = 32'h16;
#5 S = 32'h17;
#5 S = 32'h18;
#5 S = 32'h19;
#5 S = 32'h1a;
#5 S = 32'h1b;
#5 S = 32'h1c;
#5 S = 32'h1d;
#5 S = 32'h1e;
#5 S = 32'h1f;
#5 S = 32'h0;
#5 S = 32'h5f;
#5 S = 32'h7f;
#5 S = 32'hfff_ffe2;
#5 S = 32'h0;
end
endmodule
| 8.606549 |
module barrel_shifter_test;
reg [2:0] bs_opsel_sig;
reg [4:0] shift_amount_sig;
reg [31:0] data_in_sig;
wire [31:0] result_sig;
integer i = 0;
lab3_barrel_shifter lab3_barrel_shifter_inst (
.bs_opsel(bs_opsel_sig), // input [2:0] bs_opsel_sig
.shift_amount(shift_amount_sig), // input [4:0] shift_amount_sig
.data_in(data_in_sig), // input [31:0] data_in_sig
.result(result_sig) // output [31:0] result_sig
);
initial begin
data_in_sig = 32'habcdabcd;
bs_opsel_sig = 0;
shift_amount_sig = 0;
#10 shift_amount_sig = 5'h4;
for (i = 0; i <= 7; i++) begin
#10 bs_opsel_sig = 3'(i); //create by Vadim Charchuk
end
end
initial begin
#400 $stop();
end
endmodule
| 8.606549 |
module barrel (
bs_opsel,
shift_amount,
data_in,
result
);
input [`OPSEL_WIDTH-1:0] bs_opsel;
input [`SA_WIDTH-1:0] shift_amount;
input [`REG_WIDTH-1:0] data_in;
output reg [`REG_WIDTH-1:0] result;
wire [`REG_WIDTH*2-1:0] temp1, temp2;
wire arithm, is_arithm_shift;
assign is_arithm_shift = bs_opsel[2];
assign arithm = data_in[`REG_WIDTH-1] & is_arithm_shift;
assign temp1 = {data_in, data_in} << shift_amount;
assign temp2 = $signed({arithm, data_in, data_in}) >>> shift_amount;
always @* begin
casez (bs_opsel)
`SLL: result = temp1[`REG_WIDTH-1:0];
`SRL: result = temp2[`REG_WIDTH*2-1:`REG_WIDTH];
`ROR: result = temp2[`REG_WIDTH-1:0];
`ROL: result = temp1[`REG_WIDTH*2-1:`REG_WIDTH];
`SRA: result = temp2[`REG_WIDTH*2-1:`REG_WIDTH];
endcase
end
endmodule
| 7.311845 |
module mux2 (
input wire i0,
i1,
j,
output wire o
);
assign o = (j == 0) ? i0 : i1;
endmodule
| 7.816424 |
module barrel_shift_16bit (
in,
ctrl,
out
);
input [15:0] in;
input [3:0] ctrl;
output [15:0] out;
wire [15:0] x, y, z;
//8bit shift right
mux2 mux_15 (
in[15],
1'b0,
ctrl[3],
x[15]
);
mux2 mux_14 (
in[14],
1'b0,
ctrl[3],
x[14]
);
mux2 mux_13 (
in[13],
1'b0,
ctrl[3],
x[13]
);
mux2 mux_12 (
in[12],
1'b0,
ctrl[3],
x[12]
);
mux2 mux_11 (
in[11],
1'b0,
ctrl[3],
x[11]
);
mux2 mux_10 (
in[10],
1'b0,
ctrl[3],
x[10]
);
mux2 mux_9 (
in[9],
1'b0,
ctrl[3],
x[9]
);
mux2 mux_8 (
in[8],
1'b0,
ctrl[3],
x[8]
);
mux2 mux_7 (
in[7],
in[15],
ctrl[3],
x[7]
);
mux2 mux_6 (
in[6],
in[14],
ctrl[3],
x[6]
);
mux2 mux_5 (
in[5],
in[13],
ctrl[3],
x[5]
);
mux2 mux_4 (
in[4],
in[12],
ctrl[3],
x[4]
);
mux2 mux_3 (
in[3],
in[11],
ctrl[3],
x[3]
);
mux2 mux_2 (
in[2],
in[10],
ctrl[3],
x[2]
);
mux2 mux_1 (
in[1],
in[9],
ctrl[3],
x[1]
);
mux2 mux_0 (
in[0],
in[8],
ctrl[3],
x[0]
);
//4bit shift right
mux2 mux_31 (
x[15],
1'b0,
ctrl[2],
y[15]
);
mux2 mux_30 (
x[14],
1'b0,
ctrl[2],
y[14]
);
mux2 mux_29 (
x[13],
1'b0,
ctrl[2],
y[13]
);
mux2 mux_28 (
x[12],
1'b0,
ctrl[2],
y[12]
);
mux2 mux_27 (
x[11],
x[15],
ctrl[2],
y[11]
);
mux2 mux_26 (
x[10],
x[14],
ctrl[2],
y[10]
);
mux2 mux_25 (
x[9],
x[13],
ctrl[2],
y[9]
);
mux2 mux_24 (
x[8],
x[12],
ctrl[2],
y[8]
);
mux2 mux_23 (
x[7],
x[11],
ctrl[2],
y[7]
);
mux2 mux_22 (
x[6],
x[10],
ctrl[2],
y[6]
);
mux2 mux_21 (
x[5],
x[9],
ctrl[2],
y[5]
);
mux2 mux_20 (
x[4],
x[8],
ctrl[2],
y[4]
);
mux2 mux_19 (
x[3],
x[7],
ctrl[2],
y[3]
);
mux2 mux_18 (
x[2],
x[6],
ctrl[2],
y[2]
);
mux2 mux_17 (
x[1],
x[5],
ctrl[2],
y[1]
);
mux2 mux_16 (
x[0],
x[4],
ctrl[2],
y[0]
);
//2bit shift right
mux2 mux_47 (
y[15],
1'b0,
ctrl[1],
z[15]
);
mux2 mux_46 (
y[14],
1'b0,
ctrl[1],
z[14]
);
mux2 mux_45 (
y[13],
y[15],
ctrl[1],
z[13]
);
mux2 mux_44 (
y[12],
y[14],
ctrl[1],
z[12]
);
mux2 mux_43 (
y[11],
y[13],
ctrl[1],
z[11]
);
mux2 mux_42 (
y[10],
y[12],
ctrl[1],
z[10]
);
mux2 mux_41 (
y[9],
y[11],
ctrl[1],
z[9]
);
mux2 mux_40 (
y[8],
y[10],
ctrl[1],
z[8]
);
mux2 mux_39 (
y[7],
y[9],
ctrl[1],
z[7]
);
mux2 mux_38 (
y[6],
y[8],
ctrl[1],
z[6]
);
mux2 mux_37 (
y[5],
y[7],
ctrl[1],
z[5]
);
mux2 mux_36 (
y[4],
y[6],
ctrl[1],
z[4]
);
mux2 mux_35 (
y[3],
y[5],
ctrl[1],
z[3]
);
mux2 mux_34 (
y[2],
y[4],
ctrl[1],
z[2]
);
mux2 mux_33 (
y[1],
y[3],
ctrl[1],
z[1]
);
mux2 mux_32 (
y[0],
y[2],
ctrl[1],
z[0]
);
//1bit shift right
mux2 mux_63 (
z[15],
1'b0,
ctrl[0],
out[15]
);
mux2 mux_62 (
z[14],
z[15],
ctrl[0],
out[14]
);
mux2 mux_61 (
z[13],
z[14],
ctrl[0],
out[13]
);
mux2 mux_60 (
z[12],
z[13],
ctrl[0],
out[12]
);
mux2 mux_59 (
z[11],
z[12],
ctrl[0],
out[11]
);
mux2 mux_58 (
z[10],
z[11],
ctrl[0],
out[10]
);
mux2 mux_57 (
z[9],
z[10],
ctrl[0],
out[9]
);
mux2 mux_56 (
z[8],
z[9],
ctrl[0],
out[8]
);
mux2 mux_55 (
z[7],
z[8],
ctrl[0],
out[7]
);
mux2 mux_54 (
z[6],
z[7],
ctrl[0],
out[6]
);
mux2 mux_53 (
z[5],
z[6],
ctrl[0],
out[5]
);
mux2 mux_52 (
z[4],
z[5],
ctrl[0],
out[4]
);
mux2 mux_51 (
z[3],
z[4],
ctrl[0],
out[3]
);
mux2 mux_50 (
z[2],
z[3],
ctrl[0],
out[2]
);
mux2 mux_49 (
z[1],
z[2],
ctrl[0],
out[1]
);
mux2 mux_48 (
z[0],
z[1],
ctrl[0],
out[0]
);
endmodule
| 7.827555 |
module barrel_shift_mips #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 5,
parameter lo_l = 0,
parameter lo_r = 1,
parameter al_r = 2,
parameter ci_r = 3
) (
input [(DATA_WIDTH -1):0] data_in,
input [(ADDR_WIDTH -1):0] shift_count,
input [1:0] op,
output reg [(DATA_WIDTH -1):0] data_out
);
//integer i;
reg [(DATA_WIDTH -1):0] inter1;
reg [(DATA_WIDTH -1):0] inter2;
always @(*) begin
inter1 = 32'h0;
inter2 = 32'h0;
data_out = data_in;
case (op)
lo_l: data_out = data_in << shift_count;
lo_r: data_out = data_in >> shift_count;
al_r: data_out = $signed(data_in) >>> shift_count;
ci_r: begin
if (shift_count[4] == 1'b1) data_out = {data_out[15:0], data_out[31:16]};
if (shift_count[3] == 1'b1) data_out = {data_out[7:0], data_out[31:8]};
if (shift_count[2] == 1'b1) data_out = {data_out[3:0], data_out[31:4]};
if (shift_count[1] == 1'b1) data_out = {data_out[1:0], data_out[31:2]};
if (shift_count[0] == 1'b1) data_out = {data_out[0], data_out[31:1]};
end
endcase
end
endmodule
| 7.827555 |
module barrel_tb;
reg [ 2:0] bs_opsel_sig;
reg [ 4:0] shift_amount_sig;
reg [31:0] data_in_sig;
wire [31:0] result_sig;
integer i, j;
barrel barrel_inst (
.bs_opsel(bs_opsel_sig), // input [2:0] bs_opsel_sig
.shift_amount(shift_amount_sig), // input [4:0] shift_amount_sig
.data_in(data_in_sig), // input [31:0] data_in_sig
.result(result_sig) // output [31:0] result_sig
);
initial begin
shift_amount_sig = 0;
bs_opsel_sig = 0;
data_in_sig = $random;
for (i = 0; i <= 16; i = i + 4) begin
shift_amount_sig = i;
for (j = 0; j <= 7; j = j + 1) begin
bs_opsel_sig = j;
#2;
end
end
shift_amount_sig = 0;
bs_opsel_sig = 0;
data_in_sig = 0;
end
initial begin
#100 $stop();
end
endmodule
| 6.712577 |
module barrel_test;
parameter pattern_num = 8;
wire [7:0] out;
wire carry;
reg [7:0] x, y;
reg clk;
reg stop;
integer i, num, error;
reg [7:0] ans_out;
reg [7:0] barrel_out;
reg [7:0] data_base1 [0:100];
reg [7:0] data_base2 [0:100];
barrel_shifter B (
x,
y[2:0],
out
);
initial begin
$readmemh(`INFILE, data_base1);
$readmemh(`OUTFILE, data_base2);
clk = 1'b1;
error = 0;
stop = 0;
i = 0;
end
always begin
#(`CYCLE * 0.5) clk = ~clk;
end
initial begin
x[7:0] = data_base1[0];
y[7:0] = data_base1[1];
for (num = 2; num < (pattern_num * 2); num = num + 2) begin
@(posedge clk) begin
x[7:0] = data_base1[num];
y[7:0] = data_base1[num+1];
end
end
end
always @(posedge clk) begin
i <= i + 1;
if (i >= pattern_num) stop <= 1;
end
always @(posedge clk) begin
barrel_out <= out;
ans_out <= data_base2[i];
if (barrel_out !== ans_out) begin
error <= error + 1;
$display("An ERROR occurs at no.%d pattern: Output %b != answer %b.\n", i, barrel_out,
ans_out);
end
end
initial begin
@(posedge stop) begin
if (error == 0) begin
$display("==========================================\n");
$display("====== Congratulation! You Pass! =======\n");
$display("==========================================\n");
end else begin
$display("===============================\n");
$display("There are %d errors.", error);
$display("===============================\n");
end
$finish;
end
end
/*================Dumping Waveform files====================*/
initial begin
$dumpfile("barrel.vcd");
$dumpvars;
/* $fsdbDumpfile("barrel.fsdb");
$fsdbDumpvars; */
end
endmodule
| 7.124734 |
module DecoupledStage (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [23:0] io_in_bits_ul,
input [23:0] io_in_bits_quo,
input io_out_ready,
output io_out_valid,
output [23:0] io_out_bits_ul,
output [23:0] io_out_bits_quo
);
reg valid;
reg [23:0] reg_ul;
reg [23:0] reg_quo;
wire _T = io_in_ready & io_in_valid;
wire _GEN_0 = io_out_ready ? 1'h0 : valid;
wire _GEN_3 = _T | _GEN_0;
assign io_in_ready = ~valid | io_out_ready;
assign io_out_valid = valid;
assign io_out_bits_ul = reg_ul;
assign io_out_bits_quo = reg_quo;
always @(posedge clock) begin
if (reset) begin
valid <= 1'h0;
end else begin
valid <= _GEN_3;
end
if (_T) begin
reg_ul <= io_in_bits_ul;
end
if (_T) begin
reg_quo <= io_in_bits_quo;
end
end
initial begin
end
endmodule
| 7.271782 |
module DecoupledStage_1 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [23:0] io_in_bits_ul,
input [23:0] io_in_bits_quo,
input [23:0] io_in_bits_quo_times_Q,
input io_out_ready,
output io_out_valid,
output [23:0] io_out_bits_ul,
output [23:0] io_out_bits_quo,
output [23:0] io_out_bits_quo_times_Q
);
reg valid;
reg [23:0] reg_ul;
reg [23:0] reg_quo;
reg [23:0] reg_quo_times_Q;
wire _T = io_in_ready & io_in_valid;
wire _GEN_0 = io_out_ready ? 1'h0 : valid;
wire _GEN_4 = _T | _GEN_0;
assign io_in_ready = ~valid | io_out_ready;
assign io_out_valid = valid;
assign io_out_bits_ul = reg_ul;
assign io_out_bits_quo = reg_quo;
assign io_out_bits_quo_times_Q = reg_quo_times_Q;
always @(posedge clock) begin
if (reset) begin
valid <= 1'h0;
end else begin
valid <= _GEN_4;
end
if (_T) begin
reg_ul <= io_in_bits_ul;
end
if (_T) begin
reg_quo <= io_in_bits_quo;
end
if (_T) begin
reg_quo_times_Q <= io_in_bits_quo_times_Q;
end
end
initial begin
end
endmodule
| 7.271782 |
module DecoupledStage_2 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [22:0] io_in_bits_remainder,
input [23:0] io_in_bits_quotient,
input io_out_ready,
output io_out_valid,
output [22:0] io_out_bits_remainder,
output [23:0] io_out_bits_quotient
);
reg valid;
reg [22:0] reg_remainder;
reg [23:0] reg_quotient;
wire _T = io_in_ready & io_in_valid;
wire _GEN_0 = io_out_ready ? 1'h0 : valid;
wire _GEN_3 = _T | _GEN_0;
assign io_in_ready = ~valid | io_out_ready;
assign io_out_valid = valid;
assign io_out_bits_remainder = reg_remainder;
assign io_out_bits_quotient = reg_quotient;
always @(posedge clock) begin
if (reset) begin
valid <= 1'h0;
end else begin
valid <= _GEN_3;
end
if (_T) begin
reg_remainder <= io_in_bits_remainder;
end
if (_T) begin
reg_quotient <= io_in_bits_quotient;
end
end
initial begin
end
endmodule
| 7.271782 |
module barrett_reducer (
input clk,
input rst,
input en,
input [15:0] a,
input valid,
output reg out_valid,
output reg [13:0] result
);
wire [15:0] NEWHOPE_Q_MULTIPLE;
assign NEWHOPE_Q_MULTIPLE = (a[15:14] == 0) ? 16'd0 :
(a[15:14] == 1) ? 16'd12289 :
(a[15:14] == 2) ? 16'd24578 :
(a[15:14] == 3) ? 16'd36867 : 0;
reg [15:0] a_1;
reg valid_1;
always @(posedge clk) begin
if (rst) begin
valid_1 <= 0;
out_valid <= 0;
end else if (en) begin
a_1 <= a - NEWHOPE_Q_MULTIPLE;
valid_1 <= valid;
result <= (16'd24578 <= a_1) ? a_1 - 16'd24578 : (16'd12289 <= a_1) ? a_1 - 16'd12289 : a_1;
out_valid <= valid_1;
end
end
endmodule
| 7.179208 |
module barrido (
clk,
filas
);
input clk;
output reg [3:0] filas = 0;
reg [1:0] selector = 0;
always @(posedge clk) begin
selector = selector + 1;
case (selector)
2'b00: filas = 4'b1000;
2'b01: filas = 4'b0100;
2'b10: filas = 4'b0010;
2'b11: filas = 4'b0001;
endcase
end
endmodule
| 7.160924 |
module. Aggregates barrier good notifications
* from individual modules and pushes out a global barrier good notification
* when all modules are ready.
*
*
*/
`timescale 1ns/1ps
module barrier #(
parameter NUM_PORTS = 4
)
(
input [NUM_PORTS:0] activity_stim,
input [NUM_PORTS:0] activity_rec,
input activity_trans_sim,
input activity_trans_log,
input [NUM_PORTS:0] barrier_req,
input barrier_req_trans,
output reg barrier_proceed
);
// Time to wait before declaring the system "stuck" when we have a barrier
// and not all modules are ready to proceed.
//
parameter INACTIVITY_TIMEOUT = 4000000; //4000;
time req_time;
reg timeout;
wire [NUM_PORTS:0] activity;
wire activity_trans;
assign activity = {activity_stim[4] || activity_rec[4],activity_stim[3] || activity_rec[3],activity_stim[2] || activity_rec[2],activity_stim[1] || activity_rec[1],activity_stim[0] || activity_rec[0]};
assign activity_trans = {activity_trans_sim || activity_trans_log};
initial
begin
barrier_proceed = 0;
timeout = 0;
forever begin
wait ({barrier_req, barrier_req_trans} != 'h0);
req_time = $time;
timeout = 0;
#1;
// Wait until either all ports are asserting a barrier request,
// none of the ports are asserting a barrier request, or a timeout
// occurs waiting for the barrier
wait (({barrier_req, barrier_req_trans} === {(NUM_PORTS+2){1'b1}}) ||
({barrier_req, barrier_req_trans} === 'h0) || timeout);
if (timeout == 1) begin
$display($time," %m Error: timeout exceeded waiting for barrier");
$finish;
end
else if ({barrier_req, barrier_req_trans} === {(NUM_PORTS+2){1'b1}}) begin
// Barrier request from all modules
barrier_proceed = 1;
wait ({barrier_req, barrier_req_trans} === 'h0);
barrier_proceed = 0;
end
end
end
initial
begin
forever begin
wait ({barrier_req, barrier_req_trans} != 'h0 && {activity, activity_trans} != 'h0);
req_time = $time;
#1;
end
end
initial
begin
forever begin
if ({barrier_req, barrier_req_trans} != 'h0) begin
while ({barrier_req, barrier_req_trans} != 'h0) begin
#1;
#(req_time + INACTIVITY_TIMEOUT - $time);
if ({barrier_req, barrier_req_trans} != 'h0 && req_time + INACTIVITY_TIMEOUT <= $time)
timeout = 1;
end
end
else begin
wait ({barrier_req, barrier_req_trans} != 'h0);
end
end
end
endmodule
| 6.877898 |
module. Aggregates barrier good notifications
// from individual modules and pushes out a global barrier good notification
// when all modules are ready.
//
///////////////////////////////////////////////////////////////////////////////
// `timescale 1 ns/1 ns
module barrier_ctrl #(
parameter NUM_PORTS = 4
)
(
input [0:NUM_PORTS - 1] if_activity,
input pci_activity,
input [0:NUM_PORTS - 1] if_good,
input pci_good,
output reg barrier_proceed
);
// Time to wait before declaring the system "stuck" when we have a barrier
// and not all modules are ready to proceed.
//
// Currently: 200 ns
parameter INACTIVITY_TIMEOUT = 200000;
time req_time;
reg timeout;
initial
begin
barrier_proceed = 0;
timeout = 0;
forever begin
wait ({if_good, pci_good} != 'h0);
req_time = $time;
timeout = 0;
#1;
// Wait until either all ports are asserting a barrier request,
// none of the ports are asserting a barrier request, or a timeout
// occurs waiting for the barrier
wait (({if_good, pci_good} === {(NUM_PORTS + 1){1'b1}}) ||
({if_good, pci_good} === 'h0) || timeout);
if (timeout) begin
$display($time," %m Error: timeout exceeded waiting for barrier");
$finish;
end
else if ({if_good, pci_good} === {(NUM_PORTS + 1){1'b1}}) begin
// Barrier request from all modules
barrier_proceed = 1;
wait ({if_good, pci_good} === 'h0);
barrier_proceed = 0;
end
end
end
initial
begin
forever begin
wait ({if_good, pci_good} != 'h0 && {if_activity, pci_activity} != 'h0);
req_time = $time;
#1;
end
end
initial
begin
forever begin
if ({if_good, pci_good} != 'h0) begin
while ({if_good, pci_good} != 'h0) begin
#1;
#(req_time + INACTIVITY_TIMEOUT - $time);
if ({if_good, pci_good} != 'h0 && req_time + INACTIVITY_TIMEOUT <= $time)
timeout = 1;
end
end
else begin
wait ({if_good, pci_good} != 'h0);
end
end
end
endmodule
| 6.877898 |
module barrier_gluelogic (
input wire in_pin4,
input wire in_pin3,
input wire in_pin2,
input wire in_pin1,
input wire in_pin0,
output wire [4:0] out_bus
);
assign out_bus = {in_pin4, in_pin3, in_pin2, in_pin1, in_pin0};
endmodule
| 7.931567 |
module bars (
input wire [9:0] x_px,
output wire [2:0] color_px
);
//Calculate width bar.
localparam barwidth = 80; // For a 640x480@72Hz, 3bits controller
// We're inside a bar, set its color.
assign color_px = ((x_px >= 0*barwidth) && (x_px < 1*barwidth)) ? 3'b111 :
(((x_px >= 1*barwidth) && (x_px < 2*barwidth)) ? 3'b110 :
(((x_px >= 2*barwidth) && (x_px < 3*barwidth)) ? 3'b101 :
(((x_px >= 3*barwidth) && (x_px < 4*barwidth)) ? 3'b100 :
(((x_px >= 4*barwidth) && (x_px < 5*barwidth)) ? 3'b011 :
(((x_px >= 5*barwidth) && (x_px < 6*barwidth)) ? 3'b010 :
(((x_px >= 6*barwidth) && (x_px < 7*barwidth)) ? 3'b001 : 3'b000 ))))));
endmodule
| 10.146891 |
module BarSH (
input [ 1:0] ex_shift_op,
input [31:0] ex_b,
input [ 4:0] ex_shift_amount,
output [31:0] ex_bs_out
);
reg [31:0] r;
always @(ex_shift_amount or ex_b or ex_shift_op) begin
r = ex_b;
case (ex_shift_op)
2'b01: begin
if (ex_shift_amount[0]) r = {1'b0, r[31:1]};
if (ex_shift_amount[1]) r = {2'd0, r[31:2]};
if (ex_shift_amount[2]) r = {4'd0, r[31:4]};
if (ex_shift_amount[3]) r = {8'd0, r[31:8]};
if (ex_shift_amount[4]) r = {16'd0, r[31:16]};
end
2'b10: begin
if (r[31]) begin
if (ex_shift_amount[0]) r = {1'b1, r[31:1]};
if (ex_shift_amount[1]) r = {2'b11, r[31:2]};
if (ex_shift_amount[2]) r = {4'hf, r[31:4]};
if (ex_shift_amount[3]) r = {8'hff, r[31:8]};
if (ex_shift_amount[4]) r = {16'hffff, r[31:16]};
end else begin
if (ex_shift_amount[0]) r = {1'b0, r[31:1]};
if (ex_shift_amount[1]) r = {2'd0, r[31:2]};
if (ex_shift_amount[2]) r = {4'd0, r[31:4]};
if (ex_shift_amount[3]) r = {8'd0, r[31:8]};
if (ex_shift_amount[4]) r = {16'd0, r[31:16]};
end
end
default: begin
if (ex_shift_amount[0]) r = {r[30:0], 1'b0};
if (ex_shift_amount[1]) r = {r[29:0], 2'd0};
if (ex_shift_amount[2]) r = {r[27:0], 4'd0};
if (ex_shift_amount[3]) r = {r[23:0], 8'd0};
if (ex_shift_amount[4]) r = {r[15:0], 16'd0};
end
endcase
end
assign ex_bs_out = r;
endmodule
| 6.587072 |
module barshift_128b_tb ();
wire [127:0] out0;
reg [127:0] in0;
reg [ 6:0] in1;
integer i, file, mem, temp;
barshift_128b U0 (
in0,
in1,
out0
);
initial begin
$display("-- Begining Simulation --");
$dumpfile("./barshift_128b.vcd");
$dumpvars(0, barshift_128b_tb);
file = $fopen("output.txt", "w");
mem = $fopen("dataset", "r");
in0 = 0;
in1 = 0;
#10
for (i = 0; i < 1000000; i = i + 1) begin
temp = $fscanf(mem, "%h %h \n", in0, in1);
#10 $fwrite(file, "%d\n", {out0});
$display("-- Progress: %d/1000000 --", i + 1);
end
$fclose(file);
$fclose(mem);
$finish;
end
endmodule
| 6.708298 |
module BarTop (
input Clock,
Reset,
Start,
NewFrame,
input [2:0] FallSpeed,
input [6:0] Bar,
output reg [6:0] Top
);
localparam depth_ram = 800;
localparam bw_addr = 10;
localparam preset_resetval = 0;
localparam hfp = 4; //Heightの固定小数点位置 右から
localparam sfp = 5;
localparam bw_speed = 2 + sfp;
localparam bw_height = 7 + hfp;
reg [bw_addr-1:0] rRAMAddr;
reg [bw_height-1:0] rHeightData;
reg rWE;
reg rStart;
reg [bw_speed-1:0] rSpeedData;
wire [bw_speed-1:0] wSpeed; //落下速度
wire [bw_height-1:0] wHeight; //位置
wire wInBarIsBig = Bar > wHeight[bw_height-1:hfp];
pmi_ram_dq #(
.pmi_addr_depth(800),
.pmi_addr_width(bw_addr),
.pmi_data_width(bw_height + bw_speed),
.pmi_regmode("reg"),
.pmi_gsr("disable"),
.pmi_resetmode("sync"),
.pmi_optimization("speed"),
.pmi_init_file("none"),
.pmi_init_file_format("binary"),
.pmi_write_mode("normal"),
.pmi_family("XP2"),
.module_type("pmi_ram_dq")
) spram (
.Data({rSpeedData, rHeightData}),
.Address(rRAMAddr),
.Clock(Clock),
.ClockEn(1'b1),
.WE(rWE),
.Reset(Reset),
.Q({wSpeed, wHeight})
);
reg [2:0] rFallSpeed;
localparam max_speed = (2 ** bw_speed) - 1;
//reg rFallFrame;
always @(posedge Reset or posedge Clock) begin
if (Reset) begin
{rRAMAddr, rHeightData, Top, rStart, rSpeedData, rWE /*,rFallFrame*/} <= 1'b0;
end else begin
/*
if(NewFrame) //落下するフレーム
rFallFrame <= ~rFallFrame;
*/
if (wInBarIsBig) rHeightData <= {Bar, {hfp{1'b0}}}; //高さをリセット
else if (wHeight >= wSpeed) rHeightData <= wHeight - wSpeed[bw_speed-1:sfp-hfp];
else rHeightData <= 1'b0;
if (wInBarIsBig) //速度をリセット
rSpeedData <= 1'b0;
else if ((wSpeed < max_speed) /*&&rFallFrame*/) //速度MAXでない
rSpeedData <= wSpeed + FallSpeed;
else //速度MAXなら
rSpeedData <= wSpeed;
rWE <= Start;
rStart <= Start;
if (NewFrame) rRAMAddr <= 1'b0;
else if (rStart) rRAMAddr <= rRAMAddr + 1'b1;
if (rStart) Top <= rHeightData[bw_height-1:hfp];
end
end
endmodule
| 7.100458 |
module bar_big (
input [11:0] x,
input [11:0] y,
input [11:0] org_x,
input [11:0] org_y,
input [11:0] line_x,
input [11:0] line_y,
output bar_space
);
assign bar_space=(
(x>=org_x) && (x<=(org_x+line_x)) &&
(y>=org_y) && (y<=(org_y+line_y))
)?1:0;
endmodule
| 7.065217 |
module bar_white (
input [11:0] CounterY,
output L_5,
output L_6,
output L_7,
output M_1,
output M_2,
output M_3,
output M_4,
output M_5,
output M_6,
output M_7,
output H_1,
output H_2,
output H_3,
output H_4,
output H_5
);
wire [11:0] ydeta = 30;
wire [11:0] yd_t = ydeta + 2;
assign H_5 = ((CounterY >= (yd_t * 0)) && (CounterY <= (yd_t * 1))) ? 1 : 0;
assign H_4 = ((CounterY >= (yd_t * 1)) && (CounterY <= (yd_t * 2))) ? 1 : 0;
assign H_3 = ((CounterY >= (yd_t * 2)) && (CounterY <= (yd_t * 3))) ? 1 : 0;
assign H_2 = ((CounterY >= (yd_t * 3)) && (CounterY <= (yd_t * 4))) ? 1 : 0;
assign H_1 = ((CounterY >= (yd_t * 4)) && (CounterY <= (yd_t * 5))) ? 1 : 0;
assign M_7 = ((CounterY >= (yd_t * 5)) && (CounterY <= (yd_t * 6))) ? 1 : 0;
assign M_6 = ((CounterY >= (yd_t * 6)) && (CounterY <= (yd_t * 7))) ? 1 : 0;
assign M_5 = ((CounterY >= (yd_t * 7)) && (CounterY <= (yd_t * 8))) ? 1 : 0;
assign M_4 = ((CounterY >= (yd_t * 8)) && (CounterY <= (yd_t * 9))) ? 1 : 0;
assign M_3 = ((CounterY >= (yd_t * 9)) && (CounterY <= (yd_t * 10))) ? 1 : 0;
assign M_2 = ((CounterY >= (yd_t * 10)) && (CounterY <= (yd_t * 11))) ? 1 : 0;
assign M_1 = ((CounterY >= (yd_t * 11)) && (CounterY <= (yd_t * 12))) ? 1 : 0;
assign L_7 = ((CounterY >= (yd_t * 12)) && (CounterY <= (yd_t * 13))) ? 1 : 0;
assign L_6 = ((CounterY >= (yd_t * 13)) && (CounterY <= (yd_t * 14))) ? 1 : 0;
assign L_5 = ((CounterY >= (yd_t * 14)) && (CounterY <= (yd_t * 15))) ? 1 : 0;
endmodule
| 7.058695 |
module base1 (
en,
clk,
addr,
data
);
input en;
input clk;
output reg [3:0] addr;
output reg [3:0] data;
always @(posedge clk, posedge en) begin
if (en == 1) begin
if (addr == 0 || data == 0 || addr == 1 || data == 1) begin
addr <= addr + 1;
data <= data + 1;
end else begin
addr <= 0;
data <= 0;
end
end else if (addr < 4'b1111) begin
addr <= addr + 1;
data <= data + 1;
end else begin
addr <= 4'bz;
data <= 4'bz;
end
end
endmodule
| 6.61489 |
module baseaddr_loop (
input wclk,
input wrst_n,
input wr_vs,
input [4:0] rd0_curr_point,
input [4:0] rd1_curr_point,
input [4:0] rd2_curr_point,
output reg [4:0] wr_current_point,
output reg [4:0] last_next_point
);
wire wr_vs_raising, wr_vs_falling;
edge_generator #(
.MODE("NORMAL") // FAST NORMAL BEST
) edge_wr_vsync_inst (
.clk (wclk),
.rst_n (wrst_n),
.in (wr_vs),
.raising(wr_vs_raising),
.falling(wr_vs_falling)
);
reg [4:0] wr_next_point, wr_next_point_Q;
reg [4:0] wr0_curr_point;
reg [3:0] prit[4:0];
reg [4:0] pri_point;
always @(posedge wclk, negedge wrst_n)
if (~wrst_n) wr_current_point <= 5'b00001;
else if (wr_vs_raising) wr_current_point <= wr_next_point_Q;
else wr_current_point <= wr_current_point;
always @(posedge wclk, negedge wrst_n)
if (~wrst_n) wr_next_point_Q <= 5'b00000;
else
casex (wr_next_point)
5'bxxxx1: wr_next_point_Q <= 5'b00001;
5'bxxx10: wr_next_point_Q <= 5'b00010;
5'bxx100: wr_next_point_Q <= 5'b00100;
5'bx1000: wr_next_point_Q <= 5'b01000;
5'b10000: wr_next_point_Q <= 5'b10000;
default: wr_next_point_Q <= 5'b00001;
endcase
always @(posedge wclk, negedge wrst_n)
if (~wrst_n) wr_next_point <= 5'b00001;
else wr_next_point <= ~(wr_current_point | rd0_curr_point | rd1_curr_point | rd2_curr_point);
always @(posedge wclk, negedge wrst_n) begin : prit_BLOCK
integer II;
if (~wrst_n) begin
for (II = 0; II < 5; II = II + 1) prit[II] <= 4'd2;
end else begin
for (II = 0; II < 5; II = II + 1) begin
if (wr_vs_raising)
if (wr_next_point_Q[II]) prit[II] <= 5'd0;
else if (prit[II] < 4'd2) prit[II] <= prit[II] + 1'b1;
else prit[II] <= prit[II];
else prit[II] <= prit[II];
end
end
end
always @(posedge wclk, negedge wrst_n) begin : PRI_POINT_BLOCK
integer II;
if (~wrst_n) pri_point <= 5'b00000;
else begin
for (II = 0; II < 5; II = II + 1) pri_point[II] <= prit[II] == 5'd1;
end
end
always @(posedge wclk, negedge wrst_n) begin
if (~wrst_n) last_next_point <= 5'b00000;
else
casex (pri_point)
5'bxxxx1: last_next_point <= 5'b00001;
5'bxxx10: last_next_point <= 5'b00010;
5'bxx100: last_next_point <= 5'b00100;
5'bx1000: last_next_point <= 5'b01000;
5'b10000: last_next_point <= 5'b10000;
default: last_next_point <= 5'b00001;
endcase
end
endmodule
| 7.033211 |
module baseaddr_loop_A2 (
input wclk,
input wrst_n,
input enable,
input wr_vs,
input [4:0] rd0_curr_point,
input [4:0] rd1_curr_point,
input [4:0] rd2_curr_point,
output reg [4:0] wr_current_point,
output reg [4:0] last_next_point
);
wire wr_vs_raising, wr_vs_falling;
edge_generator #(
.MODE("NORMAL") // FAST NORMAL BEST
) edge_wr_vsync_inst (
.clk (wclk),
.rst_n (wrst_n),
.in (wr_vs && enable),
.raising(wr_vs_raising),
.falling(wr_vs_falling)
);
reg [4:0] wr_next_point, wr_next_point_Q;
reg [4:0] wr0_curr_point;
reg [3:0] prit[4:0];
reg [4:0] pri_point;
always @(posedge wclk, negedge wrst_n)
if (~wrst_n) wr_current_point <= 5'b00001;
else if (wr_vs_raising) wr_current_point <= wr_next_point_Q;
else wr_current_point <= wr_current_point;
always @(posedge wclk, negedge wrst_n)
if (~wrst_n) wr_next_point_Q <= 5'b00000;
else
casex (wr_next_point)
5'bxxxx1: wr_next_point_Q <= 5'b00001;
5'bxxx10: wr_next_point_Q <= 5'b00010;
5'bxx100: wr_next_point_Q <= 5'b00100;
5'bx1000: wr_next_point_Q <= 5'b01000;
5'b10000: wr_next_point_Q <= 5'b10000;
default: wr_next_point_Q <= 5'b00001;
endcase
always @(posedge wclk, negedge wrst_n)
if (~wrst_n) wr_next_point <= 5'b00001;
else wr_next_point <= ~(wr_current_point | rd0_curr_point | rd1_curr_point | rd2_curr_point);
always @(posedge wclk, negedge wrst_n) begin : prit_BLOCK
integer II;
if (~wrst_n) begin
for (II = 0; II < 5; II = II + 1) prit[II] <= 4'd2;
end else begin
for (II = 0; II < 5; II = II + 1) begin
if (wr_vs_raising)
if (wr_next_point_Q[II]) prit[II] <= 5'd0;
else if (prit[II] < 4'd2) prit[II] <= prit[II] + 1'b1;
else prit[II] <= prit[II];
else prit[II] <= prit[II];
end
end
end
always @(posedge wclk, negedge wrst_n) begin : PRI_POINT_BLOCK
integer II;
if (~wrst_n) pri_point <= 5'b00000;
else begin
for (II = 0; II < 5; II = II + 1) pri_point[II] <= prit[II] == 5'd1;
end
end
always @(posedge wclk, negedge wrst_n) begin
if (~wrst_n) last_next_point <= 5'b00000;
else
casex (pri_point)
5'bxxxx1: last_next_point <= 5'b00001;
5'bxxx10: last_next_point <= 5'b00010;
5'bxx100: last_next_point <= 5'b00100;
5'bx1000: last_next_point <= 5'b01000;
5'b10000: last_next_point <= 5'b10000;
default: last_next_point <= 5'b00001;
endcase
end
endmodule
| 7.033211 |
module baseball_rom_synth (
a,
spo
);
input [7 : 0] a;
output [7 : 0] spo;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
| 7.517011 |
module baseram (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [14:0] address;
input [1:0] byteena;
input clock;
input [15:0] data;
input rden;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
| 6.515975 |
module base_3xMUX5to1 (
input [2:0] S,
input [2:0] U,
V,
W,
X,
Y,
output reg [2:0] M
);
always @(*) begin
case (S)
3'b000: begin
M = U;
end
3'b001: begin
M = V;
end
3'b010: begin
M = W;
end
3'b011: begin
M = X;
end
3'b100: begin
M = Y;
end
3'b101: begin
M = Y;
end
3'b110: begin
M = Y;
end
3'b111: begin
M = Y;
end
endcase
end
endmodule
| 7.746821 |
module base_8xMUX2to1 (
input s,
input [7:0] X,
Y,
output [7:0] M
);
assign M[7] = ((~s & X[7]) | (s & Y[7]));
assign M[6] = ((~s & X[6]) | (s & Y[6]));
assign M[5] = ((~s & X[5]) | (s & Y[5]));
assign M[4] = ((~s & X[4]) | (s & Y[4]));
assign M[3] = ((~s & X[3]) | (s & Y[3]));
assign M[2] = ((~s & X[2]) | (s & Y[2]));
assign M[1] = ((~s & X[1]) | (s & Y[1]));
assign M[0] = ((~s & X[0]) | (s & Y[0]));
//assign M = ((~s & X) | (s & Y));
endmodule
| 7.052027 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module base_auto_us_0_axi_register_slice_v2_1_15_axi_register_slice (
m_axi_rready,
mr_rvalid,
Q,
out,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
m_axi_rvalid,
E,
\aresetn_d_reg[1] ,
\aresetn_d_reg[0]
);
output m_axi_rready;
output mr_rvalid;
output [66:0] Q;
input out;
input m_axi_rlast;
input [1:0] m_axi_rresp;
input [63:0] m_axi_rdata;
input m_axi_rvalid;
input [0:0] E;
input \aresetn_d_reg[1] ;
input \aresetn_d_reg[0] ;
wire [0:0] E;
wire [66:0] Q;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1] ;
wire [63:0] m_axi_rdata;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0] m_axi_rresp;
wire m_axi_rvalid;
wire mr_rvalid;
wire out;
base_auto_us_0_axi_register_slice_v2_1_15_axic_register_slice__parameterized2 \r.r_pipe (
.E(E),
.Q(Q),
.\aresetn_d_reg[0] (\aresetn_d_reg[0] ),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.mr_rvalid(mr_rvalid),
.out(out)
);
endmodule
| 6.616439 |
module base_auto_us_0_axi_register_slice_v2_1_15_axi_register_slice__parameterized0 (
\aresetn_d_reg[1] ,
s_ready_i_reg,
sr_arvalid,
in,
m_axi_arburst,
m_axi_araddr,
s_axi_arready,
Q,
m_axi_arsize,
s_axi_aresetn,
out,
cmd_push_block_reg,
s_axi_arvalid,
D
);
output \aresetn_d_reg[1] ;
output s_ready_i_reg;
output sr_arvalid;
output [27:0] in;
output [1:0] m_axi_arburst;
output [31:0] m_axi_araddr;
output s_axi_arready;
output [15:0] Q;
output [2:0] m_axi_arsize;
input s_axi_aresetn;
input out;
input cmd_push_block_reg;
input s_axi_arvalid;
input [60:0] D;
wire [60:0] D;
wire [15:0] Q;
wire \aresetn_d_reg[1] ;
wire cmd_push_block_reg;
wire [27:0] in;
wire [31:0] m_axi_araddr;
wire [1:0] m_axi_arburst;
wire [2:0] m_axi_arsize;
wire out;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_ready_i_reg;
wire sr_arvalid;
base_auto_us_0_axi_register_slice_v2_1_15_axic_register_slice \ar.ar_pipe (
.D(D),
.Q(Q),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1] ),
.cmd_push_block_reg(cmd_push_block_reg),
.in(in),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arsize(m_axi_arsize),
.out(out),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(s_ready_i_reg),
.sr_arvalid(sr_arvalid)
);
endmodule
| 6.616439 |
module base_auto_us_1_axi_register_slice_v2_1_15_axi_register_slice (
sr_awvalid,
s_axi_awready,
in,
m_axi_awburst,
m_axi_awaddr,
Q,
m_axi_awsize,
out,
\USE_RTL_VALID_WRITE.buffer_Full_q_reg ,
s_axi_awvalid,
s_axi_aresetn,
m_axi_awready,
cmd_push_block_reg,
SR,
D
);
output sr_awvalid;
output s_axi_awready;
output [27:0] in;
output [1:0] m_axi_awburst;
output [31:0] m_axi_awaddr;
output [15:0] Q;
output [2:0] m_axi_awsize;
input out;
input \USE_RTL_VALID_WRITE.buffer_Full_q_reg ;
input s_axi_awvalid;
input s_axi_aresetn;
input m_axi_awready;
input cmd_push_block_reg;
input [0:0] SR;
input [60:0] D;
wire [60:0] D;
wire [15:0] Q;
wire [0:0] SR;
wire \USE_RTL_VALID_WRITE.buffer_Full_q_reg ;
wire cmd_push_block_reg;
wire [27:0] in;
wire [31:0] m_axi_awaddr;
wire [1:0] m_axi_awburst;
wire m_axi_awready;
wire [2:0] m_axi_awsize;
wire out;
wire s_axi_aresetn;
wire s_axi_awready;
wire s_axi_awvalid;
wire sr_awvalid;
base_auto_us_1_axi_register_slice_v2_1_15_axic_register_slice \aw.aw_pipe (
.D(D),
.Q(Q),
.SR(SR),
.\USE_RTL_VALID_WRITE.buffer_Full_q_reg (\USE_RTL_VALID_WRITE.buffer_Full_q_reg ),
.cmd_push_block_reg(cmd_push_block_reg),
.in(in),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awready(m_axi_awready),
.m_axi_awsize(m_axi_awsize),
.out(out),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.sr_awvalid(sr_awvalid)
);
endmodule
| 6.616439 |
modules
`timescale 1ns / 1ps
module basecell_ha(f1_i, f2_i, b_i, sum_o, c_o);
input f1_i, f2_i, b_i;
output sum_o, c_o;
wire pp;
assign pp = f1_i & f2_i;
HA adder(pp, b_i, sum_o, c_o);
endmodule
| 7.369394 |
module basecell_fa (
f1_i,
f2_i,
b_i,
c_i,
sum_o,
c_o
);
input f1_i, f2_i, b_i, c_i;
output sum_o, c_o;
wire pp;
assign pp = f1_i & f2_i;
FA adder (
pp,
b_i,
c_i,
sum_o,
c_o
);
endmodule
| 7.196538 |
module HA (
A,
B,
S,
Cout
);
input A, B;
output S, Cout;
assign S = A ^ B;
assign Cout = A & B;
endmodule
| 7.265208 |
module d_flip_flop (
q,
d,
clk
);
output reg q;
input d, clk;
always @(*) begin
if (clk) begin
q <= d;
end
end
endmodule
| 7.497066 |
module inv_tri_buffer (
q,
d,
OE
);
output q;
input d, OE;
assign q = (OE) ? 1'bZ : ~d;
endmodule
| 7.12638 |
module octal_d_flip_flop (
q,
d,
OE,
CP
);
output wire [7:0] q;
wire [7:0] q_mid;
input [7:0] d;
input OE, CP;
d_flip_flop dff0 (
q_mid[0],
d[0],
CP
);
d_flip_flop dff1 (
q_mid[1],
d[1],
CP
);
d_flip_flop dff2 (
q_mid[2],
d[2],
CP
);
d_flip_flop dff3 (
q_mid[3],
d[3],
CP
);
d_flip_flop dff4 (
q_mid[4],
d[4],
CP
);
d_flip_flop dff5 (
q_mid[5],
d[5],
CP
);
d_flip_flop dff6 (
q_mid[6],
d[6],
CP
);
d_flip_flop dff7 (
q_mid[7],
d[7],
CP
);
tri_buffer tr0 (
q[0],
q_mid[0],
OE
);
tri_buffer tr1 (
q[1],
q_mid[1],
OE
);
tri_buffer tr2 (
q[2],
q_mid[2],
OE
);
tri_buffer tr3 (
q[3],
q_mid[3],
OE
);
tri_buffer tr4 (
q[4],
q_mid[4],
OE
);
tri_buffer tr5 (
q[5],
q_mid[5],
OE
);
tri_buffer tr6 (
q[6],
q_mid[6],
OE
);
tri_buffer tr7 (
q[7],
q_mid[7],
OE
);
endmodule
| 7.112496 |
module quad_adder (
s,
a,
b,
c_in,
c_out
);
output wire [3:0] s;
output c_out;
input [3:0] a, b;
input c_in;
assign {c_out, s} = (a + b + c_in);
endmodule
| 8.178474 |
module demux_2_4 (
o,
a0,
a1,
e
);
output [3:0] o;
input a0, a1, e;
assign o[0] = ~(~e & ~a0 & ~a1);
assign o[1] = ~(~e & a0 & ~a1);
assign o[2] = ~(~e & ~a0 & a1);
assign o[3] = ~(~e & a0 & a1);
endmodule
| 6.918606 |
module generates a frequency based on an input note.
//1 is a C2. The frequencies generated are 64x the desired frequency.
module base_freq_genx64(
note_in,
clk50mhz,
freq_out,
offset_mult,
offset_dir
);
input clk50mhz;
input [5:0] note_in;
input [2:0] offset_mult;
input offset_dir; //offset direction: 0: lower pitch, 1: higher pitch
//wire offset_direction;
integer base_freq;
reg [15:0] count;
output reg freq_out;
wire [31:0] base_freq_wire;
reg [3:0] offset;
assign base_freq_wire = (offset_dir == 0)? base_freq - (offset * offset_mult) : base_freq + (offset * offset_mult) ;
initial
begin
count <= 0;
freq_out <= 0;
offset <= 0;
end
//assign offset_direction = (offset_dir == 0 ) ? :
//(prev_note_A>note_in) ? (prev_note_A - note_in) : (note_in - prev_note_A);
//base_freq = x + (offset * offset_mult * offset_dir)
always@(posedge clk50mhz)
begin
case(note_in)
0: base_freq <= 12654; //having this as zero breaks the enable bit on the generator.
1: base_freq <= 11945;
2: base_freq <= 11274;
3: base_freq <= 10641;
4: base_freq <= 10044;
5: base_freq <= 9480;
6: base_freq <= 8948;
7: base_freq <= 8446;
8: base_freq <= 7972;
9: base_freq <= 7525;
10: base_freq <= 7102;
11: base_freq <= 6704;
12: base_freq <= 6327;
13: base_freq <= 5972;
14: base_freq <= 5637;
15: base_freq <= 5321;
16: base_freq <= 5022;
17: base_freq <= 4740;
18: base_freq <= 4474;
19: base_freq <= 4223;
20: base_freq <= 3986;
21: base_freq <= 3762;
22: base_freq <= 3551;
23: base_freq <= 3352;
24: base_freq <= 3164;
25: base_freq <= 2986;
26: base_freq <= 2819;
27: base_freq <= 2660;
28: base_freq <= 2511;
29: base_freq <= 2370;
30: base_freq <= 2237;
31: base_freq <= 2112;
32: base_freq <= 1993;
33: base_freq <= 1881;
34: base_freq <= 1776;
35: base_freq <= 1676;
36: base_freq <= 1582;
37: base_freq <= 1493;
38: base_freq <= 1409;
39: base_freq <= 1330;
40: base_freq <= 1256;
41: base_freq <= 1185;
42: base_freq <= 1119;
43: base_freq <= 1056;
44: base_freq <= 997;
45: base_freq <= 941;
46: base_freq <= 888;
47: base_freq <= 838;
48: base_freq <= 791;
49: base_freq <= 747;
50: base_freq <= 705;
51: base_freq <= 665;
52: base_freq <= 628;
53: base_freq <= 593;
54: base_freq <= 559;
55: base_freq <= 528;
56: base_freq <= 498;
57: base_freq <= 470;
58: base_freq <= 444;
59: base_freq <= 419;
60: base_freq <= 395;
61: base_freq <= 373;
62: base_freq <= 352;
63: base_freq <= 333;
default: base_freq <= 0;
endcase
if(note_in <= 63 && note_in > 47)
begin
offset <= 1;
end
else if(note_in <= 47 && note_in > 31)
begin
offset <= 2;
end
else if(note_in <= 31 && note_in > 15)
begin
offset <= 5;
end
else if(note_in <= 15)
begin
offset <= 13;
end
/*
if(offset_dir == 0) //offset_dir = 0 means the offset is negative
begin
base_freq <= base_freq - (offset * offset_mult * offset_dir);
end
else if(offset_dir == 1) //offset_dir = 1 means the offset is positive
begin
base_freq <= base_freq + (offset * offset_mult * offset_dir);
end
*/
if(count >= base_freq_wire)
begin
freq_out <= ~freq_out; //generate the output frequency
count <= 0;
end
else
begin
count <= count + 1;
end
if (base_freq == 0) //don't do anything if our base frequency is zero
begin
freq_out <= 0;
end
//count <= count + 1;//increment counter for outputting frequency
end
endmodule
| 6.867098 |
module base_generator #(
parameter FPGA_FAMILY = "ALTERA",
parameter X_W = 16,
parameter E_W = 16,
parameter W_W = 16
) (
input clk,
input rst_n,
input en,
input signed [ X_W-1:0] xin,
input signed [ E_W-1:0] err,
output signed [X_W+W_W-1:0] yout,
output reg signed [ W_W-1:0] wout,
output reg update
);
wire signed [X_W+E_W-1:0] coef_tmp; // xin * err
reg signed [ X_W+E_W:0] coef_nxt; // wout(k+1)
reg signed [X_W+E_W-1:0] coef; // wout(k)
reg signed [ X_W-1:0] x_r; // Save xin value for later calculation
reg signed [ E_W-1:0] e_r; // Save err value for later calculation
reg [ 2:0] state;
//因为调用了Altera的IP核，不使用Altera就用*代替
generate
if (FPGA_FAMILY == "ALTERA") begin
mult16 m1 (
.dataa (x_r),
.datab (e_r),
.result(coef_tmp)
);
mult16 m2 (
.dataa (x_r),
.datab (wout),
.result(yout)
);
end else begin
assign coef_tmp = x_r * e_r;
assign yout = x_r * wout;
end
endgenerate
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= 'd0;
coef_nxt <= 'd0;
coef <= 'd0;
wout <= 'd0;
update <= 'd0;
x_r <= 'd0;
e_r <= 'd0;
end else
case (state)
3'd0: begin
if (en) begin
state <= 3'd1;
x_r <= xin;
e_r <= err;
end
update <= 1'b0;
end
3'd1: begin
coef_nxt <= coef_tmp + coef;
coef <= coef_nxt[X_W-1+E_W:0];
wout <= coef_nxt[X_W-1+E_W-:W_W];
state <= 3'd0;
update <= 1'b1;
end
default: state <= 3'd0;
endcase
end
endmodule
| 6.777899 |
module base_ram (
input logic clk,
input logic nrst,
input logic we,
input logic re,
input logic [7:0] raddr1,
input logic [7:0] raddr2,
input logic [7:0] waddr,
input logic [31:0] wdata,
output logic [31:0] rdataA,
output logic [31:0] rdataB
);
logic [31:0] mem[255:0]; //Define memory of size to hold 8 elements of 32 VRs
always_ff @(posedge clk, negedge nrst) begin
if (!nrst) begin
rdataA <= 'hdead_dead;
rdataB <= 'hdead_dead;
end else if (we && !re) begin
mem[waddr] <= wdata;
rdataA <= rdataA;
rdataB <= rdataB;
end else if (re && !we) begin
rdataA <= mem[raddr1];
rdataB <= mem[raddr2];
//wdata <= wdata;
end else if (we && re) begin
mem[waddr] <= wdata;
rdataA <= mem[raddr1];
rdataB <= mem[raddr2];
end else begin
rdataA <= rdataA;
rdataB <= rdataB;
end
end
endmodule
| 7.454095 |
module base_rst_ps7_0_50M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 66666672, PHASE 0.000, CLK_DOMAIN base_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0] bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0] interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0] peripheral_aresetn;
wire [0:0] peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
base_rst_ps7_0_50M_0_proc_sys_reset U0 (
.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk)
);
endmodule
| 7.24774 |
module base_rst_ps7_0_50M_0_cdc_sync (
lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0] asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0] asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (
.C (slowest_sync_clk),
.CE(1'b1),
.D (asr_d1),
.Q (s_level_out_d1_cdc_to),
.R (1'b0)
);
LUT1 #(
.INIT(2'h1)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1 (
.I0(aux_reset_in),
.O (asr_d1)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d1_cdc_to),
.Q (s_level_out_d2),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d2),
.Q (s_level_out_d3),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d3),
.Q (scndry_out),
.R (1'b0)
);
LUT5 #(
.INIT(32'hEAAAAAA8)
) lpf_asr_i_1 (
.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O (lpf_asr_reg)
);
endmodule
| 7.24774 |
module base_rst_ps7_0_50M_0_cdc_sync_0 (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0] p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q (s_level_out_d1_cdc_to),
.R (1'b0)
);
LUT2 #(
.INIT(4'hB)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0 (
.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O (\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 )
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d1_cdc_to),
.Q (s_level_out_d2),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d2),
.Q (s_level_out_d3),
.R (1'b0)
);
(* ASYNC_REG *) (* XILINX_LEGACY_PRIM = "FDR" *) (* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0)
) \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4 (
.C (slowest_sync_clk),
.CE(1'b1),
.D (s_level_out_d3),
.Q (scndry_out),
.R (1'b0)
);
LUT5 #(
.INIT(32'hEAAAAAA8)
) lpf_exr_i_1 (
.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O (lpf_exr_reg)
);
endmodule
| 7.24774 |
module base_rst_ps7_0_50M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0] asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0] p_3_out;
wire slowest_sync_clk;
base_rst_ps7_0_50M_0_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX (
.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk)
);
base_rst_ps7_0_50M_0_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT (
.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[1].asr_lpf_reg[1] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_in1_in),
.Q (p_2_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[2].asr_lpf_reg[2] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_2_in),
.Q (p_1_in),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \AUX_LPF[3].asr_lpf_reg[3] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_1_in),
.Q (asr_lpf),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[1].exr_lpf_reg[1] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[3]),
.Q (p_3_out[2]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[2].exr_lpf_reg[2] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[2]),
.Q (p_3_out[1]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \EXT_LPF[3].exr_lpf_reg[3] (
.C (slowest_sync_clk),
.CE(1'b1),
.D (p_3_out[1]),
.Q (p_3_out[0]),
.R (1'b0)
);
(* XILINX_LEGACY_PRIM = "SRL16" *) (* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF)
) POR_SRL_I (
.A0 (1'b1),
.A1 (1'b1),
.A2 (1'b1),
.A3 (1'b1),
.CE (1'b1),
.CLK(slowest_sync_clk),
.D (1'b0),
.Q (Q)
);
FDRE #(
.INIT(1'b0)
) lpf_asr_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q (lpf_asr),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) lpf_exr_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q (lpf_exr),
.R (1'b0)
);
LUT4 #(
.INIT(16'hFFEF)
) lpf_int0 (
.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O (lpf_int0__0)
);
FDRE #(
.INIT(1'b0)
) lpf_int_reg (
.C (slowest_sync_clk),
.CE(1'b1),
.D (lpf_int0__0),
.Q (lpf_int),
.R (1'b0)
);
endmodule
| 7.24774 |
module base_rst_ps7_0_50M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0] bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0] peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0] interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0] peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0] bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0] interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0] peripheral_aresetn;
wire [0:0] peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (
.C (slowest_sync_clk),
.CE(1'b1),
.D (SEQ_n_3),
.Q (interconnect_aresetn),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (
.C (slowest_sync_clk),
.CE(1'b1),
.D (SEQ_n_4),
.Q (peripheral_aresetn),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \BSR_OUT_DFF[0].FDRE_BSR (
.C (slowest_sync_clk),
.CE(1'b1),
.D (Bsr_out),
.Q (bus_struct_reset),
.R (1'b0)
);
base_rst_ps7_0_50M_0_lpf EXT_LPF (
.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) FDRE_inst (
.C (slowest_sync_clk),
.CE(1'b1),
.D (MB_out),
.Q (mb_reset),
.R (1'b0)
);
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0)
) \PR_OUT_DFF[0].FDRE_PER (
.C (slowest_sync_clk),
.CE(1'b1),
.D (Pr_out),
.Q (peripheral_reset),
.R (1'b0)
);
base_rst_ps7_0_50M_0_sequence_psr SEQ (
.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk)
);
endmodule
| 7.24774 |
module base_rst_ps7_0_50M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1)
) \q_int[0]_i_1 (
.I0(Q[0]),
.O (q_int0[0])
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6)
) \q_int[1]_i_1 (
.I0(Q[0]),
.I1(Q[1]),
.O (q_int0[1])
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78)
) \q_int[2]_i_1 (
.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O (q_int0[2])
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80)
) \q_int[3]_i_1 (
.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O (q_int0[3])
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000)
) \q_int[4]_i_1 (
.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O (q_int0[4])
);
LUT1 #(
.INIT(2'h1)
) \q_int[5]_i_1 (
.I0(seq_clr),
.O (clear)
);
LUT6 #(
.INIT(64'h7FFFFFFF80000000)
) \q_int[5]_i_2 (
.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O (q_int0[5])
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[0] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[0]),
.Q (Q[0]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[1] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[1]),
.Q (Q[1]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[2] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[2]),
.Q (Q[2]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[3] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[3]),
.Q (Q[3]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[4] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[4]),
.Q (Q[4]),
.R (clear)
);
FDRE #(
.INIT(1'b1)
) \q_int_reg[5] (
.C (slowest_sync_clk),
.CE(seq_cnt_en),
.D (q_int0[5]),
.Q (Q[5]),
.R (clear)
);
endmodule
| 7.24774 |
module base_rx_mac (
// Host side of Rx MAC memory
input host_clk,
input [10:0] host_raddr,
output reg [15:0] host_rdata,
// port to Rx MAC memory
input rx_clk,
input [7:0] rx_mac_d,
input [11:0] rx_mac_a,
input rx_mac_wen,
// port to Rx MAC packet selector
output rx_mac_accept,
input [7:0] rx_mac_status_d,
input rx_mac_status_s
);
initial host_rdata = 0;
// Dual-port RAM
localparam aw = 11;
reg [7:0] pack_mem_l[0:(1<<aw)-1];
reg [7:0] pack_mem_h[0:(1<<aw)-1];
// Write from Ethernet, 8-bit port and therefore aw+1 address bits coming in
wire a_lsb = rx_mac_a[0];
wire [aw-1:0] a_msb = rx_mac_a[aw:1];
always @(posedge rx_clk)
if (rx_mac_wen) begin
if (a_lsb) pack_mem_l[a_msb] <= rx_mac_d;
else pack_mem_h[a_msb] <= rx_mac_d;
end
// Read from host
wire [aw-1:0] raddr = host_raddr;
always @(posedge host_clk) host_rdata <= {pack_mem_h[raddr], pack_mem_l[raddr]};
// Accept valid IP packets addressed to us, that won't be handled by fabric.
// See comments regarding status_vec in scanner.v.
reg rx_mac_accept_r = 0;
always @(posedge rx_clk) if (rx_mac_status_s) rx_mac_accept_r <= rx_mac_status_d[4:0] == 5'b11100;
assign rx_mac_accept = rx_mac_accept_r;
endmodule
| 7.3496 |
module base_soc (
//base signals
input wire clk_i,
input wire reset_i,
//wb bus signals
output wire [31:0] wb_adr_o,
output wire [31:0] wb_dat_o,
input wire [31:0] wb_dat_i,
output wire wb_we_o,
output wire [3:0] wb_sel_o,
output wire wb_stb_o,
input wire wb_ack_i,
output wire wb_cyc_o,
//base peripheral signals
output wire [31:0] gpio_o,
input wire [31:0] gpio_i,
output wire spi_mosi_o,
output wire spi_sclk_o,
input wire spi_miso_i,
output wire tx_o,
input wire rx_i
);
wire [31:0] wb_dat_i_internal;
wire wb_ack_i_internal;
//wb ram
wire [31:0] wb_ram_dat_o;
wire wb_ram_ack_o;
//wb rom
wire [31:0] wb_rom_dat_o;
wire wb_rom_ack_o;
//wb gpio
wire [31:0] wb_gpio_dat_o;
wire wb_gpio_ack_o;
//wb uart
wire [31:0] wb_uart_dat_o;
wire wb_uart_ack_o;
//wb spi
wire [31:0] wb_spi_dat_o;
wire wb_spi_ack_o;
assign wb_ack_i_internal =
wb_ack_i | wb_ram_ack_o | wb_rom_ack_o | wb_gpio_ack_o | wb_uart_ack_o | wb_spi_ack_o;
assign wb_dat_i_internal =
wb_dat_i | wb_ram_dat_o | wb_rom_dat_o | wb_gpio_dat_o | wb_uart_dat_o | wb_spi_dat_o;
picorv32_wb #(
.ENABLE_MUL(0),
.ENABLE_IRQ(0),
.PROGADDR_RESET(32'h100000), //start of ROM
.STACKADDR(32'h001000) //end of RAM
) processor (
.mem_instr(),
.wb_clk_i (clk_i),
.wb_rst_i (reset_i),
.wbm_adr_o(wb_adr_o),
.wbm_dat_i(wb_dat_i_internal),
.wbm_stb_o(wb_stb_o),
.wbm_ack_i(wb_ack_i_internal),
.wbm_cyc_o(wb_cyc_o),
.wbm_dat_o(wb_dat_o),
.wbm_we_o (wb_we_o),
.wbm_sel_o(wb_sel_o)
);
//wb ram, 4KB
wb_memory #(
.BASE_ADR(32'h00000000),
.LOG_SIZE(10), //size in words
.MEMFILE("")
) ram (
.wb_clk_i(clk_i),
.wb_rst_i(reset_i),
.wb_adr_i(wb_adr_o),
.wb_dat_i(wb_dat_o),
.wb_sel_i(wb_sel_o),
.wb_we_i (wb_we_o),
.wb_cyc_i(wb_cyc_o),
.wb_stb_i(wb_stb_o),
.wb_ack_o(wb_ram_ack_o),
.wb_dat_o(wb_ram_dat_o)
);
//wb rom, 16KB
wb_memory #(
.BASE_ADR(32'h00100000),
.LOG_SIZE(12),
.MEMFILE ("src/firmware.hex")
) rom (
.wb_clk_i(clk_i),
.wb_rst_i(reset_i),
.wb_adr_i(wb_adr_o),
.wb_dat_i(wb_dat_o),
.wb_sel_i(wb_sel_o),
.wb_we_i (wb_we_o),
.wb_cyc_i(wb_cyc_o),
.wb_stb_i(wb_stb_o),
.wb_ack_o(wb_rom_ack_o),
.wb_dat_o(wb_rom_dat_o)
);
//wb uart
wb_simpleuart #(
.BASE_ADR(32'h02000000),
.DAT_ADR_OFFSET(32'h08),
.DIV_ADR_OFFSET(32'h04)
) uart (
.wb_clk_i(clk_i),
.wb_rst_i(reset_i),
.wb_adr_i(wb_adr_o),
.wb_dat_i(wb_dat_o),
.wb_sel_i(wb_sel_o),
.wb_we_i (wb_we_o),
.wb_cyc_i(wb_cyc_o),
.wb_stb_i(wb_stb_o),
.wb_ack_o(wb_uart_ack_o),
.wb_dat_o(wb_uart_dat_o),
.rx (rx_i),
.tx (tx_o)
);
//wb gpio
wb_gpio #(
.BASE_ADR(32'h02100000)
) gpio (
.wb_clk_i(clk_i),
.wb_rst_i(reset_i),
.wb_adr_i(wb_adr_o),
.wb_dat_i(wb_dat_o),
.wb_sel_i(wb_sel_o),
.wb_we_i (wb_we_o),
.wb_cyc_i(wb_cyc_o),
.wb_stb_i(wb_stb_o),
.wb_ack_o(wb_gpio_ack_o),
.wb_dat_o(wb_gpio_dat_o),
.gpio_i (gpio_i),
.gpio_o (gpio_o)
);
//wb spi
wb_spi #(
.BASE_ADR(32'h02200000)
) spi (
.wb_clk_i(clk_i),
.wb_rst_i(reset_i),
.wb_adr_i(wb_adr_o),
.wb_dat_i(wb_dat_o),
.wb_sel_i(wb_sel_o),
.wb_we_i (wb_we_o),
.wb_cyc_i(wb_cyc_o),
.wb_stb_i(wb_stb_o),
.wb_ack_o(wb_spi_ack_o),
.wb_dat_o(wb_spi_dat_o),
.miso (spi_miso_i),
.mosi (spi_mosi_o),
.sclk (spi_sclk_o)
);
endmodule
| 7.193989 |
module: base
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module base_tb;
// Inputs
reg clk;
reg rst;
// Outputs
wire out;
wire err_en;
wire err_ctrl;
wire sh_clk;
wire sh_rst;
wire c_en;
wire dump_en;
wire ch_out;
wire ch_out_vld;
wire ch_out_done;
// Instantiate the Unit Under Test (UUT)
base uut (
.clk(clk),
.rst(rst),
.out(out),
.err_en(err_en),
.err_ctrl(err_ctrl),
.sh_clk(sh_clk),
.sh_rst(sh_rst),
.c_en(c_en),
.dump_en(dump_en),
.ch_out(ch_out),
.ch_out_vld(ch_out_vld),
.ch_out_done(ch_out_done)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.175384 |
module and2 (
a,
b,
y
);
input a, b;
output y;
assign y = a & b;
endmodule
| 7.692856 |
module nand2 (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a & b);
endmodule
| 9.068616 |
module or2 (
a,
b,
y
);
input a, b;
output y;
assign y = a | b;
endmodule
| 8.2416 |
module nor2 (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a | b);
endmodule
| 8.286761 |
module xor2 (
a,
b,
y
);
input a, b;
output y;
assign y = a ^ b;
endmodule
| 8.694233 |
module mux2 (
in1,
in0,
select,
out
);
parameter WIDTH = 1;
input [WIDTH-1:0] in0, in1;
input select;
output [WIDTH-1:0] out;
assign out = (select) ? in1 : in0;
endmodule
| 7.816424 |
module mux10_1bit (in, select, out);
// input [9:0] in;
// input [3:0] select;
// output out;
// case(select)
// 4'b0000: out = in[0];
// 4'b0001: out = in[1];
// 4'b0010: out = in[2];
// 4'b0011: out = in[3];
// 4'b0100: out = in[4];
// 4'b0101: out = in[5];
// 4'b0110: out = in[6];
// 4'b0111: out = in[7];
// 4'b1000: out = in[8];
// 4'b1001: out = in[9];
// endcase
// endmodule
| 8.025449 |
module mux_1bit (
in,
select,
out
);
parameter IN_WIDTH = 2;
parameter SEL_WIDTH = 1;
input [IN_WIDTH-1:0] in;
input [SEL_WIDTH-1:0] select;
output out;
assign out = in[select];
endmodule
| 8.087151 |
module register (
clk,
rst,
D,
Q,
wen
);
parameter WIDTH = 1;
input clk, rst, wen;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
always @(posedge clk or posedge rst) begin
if (rst) begin
Q <= {(WIDTH) {1'b0}};
end else if (wen) begin
Q <= D;
end
end
endmodule
| 6.542519 |
module BasicCORE (
input [31:0] instr,
output [6:0] order,
output reg [4:0] A1,
output reg [4:0] A2,
output reg [4:0] A3
);
wire [5:0] opcode = instr[31:26];
wire [5:0] funcode = instr[5:0];
wire [4:0] rs, rt, rd;
assign rs = instr[25:21];
assign rt = instr[20:16];
assign rd = instr[15:11];
CORE core (
.instr(instr),
.order(order)
);
always @(*)
case (order)
`addu, `subu, `ori, `lw, `sw, `beq, `jr: A1 = rs;
default: A1 = 0;
endcase
always @(*)
case (order)
`sw, `addu, `subu, `beq: A2 = rt;
default: A2 = 0;
endcase
always @(*)
case (order)
`addu, `subu: A3 = rd;
`jal: A3 = 5'd31;
`ori, `lw, `lui: A3 = rt;
default: A3 = 0;
endcase
endmodule
| 7.373694 |
module adder (
q,
a,
b
);
input a, b;
output [1:0] q;
assign q = {1'b0, a} + {1'b0, b};
endmodule
| 7.555649 |
module mul (
q,
a,
b
);
input a, b;
output [1:0] q;
assign q = {1'b0, a} * {1'b0, b};
endmodule
| 7.034324 |
module adder (
q,
a,
b
);
input a, b;
output [1:0] q;
assign q = a + b;
endmodule
| 7.555649 |
module BasicGates (
input1,
input2,
output_and,
output_or,
output_not,
output_nand,
output_nor,
output_xor
);
input input1;
input input2;
output output_and;
output output_or;
output output_not;
output output_nand;
output output_nor;
output output_xor;
assign output_and = input1 & input2;
assign output_or = input1 | input2;
assign output_not = ~input1;
assign output_nand = ~(input1 & input2);
assign output_nor = ~(input1 | input2);
assign output_xor = (~input1 & input2) | (input1 & ~input2);
endmodule
| 7.884618 |
module BasicGates_tb;
wire t_y1, t_y2, t_y3, t_y4, t_y5, t_y6;
reg t_a, t_b;
BasicGates my_gates (
.input1(t_a),
.input2(t_b),
.output_and(t_y1),
.output_or(t_y2),
.output_not(t_y3),
.output_nand(t_y4),
.output_nor(t_y5),
.output_xor(t_y6)
);
initial begin
$monitor(t_a, t_b, t_y1, t_y2, t_y3, t_y4, t_y5, t_y6);
t_a = 1'b0;
t_b = 1'b0;
#50 t_a = 1'b0;
t_b = 1'b1;
#50 t_a = 1'b1;
t_b = 1'b0;
#50 t_a = 1'b1;
t_b = 1'b1;
end
endmodule
| 6.526518 |
module mux #(
parameter integer LENGTH = 32
) (
in1,
in2,
sel,
out
);
input sel;
input [LENGTH-1:0] in1, in2;
output [LENGTH-1:0] out;
assign out = (sel == 0) ? in1 : in2;
endmodule
| 8.575874 |
module mux_3input #(
parameter integer LENGTH = 32
) (
in1,
in2,
in3,
sel,
out
);
input [LENGTH-1:0] in1, in2, in3;
input [1:0] sel;
output [LENGTH-1:0] out;
assign out = (sel == 2'd0) ? in1 : (sel == 2'd1) ? in2 : in3;
endmodule
| 8.526131 |
module register (
clk,
reset,
writeEn,
regIn,
regOut
); //PC
input clk, reset, writeEn;
input [31:0] regIn;
output reg [31:0] regOut;
always @(posedge clk) begin
if (reset == 1) regOut <= 0;
else if (writeEn) regOut <= regIn;
end
endmodule
| 6.542519 |
module regFile (
clk,
rst,
src1,
src2,
dest,
writeVal,
writeEn,
reg1,
reg2
);
input clk, rst, writeEn;
input [`REG_FILE_ADDR_LEN-1:0] src1, src2, dest;
input [`WORD_LEN-1:0] writeVal;
output [`WORD_LEN-1:0] reg1, reg2;
reg [`WORD_LEN-1:0] regMem[0:`REG_FILE_SIZE-1];
integer i;
always @(negedge clk) begin
if (rst) begin
for (i = 0; i < `WORD_LEN; i = i + 1) regMem[i] <= 0;
end else if (writeEn) regMem[dest] <= writeVal;
regMem[0] <= 0;
end
assign reg1 = (regMem[src1]);
assign reg2 = (regMem[src2]);
endmodule
| 7.797802 |
module signExtend (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out = (in[15] == 1) ? {16'b1111111111111111, in} : {16'b0000000000000000, in};
endmodule
| 7.397526 |
module ALU (
val1,
val2,
EXE_CMD,
aluOut
);
input [`WORD_LEN-1:0] val1, val2;
input [`EXE_CMD_LEN-1:0] EXE_CMD;
output reg [`WORD_LEN-1:0] aluOut;
always @(*) begin
case (EXE_CMD)
`EXE_ADD: aluOut <= val1 + val2;
`EXE_SUB: aluOut <= val1 - val2;
`EXE_AND: aluOut <= val1 & val2;
`EXE_OR: aluOut <= val1 | val2;
`EXE_NOR: aluOut <= ~(val1 | val2);
`EXE_XOR: aluOut <= val1 ^ val2;
`EXE_SLA: aluOut <= val1 << val2;
`EXE_SLL: aluOut <= val1 <<< val2;
`EXE_SRA: aluOut <= val1 >> val2;
`EXE_SRL: aluOut <= val1 >>> val2;
default: aluOut <= 0;
endcase
end
endmodule
| 7.896404 |
module basicProcessor_tb ();
reg [31:0] memory[31:0];
reg [31:0] instruction[31:0];
reg clk;
reg reset;
wire [31:0] memOut, memAddress, instructionAddress;
wire WE;
reg [31:0] cycleCount;
localparam [31:0] noOp = 32'h00000000;
localparam [1:0] Load = 2'b01;
localparam [1:0] mem = 2'b00;
localparam [1:0] immediate = 2'b01;
localparam [1:0] write = 2'b10;
localparam [1:0] move = 2'b11;
localparam [1:0] jump = 2'b10;
localparam [1:0] unconditional = 2'b00;
localparam [1:0] equal = 2'b01;
localparam [1:0] notEqual = 2'b10;
localparam [1:0] negative = 2'b11;
localparam [1:0] alu = 2'b11;
always @(posedge clk) begin
if (WE) begin
memory[memAddress] <= memOut;
$display("Memory Written address = %h, value = %d", memAddress, memOut);
end
end
initial begin
$readmemh("program.hex", instruction);
$monitor("Time %t, instruction address = %h", $time, instructionAddress);
//set instruction memory
// instruction[0] = noOp; //NO op
// instruction[1] = {Load,immediate,4'h0,24'd13}; //Load 13 to reg 0
// instruction[2] = {Load,immediate,4'h1,24'd17}; //load 17 to reg 1
// instruction[3] = {Load,immediate,4'h2,24'h0}; //load 0 to reg 2
// instruction[4] = {Load,immediate,4'h3,24'h1}; //load 1 to reg 3
// instruction[5] = {Load,immediate,4'h4,24'h0}; //load 0 to reg 4
// instruction[6] = {Load,immediate,4'h5,24'hffffff}; //load ffffff to reg 5 (for subtracting)
// instruction[7] = {Load,immediate,4'h6,24'hff}; //load ff to reg 6 (for subtracting)
// instruction[8] = {alu,2'b00,4'h8,8'h5,8'h5,8'h5}; //Shift reg 5 8 bits
// instruction[9] = {alu,2'b01,4'b0,8'h5,8'h5,8'h6}; //or ff to ffffff00 to get our negative 1
// instruction[10] = {alu,2'b11,4'h0,8'h1,8'h1,8'h0}; //add reg 1 to reg 0 store in reg 1
// instruction[11] = {Load,write,4'h4,8'h1,16'h0000}; //store created value in memory at address in reg 4
// instruction[12] = {alu,2'b11,4'h0,8'h4,8'h4,8'h3}; //add 1 to reg 4
// instruction[13] = {alu,2'b10,4'h0,8'h7,8'h0,8'h5}; //xor reg 0 to reg 5 (for subtraction)
// instruction[14] = {alu,2'b11,4'h0,8'h7,8'h7,8'h3}; //add 1 to get negative reg 0
// instruction[15] = {alu,2'b11,4'h0,8'h7,8'h7,8'h4}; //add to reg 4 to see if result is negative
// instruction[16] = {jump,negative,4'h1,24'ha}; //loop back to instruction 10 13 times
// instruction[17] = noOp; //NO op
// instruction[18] = noOp; //NO op
// instruction[19] = noOp; //NO op
// instruction[20] = noOp; //NO op
// instruction[21] = {jump,unconditional,4'h0,8'h4,16'h0000}; //jump to instruction 0
// $writememb("instructions_binary.txt",instruction);
// $writememh("instructions_hex.txt",instruction);
reset = 1'b1;
#20;
reset = 1'b0;
#20;
cycleCount = 0;
clk = 0;
#8000;
$writememh("memory_out.hex", memory);
$writememh("register_out.hex", p.reg0.regfile);
$finish;
end
always begin
$display("Cycle %d", cycleCount);
clk = 0;
#20;
$display("A = %h, B = %h, nPC = %h, op = %b, isTakenBranch = %b, fZero = %b, fNegative = %b",
p.A, p.B, p.nPC, p.op, p.isTakenBranch, p.fZero, p.fNegative);
$display("isALU = %b, aluOut = %h, nFN = %b", p.isALU, p.aluOut, p.nFN);
clk = 1;
#20;
cycleCount = cycleCount + 1;
end
Processor p (
.memoryIn(memory[memAddress]),
.memoryOut(memOut),
.memoryAddress(memAddress),
.memoryWE(WE),
.instruction(instruction[instructionAddress]),
.instructionAddress(instructionAddress),
.reset(reset),
.clk(clk)
);
endmodule
| 7.234379 |
module as declared in thinpad_top.v
// to a basic RAM / ROM module.
// Author: LYL
// Created on: 2018/11/24
`timescale 1ns / 1ps
`include "defines.vh"
module BasicRamWrapper(
input wire clk,
// From MEM
input wire ce_i,
input wire we_i,
input wire[`DataAddrBus] addr_i,
input wire[3:0] sel_i,
input wire[`DataBus] data_i,
// To MEM
output reg[`DataBus] data_o,
// Adaptee protected (OK to write when !ce_i or !we_i)
inout wire[`InstBus] ram_data, // RAM
// Adaptee private
output reg[19:0] ram_addr, // RAMַ
output reg[3:0] ram_be_n, // RAMֽʹܣЧʹֽʹܣ뱣Ϊ0
output reg ram_ce_n, // RAMƬѡЧ
output reg ram_oe_n, // RAMʹܣЧ
output reg ram_we_n // RAMдʹܣЧ
);
// Tri-state, write to MEM
assign ram_data = (ce_i == `ChipEnable && we_i == `WriteEnable) ? data_i : {`DataWidth{1'bz}};
// Read data_o from ram_data
always @(*) begin
if (ce_i == `ChipEnable && we_i == `WriteDisable)
data_o <= ram_data;
else
data_o <= 0;
end
always @ (*) begin
ram_be_n <= 0;
ram_addr <= addr_i[21:2]; // Only use low 20 bits, index by 32-bit word
if (ce_i == `ChipDisable) begin
ram_ce_n <= 1;
ram_oe_n <= 1;
ram_we_n <= 1;
end else begin
ram_ce_n <= 0;
if (we_i == `WriteEnable) begin
ram_oe_n <= 1;
ram_we_n <= !clk; // LOW at the first half cycle, HIGH for the rest
ram_be_n <= ~sel_i; // Happily, their meanings are almost the same
end else begin
ram_oe_n <= 0;
ram_we_n <= 1;
end
end
end
endmodule
| 8.924335 |
module generator (
clk,
reset,
send
);
parameter SIM_CYLES = 10000;
parameter COOLDOWN_CYCLES = 2000;
output clk, reset, send;
reg clk, reset, send;
initial begin
clk = 0;
#0 reset = 1;
#2 reset = 0;
end
always begin
#1 clk = !clk;
end
initial $display("Start of simulation ...");
initial begin
$dumpfile("dump1.vcd");
$dumpvars(0, testbench);
end
initial begin
$display("Sending data ...");
send = 1;
#(SIM_CYLES) $display("Cooling down ...");
send = 0;
#(COOLDOWN_CYCLES) $display("End of simulation.");
$finish;
end
endmodule
| 7.128432 |
module sm (
clk,
rst,
st
);
input clk, rst;
output [1:0] st;
reg [1:0] st;
always @(posedge clk or posedge rst)
if (rst) st <= 2'b0;
else
case (st)
2'b00: st <= 2'b01;
2'b01: st <= 2'b11;
2'b11: st <= 2'b10;
2'b10: st <= 2'b00;
endcase
endmodule
| 6.695888 |
module sm (
clk,
rst,
st
);
input clk, rst;
output [1:0] st;
reg [1:0] st, next_st;
always @(posedge clk or posedge rst)
if (rst) st <= 2'b0;
else st <= next_st;
always @(st)
case (st)
2'b00: next_st <= 2'b01;
2'b01: next_st <= 2'b11;
2'b11: next_st <= 2'b10;
2'b10: next_st <= 2'b00;
endcase
endmodule
| 6.695888 |
module HazardUnit (
Rs1E,
Rs2E,
ForwardAE,
ForwardBE,
RdM,
RdW,
RegWriteM,
RegWriteW,
ResultSrc0,
RdE,
Rs1D,
Rs2D,
StallF,
StallD,
FlushE,
PCSrcE,
FlushD,
intrupt,
FlushM,
ret
);
input [4:0] Rs1E, Rs2E, Rs1D, Rs2D, RdE, RdM, RdW;
input RegWriteM, RegWriteW, ResultSrc0, PCSrcE, intrupt, ret;
output reg [1:0] ForwardAE, ForwardBE;
output reg StallF, StallD, FlushE, FlushD, FlushM;
reg lwStall;
always @(*) begin
if (((Rs1E == RdM) & RegWriteM) & (Rs1E != 0)) ForwardAE = 2'b10;
else if (((Rs1E == RdW) & RegWriteW) & (Rs1E != 0)) ForwardAE = 2'b01;
else ForwardAE = 2'b00;
end
always @(*) begin
if (((Rs2E == RdM) & RegWriteM) & (Rs2E != 0)) ForwardBE = 2'b10;
else if (((Rs2E == RdW) & RegWriteW) & (Rs2E != 0)) ForwardBE = 2'b01;
else ForwardBE = 2'b00;
end
always @(*) begin
lwStall = ResultSrc0 & ((Rs1D == RdE) || (Rs2D == RdE));
FlushE = lwStall || PCSrcE || intrupt;
StallD = lwStall;
StallF = lwStall;
FlushD = PCSrcE || intrupt || ret;
FlushM = intrupt;
end
endmodule
| 8.02365 |
module to generate the address of next instruction
// LOGIC: Add 1 in program counter if its a normal instruction
// Add address of label in PC if its a branch instruction
// other parameters can also be added based on Datapath and Controller Inputs/Outputs
//module adress_generator (output [31:0] pc, input PC_Src, input [31:0] immext,input rst,input clk);
// // Write your code here. This is not the part of Phase-I
// wire [31:0] Pc_next ,Pc_target ;
// always @ (posedge clk) begin
// if (rst) begin
// pc = 32'h00;
// end
// else begin
// adder(.a(pc),.b(32'd4),.y(Pc_next));
// adder(.a(pc),.b(immext),.y(Pc_target));
// mux2x1(.a(Pc_target),.b(Pc_next),.sel(PC_Src),.o(pc));
// end
//endmodule
| 7.132498 |
module that will carry the all instructions. PC value will be provided to this module and it will return the instuction
// other parameters can also be added based on Datapath and Controller Inputs/Outputs
module Instruction_Memory (input [31:0] pc,output reg [31:0] instruction);
always @ (*) begin
case(pc) //31
// 32'h0000: instruction = 32'h00002403;
// 32'h0004: instruction = 32'h00102483;
// 32'h0008: instruction = 32'h00202503;
// 32'h000c: instruction = 32'h00152583;
//32'h0000: instruction = 32'h00800413;//00000000110000000000010000010011;// a = 12
//32'h0004: instruction = 32'h00900493;//00000000100100000000010010010011;//4 b = 9
//not
//32'h0000: instruction = 32'h01900413;
//32'h0004: instruction = 32'h01400493;
//32'h0008: instruction = 32'h0x40940433;
// 32'h0008: instruction = 32'h00A00513;//00940c63;//32'b00000000100101000000011001100011;//8
// 32'h000c: instruction = 32'h00B00593; //00944663;//32'b00000000100101000000011001010101; //12
// 32'h0010: instruction = 32'h00B50633;//40940433;//32'b00100000100101000000010000110011;//16
// 32'h0014: instruction = 32'h00A606B3;//ff5ff06f;//32'b11111111010111111111000011101111;//20
// 32'h0018: instruction = 32'h00068713;//408484b3;//32'b00100000100001001000010010110011;//24
// 32'h001c: instruction = 32'hFED70EE3;//fedff06f;//32'b11111111010111111111000011101111;//28
//32'h0020: instruction = 32'hFEDA4AE3;//0000006f;//32
//32'h0024: instruction = 32'hFEFA06E3;//36
// 32'h0 : instruction = 32'h00b00513;
// 32'h4 : instruction = 32'h00e00593;
// 32'hc : instruction = 32'h00d00613;
// 32'h10 : instruction = 32'h01300693;
// 32'h14 : instruction = 32'h01800713;
// 32'h18 : instruction = 32'h00b569b3;
// 32'h1c : instruction = 32'h00c59a33;
// 32'h20 : instruction = 32'h40e68ab3;
// 32'h24 : instruction = 32'h00a00513;
// 32'h28 : instruction = 32'h00c00593;
// 32'h2c : instruction = 32'h00f00613;
// 32'h30 : instruction = 32'h01400693;
// 32'h34 : instruction = 32'h00d587b3;
// 32'h38 : instruction = 32'h00f68833;
// 32'h3c : instruction = 32'h00a02623;
// 32'h40 : instruction = 32'h00000013;
// 32'h44 : instruction = 32'h00000013;
// 32'h48 : instruction = 32'h00000013;
// 32'h4c : instruction = 32'h00000013;
// 32'h50 : instruction = 32'h00000013;
// 32'h54 : instruction = 32'h00c02883;
// 32'h58 : instruction = 32'h01100933;
// 32'h5c : instruction = 32'h01700663;
// 32'h60 : instruction = 32'h016b0b13;
// 32'h64 : instruction = 32'h00000663;
// 32'h68 : instruction = 32'h01700b93;
// 32'h6c : instruction = 32'hfe0008e3;
// 32'h70 : instruction = 32'h00000013;
// 32'h0 : instruction = 32'h01400A13;
// 32'h4 : instruction = 32'h00C00613;
// 32'h8 : instruction = 32'h00CA2023;
// 32'hc : instruction = 32'h000A2C83;
// 32'h10 : instruction = 32'h002C8713;
32'h0 : instruction = 32'h01400A13;
32'h4 : instruction = 32'h00C00613;
32'h8 : instruction = 32'h00800093;
32'hc : instruction = 32'h03200C93;
32'h10 : instruction = 32'h002C8713;
32'h14 : instruction = 32'h00100093;
32'h18 : instruction = 32'h00200113;
32'h1c : instruction = 32'h00300193;
32'h20 : instruction = 32'h00400213;
32'h24 : instruction = 32'h00500293;
32'h28 : instruction = 32'h03200313;
32'h2c : instruction = 32'h414303B3;
32'h30 : instruction = 32'h00008067;
endcase
end
endmodule
| 7.967585 |
module is called Data_Memory. It will consists of 256 byte memory unit. It will have
// one input as 8-bit address, 1 input flag wr that will decide if you want to read memory or write memory
module Data_Memory(output reg [31:0] Data_Out, input [31:0] Data_In, input [31:0] D_Addr, input wr, input clk );
reg [31:0] Mem [255:0]; // Data Memory
// Write your code here
always @(*) begin
Data_Out = Mem[D_Addr]; // Data Loading
Mem[5] = 5;
Mem[1] = 1;
Mem[2] = 2;
Mem[3] = 3;
end
always @(negedge clk) begin // Data Storing
if (wr)
Mem[D_Addr] = Data_In;
end
endmodule
| 7.273784 |
module is called Register_Memory. It will consists of 32 registers each of 32-bits. It will have
// one input flag wr that will decide if you want to read any register or write or update any value in register
// This module will 2 addresses and provide the data in 2 different outputs
module register_file(Port_A, Port_B, Din, Addr_A, Addr_B, Addr_Wr, wr,Hard_wired, clk);
output reg [31:0] Port_A, Port_B; // Data to be provided from register to execute the instruction // reg by me
input [31:0] Din; // Data to be loaded in the register
input [4:0] Addr_A, Addr_B, Addr_Wr; // Address (or number) of register to be written or to be read
input wr, clk;
output reg [31:0] Hard_wired; // input wr flag input // by me clk
reg [31:0] Reg_File [31:0]; // Register file
// Write your code here
// read
always @ (*) begin // Data Reading
Reg_File[0] = 32'd0;
Port_A = Reg_File[Addr_A];
Port_B = Reg_File[Addr_B];
Hard_wired = Reg_File[8];
end
always @(negedge clk) begin // Data Writing
if(wr)
Reg_File[Addr_Wr] = Din;
end
endmodule
| 7.992154 |
module mux(o,a,b, sel);
// input [4:0] a,b; // 5 bit inputs
// input sel; // selection signal
// output reg [4:0] o; // 5 bit output
// // write your code here!
//endmodule
| 6.851734 |
module mux3x1 (
output [31:0] o, // 32 bit output
input [31:0] a,
b,
c, // 32 bit inputs
input [ 1:0] sel // Selection Signal
);
// Write your code here!
assign o = sel[1] ? c : (sel[0] ? b : a);
endmodule
| 8.051765 |
module ALU which will accept the signal (Function) from Control Unit
// and two operands (either from register file or from memory (data or address),
// will perform the desired operarion and proivde the output in Result and Zero flag.
//module ALU(Result, alu_z, Op_A, Op_B, Function);
// output [31:0] Result; // 32 bit Result
// output alu_z; // Zero flag (1 if result is zero)
// input [31:0] Op_A, Op_B; // Two operands based on the type of instruction
// input [3:0] Func; // Function to be performed as per instructed by Control Unit
// // Write your code here
//endmodule
| 9.330097 |
module extend (
input [31:7] instr,
input [1:0] immsrc,
output reg [31:0] immext
);
always @(*)
case (immsrc)
// I−type
2'b00: immext = {{20{instr[31]}}, instr[31:20]};
// S−type (stores)
2'b01: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
// B−type (branches)
2'b10:
immext = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0}; // J−type (jal)
// J−type (branches)
2'b11: immext = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
default: immext = 32'bx; // undefined
endcase
endmodule
| 7.602103 |
module half_adder (
i_a,
i_b,
o_sum,
o_carry
);
input i_a, i_b;
output o_sum, o_carry;
and inst1 (o_carry, i_a, i_b);
xor inst2 (o_sum, i_a, i_b);
endmodule
| 6.966406 |
module basic_adder #(
parameter DATA_BITWIDTH = 16
) (
input [DATA_BITWIDTH-1:0] left,
right,
input [1:0] mode, //mode for basic_adder
output reg [DATA_BITWIDTH-1:0] out
);
always @(*) begin
case (mode)
2'b00: out = left;
2'b01: out = right;
2'b10: out = left + right;
2'b11: out = {DATA_BITWIDTH{1'b0}};
default: out = {DATA_BITWIDTH{1'bx}};
endcase
end
endmodule
| 7.548833 |
module basic_branch_predictor (
clk,
reset_n,
input_ip,
output_prediction,
input_taken
);
input clk;
input reset_n;
input [63:0] input_ip;
input [0:0] input_taken;
output [0:0] output_prediction;
reg [0:0] output_reg;
// you can add more variables
assign output_prediction = output_reg;
initial begin
output_reg <= 0;
end
always @(*) begin
end
always @(negedge reset_n) begin
// reset all state asynchronously
output_reg <= 0;
end
always @(posedge clk) begin
end
endmodule
| 6.927213 |
module basic_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter `BSG_INV_PARAM(mem_size_p)
)
(
input clk_i
, input reset_i
, input en_i
, input [cache_pkt_width_lp-1:0] cache_pkt_i
, input ready_o
, input v_i
, input [id_width_p-1:0] id_o
, input [data_width_p-1:0] data_o
, input v_o
, input yumi_i
);
`declare_bsg_cache_non_blocking_pkt_s(id_width_p,addr_width_p,data_width_p);
bsg_cache_non_blocking_pkt_s cache_pkt;
assign cache_pkt = cache_pkt_i;
// shadow mem
logic [data_width_p-1:0] shadow_mem [mem_size_p-1:0];
logic [data_width_p-1:0] result [*];
wire [addr_width_p-1:0] cache_pkt_word_addr = cache_pkt.addr[addr_width_p-1:2];
// store logic
logic [data_width_p-1:0] store_data;
logic [data_mask_width_lp-1:0] store_mask;
always_comb begin
case (cache_pkt.opcode)
SW: begin
store_data = cache_pkt.data;
store_mask = 4'b1111;
end
SH: begin
store_data = {2{cache_pkt.data[15:0]}};
store_mask = {
{2{ cache_pkt.addr[1]}},
{2{~cache_pkt.addr[1]}}
};
end
SB: begin
store_data = {4{cache_pkt.data[7:0]}};
store_mask = {
cache_pkt.addr[1] & cache_pkt.addr[0],
cache_pkt.addr[1] & ~cache_pkt.addr[0],
~cache_pkt.addr[1] & cache_pkt.addr[0],
~cache_pkt.addr[1] & ~cache_pkt.addr[0]
};
end
SM: begin
store_data = cache_pkt.data;
store_mask = cache_pkt.mask;
end
default: begin
store_data = '0;
store_mask = '0;
end
endcase
end
// load logic
logic [data_width_p-1:0] load_data, load_data_final;
logic [7:0] byte_sel;
logic [15:0] half_sel;
assign load_data = shadow_mem[cache_pkt_word_addr];
bsg_mux #(
.els_p(4)
,.width_p(8)
) byte_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1:0])
,.data_o(byte_sel)
);
bsg_mux #(
.els_p(2)
,.width_p(16)
) half_mux (
.data_i(load_data)
,.sel_i(cache_pkt.addr[1])
,.data_o(half_sel)
);
always_comb begin
case (cache_pkt.opcode)
LW: load_data_final = load_data;
LH: load_data_final = {{16{half_sel[15]}}, half_sel};
LB: load_data_final = {{24{byte_sel[7]}}, byte_sel};
LHU: load_data_final = {{16{1'b0}}, half_sel};
LBU: load_data_final = {{24{1'b0}}, byte_sel};
default: load_data_final = '0;
endcase
end
always_ff @ (posedge clk_i) begin
if (reset_i) begin
for (integer i = 0; i < mem_size_p; i++)
shadow_mem[i] <= '0;
end
else begin
if (en_i) begin
if (v_i & ready_o) begin
case (cache_pkt.opcode)
TAGST: begin
result[cache_pkt.id] = '0;
end
ALOCK, AUNLOCK: begin
result[cache_pkt.id] = '0;
end
TAGFL, AFL, AFLINV: begin
result[cache_pkt.id] = '0;
end
SB, SH, SW, SM: begin
result[cache_pkt.id] = '0;
for (integer i = 0; i < data_mask_width_lp; i++)
if (store_mask[i])
shadow_mem[cache_pkt_word_addr][8*i+:8] <= store_data[8*i+:8];
end
LW, LH, LB, LHU, LBU: begin
result[cache_pkt.id] = load_data_final;
end
endcase
end
end
end
if (~reset_i & v_o & yumi_i & en_i) begin
$display("id=%d, data=%x", id_o, data_o);
assert(result[id_o] == data_o)
else $fatal("[BSG_FATAL] Output does not match expected result. Id= %d, Expected: %x. Actual: %x",
id_o, result[id_o], data_o);
end
end
endmodule
| 6.840592 |
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