code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module barrel (
bs_opsel,
shift_amount,
data_in,
result
);
input [`OPSEL_WIDTH-1:0] bs_opsel;
input [`SA_WIDTH-1:0] shift_amount;
input [`REG_WIDTH-1:0] data_in;
output reg [`REG_WIDTH-1:0] result;
wire [`REG_WIDTH*2-1:0] temp1, temp2;
wire arithm, is_arithm_shift;
assign is_arithm_shif... | 7.311845 |
module barrel_shifter_stage (
input wire [7:0] a,
input wire [2:0] amt,
output wire [7:0] y
);
// signal declaration
wire [7:0] s0, s1;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[7:1]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[1:0], s0[7:2]} : s0;
... | 8.606549 |
module barrel_shifter_stage (
input wire [3:0] a,
input wire [1:0] amt,
output wire [3:0] y
);
//signal declaration
wire [3:0] s0; //, s1;
//body
//stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[3:1]} : a;
//stage 1, shift 0 or 2 bits
assign y = amt[1] ? {s0[1:0], s0[3:2]} : s0;
... | 8.606549 |
module barrel_shifter_stage_l (
input wire [7:0] a,
input wire [2:0] amt,
output wire [7:0] y
);
// signal declaration
wire [7:0] s0, s1;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[6:0], a[7]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[5:0], s0[7:6]} : s0... | 8.606549 |
module barrel_shifter_stage_r (
input wire [7:0] a,
input wire [2:0] amt,
output wire [7:0] y
);
// signal declaration
wire [7:0] s0, s1;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[7:1]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[1:0], s0[7:2]} : s0... | 8.606549 |
module barrel_shifter_stage_r_16b (
input wire [15:0] a,
input wire [ 3:0] amt,
output wire [15:0] y
);
// signal declaration
wire [15:0] s0, s1, s2;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[15:1]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[1:0], ... | 8.606549 |
module barrel_shifter_stage_r_32b (
input wire [31:0] a,
input wire [ 4:0] amt,
output wire [31:0] y
);
// signal declaration
wire [31:0] s0, s1, s2, s3;
// body
// stage 0, shift 0 or 1 bit
assign s0 = amt[0] ? {a[0], a[31:1]} : a;
// stage 1, shift 0 or 2 bits
assign s1 = amt[1] ? {s0[1:... | 8.606549 |
module barrel_shifter_tb;
reg [ 2:0] bs_opsel_sig;
reg [ 4:0] shift_amount_sig;
reg [31:0] data_in_sig;
wire [31:0] result_sig;
barrel_shifter barrel_shifter_inst (
.bs_opsel(bs_opsel_sig), // input [2:0] bs_opsel_sig
.shift_amount(shift_amount_sig), // input [31:0] shift_amount_sig
.... | 8.606549 |
module barrel_shifter_tb2;
reg [31:0] D;
reg [31:0] S;
reg LnR;
wire [31:0] Y;
SHIFT32 shift32 (
.Y (Y),
.D (D),
.S (S),
.LnR(LnR)
);
initial begin
S = 32'h0;
D = 32'h1;
LnR = 1'b1;
#5 S = 32'h1;
#5 S = 32'h2;
#5 S = 32'h3;
#5 S = 32'h4;
... | 8.606549 |
module barrel_shifter_test;
reg [2:0] bs_opsel_sig;
reg [4:0] shift_amount_sig;
reg [31:0] data_in_sig;
wire [31:0] result_sig;
integer i = 0;
lab3_barrel_shifter lab3_barrel_shifter_inst (
.bs_opsel(bs_opsel_sig), // input [2:0] bs_opsel_sig
.shift_amount(shift_amount_sig), // input [4:0] ... | 8.606549 |
module barrel (
bs_opsel,
shift_amount,
data_in,
result
);
input [`OPSEL_WIDTH-1:0] bs_opsel;
input [`SA_WIDTH-1:0] shift_amount;
input [`REG_WIDTH-1:0] data_in;
output reg [`REG_WIDTH-1:0] result;
wire [`REG_WIDTH*2-1:0] temp1, temp2;
wire arithm, is_arithm_shift;
assign is_arithm_shif... | 7.311845 |
module mux2 (
input wire i0,
i1,
j,
output wire o
);
assign o = (j == 0) ? i0 : i1;
endmodule
| 7.816424 |
module barrel_shift_16bit (
in,
ctrl,
out
);
input [15:0] in;
input [3:0] ctrl;
output [15:0] out;
wire [15:0] x, y, z;
//8bit shift right
mux2 mux_15 (
in[15],
1'b0,
ctrl[3],
x[15]
);
mux2 mux_14 (
in[14],
1'b0,
ctrl[3],
x[14]
);
mux2 mu... | 7.827555 |
module barrel_shift_mips #(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 5,
parameter lo_l = 0,
parameter lo_r = 1,
parameter al_r = 2,
parameter ci_r = 3
) (
input [(DATA_WIDTH -1):0] data_in,
input [(ADDR_WIDTH -1):0] shift_count,
input [1:0] op,
output reg [(DATA_WIDTH -1... | 7.827555 |
module barrel_tb;
reg [ 2:0] bs_opsel_sig;
reg [ 4:0] shift_amount_sig;
reg [31:0] data_in_sig;
wire [31:0] result_sig;
integer i, j;
barrel barrel_inst (
.bs_opsel(bs_opsel_sig), // input [2:0] bs_opsel_sig
.shift_amount(shift_amount_sig), // input [4:0] shift_amount_sig
.data_in... | 6.712577 |
module barrel_test;
parameter pattern_num = 8;
wire [7:0] out;
wire carry;
reg [7:0] x, y;
reg clk;
reg stop;
integer i, num, error;
reg [7:0] ans_out;
reg [7:0] barrel_out;
reg [7:0] data_base1 [0:100];
reg [7:0] data_base2 [0:100];
barrel_shifter B (
x,
y[2:0],
out
);
... | 7.124734 |
module DecoupledStage (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [23:0] io_in_bits_ul,
input [23:0] io_in_bits_quo,
input io_out_ready,
output io_out_valid,
output [23:0] io_out_bits_ul,
output [23:0] i... | 7.271782 |
module DecoupledStage_1 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [23:0] io_in_bits_ul,
input [23:0] io_in_bits_quo,
input [23:0] io_in_bits_quo_times_Q,
input io_out_ready,
output io_out_valid,
outpu... | 7.271782 |
module DecoupledStage_2 (
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input [22:0] io_in_bits_remainder,
input [23:0] io_in_bits_quotient,
input io_out_ready,
output io_out_valid,
output [22:0] io_out_bits_remainder... | 7.271782 |
module barrett_reducer (
input clk,
input rst,
input en,
input [15:0] a,
input valid,
output reg out_valid,
output reg [13:0] result
);
wire [15:0] NEWHOPE_Q_MULTIPLE;
assign NEWHOPE_Q_MULTIPLE = (a[15:14] == 0) ? 16'd0 :
(a[15:14] == 1) ? 16'd12289 :
... | 7.179208 |
module barrido (
clk,
filas
);
input clk;
output reg [3:0] filas = 0;
reg [1:0] selector = 0;
always @(posedge clk) begin
selector = selector + 1;
case (selector)
2'b00: filas = 4'b1000;
2'b01: filas = 4'b0100;
2'b10: filas = 4'b0010;
2'b11: filas = 4'b0001;
endc... | 7.160924 |
module. Aggregates barrier good notifications
* from individual modules and pushes out a global barrier good notification
* when all modules are ready.
*
*
*/
`timescale 1ns/1ps
module barrier #(
parameter NUM_PORTS = 4
)
(
input [NUM_PORTS:0] activity_stim,
input [NUM_PORTS:0] activity_rec,
i... | 6.877898 |
module. Aggregates barrier good notifications
// from individual modules and pushes out a global barrier good notification
// when all modules are ready.
//
///////////////////////////////////////////////////////////////////////////////
// `timescale 1 ns/1 ns
module barrier_ctrl #(
parameter NUM_PORTS = 4
)
(
i... | 6.877898 |
module barrier_gluelogic (
input wire in_pin4,
input wire in_pin3,
input wire in_pin2,
input wire in_pin1,
input wire in_pin0,
output wire [4:0] out_bus
);
assign out_bus = {in_pin4, in_pin3, in_pin2, in_pin1, in_pin0};
endmodule
| 7.931567 |
module bars (
input wire [9:0] x_px,
output wire [2:0] color_px
);
//Calculate width bar.
localparam barwidth = 80; // For a 640x480@72Hz, 3bits controller
// We're inside a bar, set its color.
assign color_px = ((x_px >= 0*barwidth) && (x_px < 1*barwidth)) ? 3'b111 :
(((x_px >= 1... | 10.146891 |
module BarSH (
input [ 1:0] ex_shift_op,
input [31:0] ex_b,
input [ 4:0] ex_shift_amount,
output [31:0] ex_bs_out
);
reg [31:0] r;
always @(ex_shift_amount or ex_b or ex_shift_op) begin
r = ex_b;
case (ex_shift_op)
2'b01: begin
if (ex_shift_amount[0]) r = {1'b0, r[31:1]};
... | 6.587072 |
module barshift_128b_tb ();
wire [127:0] out0;
reg [127:0] in0;
reg [ 6:0] in1;
integer i, file, mem, temp;
barshift_128b U0 (
in0,
in1,
out0
);
initial begin
$display("-- Begining Simulation --");
$dumpfile("./barshift_128b.vcd");
$dumpvars(0, barshift_128b_tb);
... | 6.708298 |
module BarTop (
input Clock,
Reset,
Start,
NewFrame,
input [2:0] FallSpeed,
input [6:0] Bar,
output reg [6:0] Top
);
localparam depth_ram = 800;
localparam bw_addr = 10;
localparam preset_resetval = 0;
localparam hfp = 4; //Heightの固定小数点位置 右から
localparam sfp = 5;
localparam bw_sp... | 7.100458 |
module bar_big (
input [11:0] x,
input [11:0] y,
input [11:0] org_x,
input [11:0] org_y,
input [11:0] line_x,
input [11:0] line_y,
output bar_space
);
assign bar_space=(
(x>=org_x) && (x<=(org_x+line_x)) &&
(y>=org_y) && (y<=(org_y+line_y))
... | 7.065217 |
module bar_white (
input [11:0] CounterY,
output L_5,
output L_6,
output L_7,
output M_1,
output M_2,
output M_3,
output M_4,
output M_5,
output M_6,
output M_7,
output H_1,
output H_2,
output H_3,
output H_4,
output H_5
);
wire [11:0] ydeta = 30;
wir... | 7.058695 |
module base1 (
en,
clk,
addr,
data
);
input en;
input clk;
output reg [3:0] addr;
output reg [3:0] data;
always @(posedge clk, posedge en) begin
if (en == 1) begin
if (addr == 0 || data == 0 || addr == 1 || data == 1) begin
addr <= addr + 1;
data <= data + 1;
... | 6.61489 |
module baseaddr_loop (
input wclk,
input wrst_n,
input wr_vs,
input [4:0] rd0_curr_point,
input [4:0] rd1_curr_point,
input [4:0] rd2_curr_point,
output reg [4:0] wr_current_point,
output reg [4:0] last_next_point
);
wire wr_vs_raising, wr_vs_falling;
edge_generator #(
.MO... | 7.033211 |
module baseaddr_loop_A2 (
input wclk,
input wrst_n,
input enable,
input wr_vs,
input [4:0] rd0_curr_point,
input [4:0] rd1_curr_point,
input [4:0] rd2_curr_point,
output reg [4:0] wr_current_point,
output reg [4:0] last_next_point
);
wire wr_vs_raising, wr_vs_falling;
edge_g... | 7.033211 |
module baseball_rom_synth (
a,
spo
);
input [7 : 0] a;
output [7 : 0] spo;
// WARNING: This file provides a module declaration only, it does not support
// direct instantiation. Please use an instantiation template (VEO) to
// instantiate the IP within a design.
endmodule
| 7.517011 |
module baseram (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [14:0] address;
input [1:0] byteena;
input clock;
input [15:0] data;
input rden;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1... | 6.515975 |
module base_3xMUX5to1 (
input [2:0] S,
input [2:0] U,
V,
W,
X,
Y,
output reg [2:0] M
);
always @(*) begin
case (S)
3'b000: begin
M = U;
end
3'b001: begin
M = V;
end
3'b010: begin
M = W;
end
3'b011: begin
M = X;
... | 7.746821 |
module base_8xMUX2to1 (
input s,
input [7:0] X,
Y,
output [7:0] M
);
assign M[7] = ((~s & X[7]) | (s & Y[7]));
assign M[6] = ((~s & X[6]) | (s & Y[6]));
assign M[5] = ((~s & X[5]) | (s & Y[5]));
assign M[4] = ((~s & X[4]) | (s & Y[4]));
assign M[3] = ((~s & X[3]) | (s & Y[3]));
assign M[2] ... | 7.052027 |
module half_adder (
output wire sum,
output wire cout,
input wire in1,
input wire in2
);
xor (sum, in1, in2);
and (cout, in1, in2);
endmodule
| 6.966406 |
module base_auto_us_0_axi_register_slice_v2_1_15_axi_register_slice (
m_axi_rready,
mr_rvalid,
Q,
out,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
m_axi_rvalid,
E,
\aresetn_d_reg[1] ,
\aresetn_d_reg[0]
);
output m_axi_rready;
output mr_rvalid;
output [66:0] Q;
input out;
... | 6.616439 |
module base_auto_us_0_axi_register_slice_v2_1_15_axi_register_slice__parameterized0 (
\aresetn_d_reg[1] ,
s_ready_i_reg,
sr_arvalid,
in,
m_axi_arburst,
m_axi_araddr,
s_axi_arready,
Q,
m_axi_arsize,
s_axi_aresetn,
out,
cmd_push_block_reg,
s_axi_arvalid,
D
);
outp... | 6.616439 |
module base_auto_us_1_axi_register_slice_v2_1_15_axi_register_slice (
sr_awvalid,
s_axi_awready,
in,
m_axi_awburst,
m_axi_awaddr,
Q,
m_axi_awsize,
out,
\USE_RTL_VALID_WRITE.buffer_Full_q_reg ,
s_axi_awvalid,
s_axi_aresetn,
m_axi_awready,
cmd_push_block_reg,
SR,
... | 6.616439 |
modules
`timescale 1ns / 1ps
module basecell_ha(f1_i, f2_i, b_i, sum_o, c_o);
input f1_i, f2_i, b_i;
output sum_o, c_o;
wire pp;
assign pp = f1_i & f2_i;
HA adder(pp, b_i, sum_o, c_o);
endmodule
| 7.369394 |
module basecell_fa (
f1_i,
f2_i,
b_i,
c_i,
sum_o,
c_o
);
input f1_i, f2_i, b_i, c_i;
output sum_o, c_o;
wire pp;
assign pp = f1_i & f2_i;
FA adder (
pp,
b_i,
c_i,
sum_o,
c_o
);
endmodule
| 7.196538 |
module HA (
A,
B,
S,
Cout
);
input A, B;
output S, Cout;
assign S = A ^ B;
assign Cout = A & B;
endmodule
| 7.265208 |
module d_flip_flop (
q,
d,
clk
);
output reg q;
input d, clk;
always @(*) begin
if (clk) begin
q <= d;
end
end
endmodule
| 7.497066 |
module inv_tri_buffer (
q,
d,
OE
);
output q;
input d, OE;
assign q = (OE) ? 1'bZ : ~d;
endmodule
| 7.12638 |
module octal_d_flip_flop (
q,
d,
OE,
CP
);
output wire [7:0] q;
wire [7:0] q_mid;
input [7:0] d;
input OE, CP;
d_flip_flop dff0 (
q_mid[0],
d[0],
CP
);
d_flip_flop dff1 (
q_mid[1],
d[1],
CP
);
d_flip_flop dff2 (
q_mid[2],
d[2],
CP... | 7.112496 |
module quad_adder (
s,
a,
b,
c_in,
c_out
);
output wire [3:0] s;
output c_out;
input [3:0] a, b;
input c_in;
assign {c_out, s} = (a + b + c_in);
endmodule
| 8.178474 |
module demux_2_4 (
o,
a0,
a1,
e
);
output [3:0] o;
input a0, a1, e;
assign o[0] = ~(~e & ~a0 & ~a1);
assign o[1] = ~(~e & a0 & ~a1);
assign o[2] = ~(~e & ~a0 & a1);
assign o[3] = ~(~e & a0 & a1);
endmodule
| 6.918606 |
module generates a frequency based on an input note.
//1 is a C2. The frequencies generated are 64x the desired frequency.
module base_freq_genx64(
note_in,
clk50mhz,
freq_out,
offset_mult,
offset_dir
);
input clk50mhz;
input [5:0] note_in;
input [2:0] offset_mult;
input offset_dir; //offset direction: 0... | 6.867098 |
module base_generator #(
parameter FPGA_FAMILY = "ALTERA",
parameter X_W = 16,
parameter E_W = 16,
parameter W_W = 16
) (
input clk,
input rst_n,
input en,
input signed [ X_W-1:0] xin,
input signed [ E_W-1:0] err,
output signed [X_W+W_... | 6.777899 |
module base_ram (
input logic clk,
input logic nrst,
input logic we,
input logic re,
input logic [7:0] raddr1,
input logic [7:0] raddr2,
input logic [7:0] waddr,
input logic [31:0] wdata,
output logic [31:0] rdataA,
output logic [31:0] rdataB
);
logic [31:0] mem[255:0]; //Def... | 7.454095 |
module base_rst_ps7_0_50M_0 (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_pa... | 7.24774 |
module base_rst_ps7_0_50M_0_cdc_sync (
lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk
);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0] asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_syn... | 7.24774 |
module base_rst_ps7_0_50M_0_cdc_sync_0 (
lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk
);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0] p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;... | 7.24774 |
module base_rst_ps7_0_50M_0_lpf (
lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in
);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
... | 7.24774 |
module base_rst_ps7_0_50M_0_proc_sys_reset (
slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn
);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;... | 7.24774 |
module base_rst_ps7_0_50M_0_upcnt_n (
Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk
);
output [5:0] Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0] Q;
wire clear;
wire [5:0] q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1)
... | 7.24774 |
module base_rx_mac (
// Host side of Rx MAC memory
input host_clk,
input [10:0] host_raddr,
output reg [15:0] host_rdata,
// port to Rx MAC memory
input rx_clk,
input [7:0] rx_mac_d,
input [11:0] rx_mac_a,
input rx_mac_wen,
// port to Rx MAC packet selector
output rx_mac_acce... | 7.3496 |
module base_soc (
//base signals
input wire clk_i,
input wire reset_i,
//wb bus signals
output wire [31:0] wb_adr_o,
output wire [31:0] wb_dat_o,
input wire [31:0] wb_dat_i,
output wire wb_we_o,
output wire [3:0] wb_sel_o,
output wire wb_stb_o,
input wire wb_ack_i,
output... | 7.193989 |
module: base
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module base_tb;
// Inputs
reg clk;
reg rst;
// Outputs
wire out;
wire err_en;
wire err_ctrl;
wire sh_clk;
wire sh_rst... | 7.175384 |
module and2 (
a,
b,
y
);
input a, b;
output y;
assign y = a & b;
endmodule
| 7.692856 |
module nand2 (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a & b);
endmodule
| 9.068616 |
module or2 (
a,
b,
y
);
input a, b;
output y;
assign y = a | b;
endmodule
| 8.2416 |
module nor2 (
a,
b,
y
);
input a, b;
output y;
assign y = ~(a | b);
endmodule
| 8.286761 |
module xor2 (
a,
b,
y
);
input a, b;
output y;
assign y = a ^ b;
endmodule
| 8.694233 |
module mux2 (
in1,
in0,
select,
out
);
parameter WIDTH = 1;
input [WIDTH-1:0] in0, in1;
input select;
output [WIDTH-1:0] out;
assign out = (select) ? in1 : in0;
endmodule
| 7.816424 |
module mux10_1bit (in, select, out);
// input [9:0] in;
// input [3:0] select;
// output out;
// case(select)
// 4'b0000: out = in[0];
// 4'b0001: out = in[1];
// 4'b0010: out = in[2];
// 4'b0011: out = in[3];
// 4'b0100: out = in[4];
// 4'b0101: out = in[5];
// 4'b0110: out = in[6];
// 4'b0111: out... | 8.025449 |
module mux_1bit (
in,
select,
out
);
parameter IN_WIDTH = 2;
parameter SEL_WIDTH = 1;
input [IN_WIDTH-1:0] in;
input [SEL_WIDTH-1:0] select;
output out;
assign out = in[select];
endmodule
| 8.087151 |
module register (
clk,
rst,
D,
Q,
wen
);
parameter WIDTH = 1;
input clk, rst, wen;
input [WIDTH-1:0] D;
output reg [WIDTH-1:0] Q;
always @(posedge clk or posedge rst) begin
if (rst) begin
Q <= {(WIDTH) {1'b0}};
end else if (wen) begin
Q <= D;
end
end
endmodule
| 6.542519 |
module BasicCORE (
input [31:0] instr,
output [6:0] order,
output reg [4:0] A1,
output reg [4:0] A2,
output reg [4:0] A3
);
wire [5:0] opcode = instr[31:26];
wire [5:0] funcode = instr[5:0];
wire [4:0] rs, rt, rd;
assign rs = instr[25:21];
assign rt = instr[20:16];
assign rd = instr[15:... | 7.373694 |
module adder (
q,
a,
b
);
input a, b;
output [1:0] q;
assign q = {1'b0, a} + {1'b0, b};
endmodule
| 7.555649 |
module mul (
q,
a,
b
);
input a, b;
output [1:0] q;
assign q = {1'b0, a} * {1'b0, b};
endmodule
| 7.034324 |
module adder (
q,
a,
b
);
input a, b;
output [1:0] q;
assign q = a + b;
endmodule
| 7.555649 |
module BasicGates (
input1,
input2,
output_and,
output_or,
output_not,
output_nand,
output_nor,
output_xor
);
input input1;
input input2;
output output_and;
output output_or;
output output_not;
output output_nand;
output output_nor;
output output_xor;
assign output_an... | 7.884618 |
module BasicGates_tb;
wire t_y1, t_y2, t_y3, t_y4, t_y5, t_y6;
reg t_a, t_b;
BasicGates my_gates (
.input1(t_a),
.input2(t_b),
.output_and(t_y1),
.output_or(t_y2),
.output_not(t_y3),
.output_nand(t_y4),
.output_nor(t_y5),
.output_xor(t_y6)
);
initial begin
... | 6.526518 |
module mux #(
parameter integer LENGTH = 32
) (
in1,
in2,
sel,
out
);
input sel;
input [LENGTH-1:0] in1, in2;
output [LENGTH-1:0] out;
assign out = (sel == 0) ? in1 : in2;
endmodule
| 8.575874 |
module mux_3input #(
parameter integer LENGTH = 32
) (
in1,
in2,
in3,
sel,
out
);
input [LENGTH-1:0] in1, in2, in3;
input [1:0] sel;
output [LENGTH-1:0] out;
assign out = (sel == 2'd0) ? in1 : (sel == 2'd1) ? in2 : in3;
endmodule
| 8.526131 |
module register (
clk,
reset,
writeEn,
regIn,
regOut
); //PC
input clk, reset, writeEn;
input [31:0] regIn;
output reg [31:0] regOut;
always @(posedge clk) begin
if (reset == 1) regOut <= 0;
else if (writeEn) regOut <= regIn;
end
endmodule
| 6.542519 |
module regFile (
clk,
rst,
src1,
src2,
dest,
writeVal,
writeEn,
reg1,
reg2
);
input clk, rst, writeEn;
input [`REG_FILE_ADDR_LEN-1:0] src1, src2, dest;
input [`WORD_LEN-1:0] writeVal;
output [`WORD_LEN-1:0] reg1, reg2;
reg [`WORD_LEN-1:0] regMem[0:`REG_FILE_SIZE-1];
inte... | 7.797802 |
module signExtend (
in,
out
);
input [15:0] in;
output [31:0] out;
assign out = (in[15] == 1) ? {16'b1111111111111111, in} : {16'b0000000000000000, in};
endmodule
| 7.397526 |
module ALU (
val1,
val2,
EXE_CMD,
aluOut
);
input [`WORD_LEN-1:0] val1, val2;
input [`EXE_CMD_LEN-1:0] EXE_CMD;
output reg [`WORD_LEN-1:0] aluOut;
always @(*) begin
case (EXE_CMD)
`EXE_ADD: aluOut <= val1 + val2;
`EXE_SUB: aluOut <= val1 - val2;
`EXE_AND: aluOut <= val1 & ... | 7.896404 |
module basicProcessor_tb ();
reg [31:0] memory[31:0];
reg [31:0] instruction[31:0];
reg clk;
reg reset;
wire [31:0] memOut, memAddress, instructionAddress;
wire WE;
reg [31:0] cycleCount;
localparam [31:0] noOp = 32'h00000000;
localparam [1:0] Load = 2'b01;
localparam [1:0] mem = 2'b00;
localparam... | 7.234379 |
module as declared in thinpad_top.v
// to a basic RAM / ROM module.
// Author: LYL
// Created on: 2018/11/24
`timescale 1ns / 1ps
`include "defines.vh"
module BasicRamWrapper(
input wire clk,
// From MEM
input wire ce_i,
input wire we_i,
input wire[`DataAddrBus] addr_i,
input wire[3:0] sel_i,
... | 8.924335 |
module generator (
clk,
reset,
send
);
parameter SIM_CYLES = 10000;
parameter COOLDOWN_CYCLES = 2000;
output clk, reset, send;
reg clk, reset, send;
initial begin
clk = 0;
#0 reset = 1;
#2 reset = 0;
end
always begin
#1 clk = !clk;
end
initial $display("Start of simula... | 7.128432 |
module sm (
clk,
rst,
st
);
input clk, rst;
output [1:0] st;
reg [1:0] st;
always @(posedge clk or posedge rst)
if (rst) st <= 2'b0;
else
case (st)
2'b00: st <= 2'b01;
2'b01: st <= 2'b11;
2'b11: st <= 2'b10;
2'b10: st <= 2'b00;
endcase
endmodule
... | 6.695888 |
module sm (
clk,
rst,
st
);
input clk, rst;
output [1:0] st;
reg [1:0] st, next_st;
always @(posedge clk or posedge rst)
if (rst) st <= 2'b0;
else st <= next_st;
always @(st)
case (st)
2'b00: next_st <= 2'b01;
2'b01: next_st <= 2'b11;
2'b11: next_st <= 2'b10;
... | 6.695888 |
module HazardUnit (
Rs1E,
Rs2E,
ForwardAE,
ForwardBE,
RdM,
RdW,
RegWriteM,
RegWriteW,
ResultSrc0,
RdE,
Rs1D,
Rs2D,
StallF,
StallD,
FlushE,
PCSrcE,
FlushD,
intrupt,
FlushM,
ret
);
input [4:0] Rs1E, Rs2E, Rs1D, Rs2D, RdE, RdM, RdW;
input... | 8.02365 |
module to generate the address of next instruction
// LOGIC: Add 1 in program counter if its a normal instruction
// Add address of label in PC if its a branch instruction
// other parameters can also be added based on Datapath and Controller Inputs/Outputs
//module adress_generator (output [31:0] pc, input PC_Sr... | 7.132498 |
module that will carry the all instructions. PC value will be provided to this module and it will return the instuction
// other parameters can also be added based on Datapath and Controller Inputs/Outputs
module Instruction_Memory (input [31:0] pc,output reg [31:0] instruction);
always @ (*) begin
case(pc... | 7.967585 |
module is called Data_Memory. It will consists of 256 byte memory unit. It will have
// one input as 8-bit address, 1 input flag wr that will decide if you want to read memory or write memory
module Data_Memory(output reg [31:0] Data_Out, input [31:0] Data_In, input [31:0] D_Addr, input wr, input clk );
reg [31:0] M... | 7.273784 |
module is called Register_Memory. It will consists of 32 registers each of 32-bits. It will have
// one input flag wr that will decide if you want to read any register or write or update any value in register
// This module will 2 addresses and provide the data in 2 different outputs
module register_file(Port_A, Port_... | 7.992154 |
module mux(o,a,b, sel);
// input [4:0] a,b; // 5 bit inputs
// input sel; // selection signal
// output reg [4:0] o; // 5 bit output
// // write your code here!
//endmodule
| 6.851734 |
module mux3x1 (
output [31:0] o, // 32 bit output
input [31:0] a,
b,
c, // 32 bit inputs
input [ 1:0] sel // Selection Signal
);
// Write your code here!
assign o = sel[1] ? c : (sel[0] ? b : a);
endmodule
| 8.051765 |
module ALU which will accept the signal (Function) from Control Unit
// and two operands (either from register file or from memory (data or address),
// will perform the desired operarion and proivde the output in Result and Zero flag.
//module ALU(Result, alu_z, Op_A, Op_B, Function);
// output [31:0] Result; // 32 b... | 9.330097 |
module extend (
input [31:7] instr,
input [1:0] immsrc,
output reg [31:0] immext
);
always @(*)
case (immsrc)
// I−type
2'b00: immext = {{20{instr[31]}}, instr[31:20]};
// S−type (stores)
2'b01: immext = {{20{instr[31]}}, instr[31:25], instr[11:7]};
// B−type (bra... | 7.602103 |
module half_adder (
i_a,
i_b,
o_sum,
o_carry
);
input i_a, i_b;
output o_sum, o_carry;
and inst1 (o_carry, i_a, i_b);
xor inst2 (o_sum, i_a, i_b);
endmodule
| 6.966406 |
module basic_adder #(
parameter DATA_BITWIDTH = 16
) (
input [DATA_BITWIDTH-1:0] left,
right,
input [1:0] mode, //mode for basic_adder
output reg [DATA_BITWIDTH-1:0] out
);
always @(*) begin
case (mode)
2'b00: out = left;
2'b01: out = right;
2'b10: out = left + right;... | 7.548833 |
module basic_branch_predictor (
clk,
reset_n,
input_ip,
output_prediction,
input_taken
);
input clk;
input reset_n;
input [63:0] input_ip;
input [0:0] input_taken;
output [0:0] output_prediction;
reg [0:0] output_reg;
// you can add more variables
assign output_prediction = outpu... | 6.927213 |
module basic_checker
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(id_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(cache_pkt_width_lp)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter `BSG_IN... | 6.840592 |
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