code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AND2_16 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.975484 |
module CSA_Cell_16 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_16 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_16 U1 (
.A (And_XY),
.B (S_in),
.CI(1'b0),
.CO(C_out),
.S (S_out)
);
endmodule
| 6.951962 |
module AND2_0 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.420626 |
module FA_7 (
A,
B,
CI,
CO,
S
);
input A, B, CI;
output CO, S;
wire A;
assign S = A;
endmodule
| 6.624434 |
module AND2_7 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.456289 |
module CSA_Cell_7 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_7 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_7 U1 (
.A (And_XY),
.B (1'b0),
.CI(1'b0),
.S (S_out)
);
endmodule
| 6.646269 |
module AND2_13 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.522602 |
module AND2_18 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.602137 |
module AND2_19 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.685614 |
module CSA_Cell_19 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_19 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_19 U1 (
.A (And_XY),
.B (1'b0),
.CI(1'b0),
.S (S_out)
);
endmodule
| 6.517123 |
module AND2_20 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.950668 |
module CSA_Cell_20 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_20 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_20 U1 (
.A (And_XY),
.B (1'b0),
.CI(1'b0),
.S (S_out)
);
endmodule
| 6.543769 |
module ban_reg_micro (
input [5:0] Sel_reg,
input W,
input [7:0] DW,
output [7:0] Rx,
output [7:0] Ry,
input rst,
input clk
);
reg [7:0] Fnd[0:7];
always @(posedge clk, posedge rst) begin
if (rst) begin
Fnd[0] <= 0;
Fnd[1] <= 0;
Fnd[2] <= 0;
Fnd[3] <= 0;
Fnd[4] <= 0;
Fnd[5] <= 0;
Fnd[6] <= 0;
Fnd[7] <= 0;
end else if (W) Fnd[Sel_reg[2:0]] <= DW;
end
assign Rx = Fnd[Sel_reg[2:0]];
assign Ry = Fnd[Sel_reg[5:3]];
endmodule
| 7.185678 |
module Registerfile (
clk,
we3,
wa3,
ra1,
ra2,
wd3,
rd1,
rd2,
S0,
S1,
S2,
S3,
S4,
S5,
S6,
S7
);
input [7:0] wd3;
input [2:0] wa3, ra1, ra2;
input we3, clk;
output reg [7:0] rd1, rd2;
output reg [7:0] S0, S1, S2, S3, S4, S5, S6, S7;
reg [7:0] registrador[7:0];
always @(posedge clk) begin
if (we3 == 1) registrador[wa3] <= wd3;
registrador[0] <= 2'b00000000;
end
always @(*) begin
rd1 <= registrador[ra1];
rd2 <= registrador[ra2];
S0 <= registrador[0];
S1 <= registrador[1];
S2 <= registrador[2];
S3 <= registrador[3];
S4 <= registrador[4];
S5 <= registrador[5];
S6 <= registrador[6];
S7 <= registrador[7];
end
endmodule
| 6.695704 |
module Banco_registros (
input [4:0] dirL1,
dirL2,
dirW,
input wr,
input [31:0] datoIn,
output reg [31:0] dataOut1,
dataOut2
);
reg [31:0] BRegistros[31:0];
initial begin
BRegistros[0] = 32'd12;
BRegistros[1] = 32'd45;
BRegistros[2] = 32'd2;
BRegistros[3] = 32'd50;
BRegistros[4] = 32'd47;
BRegistros[5] = 32'd64;
BRegistros[6] = 32'd24;
BRegistros[7] = 32'd7;
BRegistros[8] = 32'd132;
BRegistros[9] = 32'd127;
BRegistros[10] = 32'd38;
BRegistros[11] = 32'd96;
BRegistros[12] = 32'd35;
BRegistros[13] = 32'd94;
BRegistros[14] = 32'd82;
BRegistros[15] = 32'd22;
BRegistros[16] = 32'd130;
BRegistros[17] = 32'd101;
BRegistros[18] = 32'd177;
BRegistros[19] = 32'd115;
end
always @(*) begin
if (wr == 1) begin
BRegistros[dirW] = datoIn;
end
dataOut1 = BRegistros[dirL1];
dataOut2 = BRegistros[dirL2];
end
endmodule
| 7.07719 |
module BancoInstrucao (
clock,
Endereco,
Instrucao
);
input wire clock;
input wire [7:0] Endereco;
output [7:0] Instrucao;
reg [7:0] Memoria[255:0];
reg [7:0] aux;
always @(negedge clock) begin
begin
aux = Memoria[Endereco];
end
end
assign Instrucao = aux;
endmodule
| 7.114402 |
module BancoPruebas; // Testbench
// Por lo general, las senales en el banco de pruebas son wires.
// No almacenan un valor, son manejadas por otras instancias de modulos.
// Dado que requieren coincidir con el tamaño de las entradas y salidas se debe asignar con su tamano
// definido en los modulos
// Si define formato de cantidad, se recomienda mantenerlo en el mismo formato siendo el
// mismo utilizado en el modulo para la cantidad de bits -- [1:0] ---, otra forma de hacerlo es con
// [0:1]
wire [1:0] data_out_banco_conduc, data_in0_banco_conduc, data_in1_banco_conduc;
wire reset_L_banco_conduc, clk_banco_conduc, selector_banco_conduc;
// Descripcion conductual de alarma
mux2_1 a_cond (
.data_out(data_out_banco_conduc),
.data_in0(data_in0_banco_conduc),
.data_in1(data_in1_banco_conduc),
.reset_L (reset_L_banco_conduc),
.clk (clk_banco_conduc),
.selector(selector_banco_conduc)
);
// Probador: generador de senales y monitor
probador prob (
.data_out_probador(data_out_banco_conduc),
.data_in0_probador(data_in0_banco_conduc),
.data_in1_probador(data_in1_banco_conduc),
.reset_L_probador (reset_L_banco_conduc),
.clk_probador (clk_banco_conduc),
.selector_probador(selector_banco_conduc)
);
endmodule
| 7.69717 |
module BancoPruebas_arbitro; // Testbench
wire almost_full0, almost_full1, almost_full2, almost_full3;
wire empty0_naranja,empty1_naranja,empty2_naranja,empty3_naranja, empty0_morado, empty1_morado ,empty2_morado,empty3_morado;
wire [7:0] empties, empties_estruct;
wire push;
wire pop0, pop1, pop2, pop3;
wire push_estruct;
wire pop0_estruct, pop1_estruct, pop2_estruct, pop3_estruct;
/*AUTOWIRE*/
wire clk; // From prob of Probador_Contador.v
wire [3:0] state;
// End of automatics
///////////////////////////////// arbitro /////////////////////////
arbitro arbitro_conductual (
.almost_full0(almost_full0),
.almost_full1(almost_full1),
.almost_full2(almost_full2),
.almost_full3(almost_full3),
.empty0_naranja(empty0_naranja),
.empty1_naranja(empty1_naranja),
.empty2_naranja(empty2_naranja),
.empty3_naranja(empty3_naranja),
.empty0_morado(empty0_morado),
.empty1_morado(empty1_morado),
.empty2_morado(empty2_morado),
.empty3_morado(empty3_morado),
.push(push),
// .push1(push1),
// .push2(push2),
// .push3(push3),
.pop0(pop0),
.pop1(pop1),
.pop2(pop2),
.pop3(pop3),
/*AUTOINST*/
// Outputs
.empties(empties[7:0]),
// Inputs
.clk(clk),
.state(state[3:0]),
.push0(push0),
.push1(push1),
.push2(push2),
.push3(push3)
);
arbitro_estruct arbitro_estructural (
.almost_full0(almost_full0),
.almost_full1(almost_full1),
.almost_full2(almost_full2),
.almost_full3(almost_full3),
.empty0_naranja(empty0_naranja),
.empty1_naranja(empty1_naranja),
.empty2_naranja(empty2_naranja),
.empty3_naranja(empty3_naranja),
.empty0_morado(empty0_morado),
.empty1_morado(empty1_morado),
.empty2_morado(empty2_morado),
.empty3_morado(empty3_morado),
.push(push_estruct),
// .push1(push1_estruct),
// .push2(push2_estruct),
// .push3(push3_estruct),
.pop0(pop0_estruct),
.pop1(pop1_estruct),
.pop2(pop2_estruct),
.pop3(pop3_estruct),
.empties(empties_estruct),
/*AUTOINST*/
// Inputs
.clk(clk),
.push0(push0),
.push1(push1),
.push2(push2),
.push3(push3),
.state(state[3:0])
);
Probador_arbitro Probador (
.almost_full0(almost_full0),
.almost_full1(almost_full1),
.almost_full2(almost_full2),
.almost_full3(almost_full3),
.empty0_naranja(empty0_naranja),
.empty1_naranja(empty1_naranja),
.empty2_naranja(empty2_naranja),
.empty3_naranja(empty3_naranja),
.empty0_morado(empty0_morado),
.empty1_morado(empty1_morado),
.empty2_morado(empty2_morado),
.empty3_morado(empty3_morado),
.push(push),
// .push1(push1),
// .push2(push2),
// .push3(push3),
.pop0(pop0),
.pop1(pop1),
.pop2(pop2),
.pop3(pop3),
/*AUTOINST*/
// Outputs
.clk (clk),
.state (state[3:0]),
// Inputs
.empties (empties[7:0]),
.empties_estruct (empties_estruct[7:0]),
.push_estruct (push_estruct)
);
endmodule
| 6.995131 |
module BancoPruebas_FIFO; // Testbench
wire empty_conduct, empty_estruct, almost_full_estruct, almost_full_conduct;
wire [9:0] data_out_conduct, data_out_estruct;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire almost_empty; // From conductual of FIFO.v, ...
wire clk; // From prob of Probador_FIFO.v
wire [9:0] data_in; // From prob of Probador_FIFO.v
wire pop; // From prob of Probador_FIFO.v
wire push; // From prob of Probador_FIFO.v
wire [3:0] state; // From prob of Probador_FIFO.v
wire [2:0] umbral_inferior; // From prob of Probador_FIFO.v
wire [2:0] umbral_superior; // From prob of Probador_FIFO.v
// End of automatics
FIFO conductual (
.data_out(data_out_conduct),
.empty(empty_conduct),
.almost_full(almost_full_conduct),
/*AUTOINST*/
// Outputs
.almost_empty(almost_empty),
// Inputs
.clk(clk),
.state(state[3:0]),
.push(push),
.pop(pop),
.data_in(data_in[9:0]),
.umbral_superior(umbral_superior[2:0]),
.umbral_inferior(umbral_inferior[2:0])
);
Probador_FIFO prob (
.data_out_conduct(data_out_conduct),
.data_out_estruct(data_out_estruct),
.empty_conduct(empty_conduct),
.almost_full_conduct(almost_full_conduct),
.empty_estruct(empty_estruct),
.almost_full_estruct(almost_full_estruct),
/*AUTOINST*/
// Outputs
.clk(clk),
.state(state[3:0]),
.push(push),
.pop(pop),
.data_in(data_in[9:0]),
.umbral_superior(umbral_superior[2:0]),
.umbral_inferior(umbral_inferior[2:0])
);
FIFO_estruct estructural (
.data_out(data_out_estruct),
.empty(empty_estruct),
.almost_full(almost_full_estruct),
/*AUTOINST*/
// Outputs
.almost_empty(almost_empty),
// Inputs
.clk(clk),
.data_in(data_in[9:0]),
.pop(pop),
.push(push),
.state(state[3:0]),
.umbral_inferior(umbral_inferior[2:0]),
.umbral_superior(umbral_superior[2:0])
);
endmodule
| 6.995131 |
module BancoPruebas_MUX; // Testbench
wire [9:0] Out0_conduct, Out1_conduct, Out2_conduct, Out3_conduct;
wire [9:0] Out0_estruct, Out1_estruct, Out2_estruct, Out3_estruct;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] P0; // From prob of Probador_MUX.v
wire [9:0] P1; // From prob of Probador_MUX.v
wire [9:0] P2; // From prob of Probador_MUX.v
wire [9:0] P3; // From prob of Probador_MUX.v
wire clk; // From prob of Probador_MUX.v
wire [3:0] state; // From prob of Probador_MUX.v
// End of automatics
MUX conductual (
.Out0(Out0_conduct),
.Out1(Out1_conduct),
.Out2(Out2_conduct),
.Out3(Out3_conduct),
/*AUTOINST*/
// Inputs
.clk (clk),
.state (state[3:0]),
.P0 (P0[9:0]),
.P1 (P1[9:0]),
.P2 (P2[9:0]),
.P3 (P3[9:0])
);
Probador_MUX prob (
/*AUTOINST*/
// Outputs
.clk (clk),
.state (state[3:0]),
.P0 (P0[9:0]),
.P1 (P1[9:0]),
.P2 (P2[9:0]),
.P3 (P3[9:0]),
// Inputs
.Out0_conduct (Out0_conduct[9:0]),
.Out1_conduct (Out1_conduct[9:0]),
.Out2_conduct (Out2_conduct[9:0]),
.Out3_conduct (Out3_conduct[9:0]),
.Out0_estruct (Out0_estruct[9:0]),
.Out1_estruct (Out1_estruct[9:0]),
.Out2_estruct (Out2_estruct[9:0]),
.Out3_estruct (Out3_estruct[9:0])
);
MUX_estruct estructural (
.Out0(Out0_estruct),
.Out1(Out1_estruct),
.Out2(Out2_estruct),
.Out3(Out3_estruct),
/*AUTOINST*/
// Inputs
.P0(P0[9:0]),
.P1(P1[9:0]),
.P2(P2[9:0]),
.P3(P3[9:0]),
.clk(clk),
.state(state[3:0])
);
endmodule
| 6.995131 |
module BancoPrueba_contador();
parameter FIFO_UNITS = 4;
parameter INDEX = 2;
wire clk;
wire reset;
wire req;
wire [INDEX-1:0] idx;
wire IDLE;
wire pop_0;
wire pop_1;
wire pop_2;
wire pop_3;
wire [4:0] cuenta;
wire [4:0] cuenta_sint;
wire [4:0] contador_4;
wire [4:0] contador_4_sint;
wire valid;
wire valid_sint;
contador #(.FIFO_UNITS(FIFO_UNITS),
.INDEX(INDEX)) contador_cond1 (
.clk(clk),
.reset(reset),
.req(req),
.idx(idx),
.IDLE(IDLE),
.pop(pop),
.pop_0(pop_0),
.pop_1(pop_1),
.pop_2(pop_2),
.pop_3(pop_3),
.cuenta(cuenta),
.contador_4(contador_4),
.valid(valid)
);
contador_sint #(.FIFO_UNITS(FIFO_UNITS),
.INDEX(INDEX)) contador_sint1 (
.clk(clk),
.reset(reset),
.req(req),
.idx(idx),
.IDLE(IDLE),
.pop(pop),
.pop_0(pop_0),
.pop_1(pop_1),
.pop_2(pop_2),
.pop_3(pop_3),
.cuenta_sint(cuenta_sint),
.contador_4_sint(contador_4_sint),
.valid_sint(valid_sint)
);
Probador_contador #(.FIFO_UNITS(FIFO_UNITS),
.INDEX(INDEX)) probador_contador1 (
.clk(clk),
.reset(reset),
.req(req),
.idx(idx),
.IDLE(IDLE),
.pop(pop),
.pop_0(pop_0),
.pop_1(pop_1),
.pop_2(pop_2),
.pop_3(pop_3),
.cuenta(cuenta),
.cuenta_sint(cuenta_sint),
.contador_4(contador_4),
.contador_4_sint(contador_4_sint),
.valid(valid),
.valid_sint(valid_sint)
);
// Se guarda el checkeo de cada salida
// checker para cuenta, cuenta_sint, valid y
reg [2:0] checker;
always @(*) begin
if (cuenta == cuenta_sint) checker[2] = 1;
else checker[2] = 0;
if (contador_4 == contador_4_sint) checker[1] = 1;
else checker[1] = 0;
if (valid == valid_sint) checker[0] = 1;
else checker[0] = 0;
end
endmodule
| 6.698287 |
module BancoReg (
input RegWrite,
input [4:0] RA1,
input [4:0] RA2,
input [31:0] WriteData,
input [4:0] AW,
output reg [31:0] DR1,
output reg [31:0] DR2
);
reg [31:0] Reg[0:31];
initial begin
$readmemb("BancoReg.mem", Reg);
end
always @* begin
if (RegWrite == 1) begin
Reg[AW] <= WriteData;
end
DR1 <= Reg[RA1];
DR2 <= Reg[RA2];
end
endmodule
| 6.555106 |
module BancoRegis (
EscreveReg,
clock,
inRA,
in1,
in2,
regEscrito,
dadoEscrito,
outRA,
out1,
out2
);
input wire EscreveReg;
input wire [1:0] inRA;
input wire [1:0] in1;
input wire [1:0] in2;
input wire [1:0] regEscrito;
input wire [7:0] dadoEscrito;
input wire clock;
output wire [7:0] outRA;
output wire [7:0] out1;
output wire [7:0] out2;
reg [7:0] registradores[3:0];
initial begin
registradores[0] = 0; // $zero
registradores[1] = 0;
registradores[2] = 0;
registradores[3] = 0;
end
always @(posedge clock) begin // Escrita
if (EscreveReg) begin
if (regEscrito != 0) begin
registradores[regEscrito] = dadoEscrito;
end
end
end
assign outRA = registradores[inRA];
assign out1 = registradores[in1];
assign out2 = registradores[in2];
endmodule
| 6.795783 |
module BancoRegistro #( // #( Parametros
parameter BIT_ADDR = 4, // BIT_ADDR Nmero de bit para la direccin
parameter BIT_DATO = 4, // BIT_DATO Nmero de bit para el dato
parameter RegFILE = "src/Reg16.men"
) (
input [BIT_ADDR-1:0] addrRa,
input [BIT_ADDR-1:0] addrRb,
output [BIT_DATO-1:0] datOutRa,
output [BIT_DATO-1:0] datOutRb,
input [BIT_ADDR-1:0] addrW,
input [BIT_DATO-1:0] datW,
input RegWrite,
input clk,
input rst
);
// La cantdiad de registros es igual a:
localparam NREG = 2 ** BIT_ADDR;
//configiracin del banco de registro
reg [BIT_DATO-1:0] breg[NREG-1:0];
assign datOutRa = breg[addrRa];
assign datOutRb = breg[addrRb];
always @(posedge clk) begin
if (RegWrite == 1) breg[addrW] <= datW;
end
initial begin
$readmemh(RegFILE, breg);
end
endmodule
| 8.80606 |
module banco_de_registradores (
clk,
rl1,
rl2,
resc,
dado,
h_esc,
d1,
d2
);
input clk;
input [31:0] dado; // dado a ser escrito
input [4:0] rl1, rl2, resc; //endereco dos regs
input h_esc;
output [31:0] d1, d2;
reg [31:0] x[31:0]; // 32 reg's de 32 bits
// x[0:25] de propósito geral (GPRs)
// x[26] $zero
// x[27] $aux
// x[28] rv - return value
// x[29] fp - frame pointer1
// x[30] sp - stack pointer
// x[31] ra - return address
always @(posedge (clk)) begin
if (h_esc == 1) x[resc] = dado; //escrita
end
//leituras
assign d1 = x[rl1];
assign d2 = x[rl2];
endmodule
| 6.889583 |
module Banco_Registro (
//Inputs
input [4:0] RA1,
input [4:0] RA2,
input [31:0] di,
input [4:0] dir,
input RW,
//Outputs
output reg [31:0] DR1,
output reg [31:0] DR2
);
reg [31:0] mem2[0:31];
initial begin
$readmemb("TestF1_BReg", mem2);
end
always @* begin
DR1 <= mem2[di];
DR2 <= mem2[di];
if (RW == 1) begin
mem2[dir] = di;
end
end
endmodule
| 7.598552 |
module Banco_Registros (
input Rst,
input Clk,
input [5:0] SelR, // SelR[2:0]->Rx, SelR[5:3]->Ry
input RW, // 0->leer, 1->escribir
input [7:0] DW,
output [7:0] Rx,
output [7:0] Ry
);
reg [7:0] Rgs[0:7];
always @(posedge Clk, posedge Rst) begin
if (Rst) begin
Rgs[0] <= 0;
Rgs[1] <= 0;
Rgs[2] <= 0;
Rgs[3] <= 0;
Rgs[4] <= 0;
Rgs[5] <= 0;
Rgs[6] <= 0;
Rgs[7] <= 0;
end else if (RW) Rgs[SelR[2:0]] <= DW;
end
assign Rx = Rgs[SelR[2:0]];
assign Ry = Rgs[SelR[5:3]];
endmodule
| 7.598552 |
module BancReg (
input RegEn,
input [4:0] RR1,
input [4:0] RR2,
input [4:0] WriteRegister,
input [31:0] WriteData,
output reg [31:0] RD1,
output reg [31:0] RD2
);
reg [31:0] Banco[0:31];
initial begin
$readmemh("TestF1_BReg.mem", Banco);
end
always @* begin
RD1 <= Banco[RR1];
RD2 <= Banco[RR2];
if (RegEn) begin
if (WriteData === 32'dx) begin
Banco[WriteRegister] = 32'd0;
end else begin
Banco[WriteRegister] = WriteData;
end
end
end
endmodule
| 6.652886 |
module BANDAI2003 (
input CLK,
input CEn,
input WEn,
input OEn,
input SSn,
output SO, /* Synchronous out */
input RSTn,
input [7:0] ADDR, /* A-1 to A3 + A15 to A18 */
inout [7:0] DQ, /* Warning: Tri-state */
output ROMCEn,
output RAMCEn,
output [6:0] RADDR /* ROM/RAM A15 to A21 */
);
reg [7:0] lckS; // Lock State - Addressed unlock sequence
localparam ADDR_ACK = 8'h5A;
localparam ADDR_NAK = 8'hA5;
localparam ADDR_NIH = 8'hFF;
wire LCKn = lckS != ADDR_NIH; // The end is nigh
reg [17:0] shR; // Shift Register - Right
// ¯\______/¯\_/¯\___/¯\_/¯\___/¯
// Bit-stream - Invokes SYSTEM_CTRL1 (A0h) bit 7 to 1.
localparam [17:0] bitS = {1'b0, 16'h28A0, 1'b0};
assign SO = ~RSTn ? 1'bZ : shR[0]; // Change hi-Z on cart
always @(posedge CLK or negedge RSTn) begin
if (~RSTn) begin
shR <= {(18) {1'b1}};
lckS <= ADDR_ACK;
end else if (LCKn && ADDR == lckS)
case (ADDR)
ADDR_ACK: lckS <= ADDR_NAK;
ADDR_NAK: begin
shR <= bitS;
lckS <= ADDR_NIH;
end
endcase
else shR <= {1'b1, shR[17:1]};
end
reg [7:0] bnkR[3:0]; // Bank Registers
localparam ADDR_LAO = 8'hC0; // Linear Address Offset
localparam ADDR_RAMB = 8'hC1; // RAM Bank
localparam ADDR_ROMB0 = 8'hC2; // ROM Bank #0
localparam ADDR_ROMB1 = 8'hC3; // ROM Bank #1
wire iBR = ~(SSn & CEn) && (ADDR >= ADDR_LAO && ADDR <= ADDR_ROMB1);
wire oBR = iBR && ~OEn && WEn;
assign DQ = ~LCKn && oBR ? bnkR[ADDR[1:0]] : 8'hZZ;
wire [7:0] iDQ = DQ;
wire rwC = OEn && WEn;
integer i;
always @(posedge rwC or negedge RSTn) begin
if (~RSTn) for (i = 0; i < 4; i = i + 1) bnkR[i] <= 8'hFF;
else if (~LCKn && iBR) bnkR[ADDR[1:0]] <= iDQ;
end
wire rCE = ~LCKn && SSn && ~CEn;
assign RAMCEn = ~(rCE && ADDR[7:4] == 4'h1);
assign ROMCEn = ~(rCE && ADDR[7:4] > 4'h1);
assign RADDR = ~RAMCEn || ~ROMCEn ? ADDR[7:4] > 4'h3 ? {bnkR[0][2:0], ADDR[7:4]} : bnkR[ADDR[5:4]][6:0] : 7'b0;
endmodule
| 7.617154 |
module BandFIR5503000 (
input wire clk, // clk.clk
input wire reset_n, // rst.reset_n
input wire [31:0] ast_sink_data, // avalon_streaming_sink.data
input wire ast_sink_valid, // .valid
input wire [ 1:0] ast_sink_error, // .error
output wire [31:0] ast_source_data, // avalon_streaming_source.data
output wire ast_source_valid, // .valid
output wire [ 1:0] ast_source_error // .error
);
BandFIR5503000_0002 bandfir5503000_inst (
.clk (clk), // clk.clk
.reset_n (reset_n), // rst.reset_n
.ast_sink_data (ast_sink_data), // avalon_streaming_sink.data
.ast_sink_valid (ast_sink_valid), // .valid
.ast_sink_error (ast_sink_error), // .error
.ast_source_data (ast_source_data), // avalon_streaming_source.data
.ast_source_valid(ast_source_valid), // .valid
.ast_source_error(ast_source_error) // .error
);
endmodule
| 6.588166 |
module bandpass3 (
input clk, // timespec 9.4 ns
input signed [15:0] inp,
input zerome,
input oe,
output reg signed [17:0] out,
input signed [16:0] cm1,
input signed [16:0] d
);
// cm1 and d are host-settable registers
// cm1 (read "c minus 1") and d are signed 17-bit
// integers, representing real numbers -0.5<=x<+0.5.
// That is, take the integer in the range -65536 to 65535
// and divide by 131072 to get the real number.
// z-transform filter gain
// (1-z^{-1})/(a + b*z^{-1} + c*z^{-2} + d*z^{-3})
// hard-code a=1, b=-1, and use c=(1+cm1)
//
// With default cm1=0, d=0, turns into an infinite-Q filter centered
// at acos(-b/2) = 2*pi/6 = 0.167*2*pi, close to APEX's 0.143*2*pi.
// Use host-settable cm1 and d to adjust frequency and Q as desired,
// see cubicr.m.
//
// Input differentiator expects dominant signal at 1/7*f_S.
// For an input A*sin(n*theta), max (1-z^{-1}) amplitude is
// A*2*sin(theta/2) = A*0.8678. Accept the full range of input
// by including the next most significant bit; the next step will
// sign extend this a few bits anyway.
reg signed [15:0] ireg = 0, ireg1 = 0; // binary point to left of ireg[15]
reg signed [16:0] d1 = 0; // binary point to left of d1[15]
// Q can be arbitrarily high, and this module will just clip.
reg signed [19:0] r0 = 0;
reg signed [18:0] r1 = 0;
reg signed [33:0] p1 = 0, p2 = 0;
reg signed [19:0] s0 = 0;
wire signed [19:0] p1s = p1[33:14];
wire signed [19:0] p2s = p2[33:14];
// Universal definition; note: old and new are msb numbers, not bit widths.
`define SAT(x, old, new) ((~|x[old:new] | &x[old:new]) ? x : {x[old],{new{~x[old]}}})
always @(posedge clk) begin
ireg <= inp;
ireg1 <= ireg;
d1 <= ireg - ireg1;
// conceptually: r2 <= r1 <= r0 <= d1 + r0 - (1+cm1)*r1 - d*r2;
r1 <= {19{~zerome}} & `SAT(r0, 19, 18); // avoid wind-up, implement clear
p1 <= cm1 * $signed(r0[19:3]);
p2 <= d * $signed(r0[19:3]);
s0 <= d1 - p2s + 1;
r0 <= r0 + s0 - (p1s + r1);
if (oe) out <= r1[18:1];
end
endmodule
| 7.705712 |
module bandpass3_tb;
reg clk;
integer cc;
// Integer values for cm1 and d are
// scaled by 2^17 from real value. See cset.m
reg signed [16:0] cm1, d;
initial begin
if (!$value$plusargs("cm1=%d", cm1)) cm1 = 7510;
if (!$value$plusargs("d=%d", d)) d = -23395;
for (cc = 0; cc < 500; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
$finish();
end
`define COHERENT_DEN 7
`define RF_NUM 1
integer ccr;
real volt;
reg signed [15:0] ind = 0, temp = 0;
always @(posedge clk) begin
if (cc == 10) begin // impulse response
ind <= 30000;
end else if (cc > 200 && cc < 300) begin // check for clipping: max amp at center
ccr = cc % `COHERENT_DEN;
volt = $sin(`M_TWO_PI * `RF_NUM * ccr / `COHERENT_DEN);
temp = $floor(3500 * volt + 0.5);
ind <= temp;
end else begin
ind <= 0;
end
end
wire signed [17:0] outd;
bandpass3 mut (
.clk(clk),
.inp(ind),
.oe(1'b1),
.zerome(1'b0),
.out(outd),
.cm1(cm1),
.d(d)
);
always @(negedge clk) $display("%d %d", ind, outd);
endmodule
| 6.892856 |
module: bandpass
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bandpass_test;
// Inputs
reg clk;
reg rst;
reg [7:0] x;
// Outputs
wire [9:0] dataout;
// Instantiate the Unit Under Test (UUT)
bandpass uut (
.clk(clk),
.rst(rst),
.x(x),
.dataout(dataout)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
x = 0;
#100;
rst = 1;
#100;
rst = 0;
x = 8'd5;
#100;
x = 8'd10;
#100;
x = 8'd12;
#100;
x = 8'd15;
#100;
x = 8'd16;
#100;
end
always begin #50 clk=~clk;
end
endmodule
| 6.633353 |
module bank64k (
clk,
rd_en,
rd_addr,
rd_muxcode,
wr_en,
wr_addr,
wr_muxcode,
rdi_word,
wri_word,
rdd_word,
wrd_word,
rdc_word,
wrc_word
);
/* Parameters */
parameter w = 64;
parameter a = 10;
parameter C_DISABLE_WARN_BHV_COLL = 0;
/* Interface */
input wire clk;
input wire rd_en;
input wire [a-1 : 0] rd_addr;
input wire [1 : 0] rd_muxcode;
input wire wr_en;
input wire [a-1 : 0] wr_addr;
input wire [1 : 0] wr_muxcode;
output wire [w-1 : 0] rdi_word;
output wire [w-1 : 0] rdd_word;
output wire [w-1 : 0] rdc_word;
input wire [w-1 : 0] wri_word;
input wire [w-1 : 0] wrd_word;
input wire [w-1 : 0] wrc_word;
/* Local */
wire [w-1 : 0] rd_word;
reg [w-1 : 0] wr_word;
genvar i;
/* Wiring */
/* Muxed Write */
/* DOES NOT WORK IN SIM
generate for(i=0;i<w;i=i+1) begin:mux
reg[2:0] wr_bits;
always @(wri_word or wrd_word or wrc_word or wr_muxcode) begin
wr_bits = {wri_word[i], wrd_word[i], wrc_word[i]};
wr_word[i] = wr_bits[wr_muxcode];
end
end endgenerate
*/
always @(wri_word or wrd_word or wrc_word or wr_muxcode) begin
case (wr_muxcode)
2'b00: wr_word = wri_word;
2'b01: wr_word = wrd_word;
2'b10: wr_word = wrc_word;
default: wr_word = {w{1'b0}};
endcase
end
/* Bcast Read */
assign rdi_word = rd_word;
assign rdd_word = rd_word;
assign rdc_word = rd_word;
/* Temporary signals */
wire [w-1 : 0] douta;
wire [w-1 : 0] dinb;
// Temporary assignments
assign dinb = 0;
/* 64k internal BRAM */
`ifdef INTEL
bram64k b (
clk,
wr_word,
rd_addr,
wr_addr,
wr_en,
rd_word
);
`elsif XILINX
bram64k_64x1024_xilinx b (
.clka (clk), // input wire clka
.ena (1'b1), // always enabled
.wea (wr_en), // input wire [0 : 0] wea
.addra(wr_addr), // input wire [9 : 0] addra
.dina (wr_word), // input wire [63 : 0] dina
.douta(douta), // output data (going nowhere, for now)
.clkb (clk), // input wire clkb
.enb (rd_en), // input wire enb
.web (1'b0), // disable writes on second port (for now)
.addrb(rd_addr), // input wire [9 : 0] addrb
.dinb (dinb), // input data (going nowhere, for now)
.doutb(rd_word) // output wire [64 : 0] doutb
);
`else
$display("ERROR: INTEL or XILINX macro not defined!");
`endif
/* Module end */
endmodule
| 6.672932 |
module CACHE_ATTR_{{ name }}(CLK, A0, A1, D0, D1, WE0, WE1, Q0, Q1);
parameter W_A = 19;
parameter W_INDEX = 7;
parameter N_LINE = 128;
parameter W_ATTR = 7;
input CLK;
input [W_INDEX-1:0] A0;
input [W_INDEX-1:0] A1;
input [W_ATTR-1:0] D0;
input [W_ATTR-1:0] D1;
input WE0;
input WE1;
output [W_ATTR-1:0] Q0;
output [W_ATTR-1:0] Q1;
`ifndef SIM
(* RAM_STYLE="BLOCK" *)
`endif
reg [W_ATTR-1:0] mem [0:N_LINE-1];
reg [W_INDEX-1:0] d_A0;
reg [W_INDEX-1:0] d_A1;
always @(posedge CLK) begin
d_A0 <= A0;
d_A1 <= A1;
if(WE0)
mem[A0] <= D0;
if(WE1)
mem[A1] <= D1;
end
assign Q0 = mem[d_A0];
assign Q1 = mem[d_A1];
endmodule
| 6.510423 |
module displaySelection (
dig0,
dig1,
dig2,
dig3,
bankClosed,
queueNum,
totalCus,
teller1call,
teller0call,
notRdyCls,
waitingCus,
blinkOff /*, pswrdCH*/
);
parameter a = 5'd10, b = 5'd11, c = 5'd12, d = 5'd13, h = 5'd19;
parameter e = 5'd14, f = 5'd15, o = 5'd16, L = 5'd17, p = 5'd18, r = 5'd20;
output reg [4:0] dig0, dig1, dig2, dig3;
input bankClosed, notRdyCls;
input blinkOff, queueNum /*, pswrdCH*/;
input [7:0] totalCus, teller1call, teller0call, waitingCus;
always @(*)
if(!bankClosed) //bank closed
begin
dig3 = c;
dig2 = L;
dig1 = 5'd5; //s
dig0 = d;
end
else if(blinkOff) //ssd's are not ilmunated (used for blinking)
begin
dig3 = 5'b11111;
dig2 = 5'b11111;
dig1 = 5'b11111;
dig0 = 5'b11111;
end
else if(queueNum) //show taken number
begin
dig3 = 5'b11111;
dig2 = 5'b11111;
dig1 = {1'b0, totalCus[7:4]};
dig0 = {1'b0, totalCus[3:0]};
end
else if(notRdyCls) //show taken number
begin
dig3 = r;
dig2 = 5'd12; //c
dig1 = {1'b0, waitingCus[7:4]};
dig0 = {1'b0, waitingCus[3:0]};
end /* else if(pswrdCH) //ch pasword mode
begin
dig3 = 5'd12; //c
dig2 = h;
dig1 = p;//
dig0 = 5'd5; //s
end */
else begin //last called number
dig3 = {1'b0, teller1call[7:4]};
dig2 = {1'b0, teller1call[3:0]};
dig1 = {1'b0, teller0call[7:4]};
dig0 = {1'b0, teller0call[3:0]};
end
endmodule
| 7.1205 |
module BankR (
//Entradas
input Rw,
input [4:0] Rd1,
input [4:0] Rd2,
input [4:0] Dir,
input [31:0] DIn,
//Salidas
output reg [31:0] L1,
output reg [31:0] L2
);
//2- Delcaracion de señales --> NA(No aplica)
//Registros
reg [31:0] BReg[0:31];
//3- Cuerpo del modulo (NA)
//Pre-Charge Reading.
initial begin
$readmemh("TestBankR3", BReg);
end
//Bloque Always
always @* begin //Inicio_A
//AlwaysReading
L1 = BReg[Rd1];
L2 = BReg[Rd2];
if (Rw) //Writting
BReg[Dir] <= DIn;
//Test
$display(" Rw[%d]; Rd1[%d]: %d; Rd2[%d]: %d; Din[%d]; BReg[%d]: %d;", Rw, Rd1, L1, Rd2, L2,
DIn, Dir, BReg[Dir]);
end
endmodule
| 6.614944 |
module bankRAM #(
parameter NO_BANKS = 2,
DATA_WIDTH = 4,
DEPTH = 4096,
MEM_FILE = ""
) (
input wire clk_rd,
input wire clk_wr,
input wire [NO_BANKS-1:0] wr_bank_select,
input wire [NO_BANKS-1:0] rd_bank_select,
input wire [NO_BANKS-1:0] wr_en,
input wire [ADDR_WIDTH-1:0] addr_wr,
input wire [ADDR_WIDTH-1:0] addr_rd,
input wire [DATA_WIDTH-1:0] data_wr,
output reg [DATA_WIDTH-1:0] data_rd
);
localparam ADDR_WIDTH = $clog2(DEPTH);
localparam MEM_FILE2 = "/home/saviour/study/fpga_spectrogram/src/videogen/helpers/samplehex2.mi";
wire [DATA_WIDTH-1:0] read1, read2;
sdpRAM #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH),
.MEM_FILE(MEM_FILE)
) RAM0 (
.clk_wr(clk_wr),
.clk_rd(clk_rd),
.we((wr_en[0] && wr_bank_select[0])),
.addr_wr(addr_wr),
.addr_rd(addr_rd),
.data_wr(data_wr),
.data_rd(read1)
);
sdpRAM #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH),
.MEM_FILE(MEM_FILE2)
) RAM1 (
.clk_wr(clk_wr),
.clk_rd(clk_rd),
.we((wr_en[1] && wr_bank_select[1])),
.addr_wr(addr_wr),
.addr_rd(addr_rd),
.data_wr(data_wr),
.data_rd(read2)
);
//TODO: FIGURE OUT DYNAMIC ALTERNATIVE TO CASE, FOR NOW, ONWARDS!!!
always @(posedge clk_rd) begin
case (rd_bank_select)
2'b01: data_rd = read1;
2'b10: data_rd = read2;
default: data_rd = read1;
endcase
end
endmodule
| 7.274169 |
module BANK_INIT #(
parameter length = 32,
parameter R = 5,
parameter DATA_LENGTH = 256
) (
// SYSTEM I/O
input i_clk,
input i_rst,
// FFT CONTROLLER
input i_BI_en,
// ROM
input [2*length-1:0] i_rom_data,
output reg [9:0] o_rom_addr,
// memory bank0
output reg [R-2:0] o_m0_addr,
output reg [2*length-1:0] o_m0_data,
output reg o_m0_w_en,
// memory bank1
output reg [R-2:0] o_m1_addr,
output reg [2*length-1:0] o_m1_data,
output reg o_m1_w_en
);
// parameter, reg, wire
localparam ST_IDLE = 0;
localparam ST_ROM_ADDR_OUT = 1;
localparam ST_ROM_DATA_IN = 2;
localparam ST_MEMORY_ADDR_OUT = 3;
localparam ST_MEMORY_WRITE = 4;
localparam ST_DONE = 5;
reg [ 2:0] r_ps;
reg [R-1:0] r_cnt;
// Sequential Logic
always @(posedge i_clk) begin
if (i_rst) begin
o_rom_addr <= 0;
o_m0_data <= 0;
o_m0_addr <= 0;
o_m0_w_en <= 0;
o_m1_data <= 0;
o_m1_addr <= 0;
o_m1_w_en <= 0;
r_cnt <= 0;
r_ps <= ST_IDLE;
end else begin
case (r_ps)
ST_IDLE: begin
if (i_BI_en) r_ps <= ST_ROM_ADDR_OUT;
end
ST_ROM_ADDR_OUT: begin
r_ps <= ST_ROM_DATA_IN;
end
ST_ROM_DATA_IN: begin
r_ps <= ST_MEMORY_ADDR_OUT;
end
ST_MEMORY_ADDR_OUT: begin
if (^r_cnt) begin
r_ps <= ST_MEMORY_WRITE;
o_m1_w_en <= 1;
o_m1_addr <= r_cnt[R-2:0];
o_m1_data <= i_rom_data;
end else begin
r_ps <= ST_MEMORY_WRITE;
o_m0_w_en <= 1;
o_m0_addr <= r_cnt[R-2:0];
o_m0_data <= i_rom_data;
end
end
ST_MEMORY_WRITE: begin
r_ps <= ST_DONE;
r_cnt <= r_cnt + 1'b1;
o_m1_w_en <= 0;
o_m0_w_en <= 0;
end
ST_DONE: begin
r_ps <= ST_IDLE;
if (o_rom_addr == DATA_LENGTH - 1) o_rom_addr <= 0;
else o_rom_addr <= o_rom_addr + 1'b1;
end
default: r_ps <= ST_IDLE;
endcase
end
end
endmodule
| 6.780637 |
module bank_out_arb (
input wire [15:0] rw1_data,
input wire [15:0] rw2_data,
input wire [15:0] rw3_data,
input wire rw1_valid,
input wire rw2_valid,
input wire rw3_valid,
input wire [1:0] rw1_req_tag,
input wire [1:0] rw2_req_tag,
input wire [1:0] rw3_req_tag,
input wire [15:0] r1_data,
input wire [15:0] r2_data,
input wire [15:0] r3_data,
input wire r1_valid,
input wire r2_valid,
input wire r3_valid,
input wire [1:0] r1_req_tag,
input wire [1:0] r2_req_tag,
input wire [1:0] r3_req_tag,
output wire [15:0] port1_data,
output wire [15:0] port2_data,
output wire [15:0] port3_data,
output wire port1_valid,
output wire port2_valid,
output wire port3_valid,
output wire [1:0] port1_req_tag,
output wire [1:0] port2_req_tag,
output wire [1:0] port3_req_tag
);
wire [18:0] rw1_in;
wire [18:0] rw2_in;
wire [18:0] rw3_in;
assign rw1_in = {rw1_valid, rw1_data, rw1_req_tag};
assign rw2_in = {rw2_valid, rw2_data, rw2_req_tag};
assign rw3_in = {rw3_valid, rw3_data, rw3_req_tag};
wire [18:0] r1_in;
wire [18:0] r2_in;
wire [18:0] r3_in;
assign r1_in = {r1_valid, r1_data, r1_req_tag};
assign r2_in = {r2_valid, r2_data, r2_req_tag};
assign r3_in = {r3_valid, r3_data, r3_req_tag};
reg [18:0] port1_out;
reg [18:0] port2_out;
reg [18:0] port3_out;
assign {port1_valid, port1_data, port1_req_tag} = port1_out;
assign {port2_valid, port2_data, port2_req_tag} = port2_out;
assign {port3_valid, port3_data, port3_req_tag} = port3_out;
always @(*) begin
case ({
rw1_valid, r1_valid
})
2'b01: begin
port1_out = r1_in;
end
2'b10: begin
port1_out = rw1_in;
end
2'b11: begin
port1_out = r1_in;
end
default: begin
port1_out = 0;
end
endcase
case ({
rw2_valid, r2_valid
})
2'b01: begin
port2_out = r2_in;
end
2'b10: begin
port2_out = rw2_in;
end
2'b11: begin
port2_out = r2_in;
end
default: begin
port2_out = 0;
end
endcase
case ({
rw3_valid, r3_valid
})
2'b01: begin
port3_out = r3_in;
end
2'b10: begin
port3_out = rw3_in;
end
2'b11: begin
port3_out = r3_in;
end
default: begin
port3_out = 0;
end
endcase
end
endmodule
| 7.382603 |
module bank_sel (
input wire [ 1:0] sel_in,
output reg [18:0] x_out
);
always @* begin
case (sel_in)
2'b00: begin
x_out = 19'd0;
end
2'b01: begin
x_out = 19'd174763;
end
2'b10: begin
x_out = 19'd349525;
end
2'b11: begin
x_out = 19'bz;
end
default: begin
x_out = 19'bz;
end
endcase
end
endmodule
| 6.697374 |
module bank_switch #(
parameter COUNT = 24,
parameter MSB = COUNT - 1,
parameter TICKS = 4,
parameter TSB = TICKS - 1,
parameter DELAY = 3
) (
input clk_x, // correlator clock
input rst_x,
input clk_i, // bus clock
input rst_i,
input ce_i,
input [MSB:0] bcount_i, // block size - 1
input frame_i, // new antenna data
output swap_x, // NOTE: correlator domain
output swap_o // NOTE: bus domain
);
reg sw = 1'b0, switch = 1'b0;
reg sw_x = 0, sw_d = 0; // correlator domain
reg sw_b = 1'b0; // bus domain
assign swap_x = sw;
assign swap_o = switch;
//-------------------------------------------------------------------------
//
// Hardware-correlator bank-switching control logic.
//
//-------------------------------------------------------------------------
wire [COUNT:0] next_count = wrap_count ? {COUNT + 1{1'b0}} : count + 1;
wire wrap_count = count == bcount_i;
reg [ MSB:0] count = {COUNT{1'b0}};
reg [ TSB:0] delays = {TICKS{1'b0}};
//-------------------------------------------------------------------------
// Count the number of correlations for the current bank, and signal a
// bank-switch when the counter reaches its maximum.
always @(posedge clk_x)
if (rst_x) begin
sw <= #DELAY 1'b0;
count <= #DELAY {COUNT{1'b0}};
end else if (ce_i) begin
sw <= #DELAY delays[TSB] && wrap_count; // signal an upcoming bank-swap
count <= #DELAY frame_i ? next_count[MSB:0] : count;
end else begin
sw <= #DELAY 1'b0;
count <= #DELAY count;
end
always @(posedge clk_x) delays <= #DELAY{delays[TSB-1:0], !rst_x && frame_i};
//-------------------------------------------------------------------------
// Synchronise the bank-switching signal to the bus domain.
//-------------------------------------------------------------------------
// TODO: Is this OK?
always @(posedge clk_x)
if (rst_x || frame_i) sw_x <= #DELAY 1'b0;
else if (sw) sw_x <= #DELAY 1'b1;
else sw_x <= #DELAY sw_x;
always @(posedge clk_x)
if (rst_x) sw_d <= #DELAY 0;
else sw_d <= #DELAY sw_x && frame_i;
always @(posedge clk_i or posedge sw_d)
if (sw_d) sw_b <= #DELAY 1'b1;
else if (rst_i || switch) sw_b <= #DELAY 1'b0;
always @(posedge clk_i)
if (rst_i) switch <= #DELAY 1'b0;
else switch <= #DELAY sw_b && !switch;
endmodule
| 8.024708 |
module Bank_tb;
reg clk;
reg rst_n;
reg [8*`PIXEL-1:0] ref_in;
reg Bank_sel;
reg [6:0] address;
reg [6:0] write_address;
reg rd_en;
wire [8*`PIXEL-1:0] ref_ou;
Bank bank (
.clk(clk),
.rst_n(rst_n),
.ref_in(ref_in),
.Bank_sel(Bank_sel),
.address(address),
.write_address(write_address),
.rd_en(rd_en),
.ref_ou(ref_ou)
);
initial clk = 1'b0;
always #5 clk = ~clk;
initial begin
rst_n = 1'b0;
#10 rst_n = 1'b1;
// 已修改，（先从B端口写入一些数据，地址由bank自动生成1，2，..96）
Bank_sel = 1'b0;
write_address = 7'b0000000;
ref_in = {8{8'b00000000}};
#30 ref_in = {8{8'b00000001}};
write_address = 7'b0000001;
#30 ref_in = {8{8'b00000011}};
write_address = 7'b0000011;
#30 ref_in = {8{8'b00000100}};
write_address = 7'b0000100;
#30 ref_in = {8{8'b00000101}};
write_address = 7'b0000101;
#100 address = 7'b0000000;
rd_en = 1'b0;
#10 address = 7'b0000001;
#10 address = 7'b0000011;
#10 address = 7'b0000100;
#10 address = 7'b0000101;
end
initial $monitor($time, " ref_ou = %b", ref_ou);
endmodule
| 6.620064 |
module banyan #(
parameter dw = 16, // data width
parameter np = 8, // number of ports, must be a power of 2
parameter rl = 3 // number of routing layers == log_2(np)
) (
input clk,
input [rl-1:0] time_state,
input [np-1:0] mask_in,
input [dw*np-1:0] data_in,
output [np-1:0] mask_out, // for DPRAM write-enable
output [dw*np-1:0] data_out
);
localparam M = np / 2; // number of swap-boxes
wire two_or_more; // use balance mode, when more than one bit of mask is set
two_set #(
.dw(np)
) two_set (
.d (mask_in),
.two(two_or_more)
);
wire [M-1:0] mask_upper = mask_in[2*M-1:M];
wire [M-1:0] mask_lower = mask_in[M-1:0];
wire any_lower = |mask_lower;
// The below statement creates a Ripple-Carry chain of xors with the initial
// bit being fed from the right (a 1'b0). The in and out refer to the circuit
// verilator lint_save
// verilator lint_off UNOPTFLAT
wire [M:0] imbalance_in;
wire [M-1:0] imbalance_out = imbalance_in ^ mask_upper ^ mask_lower;
assign imbalance_in = {imbalance_out, 1'b0};
// verilator lint_restore
// Priority set sources to Lower sinks when in Balance.
// If currently NOT imbalanced, and lower is 0 and upper 1, Flip and route to Lower
// If currently imbalanced, and lower is 1 and upper 0, Flip and route to Upper
// You can at most flip M/2 channels
wire [M-1:0] flip_bal = imbalance_in & ~mask_upper & mask_lower
| ~imbalance_in & mask_upper & ~mask_lower;
// If only single source; Alternate routing to different sink based on time
wire [M-1:0] flip_deal = {M{~any_lower ^ time_state[rl-1]}};
wire [M-1:0] flip_ctl = two_or_more ? flip_bal : flip_deal;
reg [M-1:0] out_mask_upper = 0, out_mask_lower = 0, data_flip = 0;
reg [rl-1:0] recurse_time_state = 0; // upper bit will be ignored
always @(posedge clk) begin
out_mask_upper <= flip_ctl & mask_lower | ~flip_ctl & mask_upper;
out_mask_lower <= flip_ctl & mask_upper | ~flip_ctl & mask_lower;
recurse_time_state <= time_state;
data_flip <= flip_ctl; // pipeline
end
// Data goes through one cycle after control
reg [dw*np-1:0] stage = 0;
genvar jx;
generate
for (jx = 0; jx < M; jx = jx + 1) begin : ss
always @(posedge clk) begin
stage[(jx+0+1)*dw-1:(jx+0)*dw] <= data_flip[jx] ? data_in[(jx+M+1)*dw-1:(jx+M)*dw] : data_in[(jx+0+1)*dw-1:(jx+0)*dw];
stage[(jx+M+1)*dw-1:(jx+M)*dw] <= data_flip[jx] ? data_in[(jx+0+1)*dw-1:(jx+0)*dw] : data_in[(jx+M+1)*dw-1:(jx+M)*dw];
end
end
endgenerate
// Recursive step
generate
if (rl > 1) begin : halvsies
banyan #(
.rl(rl - 1),
.dw(dw),
.np(np / 2)
) top (
.clk(clk),
.time_state(recurse_time_state[rl-2:0]),
.mask_in(out_mask_upper),
.data_in(stage[dw*np-1:dw*np/2]),
.data_out(data_out[dw*np-1:dw*np/2]),
.mask_out(mask_out[2*M-1:M])
);
banyan #(
.rl(rl - 1),
.dw(dw),
.np(np / 2)
) bot (
.clk (clk),
.time_state(recurse_time_state[rl-2:0]),
.mask_in (out_mask_lower),
.data_in (stage[dw*np/2-1:0]),
.data_out (data_out[dw*np/2-1:0]),
.mask_out (mask_out[M-1:0])
);
end else begin : passthrough
// base of recursion
assign data_out = stage;
assign mask_out = {out_mask_upper, out_mask_lower};
end
endgenerate
endmodule
| 8.434589 |
module two_set #(
parameter dw = 8
) (
input [dw-1:0] d,
output one, // or more bits of d are set
output two // or more bits of d are set
);
wire one_lower, one_upper;
wire two_lower, two_upper;
generate
if (dw > 1) begin : split
two_set #(
.dw(dw / 2)
) lower (
.d (d[dw/2-1 : 0]),
.one(one_lower),
.two(two_lower)
);
two_set #(
.dw(dw - dw / 2)
) upper (
.d (d[dw-1 : dw/2]),
.one(one_upper),
.two(two_upper)
);
assign one = one_lower | one_upper;
assign two = two_lower | two_upper | (one_lower & one_upper);
end else begin : passthrough
// single bit case is trivial
assign one = d[0];
assign two = 0;
end
endgenerate
endmodule
| 7.676139 |
module banyan_mem_shell (
input clk, // timespec 6.1 ns
input [14:0] lb_addr,
input lb_write,
input [31:0] lb_data,
output [15:0] result,
output [15:0] status
);
// 8 blocks of RAM, each 4K x 16
parameter aw = 12;
parameter dw = 16;
// IOB latches on inputs
reg [14:0] addr = 0;
reg write = 0;
reg [31:0] data = 0;
always @(posedge clk) begin
addr <= lb_addr;
write <= lb_write;
data <= lb_data;
end
// Semi-realistic local bus control
reg [7:0] banyan_mask = 0;
reg rnd_run = 0;
reg trig = 0;
wire init_1 = write & (addr == 1);
wire init_2 = write & (addr == 2);
wire init_3 = write & (addr == 3);
wire init_4 = write & (addr == 4);
always @(posedge clk) if (write & (addr == 5)) banyan_mask <= data;
always @(posedge clk) if (write & (addr == 7)) rnd_run <= data;
always @(posedge clk) trig <= write & (addr == 0);
// 128 bits of pseudo-randomness
wire [31:0] random1, random2, random3, random4;
tt800 r1 (
.clk(clk),
.en(rnd_run | init_1),
.init(init_1),
.initv(data),
.y(random1)
);
tt800 r2 (
.clk(clk),
.en(rnd_run | init_2),
.init(init_2),
.initv(data),
.y(random2)
);
tt800 r3 (
.clk(clk),
.en(rnd_run | init_3),
.init(init_3),
.initv(data),
.y(random3)
);
tt800 r4 (
.clk(clk),
.en(rnd_run | init_4),
.init(init_4),
.initv(data),
.y(random4)
);
wire [127:0] fake_adc = {random1, random2, random3, random4};
// Simple one-shot fill
reg run = 0;
wire rollover, full;
always @(posedge clk) if (trig | rollover) run <= trig;
wire reset = trig;
// DUT instantiation
wire [aw+3-1:0] pointer;
wire [aw+3-1:0] ro_addr = addr;
wire [dw-1:0] ro_data;
banyan_mem #(
.aw(aw),
.dw(dw)
) banyan_mem (
.clk(clk),
.adc_data(fake_adc),
.banyan_mask(banyan_mask),
.reset(reset),
.run(run),
.pointer(pointer),
.rollover(rollover),
.full(full),
.ro_clk(clk),
.ro_addr(ro_addr),
.ro_data(ro_data)
);
// IOB latch on output
reg [dw-1:0] result_r = 0;
always @(posedge clk) result_r <= ro_data;
assign result = result_r;
reg [15:0] status = 0;
always @(posedge clk) status <= {full, run, pointer};
endmodule
| 8.263614 |
module banyan_mem_tb;
parameter dw = 12;
parameter aw = 4;
reg clk;
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("banyan_mem.vcd");
$dumpvars(7, banyan_mem_tb);
end
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 2000; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
$display("PASS");
$finish(0);
end
// Create input test data that is easy to understand
reg [8*dw-1:0] test = 0;
integer ix;
reg [7:0] cx = 0;
reg data_valid = 1;
always @(posedge clk) begin
cx <= cx + 1;
for (ix = 0; ix < 8; ix = ix + 1) test[(ix)*dw+:dw] <= ((ix + 1) << 8) + cx;
if (cc > 1600) data_valid <= cx[0];
end
// Main test vector setup
reg trig = 0;
reg [7:0] banyan_mask = 0;
always @(posedge clk) begin
trig <= 0;
case (cc)
6: banyan_mask <= 8'h01;
8: trig <= 1;
406: banyan_mask <= 8'h30;
408: trig <= 1;
806: banyan_mask <= 8'h55;
808: trig <= 1;
1206: banyan_mask <= 8'hff;
1208: trig <= 1;
1606: banyan_mask <= 8'hff;
1608: trig <= 1;
endcase
end
// Simple one-shot fill
reg run = 0, run_d = 0;
wire rollover, full;
always @(posedge clk) begin
if (trig | rollover) run <= trig;
run_d <= run;
end
wire reset = trig;
// DUT instantiation
wire [aw+3-1:0] pointer;
reg [aw+3-1:0] ro_addr = 0, ro_addr_d = 0;
wire [dw-1:0] ro_data;
banyan_mem #(
.aw(aw),
.dw(dw)
) dut3 (
.clk(clk),
.adc_data(test),
.banyan_mask(banyan_mask),
.reset(reset),
.run(run & data_valid),
.pointer(pointer),
.rollover(rollover),
.full(full),
.ro_clk(clk),
.ro_addr(ro_addr),
.ro_data(ro_data)
);
// Output status can be expected to cross clock domains.
// pointer readout is only intended to be valid if ~run.
// Stretch the reported run signal to guarantee that validity rule.
wire banyan_run_s = run_d | run;
wire [5:0] banyan_aw_fix = aw;
wire [19:0] pointer_fix = pointer;
wire [31:0] status = {banyan_run_s, full, banyan_aw_fix, 4'b0, pointer_fix};
// Readout
reg ro_done = 0, display_next = 0;
always @(posedge clk) begin
if (full & ~ro_done) ro_addr <= ro_addr + 1;
if (&ro_addr) ro_done <= 1;
if (~full) ro_done <= 0;
ro_addr_d <= ro_addr; // pipeline match
display_next <= full & ~ro_done;
end
always @(negedge clk) if (display_next) $display("%x %x %x", banyan_mask, ro_addr_d, ro_data);
endmodule
| 8.042747 |
module banyan_shell (
input clk, // timespec 6.1 ns
input [2:0] lb_addr,
input lb_write,
input [31:0] lb_data,
output [16:0] result
);
// IOB latches on inputs
reg [2:0] addr = 0;
reg write = 0;
reg [31:0] data = 0;
always @(posedge clk) begin
addr <= lb_addr;
write <= lb_write;
data <= lb_data;
end
reg run = 0;
reg [2:0] out_sel = 0;
reg [7:0] banyan_mask = 0;
reg [2:0] time_state = 0;
wire init_1 = write & (addr == 1);
wire init_2 = write & (addr == 2);
wire init_3 = write & (addr == 3);
wire init_4 = write & (addr == 4);
always @(posedge clk) if (write & (addr == 5)) banyan_mask <= data;
always @(posedge clk) if (write & (addr == 6)) out_sel <= data;
always @(posedge clk) if (write & (addr == 7)) run <= data;
always @(posedge clk) begin
if (write & (addr == 7)) time_state <= 0;
if (write & (addr == 0)) time_state <= time_state + 1;
end
// 128 bits of pseudo-randomness
wire [31:0] random1, random2, random3, random4;
tt800 r1 (
.clk(clk),
.en(run | init_1),
.init(init_1),
.initv(data),
.y(random1)
);
tt800 r2 (
.clk(clk),
.en(run | init_2),
.init(init_2),
.initv(data),
.y(random2)
);
tt800 r3 (
.clk(clk),
.en(run | init_3),
.init(init_3),
.initv(data),
.y(random3)
);
tt800 r4 (
.clk(clk),
.en(run | init_4),
.init(init_4),
.initv(data),
.y(random4)
);
wire [127:0] fake_adc = {random1, random2, random3, random4};
wire [ 7:0] mask_out;
wire [127:0] data_out;
`ifdef BASELINE
assign data_out = fake_adc;
assign mask_out = banyan_mask;
`else
banyan #(
.dw(16),
.np(8),
.rl(3)
) banyan (
.clk(clk),
.time_state(time_state),
.mask_in(banyan_mask),
.data_in(fake_adc),
.mask_out(mask_out),
.data_out(data_out)
);
`endif
reg [15:0] data_r = 0;
reg flag_r = 0;
always @(posedge clk) begin
data_r <= data_out[out_sel*16+15-:16];
flag_r <= mask_out[out_sel];
end
// IOB latch on output
reg [16:0] result_r = 0;
always @(posedge clk) result_r <= {flag_r, data_r};
assign result = result_r;
endmodule
| 8.713394 |
module banyan_tb;
parameter dw = 7;
reg clk;
reg trace, squelch;
integer cc;
integer pass_count = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("banyan_tb.vcd");
$dumpvars(5, banyan_tb);
end
trace = $test$plusargs("trace");
squelch = $test$plusargs("squelch");
for (cc = 0; cc < 2052; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
// 1*1 + 70*2 + 28*4 + 8*8 = 317
if (pass_count == 317) begin
$display("PASS");
$finish(0);
end else begin
$display("FAIL %d", pass_count);
$stop(0);
end
end
// Create input test data that is easy to understand
reg [8*dw-1:0] test;
integer ix;
initial for (ix = 0; ix < 8; ix = ix + 1) test[(ix)*dw+:dw] = (ix + 0) * 1;
// Fully exercise an 11-bit control word combining mask and time_step
// A lot of these patterns make no sense, but run through them anyway.
// Only patterns that are relevant will be checked.
reg [10:0] ctl = 0;
always @(posedge clk) ctl <= ctl + 1;
wire [8*dw-1:0] result;
wire [7:0] mask_in = ctl[10:3];
wire [2:0] time_state = ctl[2:0];
wire [7:0] mask_out;
banyan #(
.rl(3),
.np(8),
.dw(dw)
) dut3 (
.clk(clk),
.time_state(time_state),
.mask_in(mask_in),
.data_in(test[55:0]),
.data_out(result),
.mask_out(mask_out)
);
// Time align the input conditions with the (pipelined) output
parameter pipe_stages = 4;
reg [11*pipe_stages-1:0] ctl_pipe = 0;
reg [7:0] mask_out_r = 0;
always @(posedge clk) begin
ctl_pipe <= {ctl_pipe[(pipe_stages-1)*11-1:0], ctl};
mask_out_r <= mask_out;
end
// Display
reg [7:0] mask_disp;
reg [2:0] ts_disp;
reg [3:0] bit_cnt;
integer jx, fanout, appears, good;
reg fault;
reg [7:0] showme[0:7];
always @(negedge clk) begin
mask_disp = ctl_pipe[pipe_stages*11-1-:8];
ts_disp = ctl_pipe[pipe_stages*11-9-:3];
bit_cnt = 0;
for (ix = 0; ix < 8; ix = ix + 1) bit_cnt = bit_cnt + mask_disp[ix];
fanout = 8 / bit_cnt;
if ((bit_cnt == 1 || bit_cnt == 2 || bit_cnt == 4 || bit_cnt == 8) && (ts_disp < fanout)) begin
// This check process is purposefully insensitive to the order
// that data appears in the output. In real life this order
// will need to be "well known" by the host software that reads
// and assembles the results.
good = 0;
for (ix = 0; ix < 8; ix = ix + 1) begin
if (mask_disp[ix]) begin
// channel ix is found in the mask word, so it
// should appear exactly once in the output data
appears = 0;
for (jx = 0; jx < bit_cnt; jx += 1)
if (result[(ts_disp%fanout+jx*fanout)*dw+dw-1-:dw] == (ix + 0)) appears += 1;
if (appears == 1) good += 1;
end
end
fault = good != bit_cnt;
if (fault || trace) begin
for (ix = 0; ix < 8; ix = ix + 1) begin
showme[ix] = ".";
if (mask_out_r[ix] || ~squelch) showme[ix] = result[dw*(ix+1)-1-:dw] + "0";
end
$display("%x %d %x %1d : %c %c %c %c %c %c %c %c %s", mask_disp, ts_disp, mask_out_r,
bit_cnt, showme[7], showme[6], showme[5], showme[4], showme[3], showme[2],
showme[1], showme[0], fault ? "FAULT" : " .");
end
if (fault == 0) pass_count = pass_count + 1;
end
end
endmodule
| 7.009455 |
module designed to arbitrate different write port to BAR1.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module BAR1_WR_ARBITER (
rst_n,
init_rst_i,
//write port 0
wr_en0_i,
addr0_i,
wr_be0_i,
wr_d0_i,
//write port 1
wr_en1_i,
addr1_i,
wr_be1_i,
wr_d1_i,
//write port 2
wr_en2_i,
addr2_i,
wr_be2_i,
wr_d2_i,
//write port 3
wr_en3_i,
addr3_i,
wr_be3_i,
wr_d3_i,
//read port 0
rd_be0_i,
rd_d0_o,
//write port arbitration output
wr_en_o,
addr_o,
wr_be_o,
wr_d_o,
//write port feedback signals
ack0_n_o,
ack1_n_o,
ack2_n_o,
ack3_n_o,
rd_be_o,
rd_d_i,
busy_o
);
input rst_n;
input init_rst_i;
input wr_en0_i;
input [6:0] addr0_i;
input [3:0] wr_be0_i;
input [31:0] wr_d0_i;
input wr_en1_i;
input [6:0] addr1_i;
input [3:0] wr_be1_i;
input [31:0] wr_d1_i;
input wr_en2_i;
input [6:0] addr2_i;
input [3:0] wr_be2_i;
input [31:0] wr_d2_i;
input wr_en3_i;
input [6:0] addr3_i;
input [3:0] wr_be3_i;
input [31:0] wr_d3_i;
input [3:0] rd_be0_i;
output [31:0] rd_d0_o;
output wr_en_o;
output [6:0] addr_o;
output [3:0] wr_be_o;
output [31:0] wr_d_o;
output ack0_n_o;
output ack1_n_o;
output ack2_n_o;
output ack3_n_o;
output [3:0] rd_be_o;
input [31:0] rd_d_i;
output busy_o;
reg [31:0] rd_d0_o;
reg wr_en_o;
reg [6:0] addr_o;
reg [3:0] wr_be_o;
reg [31:0] wr_d_o;
reg ack0_n_o;
reg ack1_n_o;
reg ack2_n_o;
reg ack3_n_o;
reg [3:0] rd_be_o;
assign busy_o = wr_en0_i | wr_en1_i | wr_en2_i | wr_en3_i;
//write port arbitration
always @( * ) begin
if( !rst_n | init_rst_i ) begin
wr_en_o = 1'b0;
addr_o = 7'b0;
wr_be_o = 4'b0;
wr_d_o = 32'b0;
ack0_n_o = 1'b1;
ack1_n_o = 1'b1;
ack2_n_o = 1'b1;
ack3_n_o = 1'b1;
end
else begin
//write priority: port0 > port1 > port2 > port3
if( wr_en0_i ) begin
wr_en_o = wr_en0_i;
addr_o = addr0_i;
wr_be_o = wr_be0_i;
wr_d_o = wr_d0_i;
ack0_n_o = 1'b0;
ack1_n_o = 1'b1;
ack2_n_o = 1'b1;
ack3_n_o = 1'b1;
end
else if( wr_en1_i ) begin
wr_en_o = wr_en1_i;
addr_o = addr1_i;
wr_be_o = wr_be1_i;
wr_d_o = wr_d1_i;
ack0_n_o = 1'b1;
ack1_n_o = 1'b0;
ack2_n_o = 1'b1;
ack3_n_o = 1'b1;
end
else if ( wr_en2_i ) begin
wr_en_o = wr_en2_i;
addr_o = addr2_i;
wr_be_o = wr_be2_i;
wr_d_o = wr_d2_i;
ack0_n_o = 1'b1;
ack1_n_o = 1'b1;
ack2_n_o = 1'b0;
ack3_n_o = 1'b1;
end
else if ( wr_en3_i ) begin
wr_en_o = wr_en3_i;
addr_o = addr3_i;
wr_be_o = wr_be3_i;
wr_d_o = wr_d3_i;
ack0_n_o = 1'b1;
ack1_n_o = 1'b1;
ack2_n_o = 1'b1;
ack3_n_o = 1'b0;
end
else begin
wr_en_o = 1'b0;
addr_o = 7'b0;
wr_be_o = 4'b0;
wr_d_o = 32'b0;
ack0_n_o = 1'b1;
ack1_n_o = 1'b1;
ack2_n_o = 1'b1;
ack3_n_o = 1'b1;
end //if( wr_en0_i )
end //if( !rst_n | !en )
end
//read port control
always @( * ) begin
if( !rst_n | init_rst_i ) begin
rd_be_o = 4'b0;
rd_d0_o = 32'b0;
end else begin
if( !wr_en1_i & !wr_en2_i & !wr_en3_i ) begin
rd_be_o = rd_be0_i;
rd_d0_o = rd_d_i;
end
else begin
rd_be_o = 4'b0;
rd_d0_o = 32'b0;
end //if( wr_en1_i & wr_en2_i & wr_en3_i )
end //if( !rst_n | !en )
end
endmodule
| 8.894011 |
module BarColor (
input Clock,
Reset,
Start,
GradationEn,
input [6:0] Bar,
input [14:0] InColor,
output [14:0] OutColor,
output reg Busy,
End
);
wire [4:0] wInR = InColor[14:10];
wire [4:0] wInG = InColor[9:5];
wire [4:0] wInB = InColor[4:0];
reg [4:0] R, G, B;
assign OutColor = {R, G, B};
wire [6:0] wQuo;
Divider #(
.bw_Dsor(2),
.bw_Dend(7),
.bw_i(3)
) div (
.Clock(Clock),
.Reset(Reset),
.Start(Start),
.Dsor (2'd3),
.Dend (Bar),
.Quo (wQuo),
.End (DivEnd),
.Busy (DivBusy)
);
wire [5:0] wGradation = wQuo[5:0];
wire [4:0] wGradR, wGradG, wGradB;
wire wSatR, wSatG, wSatB; //飽和判定
assign {wSatR, wGradR} = wInR + wGradation;
assign {wSatG, wGradG} = wInG + wGradation;
assign {wSatB, wGradB} = wInB + wGradation;
always @(posedge Reset or posedge Clock) begin
if (Reset) begin
{Busy, End, R, G, B} <= 1'b0;
end else begin
if (GradationEn) begin
R <= (wSatR) ? 5'h1f : wGradR;
G <= (wSatG) ? 5'h1f : wGradG;
B <= (wSatB) ? 5'h1f : wGradB;
end else begin
{R, G, B} <= InColor;
end
End <= DivEnd;
if (Start) Busy <= 1'b1;
else if (DivEnd) Busy <= 1'b0;
end
end
endmodule
| 7.054949 |
module BarDraw (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
LRChange,
input [1:0] ActiveScreen,
// For FFTSequenser
input Start,
input DrawTop,
input [14:0] BarColor,
TopColor,
BGColor,
input [6:0] Bar, //描画するバーの高さ 0~96
input [6:0] Top, //トップの位置 0~96
output reg End,
Busy,
// For SRAMCtrl
input AddrValid,
output ReqBurstWrite,
output reg [8:0] X, //描画するバーの位置
output [17:0] WrAddress,
output [15:0] WrData
);
////////////////////////////////////////////////////
// Registers
reg [14:0] rColor;
reg rChannel;
reg [6:0] rBarTop, rY, rY2;
reg [8:0] rX;
////////////////////////////////////////////////////
// Net
assign ReqBurstWrite = Busy;
assign WrData = rColor; //MSB R54321,G54321,B54321 LSB
assign WrAddress = {ActiveScreen, rY2, rX};
wire wY_EqualBarBottom = (rY == 7'd96) && AddrValid;
wire [8:0] wX;
always @(posedge Clock or posedge Reset) begin
if (Reset) begin
rChannel <= 1'b1;
X <= 1'b0;
end else begin
if (LRChange) rChannel <= ~rChannel;
if (LRChange) begin
if (rChannel) X <= 9'd0;
else X <= 9'd399;
end else if (Start) begin
X <= wX;
end
end
end
// Increment and Decrementer
IncDec #(
.width(9)
) incdec (
.DecEn(rChannel),
.A(X),
.S(wX)
);
reg [6:0] rTopPos;
wire wDrawTopPos = (rTopPos == rY);
wire wDrawBar = (rBarTop <= rY);
always @(posedge Clock or posedge Reset) begin
if (Reset) begin
{End, Busy, rBarTop, rColor, rY, rY2, rX, rTopPos} <= 1'b0;
end else begin
if (Start) rX <= X;
if (Start) Busy <= 1'b1;
else if (wY_EqualBarBottom) Busy <= 1'b0;
if (Start) rTopPos <= 7'd96 - Top;
if (End) rBarTop <= 7'd0;
if (Start) rBarTop <= 7'd96 - Bar;
if (End) begin
rY <= 7'b0;
rY2 <= 7'b0;
end else if (Busy && AddrValid) begin
rY <= rY + 1'b1;
rY2 <= rY;
end
if (AddrValid) begin
if (DrawTop && wDrawTopPos) rColor <= TopColor;
else if (wDrawBar) rColor <= BarColor;
else rColor <= BGColor;
end
if (End) End <= 1'b0;
else if (wY_EqualBarBottom) End <= 1'b1;
end
end
endmodule
| 7.386399 |
module BarGraph #(
parameter IN_WIDTH = 8, ///< Input data
parameter OUT_WIDTH = 8, ///< Number of elements in bar display
parameter LSB = 0 ///< LSB of data word to look at (usually 0)
) (
input wire clk, ///< System clock
input wire rst, ///< System reset - active high & synchronous
input wire en, ///< Strobe for input data to update bar display
input wire [ IN_WIDTH-1:0] data, ///< Input data word (binary, unsigned)
output reg [OUT_WIDTH-1:0] bar ///< Output to LED bar
);
localparam OUT_RANGE = (OUT_WIDTH + LSB > IN_WIDTH) ? (IN_WIDTH - LSB) : OUT_WIDTH;
integer i;
always @(posedge clk) begin
if (rst) begin
bar <= 'd0;
end else begin
for (i = 0; i < OUT_RANGE; i = i + 1) begin
bar[i] <= |(data >> (i + LSB));
end
end
end
endmodule
| 7.085929 |
module BarGraph_tb ();
parameter IN_WIDTH = 8; ///< Input data
parameter OUT_WIDTH = 8; ///< Number of elements in bar display
parameter LSB = 0; ///< LSB of data word to look at (usually 0)
reg clk; ///< System clock
reg rst; ///< System reset - active high & synchronous
reg en; ///< Strobe for input data to update bar display
reg [ IN_WIDTH-1:0] data; ///< Input data word (binary; unsigned)
wire [OUT_WIDTH-1:0] bar; ///< Output to LED bar
initial begin
clk = 1'b0;
rst = 1'b1;
en = 1'b1;
data = 'd0;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b0;
end
always #1 clk = ~clk;
always @(posedge clk) begin
if (rst) data <= 'd0;
else data <= data + 2'd1;
end
BarGraph #(
.IN_WIDTH (IN_WIDTH), ///< Input data
.OUT_WIDTH(OUT_WIDTH), ///< Number of elements in bar display
.LSB (LSB) ///< LSB of data word to look at (usually 0)
) uut (
.clk (clk), ///< System clock
.rst (rst), ///< System reset - active high & synchronous
.en (en), ///< Strobe for input data to update bar display
.data(data), ///< [IN_WIDTH-1:0] Input data word (binary, unsigned)
.bar (bar) ///< [OUT_WIDTH-1:0] Output to LED bar
);
endmodule
| 7.223951 |
module barramentoT #(
parameter DATA_WIDTH = 16
) (
input [DATA_WIDTH-1:0] top,
output [DATA_WIDTH-1:0] outputT
);
assign outputT = top;
endmodule
| 8.372061 |
module barrel (
input wire [ 1:0] shift_type,
input wire [ 3:0] shift,
input wire [15:0] data_in,
output reg [15:0] data_out
);
parameter lsl = 2'b00, lsr = 2'b01, asr = 2'b10, ror = 2'b11;
always @(*) begin
if (shift_type == lsl) data_out = data_in << shift;
else if (shift_type == lsr) data_out = data_in >> shift;
else if (shift_type == asr) data_out = {{16{data_in[15]}}, data_in} >> shift;
else data_out = (data_in >> shift) | (data_in << (16 - shift));
end
endmodule
| 7.311845 |
module barrel16 (
data_in,
data_out,
rotate,
direction,
clk
);
input [15:0] data_in;
input [3:0] rotate;
input clk, direction;
output [15:0] data_out;
reg [15:0] data_out ;
reg [15:0] reg_data_in ;
reg [3:0] reg_rotate ;
reg reg_direction;
always @(posedge clk) begin
reg_data_in <= data_in;
reg_rotate <= rotate;
reg_direction <= direction;
// direction = 1, shift right
// direction = 0, shift left
if (reg_direction) begin
case (reg_rotate)
4'b0000: data_out <= reg_data_in[15:0];
4'b0001: data_out <= {reg_data_in[0], reg_data_in[15:1]};
4'b0010: data_out <= {reg_data_in[1:0], reg_data_in[15:2]};
4'b0011: data_out <= {reg_data_in[2:0], reg_data_in[15:3]};
4'b0100: data_out <= {reg_data_in[3:0], reg_data_in[15:4]};
4'b0101: data_out <= {reg_data_in[4:0], reg_data_in[15:5]};
4'b0110: data_out <= {reg_data_in[5:0], reg_data_in[15:6]};
4'b0111: data_out <= {reg_data_in[6:0], reg_data_in[15:7]};
4'b1000: data_out <= {reg_data_in[7:0], reg_data_in[15:8]};
4'b1001: data_out <= {reg_data_in[8:0], reg_data_in[15:9]};
4'b1010: data_out <= {reg_data_in[9:0], reg_data_in[15:10]};
4'b1011: data_out <= {reg_data_in[10:0], reg_data_in[15:11]};
4'b1100: data_out <= {reg_data_in[11:0], reg_data_in[15:12]};
4'b1101: data_out <= {reg_data_in[12:0], reg_data_in[15:13]};
4'b1110: data_out <= {reg_data_in[13:0], reg_data_in[15:14]};
4'b1111: data_out <= {reg_data_in[14:0], reg_data_in[15]};
endcase
end // if (direction)
else
begin
case (reg_rotate)
4'b0000: data_out <= reg_data_in[15:0];
4'b0001: data_out <= {reg_data_in[14:0], reg_data_in[15]};
4'b0010: data_out <= {reg_data_in[13:0], reg_data_in[15:14]};
4'b0011: data_out <= {reg_data_in[12:0], reg_data_in[15:13]};
4'b0100: data_out <= {reg_data_in[11:0], reg_data_in[15:12]};
4'b0101: data_out <= {reg_data_in[10:0], reg_data_in[15:11]};
4'b0110: data_out <= {reg_data_in[9:0], reg_data_in[15:10]};
4'b0111: data_out <= {reg_data_in[8:0], reg_data_in[15:9]};
4'b1000: data_out <= {reg_data_in[7:0], reg_data_in[15:8]};
4'b1001: data_out <= {reg_data_in[6:0], reg_data_in[15:7]};
4'b1010: data_out <= {reg_data_in[5:0], reg_data_in[15:6]};
4'b1011: data_out <= {reg_data_in[4:0], reg_data_in[15:5]};
4'b1100: data_out <= {reg_data_in[3:0], reg_data_in[15:4]};
4'b1101: data_out <= {reg_data_in[2:0], reg_data_in[15:3]};
4'b1110: data_out <= {reg_data_in[1:0], reg_data_in[15:2]};
4'b1111: data_out <= {reg_data_in[0], reg_data_in[15:1]};
endcase
end // else: !if(direction)
end
endmodule
| 6.671366 |
module barrelShifter_tb;
// Inputs
reg [2:0] s;
reg [3:0] shift;
reg [15:0] i0, i1;
wire [15:0] o;
wire cout;
initial begin
$dumpfile("tb_barrel.vcd");
$dumpvars(0, barrelShifter_tb);
end
// Instantiate
alu bs (
.i0(i0),
.i1(i1),
.select(s),
.shift_mag(shift),
.o(o)
);
initial begin
i0 = 16'd64;
i1 = 16'd320;
s = 3'd0;
shift = 4'd2;
#5 i0 = 16'd80;
i1 = 16'd50;
s = 3'd1;
shift = 4'd2;
#5 i0 = 16'd50;
i1 = 16'd4;
s = 3'd2;
shift = 4'd2;
#5 i0 = 16'd500;
i1 = 16'd1000;
s = 3'd3;
shift = 4'd2;
#5 i0 = 16'd16;
i1 = 16'd4;
s = 3'd4;
shift = 4'd9;
#5 i0 = 16'd16;
i1 = 16'd4;
s = 3'd5;
shift = 4'd4;
#5 i0 = 16'd500;
i1 = 16'd1000;
s = 3'd6;
shift = 4'd10;
#5 i0 = 16'd10;
i1 = 16'd4;
s = 3'd7;
shift = 4'd4;
#5 i0 = 16'd16;
i1 = 16'd4;
s = 3'd4;
shift = 4'd2;
end
endmodule
| 6.666856 |
module BarrelShifter (
input [23:0] In,
output [23:0] Out,
input [ 4:0] Shift
);
wire [23:0] a;
genvar i;
generate
begin : b1
for (i = 0; i < 23; i = i + 1) begin : b2
Mux M (
In[i],
In[i+1],
Shift[0],
a[i]
);
end
Mux M1 (
In[23],
1'b0,
Shift[0],
a[23]
);
end
endgenerate
wire [23:0] a1;
genvar j, k;
generate
begin : b3
for (j = 0; j < 22; j = j + 1) begin : b4
Mux M2 (
a[j],
a[j+2],
Shift[1],
a1[j]
);
end
for (k = 22; k < 24; k = k + 1) begin : b5
Mux M3 (
a[k],
1'b0,
Shift[1],
a1[k]
);
end
end
endgenerate
genvar p, q;
wire [23:0] a2;
generate
begin : b6
for (p = 0; p < 20; p = p + 1) begin : b7
Mux M4 (
a1[p],
a1[p+4],
Shift[2],
a2[p]
);
end
for (k = 20; k < 24; k = k + 1) begin : b8
Mux M5 (
a1[k],
1'b0,
Shift[2],
a2[k]
);
end
end
endgenerate
genvar x, y;
wire [23:0] a3;
generate
begin
for (x = 0; x < 16; x = x + 1) begin : b9
Mux M6 (
a2[x],
a2[x+8],
Shift[3],
a3[x]
);
end
for (y = 16; y < 24; y = y + 1) begin : b10
Mux M7 (
a2[y],
1'b0,
Shift[3],
a3[y]
);
end
end
endgenerate
genvar s, t;
wire [23:0] a4;
generate
begin : b11
for (s = 0; s < 8; s = s + 1) begin : b12
Mux M8 (
a3[s],
a3[s+4],
Shift[4],
a4[s]
);
end
for (t = 8; t < 24; t = t + 1) begin : b13
Mux M9 (
a3[t],
1'b0,
Shift[4],
a4[t]
);
end
end
endgenerate
assign Out = a4;
endmodule
| 7.181217 |
module barrelshifter32 (
input [31:0] a,
input [4:0] b,
input [1:0] aluc,
output reg [31:0] c
);
integer temp;
always @(*) begin
temp = a;
case (aluc)
2'b00: c = temp / (2 ** b);
2'b01: c = temp << b;
2'b10: c = a >> b;
2'b11: c = a << b;
endcase
end
endmodule
| 6.846779 |
module barrelshifter32_tb ();
reg [31:0] a;
reg [ 4:0] b;
reg [ 1:0] aluc;
wire [31:0] c;
barrelshifter32 uut (
.a(a),
.b(b),
.aluc(aluc),
.c(c)
);
initial begin
a = 32'hffff_0000;
b = 5'b1010;
#80 b = 5'b10000;
#80 b = 5'b0100;
end
initial begin
aluc = 2'b00;
#20 aluc = 2'b01;
#20 aluc = 2'b10;
#20 aluc = 2'b11;
#20 aluc = 2'b00;
#20 aluc = 2'b01;
#20 aluc = 2'b10;
#20 aluc = 2'b11;
#20 aluc = 2'b00;
#20 aluc = 2'b01;
#20 aluc = 2'b10;
#20 aluc = 2'b11;
end
endmodule
| 6.846779 |
module BarrelShifterLeft (
a,
shift,
b
);
input [11:1] a;
input [5:1] shift;
output [11:1] b;
wire [11:1] o1, o2, o3, o4;
wire [11:1] w1, w21, w22, w31, w32, w33, w34, w41, w42, w43, w44, w45, w46, w47, w48;
// Bit 1
ShiftLeftOnce_11Bit s_1 (
a,
w1
);
assign o1 = (shift[1]) ? w1 : a;
// Bit 2
ShiftLeftOnce_11Bit s_21 (
o1,
w21
);
ShiftLeftOnce_11Bit s_22 (
w21,
w22
);
assign o2 = (shift[2]) ? w22 : o1;
// Bit 3
ShiftLeftOnce_11Bit s_31 (
o2,
w31
);
ShiftLeftOnce_11Bit s_32 (
w31,
w32
);
ShiftLeftOnce_11Bit s_33 (
w32,
w33
);
ShiftLeftOnce_11Bit s_34 (
w33,
w34
);
assign o3 = (shift[3]) ? w34 : o2;
// Bit 4
ShiftLeftOnce_11Bit s_41 (
o3,
w41
);
ShiftLeftOnce_11Bit s_42 (
w41,
w42
);
ShiftLeftOnce_11Bit s_43 (
w42,
w43
);
ShiftLeftOnce_11Bit s_44 (
w43,
w44
);
ShiftLeftOnce_11Bit s_45 (
w44,
w45
);
ShiftLeftOnce_11Bit s_46 (
w45,
w46
);
ShiftLeftOnce_11Bit s_47 (
w46,
w47
);
ShiftLeftOnce_11Bit s_48 (
w47,
w48
);
assign o4 = (shift[4]) ? w48 : o3;
// If Bit 5 is 1, as a is only 11 bits, output is 0 - all right shifted
assign b = (shift[5]) ? 11'b00000000000 : o4;
endmodule
| 7.181217 |
module BarrelShifterRight (
a,
shift,
b
);
input [11:1] a;
input [5:1] shift;
output [11:1] b;
wire [11:1] o1, o2, o3, o4;
wire [11:1] w1, w21, w22, w31, w32, w33, w34, w41, w42, w43, w44, w45, w46, w47, w48;
// Bit 1
ShiftRightOnce_11Bit s_1 (
a,
w1
);
assign o1 = (shift[1]) ? w1 : a;
// Bit 2
ShiftRightOnce_11Bit s_21 (
o1,
w21
);
ShiftRightOnce_11Bit s_22 (
w21,
w22
);
assign o2 = (shift[2]) ? w22 : o1;
// Bit 3
ShiftRightOnce_11Bit s_31 (
o2,
w31
);
ShiftRightOnce_11Bit s_32 (
w31,
w32
);
ShiftRightOnce_11Bit s_33 (
w32,
w33
);
ShiftRightOnce_11Bit s_34 (
w33,
w34
);
assign o3 = (shift[3]) ? w34 : o2;
// Bit 4
ShiftRightOnce_11Bit s_41 (
o3,
w41
);
ShiftRightOnce_11Bit s_42 (
w41,
w42
);
ShiftRightOnce_11Bit s_43 (
w42,
w43
);
ShiftRightOnce_11Bit s_44 (
w43,
w44
);
ShiftRightOnce_11Bit s_45 (
w44,
w45
);
ShiftRightOnce_11Bit s_46 (
w45,
w46
);
ShiftRightOnce_11Bit s_47 (
w46,
w47
);
ShiftRightOnce_11Bit s_48 (
w47,
w48
);
assign o4 = (shift[4]) ? w48 : o3;
// If Bit 5 is 1, as a is only 11 bits, output is 0 - all right shifted
assign b = (shift[5]) ? 11'b00000000000 : o4;
endmodule
| 7.181217 |
module barrelshifter8 (
input [7:0] d,
input [2:0] s, // ƶΪ
input [1:0] t, // 1X-- 00-- 01--
output [7:0] q
);
wire [7:0] rq, lq;
rshifter8 u1 (
d,
s,
t[0],
rq
); //
lshifter8 u2 (
d,
s,
lq
); //
assign q = (t[1] == 1) ? lq : rq;
endmodule
| 6.846779 |
module barrelshifter8_0 (
d,
s,
t,
q
);
input wire [7 : 0] d;
input wire [2 : 0] s;
input wire [1 : 0] t;
output wire [7 : 0] q;
barrelshifter8 inst (
.d(d),
.s(s),
.t(t),
.q(q)
);
endmodule
| 6.846779 |
module barrelshifter8_sim ();
// input
reg [7:0] d = 8'h00;
reg [2:0] s = 3'b000;
reg [1:0] t = 2'b00;
//output
wire [7:0] q;
barrelshifter8 ut (
d,
s,
t,
q
);
initial begin
#50 d = 8'h87;
#50 s = 3'b100;
#50 t = 2'b10;
#100 t = 2'b00;
#100 t = 2'b01;
end
;
endmodule
| 6.846779 |
module BarrelShifterA #(
parameter WIDTH = 32
) (
input wire LR,
input wire LA,
input wire [$clog2(WIDTH) - 1 : 0] W,
input wire [WIDTH - 1 : 0] A,
output wire [WIDTH - 1 : 0] Y
);
wire [WIDTH - 1 : 0] Ai;
wire [WIDTH - 1 : 0] Mn;
wire [WIDTH - 1 : 0] Mi;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin
assign Ai[i] = A[WIDTH-1-i];
end
endgenerate
RightBarrelShifter #(1, WIDTH) Unit (
LR & LA,
W,
LR ? A : Ai,
Mn
);
generate
for (i = 0; i < WIDTH; i = i + 1) begin
assign Mi[i] = Mn[WIDTH-1-i];
end
endgenerate
assign Y = LR ? Mn : Mi;
endmodule
| 7.181217 |
module BarrelShifterB #(
parameter WIDTH = 32
) (
input wire LR,
input wire LA,
input wire [$clog2(WIDTH) - 1 : 0] W,
input wire [WIDTH - 1 : 0] A,
output wire [WIDTH - 1 : 0] Y
);
wire [WIDTH - 1 : 0] Yl;
wire [WIDTH - 1 : 0] Yr;
LeftBarrelShifter #(0, WIDTH) UnitL (
W,
A,
Yl
);
RightBarrelShifter #(1, WIDTH) UnitR (
LA,
W,
A,
Yr
);
assign Y = LR ? Yr : Yl;
endmodule
| 7.181217 |
module BarrelShifterC #(
parameter WIDTH = 32
) (
input wire LR,
input wire LA,
input wire [$clog2(WIDTH) - 1 : 0] W,
input wire [WIDTH - 1 : 0] A,
output wire [WIDTH - 1 : 0] Y
);
wire [WIDTH - 1 : 0] M[$clog2(WIDTH) : 0];
genvar i;
genvar j;
generate
for (i = 0; i < $clog2(WIDTH); i = i + 1) begin
for (j = 0; j < WIDTH; j = j + 1) begin
reg [WIDTH - 1 : 0] S;
always @(*) begin
casex ({
W[i], LR, LA
})
3'b0xx: S <= M[i][j];
3'b10x: S <= (j - 2 ** i >= 0) ? M[i][j-2**i] : 1'b0;
3'b110: S <= (j + 2 ** i < WIDTH) ? M[i][j+2**i] : 1'b0;
3'b111: S <= (j + 2 ** i < WIDTH) ? M[i][j+2**i] : M[0][WIDTH-1];
endcase
end
assign M[i+1][j] = S;
end
end
endgenerate
assign M[0] = A;
assign Y = M[$clog2(WIDTH)];
endmodule
| 7.181217 |
module
//
//
// License: MIT
//
////////////////////////////////////////////////////////////////////////
`default_nettype None
`timescale 1ns/1ps
module barrelShifterNBit #(parameter n = 4) (output reg[n-1:0] out, input[n-1:0] in, input[$clog2(n):0] shift);
integer i;
always @ (in, shift) begin
for(i = 0; i < n; i = i+1) begin
if(i + shift < n)
out[i+shift] = in[i];
else
out[i+shift-n] = in[i];
end
end
endmodule
| 7.401748 |
module barrelshifter_1 (
input [23:0] Z,
input [7:0] ZE,
input [4:0] c,
input E,
AS,
BS,
output reg [23:0] ZN,
output reg [7:0] ZEN
);
parameter N = 3'b0;
always @(Z, AS, BS, ZE, c, E) begin
if ((AS == 0 && BS == 1) || (AS == 1 && BS == 0)) begin
if (E == 0) begin
ZN <= Z << c;
ZEN <= ZE - {N, c};
end else begin
ZN <= Z << c;
ZEN <= ZE - {N, c};
end
end else begin
if (E == 1) begin
ZN <= Z >> 1;
ZN[23] <= E;
ZEN <= ZE + 8'b1;
end else begin
ZN <= Z;
ZEN <= ZE;
end
end
end
endmodule
| 6.846779 |
module BarrelShifter (
aclr,
clken,
clock,
data,
distance,
result
);
input aclr;
input clken;
input clock;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
endmodule
| 7.181217 |
module BarrelShifter_comb (
data,
distance,
result
);
input [63:0] data;
input [5:0] distance;
output [63:0] result;
wire sub_wire0 = 1'h1;
wire [63:0] sub_wire1;
wire [63:0] result = sub_wire1[63:0];
lpm_clshift LPM_CLSHIFT_component (
.data(data),
.direction(sub_wire0),
.distance(distance),
.result(sub_wire1)
// synopsys translate_off
, .aclr(),
.clken(),
.clock(),
.overflow(),
.underflow()
// synopsys translate_on
);
defparam LPM_CLSHIFT_component.lpm_shifttype = "ROTATE", LPM_CLSHIFT_component.lpm_type =
"LPM_CLSHIFT", LPM_CLSHIFT_component.lpm_width = 64, LPM_CLSHIFT_component.lpm_widthdist = 6;
endmodule
| 7.181217 |
module BarrelShifter_comb (
data,
distance,
result
);
input [63:0] data;
input [5:0] distance;
output [63:0] result;
endmodule
| 7.181217 |
module around the barrel shifter to combine it with the clock and
reset.
*/
module barrelShifter_hier(In, Cnt, Op, Out);
// declare constant for size of inputs, outputs (N) and # bits to shift (C)
parameter N = 16;
parameter C = 4;
parameter O = 2;
input [N-1:0] In;
input [C-1:0] Cnt;
input [O-1:0] Op;
output [N-1:0] Out;
wire clk;
wire rst;
wire err;
assign err = 1'b0;
clkrst c0(
// Outputs
.clk (clk),
.rst (rst),
// Inputs
.err (err)
);
barrelShifter s0(
// Outputs
.Out (Out),
// Inputs
.In (In),
.Cnt (Cnt),
.Op (Op)
);
endmodule
| 7.926948 |
module barrelShifter_hier_bench;
// declare constant for size of inputs, outputs (N) and # bits to shift (C)
parameter N = 16;
parameter C = 4;
parameter O = 2;
reg [N-1:0] In;
reg [C-1:0] Cnt;
reg [O-1:0] Op;
wire [N-1:0] Out;
reg fail;
reg [ 31:0] Expected;
integer idx;
barrelShifter_hier DUT (
.In (In),
.Cnt(Cnt),
.Op (Op),
.Out(Out)
);
initial begin
In = 16'h0000;
Cnt = 4'b0000;
Op = 2'b00;
fail = 0;
#5000;
if (fail) $display("TEST FAILED");
else $display("TEST PASSED");
$finish;
end
always @(posedge DUT.clk) begin
In[15:0] = $random;
// In[15:0] = 16'hA0A0;
Cnt[3:0] = $random;
Op[1:0] = $random;
end
always @(negedge DUT.clk) begin
case (Op)
2'b00: // Rotate Left
begin
Expected = In << Cnt | In >> 16 - Cnt;
if (Expected[15:0] != Out) begin
$display(
"ERRORCHECK :: BarrelShifter :: Rotate Left : Count : %d, In = %x ; Expected : %x, Got %x",
Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b01: // Shift Left
begin
Expected = In << Cnt;
if (Expected[15:0] != Out) begin
$display(
"ERRORCHECK :: BarrelShifter :: Shift Left : Count : %d, In = %x ; Expected : %x, Got %x",
Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b10: // Shift Right Arithmetic
begin
for (idx = 31; idx > 15; idx = idx - 1) Expected[idx] = In[15];
Expected[15:0] = In[15:0];
Expected[15:0] = Expected >> Cnt;
if (Expected[15:0] != Out) begin
$display(
"ERRORCHECK :: BarrelShifter :: Shift Right Arith : Count : %d, In = %x ; Expected : %x, Got %x",
Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
2'b11: // Shift Right Logical
begin
Expected = In >> Cnt;
if (Expected[15:0] != Out) begin
$display(
"ERRORCHECK :: BarrelShifter :: Shift Right Logic : Count : %d, In = %x ; Expected : %x, Got %x",
Cnt, In, Expected[15:0], Out);
fail = 1;
end
end
endcase
end
endmodule
| 6.666856 |
module barreLshifter;
// Inputs
reg [15:0] num;
reg [3:0] amt;
reg LR;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
Multi_Barrel_Shifter8x16x32x #(
.N(16),
.M(4)
) uut (
.num(num),
.amt(amt),
.LR (LR),
.out(out)
);
initial begin
// Initialize Inputs
num = 0;
amt = 0;
LR = 0; //0=right, 1=left
#100 #10 num = 16'b11111111_00000000;
//Rotate right bit by bit
$display("ROTATE RIGHT");
for (amt = 4'd0; amt < 4'b1111; amt = amt + 1) begin
#5 $display("%b", out);
end
#5 $display("%b", out);
//Rotate left bit by bit
$display(" ");
$display("ROTATE LEFT");
LR = 1;
for (amt = 4'd0; amt < 4'b1111; amt = amt + 1) begin
#5 $display("%b", out);
end
#5 $display("%b", out);
#100 $finish;
end
endmodule
| 7.3786 |
module BarrelShifter_Testbench #(
parameter WIDTH = 32
) ();
reg LR = 1'b0;
reg LA = 1'b0;
reg [$clog2(WIDTH) - 1 : 0] W = {$clog2(WIDTH) {1'b0}};
reg [WIDTH - 1 : 0] A = {WIDTH{1'b0}};
wire [WIDTH - 1 : 0] Ya;
wire [WIDTH - 1 : 0] Yb;
wire [WIDTH - 1 : 0] Yc;
BarrelShifter #(0, WIDTH) aUnit (
LR,
LA,
W,
A,
Ya
);
BarrelShifter #(1, WIDTH) bUnit (
LR,
LA,
W,
A,
Yb
);
BarrelShifter #(2, WIDTH) cUnit (
LR,
LA,
W,
A,
Yc
);
always begin
W <= $random();
A <= $random();
#5{LR, LA} = 2'b00;
#5{LR, LA} = 2'b01;
#5{LR, LA} = 2'b10;
#5{LR, LA} = 2'b11;
end
endmodule
| 7.181217 |
module barrel_gate_test;
parameter pattern_num = 8;
wire [7:0] out;
wire carry;
reg [7:0] x, y;
reg clk;
reg stop;
integer i, num, error;
reg [7:0] ans_out;
reg [7:0] barrel_out;
reg [7:0] data_base1 [0:100];
reg [7:0] data_base2 [0:100];
barrel_shifter_gate B (
x,
y[2:0],
out
);
initial begin
$readmemh(`INFILE, data_base1);
$readmemh(`OUTFILE, data_base2);
clk = 1'b1;
error = 0;
stop = 0;
i = 0;
end
always begin
#(`CYCLE * 0.5) clk = ~clk;
end
initial begin
x[7:0] = data_base1[0];
y[7:0] = data_base1[1];
for (num = 2; num < (pattern_num * 2); num = num + 2) begin
@(posedge clk) begin
x[7:0] = data_base1[num];
y[7:0] = data_base1[num+1];
end
end
end
always @(posedge clk) begin
i <= i + 1;
if (i >= pattern_num) stop <= 1;
end
always @(posedge clk) begin
barrel_out <= out;
ans_out <= data_base2[i];
if (barrel_out !== ans_out) begin
error <= error + 1;
$display("An ERROR occurs at no.%d pattern: Output %b != answer %b.\n", i, barrel_out,
ans_out);
end
end
initial begin
@(posedge stop) begin
if (error == 0) begin
$display("==========================================\n");
$display("====== Congratulation! You Pass! =======\n");
$display("==========================================\n");
end else begin
$display("===============================\n");
$display("There are %d errors.", error);
$display("===============================\n");
end
$finish;
end
end
/*================Dumping Waveform files====================*/
initial begin
$dumpfile("barrel.vcd");
$dumpvars;
/* $fsdbDumpfile("barrel.fsdb");
$fsdbDumpvars; */
end
endmodule
| 7.556483 |
module Barrel_Rotator (
output [7:0] data_out,
input wire lr,
input wire [2:0] amount,
input [7:0] data_in
);
// internal signals
wire [7:0] left_out, right_out;
left_rotator left_rotator1 (
.d_out(left_out), //output
.d_in(data_in), //inputs
.bit_amount(amount)
);
right_rotator right_rotator1 (
.d_out(right_out), //output
.d_in(data_in), //inputs
.bit_amount(amount)
);
mux_2_to_1 mux_2_to_1_1 (
.y(data_out), //output
.left(left_out), //inputs
.right(right_out),
.lr(lr)
);
endmodule
| 6.781226 |
module Barrel_Rotator_testbench;
// Inputs
reg lr;
reg [2:0] amount;
reg [7:0] data_in;
// Outputs
wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT)
Barrel_Rotator uut (
.data_out(data_out),
.lr(lr),
.amount(amount),
.data_in(data_in)
);
initial begin
// Initialize Inputs and check for left rotate first
data_in = 8'b10010010;
lr = 1;
amount = 3'b000;
#5;
amount = 3'b001;
#5 amount = 3'b010;
#5 amount = 3'b011;
#5 amount = 3'b100;
#5;
amount = 3'b101;
#5 amount = 3'b110;
#5 amount = 3'b111;
#5 lr = 0; // Now check for right rotate
amount = 3'b000;
#5;
amount = 3'b001;
#5 amount = 3'b010;
#5 amount = 3'b011;
#5 amount = 3'b100;
#5;
amount = 3'b101;
#5 amount = 3'b110;
#5 amount = 3'b111;
end
always @(data_out)
#1
$display(
"Time = %d \t data_in = %b \t amount = %d \t lr = %b \t data_out = %b",
$time,
data_in,
amount,
lr,
data_out
);
endmodule
| 6.781226 |
module barrel_shift (
din,
dout,
distance
);
`include "log2.inc"
parameter RIGHT = 1;
parameter WIDTH = 16;
parameter DIST_WIDTH = log2(WIDTH - 1);
parameter GENERIC = 0;
localparam MAX_D = 1 << DIST_WIDTH; // The shifting range described by
// the distance.
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
input [DIST_WIDTH-1:0] distance;
wire [WIDTH-1:0] din_int, dout_int;
// input reversal for ROL
genvar i;
generate
if (RIGHT) assign din_int = din;
else begin
for (i = 0; i < WIDTH; i = i + 1) begin : revi
assign din_int[i] = din[WIDTH-1-i];
end
end
endgenerate
// rotate right sorting network
rotate_internal r (
.din(din_int),
.dout(dout_int),
.distance(distance)
);
defparam r.WIDTH = WIDTH; defparam r.DIST_WIDTH = DIST_WIDTH; defparam r.GENERIC = GENERIC;
// output reversal for ROL
generate
if (RIGHT) assign dout = dout_int;
else begin
for (i = 0; i < WIDTH; i = i + 1) begin : revo
assign dout[i] = dout_int[WIDTH-1-i];
end
end
endgenerate
endmodule
| 8.19148 |
module barrel_shifter (
s,
w,
y
);
input [1:0] s;
input [3:0] w;
output [3:0] y;
//4 4:1 mux used in barrel shifter
four_to_one_mux F1 (
w[3],
w[0],
w[1],
w[2],
s,
y[3]
);
four_to_one_mux F2 (
w[2],
w[3],
w[0],
w[1],
s,
y[2]
);
four_to_one_mux F3 (
w[1],
w[2],
w[3],
w[0],
s,
y[1]
);
four_to_one_mux F4 (
w[0],
w[1],
w[2],
w[3],
s,
y[0]
);
endmodule
| 8.606549 |
module barrel_shifter_1stage #(
parameter N = 16, // # of elements
parameter WIDTH = 8, // data width
parameter SHIFT_VALUE = 1, // shift offset
parameter K = 4, // K = log2(N)
parameter STAGE_NUM = 0 // range from 0 to K-1
) (
input clk,
input [N * WIDTH - 1:0] in,
input [K - 1:0] sel, // K-bit select signal
output [N * WIDTH - 1:0] out,
output [K - 1:0] sel_out
);
reg [N * WIDTH - 1:0] stage_reg; // stage register
reg [K - 1:0] sel_reg; // register the K-1 bits select signal
// Register select signal to next stage
always @(posedge clk) begin
sel_reg <= sel;
end
genvar count;
generate
begin
for (count = 0; count < N; count = count + 1) begin : for_loop
always @(posedge clk) begin
if (sel[STAGE_NUM]) // shift data by SHIFT_VALUE bit
stage_reg[((((count + SHIFT_VALUE) % N) + 1) * WIDTH - 1)-:WIDTH] <= in[((count + 1) * WIDTH - 1)-:WIDTH];
else // carry data to output as it is
stage_reg[((count+1)*WIDTH-1)-:WIDTH] <= in[((count+1)*WIDTH-1)-:WIDTH];
end
end
end
endgenerate
assign out = stage_reg;
assign sel_out = sel_reg;
endmodule
| 8.606549 |
module barrel_shifter_512bits (
clk,
reset,
data_in,
len_in,
enable,
last,
current_len,
data_full,
data_to_write,
data_out
);
input clk;
input reset;
input [255:0] data_in;
input [7:0] len_in;
input enable;
input last;
output [8:0] current_len;
output data_full;
output [255:0] data_to_write;
output [511:0] data_out;
reg [8:0] len_sum;
reg [511:0] data_tmp;
reg [8:0] current_len_reg;
reg [511:0] data_out_reg;
reg [255:0] data_to_write_reg;
reg data_full_reg;
always @(posedge clk) begin
if (reset) begin
current_len_reg <= 9'd0;
data_out_reg <= 512'd0;
data_full_reg <= 1'b0;
data_to_write_reg <= 256'd0;
end else begin
if (enable) begin
if (last) begin
len_sum <= current_len_reg + {1'b0, len_in} + 9'd7;
data_tmp <= (data_in << current_len_reg) | data_out_reg;
if(len_sum[8]) //means lower half is full
begin
data_out_reg <= {256'd0, data_tmp[511:256]};
current_len_reg <= {1'b0, len_sum[7:0]};
data_full_reg <= 1'b1;
data_to_write_reg <= data_tmp[255:0];
end else begin
data_out_reg <= data_tmp;
current_len_reg <= len_sum;
data_full_reg <= 1'b0;
data_to_write_reg <= 256'd0;
end
end else begin
len_sum <= current_len_reg + {1'b0, len_in};
data_tmp <= (data_in << current_len_reg) | data_out_reg;
if(len_sum[8]) //means lower half is full
begin
data_out_reg <= {256'd0, data_tmp[511:256]};
current_len_reg <= {1'b0, len_sum[7:0]};
data_full_reg <= 1'b1;
data_to_write_reg <= data_tmp[255:0];
end else begin
data_out_reg <= data_tmp;
current_len_reg <= len_sum;
data_full_reg <= 1'b0;
data_to_write_reg <= 256'd0;
end
end
end else begin
data_full_reg <= 1'b0;
current_len_reg <= current_len_reg;
data_out_reg <= data_out_reg;
data_to_write_reg <= 256'd0;
end
end
end
assign current_len = current_len_reg;
assign data_full = data_full_reg;
assign data_to_write = data_to_write_reg;
assign data_out = data_out_reg;
endmodule
| 8.606549 |
module barrel_shifter_64bits (
clk,
reset,
pre_data,
pre_len,
data_in,
len_in,
enable,
current_len,
data_full,
data_to_write,
data_out
);
// input & output ports
input clk;
input reset;
input [63:0] pre_data;
input [5:0] pre_len;
input [31:0] data_in;
input [4:0] len_in;
input enable;
output [5:0] current_len;
output data_full;
output [31:0] data_to_write;
output [63:0] data_out;
reg [5:0] len_sum;
reg [63:0] data_tmp;
reg [5:0] current_len_reg;
reg [63:0] data_out_reg;
reg [31:0] data_to_write_reg;
reg data_full_reg;
always @(posedge clk) begin
if (reset) begin
current_len_reg = 6'd0;
data_out_reg = 64'd0;
data_full_reg = 1'b0;
data_to_write_reg = 32'd0;
end else begin
if (enable) begin
len_sum = pre_len + len_in;
data_tmp = (data_in << pre_len) | pre_data;
if(len_sum[5]) //means lower half is full
begin
data_out_reg = {32'd0, data_tmp[63:32]};
current_len_reg = {1'b0, len_sum[4:0]};
data_full_reg = 1'b1;
data_to_write_reg = data_tmp[31:0];
end else begin
data_out_reg = data_tmp;
current_len_reg = len_sum;
data_full_reg = 1'b0;
data_to_write_reg = 32'd0;
end
end else begin
data_out_reg = 0;
current_len_reg = 0;
data_full_reg = 0;
data_to_write_reg = 0;
end
end
end
assign current_len = current_len_reg;
assign data_full = data_full_reg;
assign data_to_write = data_to_write_reg;
assign data_out = data_out_reg;
endmodule
| 8.606549 |
module barrel_shifter_8bit (
in,
ctrl,
out
);
input [7:0] in;
input [2:0] ctrl;
output [7:0] out;
wire [7:0] x, y;
//4bit shift right
mux2X1 ins_17 (
.in0(in[7]),
.in1(1'b0),
.sel(ctrl[2]),
.out(x[7])
);
mux2X1 ins_16 (
.in0(in[6]),
.in1(1'b0),
.sel(ctrl[2]),
.out(x[6])
);
mux2X1 ins_15 (
.in0(in[5]),
.in1(1'b0),
.sel(ctrl[2]),
.out(x[5])
);
mux2X1 ins_14 (
.in0(in[4]),
.in1(1'b0),
.sel(ctrl[2]),
.out(x[4])
);
mux2X1 ins_13 (
.in0(in[3]),
.in1(in[7]),
.sel(ctrl[2]),
.out(x[3])
);
mux2X1 ins_12 (
.in0(in[2]),
.in1(in[6]),
.sel(ctrl[2]),
.out(x[2])
);
mux2X1 ins_11 (
.in0(in[1]),
.in1(in[5]),
.sel(ctrl[2]),
.out(x[1])
);
mux2X1 ins_10 (
.in0(in[0]),
.in1(in[4]),
.sel(ctrl[2]),
.out(x[0])
);
//2 bit shift right
mux2X1 ins_27 (
.in0(x[7]),
.in1(1'b0),
.sel(ctrl[1]),
.out(y[7])
);
mux2X1 ins_26 (
.in0(x[6]),
.in1(1'b0),
.sel(ctrl[1]),
.out(y[6])
);
mux2X1 ins_25 (
.in0(x[5]),
.in1(x[7]),
.sel(ctrl[1]),
.out(y[5])
);
mux2X1 ins_24 (
.in0(x[4]),
.in1(x[6]),
.sel(ctrl[1]),
.out(y[4])
);
mux2X1 ins_23 (
.in0(x[3]),
.in1(x[5]),
.sel(ctrl[1]),
.out(y[3])
);
mux2X1 ins_22 (
.in0(x[2]),
.in1(x[4]),
.sel(ctrl[1]),
.out(y[2])
);
mux2X1 ins_21 (
.in0(x[1]),
.in1(x[3]),
.sel(ctrl[1]),
.out(y[1])
);
mux2X1 ins_20 (
.in0(x[0]),
.in1(x[2]),
.sel(ctrl[1]),
.out(y[0])
);
//1 bit shift right
mux2X1 ins_07 (
.in0(y[7]),
.in1(1'b0),
.sel(ctrl[0]),
.out(out[7])
);
mux2X1 ins_06 (
.in0(y[6]),
.in1(y[7]),
.sel(ctrl[0]),
.out(out[6])
);
mux2X1 ins_05 (
.in0(y[5]),
.in1(y[6]),
.sel(ctrl[0]),
.out(out[5])
);
mux2X1 ins_04 (
.in0(y[4]),
.in1(y[5]),
.sel(ctrl[0]),
.out(out[4])
);
mux2X1 ins_03 (
.in0(y[3]),
.in1(y[4]),
.sel(ctrl[0]),
.out(out[3])
);
mux2X1 ins_02 (
.in0(y[2]),
.in1(y[3]),
.sel(ctrl[0]),
.out(out[2])
);
mux2X1 ins_01 (
.in0(y[1]),
.in1(y[2]),
.sel(ctrl[0]),
.out(out[1])
);
mux2X1 ins_00 (
.in0(y[0]),
.in1(y[1]),
.sel(ctrl[0]),
.out(out[0])
);
endmodule
| 8.606549 |
module barrel_shifter_8bit_tb;
reg [7:0] in;
reg [2:0] ctrl;
wire [7:0] out;
barrel_shifter_8bit uut (
.in (in),
.ctrl(ctrl),
.out (out)
);
initial begin
$display($time, " << Starting the Simulation >>");
in = 8'd0;
ctrl = 3'd0; //no shift
#10 in = 8'd128;
ctrl = 3'd4; //shift 4 bit
#10 in = 8'd128;
ctrl = 3'd2; //shift 2 bit
#10 in = 8'd128;
ctrl = 3'd1; //shift by 1 bit
#10 in = 8'd255;
ctrl = 3'd7; //shift by 7bit
end
initial begin
$monitor("Input=%d, Control=%d, Output=%d", in, ctrl, out);
end
endmodule
| 8.606549 |
module barrel_shifter_case (
input wire [7:0] a,
input wire [2:0] amt,
output reg [7:0] y
);
// body
always @*
case (amt)
3'o0: y = a;
3'o1: y = {a[1:0], a[7:1]};
3'o2: y = {a[2:0], a[7:2]};
3'o3: y = {a[3:0], a[7:3]};
3'o4: y = {a[4:0], a[7:4]};
3'o5: y = {a[5:0], a[7:5]};
3'o6: y = {a[6:0], a[7:6]};
default: y = {a[6:0], a[7]};
endcase
endmodule
| 8.606549 |
module barrel_shifter_DE10_Lite (
KEY,
SW,
LEDR
);
input [1:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
barrel_shifter_right bsr_inst (
.i_data(SW[7:0]),
.i_sa ({~KEY[0], SW[9:8]}),
.i_st (KEY[1]),
.o_data(LEDR[7:0])
);
endmodule
| 8.606549 |
module barrel_shifter_gate (
in,
shift,
out
);
input [7:0] in;
input [2:0] shift;
output [7:0] out;
wire [7:0] l1, l2;
barrel_shift_gate_layer shift_l1 (
in,
{in[6:0], {1{1'b0}}},
shift[0],
l1
);
barrel_shift_gate_layer shift_l2 (
l1,
{l1[5:0], {2{1'b0}}},
shift[1],
l2
);
barrel_shift_gate_layer shift_l3 (
l2,
{l2[3:0], {4{1'b0}}},
shift[2],
out
);
endmodule
| 8.606549 |
module barrel_shift_gate_layer (
in0,
in1,
shift,
out
);
input [7:0] in0, in1;
input shift;
output [7:0] out;
mux mux0 (
out[0],
in0[0],
in1[0],
shift
);
mux mux1 (
out[1],
in0[1],
in1[1],
shift
);
mux mux2 (
out[2],
in0[2],
in1[2],
shift
);
mux mux3 (
out[3],
in0[3],
in1[3],
shift
);
mux mux4 (
out[4],
in0[4],
in1[4],
shift
);
mux mux5 (
out[5],
in0[5],
in1[5],
shift
);
mux mux6 (
out[6],
in0[6],
in1[6],
shift
);
mux mux7 (
out[7],
in0[7],
in1[7],
shift
);
endmodule
| 7.827555 |
module barrel_shifter_tb;
reg [2:0] bs_opsel_sig;
reg [4:0] shift_amount_sig;
reg [31:0] data_in_sig;
wire [31:0] result_sig;
integer i = 0;
barrel_shifter barrel_shifter_inst (
.bs_opsel(bs_opsel_sig), // input [2:0] bs_opsel_sig
.shift_amount(shift_amount_sig), // input [31:0] shift_amount_sig
.data_in(data_in_sig), // input [31:0] data_in_sig
.result(result_sig) // output [31:0] result_sig
);
initial begin
data_in_sig = 32'hbadc0de1;
bs_opsel_sig = 0;
shift_amount_sig = 4'h4;
while (1) begin
#10 bs_opsel_sig = 3'(i); //the statemant "n'(i)" was adviced by Vadim Charvchuk
i++;
end
end
initial begin
#400 $stop();
end
endmodule
| 8.606549 |
module barrel_shifter_left #(
parameter N = 16
) (
a,
shift,
o
);
localparam LOG_N = $clog2(N);
input [N-1:0] a;
input [LOG_N:0] shift;
output [N-1:0] o;
wire [N-1:0] ai[LOG_N+1:0];
assign ai[0] = a;
genvar i;
generate
for (i = 0; i < LOG_N + 1; i = i + 1) begin : loop1
assign ai[i+1] = (shift[i]) ? (ai[i] >> 2 ** i) : (ai[i]);
end
endgenerate
assign o = ai[LOG_N+1];
endmodule
| 8.606549 |
module barrel_shifter_left_test ();
localparam N = 16;
localparam LOG_N = $clog2(N);
reg [ N-1:0] a;
reg [LOG_N:0] shift;
wire [ N-1:0] o;
barrel_shifter_left #(
.N(N)
) _barrel_shifter_left_ (
.a(a),
.shift(shift),
.o(o)
);
initial begin
a = 16'hAAAA;
shift = 5'h00;
#10 shift = 5'h01;
#10 shift = 5'h02;
#10 shift = 5'h0F;
#10 shift = 5'h10;
#10 $stop;
end
endmodule
| 8.606549 |
module Barrel_Shifter_M #(
parameter SW = 26
) (
input wire clk,
input wire rst,
input wire load_i,
input wire Shift_Value_i,
input wire [SW-1:0] Shift_Data_i,
/////////////////////////////////////////////7
output wire [SW-1:0] N_mant_o
);
wire [SW-1:0] Data_Reg;
////////////////////////////////////////////////////7
shift_mux_array #(
.SWR (SW),
.LEVEL(0)
) shift_mux_array (
.Data_i(Shift_Data_i),
.select_i(Shift_Value_i),
.bit_shift_i(1'b1),
.Data_o(Data_Reg)
);
RegisterMult #(
.W(SW)
) Output_Reg (
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_Reg),
.Q(N_mant_o)
);
endmodule
| 7.114978 |
module barrel_shifter_rev #(
parameter N = 8,
parameter M = 3
) (
input wire [N-1:0] a,
input wire [M-1:0] amt,
input wire lr, // left is 1, right is 0
output wire [N-1:0] y
);
// internal signal declaration
wire [N-1:0] shifter_in, shifter_out;
// instantiate shifters depending on bit width
generate
if (N == 8)
barrel_shifter_stage_r shift_unit_left (
.a (shifter_in),
.amt(amt),
.y (shifter_out)
);
else if (N == 16)
barrel_shifter_stage_r_16b shift_unit_left (
.a (shifter_in),
.amt(amt),
.y (shifter_out)
);
else if (N == 32)
barrel_shifter_stage_r_32b shift_unit_left (
.a (shifter_in),
.amt(amt),
.y (shifter_out)
);
endgenerate
// instantiate reversers
reverser #(
.N(N)
) rev_pre (
.in (a),
.en (lr),
.out(shifter_in)
);
reverser #(
.N(N)
) rev_pos (
.in (shifter_out),
.en (lr),
.out(y)
);
endmodule
| 8.606549 |
module barrel (
input [2:0] amt,
input [1:0] lar,
input [7:0] a,
output reg [7:0] o
);
reg [7:0] rot_result, logic_result, arith_result;
always @(*)
fork
case (amt)
3'd0: rot_result <= a;
3'd1: rot_result <= {a[0], a[7:1]};
3'd2: rot_result <= {a[1:0], a[7:2]};
3'd3: rot_result <= {a[2:0], a[7:3]};
3'd4: rot_result <= {a[3:0], a[7:4]};
3'd5: rot_result <= {a[4:0], a[7:5]};
3'd6: rot_result <= {a[5:0], a[7:6]};
3'd7: rot_result <= {a[6:0], a[7]};
endcase
case (amt)
3'd0: logic_result <= a;
3'd1: logic_result <= {1'b0, a[7:1]};
3'd2: logic_result <= {2'b0, a[7:2]};
3'd3: logic_result <= {3'b0, a[7:3]};
3'd4: logic_result <= {4'b0, a[7:4]};
3'd5: logic_result <= {5'b0, a[7:5]};
3'd6: logic_result <= {6'b0, a[7:6]};
3'd7: logic_result <= {7'b0, a[7]};
endcase
case (amt)
3'd0: arith_result <= a;
3'd1: arith_result <= {a[7], a[7:1]};
3'd2: arith_result <= {{2{a[7]}}, a[7:2]};
3'd3: arith_result <= {{3{a[7]}}, a[7:3]};
3'd4: arith_result <= {{4{a[7]}}, a[7:4]};
3'd5: arith_result <= {{5{a[7]}}, a[7:5]};
3'd6: arith_result <= {{6{a[7]}}, a[7:6]};
3'd7: arith_result <= {{7{a[7]}}, a[7]};
endcase
case (lar)
2'b00: o <= logic_result;
2'b01: o <= arith_result;
2'b10: o <= rot_result;
2'b11: o <= rot_result;
endcase
join
endmodule
| 7.311845 |
module barrel_efficient (
input [2:0] amt,
input [1:0] lar,
input [7:0] a,
output reg [7:0] o
);
reg [7:0] shift_temp;
always @(*)
fork
case (lar)
2'b00: shift_temp <= 8'h00;
2'b01: shift_temp <= {8{a[7]}};
2'b10: shift_temp <= a;
2'b11: shift_temp <= a;
endcase
case (amt)
3'd0: o <= a;
3'd1: o <= {shift_temp[0], a[7:1]};
3'd2: o <= {shift_temp[1:0], a[7:2]};
3'd3: o <= {shift_temp[2:0], a[7:3]};
3'd4: o <= {shift_temp[3:0], a[7:4]};
3'd5: o <= {shift_temp[4:0], a[7:5]};
3'd6: o <= {shift_temp[5:0], a[7:6]};
3'd7: o <= {shift_temp[6:0], a[7]};
endcase
join
endmodule
| 6.501822 |
module testbench;
parameter DELAY = 20;
parameter N = 10_000;
reg i_st; // st - shift type (0:logical 1:arithmetic)
reg [7:0] i_data;
reg [2:0] i_sa; // sa -shift amount
wire [7:0] o_data;
barrel_shifter_right bsr_inst (
.i_data(i_data),
.i_sa (i_sa),
.i_st (i_st),
.o_data(o_data)
);
initial begin
repeat (N) begin
i_st = $random;
i_sa = $random;
i_data = $random;
#DELAY;
end
$finish;
end
endmodule
| 7.015571 |
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