code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module AND2_16 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.975484 |
module CSA_Cell_16 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_16 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_16 U1 (
.A (And_XY),
.B (S_in),
.CI(1'b0),
.CO(C_out),
.S (S_out)
);
endm... | 6.951962 |
module AND2_0 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.420626 |
module FA_7 (
A,
B,
CI,
CO,
S
);
input A, B, CI;
output CO, S;
wire A;
assign S = A;
endmodule
| 6.624434 |
module AND2_7 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.456289 |
module CSA_Cell_7 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_7 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_7 U1 (
.A (And_XY),
.B (1'b0),
.CI(1'b0),
.S (S_out)
);
endmodule
| 6.646269 |
module AND2_13 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.522602 |
module AND2_18 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.602137 |
module AND2_19 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.685614 |
module CSA_Cell_19 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_19 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_19 U1 (
.A (And_XY),
.B (1'b0),
.CI(1'b0),
.S (S_out)
);
endmodule
| 6.517123 |
module AND2_20 (
A1,
A2,
Z
);
input A1, A2;
output Z;
AND2_X1 U1 (
.A1(A2),
.A2(A1),
.Z (Z)
);
endmodule
| 7.950668 |
module CSA_Cell_20 (
X,
Y,
S_in,
C_in,
S_out,
C_out
);
input X, Y, S_in, C_in;
output S_out, C_out;
wire And_XY;
AND2_20 U0 (
.A1(X),
.A2(Y),
.Z (And_XY)
);
FA_20 U1 (
.A (And_XY),
.B (1'b0),
.CI(1'b0),
.S (S_out)
);
endmodule
| 6.543769 |
module ban_reg_micro (
input [5:0] Sel_reg,
input W,
input [7:0] DW,
output [7:0] Rx,
output [7:0] Ry,
input rst,
input clk
);
reg [7:0] Fnd[0:7];
always @(posedge clk, posedge rst) begin
if (rst) begin
Fnd[0] <= 0;
Fnd[1] <= 0;
Fnd[2] <= 0;
Fnd[3] <= 0;
... | 7.185678 |
module Registerfile (
clk,
we3,
wa3,
ra1,
ra2,
wd3,
rd1,
rd2,
S0,
S1,
S2,
S3,
S4,
S5,
S6,
S7
);
input [7:0] wd3;
input [2:0] wa3, ra1, ra2;
input we3, clk;
output reg [7:0] rd1, rd2;
output reg [7:0] S0, S1, S2, S3, S4, S5, S6, S7;
reg [7:0] ... | 6.695704 |
module Banco_registros (
input [4:0] dirL1,
dirL2,
dirW,
input wr,
input [31:0] datoIn,
output reg [31:0] dataOut1,
dataOut2
);
reg [31:0] BRegistros[31:0];
initial begin
BRegistros[0] = 32'd12;
BRegistros[1] = 32'd45;
BRegistros[2] = 32'd2;
BRegistros[3] = 32'd50;
... | 7.07719 |
module BancoInstrucao (
clock,
Endereco,
Instrucao
);
input wire clock;
input wire [7:0] Endereco;
output [7:0] Instrucao;
reg [7:0] Memoria[255:0];
reg [7:0] aux;
always @(negedge clock) begin
begin
aux = Memoria[Endereco];
end
end
assign Instrucao = aux;
endmodule
| 7.114402 |
module BancoPruebas; // Testbench
// Por lo general, las senales en el banco de pruebas son wires.
// No almacenan un valor, son manejadas por otras instancias de modulos.
// Dado que requieren coincidir con el tamaño de las entradas y salidas se debe asignar con su tamano
// definido en los modulos
// Si d... | 7.69717 |
module BancoPruebas_arbitro; // Testbench
wire almost_full0, almost_full1, almost_full2, almost_full3;
wire empty0_naranja,empty1_naranja,empty2_naranja,empty3_naranja, empty0_morado, empty1_morado ,empty2_morado,empty3_morado;
wire [7:0] empties, empties_estruct;
wire push;
wire pop0, pop1, pop2, pop3;
w... | 6.995131 |
module BancoPruebas_FIFO; // Testbench
wire empty_conduct, empty_estruct, almost_full_estruct, almost_full_conduct;
wire [9:0] data_out_conduct, data_out_estruct;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire almost_empty; // From conductual of FIFO.v, ...
... | 6.995131 |
module BancoPruebas_MUX; // Testbench
wire [9:0] Out0_conduct, Out1_conduct, Out2_conduct, Out3_conduct;
wire [9:0] Out0_estruct, Out1_estruct, Out2_estruct, Out3_estruct;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] P0; // From prob of Probador_MUX.v... | 6.995131 |
module BancoPrueba_contador();
parameter FIFO_UNITS = 4;
parameter INDEX = 2;
wire clk;
wire reset;
wire req;
wire [INDEX-1:0] idx;
wire IDLE;
wire pop_0;
wire pop_1;
wire pop_2;
wire pop_3;
wire [4:0] cuenta;
wire [4:0] cuenta_sint;
wire [4:0] contador_4;
wi... | 6.698287 |
module BancoReg (
input RegWrite,
input [4:0] RA1,
input [4:0] RA2,
input [31:0] WriteData,
input [4:0] AW,
output reg [31:0] DR1,
output reg [31:0] DR2
);
reg [31:0] Reg[0:31];
initial begin
$readmemb("BancoReg.mem", Reg);
end
always @* begin
if (RegWrite == 1) begin
... | 6.555106 |
module BancoRegis (
EscreveReg,
clock,
inRA,
in1,
in2,
regEscrito,
dadoEscrito,
outRA,
out1,
out2
);
input wire EscreveReg;
input wire [1:0] inRA;
input wire [1:0] in1;
input wire [1:0] in2;
input wire [1:0] regEscrito;
input wire [7:0] dadoEscrito;
input wire cloc... | 6.795783 |
module BancoRegistro #( // #( Parametros
parameter BIT_ADDR = 4, // BIT_ADDR Nmero de bit para la direccin
parameter BIT_DATO = 4, // BIT_DATO Nmero de bit para el dato
parameter RegFILE = "src/Reg16.men"
) (
input [BIT_ADDR-1:0] addrRa,
input [BIT_ADDR-1:0] addrRb,
output [BIT_DATO-1:... | 8.80606 |
module banco_de_registradores (
clk,
rl1,
rl2,
resc,
dado,
h_esc,
d1,
d2
);
input clk;
input [31:0] dado; // dado a ser escrito
input [4:0] rl1, rl2, resc; //endereco dos regs
input h_esc;
output [31:0] d1, d2;
reg [31:0] x[31:0]; // 32 reg's de 32 bits
// x[0:25] de p... | 6.889583 |
module Banco_Registro (
//Inputs
input [4:0] RA1,
input [4:0] RA2,
input [31:0] di,
input [4:0] dir,
input RW,
//Outputs
output reg [31:0] DR1,
output reg [31:0] DR2
);
reg [31:0] mem2[0:31];
initial begin
$readmemb("TestF1_BReg", mem2);
end
always @* begin
DR1 <= m... | 7.598552 |
module Banco_Registros (
input Rst,
input Clk,
input [5:0] SelR, // SelR[2:0]->Rx, SelR[5:3]->Ry
input RW, // 0->leer, 1->escribir
input [7:0] DW,
output [7:0] Rx,
output [7:0] Ry
);
reg [7:0] Rgs[0:7];
always @(posedge Clk, posedge Rst) begin
if (Rst) begin
Rgs[0] <= 0;
... | 7.598552 |
module BancReg (
input RegEn,
input [4:0] RR1,
input [4:0] RR2,
input [4:0] WriteRegister,
input [31:0] WriteData,
output reg [31:0] RD1,
output reg [31:0] RD2
);
reg [31:0] Banco[0:31];
initial begin
$readmemh("TestF1_BReg.mem", Banco);
end
always @* begin
RD1 <= Banco[RR... | 6.652886 |
module BANDAI2003 (
input CLK,
input CEn,
input WEn,
input OEn,
input SSn,
output SO, /* Synchronous out */
input RSTn,
input [7:0] ADDR, /* A-1 to A3 + A15 to A18 */
inout [7:0] DQ, /* Warning: Tri-state */
output ROMCEn,
output RAMCEn,
output [6:0] RADDR /* ROM/RAM ... | 7.617154 |
module BandFIR5503000 (
input wire clk, // clk.clk
input wire reset_n, // rst.reset_n
input wire [31:0] ast_sink_data, // avalon_streaming_sink.data
input wire ast_sink_valid, // .val... | 6.588166 |
module bandpass3 (
input clk, // timespec 9.4 ns
input signed [15:0] inp,
input zerome,
input oe,
output reg signed [17:0] out,
input signed [16:0] cm1,
input signed [16:0] d
);
// cm1 and d are host-settable registers
// cm1 (read "c minus 1") and d are signed 17-bit
// integers, re... | 7.705712 |
module bandpass3_tb;
reg clk;
integer cc;
// Integer values for cm1 and d are
// scaled by 2^17 from real value. See cset.m
reg signed [16:0] cm1, d;
initial begin
if (!$value$plusargs("cm1=%d", cm1)) cm1 = 7510;
if (!$value$plusargs("d=%d", d)) d = -23395;
for (cc = 0; cc < 500; cc = cc + 1) ... | 6.892856 |
module: bandpass
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bandpass_test;
// Inputs
reg clk;
reg rst;
reg [7:0] x;
// Outputs
wire [9:0] dataout;
// Instantiate the Unit Und... | 6.633353 |
module bank64k (
clk,
rd_en,
rd_addr,
rd_muxcode,
wr_en,
wr_addr,
wr_muxcode,
rdi_word,
wri_word,
rdd_word,
wrd_word,
rdc_word,
wrc_word
);
/* Parameters */
parameter w = 64;
parameter a = 10;
parameter C_DISABLE_WARN_BHV_COLL = 0;
/* Interface */
inpu... | 6.672932 |
module CACHE_ATTR_{{ name }}(CLK, A0, A1, D0, D1, WE0, WE1, Q0, Q1);
parameter W_A = 19;
parameter W_INDEX = 7;
parameter N_LINE = 128;
parameter W_ATTR = 7;
input CLK;
input [W_INDEX-1:0] A0;
input [W_INDEX-1:0] A1;
input [W_ATTR-1:0] D0;
input [W_ATTR-1:0] ... | 6.510423 |
module displaySelection (
dig0,
dig1,
dig2,
dig3,
bankClosed,
queueNum,
totalCus,
teller1call,
teller0call,
notRdyCls,
waitingCus,
blinkOff /*, pswrdCH*/
);
parameter a = 5'd10, b = 5'd11, c = 5'd12, d = 5'd13, h = 5'd19;
parameter e = 5'd14, f = 5'd15, o = 5'd16, L ... | 7.1205 |
module BankR (
//Entradas
input Rw,
input [4:0] Rd1,
input [4:0] Rd2,
input [4:0] Dir,
input [31:0] DIn,
//Salidas
output reg [31:0] L1,
output reg [31:0] L2
);
//2- Delcaracion de señales --> NA(No aplica)
//Registros
reg [31:0] BReg[0:31];
//3- Cuerpo del modulo (NA)
... | 6.614944 |
module bankRAM #(
parameter NO_BANKS = 2,
DATA_WIDTH = 4,
DEPTH = 4096,
MEM_FILE = ""
) (
input wire clk_rd,
input wire clk_wr,
input wire [NO_BANKS-1:0] wr_bank_select,
input wire [NO_BANKS-1:0] rd_bank_select,
input wire [NO_BANKS-1:0] wr_en,
input wire [ADDR_WIDTH-1:0] addr_wr... | 7.274169 |
module BANK_INIT #(
parameter length = 32,
parameter R = 5,
parameter DATA_LENGTH = 256
) (
// SYSTEM I/O
input i_clk,
input i_rst,
// FFT CONTROLLER
input i_BI_en,
// ROM
input [2*length-1:0] i_rom_data,
output reg [9:0] o_rom_addr,
// memory bank0
output reg [R-2:0]... | 6.780637 |
module bank_out_arb (
input wire [15:0] rw1_data,
input wire [15:0] rw2_data,
input wire [15:0] rw3_data,
input wire rw1_valid,
input wire rw2_valid,
input wire rw3_valid,
input wire [1:0] rw1_req_tag,
input wire [1:0] rw2_req_tag,
input wire [1:0] rw3_req_tag,
input wire [15:... | 7.382603 |
module bank_sel (
input wire [ 1:0] sel_in,
output reg [18:0] x_out
);
always @* begin
case (sel_in)
2'b00: begin
x_out = 19'd0;
end
2'b01: begin
x_out = 19'd174763;
end
2'b10: begin
x_out = 19'd349525;
end
2'b11: begin
x_out = ... | 6.697374 |
module bank_switch #(
parameter COUNT = 24,
parameter MSB = COUNT - 1,
parameter TICKS = 4,
parameter TSB = TICKS - 1,
parameter DELAY = 3
) (
input clk_x, // correlator clock
input rst_x,
input clk_i, // bus clock
input rst_i,
input ce_i,
input [MSB:0] bcount_i, // ... | 8.024708 |
module Bank_tb;
reg clk;
reg rst_n;
reg [8*`PIXEL-1:0] ref_in;
reg Bank_sel;
reg [6:0] address;
reg [6:0] write_address;
reg rd_en;
wire [8*`PIXEL-1:0] ref_ou;
Bank bank (
.clk(clk),
.rst_n(rst_n),
.ref_in(ref_in),
.Bank_sel(Bank_sel),
.address(address),
.write_add... | 6.620064 |
module banyan #(
parameter dw = 16, // data width
parameter np = 8, // number of ports, must be a power of 2
parameter rl = 3 // number of routing layers == log_2(np)
) (
input clk,
input [rl-1:0] time_state,
input [np-1:0] mask_in,
input [dw*np-1:0] data_in,
output [np-1:0] mask_o... | 8.434589 |
module two_set #(
parameter dw = 8
) (
input [dw-1:0] d,
output one, // or more bits of d are set
output two // or more bits of d are set
);
wire one_lower, one_upper;
wire two_lower, two_upper;
generate
if (dw > 1) begin : split
two_set #(
.dw(dw / 2)
) lower (
... | 7.676139 |
module banyan_mem_shell (
input clk, // timespec 6.1 ns
input [14:0] lb_addr,
input lb_write,
input [31:0] lb_data,
output [15:0] result,
output [15:0] status
);
// 8 blocks of RAM, each 4K x 16
parameter aw = 12;
parameter dw = 16;
// IOB latches on inputs
reg [14:0] addr = 0;
re... | 8.263614 |
module banyan_mem_tb;
parameter dw = 12;
parameter aw = 4;
reg clk;
integer cc;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("banyan_mem.vcd");
$dumpvars(7, banyan_mem_tb);
end
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 2000; cc = cc + 1) b... | 8.042747 |
module banyan_shell (
input clk, // timespec 6.1 ns
input [2:0] lb_addr,
input lb_write,
input [31:0] lb_data,
output [16:0] result
);
// IOB latches on inputs
reg [2:0] addr = 0;
reg write = 0;
reg [31:0] data = 0;
always @(posedge clk) begin
addr <= lb_addr;
write <= lb_write;... | 8.713394 |
module banyan_tb;
parameter dw = 7;
reg clk;
reg trace, squelch;
integer cc;
integer pass_count = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("banyan_tb.vcd");
$dumpvars(5, banyan_tb);
end
trace = $test$plusargs("trace");
squelch = $test$plusargs("squelch");
... | 7.009455 |
module designed to arbitrate different write port to BAR1.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module BAR1_WR_ARBITER (
rst_n,
init_rst_i,
//write port 0
wr_en0_i,
addr0_i,
wr_be0_i,
wr_d0_i,
... | 8.894011 |
module BarColor (
input Clock,
Reset,
Start,
GradationEn,
input [6:0] Bar,
input [14:0] InColor,
output [14:0] OutColor,
output reg Busy,
End
);
wire [4:0] wInR = InColor[14:10];
wire [4:0] wInG = InColor[9:5];
wire [4:0] wInB = InColor[4:0];
reg [4:0] R, G, B;
assign Out... | 7.054949 |
module BarDraw (
////////////////////////////////////////////////////
// Ports
input Clock,
Reset,
LRChange,
input [1:0] ActiveScreen,
// For FFTSequenser
input Start,
input DrawTop,
input [14:0] BarColor,
TopColor,
BGColor,
input [6:0] Bar, //描画するバーの高さ 0~96
in... | 7.386399 |
module BarGraph #(
parameter IN_WIDTH = 8, ///< Input data
parameter OUT_WIDTH = 8, ///< Number of elements in bar display
parameter LSB = 0 ///< LSB of data word to look at (usually 0)
) (
input wire clk, ///< System clock
input wire rst, ///< System... | 7.085929 |
module BarGraph_tb ();
parameter IN_WIDTH = 8; ///< Input data
parameter OUT_WIDTH = 8; ///< Number of elements in bar display
parameter LSB = 0; ///< LSB of data word to look at (usually 0)
reg clk; ///< System clock
reg rst; ///< System reset - active high & synchro... | 7.223951 |
module barramentoT #(
parameter DATA_WIDTH = 16
) (
input [DATA_WIDTH-1:0] top,
output [DATA_WIDTH-1:0] outputT
);
assign outputT = top;
endmodule
| 8.372061 |
module barrel (
input wire [ 1:0] shift_type,
input wire [ 3:0] shift,
input wire [15:0] data_in,
output reg [15:0] data_out
);
parameter lsl = 2'b00, lsr = 2'b01, asr = 2'b10, ror = 2'b11;
always @(*) begin
if (shift_type == lsl) data_out = data_in << shift;
else if (shift_type == lsr... | 7.311845 |
module barrel16 (
data_in,
data_out,
rotate,
direction,
clk
);
input [15:0] data_in;
input [3:0] rotate;
input clk, direction;
output [15:0] data_out;
reg [15:0] data_out ;
reg [15:0] reg_data_in ;
reg [3:0] reg_rotate ;
reg reg_direction;
always @(posedge clk) begin
... | 6.671366 |
module barrelShifter_tb;
// Inputs
reg [2:0] s;
reg [3:0] shift;
reg [15:0] i0, i1;
wire [15:0] o;
wire cout;
initial begin
$dumpfile("tb_barrel.vcd");
$dumpvars(0, barrelShifter_tb);
end
// Instantiate
alu bs (
.i0(i0),
.i1(i1),
.select(s),
.shift_mag(shift),
... | 6.666856 |
module BarrelShifter (
input [23:0] In,
output [23:0] Out,
input [ 4:0] Shift
);
wire [23:0] a;
genvar i;
generate
begin : b1
for (i = 0; i < 23; i = i + 1) begin : b2
Mux M (
In[i],
In[i+1],
Shift[0],
a[i]
);
end
... | 7.181217 |
module barrelshifter32 (
input [31:0] a,
input [4:0] b,
input [1:0] aluc,
output reg [31:0] c
);
integer temp;
always @(*) begin
temp = a;
case (aluc)
2'b00: c = temp / (2 ** b);
2'b01: c = temp << b;
2'b10: c = a >> b;
2'b11: c = a << b;
endcase
end
endmodule
| 6.846779 |
module barrelshifter32_tb ();
reg [31:0] a;
reg [ 4:0] b;
reg [ 1:0] aluc;
wire [31:0] c;
barrelshifter32 uut (
.a(a),
.b(b),
.aluc(aluc),
.c(c)
);
initial begin
a = 32'hffff_0000;
b = 5'b1010;
#80 b = 5'b10000;
#80 b = 5'b0100;
end
initial begin
aluc ... | 6.846779 |
module BarrelShifterLeft (
a,
shift,
b
);
input [11:1] a;
input [5:1] shift;
output [11:1] b;
wire [11:1] o1, o2, o3, o4;
wire [11:1] w1, w21, w22, w31, w32, w33, w34, w41, w42, w43, w44, w45, w46, w47, w48;
// Bit 1
ShiftLeftOnce_11Bit s_1 (
a,
w1
);
assign o1 = (shift[1]) ... | 7.181217 |
module BarrelShifterRight (
a,
shift,
b
);
input [11:1] a;
input [5:1] shift;
output [11:1] b;
wire [11:1] o1, o2, o3, o4;
wire [11:1] w1, w21, w22, w31, w32, w33, w34, w41, w42, w43, w44, w45, w46, w47, w48;
// Bit 1
ShiftRightOnce_11Bit s_1 (
a,
w1
);
assign o1 = (shift[1]... | 7.181217 |
module barrelshifter8 (
input [7:0] d,
input [2:0] s, // ƶΪ
input [1:0] t, // 1X-- 00-- 01--
output [7:0] q
);
wire [7:0] rq, lq;
rshifter8 u1 (
d,
s,
t[0],
rq
); //
lshifter8 u2 (
d,
s,
lq
); //
assign q = (t[1] == 1) ? lq : rq;
end... | 6.846779 |
module barrelshifter8_0 (
d,
s,
t,
q
);
input wire [7 : 0] d;
input wire [2 : 0] s;
input wire [1 : 0] t;
output wire [7 : 0] q;
barrelshifter8 inst (
.d(d),
.s(s),
.t(t),
.q(q)
);
endmodule
| 6.846779 |
module barrelshifter8_sim ();
// input
reg [7:0] d = 8'h00;
reg [2:0] s = 3'b000;
reg [1:0] t = 2'b00;
//output
wire [7:0] q;
barrelshifter8 ut (
d,
s,
t,
q
);
initial begin
#50 d = 8'h87;
#50 s = 3'b100;
#50 t = 2'b10;
#100 t = 2'b00;
#100 t = 2'b01;
... | 6.846779 |
module BarrelShifterA #(
parameter WIDTH = 32
) (
input wire LR,
input wire LA,
input wire [$clog2(WIDTH) - 1 : 0] W,
input wire [WIDTH - 1 : 0] A,
output wire [WIDTH - 1 : 0] Y
);
wire [WIDTH - 1 : 0] Ai;
wire [WIDTH - 1 :... | 7.181217 |
module BarrelShifterB #(
parameter WIDTH = 32
) (
input wire LR,
input wire LA,
input wire [$clog2(WIDTH) - 1 : 0] W,
input wire [WIDTH - 1 : 0] A,
output wire [WIDTH - 1 : 0] Y
);
wire [WIDTH - 1 : 0] Yl;
wire [WIDTH - 1 :... | 7.181217 |
module BarrelShifterC #(
parameter WIDTH = 32
) (
input wire LR,
input wire LA,
input wire [$clog2(WIDTH) - 1 : 0] W,
input wire [WIDTH - 1 : 0] A,
output wire [WIDTH - 1 : 0] Y
);
wire [WIDTH - 1 : 0] M[$clog2(WIDTH) : 0];
... | 7.181217 |
module
//
//
// License: MIT
//
////////////////////////////////////////////////////////////////////////
`default_nettype None
`timescale 1ns/1ps
module barrelShifterNBit #(parameter n = 4) (output reg[n-1:0] out, input[n-1:0] in, input[$clog2(n):0] shift);
integer i;
always @ (in, shift) begin
for(... | 7.401748 |
module barrelshifter_1 (
input [23:0] Z,
input [7:0] ZE,
input [4:0] c,
input E,
AS,
BS,
output reg [23:0] ZN,
output reg [7:0] ZEN
);
parameter N = 3'b0;
always @(Z, AS, BS, ZE, c, E) begin
if ((AS == 0 && BS == 1) || (AS == 1 && BS == 0)) begin
if (E == 0) begin
Z... | 6.846779 |
module BarrelShifter (
aclr,
clken,
clock,
data,
distance,
result
);
input aclr;
input clken;
input clock;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
endmodule
| 7.181217 |
module BarrelShifter_comb (
data,
distance,
result
);
input [63:0] data;
input [5:0] distance;
output [63:0] result;
wire sub_wire0 = 1'h1;
wire [63:0] sub_wire1;
wire [63:0] result = sub_wire1[63:0];
lpm_clshift LPM_CLSHIFT_component (
.data(data),
.direction(sub_wire0),
... | 7.181217 |
module BarrelShifter_comb (
data,
distance,
result
);
input [63:0] data;
input [5:0] distance;
output [63:0] result;
endmodule
| 7.181217 |
module around the barrel shifter to combine it with the clock and
reset.
*/
module barrelShifter_hier(In, Cnt, Op, Out);
// declare constant for size of inputs, outputs (N) and # bits to shift (C)
parameter N = 16;
parameter C = 4;
parameter O = 2;
input [N-1:0] In;
input [C-1:0] Cnt;
inp... | 7.926948 |
module barrelShifter_hier_bench;
// declare constant for size of inputs, outputs (N) and # bits to shift (C)
parameter N = 16;
parameter C = 4;
parameter O = 2;
reg [N-1:0] In;
reg [C-1:0] Cnt;
reg [O-1:0] Op;
wire [N-1:0] Out;
reg fail;
reg [ 31:0] Expected;
int... | 6.666856 |
module barreLshifter;
// Inputs
reg [15:0] num;
reg [3:0] amt;
reg LR;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
Multi_Barrel_Shifter8x16x32x #(
.N(16),
.M(4)
) uut (
.num(num),
.amt(amt),
.LR (LR),
.out(out)
);
initial begin
/... | 7.3786 |
module BarrelShifter_Testbench #(
parameter WIDTH = 32
) ();
reg LR = 1'b0;
reg LA = 1'b0;
reg [$clog2(WIDTH) - 1 : 0] W = {$clog2(WIDTH) {1'b0}};
reg [WIDTH - 1 : 0] A = {WIDTH{1'b0}};
wire [WIDTH - 1 : 0] Ya;
wire [WIDTH - 1 ... | 7.181217 |
module barrel_gate_test;
parameter pattern_num = 8;
wire [7:0] out;
wire carry;
reg [7:0] x, y;
reg clk;
reg stop;
integer i, num, error;
reg [7:0] ans_out;
reg [7:0] barrel_out;
reg [7:0] data_base1 [0:100];
reg [7:0] data_base2 [0:100];
barrel_shifter_gate B (
x,
y[2:0],
o... | 7.556483 |
module Barrel_Rotator (
output [7:0] data_out,
input wire lr,
input wire [2:0] amount,
input [7:0] data_in
);
// internal signals
wire [7:0] left_out, right_out;
left_rotator left_rotator1 (
.d_out(left_out), //output
.d_in(data_in), //inputs
.bit_amount(amount)
);
right... | 6.781226 |
module Barrel_Rotator_testbench;
// Inputs
reg lr;
reg [2:0] amount;
reg [7:0] data_in;
// Outputs
wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT)
Barrel_Rotator uut (
.data_out(data_out),
.lr(lr),
.amount(amount),
.data_in(data_in)
);
initial begin
// I... | 6.781226 |
module barrel_shift (
din,
dout,
distance
);
`include "log2.inc"
parameter RIGHT = 1;
parameter WIDTH = 16;
parameter DIST_WIDTH = log2(WIDTH - 1);
parameter GENERIC = 0;
localparam MAX_D = 1 << DIST_WIDTH; // The shifting range described by
// the distance.
input [WIDTH-1:0] din;
ou... | 8.19148 |
module barrel_shifter (
s,
w,
y
);
input [1:0] s;
input [3:0] w;
output [3:0] y;
//4 4:1 mux used in barrel shifter
four_to_one_mux F1 (
w[3],
w[0],
w[1],
w[2],
s,
y[3]
);
four_to_one_mux F2 (
w[2],
w[3],
w[0],
w[1],
s,
y[... | 8.606549 |
module barrel_shifter_1stage #(
parameter N = 16, // # of elements
parameter WIDTH = 8, // data width
parameter SHIFT_VALUE = 1, // shift offset
parameter K = 4, // K = log2(N)
parameter STAGE_NUM = 0 // range from 0 to K-1
) (
input clk,
input [N * WIDTH - 1:0] in,
input [K - 1:0]... | 8.606549 |
module barrel_shifter_512bits (
clk,
reset,
data_in,
len_in,
enable,
last,
current_len,
data_full,
data_to_write,
data_out
);
input clk;
input reset;
input [255:0] data_in;
input [7:0] len_in;
input enable;
input last;
output [8:0] current_len;
output data_full;... | 8.606549 |
module barrel_shifter_64bits (
clk,
reset,
pre_data,
pre_len,
data_in,
len_in,
enable,
current_len,
data_full,
data_to_write,
data_out
);
// input & output ports
input clk;
input reset;
input [63:0] pre_data;
input [5:0] pre_len;
input [31:0] data_in;
input [4:... | 8.606549 |
module barrel_shifter_8bit (
in,
ctrl,
out
);
input [7:0] in;
input [2:0] ctrl;
output [7:0] out;
wire [7:0] x, y;
//4bit shift right
mux2X1 ins_17 (
.in0(in[7]),
.in1(1'b0),
.sel(ctrl[2]),
.out(x[7])
);
mux2X1 ins_16 (
.in0(in[6]),
.in1(1'b0),
.sel... | 8.606549 |
module barrel_shifter_8bit_tb;
reg [7:0] in;
reg [2:0] ctrl;
wire [7:0] out;
barrel_shifter_8bit uut (
.in (in),
.ctrl(ctrl),
.out (out)
);
initial begin
$display($time, " << Starting the Simulation >>");
in = 8'd0;
ctrl = 3'd0; //no shift
#10 in = 8'd128;
ctrl ... | 8.606549 |
module barrel_shifter_case (
input wire [7:0] a,
input wire [2:0] amt,
output reg [7:0] y
);
// body
always @*
case (amt)
3'o0: y = a;
3'o1: y = {a[1:0], a[7:1]};
3'o2: y = {a[2:0], a[7:2]};
3'o3: y = {a[3:0], a[7:3]};
3'o4: y = {a[4:0], a[7:4]};
3'o5: y = {a[... | 8.606549 |
module barrel_shifter_DE10_Lite (
KEY,
SW,
LEDR
);
input [1:0] KEY;
input [9:0] SW;
output [9:0] LEDR;
barrel_shifter_right bsr_inst (
.i_data(SW[7:0]),
.i_sa ({~KEY[0], SW[9:8]}),
.i_st (KEY[1]),
.o_data(LEDR[7:0])
);
endmodule
| 8.606549 |
module barrel_shifter_gate (
in,
shift,
out
);
input [7:0] in;
input [2:0] shift;
output [7:0] out;
wire [7:0] l1, l2;
barrel_shift_gate_layer shift_l1 (
in,
{in[6:0], {1{1'b0}}},
shift[0],
l1
);
barrel_shift_gate_layer shift_l2 (
l1,
{l1[5:0], {2{1'b0}}},
... | 8.606549 |
module barrel_shift_gate_layer (
in0,
in1,
shift,
out
);
input [7:0] in0, in1;
input shift;
output [7:0] out;
mux mux0 (
out[0],
in0[0],
in1[0],
shift
);
mux mux1 (
out[1],
in0[1],
in1[1],
shift
);
mux mux2 (
out[2],
in0[2],
... | 7.827555 |
module barrel_shifter_tb;
reg [2:0] bs_opsel_sig;
reg [4:0] shift_amount_sig;
reg [31:0] data_in_sig;
wire [31:0] result_sig;
integer i = 0;
barrel_shifter barrel_shifter_inst (
.bs_opsel(bs_opsel_sig), // input [2:0] bs_opsel_sig
.shift_amount(shift_amount_sig), // input [31:0] shift_amoun... | 8.606549 |
module barrel_shifter_left #(
parameter N = 16
) (
a,
shift,
o
);
localparam LOG_N = $clog2(N);
input [N-1:0] a;
input [LOG_N:0] shift;
output [N-1:0] o;
wire [N-1:0] ai[LOG_N+1:0];
assign ai[0] = a;
genvar i;
generate
for (i = 0; i < LOG_N + 1; i = i + 1) begin : loop1
a... | 8.606549 |
module barrel_shifter_left_test ();
localparam N = 16;
localparam LOG_N = $clog2(N);
reg [ N-1:0] a;
reg [LOG_N:0] shift;
wire [ N-1:0] o;
barrel_shifter_left #(
.N(N)
) _barrel_shifter_left_ (
.a(a),
.shift(shift),
.o(o)
);
initial begin
a = 16'hAAAA;
shift = 5... | 8.606549 |
module Barrel_Shifter_M #(
parameter SW = 26
) (
input wire clk,
input wire rst,
input wire load_i,
input wire Shift_Value_i,
input wire [SW-1:0] Shift_Data_i,
/////////////////////////////////////////////7
output wire [SW-1:0] N_mant_o
);
wire [SW-1:0] Data_Reg;
//////////////////... | 7.114978 |
module barrel_shifter_rev #(
parameter N = 8,
parameter M = 3
) (
input wire [N-1:0] a,
input wire [M-1:0] amt,
input wire lr, // left is 1, right is 0
output wire [N-1:0] y
);
// internal signal declaration
wire [N-1:0] shifter_in, shifter_out;
// instantiate shifters depen... | 8.606549 |
module barrel (
input [2:0] amt,
input [1:0] lar,
input [7:0] a,
output reg [7:0] o
);
reg [7:0] rot_result, logic_result, arith_result;
always @(*)
fork
case (amt)
3'd0: rot_result <= a;
3'd1: rot_result <= {a[0], a[7:1]};
3'd2: rot_result <= {a[1:0], a[7:2]};
3'd3: ... | 7.311845 |
module barrel_efficient (
input [2:0] amt,
input [1:0] lar,
input [7:0] a,
output reg [7:0] o
);
reg [7:0] shift_temp;
always @(*)
fork
case (lar)
2'b00: shift_temp <= 8'h00;
2'b01: shift_temp <= {8{a[7]}};
2'b10: shift_temp <= a;
2'b11: shift_temp <= a;
endcase
... | 6.501822 |
module testbench;
parameter DELAY = 20;
parameter N = 10_000;
reg i_st; // st - shift type (0:logical 1:arithmetic)
reg [7:0] i_data;
reg [2:0] i_sa; // sa -shift amount
wire [7:0] o_data;
barrel_shifter_right bsr_inst (
.i_data(i_data),
.i_sa (i_sa),
.i_st (i_st),
... | 7.015571 |
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