code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dice (
ck,
rst,
enable,
nSEG,
CS
);
input ck, rst, enable;
output [7:0] nSEG;
output [2:0] CS;
reg [2:0] cnt;
assign CS = 3'b011;
always @(posedge ck or negedge rst) begin
if (rst == 1'b0) cnt <= 3'h1;
else if (enable == 1'b0)
if (cnt == 3'h6) cnt <= 3'h1;
else cnt <= cnt + 3'h1;
end
function [7:0] seg;
input [2:0] din;
case (din)
3'h1: seg = 8'b11111001;
3'h2: seg = 8'b10100100;
3'h3: seg = 8'b10110000;
3'h4: seg = 8'b10011001;
3'h5: seg = 8'b10010010;
3'h6: seg = 8'b10000010;
default: seg = 8'bxxxxxxxx;
endcase
endfunction
assign nSEG = seg(cnt);
endmodule
| 6.970586 |
module yj_basic_reg_clk_p #(
parameter DW = 32,
parameter RSTVAL = 1'b0
) (
input CLK,
input RSTn,
input [DW-1:0] din,
output [DW-1:0] qout
);
reg [DW-1:0] qout_Reg;
assign qout = qout_Reg;
always @(posedge CLK or negedge RSTn) begin
if (!RSTn) begin
qout_Reg <= {DW{RSTVAL}};
end else begin
qout_Reg <= #1 din;
end
end
endmodule
| 7.244693 |
module yj_basic_reg_clk_n #(
parameter DW = 32,
parameter RSTVAL = 1'b0
) (
input CLK,
input RSTn,
input [DW-1:0] din,
output [DW-1:0] qout
);
reg [DW-1:0] qout_Reg;
assign qout = qout_Reg;
always @(negedge CLK or negedge RSTn) begin
if (!RSTn) begin
qout_Reg <= {DW{RSTVAL}};
end else begin
qout_Reg <= #1 din;
end
end
endmodule
| 7.244693 |
module yj_basic_signal_2lever_sync #(
parameter DW = 32
) (
input CLK,
input RSTn,
input [DW-1:0] din,
output [DW-1:0] dout
);
wire [DW-1:0] sync_dat[1:0];
yj_basic_reg_clk_p #(
.DW(DW),
.RSTVAL(1'b0)
) sync_1lever (
CLK,
RSTn,
din,
sync_dat[0]
);
yj_basic_reg_clk_p #(
.DW(DW),
.RSTVAL(1'b0)
) sync_2lever (
CLK,
RSTn,
sync_dat[0],
sync_dat[1]
);
assign dout = sync_dat[1];
endmodule
| 9.826814 |
module basic_fifo #(
parameter DEPTH = 5,
parameter DATA_WIDTH = 32,
parameter INIT_ZERO = 0,
parameter ADDR_WIDTH = $clog2(DEPTH)
) (
input wire clk,
input wire rst,
input wire clear,
input wire din_valid,
input wire [DATA_WIDTH-1:0] din,
output wire din_ready,
output wire dout_valid,
output wire [DATA_WIDTH-1:0] dout,
input wire dout_ready,
output wire [ADDR_WIDTH:0] item_count,
output wire full,
output wire empty
);
reg [DATA_WIDTH-1:0] mem[0:(2**ADDR_WIDTH)-1];
reg [ADDR_WIDTH-1:0] rptr, wptr;
reg [ADDR_WIDTH:0] item_count_r;
wire enque = din_valid & din_ready;
wire deque = dout_valid & dout_ready;
always @(posedge clk)
if (rst || clear) begin
wptr <= {ADDR_WIDTH{1'b0}};
rptr <= {ADDR_WIDTH{1'b0}};
end else begin
if (enque) begin
mem[wptr] <= din;
wptr <= wptr + {{(ADDR_WIDTH - 1) {1'b0}}, 1'b1};
end
if (deque) begin
rptr <= rptr + {{(ADDR_WIDTH - 1) {1'b0}}, 1'b1};
end
end
assign dout = mem[rptr];
// Latching last transaction to know FIFO is full or empty
// Using not version of them to make din_ready and dout_valid registered
reg n_full, n_empty;
always @(posedge clk)
if (rst || clear) begin
// Eventhough din_ready is asserted during rst due to n_full, enque is 0
n_full <= 1'b0;
n_empty <= 1'b0;
end else if (!n_full && !n_empty) begin // Detecting cycle after rst or clear
n_full <= 1'b1;
end else if (enque ^ deque) begin
n_full <= !(((wptr +{{(ADDR_WIDTH - 1) {1'b0}}, 1'b1}) == rptr) && enque);
n_empty <= !(((rptr +{{(ADDR_WIDTH - 1) {1'b0}}, 1'b1}) == wptr) && deque);
end
always @(posedge clk)
if (rst || clear) item_count_r <= {(ADDR_WIDTH + 1) {1'b0}};
else if (enque && !deque) item_count_r <= item_count_r + {{(ADDR_WIDTH) {1'b0}}, 1'b1};
else if (!enque && deque) item_count_r <= item_count_r - {{(ADDR_WIDTH) {1'b0}}, 1'b1};
assign din_ready = n_full;
assign dout_valid = n_empty;
// Status outputs, so a not is fine
assign empty = !n_empty;
assign full = !n_full;
assign item_count = item_count_r;
integer i;
initial begin
if (INIT_ZERO) for (i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) mem[i] <= {DATA_WIDTH{1'b0}};
end
endmodule
| 6.822719 |
module basic_gate_structural (
a,
b,
c,
d,
e,
f,
g,
h,
i
);
input a, b;
output c, d, e, f, g, h, i;
not g0 (c, a);
and g1 (d, a, b);
or g2 (e, a, b);
nand g3 (f, a, b);
nor g4 (g, a, b);
xor g5 (h, a, b);
xnor g6 (i, a, b);
endmodule
| 7.002071 |
module basic_gate_dataflow (
a,
b,
c,
d,
e,
f,
g,
h,
i
);
input a, b;
output c, d, e, f, g, h, i;
assign c = ~a;
assign d = a & b;
assign e = a | b;
assign f = a ^ b;
assign g = ~(a & b);
assign h = ~(a | b);
assign i = ~(a ^ b);
endmodule
| 8.135332 |
module basic_gate_behavioural (
a,
b,
c,
d,
e,
f,
g,
h,
i
);
input a, b;
output reg c, d, e, f, g, h, i;
always @(a, b) begin
c = ~a;
d = a & b;
e = a | b;
f = a ^ b;
g = ~(a & b);
h = ~(a | b);
i = ~(a ^ b);
end
endmodule
| 6.607693 |
module basic_hashfunc #(
parameter input_sz = 48,
parameter table_sz = 1024,
parameter fsz = $clog2(table_sz)
) (
input [input_sz-1:0] hf_in,
output reg [fsz-1:0] hf_out
);
// const function not supported by Icarus Verilog
//localparam folds = num_folds(input_sz, fsz);
localparam folds = 5;
wire [folds*fsz-1:0] tmp_array;
assign tmp_array = hf_in;
integer f, b;
always @* begin
for (b = 0; b < fsz; b = b + 1) begin
hf_out[b] = 0;
for (f = 0; f < folds; f = f + 1) hf_out[b] = hf_out[b] ^ tmp_array[f*fsz+b];
end
end
function integer num_folds;
input [31:0] in_sz;
input [31:0] func_sz;
integer tmp_in_sz;
begin
num_folds = 0;
tmp_in_sz = in_sz;
while (tmp_in_sz > 0) begin
tmp_in_sz = tmp_in_sz - func_sz;
num_folds = num_folds + 1;
end
end
endfunction
/* -----\/----- EXCLUDED -----\/-----
function integer clogb2;
input [31:0] depth;
integer i;
begin
i = depth;
for (clogb2=0; i>0; clogb2=clogb2+1)
i = i >> 1;
end
endfunction // for
-----/\----- EXCLUDED -----/\----- */
endmodule
| 7.348295 |
module Basic_layer_search (
input clk,
input rst_n,
input [255:0] ref_input,
input [511:0] current_64pixels,
input ref_begin_prepare,
input pe_begin_prepare,
output [415:0] SAD4x8,
output [415:0] SAD8x4,
output [223:0] SAD8x8,
output [119:0] SAD8x16,
output [119:0] SAD16x8,
output [63:0] SAD16x16,
output [33:0] SAD16x32,
output [33:0] SAD32x16,
output [17:0] SAD32x32,
output [4:0] search_column_count,
output [6:0] search_row_count
);
wire [31:0] Bank_sel;
wire [7*32-1:0] rd_address_all;
wire [7*32-1:0] write_address_all;
wire rd8R_en;
wire [3:0] rdR_sel;
wire [4:0] shift_value;
wire [2047:0] ref_8R_32;
wire [2047:0] ref_8R_32_shifted;
wire in_curr_enable;
wire CB_select;
wire [1:0] abs_Control;
wire change_ref;
wire [8191:0] abs_outs;
wire ref_input_control;
Ref_mem_ctrl ref_mem_ctrl (
//input 待添加来自global的控制信号
.clk(clk),
.rst_n(rst_n),
.begin_prepare(ref_begin_prepare),
//output
.Bank_sel(Bank_sel),
.rd_address_all(rd_address_all),
.write_address_all(write_address_all),
.rd8R_en(rd8R_en),
.rdR_sel(rdR_sel),
.shift_value(shift_value)
);
Ref_mem ref_mem (
//input
.clk(clk),
.rst_n(rst_n),
.ref_input(ref_input),
.Bank_sel(Bank_sel),
.rd_address_all(rd_address_all),
.write_address_all(write_address_all),
.rd8R_en(rd8R_en),
.rdR_sel(rdR_sel),
//output
.ref_8R_32(ref_8R_32),
.Oda8R_va(),
.da1R_va()
);
Ref_mem_shift ref_mem_shift (
//input
.ref_input (ref_8R_32),
.shift_value(shift_value),
//output
.ref_output (ref_8R_32_shifted)
);
PE_array_ctrl pe_array_ctrl (
//input
.clk(clk),
.rst_n(rst_n),
.begin_prepare(pe_begin_prepare), // 待添加的来自global的开始信号
//output
.in_curr_enable(in_curr_enable),
.CB_select(CB_select),
.abs_Control(abs_Control),
.change_ref(change_ref),
.ref_input_control(ref_input_control),
.search_column_count(search_column_count),
.search_row_count(search_row_count)
);
PE_array pe_array (
//input
.clk(clk),
.rst_n(rst_n),
.current_64pixels(current_64pixels),
.in_curr_enable(in_curr_enable),
.CB_select(CB_select),
.abs_Control(abs_Control),
.ref_8R_32(ref_8R_32_shifted),
.change_ref(change_ref),
.ref_input_control(ref_input_control),
//output
.abs_outs(abs_outs)
);
SAD_Tree SAD_tree (
//input
.clk(clk),
.rst_n(rst_n),
.abs_outs(abs_outs),
//output
.SAD4x8(SAD4x8),
.SAD8x4(SAD8x4),
.SAD8x8(SAD8x8),
.SAD8x16(SAD8x16),
.SAD16x8(SAD16x8),
.SAD16x16(SAD16x16),
.SAD16x32(SAD16x32),
.SAD32x16(SAD32x16),
.SAD32x32(SAD32x32)
);
endmodule
| 7.964308 |
module basic_memory_block (
input clock,
input write_enable,
input [WIDTH-1:0] read_address,
input [WIDTH-1:0] write_address,
input [15:0] data_in,
output reg [15:0] data_out,
);
parameter WIDTH = 8;
parameter mem_depth = 1 << WIDTH;
reg [15:0] mem[mem_depth-1:0];
always @(posedge clock) begin
data_out <= mem[read_address];
if(write_enable)
mem[write_address[WIDTH-1:0]] <= data_in;
end
endmodule
| 7.458004 |
module register (
q,
d,
clk,
enable,
reset
);
parameter width = 32, reset_value = 0;
output reg [(width-1):0] q;
input [(width-1):0] d;
input clk, enable, reset;
always @(posedge clk or posedge reset)
if (reset == 1'b1) q <= reset_value;
else if (enable == 1'b1) q <= d;
endmodule
| 6.542519 |
module regfile (
rsData,
rtData,
rsNum,
rtNum,
rdNum,
rdData,
rdWriteEnable,
clock,
reset
);
output [31:0] rsData, rtData;
input [4:0] rsNum, rtNum, rdNum;
input [31:0] rdData;
input rdWriteEnable, clock, reset;
reg signed [31:0] r[0:31];
integer i;
assign rsData = r[rsNum];
assign rtData = r[rtNum];
always @(posedge clock or posedge reset) begin
if (reset == 1'b1) begin
for (i = 0; i <= 31; i = i + 1) r[i] <= 0;
end else if ((rdWriteEnable == 1'b1) && (rdNum != 5'b0)) r[rdNum] <= rdData;
end
endmodule
| 7.809308 |
module mux2v (
out,
A,
B,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] A, B;
input sel;
wire [width-1:0] temp1 = ({width{(!sel)}} & A);
wire [width-1:0] temp2 = ({width{(sel)}} & B);
assign out = temp1 | temp2;
endmodule
| 8.590864 |
module mux3v (
out,
A,
B,
C,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] A, B, C;
input [1:0] sel;
wire [width-1:0] wAB;
mux2v #(width) mAB (
wAB,
A,
B,
sel[0]
);
mux2v #(width) mfinal (
out,
wAB,
C,
sel[1]
);
endmodule
| 8.723833 |
module mux4v (
out,
A,
B,
C,
D,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] A, B, C, D;
input [1:0] sel;
wire [width-1:0] wAB, wCD;
mux2v #(width) mAB (
wAB,
A,
B,
sel[0]
);
mux2v #(width) mCD (
wCD,
C,
D,
sel[0]
);
mux2v #(width) mfinal (
out,
wAB,
wCD,
sel[1]
);
endmodule
| 8.321812 |
module mux16v (
out,
A,
B,
C,
D,
E,
F,
G,
H,
I,
J,
K,
L,
M,
N,
O,
P,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P;
input [3:0] sel;
wire [width-1:0] wAB, wCD, wEF, wGH, wIJ, wKL, wMN, wOP;
wire [width-1:0] wABCD, wEFGH, wIJKL, wMNOP;
wire [width-1:0] wABCDEFGH, wIJKLMNOP;
mux2v #(width) mAB (
wAB,
A,
B,
sel[0]
);
mux2v #(width) mCD (
wCD,
C,
D,
sel[0]
);
mux2v #(width) mEF (
wEF,
E,
F,
sel[0]
);
mux2v #(width) mGH (
wGH,
G,
H,
sel[0]
);
mux2v #(width) mIJ (
wIJ,
I,
J,
sel[0]
);
mux2v #(width) mKL (
wKL,
K,
L,
sel[0]
);
mux2v #(width) mMN (
wMN,
M,
N,
sel[0]
);
mux2v #(width) mOP (
wOP,
O,
P,
sel[0]
);
mux2v #(width) mABCD (
wABCD,
wAB,
wCD,
sel[1]
);
mux2v #(width) mEFGH (
wEFGH,
wEF,
wGH,
sel[1]
);
mux2v #(width) mIJKL (
wIJKL,
wIJ,
wKL,
sel[1]
);
mux2v #(width) mMNOP (
wMNOP,
wMN,
wOP,
sel[1]
);
mux2v #(width) mABCDEFGH (
wABCDEFGH,
wABCD,
wEFGH,
sel[2]
);
mux2v #(width) mIJKLMNOP (
wIJKLMNOP,
wIJKL,
wMNOP,
sel[2]
);
mux2v #(width) mfinal (
out,
wABCDEFGH,
wIJKLMNOP,
sel[3]
);
endmodule
| 7.305093 |
module mux32v (
out,
a,
b,
c,
d,
e,
f,
g,
h,
i,
j,
k,
l,
m,
n,
o,
p,
A,
B,
C,
D,
E,
F,
G,
H,
I,
J,
K,
L,
M,
N,
O,
P,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p;
input [width-1:0] A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P;
input [4:0] sel;
wire [width-1:0] wUPPER, wlower;
mux16v #(width) m0 (
wlower,
a,
b,
c,
d,
e,
f,
g,
h,
i,
j,
k,
l,
m,
n,
o,
p,
sel[3:0]
);
mux16v #(width) m1 (
wUPPER,
A,
B,
C,
D,
E,
F,
G,
H,
I,
J,
K,
L,
M,
N,
O,
P,
sel[3:0]
);
mux2v #(width) mfinal (
out,
wlower,
wUPPER,
sel[4]
);
endmodule
| 7.557627 |
module fulladder (
s,
cout,
a,
b,
cin
);
output s, cout;
input a, b, cin;
wire partial_s, partial_c1, partial_c2;
halfadder ha0 (
partial_s,
partial_c1,
a,
b
);
halfadder ha1 (
s,
partial_c2,
partial_s,
cin
);
or o1 (cout, partial_c1, partial_c2);
endmodule
| 7.454465 |
module basic_predictor_2b #(
parameter entry_num = 256,
parameter addr_width = $clog2(entry_num)
) (
input cpu_clk,
input cpu_rstn,
input wire [addr_width - 1 : 0] predictor_raddr,
input wire [addr_width - 1 : 0] predictor_waddr,
input wire predictor_wen,
input wire branch_taken_ex,
output wire predictor_rd_data
);
reg [1:0] predictor[entry_num - 1 : 0];
reg [1:0] predictor_rd_data_i;
assign predictor_rd_data = predictor_rd_data_i[1];
//test
wire [1:0] predictor_f5 = predictor[245];
integer i;
always @(posedge cpu_clk or negedge cpu_rstn) begin
if (!cpu_rstn) begin
for (i = 0; i < entry_num; i = i + 1) predictor[i] <= 2'b01;
end else begin
predictor_rd_data_i <= predictor[predictor_raddr];
if (predictor_wen) begin
case (predictor[predictor_waddr])
2'b00: begin
if (branch_taken_ex) predictor[predictor_waddr] <= 2'b01;
else predictor[predictor_waddr] <= 2'b00;
end
2'b01: begin
if (branch_taken_ex) predictor[predictor_waddr] <= 2'b10;
else predictor[predictor_waddr] <= 2'b00;
end
2'b10: begin
if (branch_taken_ex) predictor[predictor_waddr] <= 2'b11;
else predictor[predictor_waddr] <= 2'b01;
end
2'b11: begin
if (branch_taken_ex) predictor[predictor_waddr] <= 2'b11;
else predictor[predictor_waddr] <= 2'b10;
end
endcase
end
end
end
endmodule
| 6.946715 |
module basic_register #(
parameter DATA_WIDTH = 8
) (
input clk,
input rst,
input wr_en,
input [(DATA_WIDTH-1):0] data_in,
output [(DATA_WIDTH-1):0] data_out
);
reg [(DATA_WIDTH-1):0] data;
initial data <= 0;
always @(posedge clk or posedge rst) begin
if (rst) data <= 0;
else begin
if (wr_en) data <= data_in;
end
end
assign data_out = data;
endmodule
| 8.759639 |
module basic_regs #(
parameter [19:0] BASE_ADDRESS = 0,
parameter [19:0] SIZE_ADDRESS = 0
) (
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg s_ctrlport_resp_ack,
output reg [ 1:0] s_ctrlport_resp_status,
output reg [31:0] s_ctrlport_resp_data,
//reg clk domain
input wire ctrlport_clk,
input wire ctrlport_rst
);
`include "../regmap/basic_regs_regmap_utils.vh"
`include "../../../../../../lib/rfnoc/core/ctrlport.vh"
//----------------------------------------------------------
// Internal registers
//----------------------------------------------------------
reg [SCRATCH_REG_SIZE-1:0] scratch_reg = {SCRATCH_REG_SIZE{1'b0}};
//----------------------------------------------------------
// Handling of CtrlPort
//----------------------------------------------------------
wire address_in_range = (s_ctrlport_req_addr >= BASE_ADDRESS) && (s_ctrlport_req_addr < BASE_ADDRESS + SIZE_ADDRESS);
always @(posedge ctrlport_clk) begin
// reset internal registers and responses
if (ctrlport_rst) begin
scratch_reg <= {SCRATCH_REG_SIZE{1'b0}};
s_ctrlport_resp_ack <= 1'b0;
s_ctrlport_resp_data <= {32{1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
end else begin
// write requests
if (s_ctrlport_req_wr) begin
// always issue an ack and no data
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_data <= {32{1'bx}};
s_ctrlport_resp_status <= CTRL_STS_OKAY;
case (s_ctrlport_req_addr)
BASE_ADDRESS + SLAVE_SCRATCH: begin
scratch_reg <= s_ctrlport_req_data[SCRATCH_REG_MSB : SCRATCH_REG];
end
// error on undefined address
default: begin
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// no response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// read requests
end else if (s_ctrlport_req_rd) begin
// default assumption: valid request
s_ctrlport_resp_ack <= 1'b1;
s_ctrlport_resp_status <= CTRL_STS_OKAY;
s_ctrlport_resp_data <= {32{1'b0}};
case (s_ctrlport_req_addr)
BASE_ADDRESS + SLAVE_SIGNATURE: begin
s_ctrlport_resp_data[BOARD_ID_MSB : BOARD_ID] <= BOARD_ID_VALUE[BOARD_ID_SIZE-1:0];
end
BASE_ADDRESS + SLAVE_REVISION: begin
s_ctrlport_resp_data[REVISION_REG_MSB : REVISION_REG]
<= CPLD_REVISION[REVISION_REG_SIZE-1:0];
end
BASE_ADDRESS + SLAVE_OLDEST_REVISION: begin
s_ctrlport_resp_data[OLDEST_REVISION_REG_MSB : OLDEST_REVISION_REG]
<= OLDEST_CPLD_REVISION[OLDEST_REVISION_REG_SIZE-1:0];
end
BASE_ADDRESS + SLAVE_SCRATCH: begin
s_ctrlport_resp_data[SCRATCH_REG_MSB : SCRATCH_REG] <= scratch_reg;
end
BASE_ADDRESS + GIT_HASH_REGISTER: begin
`ifdef GIT_HASH
s_ctrlport_resp_data <= `GIT_HASH;
`else
s_ctrlport_resp_data <= 32'hDEADBEEF;
`endif
end
// error on undefined address
default: begin
s_ctrlport_resp_data <= {32{1'b0}};
if (address_in_range) begin
s_ctrlport_resp_status <= CTRL_STS_CMDERR;
// no response if out of range
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
endcase
// no request
end else begin
s_ctrlport_resp_ack <= 1'b0;
end
end
end
endmodule
| 7.15389 |
module Basic_RS_FlipFlop (
input notR,
input notS,
output Q,
output notQ
);
nand nand1 (Q, notS, notQ);
nand nand2 (notQ, notR, Q);
endmodule
| 7.250125 |
module basic_shift_register #(
parameter N = 256
) (
input clk,
enable,
input sr_in,
output sr_out
);
// Declare the shift register
reg [N-1:0] sr;
// Shift everything over, load the incoming bit
always @(posedge clk)
if (enable == 1'b1) begin
sr[N-1:1] <= sr[N-2:0];
sr[0] <= sr_in;
end
// Catch the outgoing bit
assign sr_out = sr[N-1];
endmodule
| 7.951889 |
module basic_switch (
left_in,
right_in,
left_out,
right_out,
select
);
parameter WIDTH = 64;
input [WIDTH-1:0] left_in, right_in;
output [WIDTH-1:0] left_out, right_out;
input select;
assign left_out = select ? right_in : left_in;
assign right_out = select ? left_in : right_in;
endmodule
| 8.849587 |
module basic_switch_ff (
clk,
left_in,
right_in,
left_out,
right_out,
select
);
parameter WIDTH = 64;
input clk;
input [WIDTH-1:0] left_in, right_in;
(* KEEP = "TRUE" *) output reg [WIDTH-1:0] left_out, right_out;
input select;
(* KEEP = "TRUE" *) reg [WIDTH-1:0] left_in_r, right_in_r;
reg select_r;
always @(posedge clk) begin
select_r <= select;
right_in_r <= right_in;
left_in_r <= left_in;
left_out <= select_r ? right_in_r : left_in_r;
right_out <= select_r ? left_in_r : right_in_r;
end
endmodule
| 8.091191 |
module register #(
parameter width = 1
) (
input clk,
reset,
stall,
flush,
input [width - 1:0] d,
output reg [width - 1:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (~stall & flush) q <= 0;
else if (~stall) q <= d;
end
endmodule
| 8.732583 |
module mux2 #(
parameter width = 1
) (
input [width - 1:0] d0,
d1,
input sel,
output [width - 1:0] y
);
assign y = sel ? d1 : d0;
endmodule
| 9.827805 |
module mux3 #(
parameter width = 1
) (
input [width - 1:0] d0,
d1,
d2,
input [1:0] sel,
output [width - 1:0] y
);
assign y = (sel == 2'd0) ? d0 : (sel == 2'd1) ? d1 : (sel == 2'd2) ? d2 : {width{1'bx}};
endmodule
| 7.777057 |
module mux4 #(
parameter width = 1
) (
input [width - 1:0] d0,
d1,
d2,
d3,
input [1:0] sel,
output [width - 1:0] y
);
assign y = (sel == 2'd0) ? d0 :
(sel == 2'd1) ? d1 :
(sel == 2'd2) ? d2 :
(sel == 2'd3) ? d3 : {width{1'bx}};
endmodule
| 7.807913 |
module mux5 #(
parameter width = 1
) (
input [width - 1:0] d0,
d1,
d2,
d3,
d4,
input [2:0] sel,
output [width - 1:0] y
);
assign y = (sel == 3'd0) ? d0 :
(sel == 3'd1) ? d1 :
(sel == 3'd2) ? d2 :
(sel == 3'd3) ? d3 :
(sel == 3'd4) ? d4 : {width{1'bx}};
endmodule
| 7.344479 |
module signext (
input [15:0] a,
output [31:0] y
);
assign y = {{16{a[15]}}, a};
endmodule
| 7.970829 |
module zeroext (
input [15:0] a,
output [31:0] y
);
assign y = {16'b0, a};
endmodule
| 8.133229 |
module ls16 (
input [15:0] a,
output [31:0] y
); // left shift by 16
assign y = {a, 16'b0};
endmodule
| 7.435057 |
module Basy3 (
input [1:0] display_mode,
input CLK,
Reset,
Button,
output [3:0] AN,
output [7:0] Out
);
wire [31:0] ALUresult, curPC, WriteData, ReadData1, ReadData2, instruction, nextPC;
wire myCLK, myReset;
reg [3:0] store;
CPU cpu (
myCLK,
myReset,
op,
funct,
ReadData1,
ReadData2,
curPC,
nextPC,
ALUresult,
instruction,
WriteData
);
remove_shake remove_shake_clk (
CLK,
Button,
myCLK
);
remove_shake remove_shake_reset (
CLK,
Reset,
myReset
);
clk_slow slowclk (
CLK,
myReset,
AN
);
display show_in_7segment (
store,
myReset,
Out
);
always @(myCLK) begin
case (AN)
4'b1110: begin
case (display_mode)
2'b00: store <= nextPC[3:0];
2'b01: store <= ReadData1[3:0];
2'b10: store <= ReadData2[3:0];
2'b11: store <= WriteData[3:0];
endcase
end
4'b1101: begin
case (display_mode)
2'b00: store <= nextPC[7:4];
2'b01: store <= ReadData1[7:4];
2'b10: store <= ReadData2[7:4];
2'b11: store <= WriteData[7:4];
endcase
end
4'b1011: begin
case (display_mode)
2'b00: store <= curPC[3:0];
2'b01: store <= instruction[24:21];
2'b10: store <= instruction[19:16];
2'b11: store <= ALUresult[3:0];
endcase
end
4'b0111: begin
case (display_mode)
2'b00: store <= curPC[7:4];
2'b01: store <= {3'b000, instruction[25]};
2'b10: store <= {3'b000, instruction[20]};
2'b11: store <= ALUresult[7:4];
endcase
end
endcase
end
endmodule
| 6.906693 |
module basys2 (
input mclk,
input [7:0] sw,
input [3:0] btn,
output [7:0] Led,
output [6:0] seg,
output dp,
output [3:0] an
);
wire [9:0] inputs;
wire [9:0] outputs;
assign inputs = { 2'b0, sw };
assign Led = outputs [7:0];
top
(
.clock(mclk), .reset_n(btn[3]), .buttons(btn[2:0]), .inputs(inputs), .outputs(outputs)
);
endmodule
| 7.262407 |
module Basys2_Keyboard (
input wire clk,
input wire PS2C,
input wire PS2D,
output reg [7:0] key_code
);
reg [8:0] cntdiv;
wire ck1;
reg [9:0] s_buf;
reg PS2C_old;
always @(posedge clk) begin
cntdiv <= cntdiv + 1;
end
assign ck1 = cntdiv[8];
always @(posedge ck1) begin
PS2C_old <= PS2C;
if ((PS2C_old == 1'b0) && (PS2C == 1'b1)) begin
if (s_buf[0] == 1'b0) begin
if (PS2D == 1'b1) begin
key_code <= s_buf[8:1];
s_buf <= 10'b1111111111;
end else begin
s_buf <= 10'b1111111111;
end
end else begin
s_buf <= {PS2D, s_buf[9:1]};
end
end
end
endmodule
| 6.68841 |
module basys3 (
input clk,
input btnC,
input btnU,
input btnL,
input btnR,
input btnD,
input [15:0] sw,
output [15:0] led,
output [6:0] seg,
output dp,
output [3:0] an,
inout [7:0] JA,
inout [7:0] JB,
input RsRx
);
wire clock;
wire reset = btnU;
`define MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
`ifdef MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX
wire muxed_clk;
wire [1:0] sw_db;
mfp_multi_switch_or_button_sync_and_debouncer #(
.WIDTH(2)
) mfp_multi_switch_or_button_sync_and_debouncer (
.clk (clk),
.sw_in (sw[1:0]),
.sw_out(sw_db)
);
mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz
mfp_clock_divider_100_MHz_to_25_MHz_12_Hz_0_75_Hz
(
.clki (clk),
.sel_lo (sw_db[0]),
.sel_mid(sw_db[1]),
.clko (muxed_clk)
);
BUFG BUFG_slow_clk (
.O(clock),
.I(muxed_clk)
);
`else
clk_wiz_0 clk_wiz_0 (
.clk_in1 (clk),
.clk_out1(clock)
);
`endif
wire [`MFP_N_SWITCHES - 1:0] IO_Switches;
wire [`MFP_N_BUTTONS - 1:0] IO_Buttons;
wire [`MFP_N_RED_LEDS - 1:0] IO_RedLEDs;
wire [`MFP_N_GREEN_LEDS - 1:0] IO_GreenLEDs;
wire [`MFP_7_SEGMENT_HEX_WIDTH - 1:0] IO_7_SegmentHEX;
assign IO_Switches = {{`MFP_N_SWITCHES - 16{1'b0}}, sw[15:0]};
assign IO_Buttons = {{`MFP_N_BUTTONS - 5{1'b0}}, btnU, btnD, btnL, btnC, btnR};
assign led = IO_GreenLEDs[15:0];
wire [31:0] HADDR, HRDATA, HWDATA;
wire HWRITE;
wire ejtag_tck_in, ejtag_tck;
IBUF IBUF (
.O(ejtag_tck_in),
.I(JB[3])
);
BUFG BUFG_ejtag_tck (
.O(ejtag_tck),
.I(ejtag_tck_in)
);
mfp_system mfp_system (
.SI_ClkIn(clock),
.SI_Reset(reset),
.HADDR (HADDR),
.HRDATA(HRDATA),
.HWDATA(HWDATA),
.HWRITE(HWRITE),
.EJ_TRST_N_probe(JB[4]),
.EJ_TDI (JB[1]),
.EJ_TDO (JB[2]),
.EJ_TMS (JB[0]),
.EJ_TCK (ejtag_tck_in),
.SI_ColdReset (~JB[5]),
.EJ_DINT (1'b0),
.IO_Switches (IO_Switches),
.IO_Buttons (IO_Buttons),
.IO_RedLEDs (IO_RedLEDs),
.IO_GreenLEDs (IO_GreenLEDs),
.IO_7_SegmentHEX(IO_7_SegmentHEX),
.UART_RX(RsRx /* Alternative: JA [7] */),
.UART_TX( /* TODO */),
.SPI_CS (JA[0]),
.SPI_SCK(JA[3]),
.SPI_SDO(JA[2])
);
assign JA[4] = 1'b0;
wire display_clock;
mfp_clock_divider_100_MHz_to_763_Hz mfp_clock_divider_100_MHz_to_763_Hz (
clk,
display_clock
);
wire [7:0] anodes;
assign an = anodes[3:0];
mfp_multi_digit_display multi_digit_display (
.clock (display_clock),
.resetn(~reset),
.number(IO_7_SegmentHEX),
.seven_segments(seg),
.dot (dp),
.anodes (anodes)
);
endmodule
| 6.699033 |
module Basys3_button_debouncer (
input i_Clk,
input [3:0] i_Buttons,
output [3:0] o_Buttons
);
// Target clock frequency
parameter c_CLK_FREQ = 106470000;
// Time that signal must be stable in microseconds
parameter c_FILTER_MICRO = 5000;
// Number of cycles to wait to consider signal stable
localparam c_FILTER_CYCLES = c_CLK_FREQ * c_FILTER_MICRO / 1000000;
// Counts clock cycles that button input is stable
integer ValidCount = 0;
// Register button input and compare to future inputs
reg [3:0] r_UnstableButtons = 0;
// Register to hold the most previous signal, feed to output
reg [3:0] r_Buttons = 0;
always @(posedge (i_Clk)) begin
if (i_Buttons == r_UnstableButtons) begin
// Signal remains stable
if (ValidCount < c_FILTER_CYCLES) begin
// Hasn't reached full stability
ValidCount <= ValidCount + 1;
end else begin
// Signal has held its value for long enough
ValidCount <= 0;
r_Buttons <= i_Buttons;
end
end else begin
// Signal changed value
ValidCount <= 0;
r_UnstableButtons <= i_Buttons;
end
end
assign o_Buttons = r_Buttons;
endmodule
| 7.40679 |
module Basys3_CPU (
input basys3_clock,
input reset_sw,
input [1:0] SW_in,
input next_button,
output [3:0] enable,
output [7:0] dispcode
);
wire [31:0] currentIAddr, nextIAddr;
wire [4:0] rs, rt;
wire [31:0] ReadData1, ReadData2;
wire [31:0] ALU_result, DataBus;
wire next_signal; // ֶź
wire [15:0] DisplayData;
top_CPU top_CPU (
.clk(next_signal), // ȡʹð°ťṩ͵ƽɿPCŵ
.Reset(reset_sw),
.currentIAddr(currentIAddr),
.nextIAddr(nextIAddr),
.rs(rs),
.rt(rt),
.ReadData1(ReadData1),
.ReadData2(ReadData2),
.ALU_result(ALU_result),
.DataBus(DataBus)
);
Four_LED Four_LED (
.clock(basys3_clock),
.reset(reset_sw),
.hex3(DisplayData[15:12]),
.hex2(DisplayData[11:8]),
.hex1(DisplayData[7:4]),
.hex0(DisplayData[3:0]),
.enable(enable),
.dispcode(dispcode)
);
Mux4_16bits Mux4_16bits (
.choice(SW_in),
.in0({currentIAddr[7:0], nextIAddr[7:0]}),
.in1({3'b000, rs, ReadData1[7:0]}),
.in2({3'b000, rt, ReadData2[7:0]}),
.in3({ALU_result[7:0], DataBus[7:0]}),
.out(DisplayData)
);
Button_Debounce Button_Debounce (
.clk(basys3_clock),
.btn_in(next_button),
.btn_out(next_signal)
);
endmodule
| 7.854305 |
module basys3_display_controller (
input disp_clk,
input [3:0] dig3,
input [3:0] dig2,
input [3:0] dig1,
input [3:0] dig0,
input reset,
output [6:0] segments,
output reg [3:0] anodes
);
reg [3:0] decoder_input;
hex2_7seg decoder (
.hex_in (decoder_input),
.seg_out(segments)
);
always @(posedge disp_clk)
if (reset == 0) begin
anodes <= 4'b0111; // Leftmost display goes first
decoder_input <= 0;
end else
case (anodes) // Rotate bits @ Anode frequency
4'b0111: begin
anodes <= 4'b1011;
decoder_input <= dig2;
end
4'b1011: begin
anodes <= 4'b1101;
decoder_input <= dig1;
end
4'b1101: begin
anodes <= 4'b1110;
decoder_input <= dig0;
end
4'b1110: begin
anodes <= 4'b0111;
decoder_input <= dig3;
end
endcase
endmodule
| 7.608402 |
module which will infer block RAMs
*/
module Basys3FujiIIe(
input clk_in_100MHz,
input button_reset
);
wire clk_100M;
wire clk_14M;
Basys3ClockGenerator clock_generator(
.clk_in_100MHz(clk_in_100MHz),
.clk_100M(clk_100M),
.clk_14M(clk_14M),
.reset(button_reset)
);
// Diagnostics ROM socket
wire diagnostics_rom_ce_n;
wire diagnostics_rom_oe_n;
wire [12:0] diagnostics_rom_a;
wire [7:0] diagnostics_rom_d;
// Monitor ROM socket
wire monitor_rom_ce_n;
wire monitor_rom_oe_n;
wire [12:0] monitor_rom_a;
wire [7:0] monitor_rom_d;
Rom #(
.RAM_WIDTH(8),
.RAM_DEPTH(8192),
.INIT_FILE("apple_iie_diagnostics_rom.mem")
) diagnostics_rom (
.clka(clk_14M),
.addra(diagnostics_rom_a),
.ena(~diagnostics_rom_ce_n),
.oe(~diagnostics_rom_oe_n),
.douta(diagnostics_rom_d)
);
Rom #(
.RAM_WIDTH(8),
.RAM_DEPTH(8192),
.INIT_FILE("apple_iie_monitor_rom.mem")
) monitor_rom (
.clka(clk_14M),
.addra(monitor_rom_a),
.ena(~monitor_rom_ce_n),
.oe(~monitor_rom_oe_n),
.douta(monitor_rom_d)
);
FujiIIe motherboard(
.clk_core(clk_100M),
.clk_14M(clk_14M),
.reset(button_reset),
.diagnostics_rom_ce_n(diagnostics_rom_ce_n),
.diagnostics_rom_oe_n(diagnostics_rom_oe_n),
.diagnostics_rom_a(diagnostics_rom_a),
.diagnostics_rom_d(diagnostics_rom_d),
.monitor_rom_ce_n(monitor_rom_ce_n),
.monitor_rom_oe_n(monitor_rom_oe_n),
.monitor_rom_a(monitor_rom_a),
.monitor_rom_d(monitor_rom_d)
);
endmodule
| 8.000425 |
module Basys3_IO_Test (
input clk,
input btnC,
input btnL,
input btnR,
input [11:0] sw,
output [15:0] led,
output [3:0] an,
output [0:6] seg,
output dp,
output RsTx,
input RsRx
);
//
//////////////////////////////////////////////////////////////////////////////////
//
wire clk_in1 = clk;
wire clk_out1;
clk_wiz_0 inst (
// Clock in ports
.clk_in1(clk_in1),
// Clock out ports clk_wiz_0
.clk_out1(clk_out1),
// Status and control signals
.reset(1'b0),
.locked()
);
//
//////////////////////////////////////////////////////////////////////////////////
//
wire reset_asyn_N = !btnC;
wire clock = clk_out1;
//
//////////////////////////////////////////////////////////////////////////////////
//
reg reset1, reset2;
always @(posedge clock or negedge reset_asyn_N)
if (!reset_asyn_N) begin
reset1 <= 1'b1;
end else begin
reset1 <= 1'b0;
end
always @(posedge clock or negedge reset_asyn_N)
if (!reset_asyn_N) begin
reset2 <= 1'b1;
end else begin
reset2 <= reset1;
end
//
//////////////////////////////////////////////////////////////////////////////////
//
wire new_data_wire;
wire [4:0] testing_wire;
wire [7:0] data_out_wire;
//
wire busy_wire;
wire read_n_load;
assign read_n_load = !busy_wire && new_data_wire;
//
UART_rx UART_rx_01 (
.rst(reset2),
.clk(clock),
.rxd_in(RsRx),
.read(read_n_load),
.testing(testing_wire),
.data_out(data_out_wire),
.new_data(new_data_wire)
);
//
//////////////////////////////////////////////////////////////////////////////////
//
UART_tx UART_tx_01 (
.rst(reset2),
.clk(clock),
.load(read_n_load),
.data_in(data_out_wire),
.txd_out(RsTx),
.busy(busy_wire)
);
//
//////////////////////////////////////////////////////////////////////////////////
//
// reg [7:0] data_ser;
//always @(posedge clock) data_ser <= {RsRx, data_ser[7:1]};
// assign led = {RsRx, !RsRx, data_ser || data_out_wire};
assign led = {RsRx, !RsRx, new_data_wire, testing_wire, data_out_wire};
//
assign {seg, dp} = sw[7:0];
assign an = sw[11:8];
endmodule
| 7.366858 |
module: PIC16F54
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module PIC16F54_tb01_v;
// Inputs
reg rst;
reg clk;
reg [3:0] porta_in;
reg [7:0] portb_in;
// reg [15:0] test_in;
reg wdtmr;
reg tmr0_inc;
// Outputs
wire [3:0] porta_out;
wire [7:0] portb_out;
wire [4:0] porta_tris;
wire [7:0] portb_tris;
wire [7:0] option_out;
// Instantiate the Unit Under Test (UUT)
PIC16F54 uut (
.rst(rst),
.clk(clk),
.porta_in(porta_in),
.portb_in(portb_in),
.porta_out(porta_out),
.portb_out(portb_out),
.porta_tris(porta_tris),
.portb_tris(portb_tris),
// .test_in(test_in),
.wdtmr(wdtmr),
.tmr0_inc(tmr0_inc),
.option_out(option_out)
);
parameter tp = 10; // clk cycle for 100 MHz
parameter dlt = 0.01*tp;
initial begin
// Initialize Inputs
rst = 1;
// rst = 0;
clk = 0;
porta_in = 0;
portb_in = 0;
// test_in = 0;
wdtmr = 0;
tmr0_inc = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#dlt;
rst = 0;
#(0.5*tp);
end
////////
always
#(tp/2) clk = ~clk; // generating clk
///
///
initial #(10000*tp) $stop;
endmodule
| 6.567866 |
module picosoc_mem (
ram_rdata,
CLKOUT_5_BUFG,
\mem_addr_reg[9] ,
mem_wdata,
WEA,
WEBWE
);
output [31:0] ram_rdata;
input CLKOUT_5_BUFG;
input [7:0] \mem_addr_reg[9] ;
input [31:0] mem_wdata;
input [1:0] WEA;
input [1:0] WEBWE;
wire \<const0> ;
wire \<const1> ;
wire CLKOUT_5_BUFG;
wire [1:0] WEA;
wire [1:0] WEBWE;
wire [7:0] \mem_addr_reg[9] ;
wire [31:0] mem_wdata;
wire [31:0] ram_rdata;
GND GND (.G(\<const0> ));
VCC VCC (.P(\<const1> ));
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *)
(* \MEM.PORTB.DATA_BIT_LAYOUT = "p0_d8_p0_d8" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *) (* RTL_RAM_BITS = "8192" *)
(* RTL_RAM_NAME = "mem" *) (* bram_addr_begin = "0" *) (* bram_addr_end = "255" *)
(* bram_slice_begin = "0" *) (* bram_slice_end = "31" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18)
) mem_reg (
.ADDRARDADDR({
\<const0> , \<const1> , \mem_addr_reg[9] , \<const1> , \<const1> , \<const1> , \<const1>
}),
.ADDRBWRADDR({
\<const1> , \<const1> , \mem_addr_reg[9] , \<const1> , \<const1> , \<const1> , \<const1>
}),
.CLKARDCLK(CLKOUT_5_BUFG),
.CLKBWRCLK(CLKOUT_5_BUFG),
.DIADI(mem_wdata[15:0]),
.DIBDI(mem_wdata[31:16]),
.DIPADIP({\<const1> , \<const1> }),
.DIPBDIP({\<const1> , \<const1> }),
.DOADO(ram_rdata[15:0]),
.DOBDO(ram_rdata[31:16]),
.ENARDEN(\<const1> ),
.ENBWREN(\<const1> ),
.REGCEAREGCE(\<const0> ),
.REGCEB(\<const0> ),
.RSTRAMARSTRAM(\<const0> ),
.RSTRAMB(\<const0> ),
.RSTREGARSTREG(\<const0> ),
.RSTREGB(\<const0> ),
.WEA(WEA),
.WEBWE({\<const0> , \<const0> , WEBWE})
);
endmodule
| 7.00993 |
module toplevel (
input io_mainClk,
output io_uart_txd,
input io_uart_rxd,
input [15:0] sw,
output [15:0] io_led
);
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
wire io_jtag_tck;
wire io_jtag_tdi;
wire io_jtag_tdo;
wire io_jtag_tms;
wire io_uart_txd;
wire io_uart_rxd;
assign io_led = io_gpioA_write[15:0];
assign io_gpioA_read[15:0] = sw;
Murax murax (
.io_asyncReset (0),
.io_mainClk (io_mainClk),
.io_jtag_tck (1'b0),
.io_jtag_tdi (1'b0),
.io_jtag_tms (1'b0),
.io_gpioA_read (io_gpioA_read),
.io_gpioA_write (io_gpioA_write),
.io_gpioA_writeEnable(io_gpioA_writeEnable),
.io_uart_txd (io_uart_txd),
.io_uart_rxd (io_uart_rxd)
);
endmodule
| 8.460384 |
module to support synthesis of
// an inspector project. The inputs and outputs
// are present only to ensure that none of the
// logic internal to the block is optimized away.
//
// There is little functionality to the block. The
// sel input comes from SW3:SW0 on the dev board
// and is used to select the counter that is
// output to the LD7:LD0 according to the table
// below.
//
// SW3:SW0 LD7:LD0
// 0 8'hFF
// 1 total_cnt[31:24]
// 2 total_cnt[23:16]
// 3 total_cnt[15:8]
// 4 total_cnt[7:0]
// 5 skype_cnt
// 6 skype_session
// 7 ssh_cnt
// 8 ssh_session
// 9 telnet_cnt
// a telnet_session
// b ftp_cnt
// c https_cnt
// d snmp_cnt
// e smtp_cnt
// f nntp_cnt
//
// For this demonstration, no counts will appear
// on the outputs since there is no data being
// sent. Again, it's just a wrapper.
//
// USE
//
// 1. Create a new project
// 2. Add Files ...
// 3. Add your inspector and this wrapper
// 4. Add Files ...
// 5. Add the provided wrapper XDC file
// 6. Generate Bitstream
// 7. Implementation Utilization Report
//
module basys3_wrapper(
input clk, rst, data,
input [3:0] sel,
output reg [7:0] counts
);
// necessary to use button for reset
wire rst_n;
// declaration of connections
wire [31:0] total_cnt;
wire [7:0] skype_cnt;
wire [7:0] ftp_cnt;
wire [7:0] https_cnt;
wire [7:0] ssh_cnt;
wire [7:0] telnet_cnt;
wire [7:0] snmp_cnt;
wire [7:0] smtp_cnt;
wire [7:0] nntp_cnt;
wire [7:0] skype_session;
wire [7:0] ssh_session;
wire [7:0] telnet_session;
assign rst_n = ~rst;
always @* begin
case( sel )
4'h1 : counts <= total_cnt[31:24];
4'h2 : counts <= total_cnt[23:16];
4'h3 : counts <= total_cnt[15:8];
4'h4 : counts <= total_cnt[7:0];
4'h5 : counts <= skype_cnt;
4'h6 : counts <= skype_session;
4'h7 : counts <= ssh_cnt;
4'h8 : counts <= ssh_session;
4'h9 : counts <= telnet_cnt;
4'hA : counts <= telnet_session;
4'hB : counts <= ftp_cnt;
4'hC : counts <= https_cnt;
4'hD : counts <= snmp_cnt;
4'hE : counts <= smtp_cnt;
4'hF : counts <= nntp_cnt;
default : counts <= 8'hff;
endcase
end
inspector wrap (
.rst_n( rst_n ),
.clk( clk ),
.data( data ),
.total_cnt( total_cnt ),
.skype_cnt( skype_cnt ),
.ftp_cnt( ftp_cnt ),
.https_cnt( https_cnt ),
.ssh_cnt( ssh_cnt ),
.telnet_cnt( telnet_cnt ),
.snmp_cnt( snmp_cnt ),
.smtp_cnt( smtp_cnt ),
.nntp_cnt( nntp_cnt ),
.skype_session( skype_session ),
.ssh_session( ssh_session ),
.telnet_session( telnet_session )
);
endmodule
| 6.963642 |
module basysConnections (
input clock,
input [15:0] SW,
//IP sensors
input JC4,
JC3,
JC2,
JC1, //[3:0] IPsensFront_in
input JC10,
JC9,
JC8,
JC7, //[3:0] IPsensBack_in
//IR sensors
input JB7,
JB8,
input JB1, //MIC
//H-Bridge
input JB3,
JB4, //CURRENT SENSING
output JA8,
JA7, //ENB,ENA
output JA4,
JA3,
JA2,
JA1, //IN4,IN3,IN2,IN1
// output [6:0] seg,
// output dp,
// output [3:0] an,
output [7:0] LED //debug for frequency detector led[4[ detects stop
);
//create flag variable here
// reg [3:0] detectSwitches;
wire [3:0] IPsensFront_out_wire;
wire [3:0] IPsensBack_out_wire;
wire [3:0] sendToH_BridgeINs_wire;
wire [5:0] motorSpeeds_wire;
wire [5:0] previousSpeedFromDecisionMaking_wire;
wire [5:0] previousSpeedToDecisionMakinFromH_Bridge_wire;
wire [3:0] movDirec_isTurning_leftRight_wire;
wire [3:0] previous_movDirec_isTurning_leftRight_toDecMak_wire;
wire IR_sensed_wire;
sensor_IP_v2 sensor_IP_v2 (
.clock(clock),
.IPsensFront_in({JC1, JC2, JC3, JC4}),
.IPsensBack_in({JC10, JC9, JC8, JC7}),
.IPsensFront_out(IPsensFront_out_wire),
.IPsensBack_out(IPsensBack_out_wire)
);
sensorIR sensorIR (
.clock(clock),
.IR_sensors({JB8, JB7}),
.IR_sensed(IR_sensed_wire)
);
decisionMaking_v2 decisionMaking_v2 (
.clock(clock),
.IPsensors({IPsensBack_out_wire, IPsensFront_out_wire}), // [3:0] are front; [7:4] are back
.IR_sensors(IR_sensed_wire),
.mic(JB1),
.previousH_Bridge_INs({JA4, JA3, JA2, JA1}),
.previousSpeeds(previousSpeedToDecisionMakinFromH_Bridge_wire),
.previous_movDirec_isTurning_leftRight_fromHBridge(previous_movDirec_isTurning_leftRight_toDecMak_wire),
.sendToH_Bridge_INs(sendToH_BridgeINs_wire),
.movDirec_isTurning_leftRight(movDirec_isTurning_leftRight_wire),
.previousSpeedToH_Bridge(previousSpeedFromDecisionMaking_wire),
.LED_debug({LED[7], LED[5:0]})
);
H_Bridge_v3 H_Bridge_v3 (
.clock(clock),
.currentSensing_in({JB4, JB3}),
.INs_from_decisionMakin(sendToH_BridgeINs_wire),
.forwardSpeed(SW[2:0]), //two motors with different PWMs
.turningSpeeds({SW[8:6], SW[5:3]}),
.movDirec_isTurning_leftRight(movDirec_isTurning_leftRight_wire),
.previousSpeedFromDecisionMaking(previousSpeedFromDecisionMaking_wire),
.previousSpeedToDecisionMakin(previousSpeedToDecisionMakinFromH_Bridge_wire),
.enA(JA7),
.enB(JA8),
.in1(JA1),
.in2(JA2),
.in3(JA3),
.in4(JA4),
.LED_currentSense_debug(LED[6]),
.previous_movDirec_isTurning_leftRight_toDecMak(previous_movDirec_isTurning_leftRight_toDecMak_wire)
);
endmodule
| 7.493918 |
module BasysConnections_testBench ();
reg clock;
//reg [15:0] SW;
reg [3:0] IPsensFront_in;
reg [3:0] IPsensBack_in;
wire [1:0] motorSpeed;
wire [3:0] movingDirection;
basysConnections UUT (
.clock(clock),
//.SW(SW),
.JA8 (motorSpeed[1]),
.JA7 (motorSpeed[0]),
.JA4 (movingDirection[3]),
.JA3 (movingDirection[2]),
.JA2 (movingDirection[1]),
.JA1 (movingDirection[0]), //MSB to LSB
.JC1(IPsensFront_in[0]),
.JC2(IPsensFront_in[1]),
.JC3(IPsensFront_in[2]),
.JC4(IPsensFront_in[3]),
// .JC7(IPsensBack_in[0]),
// .JC8(IPsensBack_in[1]), //MSB to LSB
// .JC9(IPsensBack_in[2]),
// .JC10(IPsensBack_in[3]) //MSB to LSB
);
// initial
// begin
// //SW <= 0;
// clock <= 0;
//// SW <= 16'b1000000000000000;
// #1000000
//// SW <= 16'b1000100111111111; //100%
// #1000000
//// SW <= 16'b1000101000010001; //25%
// #1000000
//// SW <= 16'b1000011000100001; //25% and 50%
// #1000000
//// SW <= 16'b1000011000100010; //50%
// #1000000
//// SW <= 16'b1000111100010001;
// #1000000
//// SW <= 16'b1000111100100010;
// end
initial begin
clock <= 0;
IPsensFront_in = ~4'b0000;
// IPsensBack_in = ~4'b0000;
#1000000 IPsensFront_in <= ~4'b0001;
// IPsensBack_in <= ~4'b0000;
#1000000 IPsensFront_in <= ~4'b0010;
// IPsensBack_in <= ~4'b0001;
#1000000 IPsensFront_in <= ~4'b0100;
// IPsensBack_in <= ~4'b0010;
#1000000 IPsensFront_in <= ~4'b0110;
// IPsensBack_in <= ~4'b0010;
#1000000 IPsensFront_in <= ~4'b0111;
// IPsensBack_in <= ~4'b0000;
#1000000 IPsensFront_in <= ~4'b1000;
end
always begin
#1 clock = ~clock;
end
endmodule
| 8.063202 |
module basysTest (
input CLK,
input [3:0] BTN,
output [6:0] SEG,
output [3:0] AN,
output DP
);
wire RST_X = ~BTN[0];
assign AN = BTN;
assign DP = 0;
reg [ 7:0] tcount;
reg [31:0] count;
parameter MAX = 50 * 1024 * 1024;
always @(posedge CLK or negedge RST_X) begin
if (!RST_X) tcount <= 8'b0;
else if (tcount == 8'b0000_0100 && count == MAX) tcount <= 0;
else if (count == MAX) tcount <= tcount + 8'b1;
end
always @(posedge CLK or negedge RST_X) begin
if (!RST_X) count <= 31'b0;
else if (count > MAX) count <= 31'b0;
else count <= count + 31'b1;
end
reg [6:0] r_seg;
always @* begin
case (tcount)
8'b0000_0001: r_seg <= 7'b111_1001;
8'b0000_0010: r_seg <= 7'b010_0100;
8'b0000_0011: r_seg <= 7'b011_0000;
8'b0000_0100: r_seg <= 7'b011_0000;
default: r_seg <= 7'b100_0000;
endcase
end
assign SEG = r_seg;
endmodule
| 7.139842 |
module bas_top (
CLOCK,
RST,
KEY1,
KEY2,
KEY3,
KEY4,
KEY5,
KEY6,
KEY7,
KEY8,
OUT_DATA,
C_PIN
);
input CLOCK, RST;
input KEY1, KEY2, KEY3, KEY4, KEY5, KEY6, KEY7, KEY8;
output [7:0] OUT_DATA;
//reg [7:0]OUT_DATA;
output [5:0] C_PIN;
//reg [2:0]C_PIN;
wire one_time;
wire [7:0] time24_a, time24_b;
wire [7:0] time12_a, time12_b, time12_c, time12_d;
wire [7:0] mark_ab, mark_as, mark_ag, mark_bb, mark_bs, mark_bg;
frequency_divider uut (
.clk(CLOCK),
.rst(RST),
.out(one_time)
);
attack_time uut2 (
.clock(one_time),
.key2(KEY2),
.q(time24_a), //24sʱʮλ
.b(time24_b) //24sʱλ
);
subsec_time uut3 (
.clock(one_time),
.rst (RST),
.a(time12_a), //12mʱʮ 1
.s(time12_b), //12mʱλ 2
.d(time12_c), //12mʱʮ 0
.f(time12_d) //12mʱλ 0
);
mark uut4 (
.rst (RST),
.key3(KEY3),
.key4(KEY4),
.key5(KEY5),
.key6(KEY6),
.key7(KEY7),
.key8(KEY8),
.a1 (mark_ag),
.a2 (mark_as),
.a3 (mark_ab),
.b1 (mark_bg),
.b2 (mark_bs),
.b3 (mark_bb)
);
digital_screen uut5 (
.clock(CLOCK),
.key1(KEY1),
.time1(time24_a),
.time2(time24_b),
.time3(time12_a),
.time4(time12_b),
.time5(time12_c),
.time6(time12_d),
.mark_a1(mark_ag),
.mark_a2(mark_as),
.mark_a3(mark_ab),
.mark_b1(mark_bg),
.mark_b2(mark_bs),
.mark_b3(mark_bb),
.out_data(OUT_DATA),
.c_pin(C_PIN)
);
endmodule
| 7.001999 |
module bat (
input rst,
input clk2,
input clk_20m,
input [1:0] carga,
output reg wr,
output reg dr,
output reg [7:0] direc,
output reg [7:0] dbi
);
reg [3:0] estado = 0;
reg [3:0] nestado = 0;
initial wr = 0;
initial dr = 0;
parameter stay = 0;
parameter dr1 = 1;
parameter line = 2;
parameter dr2 = 3;
parameter dr3 = 4;
parameter dr4 = 5;
parameter line2 = 6;
parameter line3 = 7;
parameter line4 = 8;
always @(negedge clk_20m) begin
if (carga == 0) begin
case (estado)
stay: nestado = dr1;
dr1: nestado = line;
line: nestado = stay;
endcase
end
if (carga == 1) begin
case (estado)
stay: nestado = dr1;
dr1: nestado = line;
line: nestado = dr2;
dr2: nestado = line2;
line2: nestado = stay;
endcase
end
if (carga == 2) begin
case (estado)
stay: nestado = dr1;
dr1: nestado = line;
line: nestado = dr2;
dr2: nestado = line2;
line2: nestado = dr3;
dr3: nestado = line3;
line3: nestado = stay;
endcase
end
if (carga == 3) begin
case (estado)
stay: nestado = dr1;
dr1: nestado = line;
line: nestado = dr2;
dr2: nestado = line2;
line2: nestado = dr3;
dr3: nestado = line3;
line3: nestado = dr4;
dr4: nestado = line4;
line4: nestado = stay;
endcase
end
end
always@( posedge clk2 ) //Reset opcional, Actualizacion de estados
begin
if (rst) estado = stay;
else estado = nestado;
end
always@( estado ) //Memoria de estados
begin
case (estado)
stay: begin
wr = 0;
dr = 0;
end
dr1: begin
direc = 8'b10010000;
wr = 0;
dr = 1;
end
dr2: begin
direc = 8'b10010001;
wr = 0;
dr = 1;
end
dr3: begin
direc = 8'b10010010;
wr = 0;
dr = 1;
end
dr4: begin
direc = 8'b10010011;
wr = 0;
dr = 1;
end
line, line2, line3, line4: begin
dbi = 8'b11111111;
wr = 1;
dr = 0;
end
endcase
end
endmodule
| 7.065026 |
module
module batch_normalization(input clk, input [15:0] data_in, input [15:0] mean [64], input [15:0] variance [64], output reg [15:0] data_out, parameter H = 256, parameter W = 256, parameter filters = 64);
// Define the storage registers for the batch normalization operation
reg [15:0] normalized_data [H][W][filters];
// Loop through each pixel in the input image and perform the batch normalization
always @(posedge clk) begin
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
for (int k = 0; k < filters; k++) {
// Use a DSP slice to perform the calculations in parallel
#(.DSP_BLOCK_TYPE("DSP48E1"))
DSP_block : DSP
(
.A(data_in[i][j][k]),
.B(mean[k]),
.C(variance[k]),
.Y(normalized_data[i][j][k]),
.CLK(clk),
.CE(1'b1),
.OP(3'b101),
.ALUMODE(3'b001),
.CARRYIN(1'b0),
.CLKGATE(1'b0),
.LATCH(1'b0),
.P(1'b0)
);
}
}
}
// Store the final batch normalization output in the data_out register
data_out = normalized_data;
end
endmodule
| 6.80639 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module battery_tb;
// Inputs
reg clk;
reg rst;
reg [127:0] state;
reg [127:0] key;
// Outputs
wire [127:0] out;
// Instantiate the Unit Under Test (UUT)
top uut (
.clk(clk),
.rst(rst),
.state(state),
.key(key),
.out(out)
);
initial begin
clk = 0;
state = 0;
key = 0;
rst = 0;
#50
rst = 1;
#25
rst = 0;
#25
/*
* TIMEGRP "key" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
* TIMEGRP "state" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
* TIMEGRP "out" OFFSET = OUT 2.2 ns BEFORE "clk" HIGH;
*/
@ (negedge clk);
# 2;
state = 128'h3243f6a8_885a308d_313198a2_e0370734;
key = 128'h2b7e1516_28aed2a6_abf71588_09cf4f3c;
#10;
state = 128'h00112233_44556677_8899aabb_ccddeeff;
key = 128'h00010203_04050607_08090a0b_0c0d0e0f;
#10;
state = 128'h0;
key = 128'h0;
#10;
state = 128'h0;
key = 128'h1;
#10;
state = 128'h1;
key = 128'h0;
#170;
if (out !== 128'h3925841d02dc09fbdc118597196a0b32)
begin $display("E"); $finish; end
#10;
if (out !== 128'h69_c4_e0_d8_6a_7b_04_30_d8_cd_b7_80_70_b4_c5_5a)
begin $display("E"); $finish; end
#10;
if (out !== 128'h66_e9_4b_d4_ef_8a_2c_3b_88_4c_fa_59_ca_34_2b_2e)
begin $display("E"); $finish; end
#10;
if (out !== 128'h05_45_aa_d5_6d_a2_a9_7c_36_63_d1_43_2a_3d_1c_84)
begin $display("E"); $finish; end
#10;
if (out !== 128'h58_e2_fc_ce_fa_7e_30_61_36_7f_1d_57_a4_e7_45_5a)
begin $display("E"); $finish; end
$display("Good.");
$finish;
end
always #5 clk = ~clk;
endmodule
| 7.115105 |
module battleScene (
output [11:0] rgb,
output reg attacked,
output reg [31:0] attackDamage,
input [7:0] kbControl,
input [31:0] x,
input [31:0] y,
input isActive,
input reset,
input clk
// ,
// output reg [7:0] attackPenalty,
// output wire [15:0] gaugeOffset
);
wire text, renderGauge;
reg [7:0] attackPenalty; // 0 to 100%
reg gaugePosition; // 0 leftside, 1 rightside of the center
reg gaugeMovingDirection; // 0 to right, 1 to left
wire [15:0] gaugeOffset;
wire frameClk;
reg miss;
frameClkGenerator fclk (
frameClk,
clk
);
Pixel_On_Text2 #(
.displayText("Battle Scene")
) t1 (
clk,
200,
100,
x,
y,
text
);
gaugeRenderer gauge (
renderGauge,
{22'd0, x},
{22'd0, y},
gaugeOffset
);
assign gaugeOffset = (attackPenalty * 8'd24 / 8'd10) * (gaugePosition == 0 ? -1 : 1);
initial begin
attackPenalty = 100;
gaugeMovingDirection = 0;
gaugePosition = 0;
miss = 0;
end
always @(posedge clk) begin
if (kbControl == 32 && isActive) //space
begin
attacked <= 1;
attackDamage <= 60 - (attackPenalty * 5 / 10);
end else if (miss && isActive && !reset) begin
attacked <= 1;
attackDamage <= 0;
end else begin
attacked <= 0;
attackDamage <= 0;
end
end
// Moving gauge pointer
always @(posedge frameClk) begin
if (isActive)
case ({
gaugePosition, gaugeMovingDirection
})
2'b00: begin
attackPenalty <= attackPenalty - 1;
if (attackPenalty == 0) gaugePosition <= 1;
end
2'b01: begin
attackPenalty <= attackPenalty + 1;
if (attackPenalty == 100) gaugeMovingDirection <= 0;
end
2'b10: begin
attackPenalty <= attackPenalty + 1;
if (attackPenalty == 100) begin
miss <= 1;
end
end
2'b11: begin
attackPenalty <= attackPenalty - 1;
if (attackPenalty == 0) gaugePosition <= 0;
end
endcase
else begin
miss <= 0;
gaugeMovingDirection <= 0;
gaugePosition <= 0;
attackPenalty <= 100;
end
end
assign rgb = (text || renderGauge) ? 12'hFFF : 12'h000;
endmodule
| 6.685497 |
module battleScreen (
input clk,
input rst,
input [6:0] switch,
output reg [2:0] r,
output reg [2:0] g,
output reg [1:0] b,
output hs,
output vs
);
parameter UP_BOUND = 31;
parameter DOWN_BOUND = 510;
parameter LEFT_BOUND = 144;
parameter RIGHT_BOUND = 783;
parameter TITLE = "BATTLE START";
reg [95:0] title = TITLE;
reg h_speed, v_speed;
reg [9:0] up_pos, down_pos, left_pos, right_pos;
wire pclk;
reg [1:0] count;
reg [9:0] hcount, vcount;
//reg [95:0] screen [29:0];
assign pclk = count[1];
//Display title logic here
wire [0:7] data;
wire [10:0] v_offset, h_offset, char_xoffset, char_yoffset;
assign v_offset = (vcount - 31) % 16;
assign h_offset = (hcount - 144) % 8;
assign char_xoffset = (hcount - 144) / 8 - 35;
assign char_yoffset = (vcount - 31) / 16 - 9;
wire [7:0] char;
assign char = char_yoffset != 0 ? 8'b0:
char_xoffset == 11 ? title[7:0] :
char_xoffset == 10 ? title[15:8] :
char_xoffset == 9 ? title[23:16] :
char_xoffset == 8 ? title[31:24] :
char_xoffset == 7 ? title[39:32] :
char_xoffset == 6 ? title[47:40] :
char_xoffset == 5 ? title[55:48] :
char_xoffset == 4 ? title[63:56] :
char_xoffset == 3 ? title[71:64] :
char_xoffset == 2 ? title[79:72] :
char_xoffset == 1 ? title[87:80] :
char_xoffset == 0 ? title[95:88] : 8'b0;
//Font ROM Instantiation
font_rom f0 (
char * 16 + v_offset,
data
);
always @(posedge clk) begin
if (rst) count <= 0;
else count <= count + 1'b1;
end
assign hs = (hcount < 96) ? 1'b0 : 1'b1;
always @(posedge pclk or posedge rst) begin
if (rst) hcount <= 0;
else if (hcount == 799) hcount <= 0;
else hcount <= hcount + 1'b1;
end
assign vs = (vcount < 2) ? 1'b0 : 1'b1;
always @(posedge pclk or posedge rst) begin
if (rst) vcount <= 0;
else if (hcount == 799) begin
if (vcount == 520) vcount <= 0;
else vcount <= vcount + 1'b1;
end else vcount <= vcount;
end
always @(posedge pclk or posedge rst) begin
if (rst) begin
r <= 3'b000;
g <= 3'b000;
b <= 2'b00;
end else begin
if (vcount >= 31 && vcount <= 510 && hcount >= 144 && hcount <= 783) begin
//If we want to display letters
if (data[h_offset]) begin
r <= 3'b000;
g <= 3'b111;
b <= 2'b00;
end else begin
r <= 3'b000;
g <= 3'b000;
b <= 2'b00;
end
end else begin
r <= 3'b000;
g <= 3'b000;
b <= 2'b00;
end
end
end
endmodule
| 7.738897 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module battle_module(
input clk_b,
input col_e,
input boss,
input [6:0] player_hit,
input [7:0] enemy_hit,
input [7:0] key_in,
output reg [7:0] HP_player,
output reg [7:0] HP_enemy,
output [2:0] p_attack,
output [2:0] e_attack
);
reg clk;
reg [3:0] a_pos_neg;
reg [3:0] accuracy;
reg [6:0] enemy_ran;
reg boss_check;
initial
begin
HP_player = 7'd100; //100 HP player
enemy_ran = $random%50;
if (enemy_ran > 8'd50)
enemy_ran = ~enemy_ran + 8'h01;
HP_enemy = enemy_ran + 8'd51;
boss_check = 1'b1;
end
always @(posedge clk_b)
begin
//Boss or Enemy?
if (boss == 1'b1 && boss_check == 1'b1) begin
HP_enemy = 8'd150; //150 HP Boss
boss_check = 1'b0;
end
end
endmodule
| 7.088073 |
module
// Module Name: X:/EC551/RPG_GAME_FPGA-master/RPG/ran_test.v
// Project Name: RPG
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: battle_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module battle_test;
// Inputs
reg clk_b;
reg col_e;
reg boss;
reg [7:0] key_in;
// Outputs
wire [6:0] HP_player;
wire [7:0] HP_enemy;
wire [2:0] p_attack;
wire [2:0] e_attack;
// Instantiate the Unit Under Test (UUT)
battle_module uut (
.clk_b(clk_b),
.col_e(col_e),
.boss(boss),
.key_in(key_in),
.HP_player(HP_player),
.HP_enemy(HP_enemy),
.p_attack(p_attack),
.e_attack(e_attack)
);
always begin
#1 clk_b = !clk_b;
end
initial begin
// Initialize Inputs
clk_b = 0;
col_e = 0;
key_in = 2'b11;
boss = 1'b0;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
end
endmodule
| 6.999332 |
module bat_amateur_controller (
input wire CLK,
RST,
input wire [7:0] ALU_REG,
input wire [15:0] INSTR,
output wire PC_INC,
output wire PC_RW,
output wire PC_EN,
output wire MAR_LOAD,
output wire MAR_EN,
output wire RAM_RW,
output wire RAM_EN,
output wire IR_LOAD,
output wire IR_EN,
//A, B, 3, 4, 5, 6, 7, OUT (from small to big)
output wire [7:0] REGS_INC,
output wire [7:0] REGS_RW,
output wire [7:0] REGS_EN,
output wire ALU_EN,
output wire [4:0] ALU_OP
);
reg [2:0] uOP;
reg ZERO_FLAG;
reg C_OUT;
wire reset_counter;
wire read_alu_flags;
controller_rom my_rom (
.INSTR(INSTR),
.uOP(uOP),
.ZERO_FLAG(ZERO_FLAG),
.COUT_FLAG(C_OUT),
.RESET_uOP(reset_counter),
.READ_FLAGS(read_alu_flags),
.PC_INC(PC_INC),
.PC_RW(PC_RW),
.PC_EN(PC_EN),
.MAR_LOAD(MAR_LOAD),
.MAR_EN(MAR_EN),
.RAM_RW(RAM_RW),
.RAM_EN(RAM_EN),
.IR_LOAD(IR_LOAD),
.IR_EN(IR_EN),
.REGS_INC(REGS_INC),
.REGS_RW(REGS_RW),
.REGS_EN(REGS_EN),
.ALU_EN(ALU_EN),
.ALU_OP(ALU_OP)
);
// make a counter for the ROM
//negedge to avoid causing race conditions
always @(negedge CLK) begin
if (!RST) begin
uOP <= 3'b111;
ZERO_FLAG <= 1'b0;
C_OUT <= 1'b0;
end else begin
if (reset_counter) uOP <= 3'b111;
else begin
//increment the uOP
//reset state for uOP is 3, then
uOP <= uOP + 4'd1;
end
// read the flags
if (read_alu_flags) begin
ZERO_FLAG <= ALU_REG[0];
C_OUT <= ALU_REG[1];
end
end
end
endmodule
| 6.888686 |
module bat_amateur_tb ();
parameter ADDRESS_WIDTH = 16;
wire CLK;
wire RESET;
wire HALT;
wire RAM_RW;
wire [15:0] DATA_BUS;
wire [ADDRESS_WIDTH-1:0] ADDRESS_BUS;
wire [15:0] OUTPUT_BUS;
bat_amateur my_bat_amateur (
.DATA(DATA_BUS),
.ADDRESS(ADDRESS_BUS),
.EXT_RAM_RW(RAM_RW),
.EXT_RAM_EN(HALT),
.HALT(HALT),
.CLK(CLK),
.RST(RESET),
.OUT(OUTPUT_BUS)
);
bat_amateur_stim my_bat_amateur_stim (
.HALT(HALT),
.CLK(CLK),
.RESET(RESET),
.RAM_RW(RAM_RW),
.RAM_EN(RAM_EN),
.DATA_BUS(DATA_BUS),
.ADDRESS_BUS(ADDRESS_BUS),
.OUTPUT_BUS(OUTPUT_BUS)
);
endmodule
| 7.186853 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(inst1_CO)
);
assign O = inst0_O;
assign COUT = inst1_CO;
endmodule
| 7.610141 |
module Add8Cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire inst6_O;
wire inst6_COUT;
wire inst7_O;
wire inst7_COUT;
FullAdder inst0 (
.I0(I0[0]),
.I1(I1[0]),
.CIN(1'b0),
.O(inst0_O),
.COUT(inst0_COUT)
);
FullAdder inst1 (
.I0(I0[1]),
.I1(I1[1]),
.CIN(inst0_COUT),
.O(inst1_O),
.COUT(inst1_COUT)
);
FullAdder inst2 (
.I0(I0[2]),
.I1(I1[2]),
.CIN(inst1_COUT),
.O(inst2_O),
.COUT(inst2_COUT)
);
FullAdder inst3 (
.I0(I0[3]),
.I1(I1[3]),
.CIN(inst2_COUT),
.O(inst3_O),
.COUT(inst3_COUT)
);
FullAdder inst4 (
.I0(I0[4]),
.I1(I1[4]),
.CIN(inst3_COUT),
.O(inst4_O),
.COUT(inst4_COUT)
);
FullAdder inst5 (
.I0(I0[5]),
.I1(I1[5]),
.CIN(inst4_COUT),
.O(inst5_O),
.COUT(inst5_COUT)
);
FullAdder inst6 (
.I0(I0[6]),
.I1(I1[6]),
.CIN(inst5_COUT),
.O(inst6_O),
.COUT(inst6_COUT)
);
FullAdder inst7 (
.I0(I0[7]),
.I1(I1[7]),
.CIN(inst6_COUT),
.O(inst7_O),
.COUT(inst7_COUT)
);
assign O = {inst7_O, inst6_O, inst5_O, inst4_O, inst3_O, inst2_O, inst1_O, inst0_O};
assign COUT = inst7_COUT;
endmodule
| 7.640389 |
module Register8R (
input [7:0] I,
output [7:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
wire inst4_Q;
wire inst5_Q;
wire inst6_Q;
wire inst7_Q;
SB_DFFSR inst0 (
.C(CLK),
.R(RESET),
.D(I[0]),
.Q(inst0_Q)
);
SB_DFFSR inst1 (
.C(CLK),
.R(RESET),
.D(I[1]),
.Q(inst1_Q)
);
SB_DFFSR inst2 (
.C(CLK),
.R(RESET),
.D(I[2]),
.Q(inst2_Q)
);
SB_DFFSR inst3 (
.C(CLK),
.R(RESET),
.D(I[3]),
.Q(inst3_Q)
);
SB_DFFSR inst4 (
.C(CLK),
.R(RESET),
.D(I[4]),
.Q(inst4_Q)
);
SB_DFFSR inst5 (
.C(CLK),
.R(RESET),
.D(I[5]),
.Q(inst5_Q)
);
SB_DFFSR inst6 (
.C(CLK),
.R(RESET),
.D(I[6]),
.Q(inst6_Q)
);
SB_DFFSR inst7 (
.C(CLK),
.R(RESET),
.D(I[7]),
.Q(inst7_Q)
);
assign O = {inst7_Q, inst6_Q, inst5_Q, inst4_Q, inst3_Q, inst2_Q, inst1_Q, inst0_Q};
endmodule
| 6.828672 |
module Counter8R (
output [7:0] O,
output COUT,
input CLK,
input RESET
);
wire [7:0] inst0_O;
wire inst0_COUT;
wire [7:0] inst1_O;
Add8Cout inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register8R inst1 (
.I(inst0_O),
.O(inst1_O),
.CLK(CLK),
.RESET(RESET)
);
assign O = inst1_O;
assign COUT = inst0_COUT;
endmodule
| 6.934292 |
module EQ8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
wire inst4_O;
wire inst5_O;
wire inst6_O;
wire inst7_O;
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst0 (
.I0(1'b1),
.I1(I0[0]),
.I2(I1[0]),
.I3(1'b0),
.O (inst0_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst1 (
.I0(inst0_O),
.I1(I0[1]),
.I2(I1[1]),
.I3(1'b0),
.O (inst1_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst2 (
.I0(inst1_O),
.I1(I0[2]),
.I2(I1[2]),
.I3(1'b0),
.O (inst2_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst3 (
.I0(inst2_O),
.I1(I0[3]),
.I2(I1[3]),
.I3(1'b0),
.O (inst3_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst4 (
.I0(inst3_O),
.I1(I0[4]),
.I2(I1[4]),
.I3(1'b0),
.O (inst4_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst5 (
.I0(inst4_O),
.I1(I0[5]),
.I2(I1[5]),
.I3(1'b0),
.O (inst5_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst6 (
.I0(inst5_O),
.I1(I0[6]),
.I2(I1[6]),
.I3(1'b0),
.O (inst6_O)
);
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst7 (
.I0(inst6_O),
.I1(I0[7]),
.I2(I1[7]),
.I3(1'b0),
.O (inst7_O)
);
assign O = inst7_O;
endmodule
| 6.605022 |
module Decode1028 (
input [7:0] I,
output O
);
wire inst0_O;
EQ8 inst0 (
.I0(I),
.I1({1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0}),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 6.682234 |
module Counter8Mod103 (
output [7:0] O,
output COUT,
input CLK
);
wire [7:0] inst0_O;
wire inst0_COUT;
wire inst1_O;
Counter8R inst0 (
.O(inst0_O),
.COUT(inst0_COUT),
.CLK(CLK),
.RESET(inst1_O)
);
Decode1028 inst1 (
.I(inst0_O),
.O(inst1_O)
);
assign O = inst0_O;
assign COUT = inst1_O;
endmodule
| 6.889517 |
module from 24MHz input clock.
module baudclock (
input clki,
output reg clko = 0
);
//localparam semiperiod = 32'd10000; // 1200 Hz
//localparam semiperiod = 16'd1250; // 9600 Hz
//localparam semiperiod = 16'd208; // 57600 Hz
localparam semiperiod = 16'd104; // 115200 Hz
reg [15:0] counter = 0;
always @(posedge clki) begin
counter <= counter + 1'b1;
if (counter == semiperiod) begin
counter <= 0;
clko <= ~clko;
end
end
endmodule
| 6.769499 |
module: BaudGenerator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BaudGeneratorTest;
// Inputs
reg RST;
reg CLK;
// Outputs
wire MID;
wire END;
// Instantiate the Unit Under Test (UUT)
BaudGenerator #(.SPLIT(1)) middle (
.RST(RST),
.CLK(CLK),
.OUT(MID)
);
// Instantiate the Unit Under Test (UUT)
BaudGenerator #(.SPLIT(0)) full (
.RST(RST),
.CLK(CLK),
.OUT(END)
);
always
begin
CLK = 1;
#5;
CLK = 0;
#5;
end
initial begin
// Initialize Inputs
RST = 1;
CLK = 0;
// Wait 100 ns for global reset to finish
#100;
RST = 0;
#4000;
RST = 1;
#1000;
RST = 0;
// Add stimulus here
end
endmodule
| 7.419467 |
module baudgen_rx #(
parameter BAUD = `B115200
) (
input wire clk,
input wire clk_ena,
output wire clk_out
);
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(BAUD);
//-- Valor para generar pulso en la mitad del periodo
localparam M2 = (BAUD >> 1);
//-- Registro para implementar el contador modulo M
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
if (clk_ena)
//-- Funcionamiento normal
divcounter <= (divcounter == BAUD - 1) ? 0 : divcounter + 1;
else
//-- Contador "congelado" al valor maximo
divcounter <= BAUD - 1;
//-- Sacar un pulso de anchura 1 ciclo de reloj si el generador
//-- esta habilitado (clk_ena == 1)
//-- en caso contrario se saca 0
//-- Se pone a uno en la mitad del periodo
assign clk_out = (divcounter == M2) ? clk_ena : 0;
endmodule
| 6.919471 |
module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//-- It tells the uart_tx when to transmit the next bit
//-- __ __
//-- __| |________________________________________________________| |________________
//-- -> <- 1 clock cycle
//--
//---------------------------------------------------------------------------------------
module baudgen_tx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire rstn, //-- Reset (active low)
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
always @(posedge clk)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is 0, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == 0) ? clk_ena : 0;
endmodule
| 6.654606 |
module baudrate (
input wire clk_i,
input wire rst_i,
input wire [7:0] control,
input wire [7:0] count,
output wire [7:0] status,
output wire baudrate
);
wire count_done;
reg [7:0] internal_count;
assign count_done = ((count == internal_count) & (internal_count != 'b0));
assign baudrate = count_done;
assign status = {6'b0, baudrate, count_done};
always @(posedge clk_i)
if (rst_i) internal_count <= 'b0;
else begin
if (count_done) internal_count <= 'b0;
else if (control[7]) internal_count <= internal_count + 1;
else internal_count <= 'b0;
end // else: !if(reset)
endmodule
| 8.166837 |
module BaudRateGen (
input Clock,
output reg BaudTick,
output reg OversampleTick
);
reg [31:0] OversampleCounter;
reg [31:0] BaudCounter;
initial begin
OversampleCounter = 0;
BaudCounter = 0;
BaudTick = 0;
OversampleTick = 0;
end
always @(posedge Clock) begin
if (OversampleCounter == 27) begin
OversampleCounter = 0;
OversampleTick = 1;
if (BaudCounter == 7) begin
BaudCounter = 0;
BaudTick = 1;
end else begin
BaudCounter = BaudCounter + 1;
BaudTick = 0;
end
end else begin
OversampleCounter = OversampleCounter + 1;
OversampleTick = 0;
BaudTick = 0;
end
end
endmodule
| 6.541889 |
module BaudRateGenerator (
sysclk,
BaudRate_clk
);
input sysclk;
output reg BaudRate_clk;
reg [12:0] state;
parameter divide = 13'd5208; //can be changed as a parameter when the module is called
initial begin
state <= 13'd0;
BaudRate_clk <= 0;
end
always @(posedge sysclk) begin
if (state == divide) state <= 13'd2;
else state <= state + 13'd2;
BaudRate_clk <= (state == 13'd2) ? ~BaudRate_clk : BaudRate_clk;
end
endmodule
| 7.123524 |
module BaudRateGeneratorI2C (
Enable,
ClockI2C,
Reset,
clock,
BaudRate,
ClockFrequency
);
input [19:0] BaudRate;
input [29:0] ClockFrequency;
input clock, Reset, Enable;
output reg ClockI2C;
reg [15:0] baud_count;
reg [15:0] counter;
always @(posedge clock or posedge Reset)
if (Reset == 1) begin
baud_count <= 1'b0;
ClockI2C <= 1'b1;
end else if (Enable == 0) begin
baud_count <= 1'b0;
ClockI2C <= 1'b1;
end else if (baud_count == ClockFrequency / (BaudRate * 3)) begin
baud_count <= 1'b0;
ClockI2C <= ~ClockI2C;
end else begin
baud_count <= baud_count + 1'b1;
end
endmodule
| 7.123524 |
module BaudRateGeneratorI2C_tb;
// Inputs
reg Enable;
reg Reset;
reg clock;
reg [19:0] BaudRate;
reg [29:0] ClockFrequency;
// Outputs
wire ClockI2C;
// Instantiate the Unit Under Test (UUT)
BaudRateGeneratorI2C uut (
.Enable(Enable),
.ClockI2C(ClockI2C),
.Reset(Reset),
.clock(clock),
.BaudRate(BaudRate),
.ClockFrequency(ClockFrequency)
);
initial begin
Enable = 0;
Reset = 0;
clock = 0;
BaudRate = 2;
ClockFrequency = 10;
end
always #4 clock = ~clock;
initial
fork
#0 Reset = 0;
#12 Reset = 1;
#19 Reset = 0;
#0 Enable = 0;
#23 Enable = 1;
#89 Enable = 0;
#120 Enable = 1;
#300 $stop;
join
endmodule
| 7.123524 |
module: BaudRateGen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BaudRateTester;
// Inputs
reg Clock;
// Outputs
wire BaudTick;
wire OverSampleTick;
// Instantiate the Unit Under Test (UUT)
BaudRateGen uut (
.Clock(Clock),
.BaudTick(BaudTick),
.OversampleTick(OversampleTick)
);
integer i;
initial begin
// Initialize Inputs
Clock = 0;
// Wait 100 ns for global reset to finish
#100;
Clock = 1;
// Add stimulus here
for (i = 0; i < 1000; i = i + 1)
begin
Clock = ~Clock;
#5;
end
end
endmodule
| 7.826795 |
module baudrate_gen #(
parameter CLK = 50E6,
parameter BAUDRATE = 19200
) (
input i_clock,
input i_reset,
output o_bank_register_clock
);
localparam integer N_CONT = CLK / (BAUDRATE * `N_TICKS);
localparam integer N_BITS = $clog2(N_CONT);
reg [N_BITS - 1:0] counter;
always @(posedge i_clock) begin
if (i_reset) begin
counter <= {N_BITS{1'b0}};
end else begin
if (counter < N_CONT) counter <= counter + 1;
else counter <= {N_BITS{1'b0}};
end
end
assign o_bank_register_clock = (counter == N_CONT) ? 1'b1 : 1'b0;
endmodule
| 6.735225 |
module: BaudGen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module baudtest;
// Inputs
reg sys_clk;
// Outputs
wire BaudTick;
wire Baud8Tick;
// Instantiate the Unit Under Test (UUT)
BaudGen uut (
.sys_clk(sys_clk),
.BaudTick(BaudTick)
);
Baud8Gen uut8 (
.sys_clk(sys_clk),
.Baud8Tick(Baud8Tick)
);
initial begin
// Initialize Inputs
sys_clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always begin
#18.5 sys_clk <= !sys_clk;
end
endmodule
| 7.414222 |
module: BaudRateGen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BaudTester2;
// Inputs
reg Clock;
// Outputs
wire BaudTick;
wire OversampleTick;
// Instantiate the Unit Under Test (UUT)
BaudRateGen uut (
.Clock(Clock),
.BaudTick(BaudTick),
.OversampleTick(OversampleTick)
);
always
begin
Clock = ~Clock;
#5;
end
initial begin
// Initialize Inputs
Clock = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.826795 |
module BaudTickGen (
input clk,
enable,
output BaudTick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 50000000;
parameter Baud = 115200;
function integer log2(input integer v);
begin
for (log2 = 0; v > 0; log2 = log2 + 1) v = v >> 1;
end
endfunction
//error over a byte
localparam BaudGeneratorAccWidth = log2(ClkFrequency / Baud) + 8;
reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc = 0;
localparam BaudGeneratorInc = ((Baud << (BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
always @(posedge clk) begin
if (enable)
BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc[BaudGeneratorAccWidth:0];
else BaudGeneratorAcc <= BaudGeneratorInc[BaudGeneratorAccWidth:0];
end
assign BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
endmodule
| 7.463142 |
module baudtx (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire load, //-- Señal de cargar / desplazamiento
output wire tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Reloj para la transmision
wire clk_baud;
//-- Registro de desplazamiento, con carga paralela
//-- Cuando DTR es 0, se carga la trama
//-- Cuando DTR es 1 se desplaza hacia la derecha, y se
//-- introducen '1's por la izquierda
always @(posedge clk_baud)
if (load == 0) shifter <= {"K", 2'b01};
else shifter <= {1'b1, shifter[9:1]};
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- Cuando estamos en modo carga (dtr == 0), se saca siempre un 1 para
//-- que la linea este siempre a un estado de reposo. De esta forma en el
//-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento
//-- sea desconocido
assign tx = (load) ? shifter[0] : 1;
//-- Divisor para obtener el reloj de transmision
divider #(BAUD) BAUD0 (
.clk_in (clk),
.clk_out(clk_baud)
);
endmodule
| 8.290911 |
module baudtx2 (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire load, //-- Señal de cargar / desplazamiento
output wire tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Reloj para la transmision
wire clk_baud;
//-- Registro de desplazamiento, con carga paralela
//-- Cuando DTR es 0, se carga la trama
//-- Cuando DTR es 1 se desplaza hacia la derecha, y se
//-- introducen '1's por la izquierda
always @(posedge clk_baud)
if (load == 0) shifter <= {"K", 2'b01};
else shifter <= {shifter[0], shifter[9:1]};
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- Cuando estamos en modo carga (dtr == 0), se saca siempre un 1 para
//-- que la linea este siempre a un estado de reposo. De esta forma en el
//-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento
//-- sea desconocido
assign tx = (load) ? shifter[0] : 1;
//-- Divisor para obtener el reloj de transmision
divider #(BAUD) BAUD0 (
.clk_in (clk),
.clk_out(clk_baud)
);
endmodule
| 7.971028 |
module baudtx2_tb ();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente para que funcione a 115200 baudios
baudtx2 #(`B115200) dut (
.clk (clk),
.load(dtr),
.tx (tx)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("baudtx2_tb.vcd");
$dumpvars(0, baudtx2_tb);
//-- Primer envio: cargar y enviar
#10 dtr <= 0;
#300 dtr <= 1;
//-- Segundo envio
#10000 dtr <= 0;
#2000 dtr <= 1;
//-- Tercer envio
#10000 dtr <= 0;
#2000 dtr <= 1;
#5000 $display("FIN de la simulacion");
$finish;
end
endmodule
| 6.707279 |
module baudtx3 (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
output wire tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
parameter DELAY = `T_250ms;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- 1 bit start + 8 bits datos + 1 bit stop
reg [9:0] shifter;
//-- Reloj para la transmision
wire clk_baud;
//-- Señal de carga periodica
wire load;
//-- Señal de load sincronizada con clk_baud
reg load2;
//-- Registro de desplazamiento, con carga paralela
//-- Cuando DTR es 0, se carga la trama
//-- Cuando DTR es 1 se desplaza hacia la derecha, y se
//-- introducen '1's por la izquierda
always @(posedge clk_baud)
if (load2 == 0) shifter <= {"K", 2'b01};
else shifter <= {1'b1, shifter[9:1]};
//-- Sacar por tx el bit menos significativo del registros de desplazamiento
//-- Cuando estamos en modo carga (dtr == 0), se saca siempre un 1 para
//-- que la linea este siempre a un estado de reposo. De esta forma en el
//-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento
//-- sea desconocido
assign tx = (load2) ? shifter[0] : 1;
//-- Sincronizar la señal load con clk_baud
//-- Si no se hace, 1 de cada X caracteres enviados tendrá algún bit
//-- corrupto (en las pruebas con la icEstick salian mal 1 de cada 13 aprox
always @(posedge clk_baud) load2 <= load;
//-- Divisor para obtener el reloj de transmision
divider #(BAUD) BAUD0 (
.clk_in (clk),
.clk_out(clk_baud)
);
//-- Divisor para generar la señal de carga periodicamente
divider #(DELAY) DIV0 (
.clk_in (clk),
.clk_out(load)
);
endmodule
| 7.800065 |
module baudtx3_tb ();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Instanciar el componente para que funcione a 115200 baudios
baudtx3 #(
.BAUD (`B115200),
.DELAY(4000)
) dut (
.clk(clk),
.tx (tx)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("baudtx3_tb.vcd");
$dumpvars(0, baudtx3_tb);
#40000 $display("FIN de la simulacion");
$finish;
end
endmodule
| 7.186342 |
module baudtx_tb ();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente para que funcione a 115200 baudios
baudtx #(`B115200) dut (
.clk (clk),
.load(dtr),
.tx (tx)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk <= ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("baudtx_tb.vcd");
$dumpvars(0, baudtx_tb);
//-- Primer envio: cargar y enviar
#10 dtr <= 0;
#300 dtr <= 1;
//-- Segundo envio
#10000 dtr <= 0;
#300 dtr <= 1;
//-- Tercer envio
#10000 dtr <= 0;
#300 dtr <= 1;
#5000 $display("FIN de la simulacion");
$finish;
end
endmodule
| 7.293536 |
module baud_clk_gen (
input ACLK,
input ARESETn,
input [12:0] baud_val,
output tx_baud_pulse,
output rx_sample_pulse
);
reg [12:0] baud_cnt;
always @(posedge ACLK or negedge ARESETn) begin
if (!ARESETn) begin
baud_cnt <= 13'h0;
end else begin
if (rx_sample_pulse) begin
baud_cnt <= 13'h0;
end else begin
baud_cnt <= baud_cnt + 13'h1;
end
end
end
assign rx_sample_pulse = (baud_cnt == baud_val);
reg [3:0] tx_cnt;
wire tx_pulse_en = tx_cnt == 4'hf;
always @(posedge ACLK or negedge ARESETn) begin
if (!ARESETn) begin
tx_cnt <= 4'h0;
end else begin
if (rx_sample_pulse) begin
if (tx_pulse_en) begin
tx_cnt <= 4'h0;
end else begin
tx_cnt <= tx_cnt + 4'h1;
end
end
end
end
assign tx_baud_pulse = tx_pulse_en && rx_sample_pulse;
endmodule
| 6.544302 |
module baud_clk_generator #(
parameter CLK_PER_BIT = 625
) ( //1250 => 4800 baud; 625 => 9600 baud
input wire clk,
input wire enable,
output reg baud_clk
);
reg [30:0] cnt = 0;
initial baud_clk = 0;
always @(posedge clk) begin
if (enable == 1'b1) cnt = cnt + 1;
else cnt = 0;
if (cnt >= CLK_PER_BIT) begin
cnt = 0;
baud_clk = ~baud_clk;
end
end
endmodule
| 7.217436 |
module baud_clock #(
parameter [15:0] divider = 16'd163
) (
input clk,
output reg tick
);
reg [15:0] counter = 16'd0;
always @(posedge clk) begin
counter <= counter + 1;
if (counter == divider) begin
tick <= ~tick;
counter <= 8'd0;
end
end
endmodule
| 6.595922 |
module baud_clock_generator #(
parameter CLOCK_RATE = 10000000,
parameter BAUD_RATE = 9600
) (
input wire clk,
input wire rst_n,
output wire tx_clk,
output wire rx_clk
);
//Standard baud rates include 110, 300, 600, 1200, 2400, 4800, 9600, 14400, 19200, 38400, 57600, 115200, 128000 and 256000 bits per second
localparam BITS = 32;
reg [BITS-1:0] tx_final_val = (CLOCK_RATE / (BAUD_RATE)) - 1;
reg [BITS-1:0] rx_final_val = (CLOCK_RATE / (16 * BAUD_RATE)) - 1;
reg [BITS-1:0] tx_counter;
reg [BITS-1:0] rx_counter;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
tx_counter <= 'b0;
rx_counter <= 'b0;
end else begin
//For TX CLK
if (tx_counter == tx_final_val) tx_counter = 'b0;
else tx_counter = tx_counter + 1;
//For RX CLK
if (rx_counter == rx_final_val) rx_counter = 'b0;
else rx_counter = rx_counter + 1;
end
end
assign tx_clk = (tx_counter == tx_final_val);
assign rx_clk = (rx_counter == rx_final_val);
endmodule
| 8.103444 |
module tb_baud_clock_generator ();
reg clk, rst_n;
reg [16:0] tx_bits_counter = 'b0;
reg [16:0] rx_bits_counter = 'b0;
wire tx_clk;
wire rx_clk;
localparam CLOCK_RATE = 100000000; //Need configuration
localparam BAUD_RATE = 9600; //Need configuration
localparam PERIOD = (1000000000 / CLOCK_RATE);
localparam _1SEC = 1000000000;
baud_clock_generator #(
.CLOCK_RATE(CLOCK_RATE),
.BAUD_RATE (BAUD_RATE)
) b1 (
.clk(clk),
.rst_n(rst_n),
.tx_clk(tx_clk),
.rx_clk(rx_clk)
);
always #(PERIOD / 2) clk = ~clk;
initial begin
clk = 1;
rst_n = 0;
#(PERIOD) rst_n = 1;
#_1SEC $display("%d\n%d", tx_bits_counter, rx_bits_counter);
end
always @(posedge tx_clk) tx_bits_counter = tx_bits_counter + 1;
always @(posedge rx_clk) rx_bits_counter = rx_bits_counter + 1;
endmodule
| 7.143067 |
module baud_cnter #(
parameter PRESCALER_WID = 8
, parameter DIVIDER_WID = 2
, parameter DIVIDER_CMPVAL = 2
) (
input glb_rstn
, input glb_clk
, input [PRESCALER_WID-1:0] Cfg_data_cmpval
, input STM_ctrl_rstn
, input STM_ctrl_cnt_en
, output reg baud_ctrl_sample_en
, output reg baud_ctrl_prescalerout
);
reg [PRESCALER_WID-1:0] prescaler;
reg [ DIVIDER_WID-1:0] divider;
always @(*) begin
baud_ctrl_prescalerout = prescaler == Cfg_data_cmpval;
end // always
always @(*) begin
baud_ctrl_sample_en = divider == DIVIDER_CMPVAL;
end // always
always @(posedge glb_clk or negedge glb_rstn) begin
if (~glb_rstn | ~STM_ctrl_rstn) begin
prescaler <= 0;
end else if (STM_ctrl_cnt_en) begin
prescaler <= (baud_ctrl_prescalerout) ? 0 : prescaler + 1;
end
end
always @(posedge glb_clk or negedge glb_rstn) begin
if (~glb_rstn | ~STM_ctrl_rstn) begin
divider <= 0;
end else if (baud_ctrl_prescalerout) begin
divider <= divider + 1;
end
end
endmodule
| 6.918478 |
module baud_counter (
input wire rst,
input wire en,
input wire [19:0] baud,
input wire [19:0] baud_cnto,
output reg [19:0] baud_cntn,
output reg baud_clk
);
wire reached;
wire valid_baud;
assign valid_baud = (baud >= 20'd15) ? 1'b1 : 1'b0;
assign reached = (baud_cnto == baud - 20'b1) ? 1'b1 : 1'b0;
always @* begin
if (rst) begin
baud_clk = 1'b0;
baud_cntn = 20'b0;
end else begin
if (en) begin
if (reached) begin
baud_clk = 1'b1;
baud_cntn = 20'b0;
end else begin
baud_clk = 1'b0;
baud_cntn = baud_cnto + 20'b1;
end
end else begin
baud_clk = 1'b0;
baud_cntn = 20'b0;
end
end
end
endmodule
| 6.903452 |
module BAUD_DECODE (
BAUD,
K
);
input [3:0] BAUD;
output [19:0] K;
reg [19:0] K;
always @(*)
case (BAUD)
4'b0000: K = 20'd333333; // 300
4'b0001: K = 20'd83333; // 1200
4'b0010: K = 20'd41667; // 2400
4'b0011: K = 20'd20833; // 4800
4'b0100: K = 20'd10417; // 9600
4'b0101: K = 20'd5208; // 19200
4'b0110: K = 20'd2604; // 38400
4'b0111: K = 20'd1736; // 57600
4'b1000: K = 20'd868; // 115200
4'b1001: K = 20'd434; // 230400
4'b1010: K = 20'd217; // 460800
4'b1011: K = 20'd109; // 921600
default: K = 20'd333333; //defaulted to slowest speed
endcase
endmodule
| 7.026208 |
module has been changed to receive the baud rate dividing counter from registers.
// the two registers should be calculated as follows:
// first register:
// baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
// second register:
// baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
//
//---------------------------------------------------------------------------------------
module baud_gen
(
clock, reset,
ce_16, baud_freq, baud_limit
);
//---------------------------------------------------------------------------------------
// modules inputs and outputs
input clock; // global clock input
input reset; // global reset input
output ce_16; // baud rate multiplyed by 16
input [11:0] baud_freq; // baud rate setting registers - see header description
input [15:0] baud_limit;
// internal registers
reg ce_16;
reg [15:0] counter;
//---------------------------------------------------------------------------------------
// module implementation
// baud divider counter
always @ (posedge clock or posedge reset)
begin
if (reset)
counter <= 16'b0;
else if (counter >= baud_limit)
counter <= counter - baud_limit;
else
counter <= counter + baud_freq;
end
// clock divider output
always @ (posedge clock or posedge reset)
begin
if (reset)
ce_16 <= 1'b0;
else if (counter >= baud_limit)
ce_16 <= 1'b1;
else
ce_16 <= 1'b0;
end
endmodule
| 6.790662 |
module baud_generator #(
parameter clk_rate = 100_000_000, //全局时钟频率100M
parameter baud_rate = 9_600 //波特率
) (
input clk_p,
input clk_n,
input rst_n,
output rx_clk,
output tx_clk
);
//localparam作用域和parameter一样，但是不能重定义
localparam tx_rate = clk_rate / (baud_rate * 2); //发送模块分频系数
localparam rx_rate = clk_rate / (baud_rate * 2 * 16); //接收模块分频系数，16倍采样分频
//***设置最节约的计数寄存器的方法----------------------------------------------------
/*$clog2是向上取整，例如rx_rate只要介于[513,1024]，结果都是10，位宽就是[9:0],表示0-1023的值
由于1024比1023大，因此还要进行-1调整-------------------------------------------------*/
wire clk;
IBUFGDS clk_inst (
.O (clk),
.I (clk_p),
.IB(clk_n)
);
reg [$clog2(rx_rate)-1:0] rx_count;
reg [$clog2(tx_rate)-1:0] tx_count;
reg rx_clk_reg;
reg tx_clk_reg;
// rx_clk分频
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
rx_count <= 'b0;
rx_clk_reg <= 1'b0;
end else if (rx_count == rx_rate - 1'b1) begin
rx_clk_reg <= !rx_clk_reg;
rx_count <= 'b0;
end else rx_count = rx_count + 1'b1;
end
//tx_clk分频
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tx_count <= 'b0;
tx_clk_reg <= 1'b0;
end else if (tx_count == tx_rate - 1'b1) begin
tx_clk_reg = !tx_clk_reg;
tx_count <= 'b0;
end else tx_count = tx_count + 1'b1;
end
assign rx_clk = rx_clk_reg;
assign tx_clk = tx_clk_reg;
endmodule
| 6.552695 |
module baud_generator_1 (
input clk,
input rst,
input baud_en,
output baud_tick
);
parameter clk_frequency = 24_000_000;
parameter baud = 9600;
parameter baud_cnt_width = 15;
parameter baud_temp = (baud << baud_cnt_width) / clk_frequency; //Ƽλdz2ļη
reg [baud_cnt_width:0] baud_cnt; //һλǷƵλ
reg baud_tick_r;
always @(posedge clk) begin
if (!rst) baud_cnt <= 500;
if (baud_en == 1) begin
baud_cnt <= baud_cnt[baud_cnt_width-1:0] + baud_temp;
baud_tick_r <= baud_cnt[baud_cnt_width];
end else baud_cnt <= baud_cnt;
end
assign baud_tick = baud_tick_r;
endmodule
| 6.552695 |
module baud_gen_tb;
reg clk;
reg rst;
reg [10:0] divsr;
wire tick;
baud_gen gen (
clk,
rst,
divsr,
tick
);
initial begin
clk = 0;
divsr = 11'd650;
rst = 0;
#1 rst = 1;
#1 rst = 0;
end
always begin
#5 clk = ~clk;
end
endmodule
| 6.577119 |
module BaudTickGen (
input wire clk,
output wire tick,
input wire baud_gen_on
);
reg [32:0] acc = 33'd0;
always @(posedge clk) begin
if (baud_gen_on) acc <= acc[31:0] + 824633;
else acc <= 33'd0;
end
assign tick = acc[32];
endmodule
| 7.463142 |
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