code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module dice (
ck,
rst,
enable,
nSEG,
CS
);
input ck, rst, enable;
output [7:0] nSEG;
output [2:0] CS;
reg [2:0] cnt;
assign CS = 3'b011;
always @(posedge ck or negedge rst) begin
if (rst == 1'b0) cnt <= 3'h1;
else if (enable == 1'b0)
if (cnt == 3'h6) cnt <= 3'h1;
e... | 6.970586 |
module yj_basic_reg_clk_p #(
parameter DW = 32,
parameter RSTVAL = 1'b0
) (
input CLK,
input RSTn,
input [DW-1:0] din,
output [DW-1:0] qout
);
reg [DW-1:0] qout_Reg;
assign qout = qout_Reg;
always @(posedge CLK or negedge RSTn) begin
if (!RSTn) begin
qout_Reg <= {DW{RSTVAL}... | 7.244693 |
module yj_basic_reg_clk_n #(
parameter DW = 32,
parameter RSTVAL = 1'b0
) (
input CLK,
input RSTn,
input [DW-1:0] din,
output [DW-1:0] qout
);
reg [DW-1:0] qout_Reg;
assign qout = qout_Reg;
always @(negedge CLK or negedge RSTn) begin
if (!RSTn) begin
qout_Reg <= {DW{RSTVAL}... | 7.244693 |
module yj_basic_signal_2lever_sync #(
parameter DW = 32
) (
input CLK,
input RSTn,
input [DW-1:0] din,
output [DW-1:0] dout
);
wire [DW-1:0] sync_dat[1:0];
yj_basic_reg_clk_p #(
.DW(DW),
.RSTVAL(1'b0)
) sync_1lever (
CLK,
RSTn,
din,
sync_dat[0]
);
y... | 9.826814 |
module basic_fifo #(
parameter DEPTH = 5,
parameter DATA_WIDTH = 32,
parameter INIT_ZERO = 0,
parameter ADDR_WIDTH = $clog2(DEPTH)
) (
input wire clk,
input wire rst,
input wire clear,
input wire din_valid,
input wire [DATA_WIDTH-1:0] din,
output wire ... | 6.822719 |
module basic_gate_structural (
a,
b,
c,
d,
e,
f,
g,
h,
i
);
input a, b;
output c, d, e, f, g, h, i;
not g0 (c, a);
and g1 (d, a, b);
or g2 (e, a, b);
nand g3 (f, a, b);
nor g4 (g, a, b);
xor g5 (h, a, b);
xnor g6 (i, a, b);
endmodule
| 7.002071 |
module basic_gate_dataflow (
a,
b,
c,
d,
e,
f,
g,
h,
i
);
input a, b;
output c, d, e, f, g, h, i;
assign c = ~a;
assign d = a & b;
assign e = a | b;
assign f = a ^ b;
assign g = ~(a & b);
assign h = ~(a | b);
assign i = ~(a ^ b);
endmodule
| 8.135332 |
module basic_gate_behavioural (
a,
b,
c,
d,
e,
f,
g,
h,
i
);
input a, b;
output reg c, d, e, f, g, h, i;
always @(a, b) begin
c = ~a;
d = a & b;
e = a | b;
f = a ^ b;
g = ~(a & b);
h = ~(a | b);
i = ~(a ^ b);
end
endmodule
| 6.607693 |
module basic_hashfunc #(
parameter input_sz = 48,
parameter table_sz = 1024,
parameter fsz = $clog2(table_sz)
) (
input [input_sz-1:0] hf_in,
output reg [fsz-1:0] hf_out
);
// const function not supported by Icarus Verilog
//localparam folds = num_folds(input_sz, fsz);
localparam folds = 5;
... | 7.348295 |
module Basic_layer_search (
input clk,
input rst_n,
input [255:0] ref_input,
input [511:0] current_64pixels,
input ref_begin_prepare,
input pe_begin_prepare,
output [415:0] SAD4x8,
output [415:0] SAD8x4,
output [223:0] SAD8x8,
output [119:0] SAD8x16,
output [119:0] SAD16x8,
... | 7.964308 |
module basic_memory_block (
input clock,
input write_enable,
input [WIDTH-1:0] read_address,
input [WIDTH-1:0] write_address,
input [15:0] data_in,
output reg [15:0] data_out,
);
parameter WIDTH = 8;
parameter mem_depth = 1 << WIDTH;
reg [15:0] mem[mem_depth-1:0];
always @(posedge clock) begin
... | 7.458004 |
module register (
q,
d,
clk,
enable,
reset
);
parameter width = 32, reset_value = 0;
output reg [(width-1):0] q;
input [(width-1):0] d;
input clk, enable, reset;
always @(posedge clk or posedge reset)
if (reset == 1'b1) q <= reset_value;
else if (enable == 1'b1) q <= d;
endmodu... | 6.542519 |
module regfile (
rsData,
rtData,
rsNum,
rtNum,
rdNum,
rdData,
rdWriteEnable,
clock,
reset
);
output [31:0] rsData, rtData;
input [4:0] rsNum, rtNum, rdNum;
input [31:0] rdData;
input rdWriteEnable, clock, reset;
reg signed [31:0] r[0:31];
integer i;
assign rsData = r... | 7.809308 |
module mux2v (
out,
A,
B,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] A, B;
input sel;
wire [width-1:0] temp1 = ({width{(!sel)}} & A);
wire [width-1:0] temp2 = ({width{(sel)}} & B);
assign out = temp1 | temp2;
endmodule
| 8.590864 |
module mux3v (
out,
A,
B,
C,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] A, B, C;
input [1:0] sel;
wire [width-1:0] wAB;
mux2v #(width) mAB (
wAB,
A,
B,
sel[0]
);
mux2v #(width) mfinal (
out,
wAB,
C,
sel[1]... | 8.723833 |
module mux4v (
out,
A,
B,
C,
D,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] A, B, C, D;
input [1:0] sel;
wire [width-1:0] wAB, wCD;
mux2v #(width) mAB (
wAB,
A,
B,
sel[0]
);
mux2v #(width) mCD (
wCD,
C,
D,
... | 8.321812 |
module mux16v (
out,
A,
B,
C,
D,
E,
F,
G,
H,
I,
J,
K,
L,
M,
N,
O,
P,
sel
);
parameter width = 32;
output [width-1:0] out;
input [width-1:0] A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P;
input [3:0] sel;
wire [width-1:0] wAB, wCD, wEF... | 7.305093 |
module mux32v (
out,
a,
b,
c,
d,
e,
f,
g,
h,
i,
j,
k,
l,
m,
n,
o,
p,
A,
B,
C,
D,
E,
F,
G,
H,
I,
J,
K,
L,
M,
N,
O,
P,
sel
);
parameter width = 32;
output [width-1:0] out;
input ... | 7.557627 |
module fulladder (
s,
cout,
a,
b,
cin
);
output s, cout;
input a, b, cin;
wire partial_s, partial_c1, partial_c2;
halfadder ha0 (
partial_s,
partial_c1,
a,
b
);
halfadder ha1 (
s,
partial_c2,
partial_s,
cin
);
or o1 (cout, partial_c1, ... | 7.454465 |
module basic_predictor_2b #(
parameter entry_num = 256,
parameter addr_width = $clog2(entry_num)
) (
input cpu_clk,
input cpu_rstn,
input wire [addr_width - 1 : 0] predictor_raddr,
input wire [addr_width - 1 : 0] predictor_waddr,
input wire predictor_wen,
input wire branch_taken_ex,
... | 6.946715 |
module basic_register #(
parameter DATA_WIDTH = 8
) (
input clk,
input rst,
input wr_en,
input [(DATA_WIDTH-1):0] data_in,
output [(DATA_WIDTH-1):0] data_out
);
reg [(DATA_WIDTH-1):0] data;
initial data <= 0;
always @(posedge clk or posedge rst) begin
if (rst) data <= 0;
else be... | 8.759639 |
module basic_regs #(
parameter [19:0] BASE_ADDRESS = 0,
parameter [19:0] SIZE_ADDRESS = 0
) (
// Request
input wire s_ctrlport_req_wr,
input wire s_ctrlport_req_rd,
input wire [19:0] s_ctrlport_req_addr,
input wire [31:0] s_ctrlport_req_data,
// Response
output reg ... | 7.15389 |
module Basic_RS_FlipFlop (
input notR,
input notS,
output Q,
output notQ
);
nand nand1 (Q, notS, notQ);
nand nand2 (notQ, notR, Q);
endmodule
| 7.250125 |
module basic_shift_register #(
parameter N = 256
) (
input clk,
enable,
input sr_in,
output sr_out
);
// Declare the shift register
reg [N-1:0] sr;
// Shift everything over, load the incoming bit
always @(posedge clk)
if (enable == 1'b1) begin
sr[N-1:1] <= sr[N-2:0];
sr[0] ... | 7.951889 |
module basic_switch (
left_in,
right_in,
left_out,
right_out,
select
);
parameter WIDTH = 64;
input [WIDTH-1:0] left_in, right_in;
output [WIDTH-1:0] left_out, right_out;
input select;
assign left_out = select ? right_in : left_in;
assign right_out = select ? left_in : right_in;
endmod... | 8.849587 |
module basic_switch_ff (
clk,
left_in,
right_in,
left_out,
right_out,
select
);
parameter WIDTH = 64;
input clk;
input [WIDTH-1:0] left_in, right_in;
(* KEEP = "TRUE" *) output reg [WIDTH-1:0] left_out, right_out;
input select;
(* KEEP = "TRUE" *) reg [WIDTH-1:0] left_in_r, right_in... | 8.091191 |
module register #(
parameter width = 1
) (
input clk,
reset,
stall,
flush,
input [width - 1:0] d,
output reg [width - 1:0] q
);
always @(posedge clk) begin
if (reset) q <= 0;
else if (~stall & flush) q <= 0;
else if (~stall) q <= d;
end
endmodule
| 8.732583 |
module mux2 #(
parameter width = 1
) (
input [width - 1:0] d0,
d1,
input sel,
output [width - 1:0] y
);
assign y = sel ? d1 : d0;
endmodule
| 9.827805 |
module mux3 #(
parameter width = 1
) (
input [width - 1:0] d0,
d1,
d2,
input [1:0] sel,
output [width - 1:0] y
);
assign y = (sel == 2'd0) ? d0 : (sel == 2'd1) ? d1 : (sel == 2'd2) ? d2 : {width{1'bx}};
endmodule
| 7.777057 |
module mux4 #(
parameter width = 1
) (
input [width - 1:0] d0,
d1,
d2,
d3,
input [1:0] sel,
output [width - 1:0] y
);
assign y = (sel == 2'd0) ? d0 :
(sel == 2'd1) ? d1 :
(sel == 2'd2) ? d2 :
(sel == 2'd3) ? d3 : {width{1'bx}};
endmodule
| 7.807913 |
module mux5 #(
parameter width = 1
) (
input [width - 1:0] d0,
d1,
d2,
d3,
d4,
input [2:0] sel,
output [width - 1:0] y
);
assign y = (sel == 3'd0) ? d0 :
(sel == 3'd1) ? d1 :
(sel == 3'd2) ? d2 :
(sel == 3'd3) ? d3 :
(sel == 3'... | 7.344479 |
module signext (
input [15:0] a,
output [31:0] y
);
assign y = {{16{a[15]}}, a};
endmodule
| 7.970829 |
module zeroext (
input [15:0] a,
output [31:0] y
);
assign y = {16'b0, a};
endmodule
| 8.133229 |
module ls16 (
input [15:0] a,
output [31:0] y
); // left shift by 16
assign y = {a, 16'b0};
endmodule
| 7.435057 |
module Basy3 (
input [1:0] display_mode,
input CLK,
Reset,
Button,
output [3:0] AN,
output [7:0] Out
);
wire [31:0] ALUresult, curPC, WriteData, ReadData1, ReadData2, instruction, nextPC;
wire myCLK, myReset;
reg [3:0] store;
CPU cpu (
myCLK,
myReset,
op,
funct,... | 6.906693 |
module basys2 (
input mclk,
input [7:0] sw,
input [3:0] btn,
output [7:0] Led,
output [6:0] seg,
output dp,
output [3:0] an
);
wire [9:0] inputs;
wire [9:0] outputs;
assign inputs = { 2'b0, sw };
assign Led = outputs [7:0];
top
(
.clock(mclk), .reset_... | 7.262407 |
module Basys2_Keyboard (
input wire clk,
input wire PS2C,
input wire PS2D,
output reg [7:0] key_code
);
reg [8:0] cntdiv;
wire ck1;
reg [9:0] s_buf;
reg PS2C_old;
always @(posedge clk) begin
cntdiv <= cntdiv + 1;
end
assign ck1 = cntdiv[8];
always @(posedge ck1) begin
PS2C_old... | 6.68841 |
module basys3 (
input clk,
input btnC,
input btnU,
input btnL,
input btnR,
input btnD,
input [15:0] sw,
output [15:0] led,
output [6:0] seg,
output dp,
output [3:0] an,
inout [7:0] JA,
inout [7:0] JB,
input RsRx
);
wire clock;
wire reset = btnU;
... | 6.699033 |
module Basys3_button_debouncer (
input i_Clk,
input [3:0] i_Buttons,
output [3:0] o_Buttons
);
// Target clock frequency
parameter c_CLK_FREQ = 106470000;
// Time that signal must be stable in microseconds
parameter c_FILTER_MICRO = 5000;
// Number of cycles to wait to consider signal stable
... | 7.40679 |
module Basys3_CPU (
input basys3_clock,
input reset_sw,
input [1:0] SW_in,
input next_button,
output [3:0] enable,
output [7:0] dispcode
);
wire [31:0] currentIAddr, nextIAddr;
wire [4:0] rs, rt;
wire [31:0] ReadData1, ReadData2;
wire [31:0] ALU_result, DataBus;
wire next_signal; //... | 7.854305 |
module basys3_display_controller (
input disp_clk,
input [3:0] dig3,
input [3:0] dig2,
input [3:0] dig1,
input [3:0] dig0,
input reset,
output [6:0] segments,
output reg [3:0] anodes
);
reg [3:0] decoder_input;
hex2_7seg decoder (
.hex_in (decoder_input),
.seg_out(segme... | 7.608402 |
module which will infer block RAMs
*/
module Basys3FujiIIe(
input clk_in_100MHz,
input button_reset
);
wire clk_100M;
wire clk_14M;
Basys3ClockGenerator clock_generator(
.clk_in_100MHz(clk_in_100MHz),
.clk_100M(clk_100M),
.clk_14M(clk_14M),
.reset(button_reset... | 8.000425 |
module Basys3_IO_Test (
input clk,
input btnC,
input btnL,
input btnR,
input [11:0] sw,
output [15:0] led,
output [3:0] an,
output [0:6] seg,
output dp,
output RsTx,
input RsRx
);
//
//////////////////////////////////////////////////////////////////////////////////
//
... | 7.366858 |
module: PIC16F54
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module PIC16F54_tb01_v;
// Inputs
reg rst;
reg clk;
reg [3:0] porta_in;
reg [7:0] portb_in;
// reg [15... | 6.567866 |
module picosoc_mem (
ram_rdata,
CLKOUT_5_BUFG,
\mem_addr_reg[9] ,
mem_wdata,
WEA,
WEBWE
);
output [31:0] ram_rdata;
input CLKOUT_5_BUFG;
input [7:0] \mem_addr_reg[9] ;
input [31:0] mem_wdata;
input [1:0] WEA;
input [1:0] WEBWE;
wire \<const0> ;
wire \<const1> ;
wire CLKOUT_5_B... | 7.00993 |
module toplevel (
input io_mainClk,
output io_uart_txd,
input io_uart_rxd,
input [15:0] sw,
output [15:0] io_led
);
wire [31:0] io_gpioA_read;
wire [31:0] io_gpioA_write;
wire [31:0] io_gpioA_writeEnable;
wire io_mainClk;
wire io_jtag_tck;
wire io_jtag_tdi;
wire io_jtag_tdo;
wire io... | 8.460384 |
module to support synthesis of
// an inspector project. The inputs and outputs
// are present only to ensure that none of the
// logic internal to the block is optimized away.
//
// There is little functionality to the block. The
// sel input comes from SW3:SW0 on the dev board
// and is used to select the counter th... | 6.963642 |
module basysConnections (
input clock,
input [15:0] SW,
//IP sensors
input JC4,
JC3,
JC2,
JC1, //[3:0] IPsensFront_in
input JC10,
JC9,
JC8,
JC7, //[3:0] IPsensBack_in
//IR sensors
input JB7,
JB8,
input JB1, //MIC
//H-Bridge
input JB3,
JB4, //C... | 7.493918 |
module BasysConnections_testBench ();
reg clock;
//reg [15:0] SW;
reg [3:0] IPsensFront_in;
reg [3:0] IPsensBack_in;
wire [1:0] motorSpeed;
wire [3:0] movingDirection;
basysConnections UUT (
.clock(clock),
//.SW(SW),
.JA8 (motorSpeed[1]),
.JA7 (motorSpeed[0]),
.JA4 (movi... | 8.063202 |
module basysTest (
input CLK,
input [3:0] BTN,
output [6:0] SEG,
output [3:0] AN,
output DP
);
wire RST_X = ~BTN[0];
assign AN = BTN;
assign DP = 0;
reg [ 7:0] tcount;
reg [31:0] count;
parameter MAX = 50 * 1024 * 1024;
always @(posedge CLK or negedge RST_X) begin
... | 7.139842 |
module bas_top (
CLOCK,
RST,
KEY1,
KEY2,
KEY3,
KEY4,
KEY5,
KEY6,
KEY7,
KEY8,
OUT_DATA,
C_PIN
);
input CLOCK, RST;
input KEY1, KEY2, KEY3, KEY4, KEY5, KEY6, KEY7, KEY8;
output [7:0] OUT_DATA;
//reg [7:0]OUT_DATA;
output [5:0] C_PIN;
//reg [2:0]C_PIN;
wire one... | 7.001999 |
module bat (
input rst,
input clk2,
input clk_20m,
input [1:0] carga,
output reg wr,
output reg dr,
output reg [7:0] direc,
output reg [7:0] dbi
);
reg [3:0] estado = 0;
reg [3:0] nestado = 0;
initial wr = 0;
initial dr = 0;
parameter stay = 0;
parameter dr1 = 1;
parameter... | 7.065026 |
module
module batch_normalization(input clk, input [15:0] data_in, input [15:0] mean [64], input [15:0] variance [64], output reg [15:0] data_out, parameter H = 256, parameter W = 256, parameter filters = 64);
// Define the storage registers for the batch normalization operation
reg [15:0] normalized_data [H][W][f... | 6.80639 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module battery_tb;
// Inputs
reg clk;
reg rst;
reg [127:0] state;
reg [127:0] key;
// Outputs
wire [127:0] out;
// Ins... | 7.115105 |
module battleScene (
output [11:0] rgb,
output reg attacked,
output reg [31:0] attackDamage,
input [7:0] kbControl,
input [31:0] x,
input [31:0] y,
input isActive,
input reset,
input clk
// ,
// output reg [7:0] attackPenalty,
// output wire [15:0] gaugeOffset
);... | 6.685497 |
module battleScreen (
input clk,
input rst,
input [6:0] switch,
output reg [2:0] r,
output reg [2:0] g,
output reg [1:0] b,
output hs,
output vs
);
parameter UP_BOUND = 31;
parameter DOWN_BOUND = 510;
parameter LEFT_BOUND = 144;
parameter RIGHT_BOUND = 783;
parameter TITLE = ... | 7.738897 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module battle_module(
input clk_b,
input col_e,
... | 7.088073 |
module
// Module Name: X:/EC551/RPG_GAME_FPGA-master/RPG/ran_test.v
// Project Name: RPG
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: battle_module
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////... | 6.999332 |
module bat_amateur_controller (
input wire CLK,
RST,
input wire [7:0] ALU_REG,
input wire [15:0] INSTR,
output wire PC_INC,
output wire PC_RW,
output wire PC_EN,
output wire MAR_LOAD,
output wire MAR_EN,
output wire RAM_RW,
output wire RAM_EN,
output wire IR_LOAD,
... | 6.888686 |
module bat_amateur_tb ();
parameter ADDRESS_WIDTH = 16;
wire CLK;
wire RESET;
wire HALT;
wire RAM_RW;
wire [15:0] DATA_BUS;
wire [ADDRESS_WIDTH-1:0] ADDRESS_BUS;
wire [15:0] OUTPUT_BUS;
bat_amateur my_bat_amateur (
.DATA(DATA_BUS),
.ADDRESS(ADDRESS_BUS),
.EXT_RAM_RW(RAM_RW),
... | 7.186853 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire inst0_O;
wire inst1_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (inst0_O)
);
SB_CARRY inst1 (
.I0(I0),
.I1(I1),
... | 7.610141 |
module Add8Cout (
input [7:0] I0,
input [7:0] I1,
output [7:0] O,
output COUT
);
wire inst0_O;
wire inst0_COUT;
wire inst1_O;
wire inst1_COUT;
wire inst2_O;
wire inst2_COUT;
wire inst3_O;
wire inst3_COUT;
wire inst4_O;
wire inst4_COUT;
wire inst5_O;
wire inst5_COUT;
wire inst6_... | 7.640389 |
module Register8R (
input [7:0] I,
output [7:0] O,
input CLK,
input RESET
);
wire inst0_Q;
wire inst1_Q;
wire inst2_Q;
wire inst3_Q;
wire inst4_Q;
wire inst5_Q;
wire inst6_Q;
wire inst7_Q;
SB_DFFSR inst0 (
.C(CLK),
.R(RESET),
.D(I[0]),
.Q(inst0_Q)
);
SB_DFFS... | 6.828672 |
module Counter8R (
output [7:0] O,
output COUT,
input CLK,
input RESET
);
wire [7:0] inst0_O;
wire inst0_COUT;
wire [7:0] inst1_O;
Add8Cout inst0 (
.I0(inst1_O),
.I1({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}),
.O(inst0_O),
.COUT(inst0_COUT)
);
Register8R inst1 ... | 6.934292 |
module EQ8 (
input [7:0] I0,
input [7:0] I1,
output O
);
wire inst0_O;
wire inst1_O;
wire inst2_O;
wire inst3_O;
wire inst4_O;
wire inst5_O;
wire inst6_O;
wire inst7_O;
SB_LUT4 #(
.LUT_INIT(16'h8282)
) inst0 (
.I0(1'b1),
.I1(I0[0]),
.I2(I1[0]),
.I3(1'b0),
... | 6.605022 |
module Decode1028 (
input [7:0] I,
output O
);
wire inst0_O;
EQ8 inst0 (
.I0(I),
.I1({1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0}),
.O (inst0_O)
);
assign O = inst0_O;
endmodule
| 6.682234 |
module Counter8Mod103 (
output [7:0] O,
output COUT,
input CLK
);
wire [7:0] inst0_O;
wire inst0_COUT;
wire inst1_O;
Counter8R inst0 (
.O(inst0_O),
.COUT(inst0_COUT),
.CLK(CLK),
.RESET(inst1_O)
);
Decode1028 inst1 (
.I(inst0_O),
.O(inst1_O)
);
assign O = i... | 6.889517 |
module from 24MHz input clock.
module baudclock (
input clki,
output reg clko = 0
);
//localparam semiperiod = 32'd10000; // 1200 Hz
//localparam semiperiod = 16'd1250; // 9600 Hz
//localparam semiperiod = 16'd208; // 57600 Hz
localparam semiperiod = 16'd104; // 115200 Hz
... | 6.769499 |
module: BaudGenerator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BaudGeneratorTest;
// Inputs
reg RST;
reg CLK;
// Outputs
wire MID;
wire END;
// Instantiate the Unit ... | 7.419467 |
module baudgen_rx #(
parameter BAUD = `B115200
) (
input wire clk,
input wire clk_ena,
output wire clk_out
);
//-- Numero de bits para almacenar el divisor de baudios
localparam N = $clog2(BAUD);
//-- Valor para generar pulso en la mitad del periodo
localparam M2 = (BAUD >> 1);
//-- Regi... | 6.919471 |
module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not regis... | 6.654606 |
module baudrate (
input wire clk_i,
input wire rst_i,
input wire [7:0] control,
input wire [7:0] count,
output wire [7:0] status,
output wire baudrate
);
wire count_done;
reg [7:0] internal_count;
assign count_done = ((count == internal_count) & (internal_count != 'b0));
assign ... | 8.166837 |
module BaudRateGen (
input Clock,
output reg BaudTick,
output reg OversampleTick
);
reg [31:0] OversampleCounter;
reg [31:0] BaudCounter;
initial begin
OversampleCounter = 0;
BaudCounter = 0;
BaudTick = 0;
OversampleTick = 0;
end
always @(posedge Clock) begin
if (OversampleCo... | 6.541889 |
module BaudRateGenerator (
sysclk,
BaudRate_clk
);
input sysclk;
output reg BaudRate_clk;
reg [12:0] state;
parameter divide = 13'd5208; //can be changed as a parameter when the module is called
initial begin
state <= 13'd0;
BaudRate_clk <= 0;
end
always @(posedge sysclk) begin
if... | 7.123524 |
module BaudRateGeneratorI2C (
Enable,
ClockI2C,
Reset,
clock,
BaudRate,
ClockFrequency
);
input [19:0] BaudRate;
input [29:0] ClockFrequency;
input clock, Reset, Enable;
output reg ClockI2C;
reg [15:0] baud_count;
reg [15:0] counter;
always @(posedge clock or posedge Reset)
if... | 7.123524 |
module BaudRateGeneratorI2C_tb;
// Inputs
reg Enable;
reg Reset;
reg clock;
reg [19:0] BaudRate;
reg [29:0] ClockFrequency;
// Outputs
wire ClockI2C;
// Instantiate the Unit Under Test (UUT)
BaudRateGeneratorI2C uut (
.Enable(Enable),
.ClockI2C(ClockI2C),
.Reset(Reset),
.c... | 7.123524 |
module: BaudRateGen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BaudRateTester;
// Inputs
reg Clock;
// Outputs
wire BaudTick;
wire OverSampleTick;
// Instantiate the Un... | 7.826795 |
module baudrate_gen #(
parameter CLK = 50E6,
parameter BAUDRATE = 19200
) (
input i_clock,
input i_reset,
output o_bank_register_clock
);
localparam integer N_CONT = CLK / (BAUDRATE * `N_TICKS);
localparam integer N_BITS = $clog2(N_CONT);
reg [N_BITS - 1:0] counter;
always @(posedg... | 6.735225 |
module: BaudGen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module baudtest;
// Inputs
reg sys_clk;
// Outputs
wire BaudTick;
wire Baud8Tick;
// Instantiate the Unit Under Test... | 7.414222 |
module: BaudRateGen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BaudTester2;
// Inputs
reg Clock;
// Outputs
wire BaudTick;
wire OversampleTick;
// Instantiate the Unit ... | 7.826795 |
module BaudTickGen (
input clk,
enable,
output BaudTick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 50000000;
parameter Baud = 115200;
function integer log2(input integer v);
begin
for (log2 = 0; v > 0; log2 = log2 + 1) v = v >> 1;
end
en... | 7.463142 |
module baudtx (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire load, //-- Señal de cargar / desplazamiento
output wire tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Registro de 10 bits para alma... | 8.290911 |
module baudtx2 (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
input wire load, //-- Señal de cargar / desplazamiento
output wire tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
//-- Registro de 10 bits para alm... | 7.971028 |
module baudtx2_tb ();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente para que funcione a 115200 baudios
baudtx2 #(`B115200) dut (
.clk (clk),
.load(dtr),
.tx (... | 6.707279 |
module baudtx3 (
input wire clk, //-- Reloj del sistema (12MHz en ICEstick)
output wire tx //-- Salida de datos serie (hacia el PC)
);
//-- Parametro: velocidad de transmision
parameter BAUD = `B115200;
parameter DELAY = `T_250ms;
//-- Registro de 10 bits para almacenar la trama a enviar:
//-- ... | 7.800065 |
module baudtx3_tb ();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Instanciar el componente para que funcione a 115200 baudios
baudtx3 #(
.BAUD (`B115200),
.DELAY(4000)
) dut (
.clk(clk),
.tx (tx)
);
//-- Generador de re... | 7.186342 |
module baudtx_tb ();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Linea de tranmision
wire tx;
//-- Simulacion de la señal dtr
reg dtr = 0;
//-- Instanciar el componente para que funcione a 115200 baudios
baudtx #(`B115200) dut (
.clk (clk),
.load(dtr),
.tx (tx... | 7.293536 |
module baud_clk_gen (
input ACLK,
input ARESETn,
input [12:0] baud_val,
output tx_baud_pulse,
output rx_sample_pulse
);
reg [12:0] baud_cnt;
always @(posedge ACLK or negedge ARESETn) begin
if (!ARESETn) begin
baud_cnt <= 13'h0;
end else begin
... | 6.544302 |
module baud_clk_generator #(
parameter CLK_PER_BIT = 625
) ( //1250 => 4800 baud; 625 => 9600 baud
input wire clk,
input wire enable,
output reg baud_clk
);
reg [30:0] cnt = 0;
initial baud_clk = 0;
always @(posedge clk) begin
if (enable == 1'b1) cnt = cnt + 1;
else cnt = 0;
i... | 7.217436 |
module baud_clock #(
parameter [15:0] divider = 16'd163
) (
input clk,
output reg tick
);
reg [15:0] counter = 16'd0;
always @(posedge clk) begin
counter <= counter + 1;
if (counter == divider) begin
tick <= ~tick;
counter <= 8'd0;
end
end
endmodule
| 6.595922 |
module baud_clock_generator #(
parameter CLOCK_RATE = 10000000,
parameter BAUD_RATE = 9600
) (
input wire clk,
input wire rst_n,
output wire tx_clk,
output wire rx_clk
);
//Standard baud rates include 110, 300, 600, 1200, 2400, 4800, 9600, 14400, 19200, 38400, 57600, 115200, 128000 and 2560... | 8.103444 |
module tb_baud_clock_generator ();
reg clk, rst_n;
reg [16:0] tx_bits_counter = 'b0;
reg [16:0] rx_bits_counter = 'b0;
wire tx_clk;
wire rx_clk;
localparam CLOCK_RATE = 100000000; //Need configuration
localparam BAUD_RATE = 9600; //Need configuration
localparam PERIOD = (1000000000 / CLOCK_RATE);
... | 7.143067 |
module baud_cnter #(
parameter PRESCALER_WID = 8
, parameter DIVIDER_WID = 2
, parameter DIVIDER_CMPVAL = 2
) (
input glb_rstn
, input glb_clk
, input [PRESCALER_WID-1:0] Cfg_data_cmpval
, input STM_ctrl_rstn
, input STM_ctrl_cnt_en
, output reg baud_ctrl_sample_en
, output reg b... | 6.918478 |
module baud_counter (
input wire rst,
input wire en,
input wire [19:0] baud,
input wire [19:0] baud_cnto,
output reg [19:0] baud_cntn,
output reg baud_clk
);
wire reached;
wire valid_baud;
assign valid_baud = (baud >= 20'd15) ? 1'b1 : 1'b0;
assign reached = (baud_cnto == baud - 20'b1... | 6.903452 |
module BAUD_DECODE (
BAUD,
K
);
input [3:0] BAUD;
output [19:0] K;
reg [19:0] K;
always @(*)
case (BAUD)
4'b0000: K = 20'd333333; // 300
4'b0001: K = 20'd83333; // 1200
4'b0010: K = 20'd41667; // 2400
4'b0011: K = 20'd20833; // 4800
4'b0100: K = 20'd10417; // 9600... | 7.026208 |
module has been changed to receive the baud rate dividing counter from registers.
// the two registers should be calculated as follows:
// first register:
// baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
// second register:
// baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate))... | 6.790662 |
module baud_generator #(
parameter clk_rate = 100_000_000, //全局时钟频率100M
parameter baud_rate = 9_600 //波特率
) (
input clk_p,
input clk_n,
input rst_n,
output rx_clk,
output tx_clk
);
//localparam作用域和parameter一样，但是不能重定义
localparam tx_rate = clk_rate / (baud_rate * 2); //发送模块分频系数
loc... | 6.552695 |
module baud_generator_1 (
input clk,
input rst,
input baud_en,
output baud_tick
);
parameter clk_frequency = 24_000_000;
parameter baud = 9600;
parameter baud_cnt_width = 15;
parameter baud_temp = (baud << baud_cnt_width) / clk_frequency; //Ƽλdz2ļη
reg [baud_cnt_width:0] baud_cnt; //һλǷƵ... | 6.552695 |
module baud_gen_tb;
reg clk;
reg rst;
reg [10:0] divsr;
wire tick;
baud_gen gen (
clk,
rst,
divsr,
tick
);
initial begin
clk = 0;
divsr = 11'd650;
rst = 0;
#1 rst = 1;
#1 rst = 0;
end
always begin
#5 clk = ~clk;
end
endmodule
| 6.577119 |
module BaudTickGen (
input wire clk,
output wire tick,
input wire baud_gen_on
);
reg [32:0] acc = 33'd0;
always @(posedge clk) begin
if (baud_gen_on) acc <= acc[31:0] + 824633;
else acc <= 33'd0;
end
assign tick = acc[32];
endmodule
| 7.463142 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.