code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module addScore (
input hit,
input rst,
input [1:0] lineCount,
output reg [11:0] score
);
initial score = 0;
reg [11:0] t = 12'h001;
// map the lines to the score
always @(*) begin
case (lineCount)
2'b00: t <= 12'h001;
2'b01: t <= 12'h004;
2'b10: t <= 12'h009;
2'b1... | 7.956526 |
module bcd_3digit_incrementor (
input wire [3:0] digit0,
digit1,
digit2,
output wire [3:0] out0,
out1,
out2,
output wire carry
);
// internal signal declaration
wire carry0, carry1;
// instances of digit incrementors
bcd_digit_incrementor inc0 (
.bcd_in(digit0),
... | 6.763738 |
module bcd_3digit_incrementor_tb;
// signal declaration
reg [3:0] digit0, digit1, digit2;
wire [3:0] out0, out1, out2;
wire carry;
// instance of uut
bcd_3digit_incrementor uut (
.digit0(digit0),
.digit1(digit1),
.digit2(digit2),
.out0 (out0),
.out1 (out1),
.out2 (ou... | 6.763738 |
module BCD_4_8 (
input [3:0] in,
output reg [7:0] a
);
always @(in) begin
if (in == 4'b0000) out = 8'b00000000;
else if (in == 4'b0001) out = 8'b00000001;
else if (in == 4'b0010) out = 8'b00000010;
else if (in == 4'b0011) out = 8'b00000011;
else if (in == 4'b0100) out = 8'b00000100;
el... | 6.803691 |
module bcd_7 (
input [3:0] A,
output [6:0] out
);
wire [3:0] in;
reg [6:0] B;
assign in = A;
assign out = B;
always @(in) begin
case (in)
4'b0000: B <= 7'b0111111;
4'b0001: B <= 7'b0000110;
4'b0010: B <= 7'b1011011;
4'b0011: B <= 7'b1001111;
4'b0100: B <= 7'b110... | 7.352462 |
module bcdto7segmentclocked (
input [3:0] A,
B,
C,
D,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] x;
wire [3:0] an;
wire [1:0] sel;
wire clk_div;
bcdto7segment_dataflow bcdto7segment (
.x(x),
.an(an),
.anode(anode),
.seg(s... | 7.120176 |
module bcdto7segment_dataflow (
input [3:0] x,
input [3:0] an,
output [3:0] anode,
output reg [6:0] seg
);
//reg [6:0] seg;
assign anode = an;
always @(x or an)
case (x)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg =... | 7.120176 |
module mux16to4 (
input [3:0] A,
input [3:0] B,
input [3:0] C,
input [3:0] D,
input [1:0] sel,
output reg [3:0] S
);
always @(A, B, C, D, sel)
case (sel)
0: S = A;
1: S = B;
2: S = C;
3: S = D;
default: S = 0;
endcase
endmodule
| 7.78955 |
module demux4to1 (
input [1:0] sel,
output reg A,
output reg B,
output reg C,
output reg D
);
always @(sel)
case (sel)
0: {D, C, B, A} = ~(4'b0001);
1: {D, C, B, A} = ~(4'b0010);
2: {D, C, B, A} = ~(4'b0100);
3: {D, C, B, A} = ~(4'b1000);
default: {D, C, B, A} = ~... | 7.031285 |
module ClkDivider (
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 50000; //f=1kHz f=100MHz/(2*constantNumber)
//localparam constantNumber = 25000000;//f=2Hz f=100MHz/(2*constantNumber)
reg [31:0] count;
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1)... | 6.643482 |
module top_bcd (
//input [3:0] A, B, C, D,
input [12:0] number,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] A, B, C, D;
bcd bcd (
.number(number),
.thousands(D),
.hundreds(C),
.tens(B),
.ones(A)
);
bcdto7segmentclocked bcdt... | 7.367091 |
module bcdto7segmentclocked (
input [3:0] A,
B,
C,
D,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] x;
wire [3:0] an;
wire [1:0] sel;
wire clk_div;
bcdto7segment_dataflow bcdto7segment (
.x(x),
.an(an),
.anode(anode),
.seg(s... | 7.120176 |
module bcdto7segment_dataflow (
input [3:0] x,
input [3:0] an,
output [3:0] anode,
output reg [6:0] seg
);
//reg [6:0] seg;
assign anode = an;
always @(x or an)
case (x)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg =... | 7.120176 |
module mux16to4 (
input [3:0] A,
input [3:0] B,
input [3:0] C,
input [3:0] D,
input [1:0] sel,
output reg [3:0] S
);
always @(A, B, C, D, sel)
case (sel)
0: S = A;
1: S = B;
2: S = C;
3: S = D;
default: S = 0;
endcase
endmodule
| 7.78955 |
module demux4to1 (
input [1:0] sel,
output reg A,
output reg B,
output reg C,
output reg D
);
always @(sel)
case (sel)
0: {D, C, B, A} = ~(4'b0001);
1: {D, C, B, A} = ~(4'b0010);
2: {D, C, B, A} = ~(4'b0100);
3: {D, C, B, A} = ~(4'b1000);
default: {D, C, B, A} = ~... | 7.031285 |
module ClkDivider (
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 50000; //f=1kHz f=100MHz/(2*constantNumber)
//localparam constantNumber = 25000000;//f=2Hz f=100MHz/(2*constantNumber)
reg [31:0] count;
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1)... | 6.643482 |
module bcd_7seg (
input [3:0] bcd,
output [6:0] seg
);
reg [6:0] seg1;
assign seg = seg1;
always @(bcd)
case (bcd)
4'b0000: seg1 <= 7'b1000000;
4'b0001: seg1 <= 7'b1111001;
4'b0010: seg1 <= 7'b0100100;
4'b0011: seg1 <= 7'b0110000;
4'b0100: seg1 <= 7'b0011001;
4'b01... | 6.710996 |
module BCD_7seg_100_ca (
shiwei_out,
gewei_out,
num_in
); // 7线数据输入一个100以内的二进制数，输出两个数码管编码
output wire [7:0] shiwei_out, gewei_out;
input [6:0] num_in;
reg [3:0] shiwei_value;
reg [3:0] gewei_value;
always @(num_in) begin
shiwei_value = num_in / 10;
gewei_value = num_in % 10;
end
BCD... | 7.831039 |
module bcd_8421 (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
input wire [19:0] data, //输入需要转换的数据
output reg [3:0] unit, //个位BCD码
output reg [3:0] ten, //十位BCD码
output reg [3:0] hun, //百位BCD码
output reg [3:0] tho, //千位BCD码
out... | 7.263611 |
module BCD_8421_BCD_2421 (
a,
y
);
input [3:0] a;
output [3:0] y;
assign y[3] = a[3] & ~a[2] | a[2] & a[1] | a[2] & a[0];
assign y[2] = a[3] & ~a[2] | a[2] & a[1] | a[2] & ~a[1] & ~a[0];
assign y[1] = a[3] & ~a[2] | ~a[3] & ~a[2] & a[1] | a[2] & ~a[1] & a[0];
assign y[0] = ~a[3] & a[0] | a[3] & a[0]... | 6.939156 |
module BCD_8421_BCD_3 (
sel,
in,
out
); //selΪѡźţ0Ϊ8421תΪ3룬1Ϊ3ת8421
input [3:0] in;
input sel;
output reg [3:0] out;
always @(*) begin
if (!sel) out = in + 4'b0011;
else out = in - 4'b0011;
end
endmodule
| 6.939156 |
module bcd_adder (
a,
b,
c0,
s,
cout
);
input [3:0] a, b;
input c0;
output [3:0] s;
output cout;
wire [3:0] z, six;
wire temp_cout, o1, o2, waste_cout;
four_bit_add FB1 (
a,
b,
c0,
z,
temp_cout
);
and (o1, z[3], z[2]);
and (o2, z[3], z[1]);
or (cou... | 6.697199 |
module bcd_adder_4_tb ();
reg [15:0] a;
reg [15:0] b;
reg c_in;
wire [15:0] sum;
wire c_out;
parameter CYCLE = 5'd20;
always #10
a = ((sum[3:0]==4'd9) & (sum[7:4]!=4'd9)) ? (sum + 5'b1_0001 - 5'b0_1010 ) :
((sum[3:0]==4'd9) & (sum[7:4]==4'd9) & (sum[11:8]!=4'd9)) ? (sum + 9'b1_0001_0001 - 9'b0... | 6.561878 |
module bcd_adder_gate_level (
input Cin,
input [3:0] X1,
X0,
Y1,
Y0,
output [3:0] S1,
S0,
output Cout
);
bcd_full_adder_1digit adder0 (
Cin,
X0,
Y0,
S0,
K
);
bcd_full_adder_1digit adder1 (
K,
X1,
Y1,
S1,
Cout
);
endmod... | 7.300358 |
module bcd_adder_tb ();
reg [3:0] a;
reg [3:0] b;
reg c_in;
wire [3:0] sum;
wire c_out;
parameter CYCLE = 5'd20;
always #10 a = (sum == 4'd9) ? 4'b0 : sum + 1'd1;
initial begin
a = 4'b0000;
b = 4'b0000;
c_in = 1'b0;
#(CYCLE * 50);
$stop;
end
bcd_adder bcd_adder_test (
... | 6.86161 |
module non_carry_add (
ina,
inb,
sum
);
parameter WIDTH = 10;
input [WIDTH-1:0] ina, inb;
output [WIDTH-1:0] sum;
wire [WIDTH-1:0] sum;
wire [ WIDTH:0] cin;
assign cin[0] = 1'b0;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : chn
assign sum[i] = ina[i] ^ inb[i] ... | 7.659573 |
modules
module bcd_adj (datai,
datao,
bcd_en,
cin4,
cin8,
cout,
sub);
input [7:0] datai; // in
output [7:0] datao; // out
input bcd_en; // enable bcd adjust
input cin4; // half carry in
input cin8; // carry in
output cout; // carry out
input sub; // subtract flag
wire [7:... | 7.846843 |
module bcd_adjust (
input wire clk,
reset,
input wire start,
input wire [3:0] bcd6,
bcd5,
bcd4,
bcd3,
bcd2,
bcd1,
bcd0,
output wire [3:0] bcd_out3,
bcd_out2,
bcd_out1,
bcd_out0,
output wire [1:0] decimal_counter,
output reg ready,
... | 7.51948 |
module bcd_bin #(
parameter SIZE_bcd = 8'd28,
parameter SIZE_bin = 8'd24
) (
input clk,
input rstn,
input [SIZE_bcd-1:0] data_bcd,
output reg [SIZE_bin-1:0] data_bin,
output reg valid
);
reg [7:0] cnt;
reg [SIZE_bcd-1:0] data_b... | 7.052638 |
module bcd_control (
display1,
display2,
display3,
display4,
sel,
saida
);
input [3:0] display1;
input [3:0] display2;
input [3:0] display3;
input [3:0] display4;
input [1:0] sel;
output reg [3:0] saida;
always @(sel) begin
case (sel)
0: saida = display1;
1: sai... | 6.673665 |
module BCD_Counter (
Clk,
Cin,
Rst_n,
Cout,
q
);
input Clk;
input Cin;
input Rst_n;
output Cout;
output [3:0] q;
reg [3:0] cnt;
always @(posedge Clk or negedge Rst_n) begin
if (Rst_n == 1'b0) cnt <= 4'd0;
else if (Cin == 1'b1) begin
if (cnt == 4'd9) cnt <= 4'd0;
... | 6.966103 |
module BCD_counter_2bit (
output [3:0] value1,
output [3:0] value0,
output cout,
input [3:0] init1,
input [3:0] init0,
input [3:0] limit1,
input [3:0] limit0,
input clk,
input rst_n,
input en
);
reg [3:0] limit0_temp;
wire carry;
BCD_counter U0 (
value0,
carry... | 6.544536 |
module BCD_counter_4bit (
output [3:0] value3,
output [3:0] value2,
output [3:0] value1,
output [3:0] value0,
input [3:0] init3,
input [3:0] init2,
input [3:0] init1,
input [3:0] init0,
input [3:0] limit3,
input [3:0] limit2,
input [3:0] limit1,
input [3:0] limit0,
in... | 7.209232 |
module BCD_Counter_tb;
reg Clk;
reg Cin;
reg Rst_n;
wire Cout;
wire [3:0] q;
BCD_Counter BCD_Counter0 (
.Clk(Clk),
.Cin(Cin),
.Rst_n(Rst_n),
.Cout(Cout),
.q(q)
);
initial Clk = 1'b1;
always #(`clock_period / 2) Clk = ~Clk;
initial begin
Rst_n = 1'b0;
Cin = ... | 7.312047 |
module BCD_counter_TOP (
clk_50M,
mode,
BCD_preset,
BCD_out
);
input clk_50M;
input [3:0] mode;
input [7:0] BCD_preset;
output [7:0] BCD_out;
//ʱӷƵģ
wire clk_1s;
clock_division #(
.DIVCLK_CNTMAX(24_999_999)
) my_clock_0 (
.clk_in(clk_50M),
.divclk(clk_1s)
);
//BCDܼ
... | 6.503863 |
module bcd_decoder (
input [3:0] D,
output reg [6:0] out
);
always @(D) begin
case (D)
4'b0000: out = 7'b1000000; //0
4'b0001: out = 7'b1111001; //1
4'b0010: out = 7'b0100100; //2
4'b0011: out = 7'b0110000; //3
4'b0100: out = 7'b0011001; //4
4'b0101: out = 7'b0010... | 7.18658 |
module BCD_decoder3dig (
input [7:0] in,
output [3:0] dig1,
output [3:0] dig2,
output [3:0] dig3
);
wire [7:0] tens;
wire [7:0] hundreds;
assign dig1 = in % 10;
assign tens = in / 10;
assign dig2 = tens % 10;
assign hundreds = in / 100;
assign dig3 = hundreds % 10;
endmodule
| 6.537036 |
module BCD_decoder3dig_test;
reg [7:0] in;
wire [3:0] dig1;
wire [3:0] dig2;
wire [3:0] dig3;
BCD_decoder3dig DUT (
.in (in),
.dig1(dig1),
.dig2(dig2),
.dig3(dig3)
);
initial begin
in = 0;
#40;
end
initial begin
#100;
in = 123;
#100;
in = 145;
#1... | 6.537036 |
module BCD_decoder_modified (
Count, // Display output 0-9 with 4 bits binary input using case
Output
);
input [3:0] Count;
integer i;
output reg [0:6] Output;
always @(Count)
// 0-a, 1-b, 2-c, 3-d, 4-e, 5-f, 6-g
case (Count)
4'b0000: Output[0:6] = 7'b0000001; // 0
4'b... | 6.601495 |
module bcd_decorder0 (
binary,
hex
);
input [7:0] binary;
output reg [6:0] hex;
reg binary1;
always @(*) begin
case (binary)
8'b0: hex = ~(8'b0111111);
8'd1: hex = ~(8'b0000110);
8'd2: hex = ~(8'b1011011);
8'd3: hex = ~(8'b1001111);
8'd4: hex = ~(8'b1100110);
8'd... | 7.021072 |
module bcd_digit_incrementor_tb;
// signal declaration
reg [3:0] bcd_in;
reg inc;
wire [3:0] bcd_out;
wire carry;
// instance of digit incrementor
bcd_digit_incrementor inc0 (
.bcd_in(bcd_in),
.inc(inc),
.bcd_out(bcd_out),
.carry(carry)
);
// test vector
init... | 7.096657 |
module bcd_digit_incrementor (
input wire [3:0] bcd_in,
input wire inc,
output reg [3:0] bcd_out,
output reg carry
);
always @* begin
if (inc) begin
if (bcd_in == 4'b1001) begin
bcd_out = 4'b0000;
carry = 1'b1;
end else begin
bcd_out = bcd_in ... | 7.096657 |
module BCD_downcounter (
input clk, //时钟输入
input rst, //异步复位输入
input bin, //借位输入
input preset, //同步预置数输入
input [3:0] BCD_i, //BCD码计数输入
output [3:0] BCD_o, //BCD码计数输出
output bout //借位输出
);
reg [3:0] cnt;
always @(posedge clk or posed... | 6.997209 |
module bcd_fib_test (
input wire clk,
reset,
input wire btn,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire start;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
// debouncing circuit
debounce db_unit (
.clk(clk),
.reset... | 7.426995 |
module BCD_functional_counter (
input clk, //ʱź
input [3:0] mode, //ģʽź
input [3:0] BCD_preset, //Ԥź
output [3:0] BCD_out, //4bitBCD
input bcin, //ڼź
output reg bcout //ڼź
);
parameter preset = 4'b0001;
parameter cle... | 7.869065 |
module BCD_hex (
Output,
getValue
);
input [3:0] getValue;
output reg [6:0] Output;
always @(getValue) begin
case (getValue)
4'b0000: Output = 7'b1000000; //0
4'b0001: Output = 7'b1111001; //1
4'b0010: Output = 7'b0100100; //2
4'b0011: Output = 7'b0110000; //3
4'b01... | 6.920147 |
module bcd_incrementor_test (
input wire clk,
input wire [11:0] sw,
output wire [ 7:0] sseg,
output wire [ 3:0] an,
output wire led_carry
);
// signal declaration
wire [3:0] out0, out1, out2;
wire [7:0] led0, led1, led2, led3;
// instance of 3-digit incrementor
bcd_3digit... | 8.549542 |
module BCD_LED1 (
in,
LED
);
output [6:0] LED;
reg [6:0] LED;
input [4:0] in;
always @(in)
case (in)
0: LED = 7'b0000001;
1: LED = 7'b1001111;
2: LED = 7'b0010010;
3: LED = 7'b0000110;
4: LED = 7'b1001100;
5: LED = 7'b0100100;
6: LED = 7'b1100000;
7: L... | 7.294759 |
module BCD_n (
input wire [3:0] number,
output wire [6:0] digit_n
);
wire [6:0] digit;
BCD bcd (
.number(number[3:0]),
.digit (digit[6:0])
);
assign digit_n = ~digit[6:0];
endmodule
| 7.322114 |
module bcd_seg_disp (
input wire [3:0] in,
input wire max,
output reg [6:0] out
);
always @(*) begin
//如果计满信号为高电平，则直接输出9
if (max) begin
out <= 7'b0010000;
end //输入0-9十种BCD码判断，并输出对应的七段数码管显示信号
else begin
case (in)
4'b0000: out <= 7'b1000000;
4'b0001: out <= 7'b... | 7.59162 |
module bcd_subtracter (
input [3:0] X1,
X0,
Y1,
Y0,
output [3:0] S1,
S0,
output Cout
);
wire [3:0] Z0, Z1;
nines_complement nc0 (
Y0,
Z0
);
nines_complement nc1 (
Y1,
Z1
);
bcd_adder_gate_level adder (
1,
X1,
X0,
Z1,
Z0,
... | 6.563068 |
module bcd_to_7seg (
input [3:0] BCD,
output reg [7:0] s
);
always @(BCD) begin
case (BCD)
0: s = 8'b10001000;
1: s = 8'b11101101;
2: s = 8'b10100010;
3: s = 8'b10100100;
4: s = 8'b11000101;
5: s = 8'b10010100;
6: s = 8'b1... | 7.217745 |
module BCD_TO_7SEGMENT_1BIT (
BCD,
A,
B,
C,
D,
E,
F,
G
);
input [3:0] BCD;
output A, B, C, D, E, F, G;
reg [6:0] DECODE;
always @(BCD) begin
case (BCD)
4'b0000: DECODE <= 7'b1111110; //segment 0
4'b0001: DECODE <= 7'b0110000; //segment 1
4'b0010: DECODE... | 6.575047 |
module bcd_to_7_segment (
//----------------Input ports------------------------------
input wire [3:0] hundreds,
input wire [3:0] tens,
input wire [3:0] ones,
//----------------Output ports-----------------------------
output reg [6:0] display_0,
output reg [6:0] display_1,
output r... | 6.802975 |
module decoder_hex_10 (
input [3:0] bcd,
output reg [6:0] H,
output reg E
);
always @(bcd)
if (bcd > 4'b1001) begin
E = 1;
end else begin
E = 0;
case (bcd)
0: H = 7'b0000001;
1: H = 7'b1001111;
2: H = 7'b0010010;
3: H = 7'b0000110;
4: H = 7... | 7.325232 |
module BCD_to_DEC (
input [7:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
HEX1
);
assign LEDR[7:0] = SW[7:0];
decoder_hex_10 decoder1 (
SW[3:0],
HEX0,
LEDR[8]
);
decoder_hex_10 decoder2 (
SW[7:4],
HEX1,
LEDR[9]
);
endmodule
| 8.654396 |
module bcd_to_dec_2_bits (
input [3:0] a0,
a1,
output reg error_a0,
error_a1,
output [6:0] o_a0,
o_a1
);
always @(a0 or a1) begin
error_a0 = 0;
error_a1 = 0;
if (a0 > 4'b1001) error_a0 = 1;
if (a1 > 4'b1001) error_a1 = 1;
end
decoder_hex_10 d0 (
a0[3:0],
o_a0... | 8.887649 |
module bcd_to_dec_2_bits_on_board (
input [7:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
HEX1
);
assign LEDR[7:0] = SW;
bcd_to_dec_2_bits(
SW[3:0], SW[7:4], LEDR[8], LEDR[9], HEX0, HEX1
);
endmodule
| 8.887649 |
module decoder_hex_16 (
input [3:0] bcd,
output reg [0:6] H
);
always @(bcd)
case (bcd)
0: H = 7'b0000001;
1: H = 7'b1001111;
2: H = 7'b0010010;
3: H = 7'b0000110;
4: H = 7'b1001100;
5: H = 7'b0100100;
6: H = 7'b0100000;
7: H = 7'b0001111;
8: H = 7'b00... | 7.325232 |
module BCD_to_HEX (
input [7:0] SW,
output [0:6] HEX0,
HEX1
);
decoder_hex_16 decoder1 (
SW[3:0],
HEX0
);
decoder_hex_16 decoder2 (
SW[7:4],
HEX1
);
endmodule
| 7.326311 |
module BCD_to_LedBit (
input [3:0] BCD,
input Point, //暂未使用小数点
output reg [7:0] LedBit
);
/************************************************************************************************************************
*BCD码译成数码管断码
********************************************************************************... | 6.809166 |
module bcd_to_segment7 (
input [3:0] bcd,
output reg [6:0] seg
);
always @(bcd) begin
case (bcd)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
6: seg = 7'b0100000;
7: seg = 7'b0... | 8.172879 |
module bcd_to_sev (
hex,
led
);
input [3:0] hex;
output reg [1:7] led;
always @(hex) //a four bit input is given and a 7 line output
case (hex) //is obtained for 7 segment display
4'b0000: led = 7'b1111110; //input=0
4'b0001: led = 7'b0110000; //input=1
4'b0010: led = 7'b110110... | 8.563529 |
module bcd_to_seven (
hex,
led
);
input [3:0] hex;
output reg [1:7] led;
always @(hex) //a four bit input is given and a 7 line output
case (hex) //is obtained for 7 segment display
4'b0000: led = 7'b1111110; //input=0
4'b0001: led = 7'b0110000; //input=1
4'b0010: led = 7'b1101... | 8.224997 |
module bcd_to_sev_seg (
bcd,
seven_seg
);
input [3:0] bcd;
output reg [0:6] seven_seg;
always @* begin
case (bcd)
4'b0000: begin
seven_seg = ~7'b1111110;
end
4'b0001: begin
seven_seg = ~7'b0110000;
end
4'b0010: begin
seven_seg = ~7'b1101101;
... | 6.935241 |
module bcd_to_sev_seg (
bcd,
seven_seg
);
input [3:0] bcd;
output reg [0:6] seven_seg;
always @* begin
case (bcd)
4'b0000: begin
seven_seg = ~7'b1111110;
end
4'b0001: begin
seven_seg = ~7'b0110000;
end
4'b0010: begin
seven_seg = ~7'b1101101;
... | 6.935241 |
module bcd_to_sseg (
input wire [3:0] bcd,
input wire dp,
output reg [7:0] sseg // ouput active low
);
always @* begin
case (bcd)
4'h0: sseg[6:0] = 7'b0000001;
4'h1: sseg[6:0] = 7'b1001111;
4'h2: sseg[6:0] = 7'b0010010;
4'h3: sseg[6:0] = 7'b0000110;
4'h4: sseg[... | 7.184267 |
module tb_bcd_updown ();
wire [7:0] count;
reg clock, reset, control;
bcd_updown uut (
count,
clock,
reset,
control
);
initial begin
#00 clock = 1'b0;
forever #10 clock = ~clock;
end
initial begin
#00 reset = 1'b1;
control = 1'b0;
#10 reset = 1'b0;
#10 r... | 7.263313 |
module bcd_updown (
count,
clock,
reset,
control
);
output reg [7:0] count;
input wire clock, reset, control;
//Negative Edge Triggered Clock and Active Low Asynchronous Reset
always @(negedge clock or negedge reset)
if (reset == 0) count <= 8'b0000_0000;
else if (control == 1) //UP ... | 6.891395 |
module bch3d_128_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:127] DATA_OUT;
reg [0:144] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
bch3d_128_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.ena... | 7.166673 |
module bch3d_64_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:63] DATA_OUT;
reg [0:78] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
bch3d_64_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(... | 7.159828 |
module bch_128_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:127] DATA_OUT;
reg [0:143] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
bch_128_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(... | 7.075573 |
module bch_64_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:63] DATA_OUT;
reg [0:77] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
bch_64_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),... | 7.168894 |
module bch_blank_ecc #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* First cycle */
input ce, /* Accept input word/cycle output word */
output [BITS-1:0] xor_out,
output first, /* First output cycle */
... | 6.875218 |
module bch_chien #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
/*
* For multi-bit output, Only implement every Nth register. Use async
* logic to fill in the remaining values.
*/
parameter REG_RATIO = BITS > 8 ? 8 : BITS
) (
input clk,
input start,
input [`BCH_SI... | 7.094633 |
module bch_dec #(
parameter P_D_WIDTH = 32
) (
input wire [ P_D_WIDTH-1:0] d_i,
input wire [fn_ecc_synd_width(P_D_WIDTH)-1:0] ecc_i,
output wire [ P_D_WIDTH-1:0] msk_o,
output wire err_det_o
);
//****************************... | 7.931096 |
module bch_decode #(
parameter N = 15,
parameter K = 5,
parameter T = 3, /* Correctable errors */
parameter OPTION = "SERIAL"
) (
input clk,
input globrst,
input start,
input data_in,
input ready,
output output_valid,
output data_out
);
`include "bch.vh"
if (T < 3... | 7.057629 |
module bch_encoder #(
parameter P_D_WIDTH = 21
) (
input wire [P_D_WIDTH-1:0] data_org_in,
// output wire[fn_ecc_synd_width(P_D_WIDTH)-1:0] data_ecc_out
output wire [ 9:0] data_ecc_out
);
//**********************************************************************
`include "bch_func.in... | 7.78675 |
module bch_encode_wrapper #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter OPTION = "SERIAL",
parameter BITS = 1,
parameter REG_RATIO = 1
) (
input clk,
input reset,
input [`BCH_DATA_BITS(P)-1:0] data_in,
input din_en,
output [`BCH_CODE_BITS(P)-1:0] data_out,
output reg ... | 6.738022 |
module bch_enc_parity #(
parameter P_D_WIDTH = 16
) (
input wire [ P_D_WIDTH-1:0] d_i,
output wire [fn_ecc_synd_width(P_D_WIDTH)-1:0] p_o
);
//**********************************************************************
`include "bch_func.inc"
//**********************************... | 7.424307 |
module bch_error_dec #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Latch inputs, start calculating */
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output [`BCH... | 8.484252 |
module bch_error_one #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Latch inputs, start calculating */
input [`BCH_M(P)*2-1:0] sigma,
output first, /* First valid output data */
output [BITS-1:0] err
);
... | 7.294102 |
module bch_error_tmec #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0,
parameter ACCUM = PIPELINE_STAGES > 1 ? `CONFIG_LUT_SZ : 1
) (
input clk,
input start, /* Latch inputs, start calculating */
... | 7.140267 |
module finite_divider #(
parameter M = 6
) (
input clk,
input start,
input [M-1:0] standard_numer,
input [M-1:0] standard_denom,
output [M-1:0] dual_out,
output reg busy = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam DONE = lfsr_count(log2(M), M - 2);
localparam INITIAL = `... | 6.662806 |
module pow3 #(
parameter M = 4
) (
input [M-1:0] in,
output [M-1:0] out
);
`include "bch.vh"
genvar i, j, k;
wire [ M-1:0] ft_in;
wire [M*M-1:0] st_in;
generate
for (i = 0; i < M; i = i + 1) begin : FIRST_TERM
localparam BITS = lpow(M, 3 * i);
/* first_term = a_i * alpha^(3*i) ... | 6.886102 |
module finite_parallel_adder #(
parameter M = 4,
parameter N_INPUT = 2
) (
input [M*N_INPUT-1:0] in,
output [M-1:0] out
);
genvar i, j;
for (i = 0; i < M; i = i + 1) begin : add
wire [N_INPUT-1:0] z;
for (j = 0; j < N_INPUT; j = j + 1) begin : arrange
assign z[j] = in[j*M+i];
end
... | 7.457991 |
module bch_syndrome #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Accept first syndrome bit (assumes ce) */
input ce,
input [BITS-1:0] data_in,
output ready,
output [`BCH_... | 7.297116 |
module bch_syndrome_shuffle #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE
) (
input clk,
input start, /* Accept first syndrome bit */
input ce, /* Shuffle cycle */
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output reg [(2*`BCH_T(P)-1)*`BCH_M(P)-1:0] syn_shuffled = 0
);
localparam M = `BCH_... | 7.165201 |
module bch_errors_present #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start,
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output done,
output errors_present /* Valid during done cycle */
);
localparam M = `BCH_M(P);
genvar i;
wire... | 7.290449 |
module dsynN_method1 #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter SYN = 0,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Accept first bit of syndrome */
input start_pipelined, /* Start delayed by... | 8.49154 |
module dsynN_method2 #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter SYN = 0,
parameter DEGREE = `BCH_M(P),
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input ce, /* Accept additional bit */
input start, /* Accept first bit of syndrome */
input start_p... | 7.726686 |
module x_ychooser (
command,
xin1,
yin1,
xin2,
yin2,
out_x,
out_y,
color1in,
color2in,
color3in,
color4in,
color5in,
color6in,
color7in,
color8in,
colorout
);
output reg [7:0] out_x;
output reg [6:0] out_y;
input [7:0] xin1, xin2;
input [6:0] yin... | 6.878053 |
module bclk_dll ( // Clock in ports
input clk133in,
// Clock out ports
output clk133,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = clk133in;
// Clocking primitive
//--------------------------... | 6.912322 |
module bclk_dll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
in... | 7.274408 |
module bclk_dll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.5... | 7.671107 |
module bcnt (
clk,
rst,
trig,
out
);
input clk;
input rst;
input trig; //Order Trigger
//trig 0 == UpCounter
//trig 1 == DownCounter
output reg [3:0] out;
always @(posedge clk, negedge rst) begin
if (!rst) out <= (trig == 1'b0) ? 4'b0000 : 4'b1111;
else begin
case (trig)
... | 7.289211 |
module bcpu16_consts #(
parameter DATA_WIDTH = 16
) (
// input register value
input wire [DATA_WIDTH - 1 : 0] B_VALUE_IN,
// bbb: B register index from instruction - used as const index when CONST_MODE==1
input wire [2:0] B_REG_INDEX,
// mm: const_mode - when 00 return B_VALUE_IN, when 01,10,... | 8.381997 |
module bcpu16_sdp_regfile #(
// 16, 17, 18
parameter DATA_WIDTH = 16,
// 2^3 regs * 2^2 threads = 5 bits for 32 registers addressing
parameter REG_ADDR_WIDTH = 5
) (
//=========================================
// Synchronous write port
// clock: write operation is done synchronously using th... | 9.081002 |
module bcpu_cond_eval (
// input flag values {V,S,Z,C}
input wire [3:0] FLAGS_IN,
// condition code, 0000 is unconditional
input wire [3:0] CONDITION_CODE,
// 1 if condition is met
output wire CONDITION_RESULT
);
assign CONDITION_RESULT
= (CONDITION_CODE==`COND_NONE) ? 1'b1 // 0000 ... | 8.421206 |
module bcpu_dualport_bram #(
// data width
parameter DATA_WIDTH = 32,
// address width
parameter ADDR_WIDTH = 12,
// specify init file to fill ram with
parameter INIT_FILE = "",
// port A output register flag
parameter A_REG = 1,
// port B output register flag
parameter B_REG = 1... | 7.147466 |
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