code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module addScore (
input hit,
input rst,
input [1:0] lineCount,
output reg [11:0] score
);
initial score = 0;
reg [11:0] t = 12'h001;
// map the lines to the score
always @(*) begin
case (lineCount)
2'b00: t <= 12'h001;
2'b01: t <= 12'h004;
2'b10: t <= 12'h009;
2'b11: t <= 12'h016;
endcase
end
wire [11:0] update;
// add the scores accordingly to wire update
bcd_adder b0 (
score,
t,
update
);
// when reset, score = 0
always @(posedge hit or posedge rst) begin
if (rst == 1'b1) score <= 12'h000;
else score <= update;
end
endmodule
| 7.956526 |
module bcd_3digit_incrementor (
input wire [3:0] digit0,
digit1,
digit2,
output wire [3:0] out0,
out1,
out2,
output wire carry
);
// internal signal declaration
wire carry0, carry1;
// instances of digit incrementors
bcd_digit_incrementor inc0 (
.bcd_in(digit0),
.inc(1'b1),
.bcd_out(out0),
.carry(carry0)
);
bcd_digit_incrementor inc1 (
.bcd_in(digit1),
.inc(carry0),
.bcd_out(out1),
.carry(carry1)
);
bcd_digit_incrementor inc2 (
.bcd_in(digit2),
.inc(carry1),
.bcd_out(out2),
.carry(carry)
);
endmodule
| 6.763738 |
module bcd_3digit_incrementor_tb;
// signal declaration
reg [3:0] digit0, digit1, digit2;
wire [3:0] out0, out1, out2;
wire carry;
// instance of uut
bcd_3digit_incrementor uut (
.digit0(digit0),
.digit1(digit1),
.digit2(digit2),
.out0 (out0),
.out1 (out1),
.out2 (out2),
.carry (carry)
);
// test vector
initial begin
for (digit2 = 0; digit2 < 10; digit2 = digit2 + 1) begin
for (digit1 = 0; digit1 < 10; digit1 = digit1 + 1) begin
for (digit0 = 0; digit0 < 10; digit0 = digit0 + 1) begin
#1;
end
end
end
$stop;
end
endmodule
| 6.763738 |
module BCD_4_8 (
input [3:0] in,
output reg [7:0] a
);
always @(in) begin
if (in == 4'b0000) out = 8'b00000000;
else if (in == 4'b0001) out = 8'b00000001;
else if (in == 4'b0010) out = 8'b00000010;
else if (in == 4'b0011) out = 8'b00000011;
else if (in == 4'b0100) out = 8'b00000100;
else if (in == 4'b0101) out = 8'b00000101;
else if (in == 4'b0110) out = 8'b00000110;
else if (in == 4'b0111) out = 8'b00000111;
else if (in == 4'b1000) out = 8'b00001000;
else if (in == 4'b1001) out = 8'b00001001;
else if (in == 4'b1010) out = 8'b00010000;
else if (in == 4'b1011) out = 8'b00010001;
else if (in == 4'b1100) out = 8'b00010010;
else if (in == 4'b1101) out = 8'b00010011;
else if (in == 4'b1110) out = 8'b00010100;
else if (in == 4'b1111) out = 8'b00010101;
else out = 7'bX;
end
endmodule
| 6.803691 |
module bcd_7 (
input [3:0] A,
output [6:0] out
);
wire [3:0] in;
reg [6:0] B;
assign in = A;
assign out = B;
always @(in) begin
case (in)
4'b0000: B <= 7'b0111111;
4'b0001: B <= 7'b0000110;
4'b0010: B <= 7'b1011011;
4'b0011: B <= 7'b1001111;
4'b0100: B <= 7'b1100110;
4'b0101: B <= 7'b1101101;
4'b0110: B <= 7'b1111101;
4'b0111: B <= 7'b0100111;
4'b1000: B <= 7'b1111111;
4'b1001: B <= 7'b1101111;
default B <= 7'b0000000;
endcase
end
endmodule
| 7.352462 |
module bcdto7segmentclocked (
input [3:0] A,
B,
C,
D,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] x;
wire [3:0] an;
wire [1:0] sel;
wire clk_div;
bcdto7segment_dataflow bcdto7segment (
.x(x),
.an(an),
.anode(anode),
.seg(seg)
);
mux16to4 mux16to4 (
.A (A),
.B (B),
.C (C),
.D (D),
.sel(sel),
.S (x)
);
demux4to1 demux4to1 (
.sel(sel),
.A (an[0]),
.B (an[1]),
.C (an[2]),
.D (an[3])
);
counter counter (
.reset(reset),
.clk (clk_div),
.out (sel)
);
ClkDivider ClkDivider (
.clk(clk),
.rst(reset),
.clk_div(clk_div)
);
endmodule
| 7.120176 |
module bcdto7segment_dataflow (
input [3:0] x,
input [3:0] an,
output [3:0] anode,
output reg [6:0] seg
);
//reg [6:0] seg;
assign anode = an;
always @(x or an)
case (x)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
6: seg = 7'b0100000;
7: seg = 7'b0001111;
8: seg = 7'b0000000;
9: seg = 7'b0000100;
default: seg = 7'b0000000;
endcase
endmodule
| 7.120176 |
module mux16to4 (
input [3:0] A,
input [3:0] B,
input [3:0] C,
input [3:0] D,
input [1:0] sel,
output reg [3:0] S
);
always @(A, B, C, D, sel)
case (sel)
0: S = A;
1: S = B;
2: S = C;
3: S = D;
default: S = 0;
endcase
endmodule
| 7.78955 |
module demux4to1 (
input [1:0] sel,
output reg A,
output reg B,
output reg C,
output reg D
);
always @(sel)
case (sel)
0: {D, C, B, A} = ~(4'b0001);
1: {D, C, B, A} = ~(4'b0010);
2: {D, C, B, A} = ~(4'b0100);
3: {D, C, B, A} = ~(4'b1000);
default: {D, C, B, A} = ~(4'b0000);
endcase
endmodule
| 7.031285 |
module ClkDivider (
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 50000; //f=1kHz f=100MHz/(2*constantNumber)
//localparam constantNumber = 25000000;//f=2Hz f=100MHz/(2*constantNumber)
reg [31:0] count;
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1) count <= 32'b0;
else if (count == constantNumber - 1) count <= 32'b0;
else count <= count + 1;
end
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1) clk_div <= 1'b0;
else if (count == constantNumber - 1) clk_div <= ~clk_div;
else clk_div <= clk_div;
end
endmodule
| 6.643482 |
module top_bcd (
//input [3:0] A, B, C, D,
input [12:0] number,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] A, B, C, D;
bcd bcd (
.number(number),
.thousands(D),
.hundreds(C),
.tens(B),
.ones(A)
);
bcdto7segmentclocked bcdto7segmentclocked (
.A(A),
.B(B),
.C(C),
.D(D),
.reset(reset),
.clk(clk),
.anode(anode),
.seg(seg)
);
endmodule
| 7.367091 |
module bcdto7segmentclocked (
input [3:0] A,
B,
C,
D,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] x;
wire [3:0] an;
wire [1:0] sel;
wire clk_div;
bcdto7segment_dataflow bcdto7segment (
.x(x),
.an(an),
.anode(anode),
.seg(seg)
);
mux16to4 mux16to4 (
.A (A),
.B (B),
.C (C),
.D (D),
.sel(sel),
.S (x)
);
demux4to1 demux4to1 (
.sel(sel),
.A (an[0]),
.B (an[1]),
.C (an[2]),
.D (an[3])
);
counter counter (
.reset(reset),
.clk (clk_div),
.out (sel)
);
ClkDivider ClkDivider (
.clk(clk),
.rst(reset),
.clk_div(clk_div)
);
endmodule
| 7.120176 |
module bcdto7segment_dataflow (
input [3:0] x,
input [3:0] an,
output [3:0] anode,
output reg [6:0] seg
);
//reg [6:0] seg;
assign anode = an;
always @(x or an)
case (x)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
6: seg = 7'b0100000;
7: seg = 7'b0001111;
8: seg = 7'b0000000;
9: seg = 7'b0000100;
default: seg = 7'b0000000;
endcase
endmodule
| 7.120176 |
module mux16to4 (
input [3:0] A,
input [3:0] B,
input [3:0] C,
input [3:0] D,
input [1:0] sel,
output reg [3:0] S
);
always @(A, B, C, D, sel)
case (sel)
0: S = A;
1: S = B;
2: S = C;
3: S = D;
default: S = 0;
endcase
endmodule
| 7.78955 |
module demux4to1 (
input [1:0] sel,
output reg A,
output reg B,
output reg C,
output reg D
);
always @(sel)
case (sel)
0: {D, C, B, A} = ~(4'b0001);
1: {D, C, B, A} = ~(4'b0010);
2: {D, C, B, A} = ~(4'b0100);
3: {D, C, B, A} = ~(4'b1000);
default: {D, C, B, A} = ~(4'b0000);
endcase
endmodule
| 7.031285 |
module ClkDivider (
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 50000; //f=1kHz f=100MHz/(2*constantNumber)
//localparam constantNumber = 25000000;//f=2Hz f=100MHz/(2*constantNumber)
reg [31:0] count;
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1) count <= 32'b0;
else if (count == constantNumber - 1) count <= 32'b0;
else count <= count + 1;
end
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1) clk_div <= 1'b0;
else if (count == constantNumber - 1) clk_div <= ~clk_div;
else clk_div <= clk_div;
end
endmodule
| 6.643482 |
module bcd_7seg (
input [3:0] bcd,
output [6:0] seg
);
reg [6:0] seg1;
assign seg = seg1;
always @(bcd)
case (bcd)
4'b0000: seg1 <= 7'b1000000;
4'b0001: seg1 <= 7'b1111001;
4'b0010: seg1 <= 7'b0100100;
4'b0011: seg1 <= 7'b0110000;
4'b0100: seg1 <= 7'b0011001;
4'b0101: seg1 <= 7'b0010010;
4'b0110: seg1 <= 7'b0000010;
4'b0111: seg1 <= 7'b1111000;
4'b1000: seg1 <= 7'b0000000;
4'b1001: seg1 <= 7'b0010000;
default: seg1 <= 7'b1111111;
endcase
endmodule
| 6.710996 |
module BCD_7seg_100_ca (
shiwei_out,
gewei_out,
num_in
); // 7线数据输入一个100以内的二进制数，输出两个数码管编码
output wire [7:0] shiwei_out, gewei_out;
input [6:0] num_in;
reg [3:0] shiwei_value;
reg [3:0] gewei_value;
always @(num_in) begin
shiwei_value = num_in / 10;
gewei_value = num_in % 10;
end
BCD_7seg_decoder_ca shiweiModule (
shiwei_out,
shiwei_value
);
BCD_7seg_decoder_ca geweiModule (
gewei_out,
gewei_value
);
endmodule
| 7.831039 |
module bcd_8421 (
input wire sys_clk, //系统时钟，频率50MHz
input wire sys_rst_n, //复位信号，低电平有效
input wire [19:0] data, //输入需要转换的数据
output reg [3:0] unit, //个位BCD码
output reg [3:0] ten, //十位BCD码
output reg [3:0] hun, //百位BCD码
output reg [3:0] tho, //千位BCD码
output reg [3:0] t_tho, //万位BCD码
output reg [3:0] h_hun //十万位BCD码
);
//********************************************************************//
//******************** Parameter And Internal Signal *****************//
//********************************************************************//
//reg define
reg [ 4:0] cnt_shift; //移位判断计数器
reg [43:0] data_shift; //移位判断数据寄存器
reg shift_flag; //移位判断标志信号
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//cnt_shift:从0到21循环计数
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_shift <= 5'd0;
else if ((cnt_shift == 5'd21) && (shift_flag == 1'b1)) cnt_shift <= 5'd0;
else if (shift_flag == 1'b1) cnt_shift <= cnt_shift + 1'b1;
else cnt_shift <= cnt_shift;
//data_shift：计数器为0时赋初值，计数器为1~20时进行移位判断操作
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) data_shift <= 44'b0;
else if (cnt_shift == 5'd0) data_shift <= {24'b0, data};
else if ((cnt_shift <= 20) && (shift_flag == 1'b0)) begin
data_shift[23:20] <= (data_shift[23:20] > 4) ? (data_shift[23:20] + 2'd3) : (data_shift[23:20]);
data_shift[27:24] <= (data_shift[27:24] > 4) ? (data_shift[27:24] + 2'd3) : (data_shift[27:24]);
data_shift[31:28] <= (data_shift[31:28] > 4) ? (data_shift[31:28] + 2'd3) : (data_shift[31:28]);
data_shift[35:32] <= (data_shift[35:32] > 4) ? (data_shift[35:32] + 2'd3) : (data_shift[35:32]);
data_shift[39:36] <= (data_shift[39:36] > 4) ? (data_shift[39:36] + 2'd3) : (data_shift[39:36]);
data_shift[43:40] <= (data_shift[43:40] > 4) ? (data_shift[43:40] + 2'd3) : (data_shift[43:40]);
end else if ((cnt_shift <= 20) && (shift_flag == 1'b1)) data_shift <= data_shift << 1;
else data_shift <= data_shift;
//shift_flag：移位判断标志信号，用于控制移位判断的先后顺序
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) shift_flag <= 1'b0;
else shift_flag <= ~shift_flag;
//当计数器等于20时，移位判断操作完成，对各个位数的BCD码进行赋值
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) begin
unit <= 4'b0;
ten <= 4'b0;
hun <= 4'b0;
tho <= 4'b0;
t_tho <= 4'b0;
h_hun <= 4'b0;
end else if (cnt_shift == 5'd21) begin
unit <= data_shift[23:20];
ten <= data_shift[27:24];
hun <= data_shift[31:28];
tho <= data_shift[35:32];
t_tho <= data_shift[39:36];
h_hun <= data_shift[43:40];
end
endmodule
| 7.263611 |
module BCD_8421_BCD_2421 (
a,
y
);
input [3:0] a;
output [3:0] y;
assign y[3] = a[3] & ~a[2] | a[2] & a[1] | a[2] & a[0];
assign y[2] = a[3] & ~a[2] | a[2] & a[1] | a[2] & ~a[1] & ~a[0];
assign y[1] = a[3] & ~a[2] | ~a[3] & ~a[2] & a[1] | a[2] & ~a[1] & a[0];
assign y[0] = ~a[3] & a[0] | a[3] & a[0];
endmodule
| 6.939156 |
module BCD_8421_BCD_3 (
sel,
in,
out
); //selΪѡźţ0Ϊ8421תΪ3룬1Ϊ3ת8421
input [3:0] in;
input sel;
output reg [3:0] out;
always @(*) begin
if (!sel) out = in + 4'b0011;
else out = in - 4'b0011;
end
endmodule
| 6.939156 |
module bcd_adder (
a,
b,
c0,
s,
cout
);
input [3:0] a, b;
input c0;
output [3:0] s;
output cout;
wire [3:0] z, six;
wire temp_cout, o1, o2, waste_cout;
four_bit_add FB1 (
a,
b,
c0,
z,
temp_cout
);
and (o1, z[3], z[2]);
and (o2, z[3], z[1]);
or (cout, o1, o2, temp_cout);
assign six[3] = 1'b0;
assign six[0] = 1'b0;
assign six[1] = cout;
assign six[2] = cout;
four_bit_add FB2 (
six,
z,
0,
s,
waste_cout
);
endmodule
| 6.697199 |
module bcd_adder_4_tb ();
reg [15:0] a;
reg [15:0] b;
reg c_in;
wire [15:0] sum;
wire c_out;
parameter CYCLE = 5'd20;
always #10
a = ((sum[3:0]==4'd9) & (sum[7:4]!=4'd9)) ? (sum + 5'b1_0001 - 5'b0_1010 ) :
((sum[3:0]==4'd9) & (sum[7:4]==4'd9) & (sum[11:8]!=4'd9)) ? (sum + 9'b1_0001_0001 - 9'b0_1010_1010) :
((sum[3:0]==4'd9) & (sum[7:4]==4'd9) & (sum[11:8]==4'd9) & (sum[15:12]!=4'd9)) ? (sum + 13'b1_0001_0001_0001 - 13'b0_1010_1010_1010) :
sum + 1'd1;
initial begin
a = 16'h0000;
b = 16'h0001;
c_in = 1'b0;
#(CYCLE * 100) $stop;
end
bcd_adder_4 bcd_adder_4_test (
.a (a ),
.b (b ),
.c_in (c_in ),
.sum (sum),
.c_out(c_out)
);
endmodule
| 6.561878 |
module bcd_adder_gate_level (
input Cin,
input [3:0] X1,
X0,
Y1,
Y0,
output [3:0] S1,
S0,
output Cout
);
bcd_full_adder_1digit adder0 (
Cin,
X0,
Y0,
S0,
K
);
bcd_full_adder_1digit adder1 (
K,
X1,
Y1,
S1,
Cout
);
endmodule
| 7.300358 |
module bcd_adder_tb ();
reg [3:0] a;
reg [3:0] b;
reg c_in;
wire [3:0] sum;
wire c_out;
parameter CYCLE = 5'd20;
always #10 a = (sum == 4'd9) ? 4'b0 : sum + 1'd1;
initial begin
a = 4'b0000;
b = 4'b0000;
c_in = 1'b0;
#(CYCLE * 50);
$stop;
end
bcd_adder bcd_adder_test (
.a (a ),
.b (b ),
.c_in (c_in ),
.sum (sum),
.c_out(c_out)
);
endmodule
| 6.86161 |
module non_carry_add (
ina,
inb,
sum
);
parameter WIDTH = 10;
input [WIDTH-1:0] ina, inb;
output [WIDTH-1:0] sum;
wire [WIDTH-1:0] sum;
wire [ WIDTH:0] cin;
assign cin[0] = 1'b0;
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : chn
assign sum[i] = ina[i] ^ inb[i] ^ cin[i];
assign cin[i+1] = (ina[i] & inb[i]) | (ina[i] & cin[i]) | (cin[i] & inb[i]);
end
endgenerate
endmodule
| 7.659573 |
modules
module bcd_adj (datai,
datao,
bcd_en,
cin4,
cin8,
cout,
sub);
input [7:0] datai; // in
output [7:0] datao; // out
input bcd_en; // enable bcd adjust
input cin4; // half carry in
input cin8; // carry in
output cout; // carry out
input sub; // subtract flag
wire [7:0] datao;
wire cout;
wire [7:0] b; // adjust value
wire cout4; // half-carry out
wire cin4l; // half-carry in
wire cout8; // adder carry out
wire gnd; // logic zero
wire lo_adj; // 1= low nibble needs to have 6 added to it.
wire hi_adj; // 1= hi nibble needs to have 6 added to it.
wire lo_adj_sub; // 1= low nibble needs to have A added to it.
wire hi_adj_sub; // 1= hi nibble needs to have A added to it.
// -----------ARCHITECTURE---------
// adjust when a-f and BCD adjust is enabled
assign lo_adj = bcd_en & ~sub & (cin4 |
datai[3] & ~(~datai[2] & ~datai[1]));
// adjust when a-f and BCD adjust is enabled
//
//Bug fix: 2000.03.21
// instruction SBC will be wrong
//Original:
//assign lo_adj_sub = bcd_en & sub & datai[3] & ~(~datai[2] & ~datai[1]);
assign lo_adj_sub = bcd_en & sub & ~cin4;
// adjust when a-f and cin4=0 or 9-f when cin4=1 when enabled
assign hi_adj = bcd_en & ~sub & (cin8 |
datai[7] & ~(~cout4 &
~datai[6] & ~datai[5] | cout4 & ~datai[6] & ~datai[5] & ~datai[4]));
// adjust when a-f and BCD adjust is enabled
//Bug fix: 2000.03.21
// instruction SBC will be wrong
//Original:
//assign hi_adj_sub = bcd_en & sub & datai[7] & ~(~datai[6] & ~datai[5]);
assign hi_adj_sub = bcd_en & sub & ~cin8;
assign b[7:4] = hi_adj_sub == 1'b 1 ? 4'b 1010 :
hi_adj == 1'b 1 ? 4'b 0110 :
4'b 0000;
// add 6 for add or A for subtract to the nibble(s) that need adjusting
assign b[3:0] = lo_adj_sub == 1'b 1 ? 4'b 1010 :
lo_adj == 1'b 1 ? 4'b 0110 :
4'b 0000;
assign cout = cin8 | cout8 & ~hi_adj_sub;
// set the carry bit if adjust causes carry out.
assign cin4l = cout4 & ~lo_adj_sub;
// don't carry when adj for sub
// ------Instantiate the 4 bit adder here---------------
assign gnd = 1'b 0;
add4rpl addh (.a(datai[7:4]),
.b(b[7:4]),
.cin(cin4l),
.cout(cout8),
// ------Instantiate the 4 bit adder here---------------
.sum(datao[7:4]));
add4rpl addl (.a(datai[3:0]),
.b(b[3:0]),
// no carry in.
.cin(gnd),
.cout(cout4),
.sum(datao[3:0]));
endmodule
| 7.846843 |
module bcd_adjust (
input wire clk,
reset,
input wire start,
input wire [3:0] bcd6,
bcd5,
bcd4,
bcd3,
bcd2,
bcd1,
bcd0,
output wire [3:0] bcd_out3,
bcd_out2,
bcd_out1,
bcd_out0,
output wire [1:0] decimal_counter,
output reg ready,
done_tick
);
// symbolic state declaration
localparam [1:0] idle = 2'b00, op = 2'b01, done = 2'b10;
// signal declaration
reg [1:0] state_reg, state_next;
reg [27:0] bcd_reg, bcd_next;
reg [1:0] c_reg, c_next;
// body
// FSMD state and data registers
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= idle;
bcd_reg <= 0;
c_reg <= 0;
end else begin
state_reg <= state_next;
bcd_reg <= bcd_next;
c_reg <= c_next;
end
// FSMD next-state logic
always @* begin
// defaults
state_next = state_reg;
ready = 1'b0;
done_tick = 1'b0;
bcd_next = bcd_reg;
c_next = c_reg;
case (state_reg)
idle: begin
ready = 1'b1;
if (start) begin
state_next = op;
bcd_next = {bcd6, bcd5, bcd4, bcd3, bcd2, bcd1, bcd0};
c_next = 0;
end
end
op: begin
if (bcd_reg[27:24] == 0 && c_reg < 3) begin
c_next = c_reg + 1;
bcd_next = bcd_reg << 4;
end else state_next = done;
end
done: begin
done_tick = 1'b1;
state_next = idle;
end
default: state_next = idle;
endcase
end
// output
assign decimal_counter = c_reg;
assign bcd_out3 = bcd_reg[27:24];
assign bcd_out2 = bcd_reg[23:20];
assign bcd_out1 = bcd_reg[19:16];
assign bcd_out0 = bcd_reg[15:12];
endmodule
| 7.51948 |
module bcd_bin #(
parameter SIZE_bcd = 8'd28,
parameter SIZE_bin = 8'd24
) (
input clk,
input rstn,
input [SIZE_bcd-1:0] data_bcd,
output reg [SIZE_bin-1:0] data_bin,
output reg valid
);
reg [7:0] cnt;
reg [SIZE_bcd-1:0] data_bcd_temp;
reg [SIZE_bin-1:0] data_bin_temp;
localparam CYCCLE = SIZE_bcd / 4; //ʮλ
always @(posedge clk) begin
if (!rstn) begin
cnt <= 0;
end else begin
if (cnt > CYCCLE) cnt <= 0;
else cnt <= cnt + 1;
end
end
always @(posedge clk) begin
if (!rstn) begin
valid <= 1'd0;
data_bcd_temp <= 0;
data_bin_temp <= 0;
end else begin
if (cnt == 0) begin
valid <= 1'd0;
data_bcd_temp <= data_bcd;
data_bin_temp <= 0;
end else if (cnt <= CYCCLE) begin
data_bin_temp <= MULTI10(data_bin_temp) +
data_bcd_temp[(SIZE_bcd+3-cnt*4)-:4]; //עλдʾ8'd43-cnt*4ʼ4λ
end else if (cnt == CYCCLE + 1) begin
data_bin <= data_bin_temp;
valid <= 1'd1;
end
end
end
//ӷλƴӣ10--*8+*2
//ע⣺λ
function [SIZE_bin-1:0] MULTI10(input [SIZE_bin-1:0] a);
begin
MULTI10 = {a[SIZE_bin-4 : 0], 3'b000} + {a[SIZE_bin-2 : 0], 1'b0};
end
endfunction
endmodule
| 7.052638 |
module bcd_control (
display1,
display2,
display3,
display4,
sel,
saida
);
input [3:0] display1;
input [3:0] display2;
input [3:0] display3;
input [3:0] display4;
input [1:0] sel;
output reg [3:0] saida;
always @(sel) begin
case (sel)
0: saida = display1;
1: saida = display2;
2: saida = display3;
3: saida = display4;
endcase
end
endmodule
| 6.673665 |
module BCD_Counter (
Clk,
Cin,
Rst_n,
Cout,
q
);
input Clk;
input Cin;
input Rst_n;
output Cout;
output [3:0] q;
reg [3:0] cnt;
always @(posedge Clk or negedge Rst_n) begin
if (Rst_n == 1'b0) cnt <= 4'd0;
else if (Cin == 1'b1) begin
if (cnt == 4'd9) cnt <= 4'd0;
else cnt <= cnt + 1'b1;
end else cnt <= cnt;
end
assign Cout = (Cin == 1'b1 && cnt == 4'd9);
assign q = cnt;
endmodule
| 6.966103 |
module BCD_counter_2bit (
output [3:0] value1,
output [3:0] value0,
output cout,
input [3:0] init1,
input [3:0] init0,
input [3:0] limit1,
input [3:0] limit0,
input clk,
input rst_n,
input en
);
reg [3:0] limit0_temp;
wire carry;
BCD_counter U0 (
value0,
carry,
init0,
limit0_temp,
clk,
rst_n,
en
);
BCD_counter U1 (
value1,
cout,
init1,
limit1,
clk,
rst_n,
carry
);
always @* begin
if (value1 == limit1) limit0_temp = limit0;
else limit0_temp = 4'd9;
end
endmodule
| 6.544536 |
module BCD_counter_4bit (
output [3:0] value3,
output [3:0] value2,
output [3:0] value1,
output [3:0] value0,
input [3:0] init3,
input [3:0] init2,
input [3:0] init1,
input [3:0] init0,
input [3:0] limit3,
input [3:0] limit2,
input [3:0] limit1,
input [3:0] limit0,
input clk,
input rst_n,
input en
);
wire [2:0] carry;
BCD_counter U0 (
value0,
carry[0],
init0,
limit0,
clk,
rst_n,
en
);
BCD_counter U1 (
value1,
carry[1],
init1,
limit1,
clk,
rst_n,
carry[0]
);
BCD_counter U2 (
value2,
carry[2],
init2,
limit2,
clk,
rst_n,
carry[1]
);
BCD_counter U3 (
value3
,,
init3,
limit3,
clk,
rst_n,
carry[2]
);
endmodule
| 7.209232 |
module BCD_Counter_tb;
reg Clk;
reg Cin;
reg Rst_n;
wire Cout;
wire [3:0] q;
BCD_Counter BCD_Counter0 (
.Clk(Clk),
.Cin(Cin),
.Rst_n(Rst_n),
.Cout(Cout),
.q(q)
);
initial Clk = 1'b1;
always #(`clock_period / 2) Clk = ~Clk;
initial begin
Rst_n = 1'b0;
Cin = 1'b0;
#(`clock_period * 200);
Rst_n = 1'b1;
#(`clock_period * 20);
repeat (30) begin
Cin = 1'b1;
#`clock_period;
Cin = 1'b0;
#(`clock_period * 5);
end
#(`clock_period * 20);
$finish;
end
initial begin
$fsdbDumpfile("BCD_Counter");
$fsdbDumpvars;
end
endmodule
| 7.312047 |
module BCD_counter_TOP (
clk_50M,
mode,
BCD_preset,
BCD_out
);
input clk_50M;
input [3:0] mode;
input [7:0] BCD_preset;
output [7:0] BCD_out;
//ʱӷƵģ
wire clk_1s;
clock_division #(
.DIVCLK_CNTMAX(24_999_999)
) my_clock_0 (
.clk_in(clk_50M),
.divclk(clk_1s)
);
//BCDܼ
wire [3:0] BCD_units_preset = BCD_preset[3:0];
wire [3:0] BCD_units_out;
wire bcout_0;
BCD_functional_counter BCD_units (
.clk(clk_1s),
.mode(mode),
.BCD_preset(BCD_units_preset),
.BCD_out(BCD_units_out),
.bcin(1'b1),
.bcout(bcout_0)
);
wire [3:0] BCD_tens_preset = BCD_preset[7:4];
wire [3:0] BCD_tens_out;
BCD_functional_counter BCD_tens (
.clk(clk_1s),
.mode(mode),
.BCD_preset(BCD_tens_preset),
.BCD_out(BCD_tens_out),
.bcin(bcout_0),
.bcout()
);
assign BCD_out = {BCD_tens_out, BCD_units_out};
endmodule
| 6.503863 |
module bcd_decoder (
input [3:0] D,
output reg [6:0] out
);
always @(D) begin
case (D)
4'b0000: out = 7'b1000000; //0
4'b0001: out = 7'b1111001; //1
4'b0010: out = 7'b0100100; //2
4'b0011: out = 7'b0110000; //3
4'b0100: out = 7'b0011001; //4
4'b0101: out = 7'b0010010; //5
4'b0110: out = 7'b0000010; //6
4'b0111: out = 7'b1111000; //7
4'b1000: out = 7'b0000000; //8
4'b1001: out = 7'b0010000; //9
default: out = 7'b1111111; //blank
endcase
end
endmodule
| 7.18658 |
module BCD_decoder3dig (
input [7:0] in,
output [3:0] dig1,
output [3:0] dig2,
output [3:0] dig3
);
wire [7:0] tens;
wire [7:0] hundreds;
assign dig1 = in % 10;
assign tens = in / 10;
assign dig2 = tens % 10;
assign hundreds = in / 100;
assign dig3 = hundreds % 10;
endmodule
| 6.537036 |
module BCD_decoder3dig_test;
reg [7:0] in;
wire [3:0] dig1;
wire [3:0] dig2;
wire [3:0] dig3;
BCD_decoder3dig DUT (
.in (in),
.dig1(dig1),
.dig2(dig2),
.dig3(dig3)
);
initial begin
in = 0;
#40;
end
initial begin
#100;
in = 123;
#100;
in = 145;
#100;
in = 23;
#100;
in = 4;
#100;
$stop;
end
endmodule
| 6.537036 |
module BCD_decoder_modified (
Count, // Display output 0-9 with 4 bits binary input using case
Output
);
input [3:0] Count;
integer i;
output reg [0:6] Output;
always @(Count)
// 0-a, 1-b, 2-c, 3-d, 4-e, 5-f, 6-g
case (Count)
4'b0000: Output[0:6] = 7'b0000001; // 0
4'b0001: Output[0:6] = 7'b1001111; // 1
4'b0010: Output[0:6] = 7'b0010010; // 2
4'b0011: Output[0:6] = 7'b0000110; // 3
4'b0100: Output[0:6] = 7'b1001100; // 4
4'b0101: Output[0:6] = 7'b0100100; // 5
4'b0110: Output[0:6] = 7'b0100000; // 6
4'b0111: Output[0:6] = 7'b0001111; // 7
4'b1000: Output[0:6] = 7'b0000000; // 8
4'b1001: Output[0:6] = 7'b0001100; // 9
endcase
endmodule
| 6.601495 |
module bcd_decorder0 (
binary,
hex
);
input [7:0] binary;
output reg [6:0] hex;
reg binary1;
always @(*) begin
case (binary)
8'b0: hex = ~(8'b0111111);
8'd1: hex = ~(8'b0000110);
8'd2: hex = ~(8'b1011011);
8'd3: hex = ~(8'b1001111);
8'd4: hex = ~(8'b1100110);
8'd6: hex = ~(8'b1111101);
8'd7: hex = ~(8'b0000111);
8'd8: hex = ~(8'b1111111);
8'd9: hex = ~(8'b1101111);
default: hex = ~(8'b1000000);
endcase
end
endmodule
| 7.021072 |
module bcd_digit_incrementor_tb;
// signal declaration
reg [3:0] bcd_in;
reg inc;
wire [3:0] bcd_out;
wire carry;
// instance of digit incrementor
bcd_digit_incrementor inc0 (
.bcd_in(bcd_in),
.inc(inc),
.bcd_out(bcd_out),
.carry(carry)
);
// test vector
initial begin
inc = 1'b1;
for (bcd_in = 0; bcd_in < 10; bcd_in = bcd_in + 1) begin
#5;
end
$stop;
end
endmodule
| 7.096657 |
module bcd_digit_incrementor (
input wire [3:0] bcd_in,
input wire inc,
output reg [3:0] bcd_out,
output reg carry
);
always @* begin
if (inc) begin
if (bcd_in == 4'b1001) begin
bcd_out = 4'b0000;
carry = 1'b1;
end else begin
bcd_out = bcd_in + 1;
carry = 1'b0;
end
end else begin
bcd_out = bcd_in;
carry = 1'b0;
end
end
endmodule
| 7.096657 |
module BCD_downcounter (
input clk, //时钟输入
input rst, //异步复位输入
input bin, //借位输入
input preset, //同步预置数输入
input [3:0] BCD_i, //BCD码计数输入
output [3:0] BCD_o, //BCD码计数输出
output bout //借位输出
);
reg [3:0] cnt;
always @(posedge clk or posedge rst) begin
if (rst) cnt <= 0;
else if (preset) cnt <= BCD_i;
else if (bin) begin
if (cnt == 4'd0) cnt <= 4'd9;
else cnt <= cnt - 1'b1;
end
end
assign BCD_o = cnt;
assign bout = bin && (cnt == 4'd0); //向下计数至0时同步输出bout信号
endmodule
| 6.997209 |
module bcd_fib_test (
input wire clk,
reset,
input wire btn,
input wire [7:0] sw,
output wire [3:0] an,
output wire [7:0] sseg
);
// signal declaration
wire start;
wire [3:0] bcd3, bcd2, bcd1, bcd0;
// debouncing circuit
debounce db_unit (
.clk(clk),
.reset(reset),
.sw(btn),
.db_level(),
.db_tick(start)
);
// bcd fib circuit
bcd_fib bcd_fib_unit (
.clk(clk),
.reset(reset),
.start(start),
.bcd1(sw[7:4]),
.bcd0(sw[3:0]),
.out_bcd3(bcd3),
.out_bcd2(bcd2),
.out_bcd1(bcd1),
.out_bcd0(bcd0)
);
// display unit
disp_hex_mux dp_unit (
.clk(clk),
.reset(reset),
.hex3(bcd3),
.hex2(bcd2),
.hex1(bcd1),
.hex0(bcd0),
.dp_in(4'b1111),
.an(an),
.sseg(sseg)
);
endmodule
| 7.426995 |
module BCD_functional_counter (
input clk, //ʱź
input [3:0] mode, //ģʽź
input [3:0] BCD_preset, //Ԥź
output [3:0] BCD_out, //4bitBCD
input bcin, //ڼź
output reg bcout //ڼź
);
parameter preset = 4'b0001;
parameter clear = 4'b0010;
parameter up = 4'b0100;
parameter down = 4'b1000;
reg [3:0] cnt = 0;
//BCD
always @(posedge clk)
case (mode)
preset: cnt <= BCD_preset;
clear: cnt <= 0;
up:
if (bcin) begin
if (cnt == 4'd9) cnt <= 0;
else cnt <= cnt + 1'b1;
end
down:
if (bcin) begin
if (cnt == 4'd0) cnt <= 4'd9;
else cnt <= cnt - 1'b1;
end
default: cnt <= cnt;
endcase
assign BCD_out = cnt; //BCDֵ
//źţλ/λ
always @(*) begin
if (mode == up) bcout = bcin && (cnt == 4'd9);
else if (mode == down) bcout = bcin && (cnt == 4'd0);
else bcout = 1'b0;
end
endmodule
| 7.869065 |
module BCD_hex (
Output,
getValue
);
input [3:0] getValue;
output reg [6:0] Output;
always @(getValue) begin
case (getValue)
4'b0000: Output = 7'b1000000; //0
4'b0001: Output = 7'b1111001; //1
4'b0010: Output = 7'b0100100; //2
4'b0011: Output = 7'b0110000; //3
4'b0100: Output = 7'b0011001; //4
4'b0101: Output = 7'b0010010; //5
4'b0110: Output = 7'b0000010; //6
4'b0111: Output = 7'b1111000; //7
4'b1000: Output = 7'b0000000; //8
4'b1001: Output = 7'b0010000; //9
4'b1010: Output = 7'b0001000; //A
4'b1011: Output = 7'b0000011; //B
4'b1100: Output = 7'b1000110; //C
4'b1101: Output = 7'b0100001; //D
4'b1110: Output = 7'b0000110; //E
4'b1111: Output = 7'b0001110; //F
default Output = 7'b1111111;
endcase
end
endmodule
| 6.920147 |
module bcd_incrementor_test (
input wire clk,
input wire [11:0] sw,
output wire [ 7:0] sseg,
output wire [ 3:0] an,
output wire led_carry
);
// signal declaration
wire [3:0] out0, out1, out2;
wire [7:0] led0, led1, led2, led3;
// instance of 3-digit incrementor
bcd_3digit_incrementor bdc_incrementor_unit (
.digit0(sw[3:0]),
.digit1(sw[7:4]),
.digit2(sw[11:8]),
.out0 (out0),
.out1 (out1),
.out2 (out2),
.carry (led_carry)
);
// instances of bcd decoder
bcd_to_sseg bcd_to_sseg_unit0 (
.bcd (out0),
.dp (1'b1),
.sseg(led0)
);
bcd_to_sseg bcd_to_sseg_unit1 (
.bcd (out1),
.dp (1'b1),
.sseg(led1)
);
bcd_to_sseg bcd_to_sseg_unit2 (
.bcd (out2),
.dp (1'b1),
.sseg(led2)
);
// blank rightmost led
assign led3 = 8'b11111111;
// instance of display mux
disp_mux disp_unit (
.clk(clk),
.reset(1'b0),
.in0(led0),
.in1(led1),
.in2(led2),
.in3(led3),
.an(an),
.sseg(sseg)
);
endmodule
| 8.549542 |
module BCD_LED1 (
in,
LED
);
output [6:0] LED;
reg [6:0] LED;
input [4:0] in;
always @(in)
case (in)
0: LED = 7'b0000001;
1: LED = 7'b1001111;
2: LED = 7'b0010010;
3: LED = 7'b0000110;
4: LED = 7'b1001100;
5: LED = 7'b0100100;
6: LED = 7'b1100000;
7: LED = 7'b0001111;
8: LED = 7'b0000000;
9: LED = 7'b0001100;
10: LED = 7'b1111111;
11: LED = 7'b1111001; //l
12: LED = 7'b1100010; //o
13: LED = 7'b0100100; //S
14: LED = 7'b1110000; //t
15: LED = 7'b0011000; //p
16: LED = 7'b0001000; //A
17: LED = 7'b1111010; //r
18: LED = 7'b1100011; //u
19: LED = 7'b1101010; //n
20: LED = 7'b0110001; //C
default: LED = 7'b1111111;
endcase
endmodule
| 7.294759 |
module BCD_n (
input wire [3:0] number,
output wire [6:0] digit_n
);
wire [6:0] digit;
BCD bcd (
.number(number[3:0]),
.digit (digit[6:0])
);
assign digit_n = ~digit[6:0];
endmodule
| 7.322114 |
module bcd_seg_disp (
input wire [3:0] in,
input wire max,
output reg [6:0] out
);
always @(*) begin
//如果计满信号为高电平，则直接输出9
if (max) begin
out <= 7'b0010000;
end //输入0-9十种BCD码判断，并输出对应的七段数码管显示信号
else begin
case (in)
4'b0000: out <= 7'b1000000;
4'b0001: out <= 7'b1111001;
4'b0010: out <= 7'b0100100;
4'b0011: out <= 7'b0110000;
4'b0100: out <= 7'b0011001;
4'b0101: out <= 7'b0010010;
4'b0110: out <= 7'b0000010;
4'b0111: out <= 7'b1111000;
4'b1000: out <= 7'b0000000;
4'b1001: out <= 7'b0010000;
default: out <= 7'b1111111;
endcase
end
end
endmodule
| 7.59162 |
module bcd_subtracter (
input [3:0] X1,
X0,
Y1,
Y0,
output [3:0] S1,
S0,
output Cout
);
wire [3:0] Z0, Z1;
nines_complement nc0 (
Y0,
Z0
);
nines_complement nc1 (
Y1,
Z1
);
bcd_adder_gate_level adder (
1,
X1,
X0,
Z1,
Z0,
S1,
S0,
Cout
);
endmodule
| 6.563068 |
module bcd_to_7seg (
input [3:0] BCD,
output reg [7:0] s
);
always @(BCD) begin
case (BCD)
0: s = 8'b10001000;
1: s = 8'b11101101;
2: s = 8'b10100010;
3: s = 8'b10100100;
4: s = 8'b11000101;
5: s = 8'b10010100;
6: s = 8'b10010000;
7: s = 8'b10101101;
8: s = 8'b10000000;
9: s = 8'b10000100;
default: s = 8'b01111111;
endcase
end
endmodule
| 7.217745 |
module BCD_TO_7SEGMENT_1BIT (
BCD,
A,
B,
C,
D,
E,
F,
G
);
input [3:0] BCD;
output A, B, C, D, E, F, G;
reg [6:0] DECODE;
always @(BCD) begin
case (BCD)
4'b0000: DECODE <= 7'b1111110; //segment 0
4'b0001: DECODE <= 7'b0110000; //segment 1
4'b0010: DECODE <= 7'b1101101; //segment 2
4'b0011: DECODE <= 7'b1111001; //segment 3
4'b0100: DECODE <= 7'b0110011; //segment 4
4'b0101: DECODE <= 7'b1011011; //segment 5
4'b0110: DECODE <= 7'b1011111; //segment 6
4'b0111: DECODE <= 7'b1110010; //segment 7
4'b1000: DECODE <= 7'b1111111; //segment 8
4'b1001: DECODE <= 7'b1111011; //segment 9
default: DECODE <= 7'b0000000; //NULL
endcase
end
assign {A, B, C, D, E, F, G} = DECODE;
endmodule
| 6.575047 |
module bcd_to_7_segment (
//----------------Input ports------------------------------
input wire [3:0] hundreds,
input wire [3:0] tens,
input wire [3:0] ones,
//----------------Output ports-----------------------------
output reg [6:0] display_0,
output reg [6:0] display_1,
output reg [6:0] display_2
);
always @(hundreds or tens or ones) begin
case (ones)
4'h0: display_0 <= 7'b1000000; //to display 0
4'h1: display_0 <= 7'b1111001; //to display 1
4'h2: display_0 <= 7'b0100100; //to display 2
4'h3: display_0 <= 7'b0110000; //to display 3
4'h4: display_0 <= 7'b0011001; //to display 4
4'h5: display_0 <= 7'b0010010; //to display 5
4'h6: display_0 <= 7'b0000010; //to display 6
4'h7: display_0 <= 7'b1111000; //to display 7
4'h8: display_0 <= 7'b0000000; //to display 8
4'h9: display_0 <= 7'b0010000; //to display 9
default: display_0 <= 7'b0111111; //to display -
endcase
case (tens)
4'h0: display_1 <= 7'b1000000; //to display 0
4'h1: display_1 <= 7'b1111001; //to display 1
4'h2: display_1 <= 7'b0100100; //to display 2
4'h3: display_1 <= 7'b0110000; //to display 3
4'h4: display_1 <= 7'b0011001; //to display 4
4'h5: display_1 <= 7'b0010010; //to display 5
4'h6: display_1 <= 7'b0000010; //to display 6
4'h7: display_1 <= 7'b1111000; //to display 7
4'h8: display_1 <= 7'b0000000; //to display 8
4'h9: display_1 <= 7'b0010000; //to display 9
default: display_1 <= 7'b0111111; //to display -
endcase
case (hundreds)
4'h0: display_2 <= 7'b1000000; //to display 0
4'h1: display_2 <= 7'b1111001; //to display 1
4'h2: display_2 <= 7'b0100100; //to display 2
4'h3: display_2 <= 7'b0110000; //to display 3
4'h4: display_2 <= 7'b0011001; //to display 4
4'h5: display_2 <= 7'b0010010; //to display 5
4'h6: display_2 <= 7'b0000010; //to display 6
4'h7: display_2 <= 7'b1111000; //to display 7
4'h8: display_2 <= 7'b0000000; //to display 8
4'h9: display_2 <= 7'b0010000; //to display 9
default: display_2 <= 7'b0111111; //to display -
endcase
end
endmodule
| 6.802975 |
module decoder_hex_10 (
input [3:0] bcd,
output reg [6:0] H,
output reg E
);
always @(bcd)
if (bcd > 4'b1001) begin
E = 1;
end else begin
E = 0;
case (bcd)
0: H = 7'b0000001;
1: H = 7'b1001111;
2: H = 7'b0010010;
3: H = 7'b0000110;
4: H = 7'b1001100;
5: H = 7'b0100100;
6: H = 7'b0100000;
7: H = 7'b0001111;
8: H = 7'b0000000;
9: H = 7'b0000100;
default: H = 7'b1111111;
endcase
end
endmodule
| 7.325232 |
module BCD_to_DEC (
input [7:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
HEX1
);
assign LEDR[7:0] = SW[7:0];
decoder_hex_10 decoder1 (
SW[3:0],
HEX0,
LEDR[8]
);
decoder_hex_10 decoder2 (
SW[7:4],
HEX1,
LEDR[9]
);
endmodule
| 8.654396 |
module bcd_to_dec_2_bits (
input [3:0] a0,
a1,
output reg error_a0,
error_a1,
output [6:0] o_a0,
o_a1
);
always @(a0 or a1) begin
error_a0 = 0;
error_a1 = 0;
if (a0 > 4'b1001) error_a0 = 1;
if (a1 > 4'b1001) error_a1 = 1;
end
decoder_hex_10 d0 (
a0[3:0],
o_a0
);
decoder_hex_10 d1 (
a1[3:0],
o_a1
);
endmodule
| 8.887649 |
module bcd_to_dec_2_bits_on_board (
input [7:0] SW,
output [9:0] LEDR,
output [6:0] HEX0,
HEX1
);
assign LEDR[7:0] = SW;
bcd_to_dec_2_bits(
SW[3:0], SW[7:4], LEDR[8], LEDR[9], HEX0, HEX1
);
endmodule
| 8.887649 |
module decoder_hex_16 (
input [3:0] bcd,
output reg [0:6] H
);
always @(bcd)
case (bcd)
0: H = 7'b0000001;
1: H = 7'b1001111;
2: H = 7'b0010010;
3: H = 7'b0000110;
4: H = 7'b1001100;
5: H = 7'b0100100;
6: H = 7'b0100000;
7: H = 7'b0001111;
8: H = 7'b0000000;
9: H = 7'b0000100;
10: H = 7'b0001000;
11: H = 7'b1100000;
12: H = 7'b0110001;
13: H = 7'b1000010;
14: H = 7'b0110000;
15: H = 7'b0111000;
default: H = 7'b1111111;
endcase
endmodule
| 7.325232 |
module BCD_to_HEX (
input [7:0] SW,
output [0:6] HEX0,
HEX1
);
decoder_hex_16 decoder1 (
SW[3:0],
HEX0
);
decoder_hex_16 decoder2 (
SW[7:4],
HEX1
);
endmodule
| 7.326311 |
module BCD_to_LedBit (
input [3:0] BCD,
input Point, //暂未使用小数点
output reg [7:0] LedBit
);
/************************************************************************************************************************
*BCD码译成数码管断码
*************************************************************************************************************************/
always @(*)
case (BCD)
4'd0: LedBit = 8'h3f;
4'd1: LedBit = 8'h6;
4'd2: LedBit = 8'h5b;
4'd3: LedBit = 8'h4f;
4'd4: LedBit = 8'h66;
4'd5: LedBit = 8'h6d;
4'd6: LedBit = 8'h7d;
4'd7: LedBit = 8'h7;
4'd8: LedBit = 8'h7f;
4'd9: LedBit = 8'h6f;
default: LedBit = 8'h3f;
endcase
endmodule
| 6.809166 |
module bcd_to_segment7 (
input [3:0] bcd,
output reg [6:0] seg
);
always @(bcd) begin
case (bcd)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
6: seg = 7'b0100000;
7: seg = 7'b0001111;
8: seg = 7'b0000000;
9: seg = 7'b0000100;
// when the bcd digit is not a decimal number switch off the display
default: seg = 7'b1111111;
endcase
end
endmodule
| 8.172879 |
module bcd_to_sev (
hex,
led
);
input [3:0] hex;
output reg [1:7] led;
always @(hex) //a four bit input is given and a 7 line output
case (hex) //is obtained for 7 segment display
4'b0000: led = 7'b1111110; //input=0
4'b0001: led = 7'b0110000; //input=1
4'b0010: led = 7'b1101101; //input=2
4'b0011: led = 7'b1111001; //input=3
4'b0100: led = 7'b0110011; //input=4
4'b0101: led = 7'b1011011; //input=5
4'b0110: led = 7'b1011111; //input=6
4'b0111: led = 7'b1110000; //input=7
4'b1000: led = 7'b1111111; //input=8
4'b1001: led = 7'b1111011; //input=9
default: led = 7'b0000000;
endcase
endmodule
| 8.563529 |
module bcd_to_seven (
hex,
led
);
input [3:0] hex;
output reg [1:7] led;
always @(hex) //a four bit input is given and a 7 line output
case (hex) //is obtained for 7 segment display
4'b0000: led = 7'b1111110; //input=0
4'b0001: led = 7'b0110000; //input=1
4'b0010: led = 7'b1101101; //input=2
4'b0011: led = 7'b1111001; //input=3
4'b0100: led = 7'b0110011; //input=4
4'b0101: led = 7'b1011011; //input=5
4'b0110: led = 7'b1011111; //input=6
4'b0111: led = 7'b1110000; //input=7
4'b1000: led = 7'b1111111; //input=8
4'b1001: led = 7'b1111011; //input=9
4'b1010: led = 7'b1110111; //input=10,output=A
4'b1011: led = 7'b0011111; //input=11,output=b
4'b1100: led = 7'b1001110; //input=12,output=C
4'b1101: led = 7'b0111101; //input=13,output=d
4'b1110: led = 7'b1001111; //input=14,output=E
4'b1111: led = 7'b1000111; //input=15,output=F
default: led = 7'b0000000;
endcase
endmodule
| 8.224997 |
module bcd_to_sev_seg (
bcd,
seven_seg
);
input [3:0] bcd;
output reg [0:6] seven_seg;
always @* begin
case (bcd)
4'b0000: begin
seven_seg = ~7'b1111110;
end
4'b0001: begin
seven_seg = ~7'b0110000;
end
4'b0010: begin
seven_seg = ~7'b1101101;
end
4'b0011: begin
seven_seg = ~7'b1111001;
end
4'b0100: begin
seven_seg = ~7'b0110011;
end
4'b0101: begin
seven_seg = ~7'b1011011;
end
4'b0110: begin
seven_seg = ~7'b1011111;
end
4'b0111: begin
seven_seg = ~7'b1110000;
end
4'b1000: begin
seven_seg = ~7'b1111111;
end
4'b1001: begin
seven_seg = ~7'b1110011;
end
4'b1010: begin
seven_seg = ~7'b1111101;
end
4'b1011: begin
seven_seg = ~7'b0011111;
end
4'b1100: begin
seven_seg = ~7'b1001110;
end
4'b1101: begin
seven_seg = ~7'b0111101;
end
4'b1110: begin
seven_seg = ~7'b1101111;
end
4'b1111: begin
seven_seg = ~7'b1000111;
end
default: begin
seven_seg = ~7'b0000000;
end
endcase
end
endmodule
| 6.935241 |
module bcd_to_sev_seg (
bcd,
seven_seg
);
input [3:0] bcd;
output reg [0:6] seven_seg;
always @* begin
case (bcd)
4'b0000: begin
seven_seg = ~7'b1111110;
end
4'b0001: begin
seven_seg = ~7'b0110000;
end
4'b0010: begin
seven_seg = ~7'b1101101;
end
4'b0011: begin
seven_seg = ~7'b1111001;
end
4'b0100: begin
seven_seg = ~7'b0110011;
end
4'b0101: begin
seven_seg = ~7'b1011011;
end
4'b0110: begin
seven_seg = ~7'b1011111;
end
4'b0111: begin
seven_seg = ~7'b1110000;
end
4'b1000: begin
seven_seg = ~7'b1111111;
end
4'b1001: begin
seven_seg = ~7'b1110011;
end
4'b1010: begin
seven_seg = ~7'b1110111;
end //A
4'b1011: begin
seven_seg = ~7'b0011111;
end //B
4'b1100: begin
seven_seg = ~7'b1001110;
end //C
4'b1101: begin
seven_seg = ~7'b0111101;
end //D
4'b1110: begin
seven_seg = ~7'b1001111;
end //E
4'b1111: begin
seven_seg = ~7'b1000111;
end //F
default: begin
seven_seg = ~7'b0000000;
end
endcase
end
endmodule
| 6.935241 |
module bcd_to_sseg (
input wire [3:0] bcd,
input wire dp,
output reg [7:0] sseg // ouput active low
);
always @* begin
case (bcd)
4'h0: sseg[6:0] = 7'b0000001;
4'h1: sseg[6:0] = 7'b1001111;
4'h2: sseg[6:0] = 7'b0010010;
4'h3: sseg[6:0] = 7'b0000110;
4'h4: sseg[6:0] = 7'b1001100;
4'h5: sseg[6:0] = 7'b0100100;
4'h6: sseg[6:0] = 7'b0100000;
4'h7: sseg[6:0] = 7'b0001111;
4'h8: sseg[6:0] = 7'b0000000;
4'h9: sseg[6:0] = 7'b0000100;
default: sseg[6:0] = 7'b1001111; // error, not BCD
endcase
sseg[7] = dp;
end
endmodule
| 7.184267 |
module tb_bcd_updown ();
wire [7:0] count;
reg clock, reset, control;
bcd_updown uut (
count,
clock,
reset,
control
);
initial begin
#00 clock = 1'b0;
forever #10 clock = ~clock;
end
initial begin
#00 reset = 1'b1;
control = 1'b0;
#10 reset = 1'b0;
#10 reset = 1'b1;
#1000 control = 1'b1;
#1000 reset = 1'b0;
#10 reset = 1'b1;
#1000 $finish;
end
initial begin
$dumpfile("bcd_updown.vcd");
$dumpvars;
end
endmodule
| 7.263313 |
module bcd_updown (
count,
clock,
reset,
control
);
output reg [7:0] count;
input wire clock, reset, control;
//Negative Edge Triggered Clock and Active Low Asynchronous Reset
always @(negedge clock or negedge reset)
if (reset == 0) count <= 8'b0000_0000;
else if (control == 1) //UP CONDITION
if (count == 8'b0101_1001) count <= 8'b0000_0000;
else if (count[3:0] < 4'b1001) count <= count + 1;
else begin
count[7:4] <= count[7:4] + 1;
count[3:0] <= 4'b0000;
end
else if (control == 0) //DOWN CONDITION
if (count == 8'b0000_0000) count <= 8'b0101_1001;
else if (count[3:0] > 4'b0000) count <= count - 1;
else begin
count[7:4] <= count[7:4] - 1;
count[3:0] <= 4'b1001;
end
endmodule
| 6.891395 |
module bch3d_128_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:127] DATA_OUT;
reg [0:144] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
bch3d_128_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),
.i_code(CODE_IN),
.o_data(DATA_OUT),
.o_valid(VALID_OUT),
.o_err_corr(ERR_CORR),
.o_err_detec(ERR_DET),
.o_err_fatal(ERR_FATAL)
);
//-------- CLOCKING SETUP -----//
initial clk_drv = 1'b0; // set drive clock to 0
always #5 clk_drv = ~clk_drv; //clock period = 2x5=10ns
initial begin // ENABLE control
EN = 1'b1;
#110 EN = ~EN;
end
initial begin
rst_n = 0;
#5 rst_n = 1;
end
//--- DATA DRIVER ------//
initial begin
CODE_IN = 0; // no err
#10 CODE_IN = 145'h1000; // 1 err
#10 CODE_IN = 145'h50000; // 2e
#10 CODE_IN = 145'h80000; // 1 err
#10 CODE_IN = 145'h1; // 1e, for appending bits, it is the parity err
#10 CODE_IN = 145'ha000; // 2e
#10 CODE_IN = 145'hb0000; // 3err
end
//------- SYSTEM TASKS ----//
initial $monitor($time, " data_out = %b ", DATA_OUT);
initial #120 $finish;
endmodule
| 7.166673 |
module bch3d_64_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:63] DATA_OUT;
reg [0:78] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
bch3d_64_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),
.i_code(CODE_IN),
.o_data(DATA_OUT),
.o_valid(VALID_OUT),
.o_err_corr(ERR_CORR),
.o_err_detec(ERR_DET),
.o_err_fatal(ERR_FATAL)
);
//-------- CLOCKING SETUP -----//
initial clk_drv = 1'b0; // set drive clock to 0
always #5 clk_drv = ~clk_drv; //clock period = 2x5=10ns
initial begin // ENABLE control
EN = 1'b1;
#110 EN = ~EN;
end
initial begin
rst_n = 0;
#5 rst_n = 1;
end
//--- DATA DRIVER ------//
initial begin
CODE_IN = 0; // no err
#10 CODE_IN = 79'h1000; // 1 err
#10 CODE_IN = 79'h50000; // 2e
#10 CODE_IN = 79'h80000; // 1 err
#10 CODE_IN = 79'h1; // 1e, for appending bits, it is the parity err
#10 CODE_IN = 79'ha000; // 2e
#10 CODE_IN = 79'hb0000; // 3err
end
//------- SYSTEM TASKS ----//
initial $monitor($time, " data_out = %b ", DATA_OUT);
initial #120 $finish;
endmodule
| 7.159828 |
module bch_128_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:127] DATA_OUT;
reg [0:143] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
bch_128_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),
.i_code(CODE_IN),
.o_data(DATA_OUT),
.o_valid(VALID_OUT),
.o_err_corr(ERR_CORR),
.o_err_detec(ERR_DET),
.o_err_fatal(ERR_FATAL)
);
//-------- CLOCKING SETUP -----//
initial clk_drv = 1'b0; // set drive clock to 0
always #5 clk_drv = ~clk_drv; //clock period = 2x5=10ns
initial begin // ENABLE control
EN = 1'b1;
#110 EN = ~EN;
end
initial begin
rst_n = 0;
#5 rst_n = 1;
end
//--- DATA DRIVER ------//
initial begin
CODE_IN = 0; // no err
#10 CODE_IN = 144'h1000; // 1 err
#10 CODE_IN = 144'h50000; // 2e
#10 CODE_IN = 144'h80000; // 1 err
#10 CODE_IN = 144'h1; // 1e, for appending bits, it is the parity err
#10 CODE_IN = 144'ha000; // 2e
#10 CODE_IN = 144'hb0000; // 3err
end
//------- SYSTEM TASKS ----//
initial $monitor($time, " data_out = %b ", DATA_OUT);
initial #120 $finish;
endmodule
| 7.075573 |
module bch_64_dec_tb;
//------ SIGNALS -----
reg clk_drv;
reg rst_n;
wire [0:63] DATA_OUT;
reg [0:77] CODE_IN;
wire VALID_OUT;
reg EN;
wire ERR_DET;
wire ERR_CORR;
wire ERR_FATAL;
//------INSTANTIATE MODULE -----
bch_64_dec UUT (
.clk(clk_drv),
.reset_n(rst_n),
.enable(EN),
.i_code(CODE_IN),
.o_data(DATA_OUT),
.o_valid(VALID_OUT),
.o_err_corr(ERR_CORR),
.o_err_detec(ERR_DET),
.o_err_fatal(ERR_FATAL)
);
//-------- CLOCKING SETUP -----//
initial clk_drv = 1'b0; // set drive clock to 0
always #5 clk_drv = ~clk_drv; //clock period = 2x5=10ns
initial begin // ENABLE control
EN = 1'b1;
#110 EN = ~EN;
end
initial begin
rst_n = 0;
#5 rst_n = 1;
end
//--- DATA DRIVER ------//
initial begin
CODE_IN = 0; // no err
#10 CODE_IN = 78'h1000; // 1 err
#10 CODE_IN = 78'h50000; // 2e
#10 CODE_IN = 78'h80000; // 1 err
#10 CODE_IN = 78'h1; // 1e, for appending bits, it is the parity err
#10 CODE_IN = 78'ha000; // 2e
#10 CODE_IN = 78'hb0000; // 3err
end
//------- SYSTEM TASKS ----//
initial $monitor($time, " data_out = %b ", DATA_OUT);
initial #120 $finish;
endmodule
| 7.168894 |
module bch_blank_ecc #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* First cycle */
input ce, /* Accept input word/cycle output word */
output [BITS-1:0] xor_out,
output first, /* First output cycle */
output last /* Last output cycle */
);
`include "bch.vh"
`include "bch_encode.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam EB = `BCH_ECC_BITS(P);
localparam ECC_WORDS = (EB + BITS - 1) / BITS;
localparam [EB-1:0] ENC = encoder_poly(0);
if (PIPELINE_STAGES > 1) blank_ecc_only_supports_1_pipeline_stage u_beos1ps ();
function [ECC_WORDS*BITS-1:0] erased_ecc;
input dummy;
reg [EB-1:0] lfsr;
begin
lfsr = 0;
repeat (`BCH_DATA_BITS(P)) lfsr = (lfsr << 1) ^ (lfsr[EB-1] ? 0 : ENC);
erased_ecc = ~(lfsr << (ECC_WORDS * BITS - EB));
end
endfunction
localparam [ECC_WORDS*BITS-1:0] ERASED_ECC = erased_ecc(0);
wire _last;
if (ECC_WORDS == 1) begin
assign _last = start;
assign xor_out = ERASED_ECC;
end else if (ECC_WORDS == 2) begin
reg start0 = 0;
always @(posedge clk) begin
if (start) start0 <= #TCQ start;
else if (ce) start0 <= #TCQ 0;
end
assign _last = start0;
if (PIPELINE_STAGES > 0) begin
assign xor_out = start0 ? ERASED_ECC[BITS+:BITS] : ERASED_ECC[0+:BITS];
end else assign xor_out = start ? ERASED_ECC[BITS+:BITS] : ERASED_ECC[0+:BITS];
end else begin
reg [ (ECC_WORDS-1)*BITS-1:0] ecc_xor = ERASED_ECC;
wire [$clog2(ECC_WORDS+1)-1:0] count;
assign _last = count == 0;
counter #(ECC_WORDS, ECC_WORDS - 2, -1) u_counter (
.clk(clk),
.reset(start),
.ce(ce),
.count(count)
);
if (PIPELINE_STAGES > 0) begin
/* Add registered outputs to distributed RAM */
reg [BITS-1:0] xor_bits = ERASED_ECC[(ECC_WORDS-1)*BITS+:BITS];
always @(posedge clk) begin
if (start) xor_bits <= #TCQ ERASED_ECC[(ECC_WORDS-1)*BITS+:BITS];
else if (ce) xor_bits <= #TCQ ecc_xor[count*BITS+:BITS];
end
assign xor_out = xor_bits;
end else
assign xor_out = start ? ERASED_ECC[(ECC_WORDS-1)*BITS+:BITS] : ecc_xor[count*BITS+:BITS];
end
pipeline_ce #(PIPELINE_STAGES > 0) u_control_pipeline[1:0] (
.clk(clk),
.ce (ce || start),
.i ({start, _last}),
.o ({first, last})
);
endmodule
| 6.875218 |
module bch_chien #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
/*
* For multi-bit output, Only implement every Nth register. Use async
* logic to fill in the remaining values.
*/
parameter REG_RATIO = BITS > 8 ? 8 : BITS
) (
input clk,
input start,
input [`BCH_SIGMA_SZ(P)-1:0] sigma,
output first, /* First valid output data */
output [`BCH_CHIEN_SZ(P)*BITS-1:0] chien
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam T = `BCH_T(P);
localparam SKIP = `BCH_K(P) - `BCH_DATA_BITS(P);
if (REG_RATIO > BITS) chien_reg_ratio_must_be_less_than_or_equal_to_bits u_crrmbltoeqb ();
genvar i, b;
generate
for (b = 0; b < BITS; b = b + 1) begin : BIT
for (i = 0; i <= T; i = i + 1) begin : REG
if (!(b % REG_RATIO)) begin : ORIG
bch_chien_reg #(M, i + 1, SKIP + b - BITS + 1 +
`BCH_N(P)
, BITS) u_chien_reg (
.clk(clk),
.start(start),
.in(sigma[i*M+:M]),
.out(chien[((BITS-b-1)*(T+1)+i)*M+:M])
);
end else begin : EXPAND
bch_chien_expand #(M, i + 1, b % REG_RATIO) u_chien_expand (
.in (chien[((BITS-b+(b%REG_RATIO)-1)*(T+1)+i)*M+:M]),
.out(chien[((BITS-b-1)*(T+1)+i)*M+:M])
);
end
end
end
endgenerate
pipeline #(2) u_first_pipeline (
.clk(clk),
.i (start),
.o (first)
);
endmodule
| 7.094633 |
module bch_dec #(
parameter P_D_WIDTH = 32
) (
input wire [ P_D_WIDTH-1:0] d_i,
input wire [fn_ecc_synd_width(P_D_WIDTH)-1:0] ecc_i,
output wire [ P_D_WIDTH-1:0] msk_o,
output wire err_det_o
);
//**********************************************************************
`include "bch_func.inc"
//**********************************************************************
wire [fn_ecc_synd_width(P_D_WIDTH)-1:0] syndromes;
//**********************************************************************
enc_synd_calc #(
.P_D_WIDTH (P_D_WIDTH),
.P_SYND_GEN(1) // 0 -> parity generator, 1-> syndrome generator
) U_enc_synd_calc (
.d_i({d_i, ecc_i}),
.p_o(syndromes)
);
//***************************************************************************
// Error pattern decoder
//***************************************************************************
err_detect_rom #(
.P_D_WIDTH(P_D_WIDTH)
) U_err_detect_rom (
.syndromes_i(syndromes),
.msk_o (msk_o)
);
assign err_det_o = |syndromes;
endmodule
| 7.931096 |
module bch_decode #(
parameter N = 15,
parameter K = 5,
parameter T = 3, /* Correctable errors */
parameter OPTION = "SERIAL"
) (
input clk,
input globrst,
input start,
input data_in,
input ready,
output output_valid,
output data_out
);
`include "bch.vh"
if (T < 3) begin
assign ready = 1;
dec_decode #(N, K, T) u_decode (
.clk(clk),
.start(start),
.data_in(data_in),
.output_valid(output_valid),
.data_out(data_out)
);
end else begin
tmec_decode #(N, K, T, OPTION) u_decode (
.clk(clk),
.start(start),
.ready(ready),
.data_in(data_in),
.output_valid(output_valid),
.data_out(data_out)
);
end
endmodule
| 7.057629 |
module bch_encoder #(
parameter P_D_WIDTH = 21
) (
input wire [P_D_WIDTH-1:0] data_org_in,
// output wire[fn_ecc_synd_width(P_D_WIDTH)-1:0] data_ecc_out
output wire [ 9:0] data_ecc_out
);
//**********************************************************************
`include "bch_func.inc"
//**********************************************************************
//wire [fn_ecc_synd_width(P_D_WIDTH)-1:0] p_o;
wire [9:0] p_o;
//enc_synd_calc #(
enc_synd_calc_enc #(
.P_D_WIDTH (P_D_WIDTH),
.P_SYND_GEN(0)
) U_enc_synd_calc (
.d_i(data_org_in),
.p_o(p_o)
);
assign data_ecc_out = p_o;
endmodule
| 7.78675 |
module bch_encode_wrapper #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter OPTION = "SERIAL",
parameter BITS = 1,
parameter REG_RATIO = 1
) (
input clk,
input reset,
input [`BCH_DATA_BITS(P)-1:0] data_in,
input din_en,
output [`BCH_CODE_BITS(P)-1:0] data_out,
output reg dout_valid,
output ready
);
`include "bch.vh"
localparam TCQ = 1; //delay
localparam N = `BCH_N(P); //码长
localparam E = `BCH_ECC_BITS(P);
localparam M = `BCH_M(P);
localparam T = `BCH_T(P); //纠错?
localparam K = `BCH_K(P); //信息?
localparam B = `BCH_DATA_BITS(P);
function [BITS-1:0] reverse;
input [BITS-1:0] in;
integer i;
begin
for (i = 0; i < N; i = i + 1) reverse[i] = in[BITS-i-1];
end
endfunction
wire [BITS-1:0] encoder_in;
wire encoded_first;//encoded_last raise up one clock after encoded_last raise up,fall down after first encoded_data outputed
wire encode_ready;
wire data_bits;
wire ecc_bits;
wire encoded_last;
wire [BITS-1:0] encoded_data;
reg encode_ce;
reg start_in;
reg [B-1:0] din_buf;
reg [B-1:0] encode_buf;
reg [`BCH_CODE_BITS(P)-1:0] encoded_buf;
always @(posedge clk) begin
if (reset) begin
encode_ce <= 0; // reset
start_in <= 0;
end else if (din_en) begin
encode_ce <= 1;
start_in <= 1;
din_buf <= data_in;
end else if (encoded_last) begin
encode_ce <= 0;
start_in <= 0;
end else begin
start_in <= 0;
end
end
always @(posedge clk) begin
if (start_in) begin
encode_buf <= #TCQ din_buf >> BITS;
end else if (!encode_ready && encode_ce) encode_buf <= #TCQ encode_buf >> BITS;
end
assign encoder_in = reverse(start_in ? din_buf[BITS-1:0] : encode_buf[BITS-1:0]);
bch_encode #(P, BITS) u_bch_encode (
.clk(clk),
.start(start_in),
.ready(encode_ready),
.ce(encode_ce),
.data_in(encoder_in),
.data_out(encoded_data),
.data_bits(data_bits),
.ecc_bits(ecc_bits),
.first(encoded_first),
.last(encoded_last)
);
always @(posedge clk) begin
if (encoded_first) begin
encoded_buf <= #TCQ reverse(encoded_data) << `BCH_CODE_BITS(P) - BITS;
end else if (ecc_bits || data_bits)
encoded_buf <= #TCQ(encoded_buf >> BITS) | (reverse(
encoded_data
) <<
`BCH_CODE_BITS(P)
- BITS);
end
always @(posedge clk) begin
if (reset) begin
dout_valid <= 0;
end else dout_valid <= encoded_last;
end
assign data_out = encoded_buf;
assign ready = encode_ready;
endmodule
| 6.738022 |
module bch_enc_parity #(
parameter P_D_WIDTH = 16
) (
input wire [ P_D_WIDTH-1:0] d_i,
output wire [fn_ecc_synd_width(P_D_WIDTH)-1:0] p_o
);
//**********************************************************************
`include "bch_func.inc"
//**********************************************************************
enc_synd_calc #(
.P_D_WIDTH (P_D_WIDTH),
.P_SYND_GEN(0)
) U_enc_synd_calc (
.d_i(d_i),
.p_o(p_o)
);
endmodule
| 7.424307 |
module bch_error_dec #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Latch inputs, start calculating */
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output [`BCH_ERR_SZ(P)-1:0] err_count, /* Valid during valid cycles */
output first, /* First valid output data */
output [BITS-1:0] err
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam T = `BCH_T(P);
wire [(2*T-1)*M-1:0] expanded;
wire [`BCH_SIGMA_SZ(P)-1:0] sigma;
wire [`BCH_SIGMA_SZ(P)*BITS-1:0] chien;
wire first_raw;
reg [`BCH_ERR_SZ(P)-1:0] err_count_raw = 0;
wire [BITS-1:0] _err_raw;
bch_chien #(P, BITS, REG_RATIO) u_chien (
.clk (clk),
.start(start),
.sigma(sigma),
.chien(chien),
.first(first_raw)
);
pipeline #(PIPELINE_STAGES) u_out_pipeline (
.clk(clk),
.i (first_raw),
.o (first)
);
genvar i;
if (T == 1) begin : SEC
assign sigma = syndromes;
/*
* SEC sigma(x) = 1 + S_1 * x
* No error if S_1 = 0
*/
for (i = 0; i < BITS; i = i + 1) begin : BIT
assign _err_raw[i] = chien[i*(T+1)*M+:M] == 1;
end
always @(posedge clk) if (start) err_count_raw <= #TCQ |syndromes[0+:M];
if (PIPELINE_STAGES > 1) sec_only_supports_1_pipeline_stage u_sos1ps ();
pipeline #(PIPELINE_STAGES) u_err_pipeline[BITS+
`BCH_ERR_SZ(P)
-1:0] (
.clk(clk),
.i ({_err_raw, err_count_raw}),
.o ({err, err_count})
);
end else if (T == 2) begin : POW3
/*
* DEC simga(x) = 1 + sigma_1 * x + sigma_2 * x^2 =
* 1 + S_1 * x + (S_1^2 + S_3 * S_1^-1) * x^2
* No error if S_1 = 0, S_3 = 0
* one error if S_1 != 0, S_3 = S_1^3
* two errors if S_1 != 0, S_3 != S_1^3
* >2 errors if S_1 = 0, S_3 != 0
* The below may be a better choice for large circuits (cycles tradeoff)
* sigma_1(x) = S_1 + S_1^2 * x + (S_1^3 + S_3) * x^2
*/
reg first_cycle = 0;
wire first_cycle_pipelined;
assign sigma = {syndromes[M+:M], {M{1'b0}}, syndromes[0+:M]};
if (PIPELINE_STAGES > 2) dec_pow3_only_supports_2_pipeline_stages u_dpos2ps ();
for (i = 0; i < BITS; i = i + 1) begin : BIT
wire [M-1:0] ch1_flipped;
wire ch1_nonzero_pipelined;
wire [M-1:0] ch3_flipped;
wire ch3_nonzero_pipelined;
wire [M-1:0] ch3_flipped_pipelined;
wire [M-1:0] power;
wire [M-1:0] power_pipelined;
wire [1:0] errors;
wire [1:0] errors_pipelined;
/* For each cycle, try flipping the bit */
assign ch1_flipped = chien[(i*(T+1)+0)*M+:M] ^ !(first_cycle && !i);
assign ch3_flipped = chien[(i*(T+1)+2)*M+:M] ^ !(first_cycle && !i);
/* FIXME: Stagger output to eliminate pipeline reg */
pow3 #(M) u_pow3 (
.in (ch1_flipped),
.out(power)
);
pipeline #(PIPELINE_STAGES > 0) u_power_pipeline[M+M+2-1:0] (
.clk(clk),
.i({power, ch3_flipped, |ch1_flipped, |ch3_flipped}),
.o({power_pipelined, ch3_flipped_pipelined, ch1_nonzero_pipelined, ch3_nonzero_pipelined})
);
/* Calculate the number of erros */
assign errors = ch1_nonzero_pipelined ?
(power_pipelined == ch3_flipped_pipelined ? 1 : 2) :
(ch3_nonzero_pipelined ? 3 : 0);
pipeline #(PIPELINE_STAGES > 1) u_errors_pipeline[2-1:0] (
clk,
errors,
errors_pipelined
);
/*
* If flipping reduced the number of errors,
* then we found an error
*/
assign err[i] = err_count_raw > errors_pipelined;
end
pipeline #(PIPELINE_STAGES) u_cycle_pipeline (
.clk(clk),
.i (first_cycle),
.o (first_cycle_pipelined)
);
always @(posedge clk) begin
first_cycle <= #TCQ start;
if (first_cycle_pipelined) err_count_raw <= #TCQ BIT[0].errors_pipelined;
end
assign err_count = err_count_raw;
end else dec_only_valid_for_t_less_than_3 u_dovftlt3 ();
endmodule
| 8.484252 |
module bch_error_one #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Latch inputs, start calculating */
input [`BCH_M(P)*2-1:0] sigma,
output first, /* First valid output data */
output [BITS-1:0] err
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam SKIP = `BCH_DATA_BITS(P) - `BCH_K(P) + `BCH_N(P);
wire [BITS-1:0] err_raw;
wire [M-1:0] chien;
if (`BCH_T(P) == 1) one_does_not_support_sec u_odnss ();
bch_chien_reg #(M, 1, 0, BITS) u_chien_reg (
.clk(clk),
.start(start),
.in(sigma[M+:M]),
.out(chien)
);
genvar b;
generate
for (b = 0; b < BITS; b = b + 1) begin : BIT
assign err_raw[b] = chien == lpow(M, SKIP + b);
end
endgenerate
pipeline #(2 + PIPELINE_STAGES) u_first_pipeline (
.clk(clk),
.i (start),
.o (first)
);
pipeline #(PIPELINE_STAGES) u_out_pipeline[BITS-1:0] (
.clk(clk),
.i (err_raw),
.o (err)
);
endmodule
| 7.294102 |
module bch_error_tmec #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0,
parameter ACCUM = PIPELINE_STAGES > 1 ? `CONFIG_LUT_SZ : 1
) (
input clk,
input start, /* Latch inputs, start calculating */
input [`BCH_SIGMA_SZ(P)-1:0] sigma,
output first, /* First valid output data */
output [BITS-1:0] err
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
/*
* We have to sum all the chien outputs. Split up the outputs and sum
* them into accumulators. For instance, if REGS == 13, and ACCUM == 3
* then we group together the chien outputs into 5 regs, 4 regs, and
* 4 regs. We then sum together those accumulators.
*/
localparam REGS = `BCH_T(P) + 1;
localparam W_A = (REGS + ACCUM - 1) / ACCUM;
localparam W_B = REGS / ACCUM;
localparam ACCUM_A = REGS - W_B * ACCUM;
localparam ACCUM_B = ACCUM - ACCUM_A;
wire [BITS*`BCH_CHIEN_SZ(P)-1:0] chien;
wire [ACCUM*BITS*M-1:0] accum;
wire [ACCUM*BITS*M-1:0] accum_pipelined;
wire [BITS*M-1:0] sum;
wire [BITS*M-1:0] sum_pipelined;
wire [BITS-1:0] err_raw;
wire first_raw;
genvar i, j;
if (`BCH_T(P) == 1) tmec_does_not_support_sec u_tdnss ();
if (PIPELINE_STAGES > 3) tmec_only_supports_3_pipeline_stages u_tos2ps ();
if (ACCUM > REGS) tmec_accum_must_be_less_than_or_equal_to_regs u_tambltoretr ();
if (ACCUM > 1 && PIPELINE_STAGES < 2) tmec_accum_requires_2_or_more_pipeline_stages u_tar2omps ();
bch_chien #(P, BITS, REG_RATIO) u_chien (
.clk (clk),
.start(start),
.sigma(sigma),
.chien(chien),
.first(first_raw)
);
pipeline #(PIPELINE_STAGES) u_out_pipeline (
.clk(clk),
.i (first_raw),
.o (first)
);
for (i = 0; i < BITS; i = i + 1) begin : BITS_BLOCK
for (j = 0; j < ACCUM_A; j = j + 1) begin : ACCUM_A_BLOCK
finite_parallel_adder #(M, W_A) u_adder (
.in (chien[i*`BCH_CHIEN_SZ(P)+j*W_A*M+:W_A*M]),
.out(accum[(i*ACCUM+j)*M+:M])
);
end
for (j = 0; j < ACCUM_B; j = j + 1) begin : ACCUM_B_BLOCK
finite_parallel_adder #(M, W_B) u_adder (
.in (chien[i*`BCH_CHIEN_SZ(P)+(ACCUM_A*W_A+j*W_B)*M+:W_B*M]),
.out(accum[(i*ACCUM+ACCUM_A+j)*M+:M])
);
end
end
pipeline #(PIPELINE_STAGES > 1) u_accum_pipeline[ACCUM*BITS*M-1:0] (
clk,
accum,
accum_pipelined
);
finite_parallel_adder #(M, ACCUM) u_adder[BITS-1:0] (
accum_pipelined,
sum
);
pipeline #(PIPELINE_STAGES > 2) u_sum_pipeline[BITS*M-1:0] (
clk,
sum,
sum_pipelined
);
zero_cla #(M, PIPELINE_STAGES > 2 ? 1 : ACCUM) u_zero[BITS-1:0] (
sum_pipelined,
err_raw
);
pipeline #(PIPELINE_STAGES > 0) u_err_pipeline1[BITS-1:0] (
.clk(clk),
.i (err_raw[BITS-1:0]),
.o (err[BITS-1:0])
);
endmodule
| 7.140267 |
module finite_divider #(
parameter M = 6
) (
input clk,
input start,
input [M-1:0] standard_numer,
input [M-1:0] standard_denom,
output [M-1:0] dual_out,
output reg busy = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam DONE = lfsr_count(log2(M), M - 2);
localparam INITIAL = `BCH_DUAL(M);
reg [M-1:0] standard_a = 0;
wire [M-1:0] standard_b;
reg [M-1:0] dual_c = INITIAL;
wire [M-1:0] dual_d;
wire [log2(M)-1:0] count;
assign dual_out = dual_d;
/* Square the input each cycle */
parallel_standard_power #(M, 2) u_dsq (
.standard_in (start ? standard_denom : standard_a),
.standard_out(standard_b)
);
/*
* Accumulate the term each cycle (Reuse for C = A*B^(-1) )
* Reuse multiplier to multiply by numerator
*/
parallel_mixed_multiplier #(M) u_parallel_mixed_multiplier (
.dual_in(dual_c),
.standard_in(busy ? standard_a : standard_numer),
.dual_out(dual_d)
);
lfsr_counter #(log2(
M
)) u_counter (
.clk(clk),
.reset(start),
.ce(busy),
.count(count)
);
always @(posedge clk) begin
if (start) busy <= #TCQ 1;
else if (count == DONE) busy <= #TCQ 0;
if (start) dual_c <= #TCQ INITIAL;
else if (busy) dual_c <= #TCQ dual_d;
if (start || busy) standard_a <= #TCQ standard_b;
end
endmodule
| 6.662806 |
module pow3 #(
parameter M = 4
) (
input [M-1:0] in,
output [M-1:0] out
);
`include "bch.vh"
genvar i, j, k;
wire [ M-1:0] ft_in;
wire [M*M-1:0] st_in;
generate
for (i = 0; i < M; i = i + 1) begin : FIRST_TERM
localparam BITS = lpow(M, 3 * i);
/* first_term = a_i * alpha^(3*i) */
assign ft_in[i] = in[i];
end
/* i = 0 to m - 2, j = i to m - 1 */
for (k = 0; k < M * M; k = k + 1) begin : SECOND_TERM
/* i = k / M, j = j % M */
/* second_term = a_i * a_j * (alpha^(2*i+j) + alpha^(2*i+j)) */
localparam BITS = (k / M < k % M) ? (lpow(
M, 2 * (k / M) + k % M
) ^ lpow(
M, 2 * (k % M) + k / M
)) : 0;
assign st_in[k] = (k / M < k % M) ? (in[k/M] & in[k%M]) : 0;
end
for (i = 0; i < M; i = i + 1) begin : CALC
wire [ M-1:0] first_term;
wire [M*M-1:0] second_term;
/* Rearrange bits for multiplication */
for (j = 0; j < M; j = j + 1) begin : arrange1
assign first_term[j] = FIRST_TERM[j].BITS[i];
end
for (j = 0; j < M * M; j = j + 1) begin : arrange2
assign second_term[j] = SECOND_TERM[j].BITS[i];
end
/* a^3 = first_term + second_term*/
assign out[i] = ^(ft_in & first_term) ^ ^(st_in & second_term);
end
endgenerate
endmodule
| 6.886102 |
module finite_parallel_adder #(
parameter M = 4,
parameter N_INPUT = 2
) (
input [M*N_INPUT-1:0] in,
output [M-1:0] out
);
genvar i, j;
for (i = 0; i < M; i = i + 1) begin : add
wire [N_INPUT-1:0] z;
for (j = 0; j < N_INPUT; j = j + 1) begin : arrange
assign z[j] = in[j*M+i];
end
assign out[i] = ^z;
end
endmodule
| 7.457991 |
module bch_syndrome #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter BITS = 1,
parameter REG_RATIO = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Accept first syndrome bit (assumes ce) */
input ce,
input [BITS-1:0] data_in,
output ready,
output [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output reg done = 0
);
localparam M = `BCH_M(P);
localparam [`MAX_M*(1<<(`MAX_M-1))-1:0] TBL = syndrome_build_table(M, `BCH_T(P));
`include "bch_syndrome.vh"
localparam TCQ = 1;
genvar idx;
localparam CYCLES = PIPELINE_STAGES + (`BCH_CODE_BITS(P) + BITS - 1) / BITS;
localparam DONE = lfsr_count(M, CYCLES - 2);
localparam REM = `BCH_CODE_BITS(P) % BITS;
localparam RUNT = BITS - REM;
localparam SYN_COUNT = TBL[0+:`MAX_M];
wire [M-1:0] count;
wire [BITS-1:0] data_pipelined;
wire [BITS-1:0] shifted_in;
wire [BITS-1:0] shifted_pipelined;
wire start_pipelined;
reg busy = 0;
if (CYCLES > 2) begin : COUNTER
lfsr_counter #(M) u_counter (
.clk(clk),
.reset(start && ce),
.ce(busy && ce),
.count(count)
);
end else assign count = DONE;
assign ready = !busy;
always @(posedge clk) begin
if (ce) begin
if (start) begin
done <= #TCQ CYCLES == 1;
busy <= #TCQ CYCLES > 1;
end else if (busy && count == DONE) begin
done <= #TCQ 1;
busy <= #TCQ 0;
end else done <= #TCQ 0;
end
end
/*
* Method 1 requires data to be aligned to the first transmitted bit,
* which is how input is received. Method 2 requires data to be
* aligned to the last received bit, so we may need to insert some
* zeros in the first word, and shift the remaining bits
*/
generate
if (REM) begin
reg [RUNT-1:0] runt = 0;
assign shifted_in = {start ? {RUNT{1'b0}} : runt, data_in[BITS-1:RUNT]};
always @(posedge clk) if (ce) runt <= #TCQ data_in;
end else assign shifted_in = data_in;
endgenerate
/* Pipelined data for method1 */
pipeline_ce #(PIPELINE_STAGES > 1) u_data_pipeline[BITS-1:0] (
.clk(clk),
.ce (ce),
.i (data_in),
.o (data_pipelined)
);
/* Pipelined data for method2 */
pipeline_ce #(PIPELINE_STAGES > 0) u_shifted_pipeline[BITS-1:0] (
.clk(clk),
.ce (ce),
.i (shifted_in),
.o (shifted_pipelined)
);
pipeline_ce #(PIPELINE_STAGES > 1) u_start_pipeline (
.clk(clk),
.ce (ce),
.i (start),
.o (start_pipelined)
);
/* LFSR registers */
generate
for (idx = 0; idx < SYN_COUNT; idx = idx + 1) begin : SYNDROMES
localparam SYN = idx2syn(idx);
if (syndrome_method(`BCH_T(P), SYN) == 0) begin : METHOD1
dsynN_method1 #(P, SYN, BITS, REG_RATIO, PIPELINE_STAGES) u_syn1a (
.clk(clk),
.start(start),
.start_pipelined(start_pipelined),
.ce((busy || start) && ce),
.data_pipelined(data_pipelined),
.synN(syndromes[idx*M+:M])
);
end else begin : METHOD2
dsynN_method2 #(P, SYN, syndrome_degree(
M, SYN
), BITS, PIPELINE_STAGES) u_syn2a (
.clk(clk),
.start(start),
.start_pipelined(start_pipelined),
.ce((busy || start) && ce),
.data_in(shifted_in),
.data_pipelined(shifted_pipelined),
.synN(syndromes[idx*M+:M])
);
end
end
endgenerate
endmodule
| 7.297116 |
module bch_syndrome_shuffle #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE
) (
input clk,
input start, /* Accept first syndrome bit */
input ce, /* Shuffle cycle */
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output reg [(2*`BCH_T(P)-1)*`BCH_M(P)-1:0] syn_shuffled = 0
);
localparam M = `BCH_M(P);
localparam [`MAX_M*(1<<(`MAX_M-1))-1:0] TBL = syndrome_build_table(M, `BCH_T(P));
`include "bch_syndrome.vh"
localparam TCQ = 1;
localparam T = `BCH_T(P);
genvar i;
wire [(2*T-1)*M-1:0] bypass_in_shifted;
wire [(2*T-1)*M-1:0] syndromes_pre_expand;
wire [(2*T-1)*M-1:0] expand_in;
wire [(2*T-1)*M-1:0] expand_in1;
wire [(2*T-1)*M-1:0] syn_expanded;
for (i = 0; i < 2 * T - 1; i = i + 1) begin : ASSIGN
assign syndromes_pre_expand[i*M+:M] = syndromes[dat2idx(i+1)*M+:M] & {M{start}};
end
/* Shuffle syndromes */
rotate_right #((2 * T - 1) * M, 3 * M) u_rol_e (
syndromes_pre_expand,
expand_in1
);
reverse_words #(M, 2 * T - 1) u_rev (
expand_in1,
expand_in
);
rotate_left #((2 * T - 1) * M, 2 * M) u_rol_b (
syn_shuffled,
bypass_in_shifted
);
/*
* We need to combine syndrome expansion and shuffling into a single
* operation so we can optimize LUT usage for an XOR carry chain. It
* causes a little confusion as we need to select expansion method
* based on the pre-shuffled indexes as well as pass in the pre-
* shuffled index to the expand method.
*/
for (i = 0; i < 2 * T - 1; i = i + 1) begin : EXPAND
localparam PRE = (2 * T - 1 + 2 - i) % (2 * T - 1); /* Pre-shuffle value */
if (syndrome_method(T, dat2syn(PRE + 1)) == 0) begin : METHOD1
syndrome_expand_method1 #(P) u_expand (
.in (expand_in[i*M+:M]),
.out(syn_expanded[i*M+:M])
);
end else begin : METHOD2
syndrome_expand_method2 #(P, PRE + 1) u_expand (
.in (expand_in[i*M+:M]),
.out(syn_expanded[i*M+:M])
);
end
end
always @(posedge clk)
if (start || ce)
syn_shuffled <= #TCQ syn_expanded ^ ({(2 * T - 1) * M{!start}} & bypass_in_shifted);
endmodule
| 7.165201 |
module bch_errors_present #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start,
input [`BCH_SYNDROMES_SZ(P)-1:0] syndromes,
output done,
output errors_present /* Valid during done cycle */
);
localparam M = `BCH_M(P);
genvar i;
wire [(`BCH_SYNDROMES_SZ(P)/M)-1:0] syndrome_zero;
wire [(`BCH_SYNDROMES_SZ(P)/M)-1:0] syndrome_zero_pipelined;
generate
for (i = 0; i < `BCH_SYNDROMES_SZ(P) / M; i = i + 1) begin : ZEROS
assign syndrome_zero[i] = |syndromes[i*M+:M];
end
endgenerate
pipeline #(PIPELINE_STAGES > 0) u_sz_pipeline[
`BCH_SYNDROMES_SZ(P)
/M-1:0] (
.clk(clk),
.i (syndrome_zero),
.o (syndrome_zero_pipelined)
);
pipeline #(PIPELINE_STAGES > 1) u_present_pipeline (
.clk(clk),
.i (|syndrome_zero_pipelined),
.o (errors_present)
);
pipeline #(PIPELINE_STAGES) u_done_pipeline (
.clk(clk),
.i (start),
.o (done)
);
endmodule
| 7.290449 |
module dsynN_method1 #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter SYN = 0,
parameter BITS = 1,
parameter REG_RATIO = BITS > 8 ? 8 : BITS,
parameter PIPELINE_STAGES = 0
) (
input clk,
input start, /* Accept first bit of syndrome */
input start_pipelined, /* Start delayed by one if there are
* two pipeline stages */
input ce,
input [BITS-1:0] data_pipelined, /* One stage delay (if necessary) */
output reg [`BCH_M(P)-1:0] synN = 0
);
`include "bch.vh"
localparam TCQ = 1;
localparam M = `BCH_M(P);
localparam signed SKIP = `BCH_K(P) - `BCH_DATA_BITS(P);
localparam LPOW_S_BITS = lpow(M, `BCH_N(P) - (SYN * BITS) % `BCH_N(P));
localparam REGS = (BITS + REG_RATIO - 1) / REG_RATIO;
if (PIPELINE_STAGES > 2) dsynN_method1_only_supports_2_pipeline_stage u_dm1os2ps ();
if (REG_RATIO > BITS) syndrome_reg_ratio_must_be_less_than_or_equal_to_bits u_srrmbltoeqb ();
function [REGS*M-1:0] pow_initial;
input dummy;
integer i;
begin
for (i = 0; i < REGS; i = i + 1)
pow_initial[i*M+:M] = lpow(M, `BCH_N(P) - (SYN * (SKIP + BITS - i * REG_RATIO)) % `BCH_N(P));
end
endfunction
localparam [REGS*M-1:0] POW_INITIAL = pow_initial(0);
/*
* Reduce pow reg size by only having a reg for every other,
* or every 4th, etc register, filling in the others with async logic
*/
reg [REGS*M-1:0] pow = POW_INITIAL;
wire [REGS*M-1:0] pow_next;
wire [REGS*M-1:0] pow_curr;
wire [BITS*M-1:0] pow_all;
wire [BITS*M-1:0] terms;
wire [M-1:0] terms_summed;
wire [M-1:0] terms_summed_pipelined;
genvar i;
/* Not enough pipeline stages for set/reset, must use mux */
assign pow_curr = (PIPELINE_STAGES < 2 && start) ? POW_INITIAL : pow;
for (i = 0; i < BITS; i = i + 1) begin : GEN_TERMS
wire [M-1:0] curr = pow_curr[(i/REG_RATIO)*M+:M];
if (!(i % REG_RATIO)) assign pow_all[i*M+:M] = curr;
else begin
localparam [M-1:0] LPOW = lpow(M, (SYN * (i % REG_RATIO)) % `BCH_N(P));
if (`CONFIG_CONST_OP)
parallel_standard_multiplier_const1 #(M, LPOW) u_mult (
.standard_in (curr),
.standard_out(pow_all[i*M+:M])
);
else
parallel_standard_multiplier #(M) u_mult (
.standard_in1(LPOW),
.standard_in2(curr),
.standard_out(pow_all[i*M+:M])
);
end
assign terms[i*M+:M] = data_pipelined[i] ? pow_all[i*M+:M] : 0;
end
if (`CONFIG_CONST_OP)
parallel_standard_multiplier_const1 #(M, LPOW_S_BITS[M-1:0]) u_mult[REGS-1:0] (
.standard_in (pow_curr),
.standard_out(pow_next)
);
else
parallel_standard_multiplier #(M) u_mult[REGS-1:0] (
.standard_in1(LPOW_S_BITS[M-1:0]),
.standard_in2(pow_curr),
.standard_out(pow_next)
);
finite_parallel_adder #(M, BITS) u_adder (
.in (terms),
.out(terms_summed)
);
pipeline_ce #(PIPELINE_STAGES > 0) u_summed_pipeline[M-1:0] (
.clk(clk),
.ce (ce),
.i (terms_summed),
.o (terms_summed_pipelined)
);
always @(posedge clk) begin
if (ce) begin
/* Utilize set/reset signal if possible */
pow <= #TCQ(PIPELINE_STAGES > 1 && start) ? POW_INITIAL : pow_next;
if (start_pipelined) synN <= #TCQ PIPELINE_STAGES ? 0 : terms_summed_pipelined;
else synN <= #TCQ synN ^ terms_summed_pipelined;
end
end
endmodule
| 8.49154 |
module dsynN_method2 #(
parameter [`BCH_PARAM_SZ-1:0] P = `BCH_SANE,
parameter SYN = 0,
parameter DEGREE = `BCH_M(P),
parameter BITS = 1,
parameter PIPELINE_STAGES = 0
) (
input clk,
input ce, /* Accept additional bit */
input start, /* Accept first bit of syndrome */
input start_pipelined, /* Start delayed by one if there are
* two pipeline stages */
input [BITS-1:0] data_in,
input [BITS-1:0] data_pipelined, /* One stage delay (if necessary) */
output [`BCH_M(P)-1:0] synN
);
`include "bch.vh"
localparam M = `BCH_M(P);
function [M-1:0] syndrome_poly;
input dummy;
integer i;
integer j;
integer a;
integer first;
integer done;
integer curr;
integer prev;
reg [M*M-1:0] poly;
begin
poly = 1;
first = lpow(M, SYN);
a = first;
done = 0;
while (!done) begin
prev = 0;
for (j = 0; j < M; j = j + 1) begin
curr = poly[j*M+:M];
poly[j*M+:M] = finite_mult(M, curr, a) ^ prev;
prev = curr;
end
a = finite_mult(M, a, a);
if (a == first) done = 1;
end
syndrome_poly = 0;
for (i = 0; i < M; i = i + 1) syndrome_poly[i] = poly[i*M+:M] ? 1 : 0;
end
endfunction
localparam TCQ = 1;
localparam SYNDROME_POLY = syndrome_poly(0);
localparam signed EARLY = BITS - DEGREE;
if (PIPELINE_STAGES > 2) dsynN_method2_only_supports_2_pipeline_stage u_dm2os2ps ();
reg [DEGREE-1:0] lfsr = 0;
wire [DEGREE-1:0] in_enc_early;
wire [DEGREE-1:0] in_enc_early_pipelined;
wire [DEGREE-1:0] in_enc;
wire [DEGREE-1:0] in_enc_pipelined;
wire [DEGREE-1:0] lfsr_enc;
/*
* If the input size fills the LFSR reg, we need to calculate those
* additional lfsr terms.
*/
if (EARLY > 0) begin : INPUT_LFSR
lfsr_term #(DEGREE, SYNDROME_POLY, EARLY) u_in_terms (
.in (data_in[BITS-1:DEGREE]),
.out(in_enc_early)
);
end else assign in_enc_early = 0;
pipeline_ce #(PIPELINE_STAGES > 0) u_in_pipeline[DEGREE-1:0] (
.clk(clk),
.ce (ce),
.i (in_enc_early),
.o (in_enc_early_pipelined)
);
assign in_enc = in_enc_early_pipelined ^ data_pipelined;
pipeline_ce #(PIPELINE_STAGES > 1) u_enc_pipeline[DEGREE-1:0] (
.clk(clk),
.ce (ce),
.i (in_enc),
.o (in_enc_pipelined)
);
/* Calculate the next lfsr state (without input) */
wire [BITS-1:0] lfsr_input;
assign lfsr_input = EARLY > 0 ? (lfsr << EARLY) : (lfsr >> -EARLY);
lfsr_term #(DEGREE, SYNDROME_POLY, BITS) u_lfsr_term (
.in (lfsr_input),
.out(lfsr_enc)
);
/* Calculate remainder */
always @(posedge clk)
if (ce) begin
if (start_pipelined)
/* Use start as set/reset if possible */
lfsr <= #TCQ PIPELINE_STAGES ? 0 : in_enc_pipelined;
else lfsr <= #TCQ(lfsr << BITS) ^ lfsr_enc ^ in_enc_pipelined;
end
assign synN = lfsr;
endmodule
| 7.726686 |
module x_ychooser (
command,
xin1,
yin1,
xin2,
yin2,
out_x,
out_y,
color1in,
color2in,
color3in,
color4in,
color5in,
color6in,
color7in,
color8in,
colorout
);
output reg [7:0] out_x;
output reg [6:0] out_y;
input [7:0] xin1, xin2;
input [6:0] yin1, yin2;
input [3:0] command;
input [2:0] color1in, color2in, color3in, color4in, color5in, color6in, color7in, color8in;
output reg [2:0] colorout;
always @(*) begin
case (command[3:0])
4'b0000: begin
out_x = xin1;
out_y = yin1;
colorout = color1in;
end
4'b0001: begin
out_x = xin2;
out_y = yin2;
colorout = color2in;
end
4'b0010: begin
out_x = xin2;
out_y = yin2;
colorout = color3in;
end
4'b0011: begin
out_x = xin2;
out_y = yin2;
colorout = color4in;
end
4'b0100: begin
out_x = xin2;
out_y = yin2;
colorout = color5in;
end
4'b0101: begin
out_x = xin2;
out_y = yin2;
colorout = color6in;
end
4'b0110: //Starting one//
begin
out_x = xin2;
out_y = yin2;
colorout = color7in;
end
4'b0111: //Starting two//
begin
out_x = xin2;
out_y = yin2;
colorout = color8in;
end
//4'b0111:
//begin
//out_x=xin2;
//out_y=yin2;
//colorout=color3in;
//end
endcase
end
endmodule
| 6.878053 |
module bclk_dll ( // Clock in ports
input clk133in,
// Clock out ports
output clk133,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = clk133in;
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP #(
.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (2),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (7.518),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK ("NONE"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE")
) dcm_sp_inst
// Input clock
(
.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180(),
.CLKFX (clkfx),
.CLKFX180(),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC(1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN(1'b0)
);
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
// no phase alignment active, connect to ground
assign clkfb = 1'b0;
BUFG clkout1_buf (
.O(clk133),
.I(clkfx)
);
endmodule
| 6.912322 |
module bclk_dll_exdes #(
parameter TCQ = 100
) ( // Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
output [1:1] CLK_OUT,
// High bits of counters driven by clocks
output COUNT,
// Status and control signals
input RESET,
output LOCKED
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// When the clock goes out of lock, reset the counters
wire reset_int = !LOCKED || RESET || COUNTER_RESET;
reg rst_sync;
reg rst_sync_int;
reg rst_sync_int1;
reg rst_sync_int2;
// Declare the clocks and counter
wire clk_int;
wire clk;
reg [C_W-1:0] counter;
// Insert BUFGs on all input clocks that don't already have them
//--------------------------------------------------------------
BUFG clkin1_buf (
.O(clk_in1_buf),
.I(CLK_IN1)
);
// Instantiation of the clocking network
//--------------------------------------
bclk_dll clknetwork ( // Clock in ports
.clk133in(clk_in1_buf),
// Clock out ports
.clk133 (clk_int),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
assign CLK_OUT[1] = clk_int;
// Connect the output clocks to the design
//-----------------------------------------
assign clk = clk_int;
// Reset synchronizer
//-----------------------------------
always @(posedge reset_int or posedge clk) begin
if (reset_int) begin
rst_sync <= 1'b1;
rst_sync_int <= 1'b1;
rst_sync_int1 <= 1'b1;
rst_sync_int2 <= 1'b1;
end else begin
rst_sync <= 1'b0;
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end
end
// Output clock sampling
//-----------------------------------
always @(posedge clk or posedge rst_sync_int2) begin
if (rst_sync_int2) begin
counter <= #TCQ{C_W{1'b0}};
end else begin
counter <= #TCQ counter + 1'b1;
end
end
// alias the high bit to the output
assign COUNT = counter[C_W-1];
endmodule
| 7.274408 |
module bclk_dll_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 7.518 * ONE_NS;
localparam time PER1_1 = PER1 / 2;
localparam time PER1_2 = PER1 - PER1 / 2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [ 1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1 * 6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1 * 6);
COUNTER_RESET = 1;
#(PER1 * 19.5) COUNTER_RESET = 0;
#(PER1 * 1) $display("Timing checks are valid");
test_phase = "counting";
#(PER1 * COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
always @(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n", $time / PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
bclk_dll_exdes dut ( // Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET(COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED)
);
// Freq Check
endmodule
| 7.671107 |
module bcnt (
clk,
rst,
trig,
out
);
input clk;
input rst;
input trig; //Order Trigger
//trig 0 == UpCounter
//trig 1 == DownCounter
output reg [3:0] out;
always @(posedge clk, negedge rst) begin
if (!rst) out <= (trig == 1'b0) ? 4'b0000 : 4'b1111;
else begin
case (trig)
1'b1: out <= (out - 1'b1);
default: out <= (out + 1'b1);
endcase
end
end
endmodule
| 7.289211 |
module bcpu16_consts #(
parameter DATA_WIDTH = 16
) (
// input register value
input wire [DATA_WIDTH - 1 : 0] B_VALUE_IN,
// bbb: B register index from instruction - used as const index when CONST_MODE==1
input wire [2:0] B_REG_INDEX,
// mm: const_mode - when 00 return B_VALUE_IN, when 01,10,11 return one of 24 consts from table
input wire [1:0] CONST_MODE,
// output value: CONST_MODE?(1<<B_REG_INDEX):B_VALUE_IN
output wire [DATA_WIDTH - 1 : 0] B_VALUE_OUT
);
wire [4:0] index;
assign index = {CONST_MODE, B_REG_INDEX};
assign B_VALUE_OUT
= (CONST_MODE == 2'b00) ? B_VALUE_IN // mode 00: pass register value as is to output
// mode 01:
// small constants (non-power of 2)
: (index == 5'b01_000) ? 16'b00000000_00000011 // 3
: (index == 5'b01_001) ? 16'b00000000_00000101 // 5
: (index == 5'b01_010) ? 16'b00000000_00000110 // 6
: (index == 5'b01_011) ? 16'b00000000_00000111 // 7
// useful masks
: (index == 5'b01_100) ? 16'b00000000_00001111 // 15
: (index == 5'b01_101) ? 16'b00000000_11111111 // 255
: (index == 5'b01_110) ? 16'b11111111_00000000 // 0xff00
// all bits set (-1)
: (index == 5'b01_111) ? 16'b11111111_11111111 // 0xffff
// mode 10, 11: single bit set (powers of 2)
: (index == 5'b10_000) ? 16'b00000000_00000001 // 1<<0
: (index == 5'b10_001) ? 16'b00000000_00000010 // 1<<1
: (index == 5'b10_010) ? 16'b00000000_00000100 // 1<<2
: (index == 5'b10_011) ? 16'b00000000_00001000 // 1<<3
: (index == 5'b10_100) ? 16'b00000000_00010000 // 1<<4
: (index == 5'b10_101) ? 16'b00000000_00100000 // 1<<5
: (index == 5'b10_110) ? 16'b00000000_01000000 // 1<<6
: (index == 5'b10_111) ? 16'b00000000_10000000 // 1<<7
: (index == 5'b11_000) ? 16'b00000001_00000000 // 1<<8
: (index == 5'b11_001) ? 16'b00000010_00000000 // 1<<9
: (index == 5'b11_010) ? 16'b00000100_00000000 // 1<<10
: (index == 5'b11_011) ? 16'b00001000_00000000 // 1<<11
: (index == 5'b11_100) ? 16'b00010000_00000000 // 1<<12
: (index == 5'b11_101) ? 16'b00100000_00000000 // 1<<13
: (index == 5'b11_110) ? 16'b01000000_00000000 // 1<<14
: 16'b10000000_00000000; // 1<<15
endmodule
| 8.381997 |
module bcpu16_sdp_regfile #(
// 16, 17, 18
parameter DATA_WIDTH = 16,
// 2^3 regs * 2^2 threads = 5 bits for 32 registers addressing
parameter REG_ADDR_WIDTH = 5
) (
//=========================================
// Synchronous write port
// clock: write operation is done synchronously using this clock
input wire CLK,
input wire CE,
// when WR_EN == 1, write value WR_DATA to address WR_ADDR on raising edge of CLK
input wire WR_EN,
input wire [REG_ADDR_WIDTH-1:0] WR_ADDR,
input wire [DATA_WIDTH-1:0] WR_DATA,
//=========================================
// Asynchronous read port
// always exposes value from address RD_ADDR to RD_DATA
input wire [REG_ADDR_WIDTH-1:0] RD_ADDR,
output wire [DATA_WIDTH-1:0] RD_DATA
);
localparam MEMSIZE = 1 << REG_ADDR_WIDTH;
reg [DATA_WIDTH-1:0] memory[MEMSIZE-1:0];
integer i = 0;
initial begin
for (i = 0; i < MEMSIZE; i = i + 1) begin
memory[i] = 0;
end
end
// synchronous write
always @(posedge CLK) if (WR_EN & CE) memory[wr_addr_0] <= WR_DATA;
// asynchronous read
assign RD_DATA = memory[rd_addr_0];
endmodule
| 9.081002 |
module bcpu_cond_eval (
// input flag values {V,S,Z,C}
input wire [3:0] FLAGS_IN,
// condition code, 0000 is unconditional
input wire [3:0] CONDITION_CODE,
// 1 if condition is met
output wire CONDITION_RESULT
);
assign CONDITION_RESULT
= (CONDITION_CODE==`COND_NONE) ? 1'b1 // 0000 jmp 1 unconditional
: (CONDITION_CODE == `COND_NC) ? ~FLAGS_IN[`FLAG_C] // 0001 jnc c = 0
: (CONDITION_CODE == `COND_NZ) ? ~FLAGS_IN[`FLAG_Z] // 0010 jnz z = 0 jne
: (CONDITION_CODE == `COND_Z) ? FLAGS_IN[`FLAG_Z] // 0011 jz z = 1 je
: (CONDITION_CODE == `COND_NS) ? ~FLAGS_IN[`FLAG_S] // 0100 jns s = 0
: (CONDITION_CODE == `COND_S) ? FLAGS_IN[`FLAG_S] // 0101 js s = 1
: (CONDITION_CODE == `COND_NO) ? ~FLAGS_IN[`FLAG_V] // 0100 jno v = 0
: (CONDITION_CODE == `COND_O) ? FLAGS_IN[`FLAG_V] // 0101 jo v = 1
: (CONDITION_CODE==`COND_A) ? (~FLAGS_IN[`FLAG_C] & ~FLAGS_IN[`FLAG_Z]) // 1000 ja c = 0 & z = 0 above (unsigned compare) !jbe
: (CONDITION_CODE==`COND_AE) ? (~FLAGS_IN[`FLAG_C] & FLAGS_IN[`FLAG_Z]) // 1001 jae c = 0 | z = 1 above or equal (unsigned compare)
: (CONDITION_CODE==`COND_B) ? FLAGS_IN[`FLAG_C] // 1010 jb c = 1 below (unsigned compare) jc
: (CONDITION_CODE==`COND_BE) ? (FLAGS_IN[`FLAG_C] | FLAGS_IN[`FLAG_Z]) // 1011 jbe c = 1 | z = 1 below or equal (unsigned compare) !ja
: (CONDITION_CODE==`COND_L) ? (FLAGS_IN[`FLAG_V] != FLAGS_IN[`FLAG_S]) // 1100 jl v != s less (signed compare)
: (CONDITION_CODE==`COND_LE) ? (FLAGS_IN[`FLAG_V] != FLAGS_IN[`FLAG_S]) | FLAGS_IN[`FLAG_Z] // 1101 jle v != s | z = 1 less or equal (signed compare) !jg
: (CONDITION_CODE==`COND_G) ? (FLAGS_IN[`FLAG_V] == FLAGS_IN[`FLAG_S]) & ~FLAGS_IN[`FLAG_Z] // 1110 jg v = s & z = 0 greater (signed compare) !jle
: (FLAGS_IN[`FLAG_V] == FLAGS_IN[`FLAG_S]) | FLAGS_IN[`FLAG_Z]; // 1111 jge v = s | z = 1 less or equal (signed compare)
endmodule
| 8.421206 |
module bcpu_dualport_bram #(
// data width
parameter DATA_WIDTH = 32,
// address width
parameter ADDR_WIDTH = 12,
// specify init file to fill ram with
parameter INIT_FILE = "",
// port A output register flag
parameter A_REG = 1,
// port B output register flag
parameter B_REG = 1
) (
// clock
input wire CLK,
// reset, active 1
input wire RESET,
// clock enable
input wire CE,
//====================================
// Port A
// 1 to start port A read or write operation
input wire PORT_A_EN,
// enable port A write
input wire PORT_A_WREN,
// port A address
input wire [ADDR_WIDTH-1:0] PORT_A_ADDR,
// port A write data
input wire [DATA_WIDTH-1:0] PORT_A_WRDATA,
// port A read data
output wire [DATA_WIDTH-1:0] PORT_A_RDDATA,
//====================================
// Port B
// 1 to start port B read or write operation
input wire PORT_B_EN,
// enable port B write
input wire PORT_B_WREN,
// port B address
input wire [ADDR_WIDTH-1:0] PORT_B_ADDR,
// port B write data
input wire [DATA_WIDTH-1:0] PORT_B_WRDATA,
// port B read data
output wire [DATA_WIDTH-1:0] PORT_B_RDDATA
);
reg port_a_rden1;
reg port_b_rden1;
always @(posedge CLK) begin
if (RESET) begin
port_a_rden1 <= 0;
port_b_rden1 <= 0;
end else if (CE) begin
port_a_rden1 <= PORT_A_EN & ~PORT_A_WREN;
port_b_rden1 <= PORT_B_EN & ~PORT_B_WREN;
end
end
localparam MEMSIZE = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] memory[MEMSIZE-1:0];
// The following code either initializes the memory values to a specified file or to all zeros to match hardware
generate
if (INIT_FILE != "") begin : use_init_file
initial $readmemh(INIT_FILE, memory, 0, MEMSIZE - 1);
end else begin : init_bram_to_zero
integer ram_index;
initial
for (ram_index = 0; ram_index < MEMSIZE; ram_index = ram_index + 1)
memory[ram_index] = {DATA_WIDTH{1'b0}};
end
endgenerate
reg [DATA_WIDTH-1:0] port_a_rddata;
reg [DATA_WIDTH-1:0] port_b_rddata;
always @(posedge CLK)
if (CE & PORT_A_EN) begin
if (PORT_A_WREN) memory[PORT_A_ADDR] <= PORT_A_WRDATA;
else port_a_rddata <= memory[PORT_A_ADDR];
end
always @(posedge CLK)
if (CE & PORT_B_EN) begin
if (PORT_B_WREN) memory[PORT_B_ADDR] <= PORT_B_WRDATA;
else port_b_rddata <= memory[PORT_B_ADDR];
end
generate
// A output
if (A_REG == 1) begin
// with output register (2-stage)
reg [DATA_WIDTH-1:0] a_rddata_buf;
assign PORT_A_RDDATA = a_rddata_buf;
always @(posedge CLK)
if (RESET) a_rddata_buf <= 'b0;
else if (CE & port_a_rden1) a_rddata_buf <= port_a_rddata;
end else begin
// without output register (1-stage)
assign PORT_A_RDDATA = port_a_rddata;
end
// B output
if (B_REG == 1) begin
// with output register (2-stage)
reg [DATA_WIDTH-1:0] b_rddata_buf;
assign PORT_B_RDDATA = b_rddata_buf;
always @(posedge CLK)
if (RESET) b_rddata_buf <= 'b0;
else if (CE & port_b_rden1) b_rddata_buf <= port_b_rddata;
end else begin
// without output register (1-stage)
assign PORT_B_RDDATA = port_b_rddata;
end
endgenerate
endmodule
| 7.147466 |
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