code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module binary2seven (
input [3:0] BIN,
output reg [0:6] SEV
);
always @(BIN)
case ({
BIN[3:0]
})
4'b0000: {SEV[0:6]} = 7'b0000001; //0
4'b0001: {SEV[0:6]} = 7'b1001111; //1
4'b0010: {SEV[0:6]} = 7'b0010010; //2
4'b0011: {SEV[0:6]} = 7'b0000110; //3
4'b0100: {SEV[0:6]} = 7'b1001100; //4
4'b0101: {SEV[0:6]} = 7'b0100100; //5
4'b0110: {SEV[0:6]} = 7'b0100000; //6
4'b0111: {SEV[0:6]} = 7'b0001111; //7
4'b1000: {SEV[0:6]} = 7'b0000000; //8
4'b1001: {SEV[0:6]} = 7'b0001100; //9
4'b1010: {SEV[0:6]} = 7'b0001000; //A
4'b1011: {SEV[0:6]} = 7'b1100000; //b
4'b1100: {SEV[0:6]} = 7'b0110001; //C
4'b1101: {SEV[0:6]} = 7'b1000010; //D
4'b1110: {SEV[0:6]} = 7'b0110000; //E
4'b1111: {SEV[0:6]} = 7'b0111000; //F
endcase
endmodule
| 6.521798 |
module binaryAdderSubtractor_4_bit (
output [3:0] S,
output C4,
V,
input [3:0] A,
B,
input M
);
wire [3:1] C;
wire [3:0] W;
assign W = B ^ M;
fullAdder
FA0 (
S[0],
C[1],
A[0],
W[0],
M
),
FA1 (
S[1],
C[2],
A[1],
W[1],
C[1]
),
FA2 (
S[2],
C[3],
A[2],
W[2],
C[2]
),
FA3 (
S[3],
C4,
A[3],
W[3],
C[3]
);
assign V = C4 ^ C[3];
endmodule
| 7.406692 |
module binarycell (
en,
data,
rw,
clk,
out
);
input data, clk, rw, en;
output out;
wire set, reset, ffout;
assign set = data & en & ~rw;
assign reset = ~data & en & ~rw;
assign out = en & ffout & rw;
rsflipflop rsff (
set,
reset,
clk,
ffout
);
endmodule
| 8.053565 |
module BinaryCounter #(
parameter WIDTH = 64
) (
input clk,
enable,
reset_n,
output reg [WIDTH-1:0] count
);
// Reset if needed, or increment if counting is enabled
always @(posedge clk or negedge reset_n) begin
if (!reset_n) count <= 0;
else if (enable == 1'b1) count <= count + 1;
end
endmodule
| 7.161712 |
module BinaryDisplay (
Ovalue // <i
);
input [7:0] Ovalue;
always @(*) begin
$display("Output = %d", Ovalue);
end
endmodule
| 8.830701 |
module BinaryImage(
iCLK,
iRST,
iDVAL,
iDATA,
oDATA,
oDVAL,
);
parameter threshold = 10'd190;
input iCLK;
input iRST;
input iDVAL;
input[9:0] iDATA;
output reg[9:0] oDATA;
output reg oDVAL;
always@(posedge iCLK or negedge iRST)
begin
if(!iRST)
begin
oDVAL <= 1'b0;
oDATA <= 10'b0000000000;
end
else
begin
oDVAL <= iDVAL;
if(iDVAL)
begin
if(iDATA > threshold)
oDATA <= 10'b1111111111;
else
oDATA <= 10'b0;
end
else
oDATA <= 10'b0000000000;
end
end
endmodule
| 6.829797 |
module BinaryRepr (
input clock,
input reset,
input [ 7:0] io_uIn,
input [ 7:0] io_sIn,
input [ 9:0] io_fIn,
output io_uOut,
output io_sOut,
output io_fOut,
output [ 7:0] io_uDiv2,
output [ 7:0] io_sDiv2,
output [ 9:0] io_fDiv2,
output [15:0] io_uMul2,
output [15:0] io_sMul2,
output [19:0] io_fMul2
);
wire [9:0] _T_14 = {
$signed(io_sIn), 2'h0
}; // @[FixedPointTypeClass.scala 130:22 FixedPointTypeClass.scala 131:12]
wire [7:0] _T_17 = _T_14[9:2]; // @[FixedPointTypeClass.scala 134:23]
wire [5:0] _T_18 = _T_17[7:2]; // @[FixedPointTypeClass.scala 154:39]
wire [11:0] _T_21 = {
$signed(io_fIn), 2'h0
}; // @[FixedPointTypeClass.scala 130:22 FixedPointTypeClass.scala 131:12]
wire [9:0] _T_24 = _T_21[11:2]; // @[FixedPointTypeClass.scala 134:23]
wire [8:0] _T_25 = _T_24[9:1]; // @[FixedPointTypeClass.scala 154:39]
wire [9:0] _T_26 = {io_uIn, 2'h0}; // @[UIntTypeClass.scala 123:38]
wire [7:0] _GEN_2 = _T_25[8:1]; // @[NumbersSpec.scala 303:12]
assign io_uOut = 1'h0; // @[NumbersSpec.scala 297:11]
assign io_sOut = io_sIn[7]; // @[SIntTypeClass.scala 70:24]
assign io_fOut = io_fIn[9]; // @[FixedPointTypeClass.scala 181:24]
assign io_uDiv2 = {{2'd0}, io_uIn[7:2]}; // @[UIntTypeClass.scala 125:38]
assign io_sDiv2 = {{2{_T_18[5]}}, _T_18}; // @[FixedPointTypeClass.scala 154:39]
assign io_fDiv2 = {{2{_GEN_2[7]}}, _GEN_2}; // @[NumbersSpec.scala 303:12]
assign io_uMul2 = {{6'd0}, _T_26}; // @[UIntTypeClass.scala 123:38]
assign io_sMul2 = {{6{_T_14[9]}}, _T_14}; // @[SIntTypeClass.scala 121:38]
assign io_fMul2 = {{8{_T_21[11]}}, _T_21}; // @[FixedPointTypeClass.scala 114:50]
endmodule
| 7.252997 |
module BinaryToBCD (
number,
hundreds,
tens,
ones
);
// I/O Signal Definitions
input [7:0] number;
output reg [3:0] hundreds;
output reg [3:0] tens;
output reg [3:0] ones;
// Internal variable for storing bits
reg [19:0] shift;
integer i;
always @(number) begin
// Clear previous number and store new number in shift register
shift[19:8] = 0;
shift[7:0] = number;
// Loop eight times
for (i = 0; i < 8; i = i + 1) begin
if (shift[11:8] >= 5) shift[11:8] = shift[11:8] + 3;
if (shift[15:12] >= 5) shift[15:12] = shift[15:12] + 3;
if (shift[19:16] >= 5) shift[19:16] = shift[19:16] + 3;
// Shift entire register left once
shift = shift << 1;
end
// Push decimal numbers to output
hundreds = shift[19:16];
tens = shift[15:12];
ones = shift[11:8];
end
endmodule
| 6.668578 |
module binarytogray (
clk,
reset,
binary_input,
gray_output
);
input clk, reset;
input [3:0] binary_input;
output gray_output;
reg [3:0] gray_output;
always @(posedge clk or posedge reset)
if (reset) begin
gray_output <= 4'b0;
end else begin
gray_output[3] <= binary_input[3];
gray_output[2] <= binary_input[3] ^ binary_input[2];
gray_output[1] <= binary_input[2] ^ binary_input[1];
gray_output[0] <= binary_input[1] ^ binary_input[0];
end
endmodule
| 6.858847 |
module BinaryToLEDDisplay (
input wire clk,
input wire rst,
input wire [15:0] value,
output wire [15:0] leds
);
assign leds = value;
//always @(posedge clk or posedge rst) begin
// if (rst) begin
//// leds = 0;
// end
//end
endmodule
| 8.593888 |
module binaryzation (
input clk,
input [11:0] pixel_gray,
output [11:0] pixel_binary
);
reg [11:0] pixel;
always @(posedge clk) begin
if (pixel_gray < 12'b0101_0101_0101) pixel <= 12'b0000_0000_0000;
else pixel <= 12'b1111_1111_1111;
end
assign pixel_binary = pixel;
endmodule
| 9.219348 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100;
4'b0101: displayer = 7'b0100100;
4'b0110: displayer = 7'b0100000;
4'b0111: displayer = 7'b0001111;
4'b1000: displayer = 7'b0000000;
4'b1001: displayer = 7'b0000100;
default: displayer = 7'b1111111;
endcase
endmodule
| 8.666146 |
module binary_10_bits_BCD (
input [9:0] SW,
output [0:6] HEX0,
HEX1,
HEX2,
HEX3,
output [9:0] LEDR
);
assign LEDR = SW;
integer enteredInput, tenModulo, tenMultiple, hundredMultiple, thousandMultiple;
always @(SW[9:0]) enteredInput = SW[9:0];
reg [3:0] moduloTen, multipleTen, multipleHundred, multipleThousand;
always @(*) begin
tenModulo = enteredInput % 10;
tenMultiple = (enteredInput / 10) % 10;
hundredMultiple = (enteredInput / 100) % 10;
thousandMultiple = (enteredInput / 1000) % 10;
case (tenModulo)
0: moduloTen = 4'b0000;
1: moduloTen = 4'b0001;
2: moduloTen = 4'b0010;
3: moduloTen = 4'b0011;
4: moduloTen = 4'b0100;
5: moduloTen = 4'b0101;
6: moduloTen = 4'b0110;
7: moduloTen = 4'b0111;
8: moduloTen = 4'b1000;
9: moduloTen = 4'b1001;
default: moduloTen = 4'b1111;
endcase
case (tenMultiple)
0: multipleTen = 4'b0000;
1: multipleTen = 4'b0001;
2: multipleTen = 4'b0010;
3: multipleTen = 4'b0011;
4: multipleTen = 4'b0100;
5: multipleTen = 4'b0101;
6: multipleTen = 4'b0110;
7: multipleTen = 4'b0111;
8: multipleTen = 4'b1000;
9: multipleTen = 4'b1001;
default: multipleTen = 4'b1111;
endcase
case (hundredMultiple)
0: multipleHundred = 4'b0000;
1: multipleHundred = 4'b0001;
2: multipleHundred = 4'b0010;
3: multipleHundred = 4'b0011;
4: multipleHundred = 4'b0100;
5: multipleHundred = 4'b0101;
6: multipleHundred = 4'b0110;
7: multipleHundred = 4'b0111;
8: multipleHundred = 4'b1000;
9: multipleHundred = 4'b1001;
default: multipleHundred = 4'b1111;
endcase
case (thousandMultiple)
1: multipleThousand = 4'b0001;
default: multipleThousand = 4'b1111;
endcase
end
displayNumber displayHexZero (
moduloTen,
HEX0
);
displayNumber displayHexOne (
multipleTen,
HEX1
);
displayNumber displayHexTwo (
multipleHundred,
HEX2
);
displayNumber displayHexThree (
multipleThousand,
HEX3
);
endmodule
| 6.70284 |
module Binary_to_Gray (
dout,
din
);
output [3:0] dout;
input [3:0] din;
//--solution 1--//
/*
assign dout[3] = din[3];
assign dout[2] = din[3]^din[2];
assign dout[1] = din[2]^din[1];
assign dout[0] = din[1]^din[0];
*/
//-- solution 2--//
assign dout = din ^ (din >> 1);
//--solution 3--//
/*
always @(din) begin
case (din)
4'b0000: dout = 4'b0000;
4'b0001: dout = 4'b0001;
4'b0010: dout = 4'b0011;
4'b0011: dout = 4'b0010;
4'b0100: dout = 4'b0110;
4'b0101: dout = 4'b0111;
4'b0110: dout = 4'b0101;
4'b0111: dout = 4'b0100;
4'b1000: dout = 4'b1100;
4'b1001: dout = 4'b1101;
4'b1010: dout = 4'b1111;
4'b1011: dout = 4'b1110;
4'b1100: dout = 4'b1010;
4'b1101: dout = 4'b1011;
4'b1110: dout = 4'b1001;
4'b1111: dout = 4'b1000;
end
*/
endmodule
| 7.437129 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100;
4'b0101: displayer = 7'b0100100;
4'b0110: displayer = 7'b0100000;
4'b0111: displayer = 7'b0001111;
4'b1000: displayer = 7'b0000000;
4'b1001: displayer = 7'b0000100;
default: displayer = 7'b1111111;
endcase
endmodule
| 8.666146 |
module binary_6_bits_BCD (
input [9:0] SW,
output [0:6] HEX0,
HEX1,
output [9:0] LEDR
);
assign LEDR = SW;
integer enteredInput, tenModulo, tenMultiple;
always @(SW[5:0]) enteredInput = SW[5:0];
reg [3:0] moduloBinary;
reg [3:0] multipleBinary;
always @(*) begin
tenModulo = enteredInput % 10;
tenMultiple = enteredInput / 10;
case (tenModulo)
0: moduloBinary = 4'b0000;
1: moduloBinary = 4'b0001;
2: moduloBinary = 4'b0010;
3: moduloBinary = 4'b0011;
4: moduloBinary = 4'b0100;
5: moduloBinary = 4'b0101;
6: moduloBinary = 4'b0110;
7: moduloBinary = 4'b0111;
8: moduloBinary = 4'b1000;
9: moduloBinary = 4'b1001;
default: moduloBinary = 4'b1111;
endcase
case (tenMultiple)
0: multipleBinary = 4'b0000;
1: multipleBinary = 4'b0001;
2: multipleBinary = 4'b0010;
3: multipleBinary = 4'b0011;
4: multipleBinary = 4'b0100;
5: multipleBinary = 4'b0101;
6: multipleBinary = 4'b0110;
7: multipleBinary = 4'b0111;
8: multipleBinary = 4'b1000;
9: multipleBinary = 4'b1001;
default: multipleBinary = 4'b1111;
endcase
end
displayNumber displayModulo (
moduloBinary,
HEX0
);
displayNumber displayMultiple (
multipleBinary,
HEX1
);
endmodule
| 7.090007 |
module binary_7seg_converter (
input clk,
input [15:0] dispNum,
output reg [6:0] segments,
output reg [3:0] segsel
);
reg [6:0] decoder[0:15];
reg [1:0] seg_ctr = 2'b0;
reg [31:1] clk_dvdr = 0;
initial begin
$readmemb("nibble27seg_decoder", decoder);
end
always @(posedge clk) begin
if (clk_dvdr >= 50000) begin //Divide the 50Mhz input clock down to 1Khz
case (seg_ctr)
0: begin
segsel <= 4'b1110;
segments <= ~decoder[dispNum[3:0]];
end
1: begin
segsel <= 4'b1101;
segments <= ~decoder[dispNum[7:4]];
end
2: begin
segsel <= 4'b1011;
segments <= ~decoder[dispNum[11:8]];
end
3: begin
segsel <= 4'b0111;
segments <= ~decoder[dispNum[15:12]];
end
endcase
seg_ctr <= seg_ctr + 1;
clk_dvdr <= 0;
end else clk_dvdr <= clk_dvdr + 1;
end
endmodule
| 7.018841 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100;
4'b0101: displayer = 7'b0100100;
4'b0110: displayer = 7'b0100000;
4'b0111: displayer = 7'b0001111;
4'b1000: displayer = 7'b0000000;
4'b1001: displayer = 7'b0000100;
default: displayer = 7'b1111111;
endcase
endmodule
| 8.666146 |
module binary_7_bits_BCD (
input [9:0] SW,
output [0:6] HEX0,
HEX1,
HEX2,
output [9:0] LEDR
);
assign LEDR = SW;
integer enteredInput, tenModulo, tenMultiple, hundredMultiple;
always @(SW[6:0]) enteredInput = SW[6:0];
reg [3:0] moduloTen, multipleTen, multipleHundred;
always @(*) begin
tenModulo = enteredInput % 10;
tenMultiple = enteredInput / 10;
hundredMultiple = enteredInput / 100;
case (tenModulo)
0: moduloTen = 4'b0000;
1: moduloTen = 4'b0001;
2: moduloTen = 4'b0010;
3: moduloTen = 4'b0011;
4: moduloTen = 4'b0100;
5: moduloTen = 4'b0101;
6: moduloTen = 4'b0110;
7: moduloTen = 4'b0111;
8: moduloTen = 4'b1000;
9: moduloTen = 4'b1001;
default: moduloTen = 4'b1111;
endcase
case (tenMultiple)
0: multipleTen = 4'b0000;
1: multipleTen = 4'b0001;
2: multipleTen = 4'b0010;
3: multipleTen = 4'b0011;
4: multipleTen = 4'b0100;
5: multipleTen = 4'b0101;
6: multipleTen = 4'b0110;
7: multipleTen = 4'b0111;
8: multipleTen = 4'b1000;
9: multipleTen = 4'b1001;
default: multipleTen = 4'b1111;
endcase
case (hundredMultiple)
1: multipleHundred = 4'b0001;
default: multipleHundred = 4'b1111;
endcase
end
displayNumber displayHexZero (
moduloTen,
HEX0
);
displayNumber displayHexOne (
multipleTen,
HEX1
);
displayNumber displayHexTwo (
multipleHundred,
HEX2
);
endmodule
| 6.752796 |
module binary_8421 (
input wire clk, //系统时钟，频率50MHz
input wire rstn, //复位信号，低电平有效
input wire [19:0] data, //输入需要转换的数据
output reg [3:0] unit, //个位BCD码
output reg [3:0] ten, //十位BCD码
output reg [3:0] hun, //百位BCD码
output reg [3:0] tho, //千位BCD码
output reg [3:0] t_tho, //万位BCD码
output reg [3:0] h_hun //十万位BCD码
);
//********************************************************************//
//******************** Parameter And Internal Signal *****************//
//********************************************************************//
//reg define
reg [ 4:0] cnt_shift; //移位判断计数器
reg [43:0] data_shift; //移位判断数据寄存器
reg shift_flag; //移位判断标志信号
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//cnt_shift:从0到21循环计数
always @(posedge clk or negedge rstn)
if (rstn == 1'b0) cnt_shift <= 5'd0;
else if ((cnt_shift == 5'd21) && (shift_flag == 1'b1)) cnt_shift <= 5'd0;
else if (shift_flag == 1'b1) cnt_shift <= cnt_shift + 1'b1;
else cnt_shift <= cnt_shift;
//data_shift：计数器为0时赋初值，计数器为1~20时进行移位判断操作
always @(posedge clk or negedge rstn)
if (rstn == 1'b0) data_shift <= 44'b0;
else if (cnt_shift == 5'd0) data_shift <= {24'b0, data};
else if ((cnt_shift <= 20) && (shift_flag == 1'b0)) begin
data_shift[23:20] <= (data_shift[23:20] > 4) ? (data_shift[23:20] + 2'd3) : (data_shift[23:20]);
data_shift[27:24] <= (data_shift[27:24] > 4) ? (data_shift[27:24] + 2'd3) : (data_shift[27:24]);
data_shift[31:28] <= (data_shift[31:28] > 4) ? (data_shift[31:28] + 2'd3) : (data_shift[31:28]);
data_shift[35:32] <= (data_shift[35:32] > 4) ? (data_shift[35:32] + 2'd3) : (data_shift[35:32]);
data_shift[39:36] <= (data_shift[39:36] > 4) ? (data_shift[39:36] + 2'd3) : (data_shift[39:36]);
data_shift[43:40] <= (data_shift[43:40] > 4) ? (data_shift[43:40] + 2'd3) : (data_shift[43:40]);
end else if ((cnt_shift <= 20) && (shift_flag == 1'b1)) data_shift <= data_shift << 1;
else data_shift <= data_shift;
//shift_flag：移位判断标志信号，用于控制移位判断的先后顺序
always @(posedge clk or negedge rstn)
if (rstn == 1'b0) shift_flag <= 1'b0;
else shift_flag <= ~shift_flag;
//当计数器等于20时，移位判断操作完成，对各个位数的BCD码进行赋值
always @(posedge clk or negedge rstn)
if (rstn == 1'b0) begin
unit <= 4'b0;
ten <= 4'b0;
hun <= 4'b0;
tho <= 4'b0;
t_tho <= 4'b0;
h_hun <= 4'b0;
end else if (cnt_shift == 5'd21) begin
unit <= data_shift[23:20];
ten <= data_shift[27:24];
hun <= data_shift[31:28];
tho <= data_shift[35:32];
t_tho <= data_shift[39:36];
h_hun <= data_shift[43:40];
end
endmodule
| 7.743115 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100;
4'b0101: displayer = 7'b0100100;
4'b0110: displayer = 7'b0100000;
4'b0111: displayer = 7'b0001111;
4'b1000: displayer = 7'b0000000;
4'b1001: displayer = 7'b0000100;
default: displayer = 7'b1111111;
endcase
endmodule
| 8.666146 |
module binary_8_bits_BCD (
input [9:0] SW,
output [0:6] HEX0,
HEX1,
HEX2,
output [9:0] LEDR
);
assign LEDR = SW;
integer enteredInput, tenModulo, tenMultiple, hundredMultiple;
always @(SW[7:0]) enteredInput = SW[7:0];
reg [3:0] moduloTen, multipleTen, multipleHundred;
always @(*) begin
tenModulo = enteredInput % 10;
tenMultiple = (enteredInput / 10) % 10;
hundredMultiple = (enteredInput / 100) % 10;
case (tenModulo)
0: moduloTen = 4'b0000;
1: moduloTen = 4'b0001;
2: moduloTen = 4'b0010;
3: moduloTen = 4'b0011;
4: moduloTen = 4'b0100;
5: moduloTen = 4'b0101;
6: moduloTen = 4'b0110;
7: moduloTen = 4'b0111;
8: moduloTen = 4'b1000;
9: moduloTen = 4'b1001;
default: moduloTen = 4'b1111;
endcase
case (tenMultiple)
0: multipleTen = 4'b0000;
1: multipleTen = 4'b0001;
2: multipleTen = 4'b0010;
3: multipleTen = 4'b0011;
4: multipleTen = 4'b0100;
5: multipleTen = 4'b0101;
6: multipleTen = 4'b0110;
7: multipleTen = 4'b0111;
8: multipleTen = 4'b1000;
9: multipleTen = 4'b1001;
default: multipleTen = 4'b1111;
endcase
case (hundredMultiple)
1: multipleHundred = 4'b0001;
2: multipleHundred = 4'b0010;
default: multipleHundred = 4'b1111;
endcase
end
displayNumber displayHexZero (
moduloTen,
HEX0
);
displayNumber displayHexOne (
multipleTen,
HEX1
);
displayNumber displayHexTwo (
multipleHundred,
HEX2
);
endmodule
| 6.619261 |
module displayNumber (
input [3:0] decimalNumber,
output reg [0:6] displayer
);
always @(*)
case (decimalNumber)
4'b0000: displayer = 7'b0000001;
4'b0001: displayer = 7'b1001111;
4'b0010: displayer = 7'b0010010;
4'b0011: displayer = 7'b0000110;
4'b0100: displayer = 7'b1001100;
4'b0101: displayer = 7'b0100100;
4'b0110: displayer = 7'b0100000;
4'b0111: displayer = 7'b0001111;
4'b1000: displayer = 7'b0000000;
4'b1001: displayer = 7'b0000100;
default: displayer = 7'b1111111;
endcase
endmodule
| 8.666146 |
module tb_binary_array_multiplier_4bit ();
wire [7:0] out;
reg [3:0] x, y;
binary_array_multiplier_4bit uut (
out,
x,
y
);
initial begin
#00 x = 4'b1011;
y = 4'b1110;
#10 $finish;
end
initial begin
$dumpfile("binary_array_multiplier_4bit.vcd");
$dumpvars;
end
endmodule
| 7.496605 |
module half_adder (
sum,
carry,
a,
b
);
output sum, carry;
input a, b;
assign sum = a ^ b;
assign carry = a & b;
endmodule
| 6.966406 |
module add_3 (
in,
out
);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule
| 7.418891 |
module binary_BCD_4_bits (
input [3:0] SW,
output reg [0:6] HEX0,
HEX1
);
always @(SW)
case (SW[3:0])
0: begin
HEX0 = 7'b0000001;
HEX1 = 7'b0000001;
end
1: begin
HEX0 = 7'b1001111;
HEX1 = 7'b0000001;
end
2: begin
HEX0 = 7'b0010010;
HEX1 = 7'b0000001;
end
3: begin
HEX0 = 7'b0000110;
HEX1 = 7'b0000001;
end
4: begin
HEX0 = 7'b1001100;
HEX1 = 7'b0000001;
end
5: begin
HEX0 = 7'b0100100;
HEX1 = 7'b0000001;
end
6: begin
HEX0 = 7'b0100000;
HEX1 = 7'b0000001;
end
7: begin
HEX0 = 7'b0001111;
HEX1 = 7'b0000001;
end
8: begin
HEX0 = 7'b0000000;
HEX1 = 7'b0000001;
end
9: begin
HEX0 = 7'b0000100;
HEX1 = 7'b0000001;
end
10: begin
HEX0 = 7'b0000001;
HEX1 = 7'b1001111;
end
11: begin
HEX0 = 7'b1001111;
HEX1 = 7'b1001111;
end
12: begin
HEX0 = 7'b0010010;
HEX1 = 7'b1001111;
end
13: begin
HEX0 = 7'b0000110;
HEX1 = 7'b1001111;
end
14: begin
HEX0 = 7'b1001100;
HEX1 = 7'b1001111;
end
15: begin
HEX0 = 7'b0100100;
HEX1 = 7'b1001111;
end
default: begin
HEX0 = 7'b1111111;
HEX1 = 7'b1111111;
end
endcase
endmodule
| 6.686256 |
module binary_bcd_4_bits_board (
input [3:0] SW,
output [6:0] HEX0,
output [6:0] HEX1
);
binary_BCD_4_bits(
SW, HEX0, HEX1
);
endmodule
| 8.169419 |
module binary_counter #(
parameter WIDTH = 16
) (
input clk,
enable,
reset,
output reg [WIDTH-1:0] count
);
// Reset if needed, or increment if counting is enabled
always @(posedge clk or posedge reset) begin
if (reset) count <= 0;
else if (enable == 1'b1) count <= count + 1;
end
endmodule
| 6.540334 |
module d_ff_reset_en_tb;
reg clk;
reg reset;
wire [7:0] q;
wire max_tick;
binary_counter circuit1 (
clk,
reset,
q,
max_tick
);
always begin
clk = ~clk;
#10;
end
initial begin
$dumpfile("test.vcd");
$dumpvars(0, binary_counter);
clk <= 0;
reset <= 1;
#20;
reset <= 0;
#20;
#20;
#20;
#20;
$finish;
end
initial begin
$monitor("clk = %b, reset = %b, q = %b max_tick = %b", clk, reset, q, max_tick);
end
endmodule
| 6.62678 |
module binary_counter_virtex5_11_0_dfcd34dfb8805954 (
ce,
sinit,
clk,
q
) /* synthesis syn_black_box syn_noprune=1 */;
input ce;
input sinit;
input clk;
output [1 : 0] q;
// synthesis translate_off
wire \BU2/N0 ;
wire \BU2/thresh0 ;
wire NLW_VCC_P_UNCONNECTED;
wire NLW_GND_G_UNCONNECTED;
wire [1 : 0] NlwRenamedSig_OI_q;
wire [0 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/halfsum ;
wire [0 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple ;
wire [1 : 0] \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s ;
assign q[1] = NlwRenamedSig_OI_q[1], q[0] = NlwRenamedSig_OI_q[0];
VCC VCC_0 (.P(NLW_VCC_P_UNCONNECTED));
GND GND_1 (.G(NLW_GND_G_UNCONNECTED));
INV \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/halfsum_not00001_INV_0 (
.I(NlwRenamedSig_OI_q[0]),
.O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/halfsum [0])
);
MUXCY \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.carrymux0 (
.CI(\BU2/N0 ),
.DI(\BU2/thresh0 ),
.S(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/halfsum [0]),
.O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple [0])
);
XORCY \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.carryxor0 (
.CI(\BU2/N0 ),
.LI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/halfsum [0]),
.O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [0])
);
XORCY \BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_simple_model.i_gt_1.carryxortop (
.CI(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/carry_simple [0]),
.LI(NlwRenamedSig_OI_q[1]),
.O(\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [1])
);
FDRE #(
.INIT(1'b0)
)
\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/fd/output_1
(
.C (clk),
.CE(ce),
.D (\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [0]),
.R (sinit),
.Q (NlwRenamedSig_OI_q[0])
);
FDRE #(
.INIT(1'b0)
)
\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/no_pipelining.the_addsub/i_lut6.i_lut6_addsub/i_q.i_simple.qreg/fd/output_2
(
.C (clk),
.CE(ce),
.D (\BU2/U0/i_baseblox.i_baseblox_counter/the_addsub/s [1]),
.R (sinit),
.Q (NlwRenamedSig_OI_q[1])
);
VCC \BU2/XST_VCC (.P(\BU2/thresh0 ));
GND \BU2/XST_GND (.G(\BU2/N0 ));
// synthesis translate_on
endmodule
| 6.540334 |
module accepts a binary input of the specified
* width and produces an output of 2^n width. If ACTIVE_HIGH
* is set to 1, the output will be one-hot, otherwise it
* will be one-cold. Due to the parametric nature of this decoder,
* the decoding is performed by shifting a single bit by the input
* value, rather than using a multiplexer.
*/
module binary_decoder #(
parameter WIDTH = 3, // choose number of input (address) lines
parameter ACTIVE_HIGH = 0 // choose one-hot (1) or one-cold (0) encoding
)(
input [WIDTH-1 : 0] in,
input enable,
output [OUT_WIDTH-1 : 0] out
);
localparam OUT_WIDTH = 1 << WIDTH;
wire [OUT_WIDTH-1 : 0] one_hot = (enable) ? (1'b1 << in) : 1'b0;
assign out = (ACTIVE_HIGH) ? one_hot : ~one_hot;
endmodule
| 8.776274 |
module binary_decoder_2x4 (
input en,
input [1:0] a,
output [3:0] bcode
);
assign bcode[0] = en && !a[1] && !a[0],
bcode[1] = en && !a[1] && a[0],
bcode[2] = en && a[1] && !a[0],
bcode[3] = en && a[1] && a[0];
endmodule
| 6.738522 |
module binary_decoder_2x4_TB;
// Inputs
reg en;
reg [1:0] a;
// Outputs
wire [3:0] bcode;
// Instantiate the Unit Under Test (UUT)
binary_decoder_2x4 uut (
.en(en),
.a(a),
.bcode(bcode)
);
reg [3:0] counter;
initial begin
$display("en a[1] a[0] bcode");
for (counter = 0; counter <= 7; counter = counter + 1'b1) begin
{en, a} = counter[2:0];
$strobe("%b %b %b %b", en, a[1], a[0], bcode);
#10;
end
end
endmodule
| 6.738522 |
module binary_decoder_3x8 (
input [2:0] a,
output [7:0] bcode
);
binary_decoder_2x4 m0 (
.en({!a[2]}),
.a(a[1:0]),
.bcode(bcode[3:0])
);
binary_decoder_2x4 m1 (
.en(a[2]),
.a(a[1:0]),
.bcode(bcode[7:4])
);
endmodule
| 6.738522 |
module binary_decoder_3x8_TB;
// Inputs
reg [2:0] a;
// Outputs
wire [7:0] bcode;
// Instantiate the Unit Under Test (UUT)
binary_decoder_3x8 uut (
.a(a),
.bcode(bcode)
);
reg [3:0] counter;
initial begin
$display("a[2] a[1] a[0] bcode");
for (counter = 0; counter <= 7; counter = counter + 1'b1) begin
a = counter[2:0];
$strobe(" %b %b %b %b", a[2], a[1], a[0], bcode);
#10;
end
end
endmodule
| 6.738522 |
module binary_decoder_4x16 (
input [ 3:0] a,
output [15:0] bcode
);
binary_decoder_2x4 m0 (
.en({!a[3] && !a[2]}),
.a(a[1:0]),
.bcode(bcode[3:0])
);
binary_decoder_2x4 m1 (
.en({!a[3] && a[2]}),
.a(a[1:0]),
.bcode(bcode[7:4])
);
binary_decoder_2x4 m2 (
.en({a[3] && !a[2]}),
.a(a[1:0]),
.bcode(bcode[11:8])
);
binary_decoder_2x4 m3 (
.en({a[3] && a[2]}),
.a(a[1:0]),
.bcode(bcode[15:12])
);
endmodule
| 6.738522 |
module binary_decoder_4x16_TB;
// Inputs
reg [ 3:0] a;
// Outputs
wire [15:0] bcode;
// Instantiate the Unit Under Test (UUT)
binary_decoder_4x16 uut (
.a(a),
.bcode(bcode)
);
reg [4:0] counter;
initial begin
$display("a[3] a[2] a[1] a[0] bcode");
for (counter = 0; counter <= 15; counter = counter + 1'b1) begin
a = counter[3:0];
$strobe(" %b %b %b %b %b", a[3], a[2], a[1], a[0], bcode);
#10;
end
end
endmodule
| 6.738522 |
modules/register_file_components/binary_decoder.v"
module binary_decoder_test;
reg [3:0]in;
reg load_enable;
wire [15:0] out;
binary_decoder decoder(out, in, load_enable);
initial #100 $finish;
initial fork
load_enable = 1'b0; #5 load_enable = 1'b1; #90 load_enable = 1'b0;
in = 4'b0000;
#10 repeat(18) #5 in = in + 4'b0001;
join
initial begin
$display("\n*** BINARY DECODER TEST ***");
$display ("\n input load_enable output \t\t\ttime");
$monitor(" %b %b %b %d", in, load_enable, out, $time);
end
endmodule
| 7.417915 |
module Binary_Gray #(
parameter N = 2
) (
i_Binary,
o_Gray
);
input wire [N-1:0] i_Binary;
output wire [N-1:0] o_Gray;
assign o_Gray = i_Binary ^ (i_Binary >> 1);
endmodule
| 8.894335 |
module binary_to_gray #(
parameter DATAWIDTH = 1
)(
input [DATAWIDTH-1:0] data_in,
output [DATAWIDTH-1:0] data_out;
);
assign data_out = data_in ^ (data_in >> 1);
endmodule
| 6.958902 |
module gray_to_binary #(
parameter DATAWIDTH = 1
)(
input [DATAWIDTH-1:0] data_in,
output [DATAWIDTH-1:0] data_out;
);
assign data_out[DATAWIDTH-1] = data_in[DATAWIDTH-1];
always @(*) begin
for (int i=DATAWIDTH-2 ; i>-1 ; i--)
data_out[i] = data_out[i+1] ^ data_in[i];
end
endmodule
| 8.07018 |
module Binary_Gray_t ();
parameter N = 8;
reg [N-1:0] i_Binary;
wire [N-1:0] o_Gray;
Binary_Gray #(N) U1 (
i_Binary,
o_Gray
);
initial begin
#10 i_Binary = 8'b00101110;
end
endmodule
| 7.38161 |
module Binary_to_7Seg (
output reg [7:0] Y,
input [3:0] I
);
always @(I) begin
case (I)
4'b0000: Y = 7'b1111110;
4'b0001: Y = 7'b0110000;
4'b0010: Y = 7'b1101101;
4'b0011: Y = 7'b1111001;
4'b0100: Y = 7'b0110011;
4'b0101: Y = 7'b1011011;
4'b0110: Y = 7'b1011111;
4'b0111: Y = 7'b1110000;
4'b1000: Y = 7'b1111111;
4'b1001: Y = 7'b1110011;
4'b1010: Y = 7'b1001111;
4'b1011: Y = 7'b1001111;
4'b1100: Y = 7'b1001111;
4'b1101: Y = 7'b1001111;
4'b1110: Y = 7'b1001111;
4'b1111: Y = 7'b1001111;
endcase
end
endmodule
| 7.358073 |
module Binary_To_7Segment (
input i_Clk,
input [3:0] i_Binary_Num,
output o_Segment_A,
output o_Segment_B,
output o_Segment_C,
output o_Segment_D,
output o_Segment_E,
output o_Segment_F,
output o_Segment_G
);
reg [6:0] r_Hex_Encoding = 7'h00;
// purpose: create a case statement for all possible input binary numbers.
// drives r_Hex_Encoding appropriately for each input combination
always @(posedge i_Clk) begin
case (i_Binary_Num)
4'b0000: r_Hex_Encoding <= 7'h7E;
4'b0001: r_Hex_Encoding <= 7'h30;
4'b0010: r_Hex_Encoding <= 7'h6D;
4'b0011: r_Hex_Encoding <= 7'h79;
4'b0100: r_Hex_Encoding <= 7'h33;
4'b0101: r_Hex_Encoding <= 7'h5B;
4'b0110: r_Hex_Encoding <= 7'h5F;
4'b0111: r_Hex_Encoding <= 7'h70;
4'b1000: r_Hex_Encoding <= 7'h7F;
4'b1001: r_Hex_Encoding <= 7'h7B;
4'b1010: r_Hex_Encoding <= 7'h77;
4'b1011: r_Hex_Encoding <= 7'h1F;
4'b1100: r_Hex_Encoding <= 7'h4E;
4'b1101: r_Hex_Encoding <= 7'h3D;
4'b1110: r_Hex_Encoding <= 7'h4F;
4'b1111: r_Hex_Encoding <= 7'h47;
endcase
end
assign o_Segment_A = r_Hex_Encoding[6];
assign o_Segment_B = r_Hex_Encoding[5];
assign o_Segment_C = r_Hex_Encoding[4];
assign o_Segment_D = r_Hex_Encoding[3];
assign o_Segment_E = r_Hex_Encoding[2];
assign o_Segment_F = r_Hex_Encoding[1];
assign o_Segment_G = r_Hex_Encoding[0];
endmodule
| 7.259362 |
module binary_to_7_segment (
i,
D,
d,
ctrl
);
input [3:0] i; //i represents for 4-bit binary input
output [7:0] D; //ssd decoder
output [3:0] d; //LED controller
output [3:0] ctrl;
reg [7:0] D;
reg [3:0] d;
reg [3:0] ctrl;
always @* begin
case (i)
4'b0000: D = `SS_0;
4'b0001: D = `SS_1;
4'b0010: D = `SS_2;
4'b0011: D = `SS_3;
4'b0100: D = `SS_4;
4'b0101: D = `SS_5;
4'b0110: D = `SS_6;
4'b0111: D = `SS_7;
4'b1000: D = `SS_8;
4'b1001: D = `SS_9;
4'b1010: D = `SS_A;
4'b1011: D = `SS_b;
4'b1100: D = `SS_C;
4'b1101: D = `SS_d;
4'b1110: D = `SS_E;
4'b1111: D = `SS_F;
endcase
d = i;
ctrl = 4'b0000;
end
endmodule
| 7.316503 |
module binary_to_bcd1 (
clk_i,
ce_i,
rst_i,
start_i,
dat_binary_i,
dat_bcd_o,
done_o
);
parameter BITS_IN_PP = 32; // # of bits of binary input
parameter BCD_DIGITS_OUT_PP = 5; // # of digits of BCD output
parameter BIT_COUNT_WIDTH_PP = 16; // Width of bit counter
// I/O declarations
input clk_i; // clock signal
input ce_i; // clock enable input
input rst_i; // synchronous reset
input start_i; // initiates a conversion
input [BITS_IN_PP-1:0] dat_binary_i; // input bus
output [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o; // output bus
output done_o; // indicates conversion is done
reg [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;
// Internal signal declarations
reg [BITS_IN_PP-1:0] bin_reg;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_reg;
wire [BITS_IN_PP-1:0] bin_next;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_next;
reg busy_bit;
reg [BIT_COUNT_WIDTH_PP-1:0] bit_count;
wire bit_count_done;
//--------------------------------------------------------------------------
// Functions & Tasks
//--------------------------------------------------------------------------
function [4*BCD_DIGITS_OUT_PP-1:0] bcd_asl;
input [4*BCD_DIGITS_OUT_PP-1:0] din;
input newbit;
integer k;
reg cin;
reg [3:0] digit;
reg [3:0] digit_less;
begin
cin = newbit;
for (k = 0; k < BCD_DIGITS_OUT_PP; k = k + 1) begin
digit[3] = din[4*k+3];
digit[2] = din[4*k+2];
digit[1] = din[4*k+1];
digit[0] = din[4*k];
digit_less = digit - 5;
if (digit > 4'b0100) begin
bcd_asl[4*k+3] = digit_less[2];
bcd_asl[4*k+2] = digit_less[1];
bcd_asl[4*k+1] = digit_less[0];
bcd_asl[4*k+0] = cin;
cin = 1'b1;
end else begin
bcd_asl[4*k+3] = digit[2];
bcd_asl[4*k+2] = digit[1];
bcd_asl[4*k+1] = digit[0];
bcd_asl[4*k+0] = cin;
cin = 1'b0;
end
end // end of for loop
end
endfunction
//--------------------------------------------------------------------------
// Module code
//--------------------------------------------------------------------------
// Perform proper shifting, binary ASL and BCD ASL
assign bin_next = {bin_reg, 1'b0};
always @(bcd_reg or bin_reg) begin
bcd_next <= bcd_asl(bcd_reg, bin_reg[BITS_IN_PP-1]);
end
// Busy bit, input and output registers
always @(posedge clk_i) begin
if (rst_i) begin
busy_bit <= 0; // Synchronous reset
dat_bcd_o <= 0;
end else if (start_i && ~busy_bit) begin
busy_bit <= 1;
bin_reg <= dat_binary_i;
bcd_reg <= 0;
end else if (busy_bit && ce_i && bit_count_done && ~start_i) begin
busy_bit <= 0;
dat_bcd_o <= bcd_next;
end else if (busy_bit && ce_i && ~bit_count_done) begin
bcd_reg <= bcd_next;
bin_reg <= bin_next;
end
end
assign done_o = ~busy_bit;
// Bit counter
always @(posedge clk_i) begin
if (~busy_bit) bit_count <= 0;
else if (ce_i && ~bit_count_done) bit_count <= bit_count + 1;
end
assign bit_count_done = (bit_count == (BITS_IN_PP - 1));
endmodule
| 8.011872 |
module binary_to_bcd2 (
clk_i,
ce_i,
rst_i,
start_i,
dat_binary_i,
dat_bcd_o,
done_o
);
parameter BITS_IN_PP = 32; // # of bits of binary input
parameter BCD_DIGITS_OUT_PP = 6; // # of digits of BCD output
parameter BIT_COUNT_WIDTH_PP = 16; // Width of bit counter
// I/O declarations
input clk_i; // clock signal
input ce_i; // clock enable input
input rst_i; // synchronous reset
input start_i; // initiates a conversion
input [BITS_IN_PP-1:0] dat_binary_i; // input bus
output [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o; // output bus
output done_o; // indicates conversion is done
reg [4*BCD_DIGITS_OUT_PP-1:0] dat_bcd_o;
// Internal signal declarations
reg [BITS_IN_PP-1:0] bin_reg;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_reg;
wire [BITS_IN_PP-1:0] bin_next;
reg [4*BCD_DIGITS_OUT_PP-1:0] bcd_next;
reg busy_bit;
reg [BIT_COUNT_WIDTH_PP-1:0] bit_count;
wire bit_count_done;
//--------------------------------------------------------------------------
// Functions & Tasks
//--------------------------------------------------------------------------
function [4*BCD_DIGITS_OUT_PP-1:0] bcd_asl;
input [4*BCD_DIGITS_OUT_PP-1:0] din;
input newbit;
integer k;
reg cin;
reg [3:0] digit;
reg [3:0] digit_less;
begin
cin = newbit;
for (k = 0; k < BCD_DIGITS_OUT_PP; k = k + 1) begin
digit[3] = din[4*k+3];
digit[2] = din[4*k+2];
digit[1] = din[4*k+1];
digit[0] = din[4*k];
digit_less = digit - 5;
if (digit > 4'b0100) begin
bcd_asl[4*k+3] = digit_less[2];
bcd_asl[4*k+2] = digit_less[1];
bcd_asl[4*k+1] = digit_less[0];
bcd_asl[4*k+0] = cin;
cin = 1'b1;
end else begin
bcd_asl[4*k+3] = digit[2];
bcd_asl[4*k+2] = digit[1];
bcd_asl[4*k+1] = digit[0];
bcd_asl[4*k+0] = cin;
cin = 1'b0;
end
end // end of for loop
end
endfunction
//--------------------------------------------------------------------------
// Module code
//--------------------------------------------------------------------------
// Perform proper shifting, binary ASL and BCD ASL
assign bin_next = {bin_reg, 1'b0};
always @(bcd_reg or bin_reg) begin
bcd_next <= bcd_asl(bcd_reg, bin_reg[BITS_IN_PP-1]);
end
// Busy bit, input and output registers
always @(posedge clk_i) begin
if (rst_i) begin
busy_bit <= 0; // Synchronous reset
dat_bcd_o <= 0;
end else if (start_i && ~busy_bit) begin
busy_bit <= 1;
bin_reg <= dat_binary_i;
bcd_reg <= 0;
end else if (busy_bit && ce_i && bit_count_done && ~start_i) begin
busy_bit <= 0;
dat_bcd_o <= bcd_next;
end else if (busy_bit && ce_i && ~bit_count_done) begin
bcd_reg <= bcd_next;
bin_reg <= bin_next;
end
end
assign done_o = ~busy_bit;
// Bit counter
always @(posedge clk_i) begin
if (~busy_bit) bit_count <= 0;
else if (ce_i && ~bit_count_done) bit_count <= bit_count + 1;
end
assign bit_count_done = (bit_count == (BITS_IN_PP - 1));
endmodule
| 8.011872 |
module binary_to_bcd_24bits (
input [23:0] binary,
output reg [3:0] reg_0,
output reg [3:0] reg_1,
output reg [3:0] reg_2,
output reg [3:0] reg_3,
output reg [3:0] reg_4,
output reg [3:0] reg_5,
output reg [3:0] reg_6,
output reg [3:0] reg_7
);
integer i;
always @(binary) begin
reg_0 = 4'd0;
reg_1 = 4'd0;
reg_2 = 4'd0;
reg_3 = 4'd0;
reg_4 = 4'd0;
reg_5 = 4'd0;
reg_6 = 4'd0;
reg_7 = 4'd0;
for (i = 23; i >= 0; i = i - 1) begin
if (reg_7 >= 5) begin
reg_7 = reg_7 + 3;
end
if (reg_6 >= 5) begin
reg_6 = reg_6 + 3;
end
if (reg_5 >= 5) begin
reg_5 = reg_5 + 3;
end
if (reg_4 >= 5) begin
reg_4 = reg_4 + 3;
end
if (reg_3 >= 5) begin
reg_3 = reg_3 + 3;
end
if (reg_2 >= 5) begin
reg_2 = reg_2 + 3;
end
if (reg_1 >= 5) begin
reg_1 = reg_1 + 3;
end
if (reg_0 >= 5) begin
reg_0 = reg_0 + 3;
end
reg_7 = reg_7 << 1;
reg_7[0] = reg_6[3];
reg_6 = reg_6 << 1;
reg_6[0] = reg_5[3];
reg_5 = reg_5 << 1;
reg_5[0] = reg_4[3];
reg_4 = reg_4 << 1;
reg_4[0] = reg_3[3];
reg_3 = reg_3 << 1;
reg_3[0] = reg_2[3];
reg_2 = reg_2 << 1;
reg_2[0] = reg_1[3];
reg_1 = reg_1 << 1;
reg_1[0] = reg_0[3];
reg_0 = reg_0 << 1;
reg_0[0] = binary[i];
end
end
endmodule
| 8.011872 |
module binary_to_bcd_core (
// signals
input wire clk,
input wire reset,
input wire start_conversion,
output reg end_of_conversion,
// data
input wire [7:0] binary_data, // 8-bit input binary value
output reg [11:0] bcd_data // 12-bit output bcd value
);
// state declarations
localparam idle = 1'b0, converting = 1'b1;
// signal declarations
reg state_reg, state_next;
reg [11:0] bcd_data_next;
reg [19:0] shift_reg, shift_reg_next;
reg [3:0] count, count_next;
reg end_of_conversion_next;
// state_updation_logic
always @(posedge (clk), posedge (reset)) begin
if (reset) begin
state_reg = idle;
bcd_data = 12'b0;
shift_reg = 20'b0;
count = 4'b0;
end_of_conversion = 1'b0;
end else begin
// the last activity should be the
// synchronous activity
state_reg = state_next;
bcd_data = bcd_data_next;
shift_reg = shift_reg_next;
count = count_next;
end_of_conversion = end_of_conversion_next;
end
end
// next state logic
always @* begin
// in idle state
if (state_reg == idle) begin
// moore signals
count_next <= 4'b0;
bcd_data_next <= bcd_data;
end_of_conversion_next <= 1'b0;
// mealey signals
if (start_conversion) begin
shift_reg_next <= {12'b0, binary_data};
state_next <= converting;
end else begin
shift_reg_next <= 20'b0;
state_next <= idle;
end
// in converting state
end else begin
if (count == 8) begin
shift_reg_next <= 20'b0;
count_next <= 4'b0;
bcd_data_next <= shift_reg[19:8];
state_next <= idle;
end_of_conversion_next <= 1'b1;
end else begin
count_next <= count + 1;
bcd_data_next <= bcd_data;
state_next <= converting;
end_of_conversion_next <= 1'b0;
// updating shift_reg_next
if (shift_reg[11:8] > 4'd4) begin
if (shift_reg[15:12] > 4'd4) begin
if (shift_reg[19:16] > 4'd4) begin
shift_reg_next <= {shift_reg[18:0] + 20'b0011_0011_0011_0000_0000, 1'b0};
end else begin
shift_reg_next <= {shift_reg[18:0] + 20'b0000_0011_0011_0000_0000, 1'b0};
end
end else begin
if (shift_reg[19:16] > 4'd4) begin
shift_reg_next <= {shift_reg[18:0] + 20'b0011_0000_0011_0000_0000, 1'b0};
end else begin
shift_reg_next <= {shift_reg[18:0] + 20'b0000_0000_0011_0000_0000, 1'b0};
end
end
end else begin
if (shift_reg[15:12] > 4'd4) begin
if (shift_reg[19:16] > 4'd4) begin
shift_reg_next <= {shift_reg[18:0] + 20'b0011_0011_0000_0000_0000, 1'b0};
end else begin
shift_reg_next <= {shift_reg[18:0] + 20'b0000_0011_0000_0000_0000, 1'b0};
end
end else begin
if (shift_reg[19:16] > 4'd4) begin
shift_reg_next <= {shift_reg[18:0] + 20'b0011_0000_0000_0000_0000, 1'b0};
end else begin
shift_reg_next <= {shift_reg[18:0], 1'b0};
end
end
end
end
end
end
endmodule
| 8.011872 |
module binary_to_bcd_seq (
input [23:0] binary,
output reg [3:0] hundred_thousand,
output reg [3:0] ten_thousand,
output reg [3:0] thousand,
output reg [3:0] hundred,
output reg [3:0] ten,
output reg [3:0] one
);
integer i;
always @(binary) begin
hundred_thousand = 4'd0;
ten_thousand = 4'd0;
thousand = 4'd0;
hundred = 4'd0;
ten = 4'd0;
one = 4'd0;
for (i = 23; i >= 0; i = i - 1) begin
if (hundred_thousand >= 5) begin
hundred_thousand = hundred_thousand + 3;
end
if (ten_thousand >= 5) begin
ten_thousand = ten_thousand + 3;
end
if (thousand >= 5) begin
thousand = thousand + 3;
end
if (hundred >= 5) begin
hundred = hundred + 3;
end
if (ten >= 5) begin
ten = ten + 3;
end
if (one >= 5) begin
one = one + 3;
end
hundred_thousand = hundred_thousand << 1;
hundred_thousand[0] = ten_thousand[3];
ten_thousand = ten_thousand << 1;
ten_thousand[0] = thousand[3];
thousand = thousand << 1;
thousand[0] = hundred[3];
hundred = hundred << 1;
hundred[0] = ten[3];
ten = ten << 1;
ten[0] = one[3];
one = one << 1;
one[0] = binary[i];
end
end
endmodule
| 8.011872 |
module binary_to_bcd_tb;
reg [31:0] ALUoutput;
wire [ 4:0] D1;
wire [ 4:0] D2;
wire [ 4:0] D3;
wire [ 4:0] D4;
wire [ 4:0] D5;
wire [ 4:0] D6;
wire [ 4:0] D7;
wire [ 4:0] D8;
wire [ 4:0] D9;
wire [ 4:0] D10;
sev_seg_disp disp1 (
.ALUoutput(ALUoutput),
.D1(D1),
.D2(D2),
.D3(D3),
.D4(D4),
.D5(D5),
.D6(D6),
.D7(D7),
.D8(D8),
.D9(D9),
.D10(D10)
);
initial begin
ALUoutput = 32'd12345;
#20;
$stop;
end
endmodule
| 8.011872 |
module binary_to_bcd_transcoder #(
// Input word size.
parameter WIDTH = 8,
// Output word size. User should not change default value as it
// is derived from input width to fit all output BCD digits.
parameter OUT_WIDTH = $rtoi($ceil($log10(2 ** WIDTH - 1))) * 4
) (
// Input binary data.
input wire [WIDTH-1:0] in,
// Output BCD data.
output wire [OUT_WIDTH-1:0] out,
input wire clk,
input wire reset_n
);
//
// This module implements "double-dabble" ("shift-and-add-3") algorithm.
// Refer to any other source for algorithm details.
//
function [3:0] add_3_if_5_or_above;
input [3:0] bcd;
begin
case (bcd)
4'd0: add_3_if_5_or_above = 4'd0;
4'd1: add_3_if_5_or_above = 4'd1;
4'd2: add_3_if_5_or_above = 4'd2;
4'd3: add_3_if_5_or_above = 4'd3;
4'd4: add_3_if_5_or_above = 4'd4;
4'd5: add_3_if_5_or_above = 4'd5 + 4'd3;
4'd6: add_3_if_5_or_above = 4'd6 + 4'd3;
4'd7: add_3_if_5_or_above = 4'd7 + 4'd3;
4'd8: add_3_if_5_or_above = 4'd8 + 4'd3;
4'd9: add_3_if_5_or_above = 4'd9 + 4'd3;
default: add_3_if_5_or_above = 4'dx;
endcase
end
endfunction
//
// One pass finishes in WIDTH cycles, Assign separate state to each cycle
// and advance unconditionally till the end state will be reached.
//
reg [WIDTH-1:0] state;
localparam STATE_INIT = {{WIDTH - 1{1'b0}}, 1'b1};
localparam STATE_READY = {1'b1, {WIDTH - 1{1'b0}}};
wire ready;
assign ready = state == STATE_READY;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
state <= STATE_INIT;
end else begin
state <= ready ? STATE_INIT : {state[WIDTH-2:0], 1'b0};
end
end
wire restart;
// Do not stop even if input was not changed.
assign restart = ready;
reg [WIDTH-1:0] src_reg;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
src_reg <= {WIDTH{1'b0}};
end else begin
src_reg <= restart ? in : {src_reg[WIDTH-2:0], 1'bx};
end
end
reg [OUT_WIDTH-1:0] dst_reg;
wire [ OUT_WIDTH:0] next_dst_reg;
assign next_dst_reg[0] = src_reg[WIDTH-1];
genvar i;
for (i = 0; i < OUT_WIDTH - 4; i = i + 4) begin : next_dst
assign next_dst_reg[4+i:1+i] = add_3_if_5_or_above(dst_reg[3+i:0+i]);
end
assign next_dst_reg[OUT_WIDTH:OUT_WIDTH-3] = add_3_if_5_or_above(
dst_reg[OUT_WIDTH-1:OUT_WIDTH-4]
);
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
dst_reg <= {OUT_WIDTH{1'b0}};
end else begin
dst_reg <= restart ? {OUT_WIDTH{1'b0}} : next_dst_reg[OUT_WIDTH-1:0];
end
end
reg [OUT_WIDTH-1:0] out_reg;
assign out = out_reg;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
out_reg <= 1'b0;
end else if (ready) begin
out_reg <= next_dst_reg[OUT_WIDTH-1:0];
end
end
`ifdef REUSABLES_CHECKERS_ENABLED
`include "std_ovl_defines.h"
ovl_one_hot #(
.severity_level(`OVL_ERROR),
.width(WIDTH),
.property_type(`OVL_ASSERT),
.msg("state is not one-hot"),
.coverage_level(`OVL_COVER_DEFAULT),
.clock_edge(`OVL_POSEDGE),
.reset_polarity(`OVL_ACTIVE_LOW),
.gating_type(`OVL_GATE_NONE)
) state_is_one_hot (
.clock(clk),
.reset(reset_n),
.enable(1'b0),
.test_expr(state),
.fire()
);
`endif
endmodule
| 8.011872 |
module binary_to_decimal (
input [15:0] in_binary,
output reg [15:0] out_decimal // 4 digits
);
localparam DIGITS = 4;
integer i;
integer scale;
reg [15:0] remainder_after_thousands;
reg [15:0] remainder_after_hundreds;
reg [15:0] remainder_after_tens;
/* Combinational Logic */
always @* begin
// thousands
for (i = 0; i < 10; i = i + 1) begin
scale = 1000;
if (in_binary >= (i * scale)) begin
out_decimal[15:12] = i;
remainder_after_thousands = in_binary - (i * scale);
end
end
// hundreds
for (i = 0; i < 10; i = i + 1) begin
scale = 100;
if (remainder_after_thousands >= (i * scale)) begin
out_decimal[11:8] = i;
remainder_after_hundreds = remainder_after_thousands - (i * scale);
end
end
// tens
for (i = 0; i < 10; i = i + 1) begin
scale = 10;
if (remainder_after_hundreds >= (i * scale)) begin
out_decimal[7:4] = i;
remainder_after_tens = remainder_after_hundreds - (i * scale);
end
end
// ones
for (i = 0; i < 10; i = i + 1) begin
scale = 1;
if (remainder_after_tens >= (i * scale)) begin
out_decimal[3:0] = i;
end
end
end
endmodule
| 8.149571 |
module Binary_to_Decimal_TB;
reg [3:0] Number;
wire [3:0] Dec;
integer i;
Binary_to_Decimal uut (
.Number(Number),
.Dec(Dec)
);
initial $monitor("Binary Number = %b | Decimal = %d", Number, Dec);
initial begin
Number = 0000;
for (i = 1; i < 16; i = i + 1) begin
#50 Number = Number + 4'b1;
end
end
initial #850 $finish;
endmodule
| 7.826153 |
module binary_to_gray (
input [3:0] B,
output [3:0] G
);
assign G[3] = B[3];
xor (G[2], B[3], B[2]);
xor (G[1], B[2], B[1]);
xor (G[0], B[1], B[0]);
endmodule
| 6.958902 |
module binary_to_hex_7segDecoder (
n,
hex_decoder
);
input [3:0] n; // 4 bit binary number
output [6:0] hex_decoder; // to display a single digit of hex number
assign hex_decoder[0] = ~((n[0] & n[2] & (~n[3])) | ((~n[0]) & (~n[2])) | ((~n[0]) & n[3]) | (n[1] & n[2]) | (n[1] & (~n[3])) | ((~n[1]) & (~n[2]) & n[3]));
assign hex_decoder[1] = ~((n[0] & n[1] & (~n[3])) | (n[0] & (~n[1]) & n[3]) | ((~n[0]) & (~n[1]) & (~n[3])) | ((~n[0]) & (~n[2])) | ((~n[2]) & (~n[3])));
assign hex_decoder[2] = ~((n[0] & (~n[1])) | (n[0] & (~n[2])) | ((~n[1]) & (~n[2])) | (n[2] & (~n[3])) | ((~n[2]) & n[3]));
assign hex_decoder[3] = ~((n[0] & n[1] & (~n[2])) | (n[0] & (~n[1]) & n[2]) | ((~n[0]) & n[1] & n[2]) | ((~n[0]) & (~n[2]) & (~n[3])) | ((~n[1]) & n[3]));
assign hex_decoder[4] = ~(((~n[0]) & n[1]) | ((~n[0]) & (~n[2])) | (n[1] & n[3]) | (n[2] & n[3]));
assign hex_decoder[5] = ~(((~n[0]) & (~n[1])) | ((~n[0]) & n[2]) | (n[1] & n[3]) | ((~n[1]) & n[2] & (~n[3])) | ((~n[2]) & n[3]));
assign hex_decoder[6] = ~((n[0] & (~n[1]) & n[2]) | ((~n[0]) & n[2] & (~n[3])) | (n[1] & (~n[2])) | (n[1] & n[3]) | ((~n[2]) & n[3]));
endmodule
| 7.148154 |
module binary_to_hex_7segDecoder_BEHAVIOURAL (
num,
hex_decoder
);
input [3:0] num; // 4 bit binary number
output reg [6:0] hex_decoder; // to display a single digit of hex number
always @(*) begin
case (num)
4'b0000: hex_decoder = 7'b0111111; // 0
4'b0001: hex_decoder = 7'b0000110; // 1
4'b0010: hex_decoder = 7'b1011011; // 2
4'b0011: hex_decoder = 7'b1001111; // 3
4'b0100: hex_decoder = 7'b1100110; // 4
4'b0101: hex_decoder = 7'b1101101; // 5
4'b0110: hex_decoder = 7'b1111101; // 6
4'b0111: hex_decoder = 7'b0000111; // 7
4'b1000: hex_decoder = 7'b1111111; // 8
4'b1001: hex_decoder = 7'b1101111; // 9
4'b1010: hex_decoder = 7'b1110111; // A
4'b1011: hex_decoder = 7'b1111100; // b
4'b1100: hex_decoder = 7'b1111001; // C
4'b1101: hex_decoder = 7'b1011110; // d
4'b1110: hex_decoder = 7'b1111001; // E
4'b1111: hex_decoder = 7'b1110001; // F
default: hex_decoder = 7'b0000000; // lights off
endcase
end
endmodule
| 7.148154 |
module binary_to_octal (
num,
hex_decoder
);
input [2:0] num;
output reg [6:0] hex_decoder;
always @(*) begin
case (num)
3'b000: hex_decoder = 7'b0111111; // 0
3'b001: hex_decoder = 7'b0000110; // 1
3'b010: hex_decoder = 7'b1011011; // 2
3'b011: hex_decoder = 7'b1001111; // 3
3'b100: hex_decoder = 7'b1100110; // 4
3'b101: hex_decoder = 7'b1101101; // 5
3'b110: hex_decoder = 7'b1111101; // 6
3'b111: hex_decoder = 7'b0000111; // 7
default: hex_decoder = 7'b0000000; // lights off
endcase
end
endmodule
| 8.021909 |
module binary_to_decimal (num, prev_left, prev_mid, hex_decoder);
input [3:0] num; // 4 bit binary number
input prev_left, prev_mid;
output reg [6:0] hex_decoder; // to display a single digit of hex number
wire carryin;
carryin = prev_mid & prev_left;
always @(*) begin
case(num)
4'b0000: hex_decoder = 7'b0111111; // 0
4'b0001: hex_decoder = 7'b0000110; // 1
4'b0010: hex_decoder = 7'b1011011; // 2
4'b0011: hex_decoder = 7'b1001111; // 3
4'b0100: hex_decoder = 7'b1100110; // 4
4'b0101: hex_decoder = 7'b1101101; // 5
4'b0110: hex_decoder = 7'b1111101; // 6
4'b0111: hex_decoder = 7'b0000111; // 7
4'b1000: hex_decoder = 7'b1111111; // 8
4'b1001: hex_decoder = 7'b1101111; // 9
default: hex_decoder = 7'b0000000; // lights off
endcase
end
endmodule
| 8.149571 |
module binary_to_hex_decoder (
cc,
HEXX
);
input [3:0] cc;
output [6:0] HEXX;
//integer HEX;
wire [3:0] c;
assign c = cc;
assign HEXX = HEX;
reg [6:0] HEX;
always @(c)
case (c)
4'b0000: begin
HEX[0] = 0;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 0;
HEX[4] = 0;
HEX[5] = 0;
HEX[6] = 1;
end
4'b0001: begin
HEX[0] = 1;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 1;
HEX[4] = 1;
HEX[5] = 1;
HEX[6] = 1;
end
4'b0010: begin
HEX[0] = 0;
HEX[1] = 0;
HEX[2] = 1;
HEX[3] = 0;
HEX[4] = 0;
HEX[5] = 1;
HEX[6] = 0;
end
4'b0011: begin
HEX[0] = 0;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 0;
HEX[4] = 1;
HEX[5] = 1;
HEX[6] = 0;
end
4'b0100: begin
HEX[0] = 1;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 1;
HEX[4] = 1;
HEX[5] = 0;
HEX[6] = 0;
end
4'b0101: begin
HEX[0] = 0;
HEX[1] = 1;
HEX[2] = 0;
HEX[3] = 0;
HEX[4] = 1;
HEX[5] = 0;
HEX[6] = 0;
end
4'b0110: begin
HEX[0] = 0;
HEX[1] = 1;
HEX[2] = 0;
HEX[3] = 0;
HEX[4] = 0;
HEX[5] = 0;
HEX[6] = 0;
end
4'b0111: begin
HEX[0] = 0;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 1;
HEX[4] = 1;
HEX[5] = 1;
HEX[6] = 1;
end
4'b1000: begin
HEX[0] = 0;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 0;
HEX[4] = 0;
HEX[5] = 0;
HEX[6] = 0;
end
4'b1001: begin
HEX[0] = 0;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 0;
HEX[4] = 1;
HEX[5] = 0;
HEX[6] = 0;
end
4'b1010: begin
HEX[0] = 0;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 1;
HEX[4] = 0;
HEX[5] = 0;
HEX[6] = 0;
end
4'b1011: begin
HEX[0] = 1;
HEX[1] = 1;
HEX[2] = 0;
HEX[3] = 0;
HEX[4] = 0;
HEX[5] = 0;
HEX[6] = 0;
end
4'b1100: begin
HEX[0] = 0;
HEX[1] = 1;
HEX[2] = 1;
HEX[3] = 0;
HEX[4] = 0;
HEX[5] = 0;
HEX[6] = 1;
end
4'b1101: begin
HEX[0] = 1;
HEX[1] = 0;
HEX[2] = 0;
HEX[3] = 0;
HEX[4] = 0;
HEX[5] = 1;
HEX[6] = 0;
end
4'b1110: begin
HEX[0] = 0;
HEX[1] = 1;
HEX[2] = 1;
HEX[3] = 0;
HEX[4] = 0;
HEX[5] = 0;
HEX[6] = 0;
end
4'b1111: begin
HEX[0] = 0;
HEX[1] = 1;
HEX[2] = 1;
HEX[3] = 1;
HEX[4] = 0;
HEX[5] = 0;
HEX[6] = 0;
end
endcase
endmodule
| 7.148154 |
module binary_to_hex_decoder_1_bit (
input x,
output reg [0:6] h
);
always @(x)
case (x)
0: h = 7'b1000000;
1: h = 7'b1111001;
endcase
endmodule
| 7.148154 |
module Binary_to_onehot (
dat1,
result1
);
parameter wid = 4;
parameter result_wid = 16;
input [wid-1:0] dat1;
output [result_wid -1:0] result1;
assign result1 = 1'b1 << dat1;
endmodule
| 7.192815 |
module Binary_to_onehot_tb ();
localparam wid = 4;
localparam result_wid = 16;
integer i;
reg [wid-1:0] dat1;
wire [result_wid-1:0] result1;
Binary_to_onehot dut (
dat1,
result1
);
initial begin
for (i = 0; i < 16; i = i + 1) begin
dat1 = i;
#5;
end
end
initial begin
$monitor("Binary Value: %b | One hot encoded value : %b", dat1, result1);
#300 $finish;
end
endmodule
| 7.192815 |
module binary_to_seg7 (
output reg [6:0] S,
input [1:0] I
);
always @(I) begin
case (I)
2'b00: S = 7'b1111100;
2'b01: S = 7'b0110000;
2'b10: S = 7'b1101101;
2'b11: S = 7'b1111001;
endcase
end
endmodule
| 6.681969 |
module binary_up_counter (
clk,
rst,
b
);
input clk, rst;
output [3:0] b;
wire clk_out;
reg [3:0] b;
reg [3:0] b_temp;
frequency_divider_exact_1hz(
.clk(clk), .rst(rst), .clk_out(clk_out)
);
always @* begin
b_temp = b + 1'b1;
end
always @(posedge clk_out or negedge rst) begin
if (~rst) b <= 4'b0000;
else b <= b_temp;
end
endmodule
| 6.586672 |
module binbcd4 (
input wire [3:0] b,
output wire [4:0] p
);
assign p[4] = b[3] & b[2] | b[3] & b[1];
assign p[3] = b[3] & ~b[2] & ~b[1];
assign p[2] = ~b[3] & b[2] | b[2] & b[1];
assign p[1] = b[3] & b[2] & ~b[1] | ~b[3] & b[1];
assign p[0] = b[0];
endmodule
| 6.502157 |
module binbcd8 (
input wire [7:0] b,
output reg [9:0] p
);
reg [17:0] z;
integer i;
always @(*) begin
for (i = 0; i <= 17; i = i + 1) z[i] = 0;
z[10:3] = b;
repeat (5) begin
if (z[11:8] > 4) z[11:8] = z[11:8] + 3;
if (z[15:12] > 4) z[15:12] = z[15:12] + 3;
z[17:1] = z[16:0];
end
p = z[17:8];
end
endmodule
| 6.582155 |
module binbcd8_top (
input wire clk,
input wire btn,
input wire [7:0] sw,
input wire [7:0] ld,
output wire [6:0] a_to_g,
output wire [3:0] an,
output wire dp
);
wire [15:0] x;
wire [ 9:0] p;
//串联0和binbcd8的输出
assign x = {6'b000000, p};
//在LED上显示开关的二进制值
assign ld = sw;
//在7段数码管上显示开关对应的十进制值
binbcd8 B1 (
.b(sw),
.p(p)
);
x7segb X2 (
.x(x),
.clk(clk),
.clr(btn),
.a_to_g(a_to_g),
.an(an),
.dp(dp)
);
endmodule
| 8.300688 |
module bincnt (
out, //counter output
clk, // clock
rst_n //active low reset
);
output [`CNT_BIT_WIDTH-1:0] out; // counter output
input clk; // clock
input rst_n; //active low reset
reg [`CNT_BIT_WIDTH-1:0] out; // counter output
reg [`CNT_BIT_WIDTH-1:0] tmp_cnt;
always @(out) tmp_cnt = out + 1'b1;
always @(posedge clk or negedge rst_n)
if (~rst_n) out <= 0;
else out <= tmp_cnt;
endmodule
| 6.559836 |
module binConv #(
parameter input_width = 25,
parameter popcount_width = 5
) (
input [input_width-1:0] recField,
input [input_width-1:0] weights,
input [popcount_width-1:0] thresh,
input [1:0] sign,
output outmap
);
wire [input_width-1:0] xnor_out;
wire [popcount_width-1:0] popcount_out;
wire multiplexer_0;
wire multiplexer_1;
wire multiplexer_2;
wire nultiplexer_3;
wire [popcount_width-1:0] comparator1_0;
wire [popcount_width-1:0] comparator1_1;
wire [popcount_width-1:0] comparator2_0;
wire [popcount_width-1:0] comparator2_1;
wire comparator1_out;
wire comparator2_out;
assign comparator1_0 = popcount_out;
assign comparator2_0 = popcount_out;
assign comparator1_1 = thresh;
assign comparator2_1 = thresh;
assign comparator1_out = (popcount_out > thresh) ? 1'b1 : 1'b0;
assign comparator2_out = (popcount_out < thresh) ? 1'b1 : 1'b0;
// comparators
genvar i;
for (i = 0; i < input_width; i = i + 1) begin
xnor (xnor_out[i], recField[i], weights[i]);
end
popcount #(
.input_width (input_width),
.output_width(popcount_width)
) binpopcount (
.data_in (xnor_out),
.data_out(popcount_out)
);
multiplexer4_1 sel (
.channel({1'b0, 1'b1, comparator1_out, comparator2_out}),
.sign(sign),
.outMap(outmap)
);
endmodule
| 7.307653 |
module binenc
#(parameter n = `DEFAULT_WIDTH)
(input [n-1:0] in,
output [$clog2(n)-1:0] out);
wire [$clog2(n)-1:0] o[n:0];
wire [n:0] found;
assign o[n] = 0;
assign found[n] = 0;
assign out = o[0];
generate
genvar i;
for (i = n - 1; i >= 0; i = i - 1)
begin
assign found[i] = found[i+1] | in[i];
assign o[i] = o[i+1] | (in[i] & ~found[i+1] ? i : 0);
end
endgenerate
endmodule
| 6.816267 |
module binenc_tb;
reg [7:0] in;
wire [2:0] out;
binenc #(8) enc (
.in (in),
.out(out)
);
integer i;
initial begin
$monitor("%b %d", in, out);
in = 'b0;
#255 $finish;
end
always #1 in = in + 1;
endmodule
| 6.56182 |
module bing (
input [ 3:0] a,
input [25:0] b,
output [31:0] c
);
assign c = {a, b, 2'b00}; //ڽPC31~28λλinstruct_indexϲ32λַ
endmodule
| 8.21404 |
module add_N_tb ();
// note this only runs for 50 cycles with the below settings
// alter TB_TIMEOUT to run longer
localparam TB_TIMEOUT = 100000;
localparam TB_CLK_PERIOD = 2000;
localparam TB_RST_PERIOD = 4000;
initial #(TB_TIMEOUT) $finish();
// clock
reg tb_clk = 1'b0;
always #(TB_CLK_PERIOD / 2) tb_clk = ~tb_clk;
// DUT
wire [`DATA_WIDTH-1 : 0] outp;
wire [`DATA_WIDTH-1 : 0] inps;
binomial_filter_test #(
.data_width(`DATA_WIDTH),
.num_elem (`NUM_ELEM)
) my_add_N_test (
.clk(tb_clk),
.outp(outp),
.outp_inps(inps)
);
// display inputs and output on each clock cycle
always @(posedge tb_clk) begin
$display("inps = ", inps, " => outp = ", outp);
end
endmodule
| 6.93342 |
module binops (
in_1,
in_2,
or_o,
nor_o,
and_o,
nand_o,
xor_o,
xnor_o,
add_o,
sub_o,
mul_o,
//div_o,
equ_o,
neq_o,
gt_o,
lt_o,
geq_o,
leq_o
);
input [`BITS-1:0] in_1, in_2;
output [`BITS-1:0] or_o, nor_o, and_o, nand_o, xor_o, xnor_o, add_o, sub_o, mul_o,
//div_o,
equ_o, neq_o, gt_o, lt_o, geq_o, leq_o;
assign or_o = in_1 | in_2;
assign nor_o = in_1~|in_2;
assign and_o = in_1 & in_2;
assign nand_o = in_1~&in_2;
assign xor_o = in_1 ^ in_2;
assign xnor_o = in_1 ~^ in_2;
assign add_o = in_1 + in_2;
assign sub_o = in_1 - in_2;
assign mul_o = in_1 * in_2;
//assign div_o = in_1 / in_2;
assign equ_o = in_1 == in_2;
assign neq_o = in_1 != in_2;
assign gt_o = in_1 > in_2;
assign lt_o = in_1 < in_2;
assign geq_o = in_1 >= in_2;
assign leq_o = in_1 <= in_2;
endmodule
| 6.506344 |
module binParaBCD (
input [25:0] bin,
output reg [3:0] dezmilhao,
output reg [3:0] milhao,
output reg [3:0] cemmil,
output reg [3:0] dezmil,
output reg [3:0] mil,
output reg [3:0] cem,
output reg [3:0] dez,
output reg [3:0] um
);
integer i;
always @(bin) begin
dezmilhao = 4'd0;
milhao = 4'd0;
cemmil = 4'd0;
dezmil = 4'd0;
mil = 4'd0;
cem = 4'd0;
dez = 4'd0;
um = 4'd0;
for (i = 25; i >= 0; i = i - 1) begin
// Adicionar 3 as colunas maiores que 5
if (dezmilhao >= 5) dezmilhao = dezmilhao + 3;
if (milhao >= 5) milhao = milhao + 3;
if (cemmil >= 5) cemmil = cemmil + 3;
if (dezmil >= 5) dezmil = dezmil + 3;
if (mil >= 5) mil = mil + 3;
if (cem >= 5) cem = cem + 3;
if (dez >= 5) dez = dez + 3;
if (um >= 5) um = um + 3;
//deslocamento esquerdo de 1
dezmilhao = dezmilhao << 1;
dezmilhao[0] = milhao[3];
milhao = milhao << 1;
milhao[0] = cemmil[3];
cemmil = cemmil << 1;
cemmil[0] = dezmil[3];
dezmil = dezmil << 1;
dezmil[0] = mil[3];
mil = mil << 1;
mil[0] = cem[3];
cem = cem << 1;
cem[0] = dez[3];
dez = dez << 1;
dez[0] = um[3];
um = um << 1;
um[0] = bin[i];
end
end
endmodule
| 7.023857 |
module topModule (
In,
Clk,
Seg_sel,
Seg_data,
Seg_debug,
LED_on,
Reset
);
input [11:0] In;
input Clk;
input Reset;
output [3:0] Seg_sel;
output [7:0] Seg_data;
// debug output
output [3:0] Seg_debug;
output LED_on;
assign LED_on = 1;
wire [3:0] bcd1, bcd2, bcd3;
wire carry1, carry2, carry3;
wire [7:0] seg1, seg2, seg3, seg4;
hex2bcd first (
In[3:0],
bcd1,
0,
carry1
);
hex2bcd second (
In[7:4],
bcd2,
carry1,
carry2
);
hex2bcd third (
In[11:8],
bcd3,
carry2,
carry3
);
bcd2SevSeg bcd2SevSeg1 (
bcd1,
seg1
);
bcd2SevSeg bcd2SevSeg2 (
bcd2,
seg2
);
bcd2SevSeg bcd2SevSeg3 (
bcd3,
seg3
);
bcd2SevSeg bcd2SevSeg4 (
{3'b0, carry3},
seg4
);
switch time_multiplexing (
Clk,
seg1,
seg2,
seg3,
seg4,
Seg_data,
Seg_sel,
Seg_debug,
Reset
);
endmodule
| 7.37158 |
module bcd2SevSeg (
in,
out
);
input [3:0] in;
output reg [7:0] out;
always @(*) begin
case (in)
0: out = 8'b00111111;
1: out = 8'b00000110;
2: out = 8'b01011011;
3: out = 8'b01001111;
4: out = 8'b01100110;
5: out = 8'b01101101;
6: out = 8'b01111101;
7: out = 8'b00000111;
8: out = 8'b01111111;
9: out = 8'b01101111;
default: out = 8'b0;
endcase
end
endmodule
| 6.749872 |
module switch (
clk,
bin1,
bin2,
bin3,
bin4,
seg_data,
seg_sel,
seg_debug,
reset
);
input clk;
input reset;
input [7:0] bin1;
input [7:0] bin2;
input [7:0] bin3;
input [7:0] bin4;
output reg [3:0] seg_debug;
output reg [3:0] seg_sel; //= 4'b0001;
output reg [7:0] seg_data;
reg [31:0] counter;
always @(posedge clk) begin
// reset function
if (reset == 0) begin
counter = 0;
seg_sel = 4'b0010;
end
counter = counter + 1;
if (counter > 40000) begin
seg_sel = {seg_sel[2:0], seg_sel[3]};
seg_debug = seg_sel;
counter = 0;
end
case (seg_sel)
1: seg_data = bin1;
2: seg_data = bin2;
3: seg_data = bin3;
4: seg_data = bin4;
//default:
//seg_data = 8'b0;
endcase
end
endmodule
| 6.864438 |
module binto7seg(
input clk,
input [3:0] binary,
output reg [6:0] seg
);
always @(posedge clk)
case (binary)
4'b0000 : //Hexadecimal 0
seg = 7'b1000000;
4'b0001 : //Hexadecimal 1
seg = 7'b1111001;
4'b0010 : // Hexadecimal 2
seg = 7'b0100100;
4'b0011 : // Hexadecimal 3
seg = 7'b0110000;
4'b0100 : // Hexadecimal 4
seg = 7'b0011001;
4'b0101 : // Hexadecimal 5
seg = 7'b0010010;
4'b0110 : // Hexadecimal 6
seg = 7'b0000010;
4'b0111 : // Hexadecimal 7
seg = 7'b1111000;
4'b1000 : //Hexadecimal 8
seg = 7'b0000000;
4'b1001 : //Hexadecimal 9
seg = 7'b0010000;
4'b1010 : // Hexadecimal A
seg = 7'b0001000;
4'b1011 : // Hexadecimal B
seg = 7'b0000011;
4'b1100 : // Hexadecimal C
seg = 7'b1000110;
4'b1101 : // Hexadecimal D
seg = 7'b0100001;
4'b1110 : // Hexadecimal E
seg = 7'b0000110;
4'b1111 : // Hexadecimal F
seg = 7'b0001110;
endcase
endmodule
| 6.934714 |
module BinToBCD (
Bin,
BCD
); //ת3BCD
integer i;
//
input [31:0] Bin; //Ķ
output [31:0] BCD; //ʮBCD
reg [3:0] Thousands, Hundreds, Tens, Ones; //3BCD
assign BCD = {Thousands, Hundreds, Tens, Ones};
always @(Bin) begin
Thousands = 4'd0;
Hundreds = 4'd0;
Tens = 4'd0;
Ones = 4'd0;
for (i = 31; i >= 0; i = i - 1) begin
if (Thousands >= 5) Thousands = Thousands + 3;
if (Hundreds >= 5) Hundreds = Hundreds + 3;
if (Tens >= 5) Tens = Tens + 3;
if (Ones >= 5) Ones = Ones + 3;
Thousands = Thousands << 1;
Thousands[0] = Hundreds[3];
Hundreds = Hundreds << 1;
Hundreds[0] = Tens[3];
Tens = Tens << 1;
Tens[0] = Ones[3];
Ones = Ones << 1;
Ones[0] = Bin[i];
end
end
endmodule
| 6.501169 |
module BinToBCD_8bit (
input [7:0] bin,
output reg [7:0] bcd
);
reg [7:0] binin;
always @bin begin
binin = bin;
bcd[3:0] = binin % 10;
binin = binin / 10;
bcd[7:4] = binin % 10;
end
endmodule
| 7.073231 |
module BinToBCD_m2 (
input [7:0] bin_in,
input sampling,
input clk,
input rst,
output flag,
output [9:0] bcd_out
);
reg [17:0] bcd_out_r;
reg [17:0] tmp_bcd_out_r;
reg [ 5:0] counter;
assign bcd_out = (counter == 5'd15) ? bcd_out_r[17:8] : 'b0;
assign flag = (counter == 5'd15) ? 1'b1 : 'b0;
always @(posedge clk) begin
if (rst) begin
counter <= 'b0;
bcd_out_r <= bin_in;
tmp_bcd_out_r <= bin_in;
end else if (sampling || (counter == 5'd15)) begin
counter <= 'b0;
bcd_out_r <= bin_in;
tmp_bcd_out_r <= bin_in;
end else begin
if (counter[0] == 0) begin
bcd_out_r[17:1] <= bcd_out_r[16:0];
tmp_bcd_out_r[17:1] <= bcd_out_r[16:0];
counter <= counter + 1;
end else begin
if (tmp_bcd_out_r[11:8] >= 3'd5) begin
bcd_out_r[11:8] <= bcd_out_r[11:8] + 4'b0011;
end else begin
bcd_out_r[11:8] <= bcd_out_r[11:8];
end
if (tmp_bcd_out_r[15:12] >= 3'd5) begin
bcd_out_r[15:12] <= bcd_out_r[15:12] + 4'b0011;
end else begin
bcd_out_r[15:12] <= bcd_out_r[15:12];
end
if (counter < 5'd16) begin
counter <= counter + 1;
end else begin
counter <= 'b0;
end
end
end
end
endmodule
| 6.821071 |
module add (
input [3:0] in,
output reg [3:0] out
);
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule
| 6.686118 |
module bintogray #(
parameter w = 8
) (
bin_i,
gray_o
);
input [w-1:0] bin_i;
output [w-1:0] gray_o;
assign gray_o = (bin_i >> 1) ^ bin_i;
/*assign gray_o[w-1]=bin_i[w-1];
genvar i;
for(i=w-1;i>=0;i--)
assign gray_o[i]=bin_i[i]^bin_i[i+1]*/
endmodule
| 6.889043 |
module Bin2HexConverter (
input wire clk,
input wire reset,
input wire bottom,
// bottom input port
output reg [7:0] to_7_seg_n,
// controlling 7 segment LED to display numbers
output wire [3:0] to_7_seg_sel_n
// control signal connecting to 7 segment LED selection port
);
// nets -------------------------------------------------------------------------
reg [1:0] bottom_r;
wire bottom_rising;
// "bottom" raising edge detection ----------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
bottom_r <= 2'd0;
end else begin
bottom_r[1] <= bottom_r[0];
bottom_r[0] <= bottom;
end
end
assign bottom_rising = bottom_r[0] & ~bottom_r[1];
// 7 segment LED display configuration -------------------------------------------
always @(posedge clk or negedge reset) begin
if (reset) begin
to_7_seg_n <= `NUM_OFF;
end else begin
if (bottom_rising) begin
// simple finite state mechine
case (to_7_seg_n)
`NUM_OFF: begin
to_7_seg_n <= `NUM_0;
end
`NUM_0: begin
to_7_seg_n <= `NUM_1;
end
`NUM_1: begin
to_7_seg_n <= `NUM_2;
end
`NUM_2: begin
to_7_seg_n <= `NUM_3;
end
`NUM_3: begin
to_7_seg_n <= `NUM_4;
end
`NUM_4: begin
to_7_seg_n <= `NUM_5;
end
`NUM_5: begin
to_7_seg_n <= `NUM_6;
end
`NUM_6: begin
to_7_seg_n <= `NUM_7;
end
`NUM_7: begin
to_7_seg_n <= `NUM_8;
end
`NUM_8: begin
to_7_seg_n <= `NUM_9;
end
`NUM_9: begin
to_7_seg_n <= `NUM_A;
end
`NUM_A: begin
to_7_seg_n <= `NUM_B;
end
`NUM_B: begin
to_7_seg_n <= `NUM_C;
end
`NUM_C: begin
to_7_seg_n <= `NUM_D;
end
`NUM_D: begin
to_7_seg_n <= `NUM_E;
end
`NUM_E: begin
to_7_seg_n <= `NUM_F;
end
`NUM_F: begin
to_7_seg_n <= `NUM_OFF;
end
default begin
to_7_seg_n <= `NUM_OFF;
end
endcase
end
end
end
assign to_7_seg_sel_n = `AN0_ON; // always turn on the ANO
endmodule
| 8.278035 |
module BinToBCD (
input wire clk,
nrst,
input wire start,
output reg valid,
input [27:0] bin,
output reg [47:0] bcd,
output reg [47:0] x
);
reg [27:0] bin_in;
reg op;
reg [3:0] cnt;
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bin_in <= 0;
else if (start) bin_in <= bin;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) op <= 0;
else if (start) op <= 1;
else if (cnt == 9 - 1) op <= 0;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) cnt <= 0;
else if (op) cnt <= cnt + 1'b1;
else cnt <= 0;
end
function [3:0] fout(input reg [3:0] fin);
fout = (fin > 4) ? fin + 4'd3 : fin;
endfunction
always @(posedge clk or negedge nrst) begin
if (nrst == 0) bcd <= 0;
else if (op) begin
bcd[0] <= bin_in[8-cnt];
bcd[4:1] <= fout(bcd[3:0]);
bcd[8:5] <= fout(bcd[7:4]);
bcd[12:9] <= fout(bcd[11:8]);
bcd[16:13] <= fout(bcd[15:12]);
bcd[20:17] <= fout(bcd[19:16]);
bcd[24:21] <= fout(bcd[23:20]);
bcd[28:25] <= fout(bcd[27:24]);
bcd[32:29] <= fout(bcd[31:28]);
//bcd[36:33] <= fout(bcd[35:32]);
//bcd[40:37] <= fout(bcd[39:36]);
//bcd[44:41] <= fout(bcd[43:40]);
//bcd[47:45] <= fout(bcd[47:44]);
end else bcd <= 0;
end
always @(posedge clk or negedge nrst) begin
if (nrst == 0) valid <= 0;
else if (cnt == 9 - 1) begin
x[47:0] = 48'b0;
x[5:0] = bcd[3:0];
x[11:6] = bcd[7:4];
x[17:12] = bcd[11:8];
x[23:18] = bcd[15:12];
x[29:24] = bcd[19:16];
x[35:30] = bcd[23:20];
x[41:36] = bcd[27:24];
x[47:42] = bcd[31:28];
valid <= 1;
end else valid <= 0;
end
endmodule
| 6.501169 |
module Bin_2_7Seg_Disp (
input [3:0] B,
output reg [6:0] a_2_g
);
always @(*) begin
case (B)
4'b0000: a_2_g = 7'h3f;
4'b0001: a_2_g = 7'h86;
4'b0010: a_2_g = 7'h5b;
4'b0011: a_2_g = 7'h4f;
4'b0100: a_2_g = 7'h66;
4'b0101: a_2_g = 7'h6d;
4'b0110: a_2_g = 7'h7d;
4'b0111: a_2_g = 7'h07;
4'b1000: a_2_g = 7'h7f;
4'b1001: a_2_g = 7'h6f;
4'b1010: a_2_g = 7'h77;
4'b1011: a_2_g = 7'h7c;
4'b1100: a_2_g = 7'h39;
4'b1101: a_2_g = 7'h5e;
4'b1110: a_2_g = 7'h79;
4'b1111: a_2_g = 7'h71;
default: a_2_g = 7'h00;
endcase
end
endmodule
| 7.211302 |
module Bin_Add_4bit (
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3,
cin,
c0,
c1,
c2,
c3,
cout
);
input wire a0;
input wire a1;
input wire a2;
input wire a3;
input wire b0;
input wire b1;
input wire b2;
input wire b3;
input wire cin;
output wire c0;
output wire c1;
output wire c2;
output wire c3;
output wire cout;
wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
FA b2v_inst (
.A(a0),
.B(b0),
.Cin(cin),
.S(c0),
.Cout(SYNTHESIZED_WIRE_0)
);
FA b2v_inst1 (
.A(a1),
.B(b1),
.Cin(SYNTHESIZED_WIRE_0),
.S(c1),
.Cout(SYNTHESIZED_WIRE_1)
);
FA b2v_inst2 (
.A(a2),
.B(b2),
.Cin(SYNTHESIZED_WIRE_1),
.S(c2),
.Cout(SYNTHESIZED_WIRE_2)
);
FA b2v_inst3 (
.A(a3),
.B(b3),
.Cin(SYNTHESIZED_WIRE_2),
.S(c3),
.Cout(cout)
);
endmodule
| 6.893303 |
module top (
//input [3:0] A, B, C, D,
input [12:0] number,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] A, B, C, D;
bcd bcd (
.number(number),
.thousands(D),
.hundreds(C),
.tens(B),
.ones(A)
);
bcdto7segmentclocked bcdto7segmentclocked (
.A(A),
.B(B),
.C(C),
.D(D),
.reset(reset),
.clk(clk),
.anode(anode),
.seg(seg)
);
endmodule
| 6.966747 |
module bcdto7segmentclocked (
input [3:0] A,
B,
C,
D,
input reset,
input clk,
output [3:0] anode,
output [6:0] seg
);
wire [3:0] x;
wire [3:0] an;
wire [1:0] sel;
wire clk_div;
bcdto7segment_dataflow bcdto7segment (
.x(x),
.an(an),
.anode(anode),
.seg(seg)
);
mux16to4 mux16to4 (
.A (A),
.B (B),
.C (C),
.D (D),
.sel(sel),
.S (x)
);
demux4to1 demux4to1 (
.sel(sel),
.A (an[0]),
.B (an[1]),
.C (an[2]),
.D (an[3])
);
counter counter (
.reset(reset),
.clk (clk_div),
.out (sel)
);
ClkDivider ClkDivider (
.clk(clk),
.rst(reset),
.clk_div(clk_div)
);
endmodule
| 7.120176 |
module bcdto7segment_dataflow (
input [3:0] x,
input [3:0] an,
output [3:0] anode,
output reg [6:0] seg
);
//reg [6:0] seg;
assign anode = an;
always @(x or an)
case (x)
0: seg = 7'b0000001;
1: seg = 7'b1001111;
2: seg = 7'b0010010;
3: seg = 7'b0000110;
4: seg = 7'b1001100;
5: seg = 7'b0100100;
6: seg = 7'b0100000;
7: seg = 7'b0001111;
8: seg = 7'b0000000;
9: seg = 7'b0000100;
default: seg = 7'b0000000;
endcase
endmodule
| 7.120176 |
module mux16to4 (
input [3:0] A,
input [3:0] B,
input [3:0] C,
input [3:0] D,
input [1:0] sel,
output reg [3:0] S
);
always @(A, B, C, D, sel)
case (sel)
0: S = A;
1: S = B;
2: S = C;
3: S = D;
default: S = 0;
endcase
endmodule
| 7.78955 |
module demux4to1 (
input [1:0] sel,
output reg A,
output reg B,
output reg C,
output reg D
);
always @(sel)
case (sel)
0: {D, C, B, A} = ~(4'b0001);
1: {D, C, B, A} = ~(4'b0010);
2: {D, C, B, A} = ~(4'b0100);
3: {D, C, B, A} = ~(4'b1000);
default: {D, C, B, A} = ~(4'b0000);
endcase
endmodule
| 7.031285 |
module ClkDivider (
input clk,
input rst,
output reg clk_div
);
localparam constantNumber = 50000; //f=1kHz f=100MHz/(2*constantNumber)
//localparam constantNumber = 25000000;//f=2Hz f=100MHz/(2*constantNumber)
reg [31:0] count;
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1) count <= 32'b0;
else if (count == constantNumber - 1) count <= 32'b0;
else count <= count + 1;
end
always @(posedge (clk), posedge (rst)) begin
if (rst == 1'b1) clk_div <= 1'b0;
else if (count == constantNumber - 1) clk_div <= ~clk_div;
else clk_div <= clk_div;
end
endmodule
| 6.643482 |
module = 256, with reverse counting direction.
*/
module bin_counter(i_clk, i_rst, i_mode, o_cnt);
input i_clk; // clock signal
input i_rst; // reset -> i_clear
input i_mode; // 0 - normal mode, 1 - reverse -> i_up_dwn
output reg [7:0] o_cnt; // 0...15
always @(posedge i_clk) begin // synchr reset
if(i_rst) begin
o_cnt <= (~i_mode) ? {8{1'b0}} : {8{1'b1}};
end else begin
if(~i_mode) begin // normal
o_cnt <= o_cnt + 1'b1;
end else begin
o_cnt <= o_cnt - 1'b1;
end
end
end
endmodule
| 6.500676 |
module bin_counter_tb3 ();
// declaration
localparam T = 20; // clock period
wire clk, reset;
wire syn_clr, load, en, up;
wire [2:0] d;
wire max_tick, min_tick;
wire [2:0] q;
// uut instantiation
univ_bin_counter #(
.N(3)
) uut (
.clk(clk),
.reset(reset),
.syn_clr(syn_clr),
.load(load),
.en(en),
.up(up),
.d(d),
.max_tick(max_tick),
.min_tick(min_tick),
.q(q)
);
// test vector generator
bin_gen #(
.N(3),
.T(20)
) gen_unit (
.clk(clk),
.reset(reset),
.syn_clr(syn_clr),
.load(load),
.en(en),
.up(up),
.d(d)
);
// bin_monitor instantiation
bin_monitor #(
.N(3)
) mon_unit (
.clk(clk),
.reset(reset),
.syn_clr(syn_clr),
.load(load),
.en(en),
.up(up),
.d(d),
.max_tick(max_tick),
.min_tick(min_tick),
.q(q)
);
endmodule
| 7.092307 |
module bdd (
input [3:0] binary,
input enable,
input reset,
output reg [6:0] hex
);
always @(*)
if (~reset) hex <= 7'b1111111;
else if (enable) begin
case (binary)
4'h0: hex <= 7'b1000000;
4'h1: hex <= 7'b1111001;
4'h2: hex <= 7'b0100100;
4'h3: hex <= 7'b0110000;
4'h4: hex <= 7'b0011001;
4'h5: hex <= 7'b0010010;
4'h6: hex <= 7'b0000010;
4'h7: hex <= 7'b1111000;
4'h8: hex <= 7'b0000000;
4'h9: hex <= 7'b0010000;
default: hex <= 7'b1111111;
endcase
end
endmodule
| 7.501913 |
module oh_bin2bin #(
parameter DW = 32 // width of data inputs
) (
input [DW-1:0] in,
output [DW-1:0] out
);
wire [DW-1:0] interm;
oh_bin2gray #(
.DW(DW)
) rd_b2g (
.out(interm),
.in (in)
);
oh_gray2bin #(
.DW(DW)
) rd_g2b (
.out(out),
.in (interm)
);
endmodule
| 8.106791 |
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