code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bit_searcher_16 (
input wire [15:0] bits,
input wire target,
input wire direction,
output wire hit,
output wire [3:0] index
);
wire [3:0] hit_inner;
wire [1:0] index_inner [3:0];
wire [1:0] index_upper;
bit_searcher_4
BS0 (
.bits(bits[3:0]),
.target(target),
.direction(direction),
.hit(hit_inner[0]),
.index(index_inner[0])
),
BS1 (
.bits(bits[7:4]),
.target(target),
.direction(direction),
.hit(hit_inner[1]),
.index(index_inner[1])
),
BS2 (
.bits(bits[11:8]),
.target(target),
.direction(direction),
.hit(hit_inner[2]),
.index(index_inner[2])
),
BS3 (
.bits(bits[15:12]),
.target(target),
.direction(direction),
.hit(hit_inner[3]),
.index(index_inner[3])
);
bit_searcher_4 BS4 (
.bits(hit_inner[3:0]),
.target(1'b1),
.direction(direction),
.hit(hit),
.index(index_upper)
);
assign index = {index_upper, index_inner[index_upper]};
endmodule
| 8.72533 |
module bit_searcher_64 (
input wire [63:0] bits,
input wire target,
input wire direction,
output wire hit,
output wire [5:0] index
);
wire [3:0] hit_inner;
wire [3:0] index_inner [3:0];
wire [1:0] index_upper;
bit_searcher_16
BS0 (
.bits(bits[15:0]),
.target(target),
.direction(direction),
.hit(hit_inner[0]),
.index(index_inner[0])
),
BS1 (
.bits(bits[31:16]),
.target(target),
.direction(direction),
.hit(hit_inner[1]),
.index(index_inner[1])
),
BS2 (
.bits(bits[47:32]),
.target(target),
.direction(direction),
.hit(hit_inner[2]),
.index(index_inner[2])
),
BS3 (
.bits(bits[63:48]),
.target(target),
.direction(direction),
.hit(hit_inner[3]),
.index(index_inner[3])
);
bit_searcher_4 BS4 (
.bits(hit_inner[3:0]),
.target(1'b1),
.direction(direction),
.hit(hit),
.index(index_upper)
);
assign index = {index_upper, index_inner[index_upper]};
endmodule
| 8.72533 |
module bit_searcher_256 (
input wire [255:0] bits,
input wire target,
input wire direction,
output wire hit,
output wire [7:0] index
);
wire [3:0] hit_inner;
wire [5:0] index_inner [3:0];
wire [1:0] index_upper;
bit_searcher_64
BS0 (
.bits(bits[63:0]),
.target(target),
.direction(direction),
.hit(hit_inner[0]),
.index(index_inner[0])
),
BS1 (
.bits(bits[127:64]),
.target(target),
.direction(direction),
.hit(hit_inner[1]),
.index(index_inner[1])
),
BS2 (
.bits(bits[191:128]),
.target(target),
.direction(direction),
.hit(hit_inner[2]),
.index(index_inner[2])
),
BS3 (
.bits(bits[255:192]),
.target(target),
.direction(direction),
.hit(hit_inner[3]),
.index(index_inner[3])
);
bit_searcher_4 BS4 (
.bits(hit_inner[3:0]),
.target(1'b1),
.direction(direction),
.hit(hit),
.index(index_upper)
);
assign index = {index_upper, index_inner[index_upper]};
endmodule
| 8.72533 |
module bit_searcher_32 (
input wire [31:0] bits,
input wire target,
input wire direction,
output wire hit,
output wire [4:0] index
);
wire [1:0] hit_inner;
wire [3:0] index_inner[3:0];
wire index_upper;
bit_searcher_16
BS0 (
.bits(bits[15:0]),
.target(target),
.direction(direction),
.hit(hit_inner[0]),
.index(index_inner[0])
),
BS1 (
.bits(bits[31:16]),
.target(target),
.direction(direction),
.hit(hit_inner[1]),
.index(index_inner[1])
);
bit_searcher_2 BS4 (
.bits(hit_inner[1:0]),
.target(1'b1),
.direction(direction),
.hit(hit),
.index(index_upper)
);
assign index = {index_upper, index_inner[index_upper]};
endmodule
| 8.72533 |
module bit_searcher (
input wire [N-1:0] bits, // data being searched
input wire target, // search target
input wire direction, // search direction, 0 for lower to upper and 1 otherwise
output wire hit, // target found flag
output wire [W-1:0] index // index of target in data
);
`include "function.vh"
parameter N = 32;
localparam W = GET_WIDTH(N - 1);
generate
begin : BS_GEN
case (N)
2:
bit_searcher_2 BS_2 (
.bits(bits),
.target(target),
.direction(direction),
.hit(hit),
.index(index)
);
4:
bit_searcher_4 BS_4 (
.bits(bits),
.target(target),
.direction(direction),
.hit(hit),
.index(index)
);
16:
bit_searcher_16 BS_16 (
.bits(bits),
.target(target),
.direction(direction),
.hit(hit),
.index(index)
);
32:
bit_searcher_32 BS_32 (
.bits(bits),
.target(target),
.direction(direction),
.hit(hit),
.index(index)
);
64:
bit_searcher_64 BS_64 (
.bits(bits),
.target(target),
.direction(direction),
.hit(hit),
.index(index)
);
256:
bit_searcher_256 BS_256 (
.bits(bits),
.target(target),
.direction(direction),
.hit(hit),
.index(index)
);
default:
initial $display("Error: Illegal bit length %0d", N);
endcase
end
endgenerate
endmodule
| 8.458105 |
module bit_serial_adder (
input clk,
input reset,
input load,
input [7:0] a,
input [7:0] b,
input cin,
output wire [7:0] sum,
output wire cout
);
/*
clk: Clock
reset: Reset bit of the module (indicates to reset the adder)
load: Load bit of the module (indicates when to load data)
a: First 8-bit input bit to the adder
b: Second 8-bit input bit to the adder
cin: Carry input to the adder
out: 8-bit sum output of the adder
cout: Carry output of the adder
*/
// Declaring wires to connect various modules
wire [7:0] x, z;
wire s, c;
// Reading input bit by bit form both the given inputs
shift_register SR1 (
clk,
reset,
load,
a,
x
);
shift_register SR2 (
clk,
reset,
load,
b,
z
);
// D-Flip Flop to remember the carry
dff DFF (
clk,
reset,
cout,
cin,
c
);
// Calling adder module to add sequential bits
full_adder FA (
x[0],
z[0],
c,
s,
cout
);
// Store sum using serial input and parallel output
serial_in_parallel_out SIPO (
clk,
load,
s,
sum
);
endmodule
| 7.9223 |
module
module bit_serial_adder_tb;
// Initialising inputs and outputs
reg clk;
reg reset;
reg load;
reg sipo_load;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
bit_serial_adder UUT(.clk(clk), .reset(reset), .load(load), .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));
initial begin
// Reset everything before loading the value
clk = 0;
reset = 1'b1;
// Load the value of the inputs
#10
reset = 1'b0;
load = 1'b1;
a = 8'b11001010;
b = 8'b10110101;
cin = 1'b0;
// Wait 10 ns for loading to finish then set load = 0
#10
load = 1'b0;
// Wait for 8 clock cycles for add operation
#80
$finish;
end
// Toogle clock every 5 time units
always
#5 clk = ~clk;
// Display the results after each clock cycle
always
#10 $display("A:%b, B:%b, Sum:%b, Cout:%b", a, b, sum, cout);
endmodule
| 6.892285 |
module bit_shift #(
//==============================
// Module parameters
//==============================
parameter DATA_WIDTH = 8, // number of input bits
parameter SHIFT_DIRECTION = 1, // 1 = shift right, 0 = shift left
parameter NUMBER_BITS = 1, // number of bits to shift
parameter WRAP = 0 // whether to wrap the shift or not
) (
//==============
// IO Ports
//==============
input wire clk,
input wire [DATA_WIDTH-1:0] data_in,
output reg [DATA_WIDTH-1:0] data_out
);
// Synchronous logic
always @(posedge clk) begin
// Non wrapping
if (WRAP == 0) begin
data_out = SHIFT_DIRECTION = (data_in >> NUMBER_BITS) : (data_in << NUMBER_BITS)
if (SHIFT_DIRECTION) begin // right shift
data_out <= data_in >> NUMBER_BITS;
end else begin // left shift
data_out <= data_in << NUMBER_BITS;
end
end
// Wrapping TODO: make this code wrap
if (WRAP) begin // (WRAP)
if (SHIFT_DIRECTION) begin // right shift
data_out <= data_in >> NUMBER_BITS;
end else begin // left shift
data_out <= data_in << NUMBER_BITS;
end
end
end
endmodule
| 8.512014 |
module bit_shifter_rotator (
ctrl,
in,
out
);
input [2:0] ctrl;
input [7:0] in;
output reg [7:0] out;
always @(*) begin
//assign tmp = in;
case (ctrl)
3'b000: out <= in;
3'b001: out <= in << 1;
3'b010: out <= in << 2;
3'b011: out <= in << 3;
3'b100: out <= in << 4;
3'b101: out <= {in[0], in[3:1]};
3'b110: out <= {in[1:0], in[3:2]};
3'b111: out <= {in[2:0], in[3]};
endcase
end
endmodule
| 6.876592 |
module bit_shift_controller #(
parameter START_BITS = 8'b00010000
) (
input [23:0] buttons,
output [ 7:0] bits
);
reg [7:0] r_bits = START_BITS;
assign bits = r_bits;
always @(buttons) begin
r_bits =
(buttons[0] == 1 && r_bits[0] != 1) ? r_bits << 1 :
(buttons[1] == 1 && r_bits[7] != 1) ? r_bits >> 1 :
(buttons[2] == 1) ? 8'b00010000 :
(buttons[3] == 1) ? 8'b00101000 :
(buttons[4] == 1) ? 8'b01010101 :
(buttons[5] == 1) ? 8'b10101010 :
(buttons[6] == 1) ? 8'b00000000 :
(buttons[7] == 1) ? 8'b11111111 :
(buttons[8] == 1) ? 8'b00000001 :
(buttons[9] == 1) ? 8'b00000010 :
(buttons[10] == 1) ? 8'b00000100 :
(buttons[11] == 1) ? 8'b00001000 :
(buttons[12] == 1) ? 8'b00010000 :
(buttons[13] == 1) ? 8'b00100000 :
(buttons[14] == 1) ? 8'b01000000 :
(buttons[15] == 1) ? 8'b10000000 :
r_bits;
end
endmodule
| 8.374731 |
module bit_shift_controller_tb;
// UUT Inputs
reg [23:0] buttons = 0;
// UUT outputs
output [7:0] bits;
// Instantiate the Unit Under Test (UUT)
bit_shift_controller #(
.START_BITS(8'b00011000)
) uut (
.buttons(buttons)
);
// UUT test simulation
integer i;
integer ii;
initial begin
// Configure file output
$dumpfile("bit_shift_controller_tb.vcd");
$dumpvars(0, bit_shift_controller_tb);
// Move completely to left
for (i = 0; i < 10; i = i + 1) begin
buttons = ;
#5;
LEFT = 0;
#5;
end
// Check UUT output
if (bits == 8'b00001100)
$display("[%t] Test success - bit shifted to left", $realtime);
else
$display("[%t] Test failure - bit not shifted to left", $realtime);
// Move completely to left
for (ii = 0; ii < 10; ii = ii + 1) begin
buttons = 24'b000000000000000000000001;
#5;
buttons = 24'b000000000000000000000000;
#5;
end
// Check UUT output
if (bits == 8'b00000011)
$display("[%t] Test success - bit shifted to right", $realtime);
else
$display("[%t] Test failure - bit not shifted to right", $realtime);
// Move completely to left
for (i = 0; i < 10; i = i + 1) begin
buttons = 24'b000000000000000000000010;
#5;
buttons = 24'b000000000000000000000000;
#5;
end
// Check UUT output
if (bits == 8'b11000000)
$display("[%t] Test success - bit shifted to left", $realtime);
else
$display("[%t] Test failure - bit not shifted to left", $realtime);
// End test
#100;
$finish;
end
endmodule
| 8.374731 |
module //
// Date: Nov 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basic functionality of the module, more //
// comprehensive testing is done in the python test file //
// //
//============================================================================//
module bit_shift_tb;
//===================
// local parameters
//===================
localparam LOCAL_DATA_WIDTH = `ifdef DATA_WIDTH `DATA_WIDTH `else 8 `endif;
//===============
// declare regs
//===============
reg clk;
reg[LOCAL_DATA_WIDTH-1:0] data_in;
//================
// declare wires
//================
wire [LOCAL_DATA_WIDTH-1:0] data_out;
//======================================
// instance, "(d)esign (u)nder (t)est"
//======================================
bit_shift #(
.DATA_WIDTH (`ifdef DATA_WIDTH `DATA_WIDTH `else 8 `endif),
.SHIFT_DIRECTION (`ifdef SHIFT_DIRECTION `SHIFT_DIRECTION `else 0 `endif),
.NUMBER_BITS (`ifdef NUMBER_BITS `NUMBER_BITS `else 1 `endif),
.WRAP (`ifdef WRAP `WRAP `else 0 `endif)
) dut (
.clk (clk),
.data_in (data_in),
.data_out(data_out)
);
//=============
// initialize
//=============
initial
begin
clk = 0;
data_in = 16'b0101010101010101;
end
//=====================
// simulate the clock
//=====================
always #1
begin
clk = ~clk;
end
//===================
// print the output
//===================
always @(posedge clk) $display(data_out);
//========================
// finish after 3 clocks
//========================
initial #3 $finish;
endmodule
| 8.238592 |
module bit_shift_test (
input wire i_clk,
output wire [7:0] o_data
);
reg [ 3:0] r_counter = 0;
reg [15:0] r_data;
always @(posedge i_clk) begin
r_counter <= r_counter + 1;
r_data <= (1 << r_counter);
end
assign o_data = r_data[7:0];
endmodule
| 6.98187 |
module bit_slice (
Cout,
A,
B,
Z,
B_0,
Cin,
add_en,
add_en_n,
clk,
ppgen_en,
ppgen_en_n,
rd_enA,
rd_enA_n,
rd_enB,
rd_enB_n,
wr_en
);
output Cout;
inout A, B, Z;
input B_0, Cin, add_en, add_en_n, clk, ppgen_en, ppgen_en_n;
input [4:0] rd_enB;
input [4:0] rd_enA;
input [4:0] rd_enA_n;
input [4:0] wr_en;
input [4:0] rd_enB_n;
specify
specparam CDS_LIBNAME = "ece555_final";
specparam CDS_CELLNAME = "bit_slice";
specparam CDS_VIEWNAME = "schematic";
endspecify
reg_file_bit_slice I4 (
A,
B,
Z,
clk,
rd_enA[4],
rd_enA_n[4],
rd_enB[4],
rd_enB_n[4],
wr_en[4]
);
reg_file_bit_slice I3 (
A,
B,
Z,
clk,
rd_enA[3],
rd_enA_n[3],
rd_enB[3],
rd_enB_n[3],
wr_en[3]
);
reg_file_bit_slice I2 (
A,
B,
Z,
clk,
rd_enA[2],
rd_enA_n[2],
rd_enB[2],
rd_enB_n[2],
wr_en[2]
);
reg_file_bit_slice I1 (
A,
B,
Z,
clk,
rd_enA[1],
rd_enA_n[1],
rd_enB[1],
rd_enB_n[1],
wr_en[1]
);
reg_file_bit_slice I0 (
A,
B,
Z,
clk,
rd_enA[0],
rd_enA_n[0],
rd_enB[0],
rd_enB_n[0],
wr_en[0]
);
pp_gen I9 (
Z,
A,
B_0,
ppgen_en,
ppgen_en_n
);
adder_en I10 (
Cout,
Z,
A,
B,
Cin,
add_en,
add_en_n
);
endmodule
| 7.404372 |
module bit_slip_v (
input clk,
input rstn,
input byte_gate,
input [7:0] curr_byte,
input [7:0] last_byte,
input frame_start,
output reg found_sot,
output reg [2:0] data_offs,
output reg [7:0] actual_byte
);
reg found_hdr;
reg [2:0] hdr_offs;
always @(curr_byte or last_byte) begin
/* if({last_byte[7:0]} == 8'hb8)
begin
found_hdr = 1'b1;
hdr_offs = 0;
end
else */ if (({curr_byte[0], last_byte[7:1]} == 8'hb8) && (last_byte[0] == 0)) begin
found_hdr = 1'b1;
hdr_offs = 1;
end else if (({curr_byte[1:0], last_byte[7:2]} == 8'hb8) && (last_byte[1:0] == 0)) begin
found_hdr = 1'b1;
hdr_offs = 3'd2;
end else if (({curr_byte[2:0], last_byte[7:3]} == 8'hb8) && (last_byte[2:0] == 0)) begin
found_hdr = 1'b1;
hdr_offs = 3'd3;
end else if (({curr_byte[3:0], last_byte[7:4]} == 8'hb8) && (last_byte[3:0] == 0)) begin
found_hdr = 1'b1;
hdr_offs = 3'd4;
end else if (({curr_byte[4:0], last_byte[7:5]} == 8'hb8) && (last_byte[4:0] == 0)) begin
found_hdr = 1'b1;
hdr_offs = 3'd5;
end else if (({curr_byte[5:0], last_byte[7:6]} == 8'hb8) && (last_byte[5:0] == 0)) begin
found_hdr = 1'b1;
hdr_offs = 3'd6;
end else if (({curr_byte[6:0], last_byte[7]} == 8'hb8) && (last_byte[6:0] == 0)) begin
found_hdr = 1'b1;
hdr_offs = 3'd7;
end else if ((curr_byte[7:0] == 8'hb8) && (last_byte == 0)) begin
found_hdr = 1'b1;
hdr_offs = 0;
end else begin
found_hdr = 0;
hdr_offs = 0;
end
end
////////////////////////////////////////////////
//reg [2:0] data_offs;
//reg found_sot;
always @(posedge clk or negedge rstn)
if (!rstn) begin
data_offs <= 0;
// found_sot <= 0;
end else if (frame_start) begin
if (found_hdr) begin
data_offs <= hdr_offs;
// found_sot <= found_hdr;
end else begin
data_offs <= data_offs;
// found_sot <= found_sot;
end
end else begin
data_offs <= 0;
// found_sot <= 0;
end
/////////////////////////////////////////////
always @(posedge clk or negedge rstn)
if (!rstn) begin
actual_byte <= 0;
end else if (byte_gate) begin
actual_byte <= shifted_byte;
end
always @(posedge clk or negedge rstn)
if (!rstn) begin
found_sot <= 0;
end else if (byte_gate) begin
found_sot <= found_hdr;
end
///////////////////////////////////
reg [7:0] shifted_byte;
always @(curr_byte or last_byte) begin
case (data_offs)
3'd0: shifted_byte = {curr_byte};
3'd1: shifted_byte = {curr_byte[0], last_byte[7:1]};
3'd2: shifted_byte = {curr_byte[1:0], last_byte[7:2]};
3'd3: shifted_byte = {curr_byte[2:0], last_byte[7:3]};
3'd4: shifted_byte = {curr_byte[3:0], last_byte[7:4]};
3'd5: shifted_byte = {curr_byte[4:0], last_byte[7:5]};
3'd6: shifted_byte = {curr_byte[5:0], last_byte[7:6]};
3'd7: shifted_byte = {curr_byte[6:0], last_byte[7]};
default: ;
endcase
end
endmodule
| 7.046357 |
module bit_stream (
input clk,
EA,
input [10:0] count_h,
count_v,
output red,
green,
blue
);
reg r = 0;
reg g = 0;
reg b = 0;
assign red = r;
assign green = g;
assign blue = b;
always @(posedge clk) begin
if (EA) begin
if (count_h < 128)
// красный
begin
r = 1;
b = 0;
g = 0;
end
//желтый
if (count_h > 128) begin
r = 1;
b = 0;
g = 1;
end
//зеленый
if (count_h > 256) begin
r = 0;
b = 0;
g = 1;
end
//голубой
if (count_h > 384) begin
r = 0;
b = 1;
g = 1;
end
// синий
if (count_h > 512) begin
r = 0;
b = 1;
g = 0;
end
//фиолетовый
if (count_h > 640) begin
r = 1;
b = 1;
g = 0;
end
// белый
if (count_h > 768) begin
r = 1;
b = 1;
g = 1;
end
// черный
if (count_h > 896) begin
r = 0;
b = 0;
g = 0;
end
end else begin
r = 0;
b = 0;
g = 0;
end
end
endmodule
| 6.777608 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 19/7/2022 Mina Hanna final version
//------------------------------------------------
// KEYWORDS: multi clock system, clock domain crossing,crc , synchronizer
//------------------------------------------------
// PURPOSE:\this is a Parameterized synchronizer\
module BIT_SYNC #(parameter STAGES = 2,parameter WIDTH = 1) (
input wire [WIDTH-1:0] BitSync_ASYNC,
input wire BitSync_CLK,
input wire BitSync_RST,
output reg [WIDTH-1:0] BitSync_SYNC);
reg [STAGES-1:0] FFSTAGES [WIDTH-1:0];
integer i;
//////////////////synchronizer logic/////////////////
always@(posedge BitSync_CLK or negedge BitSync_RST)
begin
if(!BitSync_RST)
begin
for(i=0;i<WIDTH;i=i+1)
begin
FFSTAGES[i] <= 'b0;
end
end
else
for(i=0;i<WIDTH;i=i+1)
begin
FFSTAGES[i] <= {FFSTAGES[i][STAGES-2:0],BitSync_ASYNC};
end
end
always@(*)
begin
for(i=0;i<WIDTH;i=i+1)
begin
BitSync_SYNC[i] = FFSTAGES[i][STAGES-1];
end
end
endmodule
| 8.923686 |
module BIT_SYNC_tb ();
parameter NUM_STAGES_tb = 2;
parameter BUS_WIDTH_tb = 4;
/********************************************************************************/
/*******************************Internal Signals*********************************/
reg [BUS_WIDTH_tb-1:0] ASYNCH_tb;
reg RST_tb;
reg CLK_tb;
wire [BUS_WIDTH_tb-1:0] SYNC_tb;
/********************************************************************************/
/********************************Clock Period************************************/
localparam CLK_PERIOD = 100;
/********************************************************************************/
/********************************************************************************/
initial begin
$dumpfile("BIT_SYNC_tb.vcd");
$dumpvars;
CLK_tb = 'b0;
ASYNCH_tb = 'b0;
RST_tb = 'b0;
#(CLK_PERIOD * 0.7) RST_tb = 'b1;
/********************************************************************************/
/***********************************Test Cases***********************************/
#(CLK_PERIOD * 0.3) ASYNCH_tb = 'b1101;
#(CLK_PERIOD * 3) $display("\n\nTEST CASE 0");
if (SYNC_tb == 'b1101) $display("\nPassed\n");
else $display("\nFailed\n");
/********************************************************************************/
/********************************************************************************/
#(CLK_PERIOD * 10) $finish;
end
/********************************************************************************/
/*****************************Clock Generator************************************/
always #(CLK_PERIOD * 0.5) CLK_tb = !CLK_tb;
/********************************************************************************/
/************************Instantiation Of The Module*****************************/
BIT_SYNC #(
.NUM_STAGES(NUM_STAGES_tb),
.BUS_WIDTH (BUS_WIDTH_tb)
) DUT (
.ASYNCH(ASYNCH_tb),
.RST (RST_tb),
.CLK (CLK_tb),
.SYNC(SYNC_tb)
);
endmodule
| 7.201462 |
module Bit_tb ();
integer file;
reg clk = 1;
wire out;
reg load = 0;
reg in = 0;
reg [9:0] t = 10'b0;
Bit BIT (
.clk (clk),
.load(load),
.in (in),
.out (out)
);
always #1 clk = ~clk;
task display;
#1 $fwrite(file, "|%4d|%1b|%1b|%1b|\n", t, in, load, out);
endtask
initial begin
$dumpfile("Bit_tb.vcd");
$dumpvars(0, Bit_tb);
file = $fopen("Bit.out", "w");
$fwrite(file, "|time|in|load|out|\n");
display();
t = 1;
display();
in = 0;
load = 1;
display();
t = 2;
display();
in = 1;
load = 0;
display();
t = 3;
display();
in = 1;
load = 1;
display();
t = 4;
display();
in = 0;
load = 0;
display();
t = 5;
display();
in = 1;
load = 0;
display();
$finish;
end
endmodule
| 7.042786 |
module bit_timing(
input rx,
input rst,
input clk,
output sampled_rx,
output baud_clk
);
if(posedge reset
endmodule
| 7.399181 |
module bit_to_bus_4 (
input bit_3,
input bit_2,
input bit_1,
input bit_0,
output [3:0] bus_out
);
assign bus_out = {bit_3, bit_2, bit_1, bit_0};
endmodule
| 7.689119 |
module bit_vec_stat #(
parameter integer bit_width = 64,
parameter integer vec_width_index = 4,
parameter integer vec_width_value = 32,
parameter integer vec_num = 16,
parameter integer vec_width_total = (vec_width_index + vec_width_value) * vec_num
) (
input wire rst,
input wire clk,
input wire up_rd,
input wire [32-1:0] up_addr,
output wire [31 : 0] up_data_rd,
input wire clr_in,
input wire stat_chk,
input wire [ 3 : 0] stat_base_addr,
input wire [ bit_width-1 : 0] stat_bit,
input wire [vec_width_total-1:0] stat_vec
);
// CPU access
wire up_cs_bit = (up_addr[16] == 1'b0) ? 1'b1 : 1'b0; // rd 0800xxxx or 0802xxxx
wire up_cs_vec = (up_addr[16] == 1'b1) ? 1'b1 : 1'b0; // rd 0801xxxx or 0803xxxx
wire [31:0] up_data_rd_bit;
wire [31:0] up_data_rd_vec;
assign up_data_rd = up_cs_bit ? up_data_rd_bit : (up_cs_vec ? up_data_rd_vec : 32'hdeadbeef);
// Rx: bit based statistic
wire [bit_width-1:0] stat_bit_clr;
wire [bit_width-1:0] stat_bit_reg;
bit_queue stat_bit_queue (
.rst(rst),
.clk(clk),
.chk_in (stat_chk && !clr_in),
.bit_in (stat_bit),
.clr_in (stat_bit_clr),
.bit_out(stat_bit_reg)
);
bit_counter stat_bit_counter (
.rst(rst),
.clk(clk),
.clr_in(clr_in),
.up_rd(up_rd && up_cs_bit),
.up_addr(up_addr[15:0]),
.up_data_rd(up_data_rd_bit),
.base_addr(stat_base_addr),
.bit_in(stat_bit_reg),
.clr_out(stat_bit_clr)
);
// Rx: vec based statistic
wire [vec_width_index*vec_num-1:0] stat_vec_clr;
wire [vec_width_index*vec_num-1:0] stat_vec_reg;
wire [vec_width_value*vec_num-1:0] stat_vec_val;
vec_queue stat_vec_queue (
.rst(rst),
.clk(clk),
.chk_in(stat_chk && !clr_in),
.vec_in(stat_vec),
.clr_in(stat_vec_clr),
.vec_index_out(stat_vec_reg),
.vec_value_out(stat_vec_val)
);
vec_counter stat_vec_counter (
.rst(rst),
.clk(clk),
.clr_in(clr_in),
.up_rd(up_rd && up_cs_vec),
.up_addr(up_addr[15:0]),
.up_data_rd(up_data_rd_vec),
.base_addr(stat_base_addr),
.vec_index_in(stat_vec_reg),
.vec_value_in(stat_vec_val),
.clr_out(stat_vec_clr)
);
endmodule
| 8.424288 |
module BIU (
input [2:0] NUM,
input [7:0] RX,
input [7:0] RY,
input [1:0] SEL_BIU,
input reset,
input clk,
output reg [7:0] o_Address_Data_Bus,
output reg [7:0] o_DataOut_Bus,
output reg W_R
);
always @(posedge clk, posedge reset) begin
if (reset) begin
o_DataOut_Bus <= 0;
o_Address_Data_Bus <= 0;
W_R <= 0;
end else
case (SEL_BIU)
0: begin //Para la instruccin LOAD (Dato cargado de [RY])
o_DataOut_Bus <= 0;
o_Address_Data_Bus <= RY;
W_R <= 0;
end
1: begin //Para la instruccin STORE (NUM ser almacenado en [RX])
o_DataOut_Bus <= {5'b00000, NUM};
o_Address_Data_Bus <= RX;
W_R <= 1;
end
2: begin // Para la instruccin STORE (Almacenar datos del registro RY en [RX])
o_DataOut_Bus <= RY;
o_Address_Data_Bus <= RX;
W_R <= 1;
end
3: begin //NOP (NO OPERATION)
o_DataOut_Bus <= 0;
o_Address_Data_Bus <= 0;
W_R <= 0;
end
endcase
end
endmodule
| 6.836573 |
module biu8 (
//对外部总线的信号
inout [7:0] p,
//对内部总线的信号
input [7:0] data_o,
input wr_n,
input rd_n,
input en,
output [7:0] data_i,
//控制寄存器选择信号
input sel
);
reg [7:0] data;
reg [7:0] data_p;
assign p = sel ? 8'bz : data_p; //sel=1: high z or input , sel=0 output 1/0
always @(negedge rd_n) begin
data <= p;
end
always @(posedge wr_n) begin
data_p <= en ? data_o : data_p;
end
assign data_i = data;
endmodule
| 7.355211 |
module biu_ctl (
icu_req,
icu_type,
icu_size,
biu_icu_ack,
dcu_req,
dcu_type,
dcu_size,
biu_dcu_ack,
clk,
reset_l,
pj_tv,
pj_type,
pj_size,
pj_ack,
sm,
sin,
so,
arb_select,
pj_ale
);
input icu_req;
input [3:0] icu_type;
input [1:0] icu_size;
output [1:0] biu_icu_ack;
input dcu_req;
input [3:0] dcu_type;
input [1:0] dcu_size;
output [1:0] biu_dcu_ack;
input clk;
input reset_l;
output pj_tv;
input [1:0] pj_ack;
output [3:0] pj_type;
output [1:0] pj_size;
input sm;
input sin;
output so;
output arb_select;
output pj_ale;
wire arbiter_sel;
wire temp_arb_sel;
wire arb_select;
wire arb_idle;
wire [4:0] arb_next_state;
wire [4:0] arb_state;
wire icu_tx;
wire dcu_tx;
wire [2:0] num_acks;
wire [3:0] type_state;
assign pj_tv = ((icu_req | dcu_req) & arb_state[0]) | arb_state[1];
assign icu_tx = !type_state[2];
assign dcu_tx = type_state[2];
assign biu_dcu_ack = {dcu_tx, dcu_tx} & pj_ack; //2{dcu_tx}
assign biu_icu_ack = {icu_tx, icu_tx} & pj_ack;
assign pj_ale = ~(pj_tv & arb_state[0]);
/* muxes for pj_type and pj_size */
mux2_2 biu_size_mux (
.out(pj_size[1:0]),
.in1(icu_size[1:0]),
.in0(dcu_size[1:0]),
.sel({arb_select, !arb_select})
);
mux2_4 biu_type_mux (
.out(pj_type[3:0]),
.in1(icu_type[3:0]),
.in0(dcu_type[3:0]),
.sel({arb_select, !arb_select})
);
/* Generation of select for pj_addr,pj_type and pj_size muxes */
assign arbiter_sel = icu_req & !dcu_req;
ff_sre arb_select_state (
.out(temp_arb_sel),
.din(arbiter_sel),
.clk(clk),
.reset_l(reset_l),
.enable(arb_idle)
);
mux2 arb_select_mux (
.out(arb_select),
.in1(arbiter_sel),
.in0(temp_arb_sel),
.sel({arb_idle, !arb_idle})
);
/* State machine for Arbiter */
assign arb_next_state[4:0] = arbiter(arb_state[4:0], pj_ack[0], pj_ack[1], pj_tv, num_acks);
ff_sre_4 arb_state_reg (
.out(arb_state[4:1]),
.din(arb_next_state[4:1]),
.clk(clk),
.reset_l(reset_l),
.enable(1'b1)
);
ff_s arb_state_reg_0 (
.out(arb_state[0]),
.din(~reset_l | arb_next_state[0]),
.clk(clk)
);
//latch pj_type
ff_se_4 type_state_reg (
.out(type_state[3:0]), //change
.din(pj_type[3:0]),
.clk(clk),
.enable(arb_idle)
);
assign arb_idle = arb_state[0];
assign num_acks[0] = type_state[1];
assign num_acks[1] = 1'b0;
assign num_acks[2] = (type_state[3] | (type_state[2] & (!type_state[1])))|
!(type_state[1] | type_state[2] | type_state[3]);
function [4:0] arbiter;
input [4:0] cur_state;
input normal_ack;
input error_ack;
input pj_tv;
input [2:0] num_acks;
reg [4:0] next_state;
parameter
IDLE = 5'b00001,
REQ_ACTIVE = 5'b00010,
FILL3 = 5'b00100,
FILL2 = 5'b01000,
FILL1 = 5'b10000;
begin
case (cur_state)
IDLE: begin
if (pj_tv) begin
next_state = REQ_ACTIVE;
end else next_state = cur_state;
end
REQ_ACTIVE: begin
if (error_ack | (normal_ack & num_acks[0])) next_state = IDLE;
else if (normal_ack & num_acks[2]) next_state = FILL3;
else if (normal_ack & num_acks[1]) next_state = FILL1;
else next_state = cur_state;
end
FILL3: begin
if (error_ack) next_state = IDLE;
else if (normal_ack) next_state = FILL2;
else next_state = cur_state;
end
FILL2: begin
if (error_ack) next_state = IDLE;
else if (normal_ack) next_state = FILL1;
else next_state = cur_state;
end
FILL1: begin
if (normal_ack | error_ack) next_state = IDLE;
else next_state = cur_state;
end
default: begin
next_state = 5'bx;
end
endcase
arbiter[4:0] = next_state[4:0];
end
endfunction
endmodule
| 8.52045 |
module biu_dpath (
icu_addr,
dcu_addr,
dcu_dataout,
biu_data,
pj_addr,
pj_data_in,
pj_data_out,
arb_select
);
input [31:0] icu_addr;
input [31:0] dcu_addr;
input [31:0] dcu_dataout;
output [31:0] biu_data;
output [31:0] pj_addr;
input [31:0] pj_data_in;
output [31:0] pj_data_out;
input arb_select;
mux2_32 biu_addr_mux (
.out(pj_addr[31:0]),
.in1(icu_addr[31:0]),
.in0(dcu_addr[31:0]),
.sel({arb_select, !arb_select})
);
assign pj_data_out[31:0] = dcu_dataout[31:0];
assign biu_data = pj_data_in ;
endmodule
| 8.537689 |
module bi_buffer #(
parameter D_WL = 24,
parameter UNITS_NUM = 5
) (
input [7:0] addr,
output [UNITS_NUM*D_WL-1:0] w_o
);
wire [D_WL*UNITS_NUM-1:0] w_fix[0:5];
assign w_o = w_fix[addr];
assign w_fix[0] = 'h00024bffb2f4fff286000975ffc6ae;
assign w_fix[1] = 'hffe4d1fff192ffe85affe555001608;
assign w_fix[2] = 'hfff3b6ffe019ffe431ffd753ffe0df;
assign w_fix[3] = 'hffe8b7ffe7b4ffef0ffff2c8fff549;
assign w_fix[4] = 'hffe385fff65fffb256ffd636ffdafc;
assign w_fix[5] = 'hffe87afff556ffd0a1fff0a6000436;
endmodule
| 6.65284 |
module bi_chang (
is_wall,
out_is_wall
);
input is_wall;
output out_is_wall;
//when close to the wall, is_wall=0
//https://www.playrobot.com/infrared/1039-infrared-sensor.html
assign out_is_wall = (!is_wall) ? 1 : 0;
//assign led = 1;
endmodule
| 6.851805 |
module bi_direc (
i_clk,
rst_n,
CNT,
a_in,
o_TEMPout,
ld
);
parameter DATA_WIDTH2 = 8;
input i_clk;
//input [DATA_WIDTH2-1:0] d_in ;
input rst_n;
input a_in; ///used as serial in //
input ld; ///for loading the data///
input CNT ; ///used for changing the dircetion of shift register if CNT==1 then right shift else left shift ///
output reg [DATA_WIDTH2-1:0] o_TEMPout; ///used for led ////
wire o_clk ; ///intermediate clock wire for feeding the clock from clock divider module to the top module ///
///*********************************/////
clock_div U1 (
i_clk,
o_clk
);
///instantiation of clock divider ///
always @(posedge o_clk) begin
if (~rst_n) o_TEMPout <= 0;
else if (ld == 1) begin
if (CNT == 1) o_TEMPout <= {a_in, o_TEMPout[7:1]}; ///right shift //
else o_TEMPout <= {o_TEMPout[6:0], a_in}; ///left shift ///
end
end
endmodule
| 8.042317 |
module bi_direct_bus (
pindata,
Data_in,
Data_out,
OE
);
parameter n_buff = 4;
input OE;
inout [n_buff-1:0] pindata;
input [n_buff-1:0] Data_in;
output [n_buff-1:0] Data_out;
assign Data_in = pindata;
assign pindata = (OE == 1) ? Data_out : (OE == 0) ? 'z : 'x;
endmodule
| 7.05196 |
module
module bjt(input globalclock, //fpgaclock, 50MHz
input rst, //overall reset
output tx_spi_sclk, //output spi clock for AD5664
output tx_spi_sync, //output spi synchronize signal for AD5664 spi registers
output tx_spi_din, //output spi data signal for AD5664 spi registers
output ADC_CONVST, //LTC2308 spi conversion signal
output ADC_SCK, //LTC2308 spi clock
output ADC_SDI, //LTC2308 spi datain signal
input wire ADC_SDO, //LTC2308 spi dataout signal
output reg uart_tx //UART tx signal baud rate = 115200
);
wire [31:0] verti_counter;
wire [3:0] serial_counter;
clockpll pll(.globalclock(globalclock), //pll module
.rst(rst),
.dac_clk(tx_spi_sclk_wire),//spi clock, ----- if you want to boost the scanning speed, just boost the clock in clockpll.v -----
.adc_clk(adc_clk), //LTC2308 clock, 12.5M
.adc_clk_delay(adc_clk_delay), //LTC2308 delayed clock, 12.5M, phase shift 180 degrees
.uart_clk(UART_CLK) //UART Clock, Baud rate 115200
);
DAC_control DAC_control_inst(
.tx_spi_sclk_wire(tx_spi_sclk_wire),
.rst(rst),
.tx_spi_sync(tx_spi_sync),
.tx_spi_din(tx_spi_din),
.adc_start(adc_start),
.verti_counter(verti_counter),
.serial_counter(serial_counter),
.loop(loop)
);
assign tx_spi_sclk = tx_spi_sclk_wire; //output tx_spi_sclk
//----------------------------------------------------------------------------------//ADC Module
wire [23:0] fifo_data;
wire [11:0] measure_count;
ADC_control ADC_control_inst(
.adc_clk(adc_clk),
.adc_clk_delay(adc_clk_delay),
.adc_start(adc_start),
.ADC_CONVST(ADC_CONVST),
.ADC_SCK(ADC_SCK),
.ADC_SDI(ADC_SDI),
.ADC_SDO(ADC_SDO),
.rst(rst),
.loop(loop),
.serial_counter(serial_counter),
.verti_counter(verti_counter),
.fifo_data(fifo_data),
.measure_count(measure_count),
.measure_done(measure_done));
//-----------------------------------------------------------------------------//FIFO Module
wire [1:0] uart_counter_wire;
wire [23:0] q_sig_wire;
wire idle;
FIFO_control FIFO_control_inst(
.tx_spi_sclk_wire(tx_spi_sclk_wire),
.rst(rst),
.idle(idle),
.uart_counter(uart_counter_wire),
.serial_counter(serial_counter),
.measure_count(measure_count),
.fifo_data(fifo_data),
.measure_done(measure_done),
.q_sig_wire(q_sig_wire));
//----------------------------------------------------------------------------//UART Module
uart_control uart_control_inst(
.globalclock(globalclock),
.verti_counter(verti_counter),
.UART_CLK(UART_CLK),
.rst(rst),
.q_sig(q_sig_wire),
.uart_tx_wire(uart_tx_wire),
.idle(idle),
.uart_counter(uart_counter_wire));
always@(*) uart_tx = uart_tx_wire;
endmodule
| 6.708858 |
module bj_detect (
BRANCH_JUMP,
DATA1,
DATA2,
PC_SEL_OUT
);
input [2:0] BRANCH_JUMP;
output PC_SEL_OUT;
input [31:0] DATA1, DATA2;
wire eq, unsign_lt, sign_lt, PC_SEL;
reg lt;
wire out1, out2, out3, out4, out5;
assign #2 PC_SEL_OUT = PC_SEL;
assign eq = DATA1 == DATA2 ? 1 : 0;
assign unsign_lt = DATA1 < DATA2;
assign sign_lt = ($signed(DATA1) < $signed(DATA2));
always @(*) begin
case (BRANCH_JUMP[2:1])
2'b11: lt = unsign_lt;
default: lt = sign_lt;
endcase
end
and logicAnd1 (out1, !BRANCH_JUMP[2], BRANCH_JUMP[0], !eq);
and logicAnd2 (out2, !BRANCH_JUMP[2], BRANCH_JUMP[1], BRANCH_JUMP[0]);
and logicAnd3 (out3, BRANCH_JUMP[2], !BRANCH_JUMP[0], lt);
and logicAnd4 (out4, BRANCH_JUMP[2], eq, lt);
and logicAnd5 (out5, BRANCH_JUMP[2], BRANCH_JUMP[0], !lt);
and logicAnd6 (out6, !BRANCH_JUMP[2], !BRANCH_JUMP[1], !BRANCH_JUMP[0], eq);
or logicOr (PC_SEL, out1, out2, out3, out4, out5, out6);
endmodule
| 8.110429 |
module BK_0011M (
XT5_in_pin,
XT5_out_pin,
nSEL2,
DOUT,
nWRTBT,
STROBE,
END
);
// контакты разъёма XT5 (вход/выход УП)
input [15:0] XT5_in_pin;
output [15:0] XT5_out_pin;
output nSEL2, STROBE, nWRTBT, DOUT, END;
parameter cycle = 250; // период тактовой частоты, нс
reg clk; // тактовый сигнал
integer cnt; // счетчик тактов
// регистры УП
reg [15:0] UP_out_reg, UP_in_reg;
// Шина адреса/данных
tri1 [15:0] nAD;
// Шина управления
tri1 nSYNC, nWTBT, nDIN, nDOUT;
wire nBSY, nRPLY, nSEL1, nSEL2;
assign #(40) XT5_out_pin = UP_out_reg; // задержка распространения ИР22 40 нс
assign nWRTBT = nWTBT;
// тактовый генератор
initial begin
cnt = 0;
clk = 1;
forever begin
#(cycle / 4) clk = 0;
#(cycle / 2);
clk = 1;
#(cycle / 4);
++cnt;
end
end
// ЦПУ
// CLKp, nBSYp, nADp, nSYNCp, nWTBTp, nDINp, nDOUTp, nRPLYp, nSEL1p, nSEL2p
cpu_emulator #(
.dT(cycle)
) CPU1 (
.CLKp(clk),
.nBSYp(nBSY),
.nADp(nAD),
.nSYNCp(nSYNC),
.nWTBTp(nWTBT),
.nDINp(nDIN),
.nDOUTp(nDOUT),
.nRPLYp(nRPLY),
.nSEL1p(nSEL1),
.nSEL2p(nSEL2),
.simulation_end(END)
);
// комбинационная логика на плате БК0011М
parameter ln1_delay = 15; // задержка К555ЛН1
parameter la3_delay = 15; // задержка К555ЛА3
parameter le1_delay = 15; // задержка К555ЛЕ1
assign #(ln1_delay) DOUT = ~nDOUT; // D1, выв. 4
// формирователь строба записи в выходной регистр УП
parameter RC_delay = 55; // время заряда конденсатора RC цепочки до порога переключения, нс
wire #(0, RC_delay) ndout_delayed = nDOUT;
assign #(le1_delay) STROBE = ~(nSEL2 | ndout_delayed); // D30, выв. 1
// сигнал выборки входного регистра УП
wire nE0 = nDIN | nSEL2;
// данные из входного регистра УП
assign nAD = ~nE0 ? UP_in_reg : 16'bz;
// запись в выходной регистр УП
always @(posedge STROBE) UP_out_reg <= nAD;
// фиксирование состояния входных линий УП во входном регистре УП
// (в схеме БК-00011М это происходит при любом активном чтении на шине)
always @(negedge nDIN) UP_in_reg <= XT5_in_pin;
endmodule
| 6.506026 |
module bk321 (
input [15:0] A,
input [15:0] B,
input cin,
output [15:0] sum,
output cout
);
wire [15:0] sum0;
bk32 minus (
.A (~B),
.B (1),
.cin(0),
.sum(sum0)
);
bk32 minus1 (
.A (sum0),
.B (A),
.cin(0),
.sum(sum)
);
endmodule
| 6.901768 |
module stage0 (
P,
G,
a,
b
);
input [7:0] a, b;
output [7:0] P, G;
assign P[0] = a[0] ^ b[0],
P[1] = a[1] ^ b[1],
P[2] = a[2] ^ b[2],
P[3] = a[3] ^ b[3],
P[4] = a[4] ^ b[4],
P[5] = a[5] ^ b[5],
P[6] = a[6] ^ b[6],
P[7] = a[7] ^ b[7],
G[0] = a[0] & b[0],
G[1] = a[1] & b[1],
G[2] = a[2] & b[2],
G[3] = a[3] & b[3],
G[4] = a[4] & b[4],
G[5] = a[5] & b[5],
G[6] = a[6] & b[6],
G[7] = a[7] & b[7];
endmodule
| 6.706914 |
module tbBK;
wire [7:0] s;
wire cout;
reg [7:0] a, b;
reg cin;
BKadd8 BK (
a,
b,
cin,
s,
cout
);
initial begin
a <= 8'b10100011;
b <= 8'b10101111;
cin <= 1'b0;
#20 $finish;
end
endmodule
| 6.826173 |
module BK_16b_tb ();
wire [16:0] out0;
reg [15:0] in0;
reg [15:0] in1;
integer i, file, mem, temp;
BK_16b U0 (
in0,
in1,
out0
);
initial begin
$display("-- Begining Simulation --");
$dumpfile("./BK_16b.vcd");
$dumpvars(0, BK_16b_tb);
file = $fopen("output.txt", "w");
mem = $fopen("dataset", "r");
in0 = 0;
in1 = 0;
#10
for (i = 0; i < 1000000; i = i + 1) begin
temp = $fscanf(mem, "%h %h \n", in0, in1);
#10 $fwrite(file, "%d\n", {out0});
$display("-- Progress: %d/1000000 --", i + 1);
end
$fclose(file);
$fclose(mem);
$finish;
end
endmodule
| 6.825766 |
module blabla_qr (
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] internal_a_prim;
reg [63 : 0] internal_b_prim;
reg [63 : 0] internal_c_prim;
reg [63 : 0] internal_d_prim;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
//----------------------------------------------------------------
// qr
//
// The actual quarterround function.
//----------------------------------------------------------------
always @* begin : qr
reg [63 : 0] a0;
reg [63 : 0] a1;
reg [63 : 0] b0;
reg [63 : 0] b1;
reg [63 : 0] b2;
reg [63 : 0] b3;
reg [63 : 0] c0;
reg [63 : 0] c1;
reg [63 : 0] d0;
reg [63 : 0] d1;
reg [63 : 0] d2;
reg [63 : 0] d3;
a0 = a + b;
d0 = d ^ a0;
d1 = {d0[15 : 0], d0[31 : 16]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[19 : 0], b0[31 : 20]};
a1 = a0 + b1;
d2 = d1 ^ a1;
d3 = {d2[23 : 0], d2[31 : 24]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[24 : 0], b2[31 : 25]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end // qr
endmodule
| 7.435374 |
module to allow
// us to build versions of the cipher with 1, 2, 4 and even 8
// parallel qr functions.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2017 Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blabla_qr(
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] internal_a_prim;
reg [63 : 0] internal_b_prim;
reg [63 : 0] internal_c_prim;
reg [63 : 0] internal_d_prim;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
//----------------------------------------------------------------
// qr
//
// The actual quarterround function.
//----------------------------------------------------------------
always @*
begin : qr
reg [63 : 0] a0;
reg [63 : 0] a1;
reg [63 : 0] b0;
reg [63 : 0] b1;
reg [63 : 0] b2;
reg [63 : 0] b3;
reg [63 : 0] c0;
reg [63 : 0] c1;
reg [63 : 0] d0;
reg [63 : 0] d1;
reg [63 : 0] d2;
reg [63 : 0] d3;
a0 = a + b;
d0 = d ^ a0;
d1 = {d0[15 : 0], d0[31 : 16]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[19 : 0], b0[31 : 20]};
a1 = a0 + b1;
d2 = d1 ^ a1;
d3 = {d2[23 : 0], d2[31 : 24]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[24 : 0], b2[31 : 25]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end // qr
endmodule
| 7.487454 |
module black (
input G_i,
P_i,
G_k,
P_k,
output G_j,
P_j
);
and (P_j, P_i, P_k);
wire tr;
and (tr, P_i, G_k);
or (G_j, G_i, tr);
endmodule
| 6.62003 |
module BlackBlock (
G_i_k,
P_i_k,
G_km1_j,
P_km1_j,
G_i_j,
P_i_j
);
input G_i_k;
input P_i_k;
input G_km1_j;
input P_km1_j;
output G_i_j;
output P_i_j;
assign G_i_j = G_i_k | (P_i_k & G_km1_j);
assign P_i_j = P_i_k & P_km1_j;
endmodule
| 6.986558 |
module x64 #(
parameter N = 64, // N logical LUTs
parameter M = 4, // M contexts
parameter B = 4, // subcluster branching factor
parameter B_SUB = 4, // sub-subcluster branching factor
parameter K = 4, // K-input LUTs
parameter LB_IB = K, // no. of LB input buffers
parameter CFG_W = 5, // config I/O width
parameter IO_I_W = 0, // parallel IO input width
parameter IO_O_W = 0, // parallel IO output width
parameter UP_I_WS = 08_08_16, // up switch serial input widths
parameter UP_O_WS = 04_04_08, // up switch serial output widths
parameter UP_O_DELAY = 0, // default up_o delay
parameter ID = 0, // cluster identifier ::= ID of its first LB
parameter UP_I_W = UP_I_WS%100, // up switch serial input width
parameter UP_O_W = UP_O_WS%100, // up switch serial output width
parameter DN_I_W = UP_O_WS/100%100, // down switches' serial input width
parameter DN_O_W = UP_I_WS/100%100 // down switches' serial output width
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input clk, // clock
input rst, // sync reset
input grst, // S3GA configuration in progress
input `CNT(M) m, // cycle % M
input cfg, // config enable
output cfgd, // cluster is configured
input `V(CFG_W) cfg_i, // config input
input `V(IO_I_W) io_i, // parallel IO inputs
output `V(IO_O_W) io_o, // parallel IO outputs
input `V(UP_I_W) up_i, // up switch serial inputs
output `V(UP_O_W) up_o // up switch serial outputs
);
endmodule
| 8.223463 |
module BlackBoxAdder (
input [32:0] in1,
input [32:0] in2,
output [33:0] out
);
always @* begin
out <= ((in1) + (in2));
end
endmodule
| 7.24337 |
module is added as a reference only. Please add library
// cells for delay buffers and muxes from the foundry that is fabricating your SoC.
module BlackBoxDelayBuffer ( in, mux_out, out, sel
);
input in;
output mux_out;
output out;
input [4:0] sel;
assign mux_out = in;
assign out = in;
endmodule
| 6.820226 |
module BlackBoxInverter (
input [0:0] in,
output [0:0] out
);
assign out = !in;
endmodule
| 8.613857 |
module BlackBoxPassthrough (
input [0:0] in,
output [0:0] out
);
assign out = in;
endmodule
| 7.611223 |
module BlackBoxPassthrough2 (
input [0:0] in,
output [0:0] out
);
assign out = in;
endmodule
| 7.611223 |
module BlackBoxMinus (
input [15:0] in1,
input [15:0] in2,
output [15:0] out
);
assign out = in1 + in2;
endmodule
| 8.136331 |
module BlackBoxRegister (
input [0:0] clock,
input [0:0] in,
output [0:0] out
);
reg [0:0] register;
always @(posedge clock) begin
register <= in;
end
assign out = register;
endmodule
| 7.056767 |
module BlackBoxConstant #(
parameter int WIDTH = 1,
parameter int VALUE = 1
) (
output [WIDTH-1:0] out
);
assign out = VALUE;
endmodule
| 8.335849 |
module BlackBoxStringParam #(
parameter string STRING = "zero"
) (
output [31:0] out
);
assign out = (STRING == "one") ? 1 : (STRING == "two") ? 2 : 0;
endmodule
| 9.526617 |
module BlackBoxRealParam #(
parameter real REAL = 0.0
) (
output [63:0] out
);
assign out = $realtobits(REAL);
endmodule
| 8.706008 |
module BlackBoxTypeParam #(
parameter type T = bit
) (
output T out
);
assign out = 32'hdeadbeef;
endmodule
| 7.576245 |
module BlackBoxToTest #(
parameter aWidth = 0,
parameter bWidth = 0
) (
input [aWidth-1:0] io_inA,
input [bWidth-1:0] io_inB,
output reg [aWidth-1:0] io_outA,
output reg [bWidth-1:0] io_outB,
input io_clockPin,
input io_resetPin
);
always @(posedge io_clockPin or posedge io_resetPin) begin
if (io_resetPin) begin
io_outA <= 0;
io_outB <= 0;
end else begin
io_outA <= io_outA + io_inA;
io_outB <= io_outB + io_inB;
end
end
endmodule
| 6.802355 |
module Black (
G6_8,
P6_8,
G7_10,
P7_10,
G6_10,
P6_10
);
input G6_8, P6_8, G7_10, P7_10;
output G6_10, P6_10;
wire s1;
assign s1 = P6_8 & G7_10;
assign G6_10 = s1 | G6_8;
assign P6_10 = P6_8 & P7_10;
endmodule
| 6.530159 |
module Black (
G6_8,
P6_8,
G7_10,
P7_10,
G6_10,
P6_10
);
input G6_8, P6_8, G7_10, P7_10;
output G6_10, P6_10;
wire s1;
assign s1 = P6_8 & G7_10;
assign G6_10 = s1 | G6_8;
assign P6_10 = P6_8 & P7_10;
endmodule
| 6.530159 |
module BufferCC (
input io_initial,
input io_dataIn,
output io_dataOut,
input clock_out,
input clockCtrl_systemReset
);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clock_out) begin
if (clockCtrl_systemReset) begin
buffers_0 <= io_initial;
buffers_1 <= io_initial;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.712921 |
module BufferCC_1_ (
input io_dataIn,
output io_dataOut,
input clock_out,
input clockCtrl_resetUnbuffered_regNext
);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clock_out) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 7.044402 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input [15:0] io_push_payload_data,
input [4:0] io_push_payload_context_context,
output reg io_pop_valid,
input io_pop_ready,
output reg [15:0] io_pop_payload_data,
output reg [4:0] io_pop_payload_context_context,
input io_flush,
output [1:0] io_occupancy,
input clock_out,
input clockCtrl_systemReset
);
wire [20:0] _zz_3_;
wire _zz_4_;
wire [4:0] _zz_5_;
wire [20:0] _zz_6_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
reg [0:0] pushPtr_valueNext;
reg [0:0] pushPtr_value;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
reg [0:0] popPtr_valueNext;
reg [0:0] popPtr_value;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire [20:0] _zz_2_;
wire [0:0] ptrDif;
reg [20:0] ram[0:1];
assign _zz_4_ = (!empty);
assign _zz_5_ = _zz_2_[20 : 16];
assign _zz_6_ = {io_push_payload_context_context, io_push_payload_data};
always @(posedge clock_out) begin
if (_zz_1_) begin
ram[pushPtr_value] <= _zz_6_;
end
end
assign _zz_3_ = ram[popPtr_value];
always @(*) begin
_zz_1_ = 1'b0;
if (pushing) begin
_zz_1_ = 1'b1;
end
end
always @(*) begin
pushPtr_willIncrement = 1'b0;
if (pushing) begin
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
if (io_flush) begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = (pushPtr_value == (1'b1));
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
pushPtr_valueNext = (pushPtr_value + pushPtr_willIncrement);
if (pushPtr_willClear) begin
pushPtr_valueNext = (1'b0);
end
end
always @(*) begin
popPtr_willIncrement = 1'b0;
if (popping) begin
popPtr_willIncrement = 1'b1;
end
end
always @(*) begin
popPtr_willClear = 1'b0;
if (io_flush) begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = (popPtr_value == (1'b1));
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
always @(*) begin
popPtr_valueNext = (popPtr_value + popPtr_willIncrement);
if (popPtr_willClear) begin
popPtr_valueNext = (1'b0);
end
end
assign ptrMatch = (pushPtr_value == popPtr_value);
assign empty = (ptrMatch && (!risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (!full);
always @(*) begin
if (_zz_4_) begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
assign _zz_2_ = _zz_3_;
always @(*) begin
if (_zz_4_) begin
io_pop_payload_data = _zz_2_[15 : 0];
end else begin
io_pop_payload_data = io_push_payload_data;
end
end
always @(*) begin
if (_zz_4_) begin
io_pop_payload_context_context = _zz_5_[4 : 0];
end else begin
io_pop_payload_context_context = io_push_payload_context_context;
end
end
assign ptrDif = (pushPtr_value - popPtr_value);
assign io_occupancy = {(risingOccupancy && ptrMatch), ptrDif};
always @(posedge clock_out) begin
if (clockCtrl_systemReset) begin
pushPtr_value <= (1'b0);
popPtr_value <= (1'b0);
risingOccupancy <= 1'b0;
end else begin
pushPtr_value <= pushPtr_valueNext;
popPtr_value <= popPtr_valueNext;
if ((pushing != popping)) begin
risingOccupancy <= pushing;
end
if (io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
endmodule
| 7.046487 |
module UartCtrl (
input [2:0] io_config_frame_dataLength,
input `UartStopType_defaultEncoding_type io_config_frame_stop,
input `UartParityType_defaultEncoding_type io_config_frame_parity,
input [11:0] io_config_clockDivider,
input io_write_valid,
output io_write_ready,
input [7:0] io_write_payload,
output io_read_valid,
output [7:0] io_read_payload,
output io_uart_txd,
input io_uart_rxd,
input clock_out,
input clockCtrl_systemReset
);
wire tx_io_write_ready;
wire tx_io_txd;
wire rx_io_read_valid;
wire [7:0] rx_io_read_payload;
reg [11:0] clockDivider_counter;
wire clockDivider_tick;
`ifndef SYNTHESIS
reg [23:0] io_config_frame_stop_string;
reg [31:0] io_config_frame_parity_string;
`endif
UartCtrlTx tx (
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_stop(io_config_frame_stop),
.io_configFrame_parity(io_config_frame_parity),
.io_samplingTick(clockDivider_tick),
.io_write_valid(io_write_valid),
.io_write_ready(tx_io_write_ready),
.io_write_payload(io_write_payload),
.io_txd(tx_io_txd),
.clock_out(clock_out),
.clockCtrl_systemReset(clockCtrl_systemReset)
);
UartCtrlRx rx (
.io_configFrame_dataLength(io_config_frame_dataLength),
.io_configFrame_stop(io_config_frame_stop),
.io_configFrame_parity(io_config_frame_parity),
.io_samplingTick(clockDivider_tick),
.io_read_valid(rx_io_read_valid),
.io_read_payload(rx_io_read_payload),
.io_rxd(io_uart_rxd),
.clock_out(clock_out),
.clockCtrl_systemReset(clockCtrl_systemReset)
);
`ifndef SYNTHESIS
always @(*) begin
case (io_config_frame_stop)
`UartStopType_defaultEncoding_ONE: io_config_frame_stop_string = "ONE";
`UartStopType_defaultEncoding_TWO: io_config_frame_stop_string = "TWO";
default: io_config_frame_stop_string = "???";
endcase
end
always @(*) begin
case (io_config_frame_parity)
`UartParityType_defaultEncoding_NONE: io_config_frame_parity_string = "NONE";
`UartParityType_defaultEncoding_EVEN: io_config_frame_parity_string = "EVEN";
`UartParityType_defaultEncoding_ODD: io_config_frame_parity_string = "ODD ";
default: io_config_frame_parity_string = "????";
endcase
end
`endif
assign clockDivider_tick = (clockDivider_counter == (12'b000000000000));
assign io_write_ready = tx_io_write_ready;
assign io_read_valid = rx_io_read_valid;
assign io_read_payload = rx_io_read_payload;
assign io_uart_txd = tx_io_txd;
always @(posedge clock_out) begin
if (clockCtrl_systemReset) begin
clockDivider_counter <= (12'b000000000000);
end else begin
clockDivider_counter <= (clockDivider_counter - (12'b000000000001));
if (clockDivider_tick) begin
clockDivider_counter <= io_config_clockDivider;
end
end
end
endmodule
| 7.177325 |
module BufferCC_2_ (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input clock_out,
input clockCtrl_systemReset
);
reg [7:0] buffers_0;
reg [7:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clock_out) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 7.089398 |
module StreamFifoLowLatency_1_ (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output [0:0] io_occupancy,
input clock_out,
input clockCtrl_systemReset
);
wire _zz_5_;
wire [0:0] _zz_6_;
reg _zz_1_;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire [32:0] _zz_2_;
wire [32:0] _zz_3_;
reg [32:0] _zz_4_;
assign _zz_5_ = (!empty);
assign _zz_6_ = _zz_2_[0 : 0];
always @(*) begin
_zz_1_ = 1'b0;
if (pushing) begin
_zz_1_ = 1'b1;
end
end
always @(*) begin
pushPtr_willIncrement = 1'b0;
if (pushing) begin
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
if (io_flush) begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = 1'b1;
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
popPtr_willIncrement = 1'b0;
if (popping) begin
popPtr_willIncrement = 1'b1;
end
end
always @(*) begin
popPtr_willClear = 1'b0;
if (io_flush) begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = 1'b1;
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
assign ptrMatch = 1'b1;
assign empty = (ptrMatch && (!risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (!full);
always @(*) begin
if (_zz_5_) begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
assign _zz_2_ = _zz_3_;
always @(*) begin
if (_zz_5_) begin
io_pop_payload_error = _zz_6_[0];
end else begin
io_pop_payload_error = io_push_payload_error;
end
end
always @(*) begin
if (_zz_5_) begin
io_pop_payload_inst = _zz_2_[32 : 1];
end else begin
io_pop_payload_inst = io_push_payload_inst;
end
end
assign io_occupancy = (risingOccupancy && ptrMatch);
assign _zz_3_ = _zz_4_;
always @(posedge clock_out) begin
if (clockCtrl_systemReset) begin
risingOccupancy <= 1'b0;
end else begin
if ((pushing != popping)) begin
risingOccupancy <= pushing;
end
if (io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
always @(posedge clock_out) begin
if (_zz_1_) begin
_zz_4_ <= {io_push_payload_inst, io_push_payload_error};
end
end
endmodule
| 7.046487 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input clock_out,
input clockCtrl_resetUnbuffered_regNext
);
wire bufferCC_4__io_dataOut;
wire outHitSignal;
reg inputArea_target = 0;
reg inputArea_data_last;
reg [0:0] inputArea_data_fragment;
wire outputArea_target;
reg outputArea_hit;
wire outputArea_flow_valid;
wire outputArea_flow_payload_last;
wire [0:0] outputArea_flow_payload_fragment;
reg outputArea_flow_m2sPipe_valid;
reg outputArea_flow_m2sPipe_payload_last;
reg [0:0] outputArea_flow_m2sPipe_payload_fragment;
BufferCC_1_ bufferCC_4_ (
.io_dataIn(inputArea_target),
.io_dataOut(bufferCC_4__io_dataOut),
.clock_out(clock_out),
.clockCtrl_resetUnbuffered_regNext(clockCtrl_resetUnbuffered_regNext)
);
assign outputArea_target = bufferCC_4__io_dataOut;
assign outputArea_flow_valid = (outputArea_target != outputArea_hit);
assign outputArea_flow_payload_last = inputArea_data_last;
assign outputArea_flow_payload_fragment = inputArea_data_fragment;
assign io_output_valid = outputArea_flow_m2sPipe_valid;
assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last;
assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment;
always @(posedge io_jtag_tck) begin
if (io_input_valid) begin
inputArea_target <= (!inputArea_target);
inputArea_data_last <= io_input_payload_last;
inputArea_data_fragment <= io_input_payload_fragment;
end
end
always @(posedge clock_out) begin
outputArea_hit <= outputArea_target;
if (outputArea_flow_valid) begin
outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last;
outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment;
end
end
always @(posedge clock_out) begin
if (clockCtrl_resetUnbuffered_regNext) begin
outputArea_flow_m2sPipe_valid <= 1'b0;
end else begin
outputArea_flow_m2sPipe_valid <= outputArea_flow_valid;
end
end
endmodule
| 7.790686 |
module BufferCC_3_ (
input io_dataIn,
output io_dataOut,
input clock_out
);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clock_out) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 7.324384 |
module was generated automatically
* using the icepll tool from the IceStorm project.
* Use at your own risk.
*
* Given input frequency: 25.000 MHz
* Requested output frequency: 16.000 MHz
* Achieved output frequency: 16.016 MHz
*/
module blackice_mx_pll(
input clock_in,
output clock_out,
output sdram_clock_out,
output locked
);
SB_PLL40_2F_CORE #(
.FEEDBACK_PATH("SIMPLE"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
.PLLOUT_SELECT_PORTA("GENCLK"),
.PLLOUT_SELECT_PORTB("GENCLK"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000), // DIVR = 0
.DIVF(7'b0101000), // DIVF = 40
.DIVQ(3'b110), // DIVQ = 6
.FILTER_RANGE(3'b010) // FILTER_RANGE = 2
) pll (
.REFERENCECLK (clock_in),
.PLLOUTGLOBALA (clock_out),
.PLLOUTGLOBALB (sdram_clock_out),
.LOCK (locked),
.BYPASS (1'b0),
.RESETB (1'b1)
);
endmodule
| 7.841705 |
module randomGenerator (
clk,
key,
randResult
);
input clk;
input [3:0] key;
output [3:0] randResult;
reg [32:0] cnt;
reg [ 3:0] randTemp;
initial begin
randTemp = 0;
cnt = 0;
end
always @(posedge clk) begin
if (key[1] == 0 | key[2] == 0 | key[3] == 0) cnt = cnt + 1;
else randTemp = cnt % 15 + 1;
if (cnt == 500000000) cnt = 0;
end
assign randResult = randTemp;
endmodule
| 6.649502 |
module display_7seg2 (
sw,
HEX
);
input [3:0] sw;
output [0:6] HEX;
assign HEX = (sw == 4'b0000) ? 7'b0000001 : //0
(sw == 4'b0001) ? 7'b1001111 : //1
(sw == 4'b0010) ? 7'b0010010 : //2
(sw == 4'b0011) ? 7'b0000110 : //3
(sw == 4'b0100) ? 7'b1001100 : //4
(sw == 4'b0101) ? 7'b0100100 : //5
(sw == 4'b0110) ? 7'b0100000 : //6
(sw == 4'b0111) ? 7'b0001101 : //7
(sw == 4'b1000) ? 7'b0000000 : //8
(sw == 4'b1001) ? 7'b0000100 : //9
7'b1111111;
endmodule
| 6.760025 |
module display_7seg (
sw,
cntl,
res,
HEX
);
input [3:0] sw;
input [2:0] res;
input cntl;
output [0:6] HEX;
assign HEX = (sw == 4'b0001 && cntl == 0) ? 7'b0001000 : //A
(sw == 4'b0010 && cntl == 0) ? 7'b0010010 : //2
(sw == 4'b0011 && cntl == 0) ? 7'b0000110 : //3
(sw == 4'b0100 && cntl == 0) ? 7'b1001100 : //4
(sw == 4'b0101 && cntl == 0) ? 7'b0100100 : //5
(sw == 4'b0110 && cntl == 0) ? 7'b0100000 : //6
(sw == 4'b0111 && cntl == 0) ? 7'b0001101 : //7
(sw == 4'b1000 && cntl == 0) ? 7'b0000000 : //8
(sw == 4'b1001 && cntl == 0) ? 7'b0000100 : //9
(sw == 4'b1010 && cntl == 0) ? 7'b0000001 : //10
(sw == 4'b1011 && cntl == 0) ? 7'b0100111 : //j
(sw == 4'b1100 && cntl == 0) ? 7'b0001100 : //q
(sw == 4'b1101 && cntl == 0) ? 7'b1111000:
(sw >= 4'b1110 && cntl == 0) ? 7'b1111111: //k else nothing
(res == 3'b000 && cntl == 1) ? 7'b0000001:
(res == 3'b001 && cntl == 1) ? 7'b1001111:
(res == 3'b010 && cntl == 1) ? 7'b0010010:
(res == 3'b011 && cntl == 1) ? 7'b0000110:
(res == 3'b100 && cntl == 1) ? 7'b1001100: 7'b1111111;
endmodule
| 7.0436 |
module blackjack_game_test (
input clock_100Mhz,
reset,
staylever,
output reg [7:0] Anode_Activate,
output reg [6:0] LED_out
);
reg [ 4:0] LED_BCD;
reg [19:0] refresh_counter;
wire [ 2:0] LED_activating_counter;
reg [4:0] out0, out1, out2, out3, out4, out5, out6, out7;
integer seed = 1337;
integer i;
integer cards[0:51];
integer fcards[0:51];
reg [5:0] r;
integer playercards[0:10];
integer dealercards[0:10];
initial begin
//generating the array of cards
for (i = 0; i < 52; i = i + 1) cards[i] = i;
r = $random(seed) % 52;
while (i > 0) begin
if (cards[r] != -1) begin
fcards[i-1] = r + 1;
cards[r] = -1;
i = i - 1;
end
r = $random(seed) % 52;
end
//assigning initial cards for player and dealer
playercards[0] = (((fcards[i] % 12) + 1) > 10) ? 10 : ((fcards[i] % 12) + 1);
i = i + 1;
playercards[1] = (((fcards[i] % 12) + 1) > 10) ? 10 : ((fcards[i] % 12) + 1);
i = i + 1;
dealercards[0] = (((fcards[i] % 12) + 1) > 10) ? 10 : ((fcards[i] % 12) + 1);
i = i + 1;
dealercards[1] = (((fcards[i] % 12) + 1) > 10) ? 10 : ((fcards[i] % 12) + 1);
i = i + 1;
end
always @(posedge clock_100Mhz) begin
if (!reset) begin
if (staylever) begin
// out0 = 20; //YAY
// out1 = 20;
// out2 = 20;
// out3 = 20;
// out4 = 20;
// out5 = 14;
// out6 = 12;
// out7 = 14;
end else begin
out0 = 20; //READY?
out1 = 20;
out2 = 10;
out3 = 11;
out4 = 12;
out5 = 13;
out6 = 14;
out7 = 21;
end
end
end
always @(posedge clock_100Mhz or posedge reset) begin
if (reset) refresh_counter <= 0;
else refresh_counter <= refresh_counter + 1;
end
assign LED_activating_counter = refresh_counter[19:17];
always @(*) begin
case (LED_activating_counter)
0: begin
Anode_Activate = 8'b01111111;
LED_BCD = out0;
end
1: begin
Anode_Activate = 8'b10111111;
LED_BCD = out1;
end
2: begin
Anode_Activate = 8'b11011111;
LED_BCD = out2;
end
3: begin
Anode_Activate = 8'b11101111;
LED_BCD = out3;
end
4: begin
Anode_Activate = 8'b11110111;
LED_BCD = out4;
end
5: begin
Anode_Activate = 8'b11111011;
LED_BCD = out5;
end
6: begin
Anode_Activate = 8'b11111101;
LED_BCD = out6;
end
7: begin
Anode_Activate = 8'b11111110;
LED_BCD = out7;
end
endcase
end
always @(*) begin
case (LED_BCD)
0: LED_out = 7'b0000001; //0 or O
1: LED_out = 7'b1001111; //1 or I
2: LED_out = 7'b0010010; //2
3: LED_out = 7'b0000110; //3
4: LED_out = 7'b1001100; //4
5: LED_out = 7'b0100100; //5 or S
6: LED_out = 7'b0100000; //6
7: LED_out = 7'b0001111; //7
8: LED_out = 7'b0000000; //8
9: LED_out = 7'b0000100; //9
10: LED_out = 7'b0011001; //R
11: LED_out = 7'b0110000; //E
12: LED_out = 7'b0001000; //A
13: LED_out = 7'b1000010; //D
14: LED_out = 7'b1000100; //Y
15: LED_out = 7'b1000001; //U
16: LED_out = 7'b1110001; //L
17: LED_out = 7'b1010101; //W
18: LED_out = 7'b0001001; //N
19: LED_out = 7'b1110000; //T
20: LED_out = 7'b1111111; //blank
21: LED_out = 7'b0011010; //?
default: LED_out = 7'b1111111; //blank
endcase
end
endmodule
| 7.10863 |
module BSnowman_RAM_IN (
pix_val,
indx,
wren
);
input [9:0] indx;
output [15:0] pix_val;
output reg wren;
reg [15:0] pix_val;
reg [15:0] in_ram [839:0];
always @(indx) begin
pix_val = in_ram[indx];
wren = pix_val[0];
end
initial begin
$readmemb("BlackSnowman.txt", in_ram);
end
endmodule
| 6.780081 |
module blackwhite (
vin_rsc_z,
threshold_rsc_z,
vout_rsc_z,
clk,
en,
arst_n
);
input [29:0] vin_rsc_z;
input [9:0] threshold_rsc_z;
output [29:0] vout_rsc_z;
input clk;
input en;
input arst_n;
// Interconnect Declarations
wire [29:0] vin_rsc_mgc_in_wire_d;
wire [ 9:0] threshold_rsc_mgc_in_wire_d;
wire [29:0] vout_rsc_mgc_out_stdreg_d;
// Interconnect Declarations for Component Instantiations
mgc_in_wire #(
.rscid(1),
.width(30)
) vin_rsc_mgc_in_wire (
.d(vin_rsc_mgc_in_wire_d),
.z(vin_rsc_z)
);
mgc_in_wire #(
.rscid(2),
.width(10)
) threshold_rsc_mgc_in_wire (
.d(threshold_rsc_mgc_in_wire_d),
.z(threshold_rsc_z)
);
mgc_out_stdreg #(
.rscid(3),
.width(30)
) vout_rsc_mgc_out_stdreg (
.d(vout_rsc_mgc_out_stdreg_d),
.z(vout_rsc_z)
);
blackwhite_core blackwhite_core_inst (
.clk(clk),
.en(en),
.arst_n(arst_n),
.vin_rsc_mgc_in_wire_d(vin_rsc_mgc_in_wire_d),
.threshold_rsc_mgc_in_wire_d(threshold_rsc_mgc_in_wire_d),
.vout_rsc_mgc_out_stdreg_d(vout_rsc_mgc_out_stdreg_d)
);
endmodule
| 7.074218 |
module black_background_graphic (
x,
y,
flush_x,
flush_y,
colour,
enable
);
input [6:0] x;
input [6:0] y;
input [6:0] flush_x;
input [6:0] flush_y;
output reg [5:0] colour;
output reg enable;
always @(*) begin
colour <= 6'b000000;
enable <= 1;
end
endmodule
| 6.504831 |
module black_box (
input a,
b,
c,
d,
output x,
y
);
assign x = a | (b & c);
assign y = b & d;
endmodule
| 7.235556 |
module black_box1 (
in1,
in2,
dout
);
input in1, in2;
output dout;
endmodule
| 6.756224 |
module blake2b_G (
input wire clk_i,
input wire rst_i,
// input signals
input wire [ `GINDEX_BUS] index_i,
input wire [`ROUND_INDEX_BUS] round_i,
input wire [ `WORD_BUS] a_i,
input wire [ `WORD_BUS] b_i,
input wire [ `WORD_BUS] c_i,
input wire [ `WORD_BUS] d_i,
//signals to sigma table
output wire [`SIGMA_INDEX_BUS] sigma_column_0_o,
output wire [`SIGMA_INDEX_BUS] sigma_row_0_o,
input wire [ `MINDEX_BUS] mindex_0_i,
output wire [`SIGMA_INDEX_BUS] sigma_column_1_o,
output wire [`SIGMA_INDEX_BUS] sigma_row_1_o,
input wire [ `MINDEX_BUS] mindex_1_i,
// signals to message block
output wire [`MINDEX_BUS] mindex_0_o,
input wire [ `WORD_BUS] m_0_i,
output wire [`MINDEX_BUS] mindex_1_o,
input wire [ `WORD_BUS] m_1_i,
// output signals
output reg [`WORD_BUS] a_o,
output reg [`WORD_BUS] b_o,
output reg [`WORD_BUS] c_o,
output reg [`WORD_BUS] d_o
);
// fetch message
assign mindex_0_o = (rst_i == `RST_ENABLE) ? 4'd0 : mindex_0_i;
assign mindex_1_o = (rst_i == `RST_ENABLE) ? 4'd0 : mindex_1_i;
// fetch mindex
assign sigma_column_0_o = (rst_i == `RST_ENABLE) ? 4'd0 : {index_i,1'b0};
assign sigma_row_0_o = (rst_i == `RST_ENABLE) ? 4'd0 : round_i;
assign sigma_column_1_o = (rst_i == `RST_ENABLE) ? 4'd0 : {index_i, 1'b1};
assign sigma_row_1_o = (rst_i == `RST_ENABLE) ? 4'd0 : round_i;
// generate output signals
wire [`WORD_BUS] a_temp_0, b_temp_0, c_temp_0, d_temp_0;
assign a_temp_0 = a_i + b_i + m_0_i;
wire [`WORD_BUS] d_xor_a_0 = d_i ^ a_temp_0;
assign d_temp_0 = (d_xor_a_0 >> 32) | (d_xor_a_0 << 32);
assign c_temp_0 = c_i + d_temp_0;
wire [`WORD_BUS] b_xor_c_0 = b_i ^ c_temp_0;
assign b_temp_0 = (b_xor_c_0 >> 24) | (b_xor_c_0 << 40);
wire [`WORD_BUS] a_temp_1, b_temp_1, c_temp_1, d_temp_1;
assign a_temp_1 = a_temp_0 + b_temp_0 + m_1_i;
wire [`WORD_BUS] d_xor_a_1 = d_temp_0 ^ a_temp_1;
assign d_temp_1 = (d_xor_a_1 >> 16) | (d_xor_a_1 << 48);
assign c_temp_1 = c_temp_0 + d_temp_1;
wire [`WORD_BUS] b_xor_c_1 = b_temp_0 ^ c_temp_1;
assign b_temp_1 = (b_xor_c_1 >> 63) | (b_xor_c_1 << 1);
always @(posedge clk_i) begin
if (rst_i == `RST_ENABLE) begin
{a_o, b_o, c_o, d_o} <= {64'd0, 64'd0, 64'd0, 64'd0};
end else begin
{a_o, b_o, c_o, d_o} <= {a_temp_1, b_temp_1, c_temp_1, d_temp_1};
end
end
endmodule
| 7.034314 |
module blake2b_mhreg (
input wire clk_i,
input wire rst_i,
input wire [16*`WORD_WIDTH-1:0] m_i,
output reg [16*`WORD_WIDTH-1:0] m_o,
input wire [8*`WORD_WIDTH-1:0] h_i,
output reg [8*`WORD_WIDTH-1:0] h_o,
input wire [8*`MINDEX_WIDTH-1:0] mindex_bus_i,
output wire [8*`WORD_WIDTH-1 : 0] m_bus_o
);
always @(posedge clk_i) begin
if (rst_i == `RST_ENABLE) begin
m_o <= 0;
h_o <= 0;
end else begin
m_o <= m_i;
h_o <= h_i;
end
end
wire [`WORD_BUS] m_temp[16];
wire [`WORD_BUS] m_bus_temp[8];
wire [`MINDEX_BUS] mindex_bus_temp[8];
for (genvar i = 0; i < 16; i = i + 1) begin : gen_m_temp
assign m_temp[i] = m_o[(i+1)*`WORD_WIDTH-1 : i*`WORD_WIDTH];
end
for (genvar i = 0; i < 8; i = i + 1) begin : gen_m_bus_o
assign m_bus_o[(i+1)*`WORD_WIDTH-1 : i*`WORD_WIDTH] = m_bus_temp[i];
assign mindex_bus_temp[i] = mindex_bus_i[(i+1)*`MINDEX_WIDTH-1 : i*`MINDEX_WIDTH];
assign m_bus_temp[i] = m_temp[mindex_bus_temp[i]];
end
endmodule
| 6.869584 |
module to allow us to build versions with 1, 2, 4
// and even 8 parallel compression functions.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2018, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blake2s_G(
input wire [31 : 0] a,
input wire [31 : 0] b,
input wire [31 : 0] c,
input wire [31 : 0] d,
input wire [31 : 0] m0,
input wire [31 : 0] m1,
output wire [31 : 0] a_prim,
output wire [31 : 0] b_prim,
output wire [31 : 0] c_prim,
output wire [31 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] a1;
reg [31 : 0] a2;
reg [31 : 0] b1;
reg [31 : 0] b2;
reg [31 : 0] b3;
reg [31 : 0] b4;
reg [31 : 0] c1;
reg [31 : 0] c2;
reg [31 : 0] d1;
reg [31 : 0] d2;
reg [31 : 0] d3;
reg [31 : 0] d4;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = a2;
assign b_prim = b4;
assign c_prim = c2;
assign d_prim = d4;
//----------------------------------------------------------------
// G_function
//----------------------------------------------------------------
always @*
begin : G_function
a1 = a + b + m0;
d1 = d ^ a1;
d2 = {d1[15 : 0], d1[31 : 16]};
c1 = c + d2;
b1 = b ^ c1;
b2 = {b1[11 : 0], b1[31 : 12]};
a2 = a1 + b2 + m1;
d3 = d2 ^ a2;
d4 = {d3[7 : 0], d3[31 : 8]};
c2 = c1 + d4;
b3 = b2 ^ c2;
b4 = {b3[6 : 0], b3[31 : 7]};
end // G_function
endmodule
| 6.663653 |
module to allow us to build versions with 1, 2, 4
// and even 8 parallel compression functions.
//
//
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module blake2_G(
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
input wire [63 : 0] m0,
input wire [63 : 0] m1,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] internal_a_prim;
reg [63 : 0] internal_b_prim;
reg [63 : 0] internal_c_prim;
reg [63 : 0] internal_d_prim;
//----------------------------------------------------------------
// Concurrent connectivity for ports.
//----------------------------------------------------------------
assign a_prim = internal_a_prim;
assign b_prim = internal_b_prim;
assign c_prim = internal_c_prim;
assign d_prim = internal_d_prim;
//----------------------------------------------------------------
// G
//
// The actual G function.
//----------------------------------------------------------------
always @*
begin : G
reg [63 : 0] a0;
reg [63 : 0] a1;
reg [63 : 0] b0;
reg [63 : 0] b1;
reg [63 : 0] b2;
reg [63 : 0] b3;
reg [63 : 0] c0;
reg [63 : 0] c1;
reg [63 : 0] d0;
reg [63 : 0] d1;
reg [63 : 0] d2;
reg [63 : 0] d3;
a0 = a + b + m0;
d0 = d ^ a0;
d1 = {d0[31 : 0], d0[63 : 32]};
c0 = c + d1;
b0 = b ^ c0;
b1 = {b0[23 : 0], b0[63 : 24]};
a1 = a0 + b1 + m1;
d2 = d1 ^ a1;
d3 = {d2[15 : 0], d2[63 : 16]};
c1 = c0 + d3;
b2 = b1 ^ c1;
b3 = {b2[62 : 0], b2[63]};
internal_a_prim = a1;
internal_b_prim = b3;
internal_c_prim = c1;
internal_d_prim = d3;
end // G
endmodule
| 6.663653 |
module blake512_CB_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./blake512_CB_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.581679 |
module blake512_CB (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
blake512_CB_rom blake512_CB_rom_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 7.185163 |
module blake512_M_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) begin
ram[addr1] <= d1;
q1 <= d1;
end else q1 <= ram[addr1];
end
end
endmodule
| 6.865971 |
module blake512_M (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
blake512_M_ram blake512_M_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.d0(d0),
.we0(we0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.d1(d1),
.we1(we1),
.q1(q1)
);
endmodule
| 7.196522 |
module blake512_sigma_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
(* ram_style = "distributed" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
initial begin
$readmemh("./blake512_sigma_rom.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 7.423881 |
module blake512_sigma (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
blake512_sigma_rom blake512_sigma_rom_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 7.423881 |
module Blake_Red_Flashing_LED (
input CLK,
output LED_RED
);
reg [15:0] MclkDiv_Count;
reg [7:0] MSDiv_Count;
reg OneMsClk;
reg EighthSecondClk;
assign LED_RED = EighthSecondClk;
// Setup the 1ms counter
always @(posedge CLK) begin
if (MclkDiv_Count == 50000) begin
MclkDiv_Count <= 16'h00;
OneMsClk <= !OneMsClk;
end else MclkDiv_Count <= MclkDiv_Count + 1;
end
always @(posedge OneMsClk) begin
if (MSDiv_Count == 125) begin
MSDiv_Count <= 8'h00;
EighthSecondClk <= !EighthSecondClk;
end else MSDiv_Count <= MSDiv_Count + 1;
end
endmodule
| 7.001727 |
module Blanket_BIST (
input Clock,
output GoNoGo,
output Done
);
wire [7:0] Adr_Counter_SRAM;
wire WE_Counter_SRAM;
wire [3:0] Data_in_Counter_SRAM;
reg [10:0] Done_Counter = 0;
wire [3:0] Data_out_SRAM_Comp;
wire Comparator_output;
Counter B_Counter (
.clk(Clock),
.Counter_Address(Adr_Counter_SRAM),
.WE(WE_Counter_SRAM),
.MSB(Data_in_Counter_SRAM)
);
SRAM B_SRAM (
.data_in(Data_in_Counter_SRAM),
.clk(Clock),
.WE(WE_Counter_SRAM),
.Address(Adr_Counter_SRAM),
.data_out(Data_out_SRAM_Comp)
);
Comparator B_Comp (
.clk(Clock),
.Comp_in1(Data_in_Counter_SRAM),
.Comp_in2(Data_out_SRAM_Comp),
.Comp_out(Comparator_output),
.enable(WE_Counter_SRAM)
);
SR_FF B_SRFF (
.clk(Clock),
.s(Comparator_output),
.GoNoGo(GoNoGo)
);
always @(posedge Clock) begin
Done_Counter <= Done_Counter + 1;
end
assign Done = (Done_Counter == 1030) ? 1 : 0;
endmodule
| 6.838783 |
module blanking_adjustment #(
parameter rst_delay_msb = 15,
parameter rst_delay_cyc = 'd17600,
parameter h_active = 'd1920,
parameter h_total = 'd2200,
parameter v_active = 'd1080,
parameter v_total = 'd1125,
parameter H_FRONT_PORCH = 'd88,
parameter H_SYNCH = 'd44,
parameter H_BACK_PORCH = 'd148,
parameter V_FRONT_PORCH = 'd4,
parameter V_SYNCH = 'd5
) (
input rstn,
input clk,
output reg fv,
output reg lv
);
reg [ 11:0] pixcnt;
reg [ 11:0] linecnt;
reg [ 11:0] fv_cnt;
reg q_fv;
reg [rst_delay_msb:0] rstn_cnt;
always @(posedge clk or negedge rstn)
if (!rstn) rstn_cnt <= 0;
else rstn_cnt <= rstn_cnt[rst_delay_msb] ? rstn_cnt : rstn_cnt + 1;
wire reset_n;
assign reset_n = rstn_cnt[rst_delay_msb];
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
fv_cnt <= 0;
pixcnt <= 12'd0;
linecnt <= 12'd0;
lv <= 1'b0;
fv <= 1'b0;
q_fv <= 0;
end else begin
fv_cnt <= (fv_cnt == 11'h7FF) ? 11'h7FF : fv_cnt + (~fv & q_fv);
pixcnt <= (pixcnt < h_total - 1) ? pixcnt + 1 : 0;
linecnt <= (linecnt==v_total-1 && pixcnt ==h_total-1) ? 0 :
(linecnt< v_total-1 && pixcnt ==h_total-1) ? linecnt+1 : linecnt;
lv <= (pixcnt > 12'd0) & (pixcnt <= h_active) & (linecnt > 0 & linecnt <= v_active);
fv <= (linecnt >= 12'd0) & (linecnt <= v_active + 1);
q_fv <= fv;
end
end
endmodule
| 8.2179 |
module BlankSyncGen #(
// Width of counters
parameter COUNTER_WIDTH = 12,
// Horizontal timing parameters
parameter HSYNC_ON = 2007, //Active + Front
parameter HSYNC_OFF = 2051, //Active + Front + SyncWidth
parameter HBLANK_ON = 1919, //Active Pixels in the line
parameter HBLANK_OFF = 2199, //Total Pixels
// Vertical timing parameters
parameter VSYNC_ON = 1083, //Active + Front
parameter VSYNC_OFF = 1088, //Active + Front + SyncWidth
parameter VBLANK_ON = 1079, //Active Lines in the frame
parameter VBLANK_OFF = 1124 //Total lines
) (
input wire clk,
reset,
enable,
output reg [COUNTER_WIDTH-1:0] hcount,
vcount,
output reg hsync,
vsync,
hblank,
vblank
);
wire hsync_on, hsync_off, hblank_on, hblank_off, vsync_on, vsync_off, vblank_on, vblank_off;
// Determines when to turn on sync and blank signals
assign hsync_on = (hcount == HSYNC_ON);
assign hsync_off = (hcount == HSYNC_OFF);
assign hblank_on = (hcount == HBLANK_ON);
assign hblank_off = (hcount == HBLANK_OFF);
assign vsync_on = (vcount == VSYNC_ON);
assign vsync_off = (vcount == VSYNC_OFF);
assign vblank_on = (vcount == VBLANK_ON);
assign vblank_off = (vcount == VBLANK_OFF);
// Horizontal counter
always @(posedge clk or negedge reset) begin
if (reset) hcount <= {COUNTER_WIDTH{1'b0}};
else if (enable == 1'b1 && hcount <= HBLANK_OFF - 1) hcount <= hcount + 1;
else hcount <= {COUNTER_WIDTH{1'b0}};
end
// Horizontal Sync
always @(posedge clk or negedge reset) begin
if (reset) hsync <= 1'b0;
else if (enable == 1'b1 && hsync_on) hsync <= 1'b1;
else if (enable == 1'b1 && hsync_off) hsync <= 1'b0;
else hsync <= hsync;
end
// Horizontal Blank
always @(posedge clk or negedge reset) begin
if (reset) hblank <= 1'b0;
else if (enable == 1'b1 && hblank_on) hblank <= 1'b1;
else if (enable == 1'b1 && hblank_off) hblank <= 1'b0;
else hblank <= hblank;
end
// Vertical counter
always @(posedge clk or negedge reset) begin
if (reset) vcount = {COUNTER_WIDTH{1'b0}};
else if (enable == 1'b1 && hsync_on) begin
if (vcount <= VBLANK_OFF - 1) vcount <= vcount + 1;
else vcount <= {COUNTER_WIDTH{1'b0}};
end else vcount <= vcount;
end
// Vertical Sync
always @(posedge clk or negedge reset) begin
if (reset) vsync = 1'b0;
else if (enable == 1'b1 && vsync_on) vsync <= 1'b1;
else if (enable == 1'b1 && vsync_off) vsync <= 1'b0;
else vsync = vsync;
end
// Vertical Blank
always @(posedge clk or negedge reset) begin
if (reset) vblank <= 1'b0;
else if (enable == 1'b1 && vblank_on) vblank <= 1'b1;
else if (enable == 1'b1 && vblank_off) vblank <= 1'b0;
else vblank <= vblank;
end
endmodule
| 8.181388 |
module blank_cell_rom (
//input
clk,
addr,
//output
data
);
input wire clk;
input [12:0] addr;
output reg [7:0] data;
always @(posedge clk) begin
data <= 8'b00000000;
end
endmodule
| 6.595879 |
module blank_rom (
input wire clk,
input wire [0:0] row,
input wire [0:0] col,
output reg [11:0] color_data
);
(* rom_style = "block" *)
//signal declaration
reg [0:0] row_reg;
reg [0:0] col_reg;
always @(posedge clk) begin
row_reg <= row;
col_reg <= col;
end
always @*
case ({
row_reg, col_reg
})
2'b00: color_data = 12'b111111111111;
2'b01: color_data = 12'b111111111111;
2'b010: color_data = 12'b111111111111;
2'b10: color_data = 12'b111111111111;
2'b11: color_data = 12'b111111111111;
2'b110: color_data = 12'b111111111111;
2'b100: color_data = 12'b111111111111;
2'b101: color_data = 12'b111111111111;
2'b1010: color_data = 12'b111111111111;
default: color_data = 12'b000000000000;
endcase
endmodule
| 7.873982 |
module Blastoise (
input [7:0] in, //Entrada del dato de los 8 bits.Se introduce mediante los switches
input send, //push button G12 enva la cadena o trama
input clk, //reloj interno de la basys
input Rx, //Entrada del receptor
input reset, //a la mera no se necesita reset :o
output Tx, //Salida del transmisor
output [6:0] segments, //segmentos de la basys
output [3:0] trans
);
wire bauds; //Clock de velocidad de la UART
wire bandera;
wire [1:0] sel; //Para el multiplexor
wire [7:0] RxData; //Cable con la data recibida que va al decodificador
wire [6:0] msg, Yo, El; //Decodificado del mensaje, id tuyo, y el id del que envio
wire [7:0] TxData; //Aqui se guarda lo que se va atransmitir
clkredu baudGen (
.clk(clk),
.salida(bauds)
); //Da el clk para trabajar a los 9600 bauds
//Proceso de recibir
Recibir Recibir (
.outclk(bauds),
.EntradaTx(Rx),
.SalidaRx(RxData),
.reset(reset)
); //.received(received)); //quiza agregarele el reset al estado 0 vaquero
Flag Bandereador (
.clk(bauds),
.Rx(RxData[5:4]),
.identidad(in[7:6]),
.bandera(bandera),
.reset(reset)
); //Compara
//Proceso de Enviar
Mux2 EsMiador (
.switch(in),
.RX(RxData),
.sel(bandera),
.salida(TxData)
); //Enva el dato correcto al transmisor
Trans Transmitir (
.clk(bauds),
.reset(reset),
.transmitir(send),
.bandera(bandera),
.entradaSw(TxData),
.salidaTx(Tx)
);
decoder decoderBH (
.in(RxData),
.msg(msg),
.Yo(Yo),
.El(El),
.bandera(bandera)
); // Este modulo decodifica el mensaje
gtv gtv (
.clk(clk),
.sel(sel)
);
mux mux1 (
.a(msg),
.b(7'b0000001),
.c(El),
.d(Yo),
.sel(sel),
.salida(segments),
.trans(trans)
);
endmodule
| 8.068938 |
module blastT (
input clk,
input [31:0] data,
input [31:0] address, //How many bits should it be?
input dataValid,
output [511:0] querry,
output reg querryValid
);
reg [511:0] querryReg;
assign querry = querryReg;
always @(posedge clk) begin
if (dataValid & address == 64) querryValid <= 1'b1;
else querryValid <= 1'b0;
end
always @(posedge clk) begin
if (dataValid) begin
case (address)
0: begin
querryReg[31:0] <= data;
end
4: begin
querryReg[63:32] <= data;
end
8: begin
querryReg[95:64] <= data;
end
12: begin
querryReg[127:96] <= data;
end
16: begin
querryReg[159:128] <= data;
end
20: begin
querryReg[191:160] <= data;
end
24: begin
querryReg[223:192] <= data;
end
28: begin
querryReg[255:224] <= data;
end
32: begin
querryReg[287:256] <= data;
end
36: begin
querryReg[319:288] <= data;
end
40: begin
querryReg[351:320] <= data;
end
44: begin
querryReg[383:352] <= data;
end
48: begin
querryReg[415:384] <= data;
end
52: begin
querryReg[447:416] <= data;
end
56: begin
querryReg[479:448] <= data;
end
60: begin
querryReg[512:480] <= data;
end
endcase
end
end
endmodule
| 6.643528 |
module BLC (
input wire [15:0] o,
input wire [15:0] x,
output wire [18:0] log
//output wire [14:0] f /* fraction */
);
reg [ 3:0] k;
reg [15:0] y;
assign log = {k, y[14:0]};
always @(*) begin
case (o)
/*1.*/
16'b1000_0000_0000_0000: begin
k = 4'b1111;
y = x;
end
16'b0100_0000_0000_0000: begin
k = 4'b1110;
y = x << 1;
end
16'b0010_0000_0000_0000: begin
k = 4'b1101;
y = x << 2;
end
16'b0001_0000_0000_0000: begin
k = 4'b1100;
y = x << 3;
end
/*2.*/
16'b0000_1000_0000_0000: begin
k = 4'b1011;
y = x << 4;
end
16'b0000_0100_0000_0000: begin
k = 4'b1010;
y = x << 5;
end
16'b0000_0010_0000_0000: begin
k = 4'b1001;
y = x << 6;
end
16'b0000_0001_0000_0000: begin
k = 4'b1000;
y = x << 7;
end
/*3.*/
16'b0000_0000_1000_0000: begin
k = 4'b0111;
y = x << 8;
end
16'b0000_0000_0100_0000: begin
k = 4'b0110;
y = x << 9;
end
16'b0000_0000_0010_0000: begin
k = 4'b0101;
y = x << 10;
end
16'b0000_0000_0001_0000: begin
k = 4'b0100;
y = x << 11;
end
/*4.*/
16'b0000_0000_0000_1000: begin
k = 4'b0011;
y = x << 12;
end
16'b0000_0000_0000_0100: begin
k = 4'b0010;
y = x << 13;
end
16'b0000_0000_0000_0010: begin
k = 4'b0001;
y = x << 14;
end
16'b0000_0000_0000_0001: begin
k = 4'b0000;
y = 16'b0;
end
default: begin
k = 4'b0000;
y = 16'b0;
end
endcase
end
endmodule
| 6.641326 |
module bldc_FSM (
output wire [5:0] output_pins,
input fsm_clk,
pwm_input
);
//STATES
parameter AH_BL = 3'b000;
parameter AH_CL = 3'b001;
parameter BH_CL = 3'b010;
parameter BH_AL = 3'b011;
parameter CH_AL = 3'b100;
parameter CH_BL = 3'b101;
//OUTPUTS
//Since module is not TLE, we need our outputs to be wires
reg pin_11 = 1'b0;
reg pin_10 = 1'b0;
reg pin_09 = 1'b0;
reg pin_5 = 1'b0;
reg pin_4 = 1'b0;
reg pin_3 = 1'b0;
//STATE VARIABLES
reg [2:0] currentState;
reg [2:0] nextState;
//NET INSTANTIATIONS
//Assign wire outputs to internal net regs
//Only do this if you have you have combinational regs, yet output has to be wire
assign output_pins[5] = pin_11;
assign output_pins[4] = pin_10;
assign output_pins[3] = pin_09;
assign output_pins[2] = pin_5;
assign output_pins[1] = pin_4;
assign output_pins[0] = pin_3;
//STATE MEMORY BLOCK
always @(posedge (fsm_clk)) begin : stateMemory
currentState <= nextState;
end
//NEXT STATE LOGIC BLOCK
always @(currentState) begin : nextStateLogic
case (currentState)
AH_BL: begin
nextState = AH_CL;
end
AH_CL: begin
nextState = BH_CL;
end
BH_CL: begin
nextState = BH_AL;
end
BH_AL: begin
nextState = CH_AL;
end
CH_AL: begin
nextState = CH_BL;
end
CH_BL: begin
nextState = AH_BL;
end
default: begin
nextState = AH_CL;
end
endcase
end
//OUTPUT LOGIC
always @(currentState) begin : outputLogic
case (currentState)
AH_BL: begin
pin_11 = pwm_input; //PWM
pin_10 = 1'b1; //HIGH
pin_09 = 1'b0;
pin_5 = 1'b1; //HIGH
pin_4 = 1'b0;
pin_3 = 1'b0;
end
AH_CL: begin
pin_11 = pwm_input; //PWM
pin_10 = 1'b0;
pin_09 = 1'b1; //HIGH
pin_5 = 1'b1; //HIGH
pin_4 = 1'b0;
pin_3 = 1'b0;
end
BH_CL: begin
pin_11 = 1'b0;
pin_10 = pwm_input; //PWM
pin_09 = 1'b1; //HIGH
pin_5 = 1'b0;
pin_4 = 1'b1; //HIGH
pin_3 = 1'b0;
end
BH_AL: begin
pin_11 = 1'b1; //HIGH
pin_10 = pwm_input; //PWM
pin_09 = 1'b0;
pin_5 = 1'b0;
pin_4 = 1'b1; //HIGH
pin_3 = 1'b0;
end
CH_AL: begin
pin_11 = 1'b1; //HIGH
pin_10 = 1'b0;
pin_09 = pwm_input; //PWM
pin_5 = 1'b0;
pin_4 = 1'b0;
pin_3 = 1'b1; //HIGH
end
CH_BL: begin
pin_11 = 1'b0;
pin_10 = 1'b1; //HIGH
pin_09 = pwm_input; //PWM
pin_5 = 1'b0;
pin_4 = 1'b0;
pin_3 = 1'b1; //HIGH
end
default: begin
pin_11 = pwm_input; //PWM
pin_10 = 1'b1; //HIGH
pin_09 = 1'b0;
pin_5 = 1'b1; //HIGH
pin_4 = 1'b0;
pin_3 = 1'b0;
end
endcase
end
endmodule
| 7.258622 |
module bldc_hall (
clk,
rst_n,
//--------------------------------------
//Hall sensor inputs
hall_data_i,
//--------------------------------------
//Hall sensor output
hall_data_o,
hall_change_o
);
//-----------------------------------------------------------------------------
//Parameter
//-----------------------------------------------------------------------------
//Port
input clk;
input rst_n;
//--------------------------------------
//Hall sensor inputs
input [2:0] hall_data_i;
//--------------------------------------
//Hall sensor output
output [2:0] hall_data_o;
output hall_change_o;
//-----------------------------------------------------------------------------
//Internal variable
reg [2:0] hall_data_o;
reg [2:0] hall_data_1;
reg [2:0] hall_data_2;
reg [2:0] hall_data_3;
wire [2:0] nxt_hall_data;
wire latch_data_en;
reg latch_data_en_1;
reg latch_data_en_2;
//-----------------------------------------------------------------------------
//Pipeline input data
always @(posedge clk or negedge rst_n) begin
if (!rst_n) hall_data_1 <= 3'd0;
else hall_data_1 <= hall_data_i;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) hall_data_2 <= 3'd0;
else hall_data_2 <= hall_data_1;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) hall_data_3 <= 3'd0;
else hall_data_3 <= hall_data_2;
end
//-----------------------------------------------------------------------------
//Capturing new data when it is stable
assign latch_data_en = (hall_data_3 == hall_data_1) & (|hall_data_3);
assign nxt_hall_data = latch_data_en ? hall_data_3 : hall_data_o;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) hall_data_o <= 3'd0;
else hall_data_o <= nxt_hall_data;
end
//-----------------------------------------------------------------------------
//Generating interrupt status pulse when hall sensor value change to new value.
always @(posedge clk or negedge rst_n) begin
if (!rst_n) latch_data_en_1 <= 1'd0;
else latch_data_en_1 <= latch_data_en;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) latch_data_en_2 <= 1'd0;
else latch_data_en_2 <= latch_data_en_1;
end
assign hall_change_o = (~latch_data_en_2) & latch_data_en_1;
endmodule
| 7.306484 |
module bldc_wb_slave (
clk,
rst_n,
//---------------------------------
//Wishbone interface
sel_i,
dat_i,
addr_i,
cyc_i,
we_i,
stb_i,
ack_o,
dat_o,
//---------------------------------
//BLDC register interface
reg_wdata_o,
reg_wen_o,
reg_ren_o,
reg_addr_o,
reg_rdata_i
);
////////////////////////////////////////////////////////////////////////////////
//parameter
parameter WB_AW = 6'd32;
parameter WB_DW = 6'd32;
parameter REG_AW = 6'd32;
parameter REG_DW = 6'd32;
parameter IDLE = 2'd0;
parameter READ = 2'd1;
parameter WRITE = 2'd2;
////////////////////////////////////////////////////////////////////////////////
// Port declarations
input clk;
input rst_n;
//---------------------------------
//Wishbone interface
input [3:0] sel_i;
input [WB_DW-1:0] dat_i;
input [WB_AW-1:0] addr_i;
input cyc_i;
input we_i;
input stb_i;
output ack_o;
output [WB_DW-1:0] dat_o;
//---------------------------------
//BLDC register interface
output [REG_DW-1:0] reg_wdata_o;
output reg_wen_o;
output reg_ren_o;
output [REG_AW-1:0] reg_addr_o;
input [REG_DW-1:0] reg_rdata_i;
////////////////////////////////////////////////////////////////////////////////
//internal signal
reg [ WB_DW-1:0] reg_wdata_o;
wire idle_to_write;
wire idle_to_read;
reg [REG_AW-1:0] addr_1;
wire st_idle;
wire st_write;
wire st_read;
reg [ 1:0] nxt_state;
reg [ 1:0] state;
//------------------------------------------------------------------------------
// AHB next state logic
assign idle_to_write = we_i & stb_i & cyc_i & st_idle;
assign idle_to_read = (~we_i) & stb_i & cyc_i & st_idle;
always @(*) begin
case (state)
IDLE: begin
nxt_state = idle_to_write ? WRITE : idle_to_read ? READ : IDLE;
end
WRITE: begin
nxt_state = IDLE;
end
READ: begin
nxt_state = IDLE;
end
default: begin
nxt_state = IDLE;
end
endcase
end
//------------------------------------------------------------------------------
// FF
always @(posedge clk or negedge rst_n) begin
if (!rst_n) state <= IDLE;
else state <= nxt_state;
end
assign st_idle = (state == IDLE);
assign st_write = (state == WRITE);
assign st_read = (state == READ);
//------------------------------------------------------------------------------
//wdata
always @(posedge clk or negedge rst_n) begin
if (!rst_n) reg_wdata_o <= {WB_DW{1'b0}};
else reg_wdata_o <= dat_i;
end
//------------------------------------------------------------------------------
//address
always @(posedge clk or negedge rst_n) begin
if (!rst_n) addr_1 <= {REG_AW{1'b0}};
else addr_1 <= addr_i[REG_AW-1:0];
end
assign reg_addr_o = idle_to_read ? addr_i[REG_AW-1:0] : addr_1;
//------------------------------------------------------------------------------
//Write control
assign reg_wen_o = st_write;
//------------------------------------------------------------------------------
//read control
assign reg_ren_o = idle_to_read;
//------------------------------------------------------------------------------
//ACK control
assign ack_o = (st_write | st_read) & stb_i;
//------------------------------------------------------------------------------
//Data out
assign dat_o = reg_rdata_i;
endmodule
| 8.346954 |
module ble_tx_clarity
//
module ble_tx_clarity (pll_64M_CLKI, pll_64M_CLKI2, pll_64M_CLKOP, pll_64M_LOCK,
pll_64M_RST, pll_64M_SEL) /* synthesis sbp_module=true */ ;
input pll_64M_CLKI;
input pll_64M_CLKI2;
output pll_64M_CLKOP;
output pll_64M_LOCK;
input pll_64M_RST;
input pll_64M_SEL;
pll_64M pll_64M_inst (.CLKI(pll_64M_CLKI), .CLKI2(pll_64M_CLKI2), .CLKOP(pll_64M_CLKOP),
.LOCK(pll_64M_LOCK), .RST(pll_64M_RST), .SEL(pll_64M_SEL));
endmodule
| 6.742567 |
module exu (
input clk,
input rst,
input [31:0] exu_i_pc,
input [31:0] exu_i_rs1_data,
input [31:0] exu_i_rs2_data,
input [31:0] exu_i_imm,
input [1:0] exu_i_a_sel,
input [1:0] exu_i_b_sel,
input [10:0] exu_i_alu_sel,
input [3:0] exu_i_br_sel,
output [31:0] exu_o_exu_data,
output [31:0] exu_o_rs2_data,
output exu_o_branch_taken
);
wire [31:0] alu_a, alu_b;
wire br_un, br_eq, br_lt;
// because we are using single stage, we just need to pass the data through
assign exu_o_rs2_data = exu_i_rs2_data;
// alu input selection
assign alu_a = ({32{exu_i_a_sel[0]}} & exu_i_rs1_data) | ({32{exu_i_a_sel[1]}} & exu_i_pc);
assign alu_b = ({32{exu_i_b_sel[0]}} & exu_i_rs2_data) | ({32{exu_i_b_sel[1]}} & exu_i_imm);
// branch unit input selection and output calculation
assign br_un = exu_i_br_sel[2];
assign exu_o_branch_taken = (exu_i_br_sel[0] & ((exu_i_br_sel[3] ? br_lt : br_eq) ^ exu_i_br_sel[1]));
alu u_alu (
.alu_i_a (alu_a),
.alu_i_b (alu_b),
.alu_i_sel(exu_i_alu_sel),
.alu_o_out(exu_o_exu_data)
);
bru u_bru (
.bru_i_a(exu_i_rs1_data),
.bru_i_b(exu_i_rs2_data),
.bru_i_br_un(br_un),
.bru_o_br_eq(br_eq),
.bru_o_br_lt(br_lt)
);
endmodule
| 8.840183 |
module bru (
input [31:0] bru_i_a,
input [31:0] bru_i_b,
input bru_i_br_un,
output bru_o_br_eq,
output bru_o_br_lt
);
wire signed [31:0] a_signed, b_signed;
assign a_signed = bru_i_a;
assign b_signed = bru_i_b;
assign bru_o_br_eq = (bru_i_a === bru_i_b);
assign bru_o_br_lt = bru_i_br_un ? (bru_i_a < bru_i_b) : (a_signed < b_signed);
endmodule
| 6.901967 |
module regfile (
input clk,
input [ 4:0] regfile_i_rd_addr,
input regfile_i_w_en,
input [31:0] regfile_i_rd_data,
input [ 4:0] regfile_i_rs1_addr,
output [31:0] regfile_o_rs1_data,
input [ 4:0] regfile_i_rs2_addr,
output [31:0] regfile_o_rs2_data
);
(* ram_style = "distributed" *) reg [31:0] mem[31-1:0];
always @(posedge clk) begin
if (regfile_i_w_en && (regfile_i_rd_addr !== 'h0)) begin
mem[regfile_i_rd_addr-1] <= regfile_i_rd_data;
end
end
assign regfile_o_rs1_data = regfile_i_rs1_addr !== 'h0 ? mem[regfile_i_rs1_addr-1] : 'h0;
assign regfile_o_rs2_data = regfile_i_rs2_addr !== 'h0 ? mem[regfile_i_rs2_addr-1] : 'h0;
endmodule
| 7.809308 |
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