code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bit_searcher_16 (
input wire [15:0] bits,
input wire target,
input wire direction,
output wire hit,
output wire [3:0] index
);
wire [3:0] hit_inner;
wire [1:0] index_inner [3:0];
wire [1:0] index_upper;
bit_searcher_4
BS0 (
.bits(bits[3:0]),
.target(target)... | 8.72533 |
module bit_searcher_64 (
input wire [63:0] bits,
input wire target,
input wire direction,
output wire hit,
output wire [5:0] index
);
wire [3:0] hit_inner;
wire [3:0] index_inner [3:0];
wire [1:0] index_upper;
bit_searcher_16
BS0 (
.bits(bits[15:0]),
.target(targe... | 8.72533 |
module bit_searcher_256 (
input wire [255:0] bits,
input wire target,
input wire direction,
output wire hit,
output wire [7:0] index
);
wire [3:0] hit_inner;
wire [5:0] index_inner [3:0];
wire [1:0] index_upper;
bit_searcher_64
BS0 (
.bits(bits[63:0]),
.target(tar... | 8.72533 |
module bit_searcher_32 (
input wire [31:0] bits,
input wire target,
input wire direction,
output wire hit,
output wire [4:0] index
);
wire [1:0] hit_inner;
wire [3:0] index_inner[3:0];
wire index_upper;
bit_searcher_16
BS0 (
.bits(bits[15:0]),
.target(target),
... | 8.72533 |
module bit_searcher (
input wire [N-1:0] bits, // data being searched
input wire target, // search target
input wire direction, // search direction, 0 for lower to upper and 1 otherwise
output wire hit, // target found flag
output wire [W-1:0] index // index of target in data
);
`include "fu... | 8.458105 |
module bit_serial_adder (
input clk,
input reset,
input load,
input [7:0] a,
input [7:0] b,
input cin,
output wire [7:0] sum,
output wire cout
);
/*
clk: Clock
reset: Reset bit of the module (indicates to reset the adder)
load: Load bit of the module (indicates when to load d... | 7.9223 |
module
module bit_serial_adder_tb;
// Initialising inputs and outputs
reg clk;
reg reset;
reg load;
reg sipo_load;
reg [7:0] a;
reg [7:0] b;
reg cin;
wire [7:0] sum;
wire cout;
// Instantiate the Unit Under Test (UUT)
bit_serial_adder UUT(.clk(clk), .reset(reset), .load(load), .a(a), .b(b), .cin(cin), .... | 6.892285 |
module bit_shift #(
//==============================
// Module parameters
//==============================
parameter DATA_WIDTH = 8, // number of input bits
parameter SHIFT_DIRECTION = 1, // 1 = shift right, 0 = shift left
parameter NUMBER_BITS = 1, /... | 8.512014 |
module bit_shifter_rotator (
ctrl,
in,
out
);
input [2:0] ctrl;
input [7:0] in;
output reg [7:0] out;
always @(*) begin
//assign tmp = in;
case (ctrl)
3'b000: out <= in;
3'b001: out <= in << 1;
3'b010: out <= in << 2;
3'b011: out <= in << 3;
3'b100: out <= in ... | 6.876592 |
module bit_shift_controller #(
parameter START_BITS = 8'b00010000
) (
input [23:0] buttons,
output [ 7:0] bits
);
reg [7:0] r_bits = START_BITS;
assign bits = r_bits;
always @(buttons) begin
r_bits =
(buttons[0] == 1 && r_bits[0] != 1) ? r_bits << 1 :
(buttons[1] == 1 && r_bits[7] != 1) ? ... | 8.374731 |
module bit_shift_controller_tb;
// UUT Inputs
reg [23:0] buttons = 0;
// UUT outputs
output [7:0] bits;
// Instantiate the Unit Under Test (UUT)
bit_shift_controller #(
.START_BITS(8'b00011000)
) uut (
.buttons(buttons)
);
// UUT test simulation
integer i;
integer ii;
initial begin
// Configure fi... | 8.374731 |
module //
// Date: Nov 2011 //
// Developer: Wesley New //
// Licence: GNU General Public License ver 3 //
// Notes: This only tests the basi... | 8.238592 |
module bit_shift_test (
input wire i_clk,
output wire [7:0] o_data
);
reg [ 3:0] r_counter = 0;
reg [15:0] r_data;
always @(posedge i_clk) begin
r_counter <= r_counter + 1;
r_data <= (1 << r_counter);
end
assign o_data = r_data[7:0];
endmodule
| 6.98187 |
module bit_slice (
Cout,
A,
B,
Z,
B_0,
Cin,
add_en,
add_en_n,
clk,
ppgen_en,
ppgen_en_n,
rd_enA,
rd_enA_n,
rd_enB,
rd_enB_n,
wr_en
);
output Cout;
inout A, B, Z;
input B_0, Cin, add_en, add_en_n, clk, ppgen_en, ppgen_en_n;
input [4:0] rd_enB;
... | 7.404372 |
module bit_slip_v (
input clk,
input rstn,
input byte_gate,
input [7:0] curr_byte,
input [7:0] last_byte,
input frame_start,
output reg found_sot,
output reg [2:0] data_offs,
output reg [7:0] actual_byte
);
reg found_hdr;... | 7.046357 |
module bit_stream (
input clk,
EA,
input [10:0] count_h,
count_v,
output red,
green,
blue
);
reg r = 0;
reg g = 0;
reg b = 0;
assign red = r;
assign green = g;
assign blue = b;
always @(posedge clk) begin
if (EA) begin
if (count_h < 128)
// красный
begin
... | 6.777608 |
module
// DEPARTMENT: communication and electronics department
// AUTHOR: Mina Hanna
// AUTHOR EMAIL: mina.hannaone@gmail.com
//------------------------------------------------
// Release history
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 19/7/2022 Mina Hanna final version
//---------------------------------------------... | 8.923686 |
module BIT_SYNC_tb ();
parameter NUM_STAGES_tb = 2;
parameter BUS_WIDTH_tb = 4;
/********************************************************************************/
/*******************************Internal Signals*********************************/
reg [BUS_WIDTH_tb-1:0] ASYNCH_tb;
reg ... | 7.201462 |
module Bit_tb ();
integer file;
reg clk = 1;
wire out;
reg load = 0;
reg in = 0;
reg [9:0] t = 10'b0;
Bit BIT (
.clk (clk),
.load(load),
.in (in),
.out (out)
);
always #1 clk = ~clk;
task display;
#1 $fwrite(file, "|%4d|%1b|%1b|%1b|\n", t, in, load, out);
endtask
... | 7.042786 |
module bit_timing(
input rx,
input rst,
input clk,
output sampled_rx,
output baud_clk
);
if(posedge reset
endmodule
| 7.399181 |
module bit_to_bus_4 (
input bit_3,
input bit_2,
input bit_1,
input bit_0,
output [3:0] bus_out
);
assign bus_out = {bit_3, bit_2, bit_1, bit_0};
endmodule
| 7.689119 |
module bit_vec_stat #(
parameter integer bit_width = 64,
parameter integer vec_width_index = 4,
parameter integer vec_width_value = 32,
parameter integer vec_num = 16,
parameter integer vec_width_total = (vec_width_index + vec_width_value) * vec_num
) (
input wire rst,
input wire cl... | 8.424288 |
module BIU (
input [2:0] NUM,
input [7:0] RX,
input [7:0] RY,
input [1:0] SEL_BIU,
input reset,
input clk,
output reg [7:0] o_Address_Data_Bus,
output reg [7:0] o_DataOut_Bus,
output reg W_R
);
always @(posedge clk, posedge reset) begin
if (reset) begin
o_DataOut_Bus <... | 6.836573 |
module biu8 (
//对外部总线的信号
inout [7:0] p,
//对内部总线的信号
input [7:0] data_o,
input wr_n,
input rd_n,
input en,
output [7:0] data_i,
//控制寄存器选择信号
input sel
);
reg [7:0] data;
reg [7:0] data_p;
assign p = sel ? 8'bz : data_p; //sel=1: high z or input , sel=0 output 1/0
... | 7.355211 |
module biu_ctl (
icu_req,
icu_type,
icu_size,
biu_icu_ack,
dcu_req,
dcu_type,
dcu_size,
biu_dcu_ack,
clk,
reset_l,
pj_tv,
pj_type,
pj_size,
pj_ack,
sm,
sin,
so,
arb_select,
pj_ale
);
input icu_req;
input [3:0] icu_type;
input [1:0] icu_... | 8.52045 |
module biu_dpath (
icu_addr,
dcu_addr,
dcu_dataout,
biu_data,
pj_addr,
pj_data_in,
pj_data_out,
arb_select
);
input [31:0] icu_addr;
input [31:0] dcu_addr;
input [31:0] dcu_dataout;
output [31:0] biu_data;
output [31:0] pj_addr;
input [31:0] pj_data_in;
output [31:0] pj_da... | 8.537689 |
module bi_buffer #(
parameter D_WL = 24,
parameter UNITS_NUM = 5
) (
input [7:0] addr,
output [UNITS_NUM*D_WL-1:0] w_o
);
wire [D_WL*UNITS_NUM-1:0] w_fix[0:5];
assign w_o = w_fix[addr];
assign w_fix[0] = 'h00024bffb2f4fff286000975ffc6ae;
assign w_fix[1] = 'hffe4d1fff192ffe85affe555001608;
ass... | 6.65284 |
module bi_chang (
is_wall,
out_is_wall
);
input is_wall;
output out_is_wall;
//when close to the wall, is_wall=0
//https://www.playrobot.com/infrared/1039-infrared-sensor.html
assign out_is_wall = (!is_wall) ? 1 : 0;
//assign led = 1;
endmodule
| 6.851805 |
module bi_direc (
i_clk,
rst_n,
CNT,
a_in,
o_TEMPout,
ld
);
parameter DATA_WIDTH2 = 8;
input i_clk;
//input [DATA_WIDTH2-1:0] d_in ;
input rst_n;
input a_in; ///used as serial in //
input ld; ///for loading the data///
input CNT ; ///used for changing the dircetion of shift... | 8.042317 |
module bi_direct_bus (
pindata,
Data_in,
Data_out,
OE
);
parameter n_buff = 4;
input OE;
inout [n_buff-1:0] pindata;
input [n_buff-1:0] Data_in;
output [n_buff-1:0] Data_out;
assign Data_in = pindata;
assign pindata = (OE == 1) ? Data_out : (OE == 0) ? 'z : 'x;
endmodule
| 7.05196 |
module
module bjt(input globalclock, //fpgaclock, 50MHz
input rst, //overall reset
output tx_spi_sclk, //output spi clock for AD5664
output tx_spi_sync, //output spi synchronize signal for AD5664 spi registers
output tx_spi_din, //output spi data signal for AD5664 spi registers
output ... | 6.708858 |
module bj_detect (
BRANCH_JUMP,
DATA1,
DATA2,
PC_SEL_OUT
);
input [2:0] BRANCH_JUMP;
output PC_SEL_OUT;
input [31:0] DATA1, DATA2;
wire eq, unsign_lt, sign_lt, PC_SEL;
reg lt;
wire out1, out2, out3, out4, out5;
assign #2 PC_SEL_OUT = PC_SEL;
assign eq = DATA1 == DATA2 ? 1 : 0;
assig... | 8.110429 |
module BK_0011M (
XT5_in_pin,
XT5_out_pin,
nSEL2,
DOUT,
nWRTBT,
STROBE,
END
);
// контакты разъёма XT5 (вход/выход УП)
input [15:0] XT5_in_pin;
output [15:0] XT5_out_pin;
output nSEL2, STROBE, nWRTBT, DOUT, END;
parameter cycle = 250; // период тактовой частоты, нс
reg clk; /... | 6.506026 |
module bk321 (
input [15:0] A,
input [15:0] B,
input cin,
output [15:0] sum,
output cout
);
wire [15:0] sum0;
bk32 minus (
.A (~B),
.B (1),
.cin(0),
.sum(sum0)
);
bk32 minus1 (
.A (sum0),
.B (A),
.cin(0),
.sum(sum)
);
endmodule
| 6.901768 |
module stage0 (
P,
G,
a,
b
);
input [7:0] a, b;
output [7:0] P, G;
assign P[0] = a[0] ^ b[0],
P[1] = a[1] ^ b[1],
P[2] = a[2] ^ b[2],
P[3] = a[3] ^ b[3],
P[4] = a[4] ^ b[4],
P[5] = a[5] ^ b[5],
P[6] = a[6] ^ b[6],
P[7] = a[7] ^ b[7],
G[0] = a[0] & b[... | 6.706914 |
module tbBK;
wire [7:0] s;
wire cout;
reg [7:0] a, b;
reg cin;
BKadd8 BK (
a,
b,
cin,
s,
cout
);
initial begin
a <= 8'b10100011;
b <= 8'b10101111;
cin <= 1'b0;
#20 $finish;
end
endmodule
| 6.826173 |
module BK_16b_tb ();
wire [16:0] out0;
reg [15:0] in0;
reg [15:0] in1;
integer i, file, mem, temp;
BK_16b U0 (
in0,
in1,
out0
);
initial begin
$display("-- Begining Simulation --");
$dumpfile("./BK_16b.vcd");
$dumpvars(0, BK_16b_tb);
file = $fopen("output.txt", "w"... | 6.825766 |
module blabla_qr (
input wire [63 : 0] a,
input wire [63 : 0] b,
input wire [63 : 0] c,
input wire [63 : 0] d,
output wire [63 : 0] a_prim,
output wire [63 : 0] b_prim,
output wire [63 : 0] c_prim,
output wire [63 : 0] d_prim
);
//-----------------------------------------------------... | 7.435374 |
module to allow
// us to build versions of the cipher with 1, 2, 4 and even 8
// parallel qr functions.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2017 Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the... | 7.487454 |
module black (
input G_i,
P_i,
G_k,
P_k,
output G_j,
P_j
);
and (P_j, P_i, P_k);
wire tr;
and (tr, P_i, G_k);
or (G_j, G_i, tr);
endmodule
| 6.62003 |
module BlackBlock (
G_i_k,
P_i_k,
G_km1_j,
P_km1_j,
G_i_j,
P_i_j
);
input G_i_k;
input P_i_k;
input G_km1_j;
input P_km1_j;
output G_i_j;
output P_i_j;
assign G_i_j = G_i_k | (P_i_k & G_km1_j);
assign P_i_j = P_i_k & P_km1_j;
endmodule
| 6.986558 |
module x64 #(
parameter N = 64, // N logical LUTs
parameter M = 4, // M contexts
parameter B = 4, // subcluster branching factor
parameter B_SUB = 4, // sub-subcluster branching factor
parameter K = 4, // K-inp... | 8.223463 |
module BlackBoxAdder (
input [32:0] in1,
input [32:0] in2,
output [33:0] out
);
always @* begin
out <= ((in1) + (in2));
end
endmodule
| 7.24337 |
module is added as a reference only. Please add library
// cells for delay buffers and muxes from the foundry that is fabricating your SoC.
module BlackBoxDelayBuffer ( in, mux_out, out, sel
);
input in;
output mux_out;
output out;
input [4:0] sel;
assign mux_out = in;
assign out = in;
endmodule
| 6.820226 |
module BlackBoxInverter (
input [0:0] in,
output [0:0] out
);
assign out = !in;
endmodule
| 8.613857 |
module BlackBoxPassthrough (
input [0:0] in,
output [0:0] out
);
assign out = in;
endmodule
| 7.611223 |
module BlackBoxPassthrough2 (
input [0:0] in,
output [0:0] out
);
assign out = in;
endmodule
| 7.611223 |
module BlackBoxMinus (
input [15:0] in1,
input [15:0] in2,
output [15:0] out
);
assign out = in1 + in2;
endmodule
| 8.136331 |
module BlackBoxRegister (
input [0:0] clock,
input [0:0] in,
output [0:0] out
);
reg [0:0] register;
always @(posedge clock) begin
register <= in;
end
assign out = register;
endmodule
| 7.056767 |
module BlackBoxConstant #(
parameter int WIDTH = 1,
parameter int VALUE = 1
) (
output [WIDTH-1:0] out
);
assign out = VALUE;
endmodule
| 8.335849 |
module BlackBoxStringParam #(
parameter string STRING = "zero"
) (
output [31:0] out
);
assign out = (STRING == "one") ? 1 : (STRING == "two") ? 2 : 0;
endmodule
| 9.526617 |
module BlackBoxRealParam #(
parameter real REAL = 0.0
) (
output [63:0] out
);
assign out = $realtobits(REAL);
endmodule
| 8.706008 |
module BlackBoxTypeParam #(
parameter type T = bit
) (
output T out
);
assign out = 32'hdeadbeef;
endmodule
| 7.576245 |
module BlackBoxToTest #(
parameter aWidth = 0,
parameter bWidth = 0
) (
input [aWidth-1:0] io_inA,
input [bWidth-1:0] io_inB,
output reg [aWidth-1:0] io_outA,
output reg [bWidth-1:0] io_outB,
input io_clockPin,
input io_resetPin
);
always @(posedge io_clockPin or posedge io_resetPin)... | 6.802355 |
module Black (
G6_8,
P6_8,
G7_10,
P7_10,
G6_10,
P6_10
);
input G6_8, P6_8, G7_10, P7_10;
output G6_10, P6_10;
wire s1;
assign s1 = P6_8 & G7_10;
assign G6_10 = s1 | G6_8;
assign P6_10 = P6_8 & P7_10;
endmodule
| 6.530159 |
module Black (
G6_8,
P6_8,
G7_10,
P7_10,
G6_10,
P6_10
);
input G6_8, P6_8, G7_10, P7_10;
output G6_10, P6_10;
wire s1;
assign s1 = P6_8 & G7_10;
assign G6_10 = s1 | G6_8;
assign P6_10 = P6_8 & P7_10;
endmodule
| 6.530159 |
module BufferCC (
input io_initial,
input io_dataIn,
output io_dataOut,
input clock_out,
input clockCtrl_systemReset
);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clock_out) begin
if (clockCtrl_systemReset) begin
buffers_0 <= io_initial;
... | 6.712921 |
module BufferCC_1_ (
input io_dataIn,
output io_dataOut,
input clock_out,
input clockCtrl_resetUnbuffered_regNext
);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clock_out) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 7.044402 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
input [15:0] io_push_payload_data,
input [4:0] io_push_payload_context_context,
output reg io_pop_valid,
input io_pop_ready,
output reg [15:0] io_pop_payload_data,
output reg [4:0] io_pop_payload_context_context,
... | 7.046487 |
module UartCtrl (
input [2:0] io_config_frame_dataLength,
input `UartStopType_defaultEncoding_type io_config_frame_stop,
input `UartParityType_defaultEncoding_type io_config_frame_parity,
input [11:0] io_config_clockDivider,
input io_write_valid,
output io_write_ready,
input [7:0] io_write_p... | 7.177325 |
module BufferCC_2_ (
input [7:0] io_dataIn,
output [7:0] io_dataOut,
input clock_out,
input clockCtrl_systemReset
);
reg [7:0] buffers_0;
reg [7:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clock_out) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule... | 7.089398 |
module StreamFifoLowLatency_1_ (
input io_push_valid,
output io_push_ready,
input io_push_payload_error,
input [31:0] io_push_payload_inst,
output reg io_pop_valid,
input io_pop_ready,
output reg io_pop_payload_error,
output reg [31:0] io_pop_payload_inst,
input io_flush,
output ... | 7.046487 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input clock_out,
input clockCtrl_resetUnbuffered_regNex... | 7.790686 |
module BufferCC_3_ (
input io_dataIn,
output io_dataOut,
input clock_out
);
reg buffers_0;
reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge clock_out) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 7.324384 |
module was generated automatically
* using the icepll tool from the IceStorm project.
* Use at your own risk.
*
* Given input frequency: 25.000 MHz
* Requested output frequency: 16.000 MHz
* Achieved output frequency: 16.016 MHz
*/
module blackice_mx_pll(
input clock_in,
output clock_out,
output... | 7.841705 |
module randomGenerator (
clk,
key,
randResult
);
input clk;
input [3:0] key;
output [3:0] randResult;
reg [32:0] cnt;
reg [ 3:0] randTemp;
initial begin
randTemp = 0;
cnt = 0;
end
always @(posedge clk) begin
if (key[1] == 0 | key[2] == 0 | key[3] == 0) cnt = cnt + 1;
els... | 6.649502 |
module display_7seg2 (
sw,
HEX
);
input [3:0] sw;
output [0:6] HEX;
assign HEX = (sw == 4'b0000) ? 7'b0000001 : //0
(sw == 4'b0001) ? 7'b1001111 : //1
(sw == 4'b0010) ? 7'b0010010 : //2
(sw == 4'b0011) ? 7'b0000110 : //3
(sw == 4'b0100) ? 7'b1001100 : //4
(sw == 4'b010... | 6.760025 |
module display_7seg (
sw,
cntl,
res,
HEX
);
input [3:0] sw;
input [2:0] res;
input cntl;
output [0:6] HEX;
assign HEX = (sw == 4'b0001 && cntl == 0) ? 7'b0001000 : //A
(sw == 4'b0010 && cntl == 0) ? 7'b0010010 : //2
(sw == 4'b0011 && cntl == 0) ? 7'b0000110 : //3
(sw == ... | 7.0436 |
module blackjack_game_test (
input clock_100Mhz,
reset,
staylever,
output reg [7:0] Anode_Activate,
output reg [6:0] LED_out
);
reg [ 4:0] LED_BCD;
reg [19:0] refresh_counter;
wire [ 2:0] LED_activating_counter;
reg [4:0] out0, out1, out2, out3, out4, out5, out6, out7;
integer seed = 13... | 7.10863 |
module BSnowman_RAM_IN (
pix_val,
indx,
wren
);
input [9:0] indx;
output [15:0] pix_val;
output reg wren;
reg [15:0] pix_val;
reg [15:0] in_ram [839:0];
always @(indx) begin
pix_val = in_ram[indx];
wren = pix_val[0];
end
initial begin
$readmemb("BlackSnowman.txt", in_ram);
... | 6.780081 |
module blackwhite (
vin_rsc_z,
threshold_rsc_z,
vout_rsc_z,
clk,
en,
arst_n
);
input [29:0] vin_rsc_z;
input [9:0] threshold_rsc_z;
output [29:0] vout_rsc_z;
input clk;
input en;
input arst_n;
// Interconnect Declarations
wire [29:0] vin_rsc_mgc_in_wire_d;
wire [ 9:0] thresho... | 7.074218 |
module black_background_graphic (
x,
y,
flush_x,
flush_y,
colour,
enable
);
input [6:0] x;
input [6:0] y;
input [6:0] flush_x;
input [6:0] flush_y;
output reg [5:0] colour;
output reg enable;
always @(*) begin
colour <= 6'b000000;
enable <= 1;
end
endmodule
| 6.504831 |
module black_box (
input a,
b,
c,
d,
output x,
y
);
assign x = a | (b & c);
assign y = b & d;
endmodule
| 7.235556 |
module black_box1 (
in1,
in2,
dout
);
input in1, in2;
output dout;
endmodule
| 6.756224 |
module blake2b_G (
input wire clk_i,
input wire rst_i,
// input signals
input wire [ `GINDEX_BUS] index_i,
input wire [`ROUND_INDEX_BUS] round_i,
input wire [ `WORD_BUS] a_i,
input wire [ `WORD_BUS] b_i,
input wire [ `WORD_BUS] c_i,
input wire [ `WO... | 7.034314 |
module blake2b_mhreg (
input wire clk_i,
input wire rst_i,
input wire [16*`WORD_WIDTH-1:0] m_i,
output reg [16*`WORD_WIDTH-1:0] m_o,
input wire [8*`WORD_WIDTH-1:0] h_i,
output reg [8*`WORD_WIDTH-1:0] h_o,
input wire [8*`MINDEX_WIDTH-1:0] mindex_bus_i,
output wire [8*`WORD_WIDTH-1... | 6.869584 |
module to allow us to build versions with 1, 2, 4
// and even 8 parallel compression functions.
//
//
// Author: Joachim Strömbergson
// Copyright (c) 2018, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the follo... | 6.663653 |
module to allow us to build versions with 1, 2, 4
// and even 8 parallel compression functions.
//
//
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are m... | 6.663653 |
module blake512_CB_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input ... | 6.581679 |
module blake512_CB (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
... | 7.185163 |
module blake512_M_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input ... | 6.865971 |
module blake512_M (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
... | 7.196522 |
module blake512_sigma_rom (
addr0,
ce0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 4;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input [AWIDTH-1:0] addr0;
input ce0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
inp... | 7.423881 |
module blake512_sigma (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd4;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;... | 7.423881 |
module Blake_Red_Flashing_LED (
input CLK,
output LED_RED
);
reg [15:0] MclkDiv_Count;
reg [7:0] MSDiv_Count;
reg OneMsClk;
reg EighthSecondClk;
assign LED_RED = EighthSecondClk;
// Setup the 1ms counter
always @(posedge CLK) begin
if (MclkDiv_Count == 50000) begin
MclkDiv_Count <= 16... | 7.001727 |
module Blanket_BIST (
input Clock,
output GoNoGo,
output Done
);
wire [7:0] Adr_Counter_SRAM;
wire WE_Counter_SRAM;
wire [3:0] Data_in_Counter_SRAM;
reg [10:0] Done_Counter = 0;
wire [3:0] Data_out_SRAM_Comp;
wire Comparator_output;
Counter B_Counter (
.clk(Clock),
.Counter_Addres... | 6.838783 |
module blanking_adjustment #(
parameter rst_delay_msb = 15,
parameter rst_delay_cyc = 'd17600,
parameter h_active = 'd1920,
parameter h_total = 'd2200,
parameter v_active = 'd1080,
parameter v_total = 'd1125,
parameter H_FRONT_PORCH = 'd88,
parameter H_SYNCH =... | 8.2179 |
module BlankSyncGen #(
// Width of counters
parameter COUNTER_WIDTH = 12,
// Horizontal timing parameters
parameter HSYNC_ON = 2007, //Active + Front
parameter HSYNC_OFF = 2051, //Active + Front + SyncWidth
parameter HBLANK_ON = 1919, //Active Pixels in the line
parameter HBL... | 8.181388 |
module blank_cell_rom (
//input
clk,
addr,
//output
data
);
input wire clk;
input [12:0] addr;
output reg [7:0] data;
always @(posedge clk) begin
data <= 8'b00000000;
end
endmodule
| 6.595879 |
module blank_rom (
input wire clk,
input wire [0:0] row,
input wire [0:0] col,
output reg [11:0] color_data
);
(* rom_style = "block" *)
//signal declaration
reg [0:0] row_reg;
reg [0:0] col_reg;
always @(posedge clk) begin
row_reg <= row;
col_reg <= col;
end
always @*
case... | 7.873982 |
module Blastoise (
input [7:0] in, //Entrada del dato de los 8 bits.Se introduce mediante los switches
input send, //push button G12 enva la cadena o trama
input clk, //reloj interno de la basys
input Rx, //Entrada del receptor
input reset, //a la mera no se necesita reset :o
output Tx, /... | 8.068938 |
module blastT (
input clk,
input [31:0] data,
input [31:0] address, //How many bits should it be?
input dataValid,
output [511:0] querry,
output reg querryValid
);
reg [511:0] querryReg;
assign querry = querryReg;
always @(posedge clk) begin
if (dataValid & address == 64) querryV... | 6.643528 |
module BLC (
input wire [15:0] o,
input wire [15:0] x,
output wire [18:0] log
//output wire [14:0] f /* fraction */
);
reg [ 3:0] k;
reg [15:0] y;
assign log = {k, y[14:0]};
always @(*) begin
case (o)
/*1.*/
16'b1000_0000_0000_0000: begin
k = 4'b1111;
y = x;
... | 6.641326 |
module bldc_FSM (
output wire [5:0] output_pins,
input fsm_clk,
pwm_input
);
//STATES
parameter AH_BL = 3'b000;
parameter AH_CL = 3'b001;
parameter BH_CL = 3'b010;
parameter BH_AL = 3'b011;
parameter CH_AL = 3'b100;
parameter CH_BL = 3'b101;
//OUTPUTS
//Since module is not TLE, we need ... | 7.258622 |
module bldc_hall (
clk,
rst_n,
//--------------------------------------
//Hall sensor inputs
hall_data_i,
//--------------------------------------
//Hall sensor output
hall_data_o,
hall_change_o
);
//-----------------------------------------------------------------------------
//... | 7.306484 |
module bldc_wb_slave (
clk,
rst_n,
//---------------------------------
//Wishbone interface
sel_i,
dat_i,
addr_i,
cyc_i,
we_i,
stb_i,
ack_o,
dat_o,
//---------------------------------
//BLDC register interface
reg_wdata_o,
reg_wen_o,
reg_ren_o,
reg... | 8.346954 |
module ble_tx_clarity
//
module ble_tx_clarity (pll_64M_CLKI, pll_64M_CLKI2, pll_64M_CLKOP, pll_64M_LOCK,
pll_64M_RST, pll_64M_SEL) /* synthesis sbp_module=true */ ;
input pll_64M_CLKI;
input pll_64M_CLKI2;
output pll_64M_CLKOP;
output pll_64M_LOCK;
input pll_64M_RST;
input pll_64M_... | 6.742567 |
module exu (
input clk,
input rst,
input [31:0] exu_i_pc,
input [31:0] exu_i_rs1_data,
input [31:0] exu_i_rs2_data,
input [31:0] exu_i_imm,
input [1:0] exu_i_a_sel,
input [1:0] exu_i_b_sel,
input [10:0] exu_i_alu_sel,
input [3:0] exu_i_br_sel,
output [31:0] exu_o_exu_data,
... | 8.840183 |
module bru (
input [31:0] bru_i_a,
input [31:0] bru_i_b,
input bru_i_br_un,
output bru_o_br_eq,
output bru_o_br_lt
);
wire signed [31:0] a_signed, b_signed;
assign a_signed = bru_i_a;
assign b_signed = bru_i_b;
assign bru_o_br_eq = (bru_i_a === bru_i_b);
assign b... | 6.901967 |
module regfile (
input clk,
input [ 4:0] regfile_i_rd_addr,
input regfile_i_w_en,
input [31:0] regfile_i_rd_data,
input [ 4:0] regfile_i_rs1_addr,
output [31:0] regfile_o_rs1_data,
input [ 4:0] regfile_i_rs2_addr,
output [31:0] regfile_o_rs2_data
);
(* ram_style = "di... | 7.809308 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.