code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bm_functional_test (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
counter
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [7:0] counter;
reg [`B2TS-1:0] out0;
reg [`B2TS-1:0] out1;
wire [`B2TS-1:0] temp1;
wire [`B2TS-1:0] temp2;
wire [`B2TS-1:0] temp3;
wire [`B2TS-1:0] temp4;
reg [7:0]counter;
always @(posedge clock or negedge reset_n) begin
if (~reset_n) begin
counter <= 0;
out1 <= 0;
out0 <= 0;
end else begin
case (counter)
8'b00000000: out0 <= a_in & b_in;
8'b00000001: out0 <= a_in | b_in;
8'b00000010: out0 <= a_in ^ b_in;
8'b00000011: out0 <= a_in * b_in;
8'b00000100: out0 <= a_in + b_in;
8'b00000101: out0 <= a_in - b_in;
8'b00000110: out0 <= temp1;
8'b00000111: out0 <= temp2;
8'b00001000: out0 <= temp3;
8'b00001001: out0 <= temp4;
8'b00001010: out0 <= temp1 ? temp2 : temp3;
default: out0 <= 8'b11001101;
endcase
if (counter <= 8'b00001111) begin
out1 <= 1;
end else begin
out1 <= 0;
end
if (counter == 8'b11111111) counter <= 0;
else counter <= counter + 1;
end
end
assign temp1 = c_in * d_in;
assign temp2 = c_in + d_in;
assign temp3 = c_in - d_in;
assign temp4 = ~c_in & d_in;
endmodule
| 7.525302 |
module bm_function_2 (
clock,
reset_n,
a,
b,
c,
d,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a;
input [`BITS-1:0] b;
input c;
input d;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
wire out1;
reg temp1;
reg [`BITS-1:0] temp2;
function simple_func;
input [`BITS-1:0] in1;
input [`BITS-1:0] in2;
input in3;
input in4;
simple_func <= in1[0] & in2[0] | in3 ^ in4;
endfunction
function [`BITS-1:0] simple_func_2;
input in3;
input in4;
begin
simple_func_2[1] <= in3 & in4;
simple_func_2[0] <= in3 | in4;
end
endfunction
assign out1 = simple_func(a, b, c, d) & c;
always @(posedge clock or negedge reset_n) begin
temp1 <= simple_func(a, b, c, d);
temp2 <= simple_func_2(c, d);
out0 <= temp1 & temp2;
end
endmodule
| 6.647281 |
module bm_if_collapse (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out2,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output [`BITS-1:0] out2;
output out1;
reg [`BITS-1:0] out0;
reg [`BITS-1:0] out2;
reg out1;
wire [`BITS-1:0] temp_a;
a top_a (
clock,
a_in,
b_in,
temp_a
);
always @(posedge clock) begin
if (c_in == 1'b0) begin
out0 <= 2'b00;
out1 <= 1'b0;
end else begin
if (d_in == 1'b1) begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
end
out2 <= temp_a;
end
endmodule
| 7.300585 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
always @(posedge clock) begin
case (a_in)
2'b00: begin
if (b_in != 2'b01) begin
out2 <= 2'b11;
end
end
2'b01: out1 <= 2'b10;
2'b10: out1 <= 2'b01;
2'b11: out1 <= 2'b00;
endcase
out <= out1 & out2;
end
endmodule
| 6.866335 |
module bm_if_common (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out2,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output [`BITS-1:0] out2;
output out1;
reg [`BITS-1:0] out0;
reg [`BITS-1:0] out2;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a (
clock,
a_in,
temp_a
);
always @(posedge clock) begin
if (c_in == 1'b0) begin
out0 <= 2'b00;
out1 <= 1'b0;
end else begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
out2 <= temp_a;
end
endmodule
| 7.288545 |
module a (
clock,
a_in,
out
);
input clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
always @(posedge clock) begin
case (a_in)
2'b00: out2 <= 2'b11;
2'b01: out1 <= 2'b10;
2'b10: out1 <= 2'b01;
2'b11: out1 <= 2'b00;
endcase
out <= out1 & out2;
end
endmodule
| 6.866335 |
module bm_if_reset (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
wire [`BITS-1:0] temp_a;
a top_a (
clock,
a_in,
temp_a
);
always @(posedge clock or negedge reset_n) begin
if (reset_n == 1'b0) begin
out0 <= 2'b00;
out1 <= 1'b0;
end else begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
end
endmodule
| 7.609874 |
module a (
clock,
a_in,
out
);
input clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
case (a_in)
2'b00: out <= 2'b11;
2'b01: out <= 2'b10;
2'b10: out <= 2'b01;
2'b11: out <= 2'b00;
endcase
end
endmodule
| 6.866335 |
module defines a J-K flip flop with an
// asynchronous, active low reset.
//
/*********************************************************/
// DEFINES
`define DEL 1 // Clock-to-output delay. Zero
// time delays can be confusing
// and sometimes cause problems.
// TOP MODULE
module bm_jk_rtl(
clk,
clr_n,
j,
k,
q,
q_n);
// INPUTS
input clk; // Clock
input clr_n; // Active low, asynchronous reset
input j; // J input
input k; // K input
// OUTPUTS
output q; // Output
output q_n; // Inverted output
// INOUTS
// SIGNAL DECLARATIONS
wire clk;
wire clr_n;
wire j;
wire k;
reg q;
wire q_n;
// PARAMETERS
// Define the J-K input combinations as parameters
parameter[1:0] HOLD = 0,
RESET = 1,
SET = 2,
TOGGLE = 3;
// ASSIGN STATEMENTS
assign #`DEL q_n = ~q;
// MAIN CODE
// Look at the falling edge of clock for state transitions
always @(negedge clk or negedge clr_n) begin
if (~clr_n) begin
// This is the reset condition. Most synthesis tools
// require an asynchronous reset to be defined this
// way.
q <= #`DEL 1'b0;
end
else begin
case ({j,k})
RESET: q <= #`DEL 1'b0;
SET: q <= #`DEL 1'b1;
TOGGLE: q <= #`DEL ~q;
endcase
end
end
endmodule
| 8.138493 |
module bm_log_all(clock,
reset_n,
a,
b,
out1,
out2,
out3,
out4,
out5,
out6,
out7,
out8,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a;
input [`BITS-1:0] b;
output [`BITS-1:0] out1;
output [`BITS-1:0] out2;
output [`BITS-1:0] out3;
output [`BITS-1:0] out4;
output [`BITS-1:0] out5;
output [`BITS-1:0] out6;
output [`BITS-1:0] out7;
output [`BITS-1:0] out8;
wire [`BITS-1:0] out1;
wire [`BITS-1:0] out2;
wire [`BITS-1:0] out3;
wire [`BITS-1:0] out4;
wire [`BITS-1:0] out5;
wire [`BITS-1:0] out6;
wire [`BITS-1:0] out7;
wire [`BITS-1:0] out8;
// ASSIGN STATEMENTS
assign out1 = a & b; // AND
assign out2 = a | b; // OR
assign out3 = a ^ b; // XOR
assign out4 = a ~^ b; // XNOR
assign out5 = a ~& b; // NAND
assign out6 = a ~| b; // NOR
assign out7 = ~a; // NOT
assign out8 = (a & b) | (a ^ b) | (~a | b);
endmodule
| 7.299691 |
module bm_lpm_all(clock,
reset_n,
a,
b,
out1,
out2,
out3,
out4,
out5,
out6,
out7,
out8,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a;
input [`BITS-1:0] b;
output [`BITS-1:0] out1;
output [`BITS-1:0] out2;
output [`BITS-1:0] out3;
output [`BITS-1:0] out4;
output [`BITS-1:0] out5;
output [`BITS-1:0] out6;
output [`BITS-1:0] out7;
output [`BITS-1:0] out8;
wire [`BITS-1:0] out1;
wire [`BITS-1:0] out2;
wire [`BITS-1:0] out3;
wire [`BITS-1:0] out4;
wire [`BITS-1:0] out5;
wire [`BITS-1:0] out6;
wire [`BITS-1:0] out7;
wire [`BITS-1:0] out8;
// ASSIGN STATEMENTS
assign out1 = a + b;
assign out2 = a - b;
assign out3 = (a == b) ? a : b;
assign out4 = (a >= b) ? a : b;
assign out5 = (a > b) ? a : b;
assign out6 = (a <= b) ? a : b;
assign out7 = (a < b) ? a : b;
assign out8 = (a == b) ? (a + b) : (b - a);
endmodule
| 7.718448 |
module bm_lpm_concat(clock,
reset_n,
a,
b,
out1,
out2,
out3,
out4,
out5,
out6,
out7,
out8,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-9:0] a;
input [`BITS-9:0] b;
output [`BITS-8:0] out1;
output [`BITS-7:0] out2;
output [`BITS-6:0] out3;
output [`BITS-5:0] out4;
output [`BITS-4:0] out5;
output [`BITS-3:0] out6;
output [`BITS-2:0] out7;
output [`BITS-1:0] out8;
wire [`BITS-8:0] out1;
wire [`BITS-7:0] out2;
wire [`BITS-6:0] out3;
wire [`BITS-5:0] out4;
wire [`BITS-4:0] out5;
wire [`BITS-3:0] out6;
wire [`BITS-2:0] out7;
wire [`BITS-1:0] out8;
// ASSIGN STATEMENTS
assign out1 = {1'b0, a};
assign out2 = {1'b1, 1'b0, b};
assign out3 = {1'b1, 1'b1, out1};
assign out4 = {1'b0, out3};
assign out5 = {1'b1, out4};
assign out6 = {1'b0, out5};
assign out7 = {1'b1, out6};
assign out8 = {1'b0, out7};
endmodule
| 7.870522 |
module bm_match1_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
out4,
out5,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS1-1:0] c_in;
input [`BITS1-1:0] d_in;
input [`BITS2-1:0] e_in;
input [`BITS3-1:0] f_in;
output [`BITS2-1:0] out0;
output [`BITS2-1:0] out1;
output [`BITS3-1:0] out2;
output [`BITS2-1:0] out3;
output [`BITS2-1:0] out4;
output [`BITS3-1:0] out5;
reg [`BITS2-1:0] out0;
reg [`BITS2-1:0] out1;
reg [`BITS3-1:0] out2;
wire [`BITS2-1:0] out3;
wire [`BITS2-1:0] out4;
wire [`BITS3-1:0] out5;
assign out3 = a_in * b_in;
assign out4 = c_in * d_in;
assign out5 = e_in * f_in; // 16 bit * 32 bit
always @(posedge clock)
begin
out0 <= a_in * b_in;
out1 <= c_in * d_in;
out2 <= e_in * f_in;
end
endmodule
| 6.849518 |
module bm_match2_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
out4,
out5,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1:0] e_in;
input [`BITS0-1:0] f_in;
output [`BITS2-1:0] out0;
output [`BITS2-1:0] out1;
output [`BITS2-1:0] out2;
output [`BITS0-1:0] out3;
output [`BITS2-1:0] out4;
output [`BITS2-1:0] out5;
reg [`BITS2-1:0] out0;
reg [`BITS2-1:0] out1;
reg [`BITS2-1:0] out2;
wire [`BITS0-1:0] out3;
wire [`BITS2-1:0] out4;
wire [`BITS2-1:0] out5;
assign out3 = a_in + b_in;
assign out4 = a_in * b_in + c_in * d_in;
assign out5 = a_in * b_in + c_in * d_in + e_in * f_in + a_in * c_in;
always @(posedge clock)
begin
out0 <= a_in * b_in + c_in * d_in;
out1 <= c_in + d_in;
out2 <= a_in * b_in + c_in * d_in + e_in * f_in + a_in * c_in;
end
endmodule
| 6.894027 |
module bm_match3_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1:0] e_in;
input [`BITS0-1:0] f_in;
output [`BITS2-1:0] out0;
output [`BITS2-1:0] out1;
output [`BITS0-1:0] out2;
output [`BITS0-1:0] out3;
reg [`BITS2-1:0] out0;
reg [`BITS2-1:0] out1;
reg [`BITS2-1:0] temp;
wire [`BITS0-1:0] out2;
wire [`BITS0-1:0] out3;
assign out3 = a_in + b_in;
assign out2 = e_in + f_in;
always @(posedge clock)
begin
// temp <= temp + a_in * b_in;
temp <= a_in * b_in + temp;
out0 <= temp;
out1 <= c_in + d_in;
end
endmodule
| 6.777051 |
module bm_match4_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
out4,
out5,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS1-1:0] d_in;
input [`BITS1-1:0] e_in;
input [`BITS1-1:0] f_in;
output [`BITS3-1:0] out0;
output [`BITS3-1:0] out1;
output [`BITS3-1:0] out2;
output [`BITS3-1:0] out3;
output [`BITS3-1:0] out4;
output [`BITS3-1:0] out5;
reg [`BITS3-1:0] out0;
reg [`BITS3-1:0] out1;
reg [`BITS3-1:0] out2;
wire [`BITS3-1:0] out3;
wire [`BITS3-1:0] out4;
wire [`BITS3-1:0] out5;
assign out3 = a_in * b_in;
assign out4 = c_in * d_in;
assign out5 = e_in * f_in;
always @(posedge clock)
begin
out0 <= out3 + out4 + out5;
out1 <= c_in * d_in;
out2 <= e_in * f_in;
end
endmodule
| 6.655997 |
module bm_match6_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1:0] e_in;
input [`BITS0-1:0] f_in;
output [`BITS2-1:0] out0;
output [`BITS2-1:0] out1;
output [`BITS2-1:0] out2;
reg [`BITS2-1:0] out0;
reg [`BITS2-1:0] out1;
wire [`BITS2-1:0] out2;
assign out2 = c_in * a_in + b_in;
always @(posedge clock)
begin
out0 <= d_in + e_in * f_in;
out1 <= c_in + d_in;
end
endmodule
| 6.986806 |
module bm_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg out1;
always @(posedge clock) begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
endmodule
| 7.263377 |
module bm_rng (
reset,
clk,
seed_0,
seed_1,
seed_2,
seed_3,
seed_4,
seed_5,
scan_in0,
scan_en,
test_mode,
scan_out0,
x0_out,
x1_out,
valid
);
input reset, // system reset
clk; // system clock
input scan_in0, // test scan mode data input
scan_en, // test scan mode enable
test_mode; // test mode select
input [31:0] seed_0, seed_1, seed_2;
input [31:0] seed_3, seed_4, seed_5;
output scan_out0; // test scan mode data output
output [15:0] x0_out, x1_out;
output valid;
parameter TAUS_PIPE = 3;
parameter LZD_PIPE = 1;
parameter LOG_PIPE = 8 + LZD_PIPE;
parameter SQR_PIPE = 6 + LZD_PIPE;
parameter COS_PIPE = 4;
parameter TOT_PIPE = TAUS_PIPE + LOG_PIPE + SQR_PIPE - 1;
wire clk_out;
wire [31:0] a, b;
wire [47:0] u0;
wire [15:0] u1;
wire signed [30:0] e;
wire signed [15:0] g0, g1;
wire signed [16:0] f;
reg signed [15:0] x0_out, x1_out;
reg signed [15:0] g0_1;
reg signed [15:0] g0_2;
reg signed [15:0] g0_3;
reg signed [15:0] g0_4;
reg signed [15:0] g0_5;
reg signed [15:0] g0_6;
reg signed [15:0] g0_7;
reg signed [15:0] g0_8;
reg signed [15:0] g0_9;
reg signed [15:0] g0_10;
reg signed [15:0] g0_11;
reg signed [15:0] g0_12;
reg signed [15:0] g1_1;
reg signed [15:0] g1_2;
reg signed [15:0] g1_3;
reg signed [15:0] g1_4;
reg signed [15:0] g1_5;
reg signed [15:0] g1_6;
reg signed [15:0] g1_7;
reg signed [15:0] g1_8;
reg signed [15:0] g1_9;
reg signed [15:0] g1_10;
reg signed [15:0] g1_11;
reg signed [15:0] g1_12;
reg valid;
reg [4:0] valid_cnt;
assign clk_out = clk;
assign u0 = {a, b[31:16]};
assign u1 = b[15:0];
taus taus_a (
.reset(reset),
.clk(clk),
.s0(seed_0),
.s1(seed_1),
.s2(seed_2),
.a(a)
);
taus taus_b (
.reset(reset),
.clk(clk),
.s0(seed_3),
.s1(seed_4),
.s2(seed_5),
.a(b)
);
sin_cos_unit sc (
.reset(reset),
.clk(clk),
.u1(u1),
.g0(g0),
.g1(g1)
);
log_unit log_a (
.reset(reset),
.clk(clk),
.u0(u0),
.e(e)
);
square_root_unit sq (
.reset(reset),
.clk(clk),
.e(e),
.f(f)
);
always @(posedge clk or posedge reset) begin
if (reset) begin
g0_1 <= 0;
g0_2 <= 0;
g0_3 <= 0;
g0_4 <= 0;
g0_5 <= 0;
g0_6 <= 0;
g0_7 <= 0;
g0_8 <= 0;
g0_9 <= 0;
g0_10 <= 0;
g0_11 <= 0;
g0_12 <= 0;
end else begin
g0_1 <= g0;
g0_2 <= g0_1;
g0_3 <= g0_2;
g0_4 <= g0_3;
g0_5 <= g0_4;
g0_6 <= g0_5;
g0_7 <= g0_6;
g0_8 <= g0_7;
g0_9 <= g0_8;
g0_10 <= g0_9;
g0_11 <= g0_10;
g0_12 <= g0_11;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
g1_1 <= 0;
g1_2 <= 0;
g1_3 <= 0;
g1_4 <= 0;
g1_5 <= 0;
g1_6 <= 0;
g1_7 <= 0;
g1_8 <= 0;
g1_9 <= 0;
g1_10 <= 0;
g1_11 <= 0;
g1_12 <= 0;
end else begin
g1_1 <= g1;
g1_2 <= g1_1;
g1_3 <= g1_2;
g1_4 <= g1_3;
g1_5 <= g1_4;
g1_6 <= g1_5;
g1_7 <= g1_6;
g1_8 <= g1_7;
g1_9 <= g1_8;
g1_10 <= g1_9;
g1_11 <= g1_10;
g1_12 <= g1_11;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
x0_out <= 0;
x1_out <= 0;
end else begin
x0_out <= $signed(f) * $signed(g0_12);
x1_out <= $signed(f) * $signed(g1_12);
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
valid_cnt <= 0;
valid <= 0;
end else begin
valid_cnt <= (valid_cnt < TOT_PIPE) ? valid_cnt + 1 : valid_cnt;
valid <= (valid_cnt < TOT_PIPE) ? 0 : 1;
end
end
endmodule
| 6.757165 |
module defines a Synchronous FIFO. The
// FIFO memory is implemented as a ring buffer. The read
// pointer points to the beginning of the buffer, while the
// write pointer points to the end of the buffer. Note that
// in this RTL version, the memory has one more location than
// the FIFO needs in order to calculate the FIFO count
// correctly.
//
/*********************************************************/
// DEFINES
`define FIFO_DEPTH 15 // Depth of FIFO (number of bytes)
`define FIFO_HALF 8 // Half depth of FIFO
// (this avoids rounding errors)
`define FIFO_BITS 4 // Number of bits required to
// represent the FIFO size
`define FIFO_WIDTH 8 // Width of FIFO data
// TOP MODULE
module bm_sfifo_rtl(
clock,
reset_n,
data_in,
read_n,
write_n,
data_out,
full,
empty,
half);
// INPUTS
input clock; // Clock input
input reset_n; // Active low reset
input [`FIFO_WIDTH-1:0] data_in; // Data input to FIFO
input read_n; // Read FIFO (active low)
input write_n; // Write FIFO (active low)
// OUTPUTS
output [`FIFO_WIDTH-1:0] data_out; // FIFO output data
output full; // FIFO is full
output empty; // FIFO is empty
output half; // FIFO is half full
// or more
// INOUTS
// SIGNAL DECLARATIONS
wire clock;
wire reset_n;
wire [`FIFO_WIDTH-1:0] data_in;
wire read_n;
wire write_n;
reg [`FIFO_WIDTH-1:0] data_out;
wire full;
wire empty;
wire half;
// The FIFO memory.
reg [`FIFO_WIDTH-1:0] fifo_mem[`FIFO_DEPTH-1:0];
// How many locations in the FIFO
// are occupied?
reg [`FIFO_BITS-1:0] counter;
// FIFO read pointer points to
// the location in the FIFO to
// read from next
reg [`FIFO_BITS-1:0] rd_pointer;
// FIFO write pointer points to
// the location in the FIFO to
// write to next
reg [`FIFO_BITS-1:0] wr_pointer;
// PARAMETERS
// ASSIGN STATEMENTS
assign full = (counter == `FIFO_DEPTH) ? 1'b1 : 1'b0;
assign empty = (counter == 0) ? 1'b1 : 1'b0;
assign half = (counter >= `FIFO_HALF) ? 1'b1 : 1'b0;
// MAIN CODE
// This block contains all devices affected by the clock
// and reset inputs
always @(posedge clock) begin
if (~reset_n) begin
// Reset the FIFO pointer
rd_pointer <= 0;
wr_pointer <= 0;
counter <= 0;
end
else begin
// If we are doing a simultaneous read and write,
// there is no change to the counter
if (~read_n && write_n) begin
// Decrement the FIFO counter
counter <= counter - 1;
end
else if (~write_n && read_n) begin
// Increment the FIFO counter
counter <= counter + 1;
end
if (~read_n) begin
// Increment the read pointer
// Check if the read pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (rd_pointer == `FIFO_DEPTH-1)
rd_pointer <= 0;
else
rd_pointer <= rd_pointer + 1;
end
if (~write_n) begin
// Increment the write pointer
// Check if the write pointer has gone beyond the
// depth of the FIFO. If so, set it back to the
// beginning of the FIFO
if (wr_pointer == `FIFO_DEPTH-1)
wr_pointer <= 0;
else
wr_pointer <= wr_pointer + 1;
end
end
end
// This block contains all devices affected by the clock
// but not reset
always @(posedge clock) begin
if (~read_n) begin
// Output the data
data_out <= fifo_mem[rd_pointer];
end
if (~write_n) begin
// Store the data
fifo_mem[wr_pointer] <= data_in;
end
end
endmodule
| 7.908588 |
module bm_simple_memory (
clock,
reset_n,
value_out,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] value_in;
output [`BITS-1:0] value_out;
wire [`BITS-1:0] value_out;
reg [`BITS-1:0] memory [3:0]; // 4 memory slots of Bits wide
reg [1:0] address_counter;
reg [1:0] address_counter2;
wire [`BITS-1:0] temp;
always @(posedge clock) begin
address_counter <= 2'b00;
address_counter2 <= 2'b01;
if (reset_n == 1'b1) memory[address_counter] <= value_in;
end
assign value_out = memory[address_counter2];
endmodule
| 6.730904 |
module bm_stmt_all_mod (
clock,
reset_n,
a_in,
b_in,
out1,
out0,
out3,
out4,
out5,
out6,
out7,
out8,
out10,
out9
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
output [`BITS-1:0] out0;
output out1;
output out3;
output [`BITS-1:0] out4;
output out5;
output [`BITS-1:0] out6;
output out7;
output [`BITS-1:0] out8;
output out9;
output [`BITS-1:0] out10;
reg [`BITS-1:0] out0;
reg out1;
reg out3;
reg [`BITS-1:0] out4;
reg out5;
reg [`BITS-1:0] out6;
reg out7;
reg [`BITS-1:0] out8;
reg out9;
reg [`BITS-1:0] out10;
always @(posedge clock) begin
case (a_in)
4'b0000: out0 <= 4'b1111;
4'b0001: out0 <= 4'b1110;
4'b0010: out0 <= 4'b1101;
4'b0011: out0 <= 4'b1100;
4'b0100: out0 <= 4'b1011;
4'b0101: out0 <= 4'b1010;
4'b0110: out0 <= 4'b1001;
4'b0111: out0 <= 4'b1000;
4'b1000: out0 <= 4'b0111;
4'b1001: out0 <= 4'b0110;
4'b1010: out0 <= 4'b0101;
4'b1011: out0 <= 4'b0100;
4'b1100: out0 <= 4'b0011;
4'b1101: out0 <= 4'b0010;
4'b1110: out0 <= 4'b0001;
4'b1111: out0 <= 4'b0000;
default: out0 <= 4'b0000;
endcase
end
always @(posedge clock) begin
case (b_in)
1'b0: out1 <= 1'b1;
1'b1: out1 <= 1'b0;
default: out1 <= 1'b0;
endcase
end
always @(posedge clock) begin
case (b_in)
1'b0: begin
out3 <= 1'b1;
out4 <= 4'b0001;
end
1'b1: begin
out3 <= 1'b0;
out4 <= 4'b0000;
end
default: out3 <= 1'b0;
endcase
end
always @(posedge clock) begin
if (b_in == 1'b0) begin
out5 <= 1'b1;
out6 <= 4'b0001;
end else begin
out5 <= 1'b0;
out6 <= 4'b0000;
end
end
always @(posedge clock) begin
if (b_in == 1'b0) begin
out7 <= 1'b1;
out8 <= 4'b0001;
end else if (a_in == 4'b0000) begin
out7 <= 1'b0;
out8 <= 4'b0100;
end else begin
out7 <= 1'b1;
out8 <= 4'b0000;
end
end
always @(posedge clock) begin
out9 <= 1'b1;
out10 <= 4'b0000;
end
endmodule
| 6.518082 |
module bm_stmt_compare_padding(clock,
reset_n,
a_in,
b_in,
out1,
out0,
out5,
out6,
out7,
out8,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
output [`BITS-1:0] out0;
output out1;
output out5;
output [`BITS-1:0] out6;
output out7;
output [`BITS-1:0] out8;
reg [`BITS-1:0] out0;
reg out1;
reg out5;
reg [`BITS-1:0] out6;
reg out7;
reg [`BITS-1:0] out8;
always @(posedge clock)
begin
case (a_in)
3'b000: out0 <= 4'b1111 ;
3'b001: out0 <= 4'b1110 ;
3'b010: out0 <= 4'b1101 ;
3'b011: out0 <= 4'b1100 ;
3'b100: out0 <= 4'b1011 ;
3'b101: out0 <= 4'b1010 ;
3'b110: out0 <= 4'b1001 ;
3'b111: out0 <= 4'b1000 ;
default: out0 <= 4'b0000 ;
endcase
end
always @(posedge clock)
begin
case (b_in)
2'b00: out1 <= 1'b1 ;
2'b01: out1 <= 1'b0 ;
default: out1 <= 1'b0 ;
endcase
end
always @(posedge clock)
begin
if (b_in == 2'b00)
begin
out5 <= 1'b1 ;
out6 <= 4'b0001 ;
end
else
begin
out5 <= 1'b0 ;
out6 <= 4'b0000 ;
end
end
always @(posedge clock)
begin
if (a_in == 1'b0)
begin
out7 <= 1'b1 ;
out8 <= 4'b0001 ;
end
else if (a_in == 3'b000)
begin
out7 <= 1'b0 ;
out8 <= 4'b0100 ;
end
else
begin
out7 <= 1'b1 ;
out8 <= 4'b0000 ;
end
end
endmodule
| 7.942505 |
module bm_tester(clock,
reset_n,
a_in,
b_in,
out0,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
output [`BITS-1:0] out0;
reg [`BITS-1:0] out0;
always @(posedge clock)
begin
case (a_in)
4'b0000: out0 <= 4'b1111 ;
4'b0001: out0 <= 4'b1110 ;
4'b0010: out0 <= 4'b1101 ;
4'b0011: out0 <= 4'b1100 ;
4'b0100: out0 <= 4'b1011 ;
4'b0101: out0 <= 4'b1010 ;
4'b0110: out0 <= 4'b1001 ;
4'b0111: out0 <= 4'b1000 ;
4'b1000: out0 <= 4'b0111 ;
4'b1001: out0 <= 4'b0110 ;
4'b1010: out0 <= 4'b0101 ;
4'b1011: out0 <= 4'b0100 ;
4'b1100: out0 <= 4'b0011 ;
4'b1101: out0 <= 4'b0010 ;
4'b1110: out0 <= 4'b0001 ;
4'b1111: out0 <= 4'b0000 ;
default: out0 <= 4'b0000 ;
endcase
end
endmodule
| 7.509721 |
module BNE (
Op,
Y
);
input wire [31:26] Op;
output wire Y;
wire NOTOp27;
wire NOTOp29;
wire NOTOp30;
wire NOTOp31;
assign Y = NOTOp29 & NOTOp31 & NOTOp30 & Op[28] & NOTOp27 & Op[26];
assign NOTOp30 = ~Op[30];
assign NOTOp29 = ~Op[29];
assign NOTOp27 = ~Op[27];
assign NOTOp31 = ~Op[31];
endmodule
| 6.590881 |
module bnn_cfg (
//common interface
input wire clk,
rst_n,
vad_duration,
//bnn interface
output reg [15:0] conv_wt1[ 4:0],
output reg [15:0] conv_wt2[ 4:0],
output reg [15:0] conv_wt3[ 4:0],
output reg [ 2:0] fc_wt1 [107:0],
output reg [ 2:0] fc_wt1 [107:0],
output reg mfcc_wr_en,
output reg [1:0] result,
//APB interface
input wire pclk,
input wire presetn,
input wire [12:0] paddr,
input wire pwrite,
input wire psel,
input wire penable,
input wire [31:0] pwdata,
output reg [31:0] prdata,
output wire pready,
output wire pslverr
);
wire apb_wr = psel && penable && pwrite; // apb = advanced peripheral bus
wire apb_rd = psel && penable && ~pwrite;
assign pready = 1'b1;
assign pslverr = 1'b0;
localparam CONV_WEIGHT1 = 13'h0xxx;
localparam CONV_WEIGHT2 = 13'h10xx;
localparam CONV_WEIGHT3 = 13'h110x;
localparam FC_WEIGHT2 = 13'h111x;
localparam FC_WEIGHT3 = 13'h112x;
localparam MFCC_WR_EN_ADDR = 13'h113x;
localparam RESULT_ADDR = 13'h1200;
wire meet_conv_wt = ((paddr[12] == 1'b0) || (paddr[12:8] == 5'h10) || (paddr[12:4] == 9'h110));
wire meet_fc_weight1 = (paddr[12:4] == 9'h111);
wire meet_fc_weight2 = (paddr[12:4] == 9'h112);
wire mfcc_wr_en_addr = (paddr[12:4] == 9'h113);
//传weight给 bnn_conv 和 bnn_fc
always @(posedge pclk, negedge presetn) begin
if (!presetn) begin
conv_wt1 <= '{default: 5'h0};
conv_wt2 <= '{default: 5'h0};
conv_wt3 <= '{default: 5'h0};
end else if (apb_wr && meet_conv_wt) begin
conv_wt1[4:0] <= pwdata[31:27];
conv_wt2[4:0] <= pwdata[26:22];
conv_wt3[4:0] <= pwdata[21:17];
end
end
always @(posedge pclk, negedge presetn) begin
if (!presetn) begin
meet_fc_weight1 <= '{default: 108'h0};
end else if (apb_wr && meet_fc_weight1)
case (paddr[3:2])
2'b00: fc_wt1[107:96] <= pwdata[31:20];
2'b01: fc_wt1[95:64] <= pwdata[31:0];
2'b10: fc_wt1[63:32] <= pwdata[31:0];
2'b11: fc_wt1[31:0] <= pwdata[31:0];
default: fc_wt1 <= fc_wt1;
endcase
end
always @(posedge pclk, negedge presetn) begin
if (!presetn) begin
meet_fc_weight2 <= '{default: 108'h0};
end else if (apb_wr && meet_fc_weight1)
case (paddr[3:2])
2'b00: fc_wt2[107:96] <= pwdata[31:20];
2'b01: fc_wt2[95:64] <= pwdata[31:0];
2'b10: fc_wt2[63:32] <= pwdata[31:0];
2'b11: fc_wt2[31:0] <= pwdata[31:0];
default: fc_wt2 <= fc_wt2;
endcase
end
always @(posedge pclk, negedge presetn) begin
if (!presetn) mfcc_wr_en <= 0;
else if (apb_wr && mfcc_wr_en_addr) mfcc_wr_en <= 1;
end
//读输出
always @(*) begin
if (apb_rd) begin
casex (paddr)
MFCC_WR_EN_ADDR: begin
prdata[31] = vad_duration;
end
RESULT_ADDR: begin
prdata[31:30] = result;
end
default: prdata = 32'h0;
endcase
end else prdata = 32'h0;
end
endmodule
| 7.722579 |
module bnn_conv (
input wire clk,
rst_n,
input wire [15:0] data_in[1:5], //输入的一帧数据 5 位
input wire conv_en,
output reg conv_vld,
output reg [31:0] conv_out[1:3] , //卷积一次输入，每一位为一个kernel和一帧输入的运算结果
output wire conv_done //conv整个（6帧，6x20）运算结束，目前应该没用到……
);
reg [15:0] weight1[1:5];
reg [15:0] weight2[1:5];
reg [15:0] weight3[1:5];
reg [ 5:0] cnt;
//权重赋值，手动键入即可
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 0;
conv_vld <= 0;
weight1 <= {16'd1, 16'd1, 16'd1, 16'd1, 16'd1};
weight2 <= {16'd2, 16'd2, 16'd2, 16'd2, 16'd2};
weight3 <= {16'd3, 16'd3, 16'd3, 16'd3, 16'd3};
end else if (conv_en) begin
conv_out[3] <= $signed(
data_in[5]
) * $signed(
weight1[5]
) + $signed(
data_in[4]
) * $signed(
weight1[4]
) + $signed(
data_in[3]
) * $signed(
weight1[3]
) + $signed(
data_in[2]
) * $signed(
weight1[2]
) + $signed(
data_in[1]
) * $signed(
weight1[1]
);
conv_out[2] <= $signed(
data_in[5]
) * $signed(
weight2[5]
) + $signed(
data_in[4]
) * $signed(
weight2[4]
) + $signed(
data_in[3]
) * $signed(
weight2[3]
) + $signed(
data_in[2]
) * $signed(
weight2[2]
) + $signed(
data_in[1]
) * $signed(
weight2[1]
);
conv_out[1] <= $signed(
data_in[5]
) * $signed(
weight3[5]
) + $signed(
data_in[4]
) * $signed(
weight3[4]
) + $signed(
data_in[3]
) * $signed(
weight3[3]
) + $signed(
data_in[2]
) * $signed(
weight3[2]
) + $signed(
data_in[1]
) * $signed(
weight3[1]
);
conv_vld <= 1'b1;
cnt <= cnt + 6'd1;
end else begin
conv_out[1] <= conv_out[1];
conv_out[2] <= conv_out[2];
conv_out[3] <= conv_out[3];
cnt <= cnt;
end
end
//输出
assign conv_done = (cnt == 6'd35) ? 1 : 0;
endmodule
| 7.637088 |
module bn_addr_gen_Add3u16Cati0u16u32_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3;
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [17:0] asc002;
assign asc002 = {in2, 2'B00};
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (asc002);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Add3u16Cati0u16u32_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3;
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [17:0] asc002;
assign asc002 = {in2, 2'B00};
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (asc002);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Add3u16Cati0u16u32_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3;
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [17:0] asc002;
assign asc002 = {in2, 2'B00};
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) + (asc002);
assign asc001 = asc001_tmp_0 + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Add_32Ux18U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [17:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Add_32Ux18U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [17:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Add_32Ux18U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [17:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Eqi1u8_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (13'B0000000000001 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi1u8_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (13'B0000000000001 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi1u8_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (13'B0000000000001 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi3u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (21'B000000000000000000011 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi3u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (21'B000000000000000000011 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi3u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (21'B000000000000000000011 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_16Ux2U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_16Ux2U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_16Ux2U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_8Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_8Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_8Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32i0u1_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wire [31:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in4) + (asc003);
assign asc002 = asc002_tmp_0 + (in2);
reg [31:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = 32'B00000000000000000000000000000000;
endcase
end
assign out1 = asc001;
endmodule
| 6.768275 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32i0u1_4 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wire [31:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in4) + (asc003);
assign asc002 = asc002_tmp_0 + (in2);
reg [31:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = 32'B00000000000000000000000000000000;
endcase
end
assign out1 = asc001;
endmodule
| 6.768275 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32u32u1_1 (
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in5, in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wire [31:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in4) + (asc003);
assign asc002 = asc002_tmp_0 + (in2);
reg [31:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in5) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in5;
endcase
end
assign out1 = asc001;
endmodule
| 6.768275 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32u32u1_4 (
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in5, in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wire [31:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in4) + (asc003);
assign asc002 = asc002_tmp_0 + (in2);
reg [31:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in5) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in5;
endcase
end
assign out1 = asc001;
endmodule
| 6.768275 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32u32u1_4_0 (
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in5, in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wire [31:0] asc002_tmp_0;
assign asc002_tmp_0 = +(in4) + (asc003);
assign asc002 = asc002_tmp_0 + (in2);
reg [31:0] asc001_tmp_1;
assign asc001 = asc001_tmp_1;
always @(ctrl1 or asc002 or in5) begin
case (ctrl1)
1'B1: asc001_tmp_1 = asc002;
default: asc001_tmp_1 = in5;
endcase
end
assign out1 = asc001;
endmodule
| 6.768275 |
module bn_addr_gen_N_Mux_1_2_7_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.563142 |
module bn_addr_gen_N_Mux_1_2_7_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.563142 |
module bn_addr_gen_N_Mux_1_2_7_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 7.563142 |
module bn_addr_gen_N_Mux_32_2_12_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = 32'B00000000000000000000000000000000;
endcase
end
assign out1 = asc001;
endmodule
| 7.563142 |
module bn_addr_gen_N_Mux_32_2_12_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = 32'B00000000000000000000000000000000;
endcase
end
assign out1 = asc001;
endmodule
| 7.563142 |
module bn_addr_gen_Or_1U_2_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.974538 |
module bn_addr_gen_Or_1U_3_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.974538 |
module for the bn_addr_gen module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
****************************************************************************/
`timescale 1 ps / 1 ps
module bn_addr_gen_vlwrapper(
clk,
rstn,
out_feature_width,
out_feature_height,
out_feature_channel,
bn_read_base_addr,
conv_type,
bn_en,
start_rising,
data_en,
bn_addr,
bn_addr_valid
);
input clk;
input rstn;
input [15:0] out_feature_width;
input [15:0] out_feature_height;
input [15:0] out_feature_channel;
input [31:0] bn_read_base_addr;
input [7:0] conv_type;
input [7:0] bn_en;
input start_rising;
input data_en;
output [31:0] bn_addr;
reg[31:0] bn_addr;
wire [31:0] m_bn_addr;
output bn_addr_valid;
reg bn_addr_valid;
wire m_bn_addr_valid;
// Instantiate the Verilog module that instantiates the SystemC module
bn_addr_gen_type_wrapper bn_addr_gen_sc(
.clk(clk),
.rstn(rstn),
.out_feature_width(out_feature_width),
.out_feature_height(out_feature_height),
.out_feature_channel(out_feature_channel),
.bn_read_base_addr(bn_read_base_addr),
.conv_type(conv_type),
.bn_en(bn_en),
.start_rising(start_rising),
.data_en(data_en),
.bn_addr(m_bn_addr),
.bn_addr_valid(m_bn_addr_valid)
);
// Always blocks for non-blocking assignments of type_wrapper outputs to
// Verilog Verificatoin wrapper outputs.
always @(m_bn_addr)
begin
bn_addr <= m_bn_addr;
end
always @(m_bn_addr_valid)
begin
bn_addr_valid <= m_bn_addr_valid;
end
endmodule
| 7.62099 |
module bn_bias_relu (
clk,
rst,
acc_in,
op_bias,
op_dout
);
//========================================
//parameter define
//========================================
parameter RELU = 0;
parameter Q = 8;
parameter DIN_Q = 6;
parameter DOUT_DW = 16;
parameter DOUT_Q = 6;
parameter ACC_WIDTH = 40;
parameter BIAS_DW = 16;
parameter BN = 0;
parameter BN_SCALE_Q = 13;
parameter BN_BIAS_Q = 13;
parameter MID_Q = 13;
//========================================
//input/output declare
//========================================
input clk;
input rst;
input [ACC_WIDTH-1:0] acc_in;
input [BIAS_DW-1:0] op_bias;
output reg [DOUT_DW-1:0] op_dout;
//========================================
// BN or bias
//========================================
wire [DOUT_DW-1:0] op_dout_tmp;
generate
//Without BN, use bias
if (BN == 0) begin : gen_block_without_bn
reg [ACC_WIDTH-1:0] op_acc;
always @(posedge clk) begin
if (rst) op_acc <= {ACC_WIDTH{1'b0}};
else
op_acc <= acc_in + ({{(ACC_WIDTH-BIAS_DW){op_bias[BIAS_DW-1]}}, op_bias} << DIN_Q); //bias with bw=BIAS_DW, Q=Q
//acc_in with bw=ACC_WIDTH, Q=DIN_Q+Q(from weight)
//op_acc with bw=ACC_WIDTH, Q=DIN_Q+Q
end
bit_trunc #(
.ROUND(1),
.WIDTH(ACC_WIDTH),
.MSB (Q + DIN_Q - DOUT_Q + DOUT_DW - 1),
.LSB (Q + DIN_Q - DOUT_Q)
) u0_bit_trunc (
.din (op_acc),
.dout(op_dout_tmp)
);
end // With BN enable
else begin : gen_block_with_bn
wire [15:0] acc_mid; //with Q=MID_Q
//assign acc_mid = acc_in[Q+DIN_Q-MID_Q+15: Q+DIN_Q-MID_Q];
bit_trunc #(
.ROUND(0),
.WIDTH(ACC_WIDTH),
.MSB (Q + DIN_Q - MID_Q + 15),
.LSB (Q + DIN_Q - MID_Q)
) u1_bit_trunc (
.din (acc_in),
.dout(acc_mid)
);
wire [15:0] bn_scale = op_bias[15:0]; //with Q=BN_SCALE_Q
reg [15:0] bn_bias_d1;
always @(posedge clk) begin
bn_bias_d1 <= op_bias[31:16];
end
wire [31:0] acc_scaled;
mul16_signed u_mul16_signed_bn (
.CLK(clk),
.A (acc_mid),
.B (bn_scale),
.P (acc_scaled) //with 32bit, Q=MID_Q+BN_SCALE_Q
);
reg [31:0] batch_out;
always @(posedge clk) begin
if (rst) batch_out <= 32'b0;
else
batch_out <= acc_scaled + ({{16{bn_bias_d1[15]}}, bn_bias_d1} << (MID_Q+BN_SCALE_Q-BN_BIAS_Q));
end
bit_trunc #(
// .WIDTH(ACC_WIDTH),
.ROUND(1),
.WIDTH(32),
.MSB (MID_Q + BN_SCALE_Q - DOUT_Q + DOUT_DW - 1),
.LSB (MID_Q + BN_SCALE_Q - DOUT_Q)
) u2_bit_trunc (
.din (batch_out),
.dout(op_dout_tmp)
);
end
endgenerate
//========================================
//non-linearization deal
//========================================
always @(posedge clk) begin
if (rst) op_dout <= {DOUT_DW{1'b0}};
else op_dout <= RELU ? (op_dout_tmp[DOUT_DW-1] ? 0 : op_dout_tmp) : op_dout_tmp;
end
endmodule
| 6.654781 |
module bN_demux_1_4_case #(
parameter DATA_WIDTH = 2
) (
input [DATA_WIDTH-1:0] din,
input [ 1:0] sel,
output reg [DATA_WIDTH-1:0] dout0,
output reg [DATA_WIDTH-1:0] dout1,
output reg [DATA_WIDTH-1:0] dout2,
output reg [DATA_WIDTH-1:0] dout3
);
localparam ZEROS = {DATA_WIDTH{1'b0}};
always @(*) begin
dout0 = ZEROS;
dout1 = ZEROS;
dout2 = ZEROS;
dout3 = ZEROS;
case (sel)
2'b00: dout0 = din;
2'b01: dout1 = din;
2'b10: dout2 = din;
2'b11: dout3 = din;
endcase
end
endmodule
| 7.518217 |
module bn_float32_DECODE_2U_1_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.338402 |
module bn_float32_N_Muxb_1_2_0_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.605837 |
module bn_float32_N_Muxb_1_2_0_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.605837 |
module bn_float32_N_Muxb_1_2_0_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.605837 |
module bn_float32_N_Muxb_1_2_0_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
default: asc001_tmp_0 = in3;
endcase
end
assign out1 = asc001;
endmodule
| 6.605837 |
module bn_mux_n_1_generate #(
parameter DATA_WIDTH = 8,
parameter SEL_WIDTH = 2
) (
input [((2**SEL_WIDTH)*DATA_WIDTH)-1:0] data,
input [ SEL_WIDTH-1:0] sel,
output [ DATA_WIDTH-1:0] y
);
wire [DATA_WIDTH-1:0] tmp_array[0:(2**SEL_WIDTH)-1];
genvar i;
generate
for (i = 0; i < 2 ** SEL_WIDTH; i = i + 1) begin : gen_array
assign tmp_array[i] = data[((i+1)*DATA_WIDTH)-1:(i*DATA_WIDTH)];
end
endgenerate
assign y = tmp_array[sel];
endmodule
| 8.486591 |
module board;
parameter REF_CLK_FREQ = 0; // 0 - 100 MHz, 1 - 250 MHz
localparam REF_CLK_HALF_CYCLE = (REF_CLK_FREQ == 0) ? 5000 : (REF_CLK_FREQ == 1) ? 2000 : 0;
integer i;
//
// System reset
//
reg cor_sys_reset_n;
//
// System clock
//
wire rp_sys_clk;
wire cor_sys_clk_p;
wire cor_sys_clk_n;
//
// PCI-Express facric interface
//
wire [(1 - 1):0] cor_pci_exp_txn;
wire [(1 - 1):0] cor_pci_exp_txp;
wire [(1 - 1):0] cor_pci_exp_rxn;
wire [(1 - 1):0] cor_pci_exp_rxp;
//
// PCI-Express End Point Instance
//
xilinx_pci_exp_ep xilinx_pci_exp_ep (
// SYS Inteface
.sys_clk_p(cor_sys_clk_p),
.sys_clk_n(cor_sys_clk_n),
// PCI-Express Interface
.pci_exp_txn(cor_pci_exp_txn),
.pci_exp_txp(cor_pci_exp_txp),
.pci_exp_rxn(cor_pci_exp_rxn),
.pci_exp_rxp(cor_pci_exp_rxp),
.sys_reset_n(cor_sys_reset_n)
);
xilinx_pcie_2_0_rport_v6 #(
.REF_CLK_FREQ(0),
.PL_FAST_TRAIN("TRUE"),
.LINK_CAP_MAX_LINK_WIDTH(6'b1),
.DEVICE_ID(16'hEBEB),
.ALLOW_X8_GEN2("FALSE"),
.LINK_CAP_MAX_LINK_SPEED(4'b1),
.LINK_CTRL2_TARGET_LINK_SPEED(4'b1),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(3'b010),
.VC0_TX_LASTPACKET(29),
.VC0_RX_RAM_LIMIT(2047),
.VC0_CPL_INFINITE("TRUE"),
.VC0_TOTAL_CREDITS_PD(308),
.VC0_TOTAL_CREDITS_CD(308),
.USER_CLK_FREQ(0 + 1)
) RP (
// SYS Inteface
.sys_clk(rp_sys_clk),
.sys_reset_n(cor_sys_reset_n),
// PCI-Express Interface
.pci_exp_txn(cor_pci_exp_rxn),
.pci_exp_txp(cor_pci_exp_rxp),
.pci_exp_rxn(cor_pci_exp_txn),
.pci_exp_rxp(cor_pci_exp_txp)
);
sys_clk_gen #(
.halfcycle(REF_CLK_HALF_CYCLE),
.offset(0)
) SYS_CLK_GEN_DSPORT (
.sys_clk(rp_sys_clk)
);
sys_clk_gen_ds #(
.halfcycle(REF_CLK_HALF_CYCLE),
.offset(0)
) SYS_CLK_GEN_COR (
.sys_clk_p(cor_sys_clk_p),
.sys_clk_n(cor_sys_clk_n)
);
initial begin
if ($test$plusargs("dump_all")) begin
`ifdef NCV //Cadence TRN dump
$recordsetup(
`ifdef BOARDx01
"design=boardx01",
`endif
`ifdef BOARDx04
"design=boardx04",
`endif
`ifdef BOARDx08
"design=boardx08",
`endif
"compress", "wrapsize=1G", "version=1", "run=1");
$recordvars();
`else
`ifdef VCS //Synopsys VPD dump
`ifdef BOARDx01
$vcdplusfile("boardx01.vpd");
`endif
`ifdef BOARDx04
$vcdplusfile("boardx04.vpd");
`endif
`ifdef BOARDx08
$vcdplusfile("boardx08.vpd");
`endif
$vcdpluson;
$vcdplusglitchon;
$vcdplusflush;
`else
// VCD dump
`ifdef BOARDx01
$dumpfile("boardx01.vcd");
`endif
`ifdef BOARDx04
$dumpfile("boardx04.vcd");
`endif
`ifdef BOARDx08
$dumpfile("boardx08.vcd");
`endif
$dumpvars(0, board);
`endif
`endif
end
$display("[%t] : System Reset Asserted...", $realtime);
cor_sys_reset_n = 1'b0;
for (i = 0; i < 500; i = i + 1) begin
@(posedge cor_sys_clk_p);
end
$display("[%t] : System Reset De-asserted...", $realtime);
cor_sys_reset_n = 1'b1;
end
endmodule
| 6.620881 |
module Board02 (
input wire SYSCLK, //16.384MHz-主时钟
input wire MRESET, //reset
output wire RUN, //run_led
//UART interface
input wire U3TXD, //UART_R
output wire U3RXD, //UART_T
//
output wire PN, //2P01
output wire DPN, //2P02
output wire PNCLK, //2P03
//input wire EXIDATA, //2P04
//input wire EXICLK, //2P05
output wire CODE1, //2P4+
output wire CODE2, //2P4-
input wire RHDB31, //2P7+
input wire RHDB32, //2P7-
output wire RECOVER_CLK, //2P8
output wire RECOVER_DATA, //2P9
output wire NOISE, //2P6
//
input wire HOLD, //Reserve
input wire S2NSS, //Reserve
input wire S2CLK, //Reserve
input wire S2MISO, //Reserve
input wire S2MOSI, //Reserve
//
input wire WMD, //Reserve
input wire DATA //Reserve
);
//////////////////////////////////////////////////////////////////////////////
//Pll*4
wire clk;
pllx4 pllx4_inst (
.inclk0(SYSCLK), //16.384Mhz
.c0(clk) //65.536Mhz
);
//////////////////////////////////////////////////////////////////////////////
wire dpn_out;
//PN序列生成器
wire jd_valid;
jd_gen jd_gen_init1 (
.clk(clk),
.reset_n(MRESET),//reset信号，未使用
.jd_valid(jd_valid),//使能输出
.jd_clk(PNCLK), //时钟输出
.jd_data(PN), //数据输出
.jd_xd(dpn_out) //相对码输出
);
/***********************************************************************************
************************************************************************************
*- 在下面填写自己的代码
************************************************************************************
***********************************************************************************/
wire [1:0] data_add_v;
wire [1:0] data_add_b;
wire [1:0] data_polar_out;
reg test_in = 0;
hdb3_add_v hdb2addv (
.clk(PNCLK),
.data_in(test_in),
.data_v(data_add_v)
);
hdb3_add_b hdb3addb (
.clk(PNCLK),
.add_b_in(data_add_v),
.add_b_out(data_add_b)
);
hdb3_d2t hdb3d2t (
.clk(PNCLK),
.polar_in(data_add_b),
.polar_out(data_polar_out)
);
assign CODE1 = data_polar_out[1];
assign CODE2 = data_polar_out[0];
//assign CODE1 = 0;
//assign CODE2 = PN;
//assign RECOVER_CLK = data_polar_out[1];
//assign RECOVER_DATA = data_polar_out[0];
/***********************************************************************************
************************************************************************************
*- 以下部分为运行指示灯显示
************************************************************************************
***********************************************************************************/
reg LED;
reg [23:0] cnt;
always @(posedge SYSCLK) begin
cnt <= cnt + 1'b1;
if (cnt == 24'hFFFFFF) begin
cnt <= 0;
LED <= ~LED;
end
end
assign RUN = DPN;
assign NOISE = 0;
endmodule
| 7.126778 |
module binary_to_BCD (
A,
ONES,
TENS,
HUNDREDS
);
input [7:0] A;
output [3:0] ONES, TENS, HUNDREDS;
wire [3:0] c1, c2, c3, c4, c5, c6, c7;
wire [3:0] d1, d2, d3, d4, d5, d6, d7;
assign d1 = {1'b0, A[7:5]};
assign d2 = {c1[2:0], A[4]};
assign d3 = {c2[2:0], A[3]};
assign d4 = {c3[2:0], A[2]};
assign d5 = {c4[2:0], A[1]};
assign d6 = {1'b0, c1[3], c2[3], c3[3]};
assign d7 = {c6[2:0], c4[3]};
binary_to_BCD_add3 m1 (
d1,
c1
);
binary_to_BCD_add3 m2 (
d2,
c2
);
binary_to_BCD_add3 m3 (
d3,
c3
);
binary_to_BCD_add3 m4 (
d4,
c4
);
binary_to_BCD_add3 m5 (
d5,
c5
);
binary_to_BCD_add3 m6 (
d6,
c6
);
binary_to_BCD_add3 m7 (
d7,
c7
);
assign ONES = {c5[2:0], A[0]};
assign TENS = {c7[2:0], c5[3]};
assign HUNDREDS = {0, 0, c6[3], c7[3]};
endmodule
| 7.621619 |
module binary_to_BCD_add3 (
in,
out
);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule
| 7.621619 |
module board2board_switching_wrapper #(
parameter DATA_WIDTH = 65,
parameter TOTAL_CLUSTERS = 4,
parameter TOTAL_OUTPUT_BOARDS = 14,
parameter FIFO_DEPTH_BITS = 6,
parameter BOARD_ID = 0
) (
b2b_clk,
b2b_rst_n,
b2b_srst_n,
cluster_data,
cluster_req,
cluster_almost_full,
cluster_empty,
output_board_event,
output_board_wren,
output_board_almost_full
);
input wire b2b_clk;
input wire b2b_rst_n;
input wire b2b_srst_n;
input wire [259 : 0] cluster_data;
wire [64:0] cluster_data_unpacked[0:3];
assign{>>{cluster_data_unpacked}} = cluster_data;
output wire [0 : 3] cluster_req;
wire cluster_req_unpacked[0:3];
assign{>>{cluster_req}} = cluster_req_unpacked;
input wire [0 : 3] cluster_almost_full;
wire cluster_almost_full_unpacked[0:3];
assign{>>{cluster_almost_full_unpacked}} = cluster_almost_full;
input wire [0 : 3] cluster_empty;
wire cluster_empty_unpacked[0:3];
assign{>>{cluster_empty_unpacked}} = cluster_empty;
output wire [909 : 0] output_board_event;
wire [64:0] output_board_event_unpacked[0:13];
assign{>>{output_board_event}} = output_board_event_unpacked;
output wire [0 : 13] output_board_wren;
wire output_board_wren_unpacked[0:13];
assign{>>{output_board_wren}} = output_board_wren_unpacked;
input wire [0 : 13] output_board_almost_full;
wire output_board_almost_full_unpacked[0:13];
assign{>>{output_board_almost_full_unpacked}} = output_board_almost_full;
board2board_switching #(
.DATA_WIDTH(65),
.TOTAL_CLUSTERS(4),
.TOTAL_OUTPUT_BOARDS(14),
.FIFO_DEPTH_BITS(6),
.BOARD_ID(0)
) inst (
.b2b_clk(b2b_clk),
.b2b_rst_n(b2b_rst_n),
.b2b_srst_n(b2b_srst_n),
.cluster_data(cluster_data_unpacked),
.cluster_req(cluster_req_unpacked),
.cluster_almost_full(cluster_almost_full_unpacked),
.cluster_empty(cluster_empty_unpacked),
.output_board_event(output_board_event_unpacked),
.output_board_wren(output_board_wren_unpacked),
.output_board_almost_full(output_board_almost_full_unpacked)
);
endmodule
| 9.11298 |
module boardRam (
data,
clk,
wren,
q
);
output [79:0] q;
input wren, clk;
input [79:0] data;
reg [79:0] q;
always @(posedge clk) begin
if (wren) q <= data;
end
endmodule
| 7.152651 |
module BoardTimerModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire Clock,
input wire Reset,
input wire Restart,
output wire OutActive10,
output wire OutActive20
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal = 1'b0;
wire Zero = 1'b0;
wire One = 1'b1;
wire true = 1'b1;
wire false = 1'b0;
wire Inputs_Restart;
wire nestedTimerInputs_Restart;
wire timerModule10_Restart;
wire timerModule10_OutActive;
wire timerModule20_Restart;
wire timerModule20_OutActive;
wire timerModule10RestarttimerModule10_RestartHardLink;
wire timerModule10OutActivetimerModule10_OutActiveHardLink;
wire timerModule20RestarttimerModule20_RestartHardLink;
wire timerModule20OutActivetimerModule20_OutActiveHardLink;
wire BoardSignals_Clock;
wire BoardSignals_Reset;
wire BoardSignals_Running;
wire BoardSignals_Starting;
wire BoardSignals_Started;
reg InternalReset = 1'b0;
work_Quokka_BoardSignalsProc BoardSignalsConnection (
BoardSignals_Clock,
BoardSignals_Reset,
BoardSignals_Running,
BoardSignals_Starting,
BoardSignals_Started,
Clock,
Reset,
InternalReset
);
BoardTimerModule_TopLevel_BoardTimerModule_timerModule10 BoardTimerModule_TopLevel_BoardTimerModule_timerModule10
(
// [BEGIN USER MAP FOR timerModule10]
// [END USER MAP FOR timerModule10]
.BoardSignals_Clock(BoardSignals_Clock),
.BoardSignals_Reset(BoardSignals_Reset),
.BoardSignals_Running(BoardSignals_Running),
.BoardSignals_Starting(BoardSignals_Starting),
.BoardSignals_Started(BoardSignals_Started),
.Restart(timerModule10RestarttimerModule10_RestartHardLink),
.OutActive(timerModule10OutActivetimerModule10_OutActiveHardLink)
);
BoardTimerModule_TopLevel_BoardTimerModule_timerModule20 BoardTimerModule_TopLevel_BoardTimerModule_timerModule20
(
// [BEGIN USER MAP FOR timerModule20]
// [END USER MAP FOR timerModule20]
.BoardSignals_Clock(BoardSignals_Clock),
.BoardSignals_Reset(BoardSignals_Reset),
.BoardSignals_Running(BoardSignals_Running),
.BoardSignals_Starting(BoardSignals_Starting),
.BoardSignals_Started(BoardSignals_Started),
.Restart(timerModule20RestarttimerModule20_RestartHardLink),
.OutActive(timerModule20OutActivetimerModule20_OutActiveHardLink)
);
assign Inputs_Restart = Restart;
assign nestedTimerInputs_Restart = Inputs_Restart;
assign timerModule10_Restart = nestedTimerInputs_Restart;
assign timerModule20_Restart = nestedTimerInputs_Restart;
assign OutActive10 = timerModule10_OutActive;
assign OutActive20 = timerModule20_OutActive;
assign timerModule10RestarttimerModule10_RestartHardLink = timerModule10_Restart;
assign timerModule10_OutActive = timerModule10OutActivetimerModule10_OutActiveHardLink;
assign timerModule20RestarttimerModule20_RestartHardLink = timerModule20_Restart;
assign timerModule20_OutActive = timerModule20OutActivetimerModule20_OutActiveHardLink;
// [BEGIN USER ARCHITECTURE]
// [END USER ARCHITECTURE]
endmodule
| 6.824355 |
module board_digilent (
input CLK,
input [1:0] KEY,
output [7:0] HEX,
output [7:0] AN,
output [1:0] LED
);
localparam CLK_DIV = 26;
wire rst_n = ~KEY[1];
wire idata = KEY[0];
wire [2:0] smile;
wire indicator;
wire strobe;
lab_top #(
.CLK_DIV(CLK_DIV)
) lab_top (
.clk (CLK),
.rst_n (rst_n),
.idata (idata),
.smile (smile),
.indicator(indicator),
.strobe (strobe)
);
hex_smile_ca hex_smile_ca (
.clk (CLK),
.rst_n(rst_n),
.smile(smile),
.hex (HEX),
.an (AN)
);
assign LED[0] = indicator;
assign LED[1] = idata;
endmodule
| 7.587034 |
module board_disp (
input CLK100MHZ,
input [16:0] data,
input [9:0] cx,
input [9:0] cy,
input pix_stb,
output reg [11:0] VGA_color = 0,
output [1:0] row,
output [1:0] col,
output draw
);
wire [11:0] board_color;
wire [11:0] row1_color;
wire [11:0] row2_color;
wire [11:0] row3_color;
wire [11:0] row4_color;
wire [ 4:0] cur_draw;
wire [ 1:0] row1_col;
wire [ 1:0] row2_col;
wire [ 1:0] row3_col;
wire [ 1:0] row4_col;
square board (
.color(12'hbba),
.sx(10'd170),
.sy(10'd90),
.cx(cx),
.cy(cy),
.size(10'd300),
.VGA_R(board_color[11:8]),
.VGA_G(board_color[7:4]),
.VGA_B(board_color[3:0]),
.draw(cur_draw[0])
);
row row1 (
.CLK100MHZ(CLK100MHZ),
.data(data),
.sy(10'd102),
.cx(cx),
.cy(cy),
.VGA_color(row1_color),
.position(row1_col),
.draw(cur_draw[1])
);
row row2 (
.CLK100MHZ(CLK100MHZ),
.data(data),
.sy(10'd174),
.cx(cx),
.cy(cy),
.VGA_color(row2_color),
.position(row2_col),
.draw(cur_draw[2])
);
row row3 (
.CLK100MHZ(CLK100MHZ),
.data(data),
.sy(10'd246),
.cx(cx),
.cy(cy),
.VGA_color(row3_color),
.position(row3_col),
.draw(cur_draw[3])
);
row row4 (
.CLK100MHZ(CLK100MHZ),
.data(data),
.sy(10'd318),
.cx(cx),
.cy(cy),
.VGA_color(row4_color),
.position(row4_col),
.draw(cur_draw[4])
);
assign draw = cur_draw[4] | cur_draw[3] | cur_draw[2] | cur_draw[1] | cur_draw[0];
assign row = cur_draw[4] ? 3 : cur_draw[3] ? 2 : cur_draw[2] ? 1 : 0;
assign col = cur_draw[4] ? row4_col: cur_draw[3] ? row3_col: cur_draw[2] ? row2_col:
cur_draw[1] ? row1_col: 0;
always @(*) begin
if (cur_draw[4]) VGA_color = row4_color;
else if (cur_draw[3]) VGA_color = row3_color;
else if (cur_draw[2]) VGA_color = row2_color;
else if (cur_draw[1]) VGA_color = row1_color;
else VGA_color = board_color;
end
endmodule
| 6.548299 |
module board_disp_sword (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire [7:0] en, // enable for each tube
input wire mode, // 0 for text mode, 1 for graphic mode
input wire [31:0] data_text, // text data to display
input wire [63:0] data_graphic, // graphic data to display
input wire [7:0] dot, // enable for each dot
input wire [15:0] led, // LED display
// LED interfaces
output wire led_clk,
output wire led_en,
output wire led_clr_n,
output wire led_do,
// 7-segment tube interfaces
output wire seg_clk,
output wire seg_en,
output wire seg_clr_n,
output wire seg_do
);
`include "function.vh"
parameter CLK_FREQ = 100; // main clock frequency in MHz
localparam SEG_PULSE = 1'b0;
localparam REFRESH_INTERVAL = 100, // refresh interval for led and segment tubes, in ms
COUNT_REFRESH = 1 + CLK_FREQ * REFRESH_INTERVAL * 1000, COUNT_BITS = GET_WIDTH(
COUNT_REFRESH - 1
);
function [6:0] digit2seg;
input [3:0] number;
begin
case (number)
4'h0: digit2seg = 7'b0111111;
4'h1: digit2seg = 7'b0000110;
4'h2: digit2seg = 7'b1011011;
4'h3: digit2seg = 7'b1001111;
4'h4: digit2seg = 7'b1100110;
4'h5: digit2seg = 7'b1101101;
4'h6: digit2seg = 7'b1111101;
4'h7: digit2seg = 7'b0000111;
4'h8: digit2seg = 7'b1111111;
4'h9: digit2seg = 7'b1101111;
4'hA: digit2seg = 7'b1110111;
4'hB: digit2seg = 7'b1111100;
4'hC: digit2seg = 7'b0111001;
4'hD: digit2seg = 7'b1011110;
4'hE: digit2seg = 7'b1111001;
4'hF: digit2seg = 7'b1110001;
endcase
end
endfunction
wire [63:0] segment, segment_text, segment_graphic;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : SEG_GEN
assign segment_text[8*i+7] = dot[i],
segment_text[8*i+6-:7] = en[i] ? digit2seg(
data_text[4*i+3-:4]
) : 7'b0,
segment_graphic[8*i+7-:8] = en[i] ? data_graphic[8*i+7-:8] : 8'b0;
end
endgenerate
assign segment = mode ? segment_graphic : segment_text;
wire led_start, seg_start;
wire led_clr, seg_clr;
reg [COUNT_BITS-1:0] clk_count = 0;
assign led_en = 1, led_clr_n = ~led_clr, seg_en = 1, seg_clr_n = ~seg_clr;
parallel2serial #(
.P_CLK_FREQ (CLK_FREQ),
.S_CLK_FREQ (20),
.DATA_BITS (16),
.CODE_ENDIAN(1)
) P2S_LED (
.clk(clk),
.rst(rst),
.data(SEG_PULSE ? led : ~led),
.start(led_start),
.busy(),
.finish(),
.s_clk(led_clk),
.s_clr(led_clr),
.s_dat(led_do)
);
parallel2serial #(
.P_CLK_FREQ (CLK_FREQ),
.S_CLK_FREQ (20),
.DATA_BITS (64),
.CODE_ENDIAN(1)
) P2S_SEG (
.clk(clk),
.rst(rst),
.data(SEG_PULSE ? segment : ~segment),
.start(seg_start),
.busy(),
.finish(),
.s_clk(seg_clk),
.s_clr(seg_clr),
.s_dat(seg_do)
);
always @(posedge clk) begin
if (rst) clk_count <= 0;
else if (clk_count[COUNT_BITS-1]) clk_count <= 0;
else clk_count <= clk_count + 1'h1;
end
assign led_start = clk_count[COUNT_BITS-1], seg_start = clk_count[COUNT_BITS-1];
endmodule
| 7.469975 |
module board_id_generator (
input wire clock,
input wire reset,
output reg ready = 1'b0,
output reg [31:0] board_identifier = 32'b0
);
wire dout;
reg read_en = 1'b0;
reg shift_en = 1'b0;
reg [56:0] shift_data = 57'b0;
reg [5:0] shift_count = 6'b0;
reg [5:0] slow_counter = 6'b0;
DNA_PORT #(
.SIM_DNA_VALUE(57'h12345678_9ABCDE)
) dna_port_inst (
.DOUT (dout),
.DIN (dout),
.READ (read_en),
.SHIFT(shift_en),
.CLK (slow_counter[5])
);
always @(posedge clock) begin
if (reset) begin
ready <= 0;
read_en <= 0;
shift_en <= 0;
shift_data <= 0;
shift_count <= 0;
board_identifier <= 0;
slow_counter <= 0;
end else begin
slow_counter <= slow_counter + 6'd1;
if (slow_counter == 0) begin
if (!(read_en || shift_en || ready)) begin
read_en <= 1;
ready <= 0;
end else begin
if (shift_count == 6'd0) begin
read_en <= 0;
shift_en <= 1;
shift_count <= shift_count + 6'd1;
end else if (shift_count <= 6'd56) begin
shift_count <= shift_count + 6'd1;
shift_data <= {shift_data[55:0], dout};
end else begin
read_en <= 0;
shift_en <= 0;
ready <= 1;
board_identifier <= shift_data[31:0];
end
end
end
end
end
endmodule
| 6.810783 |
module board_independent_wrapper (
input fast_clk,
input slow_clk,
input rst_n,
input fast_clk_en,
input [ 3:0] key,
input [ 7:0] sw,
output [ 7:0] led,
output [ 7:0] disp_en,
output [31:0] disp,
output [ 7:0] disp_dot
);
wire [ 4:0] res_vld;
wire [39:0] res;
pow_n_en_pipe_always #(
.w(8),
.n(5)
) i_pow_5 (
.clk (fast_clk),
.rst_n (rst_n),
.clk_en (fast_clk_en),
.arg_vld(key[0]),
.arg (sw),
.res_vld(res_vld),
.res (res)
);
assign disp_en = {
res_vld[3], res_vld[3], res_vld[2], res_vld[2], res_vld[1], res_vld[1], res_vld[0], res_vld[0]
};
assign disp = res[31:0];
assign disp_dot = 8'b0;
endmodule
| 7.34689 |
module implements conversation from control signals and raw data
// to encoded_data that is 6b/8b code.
// frame_start: 00000001
// frame_end: 00000010
// data: xxxxxx11
//
// Dependencies:
// <None>
//
// Revision: 1.0
//
// Parameters:
// <None>
//
// Inputs:
// clk - system clock.
// rst - reset.
// empty - whether input fifo is empty.
// valid - whether the output of input fifo is valid.
// frame_start - indicates that this module generates a frame start signal.
// frame_end - indicates that this module generates a frame end signal.
// raw_data - raw data.
// full - whether output fifo is full.
//
// Outputs:
// rd - control input fifo.
// encoded_data - encoded data output.
////////////////////////////////////////////////////////////////////////////////
module board_level_data_physical_encoder(
input clk,
input rst,
input empty,
output rd,
input valid,
input frame_start,
input frame_end,
input [5:0] raw_data,
output reg [7:0] encoded_data,
input full
);
reg [7:0] last_encoded_data;
reg last_full;
assign rd = ~full;
always @(posedge clk) begin
if(rst) begin
last_full <= 1'b0;
end
else begin
last_full <= full;
end
end
always @(posedge clk) begin
if(rst) begin
last_encoded_data <= 8'b0;
end
else begin
last_encoded_data <= encoded_data;
end
end
always @(*) begin
if(!valid) begin
encoded_data = last_full ? last_encoded_data : 8'b0;
end
else if(frame_start) begin
encoded_data = 8'b00000001;
end
else if(frame_end) begin
encoded_data = 8'b00000010;
end
else begin
encoded_data = {raw_data, 2'b11};
end
end
endmodule
| 6.733875 |
module implements conversation to control signals and raw data
// from encoded_data that is 6b/8b code.
// frame_start: 00000001
// frame_end: 00000010
// data: xxxxxx11
//
// Dependencies:
// <None>
//
// Revision: 1.0
//
// Parameters:
// <None>
//
// Inputs:
// clk - system clock.
// rst - reset.
// raw_data - raw data.
// raw_data_valid - whether raw data is valid.
//
// Outputs:
// frame_start - whether signal indicates frame start signal.
// frame_end - whether signal indicates frame end signal.
// decoded_data - decoded data.
// decoded_data_valid - whether decoded data is valid.
////////////////////////////////////////////////////////////////////////////////
module board_level_data_physical_decoder(
input clk,
input rst,
input[7:0] raw_data,
input raw_data_valid,
output reg frame_start,
output reg frame_end,
output reg[5:0] decoded_data,
output reg decoded_data_valid
);
always @(posedge clk) begin
if(rst) begin
frame_start <= 1'b0;
end
else if(!raw_data_valid) begin
frame_start <= 1'b0;
end
else if(raw_data == 8'b00000001) begin
frame_start <= 1'b1;
end
else begin
frame_start <= 1'b0;
end
end
always @(posedge clk) begin
if(rst) begin
frame_end <= 1'b0;
end
else if(!raw_data_valid) begin
frame_end <= 1'b0;
end
else if(raw_data == 8'b00000010) begin
frame_end <= 1'b1;
end
else begin
frame_end <= 1'b0;
end
end
always @(posedge clk) begin
if(rst) begin
decoded_data <= 6'b0;
end
else if(!raw_data_valid) begin
decoded_data <= 6'b0;
end
else begin
decoded_data <= raw_data[7:2];
end
end
always @(posedge clk) begin
if(rst) begin
decoded_data_valid <= 1'b0;
end
else if(!raw_data_valid) begin
decoded_data_valid <= 1'b0;
end
else if(raw_data == 8'b0) begin
decoded_data_valid <= 1'b0;
end
else begin
decoded_data_valid <= raw_data_valid;
end
end
endmodule
| 6.733875 |
module implements data transmission physical level.
//
// Dependencies:
// board_level_data_transmitter_physical_buffer(8-bit sync fifo with 16-depth)
// board_level_data_physical_encoder.v
// board_level_data_parallel_to_serial_fifo(8-bit to 1-bit async fifo with
// 16-depth)
//
// Revision: 1.0
//
// Parameters:
// <None>
//
// Inputs:
// clk - system clock.
// rst - reset.
// send_clk - send clock.
// frame_start - indicates that this module generates a frame start signal.
// frame_end - indicates that this module generates a frame end signal.
// data - send data(when frame_start or frame_end is "1",
// this signal is meaningless).
// we - write enable.
//
// Outputs:
// full - whether this module can't receive data because fifo is full.
// serial_data - serial data to receiver.
////////////////////////////////////////////////////////////////////////////////
module board_level_data_transmitter_physical(
input clk,
input rst,
input send_clk,
input frame_start,
input frame_end,
input [5:0] data,
input we,
output full,
output serial_data
);
//signals from board_level_data_transmitter_physical_buffer
wire [7:0] data_buffer_out;
wire data_buffer_empty;
wire data_buffer_rd;
wire data_buffer_valid;
//signals from board_level_data_physical_encoder
wire [7:0] encoded_data;
//signals from board_level_data_parallel_to_serial_fifo
wire async_fifo_full;
board_level_data_transmitter_physical_buffer board_level_data_transmitter_physical_buffer_inst(
.clk(clk),
.srst(rst),
.din({frame_start, frame_end, data}),
.wr_en(we),
.rd_en(data_buffer_rd),
.full(full),
.empty(data_buffer_empty),
.valid(data_buffer_valid),
.dout(data_buffer_out)
);
board_level_data_physical_encoder board_level_data_physical_encoder_inst(
.clk(clk),
.rst(rst),
.empty(data_buffer_empty),
.rd(data_buffer_rd),
.valid(data_buffer_valid),
.frame_start(data_buffer_out[7]),
.frame_end(data_buffer_out[6]),
.raw_data(data_buffer_out[5:0]),
.encoded_data(encoded_data),
.full(async_fifo_full)
);
board_level_data_parallel_to_serial_fifo board_level_data_parallel_to_serial_fifo_inst(
.rst(rst),
.wr_clk(clk),
.rd_clk(send_clk),
.din(encoded_data),
.wr_en(1'b1),
.rd_en(1'b1),
.dout(serial_data),
.full(async_fifo_full),
.empty()
);
endmodule
| 8.653905 |
module board_lights (
input i_rstn,
input i_clk,
input [15:0] i_nes_cpu_pc,
input [ 7:0] i_nes_cpu_sp,
input [ 7:0] i_nes_cpu_ir,
input [ 7:0] i_nes_cpu_p,
input i_fl_ry,
input [17:0] i_sw,
output [ 8:0] o_LEDG,
output [17:0] o_LEDR,
output [ 6:0] o_HEX0,
output [ 6:0] o_HEX1,
output [ 6:0] o_HEX2,
output [ 6:0] o_HEX3,
output [ 6:0] o_HEX4,
output [ 6:0] o_HEX5,
output [ 6:0] o_HEX6,
output [ 6:0] o_HEX7
);
assign o_LEDG[7:0] = {
i_nes_cpu_p[0],
i_nes_cpu_p[1],
i_nes_cpu_p[2],
i_nes_cpu_p[3],
i_nes_cpu_p[4],
i_nes_cpu_p[5],
i_nes_cpu_p[6],
i_nes_cpu_p[7]
};
assign o_LEDG[8] = i_fl_ry;
breath_led breath_led (
.i_clk (i_clk),
.i_rstn(i_rstn),
.o_led (o_LEDR[0])
);
assign o_LEDR[17:11] = i_sw[17:11];
hex2sig_rotate sig0 (
.i_hex(i_nes_cpu_pc[15:12]),
.o_sig(o_HEX0)
);
hex2sig_rotate sig1 (
.i_hex(i_nes_cpu_pc[11:8]),
.o_sig(o_HEX1)
);
hex2sig_rotate sig2 (
.i_hex(i_nes_cpu_pc[7:4]),
.o_sig(o_HEX2)
);
hex2sig_rotate sig3 (
.i_hex(i_nes_cpu_pc[3:0]),
.o_sig(o_HEX3)
);
hex2sig_rotate sig4 (
.i_hex(i_nes_cpu_sp[7:4]),
.o_sig(o_HEX4)
);
hex2sig_rotate sig5 (
.i_hex(i_nes_cpu_sp[3:0]),
.o_sig(o_HEX5)
);
hex2sig_rotate sig6 (
.i_hex(i_nes_cpu_ir[7:4]),
.o_sig(o_HEX6)
);
hex2sig_rotate sig7 (
.i_hex(i_nes_cpu_ir[3:0]),
.o_sig(o_HEX7)
);
endmodule
| 6.85712 |
module Board_mem_test(
);
parameter f = 200; //Mhz
parameter PERIOD = 1/(f*0.001);
reg clk = 0;
reg rst = 0;
reg reset_mem = 0;
wire [15:0] placeholderLEDs;
wire [15:0] placeholderSwitches = 16'h1;
Head Head(
.clk (clk ),
.rst_n (rst ),
.boardLEDs (placeholderLEDs),
.boardSwitches(placeholderSwitches)
);
wire [31:0] r0 = Head.RegisterFile.rf[0];
wire [31:0] r1 = Head.RegisterFile.rf[1];
wire [31:0] r2 = Head.RegisterFile.rf[2];
wire [31:0] r3 = Head.RegisterFile.rf[3];
wire [31:0] r4 = Head.RegisterFile.rf[4];
wire [31:0] r5 = Head.RegisterFile.rf[5];
//wire [31:0] r6 = Head.RegisterFile.rf[6];
//wire [31:0] r7 = Head.RegisterFile.rf[7];
//wire [31:0] r8 = Head.RegisterFile.rf[8];
//wire [31:0] r9 = Head.RegisterFile.rf[9];
wire [31:0] r10 = Head.RegisterFile.rf[10];
wire toBranch = Head.Branch_control.bc_out;
wire [31:0]instr_output_load = Head.Instruction.instr_out;
wire [31:0]pc_address_load = Head.ProgramCounter.PC_outputAddress;
wire [31:0]decoded_rd_addr_load = Head.rd_addr;
wire [31:0] rs2_val = Head.RegisterFile.rs2;
wire [31:0] rs1_val = Head.RegisterFile.rs1;
wire [6:0]decoded_opcode_load = Head.Instruction_decode.opcode;
wire [2:0]decoded_funct3 = Head.Instruction_decode.funct;
wire [31:0] dmem_board = Head.data.board;
wire [15:0] led_temp = Head.data.LED_temp;
wire [31:0] alu_out = Head.ALU.alu_out;
wire [31:0] dmem_val_in = Head.data.dmem_in;
wire [31:0] dmem_address = Head.data.addr;
wire [31:0] dmem_switch = Head.data.dmem[16'h100010];
wire [31:0] dmem [1023:0] = Head.data.dmem;
wire [31:0] dmem_led = Head.data.dmem[16'h00100014];
wire [31:0] branchControl_operand1 = Head.Branch_control.operand1;
wire [31:0] branchControl_operand2 = Head.Branch_control.operand2;
wire bc_out = Head.Branch_control.bc_out;
wire [3:0] state = Head.ControlUnit.test_state;
wire PC_we = Head.ControlUnit.PC_we;
wire Instr_rd = Head.ControlUnit.Instr_rd;
wire RegFile_s = Head.ControlUnit.RegFile_s;
wire RegFile_we = Head.ControlUnit.RegFile_we;
//wire Imm_op = Head.ControlUnit.Imm_op
wire ALU_s1 = Head.ControlUnit.ALU_s1;
wire ALU_s2 = Head.ControlUnit.ALU_s2;
wire DataMem_rd = Head.ControlUnit.DataMem_rd;
wire Data_op = Head.ControlUnit.Data_op;
wire Data_s = Head.ControlUnit.Data_s;
wire Bc_Op = Head.ControlUnit.Bc_Op;
wire Data_we = Head.ControlUnit.Data_we;
initial begin
#100
rst = 1;
end
//clk
initial begin
forever #(PERIOD/2) clk=~clk;
end
endmodule
| 6.870513 |
module Branch_control (
branch_info,
PC_s_temp_i_3,
Bc_Op
);
output branch_info;
input PC_s_temp_i_3;
input Bc_Op;
wire Bc_Op;
wire PC_s_temp_i_3;
wire branch_info;
(* XILINX_LEGACY_PRIM = "LD" *) (* XILINX_TRANSFORM_PINMAP = "VCC:GE GND:CLR" *)
LDCE #(
.INIT(1'b0)
) bc_out_reg (
.CLR(1'b0),
.D (PC_s_temp_i_3),
.G (Bc_Op),
.GE (1'b1),
.Q (branch_info)
);
endmodule
| 7.398399 |
module BoardTB;
reg reset;
reg clk;
wire [3:0] oRed; // red signal
wire [3:0] oGreen; // green signal
wire [3:0] oBlue; // blue signal
wire oHs; // Hori sync
wire oVs; // Vert sync
wire cs_n;
reg sdi;
wire sdo;
wire wp_n;
wire hld_n;
GPUBoard gpu_board (
.clk (clk),
.reset(reset),
.cs_n (cs_n),
.sdi (sdi),
.sdo (sdo),
.wp_n (wp_n),
.hld_n(hld_n),
.oRed(oRed),
.oBlue(oBlue),
.oGreen(oGreen),
.oHs(oHs),
.oVs(oVs)
);
initial begin
clk = 0;
forever begin
#5 clk = ~clk;
end
end
// always @(posedge gpu_board.wb_controller.flash.sck) begin
// sdi <= ~sdi;
// end
initial begin
reset = 1;
sdi = 1'b0;
#17 reset = 0;
end
endmodule
| 6.500299 |
module board_terasic (
input CLK,
input [1:0] KEY,
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [1:0] LED
);
localparam CLK_DIV = 26;
wire rst_n = KEY[1];
wire idata = ~KEY[0];
wire [2:0] smile;
wire indicator;
wire strobe;
lab_top #(
.CLK_DIV(CLK_DIV)
) lab_top (
.clk (CLK),
.rst_n (rst_n),
.idata (idata),
.smile (smile),
.indicator(indicator),
.strobe (strobe)
);
hex_smile hex0 (
.smile(smile[0]),
.hex (HEX0)
);
hex_smile hex1 (
.smile(smile[1]),
.hex (HEX1)
);
hex_smile hex2 (
.smile(smile[2]),
.hex (HEX2)
);
assign LED[0] = indicator;
assign LED[1] = idata;
endmodule
| 7.421611 |
module for on-board test
// The rst and start signal is given by memory modules controlled by in memory content editor
//
// Dependency:
// RL_Pipeline_1st_Order.v
//
// Todo:
// Add results storage memory (check Board_Test_Top_RL_LJ_Pipeline_1st_Order.v)
//
// Created by:
// Chen Yang 09/28/18
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
module Board_Test_Top_RL_Pipeline_1st_Order
#(
parameter DATA_WIDTH = 32,
parameter REF_PARTICLE_NUM = 100,
parameter REF_RAM_ADDR_WIDTH = 7, // log(REF_PARTICLE_NUM)
parameter NEIGHBOR_PARTICLE_NUM = 100,
parameter NEIGHBOR_RAM_ADDR_WIDTH= 7, // log(NEIGHBOR_RAM_ADDR_WIDTH)
parameter INTERPOLATION_ORDER = 1,
parameter SEGMENT_NUM = 12,
parameter SEGMENT_WIDTH = 4,
parameter BIN_WIDTH = 8,
parameter BIN_NUM = 256,
parameter LOOKUP_NUM = SEGMENT_NUM * BIN_NUM, // SEGMENT_NUM * BIN_NUM
parameter LOOKUP_ADDR_WIDTH = SEGMENT_WIDTH + BIN_WIDTH // log LOOKUP_NUM / log 2
)
(
input ref_clk,
output [DATA_WIDTH-1:0] forceoutput,
output forceoutput_valid,
output done
);
wire rst;
wire start;
wire clk;
// Input pll
INPUT_PLL INPUT_PLL(
.locked(), // locked.export
.outclk_0(clk), // outclk0.clk
.refclk(ref_clk), // refclk.clk
.rst(rst) // reset.reset
);
// rst signal from Memory content editor
On_Board_Test_Control_RAM_rst CTRL_rst (
.data (), // input, width = 1, ram_input.datain
.address (1'b0), // input, width = 1, .address
.wren (1'b0), // input, width = 1, .wren
.clock (clk), // input, width = 1, .clk
.q (rst) // output, width = 1, ram_output.dataout
);
// Start signal from Memory content editor
On_Board_Test_Control_RAM_start CTRL_start (
.data (), // input, width = 1, ram_input.datain
.address (1'b0), // input, width = 1, .address
.wren (1'b0), // input, width = 1, .wren
.clock (clk), // input, width = 1, .clk
.q (start) // output, width = 1, ram_output.dataout
);
// RL LJ pipeline
RL_Pipeline_1st_Order
#(
.DATA_WIDTH(DATA_WIDTH),
.REF_PARTICLE_NUM(REF_PARTICLE_NUM),
.REF_RAM_ADDR_WIDTH(REF_RAM_ADDR_WIDTH), // log(REF_PARTICLE_NUM)
.NEIGHBOR_PARTICLE_NUM(NEIGHBOR_PARTICLE_NUM),
.NEIGHBOR_RAM_ADDR_WIDTH(NEIGHBOR_RAM_ADDR_WIDTH), // log(NEIGHBOR_RAM_ADDR_WIDTH)
.INTERPOLATION_ORDER(INTERPOLATION_ORDER),
.SEGMENT_NUM(SEGMENT_NUM),
.SEGMENT_WIDTH(SEGMENT_WIDTH),
.BIN_WIDTH(BIN_WIDTH),
.BIN_NUM(BIN_NUM),
.LOOKUP_NUM(LOOKUP_NUM),
.LOOKUP_ADDR_WIDTH(LOOKUP_ADDR_WIDTH)
)
RL_Pipeline_1st_Order
(
.clk(clk),
.rst(rst),
.start(start),
.forceoutput(forceoutput),
.forceoutput_valid(forceoutput_valid),
.done(done)
);
endmodule
| 7.804055 |
module board_top (
input CLK,
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 7:0] HEX0,
output [ 7:0] HEX1,
output [ 7:0] HEX2,
output [ 7:0] HEX3,
output [ 7:0] HEX4,
output [ 7:0] HEX5,
output [ 9:0] LED,
inout [35:0] GPIO
);
wire clk = CLK;
wire rst_n = KEY[0];
wire [ 3:0] row = GPIO[3:0];
wire [ 3:0] clm;
wire [31:0] value;
kb_4x4 kb (
.clk (clk),
.rst_n(rst_n),
.row (row),
.clm (clm),
.value(value)
);
display_driver hex0 (
.dig(value[0+:4]),
.seg(HEX0)
);
display_driver hex1 (
.dig(value[4+:4]),
.seg(HEX1)
);
display_driver hex2 (
.dig(value[8+:4]),
.seg(HEX2)
);
display_driver hex3 (
.dig(value[12+:4]),
.seg(HEX3)
);
display_driver hex4 (
.dig(value[16+:4]),
.seg(HEX4)
);
display_driver hex5 (
.dig(value[20+:4]),
.seg(HEX5)
);
wire [3:0] clm_force_en = SW[4];
wire [3:0] clm_force = SW[3:0];
assign GPIO[7:4] = clm_force_en ? clm_force : clm;
assign LED[3:0] = row;
endmodule
| 7.138663 |
module board_wrapper
(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR,
output [ 7:0] HEX0,
output [ 7:0] HEX1,
output [ 7:0] HEX2,
output [ 7:0] HEX3,
output [ 7:0] HEX4,
output [ 7:0] HEX5,
inout [35:0] GPIO
);
wire fast_clk = MAX10_CLK1_50;
wire rst_n = ~ SW [9];
wire divided_clk, slow_clk;
clk_divider # (.w (24)) i_clk_divider
(
.clk ( fast_clk ),
.rst_n ( rst_n ),
.divided_clk ( divided_clk )
);
global gclk (divided_clk, slow_clk);
wire fast_clk_en;
strobe_generator # (.w (24)) i_strobe_generator
(
.clk ( fast_clk ),
.rst_n ( rst_n ),
.strobe ( fast_clk_en )
);
wire [ 7:0] disp_en;
wire [31:0] disp;
wire [ 7:0] disp_dot;
board_independent_wrapper i_board_independent_wrapper
(
.fast_clk ( fast_clk ),
.slow_clk ( slow_clk ),
.rst_n ( rst_n ),
.fast_clk_en ( fast_clk_en ),
.key ( { 2'b0, ~ KEY [ 1:0] } ),
.sw ( SW [ 7:0] ),
.led ( LEDR [ 7:0] ),
.disp_en ( disp_en [ 7:0] ),
.disp ( disp [31:0] ),
.disp_dot ( disp_dot [ 7:0] )
);
wire unused = ADC_CLK_10
& MAX10_CLK2_50
& SW [8]
& (GPIO == 36'b0);
display_driver i_digit_5 (disp_en [5], disp [23:20], disp_dot [5] , HEX5);
display_driver i_digit_4 (disp_en [4], disp [19:16], disp_dot [4] , HEX4);
display_driver i_digit_3 (disp_en [3], disp [15:12], disp_dot [3] , HEX3);
display_driver i_digit_2 (disp_en [2], disp [11: 8], disp_dot [2] , HEX2);
display_driver i_digit_1 (disp_en [1], disp [ 7: 4], disp_dot [1] , HEX1);
display_driver i_digit_0 (disp_en [0], disp [ 3: 0], disp_dot [0] , HEX0);
endmodule
| 6.837587 |
module BoatA (
Left,
Right,
Reset,
Rand,
Clock,
VGAx,
VGAy,
VGAcol,
Quit
);
input Left;
input Right;
input Reset;
input [15:0] Rand;
input Clock;
output VGAx;
output VGAy;
output VGAcol;
output Quit;
reg [21:0] ticks;
reg [ 2:0] frames;
parameter tperf = 22'd2; //3.125*10^6 ticks per frame - 2 ticks per frame while testing
parameter fperb = 4'b1000; //8 frames per beat
reg [1:0] position; //00:left; 01:centre; 10:right
reg [1:0] direction; //0x:no movement; 10: right; 11: left
reg [5:0] flcrew; //LSB: deck; MSB: water
reg [5:0] mlcrew; //LSB: deck; MSB: water
reg [5:0] mrcrew; //LSB: deck; MSB: water
reg [5:0] frcrew; //LSB: deck; MSB: water
reg [2:0] corpses;
reg [2:0] leftvol; //crew in left boat;
reg [2:0] rightvol; //crew in right boat;
reg [9:0] score;
reg [1:0] lives; //lives used
always @(posedge Clock) begin
if (Reset) begin
ticks = 0;
frames = 0;
position = 1;
direction = 0;
flcrew = 0;
mlcrew = 0;
mrcrew = 0;
frcrew = 0;
corpses = 0;
leftvol = 0;
rightvol = 0;
score = 0;
lives = 0;
end else begin
ticks = ticks + 1;
if (ticks == tperf) begin //every frame
ticks = 0;
frames = frames + 1;
if (direction[1]) begin //if input
if (direction[0] && |position) begin //if left and position != 00
position = position - 1; //move left
end else if (~direction[0] && ~position[1]) begin //if right and position !=10
position = position + 1; //move right
end
direction = 2'b00;
end
if (~|position) begin //empty boat and score
score = score + leftvol;
leftvol = 0;
end else if (position[1]) begin
score = score + rightvol;
rightvol = 0;
end
end
if (frames == fperb) begin //every beat
frames = 0;
corpses = 3'b000;
if (flcrew[5]) begin //if crew about to fall in water
if (position[0] && ~leftvol[2]) begin //if boat under crew && has room
leftvol = leftvol + 1;
end else begin
lives = lives + 1;
corpses = 3'b100;
end
end else if (mlcrew[5]) begin
if (position[1] && ~leftvol[2]) begin
leftvol = leftvol + 1;
end else begin
lives = lives + 1;
corpses = 3'b101;
end
end else if (mrcrew[5]) begin
if (~|position && ~rightvol[2]) begin
rightvol = rightvol + 1;
end else begin
lives = lives + 1;
corpses = 3'b110;
end
end else if (frcrew[5]) begin
if (position[1] && ~rightvol[2]) begin
rightvol = rightvol + 1;
end else begin
lives = lives + 1;
corpses = 3'b111;
end
end
flcrew = flcrew << 1; //move crew
mlcrew = mlcrew << 1;
mrcrew = mrcrew << 1;
frcrew = frcrew << 1;
case (Rand % 4) //add crew
0: flcrew[0] = 1;
1: mlcrew[0] = 1;
2: mrcrew[0] = 1;
3: frcrew[0] = 1;
endcase
end //(frames == fperb)
if (Left && ~Right) begin
direction = 2'b11;
end else if (Right && ~Left) begin
direction = 2'b10;
end
end //always @ (posedge Clock)
end
assign VGAx = 0;
assign VGAy = 0;
assign VGAcol = 0;
assign Quit = 0;
endmodule
| 6.521545 |
module bob_except_ram (
clk,
rst,
read_burst,
read_addr,
read_data,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen,
write2_addr,
write2_data,
write2_wen,
write3_addr,
write3_data,
write3_wen,
write4_addr,
write4_data,
write4_wen,
write5_addr,
write5_data,
write5_wen,
write6_addr,
write6_data,
write6_wen,
write7_addr,
write7_data,
write7_wen,
write8_addr,
write8_data,
write8_wen,
write9_addr,
write9_data,
write9_wen
);
localparam ADDR_WIDTH = 6;
localparam ADDR_COUNT = 64;
parameter DATA_WIDTH = `except_width;
// localparam UNIT=`except_width;
input clk;
input rst;
input read_burst;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
input [ADDR_WIDTH-1:0] write0_addr;
input [DATA_WIDTH-1:0] write0_data;
input write0_wen;
input [ADDR_WIDTH-1:0] write1_addr;
input [DATA_WIDTH-1:0] write1_data;
input write1_wen;
input [ADDR_WIDTH-1:0] write2_addr;
input [DATA_WIDTH-1:0] write2_data;
input write2_wen;
input [ADDR_WIDTH-1:0] write3_addr;
input [DATA_WIDTH-1:0] write3_data;
input write3_wen;
input [ADDR_WIDTH-1:0] write4_addr;
input [DATA_WIDTH-1:0] write4_data;
input write4_wen;
input [ADDR_WIDTH-1:0] write5_addr;
input [DATA_WIDTH-1:0] write5_data;
input write5_wen;
input [ADDR_WIDTH-1:0] write6_addr;
input [DATA_WIDTH-1:0] write6_data;
input write6_wen;
input [ADDR_WIDTH-1:0] write7_addr;
input [DATA_WIDTH-1:0] write7_data;
input write7_wen;
input [ADDR_WIDTH-1:0] write8_addr;
input [DATA_WIDTH-1:0] write8_data;
input write8_wen;
input [ADDR_WIDTH-1:0] write9_addr;
input [DATA_WIDTH-1:0] write9_data;
input write9_wen;
reg [DATA_WIDTH-1:0] ram[ADDR_COUNT-1:0];
reg [ADDR_WIDTH-1:0] read_addr_reg;
assign read_data = ram[read_addr_reg];
always @(posedge clk) begin
if (write0_wen) ram[write0_addr] <= write0_data;
if (write1_wen) ram[write1_addr] <= write1_data;
if (write2_wen) ram[write2_addr] <= write2_data;
if (write3_wen) ram[write3_addr] <= write3_data;
if (write4_wen) ram[write4_addr] <= write4_data;
if (write5_wen) ram[write5_addr] <= write5_data;
if (write6_wen) ram[write6_addr] <= write6_data;
if (write7_wen) ram[write7_addr] <= write7_data;
if (write8_wen) ram[write8_addr] <= write8_data;
if (write9_wen) ram[write9_addr] <= write9_data;
if (read_burst) read_addr_reg <= read_addr;
end
endmodule
| 8.392664 |
module BOBind_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
parameter ADDR_WIDTH = `bob_addr_width;
parameter DATA_WIDTH = 65;
parameter ADDR_COUNT = `bob_count;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
input [ADDR_WIDTH-1:0] write_addr;
input [DATA_WIDTH-1:0] write_data;
input write_wen;
reg [DATA_WIDTH-1:0] ram[ADDR_COUNT-1:0];
reg [ADDR_WIDTH-1:0] read_addr_reg;
assign read_data = ram[read_addr_reg];
always @(posedge clk) begin
if (rst) read_addr_reg <= {ADDR_WIDTH{1'b0}};
else if (read_clkEn) read_addr_reg <= read_addr;
if (write_wen) ram[write_addr] <= write_data;
end
endmodule
| 7.736064 |
module BOBind_ready_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen
);
parameter ADDR_WIDTH = `bob_addr_width;
parameter DATA_WIDTH = 1;
parameter ADDR_COUNT = `bob_count;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
input [ADDR_WIDTH-1:0] write0_addr;
input [DATA_WIDTH-1:0] write0_data;
input write0_wen;
input [ADDR_WIDTH-1:0] write1_addr;
input [DATA_WIDTH-1:0] write1_data;
input write1_wen;
reg [DATA_WIDTH-1:0] ram[ADDR_COUNT-1:0];
reg [ADDR_WIDTH-1:0] read_addr_reg;
assign read_data = ram[read_addr_reg];
always @(posedge clk) begin
if (rst) read_addr_reg <= {ADDR_WIDTH{1'b0}};
else if (read_clkEn) read_addr_reg <= read_addr;
if (write0_wen) ram[write0_addr] <= write0_data;
if (write1_wen) ram[write1_addr] <= write1_data;
end
endmodule
| 8.075629 |
module BOBind (
clk,
rst,
read_clkEn,
read_addr,
read_data,
read_ready,
write_addr,
write_data,
write_wen,
writeI_addr,
writeI_ready,
writeI_wen
);
parameter ADDR_WIDTH = `bob_addr_width;
parameter DATA_WIDTH = 65;
parameter ADDR_COUNT = `bob_count;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_addr;
output [DATA_WIDTH-1:0] read_data;
output read_ready;
input [ADDR_WIDTH-1:0] write_addr;
input [DATA_WIDTH-1:0] write_data;
input write_wen;
input [ADDR_WIDTH-1:0] writeI_addr;
input writeI_ready;
input writeI_wen;
BOBind_ram ram_mod (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
BOBind_ready_ram rdy_mod (
clk,
rst,
read_clkEn,
read_addr,
read_ready,
write_addr,
1'b1,
write_wen,
writeI_addr,
writeI_ready,
writeI_wen
);
endmodule
| 7.745035 |
module BOC_PRN_GEN(rx_clk,rx_rst,rx_prn_fcw,rx_corr_paral,rx_paral_index,
tx_loc_boc,tx_loc_prn,tx_prn_sop,tx_prn_eop,tx_prn_phs,tx_acq_index,tx_phs_acc_reg);
parameter PRN_PHS_WIDTH = 13;
parameter ACC_WIDTH = 32;
input rx_clk,rx_rst;
input[ACC_WIDTH-1:0] rx_prn_fcw;
input[2:0] rx_corr_paral;
input[1:0] rx_paral_index;
output tx_loc_boc,tx_loc_prn;
output tx_prn_sop,tx_prn_eop;
output wire[11:0] tx_prn_phs;
output[11:0] tx_acq_index;
output[31:0] tx_phs_acc_reg;
(*keep="yes"*) reg[11:0] prn_phs;
(*keep="yes"*) reg[11:0] phs_index;
(*keep="yes"*) reg[11:0] acq_index;
(*keep="yes"*) reg[11:0] prn_phs_delay;
(*keep="yes"*) reg[32:0] phs_acc_reg;
(*keep="yes"*) reg[1:0] sub_boc;
assign tx_prn_phs = prn_phs;
assign tx_acq_index = acq_index;
assign tx_loc_boc = tx_loc_prn ^ sub_boc[1];
assign tx_phs_acc_reg = phs_acc_reg[31:0];
(*keep="yes"*) reg phs_acc_reg_delay;
(*keep="yes"*) reg tx_prn_sop,tx_prn_eop;
<<<<<<< HEAD
=======
reg[PRN_PHS_WIDTH-1:0] prn_phs;
reg[ACC_WIDTH-1:0] phs_acc_reg;
assign tx_prn_phs = prn_phs[PRN_PHS_WIDTH-2:0];
assign tx_loc_boc = tx_loc_prn ^ phs_acc_reg[31];
reg phs_acc_reg_delay;
reg tx_prn_sop,tx_prn_eop;
>>>>>>> origin/master
always @(posedge rx_clk) begin
if(rx_rst) begin
phs_acc_reg <= 33'b0;
phs_acc_reg_delay <= 1'b0;
prn_phs <= 12'b0;
tx_prn_sop <= 1'b0;
tx_prn_eop <= 1'b0;
phs_index <= {10'b0,rx_paral_index};
acq_index <= {10'b0,rx_paral_index};
sub_boc <= rx_paral_index;
prn_phs_delay <= 12'd4091;
end
else begin
if(prn_phs==12'd0 && prn_phs_delay==12'd4091)
tx_prn_sop <= 1'b1;
else
tx_prn_sop <= 1'b0;
if(prn_phs==12'd4091 && prn_phs_delay==12'd4090)
tx_prn_eop <= 1'b1;
else
tx_prn_eop <= 1'b0;
prn_phs_delay <= prn_phs;
phs_acc_reg <= phs_acc_reg + rx_prn_fcw;
phs_acc_reg_delay <= phs_acc_reg[ACC_WIDTH-2];
if(phs_acc_reg[32] && rx_corr_paral[2]) begin//acq
if(prn_phs == 12'd4091) begin
prn_phs <= 12'b0;
acq_index <= acq_index + 12'd4;
phs_index <= acq_index + 12'd4;
end
else begin
if(phs_index == 12'd4091) begin
phs_index <= 12'b0;
end
else begin
phs_index <= phs_index + 1;
end
prn_phs <= prn_phs + 1;
end
sub_boc <= sub_boc + 2'd1;
phs_acc_reg[32] <= 1'b0;
end
else if(phs_acc_reg[32] && !rx_corr_paral[2]) begin//trk
if(prn_phs == 12'd4091) begin
prn_phs <= 12'b0;
phs_index <= 12'b0;
end
else begin
phs_index <= phs_index + 1;
prn_phs <= prn_phs + 1;
end
sub_boc <= sub_boc + 2'd1;
phs_acc_reg[32] <= 1'b0;
end
end
end
// 调用ROM IP Core
<<<<<<< HEAD
BOC_PRN_ROM BOC_PRN( .A(phs_index), .SPO(tx_loc_prn));
=======
BOC_PRN_ROM BOC_PRN( .A(phs_acc_reg[31:18]), .SPO(tx_loc_prn));
>>>>>>> origin/master
endmodule
| 6.857753 |
module bol_44 (
input [5:0] io_dip,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
always @* begin
out = 1'h0;
case (io_dip[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
3'h6: begin
out = a ^ b;
end
4'ha: begin
out = a;
end
endcase
end
endmodule
| 7.031366 |
module bomb( rst, clk, frame_end, min, x, y, bullet_x, bullet_y, char_y, en, game_over);
parameter START = 4;
parameter MAXV = 480;
parameter MAXH = 640;
parameter NUM_BULLETS = 10;
//parameter MINX = 40;
//parameter MAXX = 550;
input clk, frame_end, rst;
input [11*NUM_BULLETS-1:0] min;
input [11*NUM_BULLETS-1:0] bullet_x, bullet_y;
input [11*NUM_BULLETS-1:0] char_y;
output reg [10:0] x;
output reg [10:0] y;
output en;
output reg game_over;
//output reg [11:0] color;
localparam BWIDTH = 16;
localparam BHEIGHT = 24;
localparam CHAR_X = 550;
localparam CHARH = 44;
localparam CHARW = 40;
//`include "bl_colors.vh"
reg [31:0] frame_count;
wire [10:0] x_loc;
wire mov_en, change_x;
wire [10:0] x_loc_range;
reg [NUM_BULLETS-1:0] en_r;
reg h_en;
LFSR lfsr
(.i_Clk(clk),
.i_Enable(1'b1),
.i_Seed_DV(1'b0),
.i_Seed_Data(START), // Replication
.o_LFSR_Data(x_loc),
.o_LFSR_Done()
);
//always@(posedge clk) begin
// if (frame_count >= START) begin
// mov_en <= 1;
// end
// else begin
// mov_en <= 0;
// end
//end
// For checking whether the bomb hit the char and drive killed
always@(posedge clk) begin
if (rst)
game_over <= 0;
else if (game_over)
game_over <= 1;
else if (h_en & x+BWIDTH>=CHAR_X & x<CHAR_X+CHARW & y+BHEIGHT > char_y & y < char_y + CHARH)
game_over <= 1;
end
assign mov_en = (frame_count >= START) ? 1'b1 : 1'b0;
assign change_x = (y==MAXV) ? 1'b1 : 1'b0;
assign x_loc_range = (x_loc < 510) ? x_loc : (x_loc%510);
always@(posedge clk) begin
if (rst) begin
frame_count <= 0;
x <= x_loc_range;
y <= -11'd20;
h_en <= 0;
end
else if (game_over) begin
frame_count <= frame_count;
x <= x;
y <= y;
end
else if (frame_end) begin
frame_count <= frame_count + 1;
x <= x;
if (mov_en & ~en & x<MAXH+BWIDTH+10) begin
x <= x + 5;
h_en <= 1;
end else if (mov_en & h_en & x>=MAXH+BWIDTH) begin
y <= MAXV;
h_en <= 0;
end else if (mov_en & h_en & x<MAXH+BWIDTH+10)
x <= x + 5;
else if (mov_en)
y <= y + 1;
else
y <= y;
end
else if (change_x) begin
frame_count <= frame_count;
x <= x_loc_range;
y <= y;
end
else if (y==MAXV+20) begin
frame_count <= frame_count;
x <= x;
y <= -11'd20;
end
else if (~mov_en) begin
frame_count <= frame_count;
y <= y;
x <= x_loc_range;
end
// else if (mov_en) begin
// frame_count <= frame_count;
// x <= x;
// y <= y - 1;
// end
else begin
frame_count <= frame_count;
x <= x;
y <= y;
end
end
genvar i;
// collision detect
generate
for (i=0; i<NUM_BULLETS; i=i+1) begin
always@(posedge clk) begin
if (rst) begin
en_r[i] <= 1;
end
else if ((bullet_x[((i+1)*11)-1:i*11] > x) & (bullet_x[((i+1)*11)-1:i*11] < x+BWIDTH) & (bullet_y[((i+1)*11)-1:i*11] > y-10) & (bullet_y[((i+1)*11)-1:i*11] < y+BHEIGHT) & (en)) begin
en_r[i] <= 0;
end
else if (~en & y==-11'd20) begin
en_r[i] <= 1;
end
else begin
en_r[i] <= en_r[i];
end
end
end
endgenerate
assign en = &en_r;
//reg [2:0] count = 0;
//wire in_balloon;
//assign en = (cx-x)*(cx-x) + (cy-y)*(cy-y) < RAD;
//always@(cy)
// if (cy==0) begin
// count = count + 1;
// color = colors[count];
// end
//assign r = color[11:8];
//assign g = color[7:4];
//assign b = color[3:0];
endmodule
| 7.41975 |
module lab6_part2 (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
wire resetn;
assign resetn = KEY[0];
// Create the colour, x, y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
//.colour(colour),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "black.mif";
// Put your code here. Your code should produce signals x,y,colour and writeEn/plot
// for the VGA controller, in addition to any other functionality your design may require.
// Instansiate datapath
datapath d0 (
.input_colour(SW[9:7]),
.coords(SW[6:0]),
.xOffset(xoffset),
.yOffset(yoffset),
.resetn(KEY[0]),
.saveX(KEY[3]),
.finalX(x),
.finalY(y),
.output_colour(colour)
);
wire [1:0] xoffset, yoffset;
// Instansiate FSM control
control c0 (
.clk(CLOCK_50),
.go(!KEY[1]),
.resetn(KEY[0]),
.xOffset(xoffset),
.yOffset(yoffset),
.plot(writeEn)
);
endmodule
| 8.313762 |
module datapath (
input [2:0] input_colour,
input [6:0] coords,
input [1:0] xOffset,
input [1:0] yOffset,
input resetn,
input saveX,
output [7:0] finalX,
output [6:0] finalY,
output [2:0] output_colour
);
// setup x coordinate
reg [7:0] x_coordinate;
always @(posedge saveX) begin
x_coordinate <= {1'b0, coords};
end
assign finalY = {coords + yOffset};
assign finalX = {x_coordinate + xOffset};
// set color
assign output_colour = input_colour[2:0];
endmodule
| 6.91752 |
module control (
input clk,
input resetn,
input go,
output reg [1:0] xOffset,
output reg [1:0] yOffset,
output plot
);
reg [5:0] current_state, next_state;
localparam P1 = 5'd0,
P2 = 5'd1,
P3 = 5'd2,
P4 = 5'd3,
P5 = 5'd4,
P6 = 5'd5,
P7 = 5'd6,
P8 = 5'd7,
P9 = 5'd8,
P10 = 5'd9,
P11 = 5'd10,
P12 = 5'd11,
P13 = 5'd12,
P14 = 5'd13,
P15 = 5'd14,
P16 = 5'd15,
RESTING = 5'd16;
always @(posedge clk) begin : state_table
case (current_state)
P1: next_state = P2;
P2: next_state = P3;
P3: next_state = P4;
P4: next_state = P5;
P5: next_state = P6;
P6: next_state = P7;
P7: next_state = P8;
P8: next_state = P9;
P9: next_state = P10;
P10: next_state = P11;
P11: next_state = P12;
P12: next_state = P13;
P13: next_state = P14;
P14: next_state = P15;
P15: next_state = P16;
P16: next_state = RESTING;
RESTING: next_state = go ? P1 : RESTING;
default: next_state = RESTING;
endcase
end
// plot
assign plot = (current_state != RESTING);
// assign offset
always @(*) begin : make_output
case (current_state)
P1: begin
xOffset <= 2'b00;
yOffset <= 2'b00;
end
P2: begin
xOffset <= 2'b01;
yOffset <= 2'b00;
end
P3: begin
xOffset <= 2'b10;
yOffset <= 2'b00;
end
P4: begin
xOffset <= 2'b11;
yOffset <= 2'b00;
end
P5: begin
xOffset <= 2'b00;
yOffset <= 2'b01;
end
P6: begin
xOffset <= 2'b01;
yOffset <= 2'b01;
end
P7: begin
xOffset <= 2'b10;
yOffset <= 2'b01;
end
P8: begin
xOffset <= 2'b11;
yOffset <= 2'b01;
end
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY, P9: begin
xOffset <= 2'b00;
yOffset <= 2'b10;
end
P10: begin
xOffset <= 2'b01;
yOffset <= 2'b10;
end
P11: begin
xOffset <= 2'b10;
yOffset <= 2'b10;
end
P12: begin
xOffset <= 2'b11;
yOffset <= 2'b10;
end
P13: begin
xOffset <= 2'b00;
yOffset <= 2'b11;
end
P14: begin
xOffset <= 2'b01;
yOffset <= 2'b11;
end
P15: begin
xOffset <= 2'b10;
yOffset <= 2'b11;
end
P16: begin
xOffset <= 2'b11;
yOffset <= 2'b11;
end
default: begin
xOffset <= 2'b00;
yOffset <= 2'b00;
end
endcase
end
always @(posedge clk) begin : state_FFs
if (!resetn) // goto resting if reset
current_state <= RESTING;
else current_state <= next_state;
end
endmodule
| 7.715617 |
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