code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bm_functional_test (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
counter
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`... | 7.525302 |
module bm_function_2 (
clock,
reset_n,
a,
b,
c,
d,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a;
input [`BITS-1:0] b;
input c;
input d;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
wire out1;
... | 6.647281 |
module bm_if_collapse (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out2,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output [`BITS-1:0] out2;
outp... | 7.300585 |
module a (
clock,
a_in,
b_in,
out
);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
always @(posedge clock) begin
case (a_in)
2'b00: begin
if (b_in != 2'b01) begin
... | 6.866335 |
module bm_if_common (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out2,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output [`BITS-1:0] out2;
output... | 7.288545 |
module a (
clock,
a_in,
out
);
input clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
always @(posedge clock) begin
case (a_in)
2'b00: out2 <= 2'b11;
2'b01: out1 <= 2'b10;
2'b10: out1 <= 2'b01;
... | 6.866335 |
module bm_if_reset (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg... | 7.609874 |
module a (
clock,
a_in,
out
);
input clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
always @(posedge clock) begin
case (a_in)
2'b00: out <= 2'b11;
2'b01: out <= 2'b10;
2'b10: out <= 2'b01;
2'b11: out <= 2'b00;
endcase
end
endmodule
... | 6.866335 |
module defines a J-K flip flop with an
// asynchronous, active low reset.
//
/*********************************************************/
// DEFINES
`define DEL 1 // Clock-to-output delay. Zero
// time delays can be confusing
// and sometimes cause problems.
// TOP MODULE
module bm_jk_rtl(
clk,
clr_n,
... | 8.138493 |
module bm_log_all(clock,
reset_n,
a,
b,
out1,
out2,
out3,
out4,
out5,
out6,
out7,
out8,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a;
input [`BITS-1:0] b;
output [`BITS-1:0] out1;
output [`BITS-1:0] out2;
output [`BITS-1:0] out3;
output [`BITS-1:0] out4;
outpu... | 7.299691 |
module bm_lpm_all(clock,
reset_n,
a,
b,
out1,
out2,
out3,
out4,
out5,
out6,
out7,
out8,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a;
input [`BITS-1:0] b;
output [`BITS-1:0] out1;
output [`BITS-1:0] out2;
output [`BITS-1:0] out3;
output [`BITS-1:0] out4;
outpu... | 7.718448 |
module bm_lpm_concat(clock,
reset_n,
a,
b,
out1,
out2,
out3,
out4,
out5,
out6,
out7,
out8,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-9:0] a;
input [`BITS-9:0] b;
output [`BITS-8:0] out1;
output [`BITS-7:0] out2;
output [`BITS-6:0] out3;
output [`BITS-5:0] out4;
ou... | 7.870522 |
module bm_match1_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
out4,
out5,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS1-1:0] c_in;
input [`BITS1-1:0] d_in;
input [`BITS2-1... | 6.849518 |
module bm_match2_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
out4,
out5,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1... | 6.894027 |
module bm_match3_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1:0] e_in;
input ... | 6.777051 |
module bm_match4_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
out3,
out4,
out5,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS1-1:0] d_in;
input [`BITS1-1... | 6.655997 |
module bm_match6_str_arch(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out1,
out2,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS0-1:0] a_in;
input [`BITS0-1:0] b_in;
input [`BITS0-1:0] c_in;
input [`BITS0-1:0] d_in;
input [`BITS0-1:0] e_in;
input [`BITS0-... | 6.986806 |
module bm_mod (
clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out1
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output out1;
reg [`BITS-1:0] out0;
reg ... | 7.263377 |
module bm_rng (
reset,
clk,
seed_0,
seed_1,
seed_2,
seed_3,
seed_4,
seed_5,
scan_in0,
scan_en,
test_mode,
scan_out0,
x0_out,
x1_out,
valid
);
input reset, // system reset
clk; // system clock
input scan_in0, // test scan mode data input
scan_en, ... | 6.757165 |
module defines a Synchronous FIFO. The
// FIFO memory is implemented as a ring buffer. The read
// pointer points to the beginning of the buffer, while the
// write pointer points to the end of the buffer. Note that
// in this RTL version, the memory has one more location than
// the FIFO needs in order to calculate th... | 7.908588 |
module bm_simple_memory (
clock,
reset_n,
value_out,
value_in
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] value_in;
output [`BITS-1:0] value_out;
wire [`BITS-1:0] value_out;
reg [`BITS-1:0] memory [3:0]; // 4 memory slots of Bits wide
reg [1:0] address_c... | 6.730904 |
module bm_stmt_all_mod (
clock,
reset_n,
a_in,
b_in,
out1,
out0,
out3,
out4,
out5,
out6,
out7,
out8,
out10,
out9
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
output [`BITS-1:0] out0;
output out1;
outp... | 6.518082 |
module bm_stmt_compare_padding(clock,
reset_n,
a_in,
b_in,
out1,
out0,
out5,
out6,
out7,
out8,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
output [`BITS-1:0] out0;
output out1;
output out5;
output [`BITS-1:0] out6;
output out7;
output [`BITS-... | 7.942505 |
module bm_tester(clock,
reset_n,
a_in,
b_in,
out0,
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input b_in;
output [`BITS-1:0] out0;
reg [`BITS-1:0] out0;
always @(posedge clock)
begin
case (a_in)
4'b0000: out0 <= 4'b1111 ;
4'b0001: out0 <= 4'b1110 ;
4'b00... | 7.509721 |
module BNE (
Op,
Y
);
input wire [31:26] Op;
output wire Y;
wire NOTOp27;
wire NOTOp29;
wire NOTOp30;
wire NOTOp31;
assign Y = NOTOp29 & NOTOp31 & NOTOp30 & Op[28] & NOTOp27 & Op[26];
assign NOTOp30 = ~Op[30];
assign NOTOp29 = ~Op[29];
assign NOTOp27 = ~Op[27];
assign NOTOp31 = ... | 6.590881 |
module bnn_cfg (
//common interface
input wire clk,
rst_n,
vad_duration,
//bnn interface
output reg [15:0] conv_wt1[ 4:0],
output reg [15:0] conv_wt2[ 4:0],
output reg [15:0] conv_wt3[ 4:0],
output reg [ 2:0] fc_wt1 [107:0],
output reg [ 2:0] fc_wt1 [107:0],
output reg... | 7.722579 |
module bnn_conv (
input wire clk,
rst_n,
input wire [15:0] data_in[1:5], //输入的一帧数据 5 位
input wire conv_en,
output reg conv_vld,
output reg [31:0] conv_out[1:3] , //卷积一次输入，每一位为一个kernel和一帧输入的运算结果
output wire conv_done //conv整个（6帧，6x20）运算结束，目前应该没用到……
);
reg [15:0] weight1[1:5];
... | 7.637088 |
module bn_addr_gen_Add3u16Cati0u16u32_1 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3;
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [17:0] asc002;
assign asc002 = {in2, 2'B00};
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) +... | 6.554738 |
module bn_addr_gen_Add3u16Cati0u16u32_4 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3;
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [17:0] asc002;
assign asc002 = {in2, 2'B00};
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3) +... | 6.554738 |
module bn_addr_gen_Add3u16Cati0u16u32_4_0 (
in3,
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in3;
input [15:0] in2, in1;
output [31:0] out1;
wire [31:0] asc001;
wire [17:0] asc002;
assign asc002 = {in2, 2'B00};
wire [31:0] asc001_tmp_0;
assign asc001_tmp_0 = +(in3)... | 6.554738 |
module bn_addr_gen_Add_32Ux18U_32U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [17:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Add_32Ux18U_32U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [17:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Add_32Ux18U_32U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input [17:0] in1;
output [31:0] out1;
wire [31:0] asc001;
assign asc001 = +(in2) + (in1);
assign out1 = asc001;
endmodule
| 6.554738 |
module bn_addr_gen_Eqi1u8_1 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (13'B0000000000001 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi1u8_4 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (13'B0000000000001 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi1u8_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [7:0] in1;
output out1;
wire asc001;
assign asc001 = (13'B0000000000001 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi3u16_1 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (21'B000000000000000000011 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi3u16_4 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (21'B000000000000000000011 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Eqi3u16_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [15:0] in1;
output out1;
wire asc001;
assign asc001 = (21'B000000000000000000011 == in1);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_16Ux2U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_16Ux2U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_16Ux2U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [15:0] in2;
input [1:0] in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_8Ux1U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_8Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_Equal_8Ux1U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [7:0] in2;
input in1;
output out1;
wire asc001;
assign asc001 = (in1 == in2);
assign out1 = asc001;
endmodule
| 6.989264 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32i0u1_1 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wire [31:0] asc00... | 6.768275 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32i0u1_4 (
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wire [31:0] asc00... | 6.768275 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32u32u1_1 (
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in5, in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wi... | 6.768275 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32u32u1_4 (
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in5, in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
wi... | 6.768275 |
module bn_addr_gen_MuxAdd3u16Cati0u16u32u32u1_4_0 (
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in5, in4;
input [15:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
wire [17:0] asc003;
assign asc003 = {in3, 2'B00};
... | 6.768275 |
module bn_addr_gen_N_Mux_1_2_7_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
def... | 7.563142 |
module bn_addr_gen_N_Mux_1_2_7_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
def... | 7.563142 |
module bn_addr_gen_N_Mux_1_2_7_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
d... | 7.563142 |
module bn_addr_gen_N_Mux_32_2_12_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in... | 7.563142 |
module bn_addr_gen_N_Mux_32_2_12_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in... | 7.563142 |
module bn_addr_gen_Or_1U_2_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.974538 |
module bn_addr_gen_Or_1U_3_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.974538 |
module for the bn_addr_gen module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
*************... | 7.62099 |
module bn_bias_relu (
clk,
rst,
acc_in,
op_bias,
op_dout
);
//========================================
//parameter define
//========================================
parameter RELU = 0;
parameter Q = 8;
parameter DIN_Q = 6;
parameter DOUT_DW = 16;
parameter DO... | 6.654781 |
module bN_demux_1_4_case #(
parameter DATA_WIDTH = 2
) (
input [DATA_WIDTH-1:0] din,
input [ 1:0] sel,
output reg [DATA_WIDTH-1:0] dout0,
output reg [DATA_WIDTH-1:0] dout1,
output reg [DATA_WIDTH-1:0] dout2,
output reg [DATA_WIDTH-1:0] dout3
);
localparam ZEROS = {DATA_... | 7.518217 |
module bn_float32_DECODE_2U_1_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output [1:0] out1;
wire [1:0] asc001;
assign asc001 = 2'B01 << in1;
assign out1 = asc001;
endmodule
| 7.338402 |
module bn_float32_N_Muxb_1_2_0_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
def... | 6.605837 |
module bn_float32_N_Muxb_1_2_0_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
d... | 6.605837 |
module bn_float32_N_Muxb_1_2_0_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
d... | 6.605837 |
module bn_float32_N_Muxb_1_2_0_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = in2;
d... | 6.605837 |
module bn_mux_n_1_generate #(
parameter DATA_WIDTH = 8,
parameter SEL_WIDTH = 2
) (
input [((2**SEL_WIDTH)*DATA_WIDTH)-1:0] data,
input [ SEL_WIDTH-1:0] sel,
output [ DATA_WIDTH-1:0] y
);
wire [DATA_WIDTH-1:0] tmp_array[0:(2**SEL_WIDTH)-1];
genvar i;
generat... | 8.486591 |
module board;
parameter REF_CLK_FREQ = 0; // 0 - 100 MHz, 1 - 250 MHz
localparam REF_CLK_HALF_CYCLE = (REF_CLK_FREQ == 0) ? 5000 : (REF_CLK_FREQ == 1) ? 2000 : 0;
integer i;
//
// System reset
//
reg cor_sys_reset_n;
//
// System clock
//
wire rp_... | 6.620881 |
module Board02 (
input wire SYSCLK, //16.384MHz-主时钟
input wire MRESET, //reset
output wire RUN, //run_led
//UART interface
input wire U3TXD, //UART_R
output wire U3RXD, //UART_T
//
output wire PN, //2P01
output wire DPN, //2P02
output wire PNCLK, //2P03
... | 7.126778 |
module binary_to_BCD (
A,
ONES,
TENS,
HUNDREDS
);
input [7:0] A;
output [3:0] ONES, TENS, HUNDREDS;
wire [3:0] c1, c2, c3, c4, c5, c6, c7;
wire [3:0] d1, d2, d3, d4, d5, d6, d7;
assign d1 = {1'b0, A[7:5]};
assign d2 = {c1[2:0], A[4]};
assign d3 = {c2[2:0], A[3]};
assign d4 = {c3[2:0], A[... | 7.621619 |
module binary_to_BCD_add3 (
in,
out
);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @(in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
... | 7.621619 |
module board2board_switching_wrapper #(
parameter DATA_WIDTH = 65,
parameter TOTAL_CLUSTERS = 4,
parameter TOTAL_OUTPUT_BOARDS = 14,
parameter FIFO_DEPTH_BITS = 6,
parameter BOARD_ID = 0
) (
b2b_clk,
b2b_rst_n,
b2b_srst_n,
cluster_data,
cluster_req,
cluster_almost_full,
c... | 9.11298 |
module boardRam (
data,
clk,
wren,
q
);
output [79:0] q;
input wren, clk;
input [79:0] data;
reg [79:0] q;
always @(posedge clk) begin
if (wren) q <= data;
end
endmodule
| 7.152651 |
module BoardTimerModule_TopLevel (
// [BEGIN USER PORTS]
// [END USER PORTS]
input wire Clock,
input wire Reset,
input wire Restart,
output wire OutActive10,
output wire OutActive20
);
// [BEGIN USER SIGNALS]
// [END USER SIGNALS]
localparam HiSignal = 1'b1;
localparam LoSignal ... | 6.824355 |
module board_digilent (
input CLK,
input [1:0] KEY,
output [7:0] HEX,
output [7:0] AN,
output [1:0] LED
);
localparam CLK_DIV = 26;
wire rst_n = ~KEY[1];
wire idata = KEY[0];
wire [2:0] smile;
wire indicator;
wire strobe;
lab_top #(
.CLK_DIV(CLK_... | 7.587034 |
module board_disp (
input CLK100MHZ,
input [16:0] data,
input [9:0] cx,
input [9:0] cy,
input pix_stb,
output reg [11:0] VGA_color = 0,
output [1:0] row,
output [1:0] col,
output draw
);
wire [11:0] board_color;
wire [11:0] row1_color;
wire [11:0] row2_color;
wire [11:0] row... | 6.548299 |
module board_disp_sword (
input wire clk, // main clock
input wire rst, // synchronous reset
input wire [7:0] en, // enable for each tube
input wire mode, // 0 for text mode, 1 for graphic mode
input wire [31:0] data_text, // text data to display
input wire [63:0] data_graphic, // graphic ... | 7.469975 |
module board_id_generator (
input wire clock,
input wire reset,
output reg ready = 1'b0,
output reg [31:0] board_identifier = 32'b0
);
wire dout;
reg read_en = 1'b0;
reg shift_en = 1'b0;
reg [56:0] shift_data = 57'b0;
reg [5:0] shift_count = 6'b0;
reg [5:0] slow_counter = 6'b0;
DNA_PORT... | 6.810783 |
module board_independent_wrapper (
input fast_clk,
input slow_clk,
input rst_n,
input fast_clk_en,
input [ 3:0] key,
input [ 7:0] sw,
output [ 7:0] led,
output [ 7:0] disp_en,
output [31:0] disp,
output [ 7:0] disp_dot
);
wire [ 4:0] res_vld;
... | 7.34689 |
module implements conversation from control signals and raw data
// to encoded_data that is 6b/8b code.
// frame_start: 00000001
// frame_end: 00000010
// data: xxxxxx11
//
// Dependencies:
// <None>
//
// Revision: 1.0
//
// Parameters:
// <None>
//
// Inputs:
// clk - system clock.
// rst - reset.
... | 6.733875 |
module implements conversation to control signals and raw data
// from encoded_data that is 6b/8b code.
// frame_start: 00000001
// frame_end: 00000010
// data: xxxxxx11
//
// Dependencies:
// <None>
//
// Revision: 1.0
//
// Parameters:
// <None>
//
// Inputs:
// clk - system clock.
// r... | 6.733875 |
module implements data transmission physical level.
//
// Dependencies:
// board_level_data_transmitter_physical_buffer(8-bit sync fifo with 16-depth)
// board_level_data_physical_encoder.v
// board_level_data_parallel_to_serial_fifo(8-bit to 1-bit async fifo with
// 16-depth)
//
// Revision: 1.0
//
// Parameters:
// ... | 8.653905 |
module board_lights (
input i_rstn,
input i_clk,
input [15:0] i_nes_cpu_pc,
input [ 7:0] i_nes_cpu_sp,
input [ 7:0] i_nes_cpu_ir,
input [ 7:0] i_nes_cpu_p,
input i_fl_ry,
input [17:0] i_sw,
output [ 8:0] o_LEDG,
output [17:0] o_LEDR,
output [ 6:0]... | 6.85712 |
module Board_mem_test(
);
parameter f = 200; //Mhz
parameter PERIOD = 1/(f*0.001);
reg clk = 0;
reg rst = 0;
reg reset_mem = 0;
wire [15:0] placeholderLEDs;
wire [15:0] placeholderSwitches = 16'h1;
Head Head(
.clk (clk ),
.rst_n (rst ),
.boardLEDs (placeholde... | 6.870513 |
module Branch_control (
branch_info,
PC_s_temp_i_3,
Bc_Op
);
output branch_info;
input PC_s_temp_i_3;
input Bc_Op;
wire Bc_Op;
wire PC_s_temp_i_3;
wire branch_info;
(* XILINX_LEGACY_PRIM = "LD" *) (* XILINX_TRANSFORM_PINMAP = "VCC:GE GND:CLR" *)
LDCE #(
.INIT(1'b0)
) bc_out_reg (
... | 7.398399 |
module BoardTB;
reg reset;
reg clk;
wire [3:0] oRed; // red signal
wire [3:0] oGreen; // green signal
wire [3:0] oBlue; // blue signal
wire oHs; // Hori sync
wire oVs; // Vert sync
wire cs_n;
reg sdi;
wire sdo;
wire wp_n;
wire hld_n;
GPUBoard gpu_board (
.clk (clk),
.rese... | 6.500299 |
module board_terasic (
input CLK,
input [1:0] KEY,
output [7:0] HEX0,
output [7:0] HEX1,
output [7:0] HEX2,
output [1:0] LED
);
localparam CLK_DIV = 26;
wire rst_n = KEY[1];
wire idata = ~KEY[0];
wire [2:0] smile;
wire indicator;
wire strobe;
lab_t... | 7.421611 |
module for on-board test
// The rst and start signal is given by memory modules controlled by in memory content editor
//
// Dependency:
// RL_Pipeline_1st_Order.v
//
// Todo:
// Add results storage memory (check Board_Test_Top_RL_LJ_Pipeline_1st_Order.v)
//
// Created by:
// Chen Yang 09/28/18
/////////////... | 7.804055 |
module board_top (
input CLK,
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 7:0] HEX0,
output [ 7:0] HEX1,
output [ 7:0] HEX2,
output [ 7:0] HEX3,
output [ 7:0] HEX4,
output [ 7:0] HEX5,
output [ 9:0] LED,
inout [35:0] GPIO
);
wire clk = CLK;
wire r... | 7.138663 |
module board_wrapper
(
input ADC_CLK_10,
input MAX10_CLK1_50,
input MAX10_CLK2_50,
input [ 1:0] KEY,
input [ 9:0] SW,
output [ 9:0] LEDR,
output [ 7:0] HEX0,
output [ 7:0] HEX1,
output [ 7:0] HEX2,
output [ 7:0] HEX3,
output [ 7:0] HEX4,
outpu... | 6.837587 |
module BoatA (
Left,
Right,
Reset,
Rand,
Clock,
VGAx,
VGAy,
VGAcol,
Quit
);
input Left;
input Right;
input Reset;
input [15:0] Rand;
input Clock;
output VGAx;
output VGAy;
output VGAcol;
output Quit;
reg [21:0] ticks;
reg [ 2:0] frames;
parameter tperf = 22... | 6.521545 |
module bob_except_ram (
clk,
rst,
read_burst,
read_addr,
read_data,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen,
write2_addr,
write2_data,
write2_wen,
write3_addr,
write3_data,
write3_wen,
write4_addr,
write4_dat... | 8.392664 |
module BOBind_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write_addr,
write_data,
write_wen
);
parameter ADDR_WIDTH = `bob_addr_width;
parameter DATA_WIDTH = 65;
parameter ADDR_COUNT = `bob_count;
input clk;
input rst;
input read_clkEn;
input [ADDR_WIDTH-1:0] read_a... | 7.736064 |
module BOBind_ready_ram (
clk,
rst,
read_clkEn,
read_addr,
read_data,
write0_addr,
write0_data,
write0_wen,
write1_addr,
write1_data,
write1_wen
);
parameter ADDR_WIDTH = `bob_addr_width;
parameter DATA_WIDTH = 1;
parameter ADDR_COUNT = `bob_count;
input clk;
inpu... | 8.075629 |
module BOBind (
clk,
rst,
read_clkEn,
read_addr,
read_data,
read_ready,
write_addr,
write_data,
write_wen,
writeI_addr,
writeI_ready,
writeI_wen
);
parameter ADDR_WIDTH = `bob_addr_width;
parameter DATA_WIDTH = 65;
parameter ADDR_COUNT = `bob_count;
input clk;
... | 7.745035 |
module BOC_PRN_GEN(rx_clk,rx_rst,rx_prn_fcw,rx_corr_paral,rx_paral_index,
tx_loc_boc,tx_loc_prn,tx_prn_sop,tx_prn_eop,tx_prn_phs,tx_acq_index,tx_phs_acc_reg);
parameter PRN_PHS_WIDTH = 13;
parameter ACC_WIDTH = 32;
input rx_clk,rx_rst;
input[ACC_WIDTH-1:0] rx_prn_fcw;
input[2:0] rx_corr_paral;
input[1:0] rx_paral_... | 6.857753 |
module bol_44 (
input [5:0] io_dip,
input [15:0] a,
input [15:0] b,
output reg [15:0] out
);
always @* begin
out = 1'h0;
case (io_dip[0+3-:4])
4'h8: begin
out = a & b;
end
4'he: begin
out = a | b;
end
3'h6: begin
out = a ^ b;
end
... | 7.031366 |
module bomb( rst, clk, frame_end, min, x, y, bullet_x, bullet_y, char_y, en, game_over);
parameter START = 4;
parameter MAXV = 480;
parameter MAXH = 640;
parameter NUM_BULLETS = 10;
//parameter MINX = 40;
//parameter MAXX = 550;
input clk, frame_end, rst;
input [11*NUM_BULLETS-1:0] min;
input [11*NUM_BULLETS-1:0] bul... | 7.41975 |
module lab6_part2 (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
SW,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R... | 8.313762 |
module datapath (
input [2:0] input_colour,
input [6:0] coords,
input [1:0] xOffset,
input [1:0] yOffset,
input resetn,
input saveX,
output [7:0] finalX,
output [6:0] finalY,
output [2:0] output_colour
);
// setup x coordinate
reg [7:0] x_coordinate;
always @(posedge saveX) b... | 6.91752 |
module control (
input clk,
input resetn,
input go,
output reg [1:0] xOffset,
output reg [1:0] yOffset,
output plot
);
reg [5:0] current_state, next_state;
localparam P1 = 5'd0,
P2 = 5'd1,
P3 = 5'd2,
P4 = 5'd3,
P5 = 5'd4,
P6 = 5'd5,
P... | 7.715617 |
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