code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module BoothMultipilcation (
clk,
X,
Y,
Z
);
input clk;
input signed [31:0] X, Y;
output signed [63:0] Z;
reg signed [63:0] Z;
reg [1:0] temp; // for 01 or 10
integer i;
reg E1;
reg [31:0] Y1;
always @(X, Y) begin
Z = 64'd0;
E1 = 1'd0;
for (i = 0; i < 32; i = i + ... | 6.92481 |
module BoothMultiplication_tb;
// Inputs
reg clk;
reg [31:0] Multiplicand;
reg [31:0] Multiplier;
reg run;
// Outputs
wire isValid;
wire [63:0] result;
// Instantiate the Unit Under Test (UUT)
BoothMultipilcation uut (
.clk(clk),
.Multiplicand(Multiplicand),
.Multiplier(Multipli... | 7.014879 |
module BoothMultiplier (
input clk,
rst,
input [4:0] cand,
ier,
output [10:0] R,
output valid
);
reg [4:0] AC = 0, QR = 0;
reg [2:0] counter = 6;
reg Qn = 0, sh_en = 0, op_en = 0;
wire [ 1:0] op;
reg [ 1:0] opr;
wire [10:0] all;
ControlUnit(
QR[0], Qn, op_en, op
); Shifter... | 7.014879 |
module boothPP #(
parameter WIDTH = 14
) (
input [WIDTH-1:0] in,
output [ WIDTH:0] out_in,
output [ WIDTH:0] out_in_n,
output [ WIDTH:0] out_in_2,
output [ WIDTH:0] out_in_2n,
output [ WIDTH:0] out_zero
);
wire [WIDTH:0] onesComp; // One's Comp
// +1 needs to be compensated in PP... | 7.890708 |
module boothPPCal #(
parameter WIDTH = 14
) (
input [WIDTH:0] pp,
input [WIDTH:0] pp_n,
input [WIDTH:0] pp_2,
input [WIDTH:0] pp_2n,
input [WIDTH:0] pp_zero,
input [ 2:0] booth,
output comp,
output [WIDTH:0] out
);
wire single_pp, double_pp, neg_pp;
boothEnc ... | 7.433765 |
module boothPPCal_tb;
parameter WIDTH = 14; // For 16 bit WIDTH = 16
// Inputs
reg [WIDTH-1:0] multiplier;
reg [WIDTH-1:0] multiplicand;
reg [2:0] booth;
reg [WIDTH+2:0] temp_multiplier;
// Outputs
wire [WIDTH:0] product; // Partial product
wire comp;
wire [WIDTH:0] pp_in, pp_n, pp_2, pp_2n, pp_... | 6.816759 |
module BoothPPG_32R4 (
a,
b,
sign,
i,
pp0,
pp1,
pp2,
pp3,
pp4,
pp5,
pp6,
pp7,
pp8,
pp9,
pp10,
pp11,
pp12,
pp13,
pp14,
pp15,
pp16
);
input wire [31:0] a;
input wire [31:0] b;
input wire sign;
output wire [15:0] i;
output wire... | 7.209531 |
module BoothPPG_32R4_MSB (
mulcand,
msb,
sign,
pp
);
input wire [31:0] mulcand;
input wire msb;
input wire sign;
output wire [31:0] pp;
assign pp = ((sign == 0) && (msb == 1)) ? mulcand : 32'b0;
endmodule
| 7.209531 |
module BoothPPG_32R4_NORM (
mulcand,
r4input,
sign,
pp
);
input wire [31:0] mulcand;
input wire [2:0] r4input;
input wire sign;
output wire [33:0] pp;
wire [32:0] raw;
assign raw[32:0] = (r4input[1]^r4input[0] === 0)?
((r4input[2]^r4input[0] === 0)?0:{mulcand[31:0], 1'b0}):
((sign... | 7.209531 |
module boothSel #(
parameter WIDTH = 14
) (
input single, // The single input to the Selector
input double, // The double input to the Selector
input neg, // The neg input to the Selector
input [WIDTH:0] in, // The input to the Selector
... | 7.630619 |
module Adder (
a,
b,
sum
);
input [7:0] a, b;
output [7:0] sum;
wire cout;
wire [7:0] q;
fa fa1 (
a[0],
b[0],
1'b0,
sum[0],
q[0]
);
fa fa2 (
a[1],
b[1],
q[0],
sum[1],
q[1]
);
fa fa3 (
a[2],
b[2],
q[1],
sum[... | 6.808429 |
module booth_substep (
input wire signed [7:0] a,
Q,
input wire signed q0,
input wire signed [7:0] m,
output reg signed [7:0] f8,
output reg signed [7:0] l8,
output reg cq0
);
wire [7:0] addam, subam;
Adder myadd (
a,
m,
addam
);
subtractor mysub (
a,
m,... | 6.761271 |
modules instantiated within the controller and datapath units,
// and the top module that instantiates the controller and datapath and wires together the necessary
// ports together.
//////////////////////////////////////////////////////////////////////////////////
// Accumulator register for the datapath circuit... | 8.393884 |
modules,
// the LSB of the B register is sent into the bi Register, this serves
// as the previous bit of the B register, while at the same time
// the LSB is also sent into the input of an XOR gate and the cin of
// 2's complement adder/subtractor.
// The LSB serves three functions. The previous bit of the B reg (b... | 9.092212 |
module xor_gate (
in0,
in1,
out
);
input in0;
input in1;
output out;
assign out = in1 ^ in0;
endmodule
| 8.121905 |
module mux_2in #(
parameter W = 32
) (
in0,
in1,
sel,
out
);
input [W-1:0] in0; // value is instantiated in datapath unit.
input [W-1:0] in1;
input sel;
output [W-1:0] out;
assign out = sel ? in1 : in0;
endmodule
| 8.648457 |
module A_Reg #(
parameter W = 32
) (
in,
clk,
load,
out
);
input [W-1:0] in;
input clk;
input load;
output [W-1:0] out;
reg [W-1:0] A_Reg;
initial begin
A_Reg = 32'b0;
end
always @(posedge clk) begin
if (load) A_Reg <= in;
end
assign out = A_Reg;
endmodule
| 8.82846 |
module AS_2comp #(
parameter W = 32
) (
a,
b,
cin,
out
);
input [W-1:0] a;
input [W-1:0] b;
input cin;
output [W-1:0] out;
assign out = cin ? (b + ~a + cin) : (b + a);
endmodule
| 8.280241 |
modules are part os the control circuit.
// The DFF is used as part of the state, next-state controller logic.
// The DFF is a clocked register that can be used to allow for
// a single clock cycle to occur before the states are sent to the controller
// after the next state inputs are sent into this DFF.
module DFF... | 7.368768 |
module Countdown_Counter (
SubCount,
CountRst,
clk,
Done,
CountReg
);
input SubCount;
input CountRst;
input clk;
output Done;
output [5:0] CountReg;
reg [5:0] CountReg;
initial begin
CountReg = 6'd32;
end
// only posedge clk in sensitivity list and not
// also posedge re... | 7.614592 |
module Controller_Logic (
Start,
Done,
state0,
state1,
nstate0,
nstate1,
SubCount,
CountRst,
accRst,
accLd,
Bld,
Ald,
biRst,
Ready,
Shift
);
input Start;
input Done;
input state0;
input state1;
output nstate0;
output nstate1;
//reg nstate0;
... | 7.304573 |
module
// for initial debugging and to view the signal occurences of
// each operand and other key outputs within the circuit.
module Booths_Signed_Mult32#( parameter W = 32 )
( A,
B,
Start,
clk,
Result,
accRst,
accLd,
Bld,
Ald,
bi_1_Rst,
Ready,
Sh... | 7.454266 |
module carry_save_adder #(
parameter DATA_WIDTH = 32
) (
input [DATA_WIDTH - 1:0] a,
input [DATA_WIDTH - 1:0] b,
input [DATA_WIDTH - 1:0] c,
output [DATA_WIDTH - 1:0] sum,
output [DATA_WIDTH - 1:0] cout
);
genvar i;
generate
for (i = 0; i < DATA_WIDTH; i = i + 1) begin : three
... | 7.192563 |
module booth_2bit #(
parameter DATA_WIDTH = 34,
parameter EXTEND_WIDTH = 33,
parameter BIAS = 0
) (
input [2:0] y,
input [DATA_WIDTH - 1:0] num_double,
input [DATA_WIDTH - 1:0] num_double_minus,
input [DATA_WIDTH - 1:0] num_data_width,
input [DATA_WIDTH - 1:0] num_minus,
output [EXT... | 6.656786 |
module booth_32x32_mult (
product,
Q,
M
);
parameter REG_SIZE = 32;
parameter REG_HALF_SIZE = REG_SIZE / 2;
input [REG_SIZE-1:0] Q, M;
output [REG_SIZE + REG_SIZE - 1:0] product;
reg [REG_SIZE + REG_SIZE -1:0] prod;
reg [2:0] two_bit_recoding[REG_SIZE-1:0];
reg [REG_SIZE + REG_SIZE-1:0] parti... | 6.621393 |
module booth_4bit;
input [3:0] m;
input [4:0] q;
output [7:0] z;
wire [3:0] a_out1;
wire [4:0] q_out1;
wire [3:0] a_out2;
wire [4:0] q_out2;
wire [3:0] a_out3;
wire [4:0] q_out3;
wire [3:0] a_out4;
wire [4:0] q_out4;
booth_base booth1 (
.a_in(4'b0000),
.m(m),
.q_in({q, 1'b... | 7.103872 |
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module alu (
out,
a,
b,
cin
);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;
assign out = a + b + cin;
endmodule
| 7.812586 |
module controls what operation is perforemed based on the booth algorithm. If adding or subtracting or just shifting.
//cass modules are full adders for each row of the array multiplier that work based on the control signals generated.
//Python script was used to generate the verilog code without errors.
//Refer to th... | 7.033768 |
module cass (
pout,
cout,
a,
pin,
cin
);
output pout, cout;
input a, pin, cin;
assign pout = a ^ pin ^ cin;
assign cout = (a & pin) | (a & cin) | (pin & cin);
endmodule
| 7.129421 |
module cass_16bit (
pout,
a,
pin,
cin
);
output [15:0] pout;
input [15:0] a;
input [14:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2... | 6.689494 |
module cass_17bit (
pout,
a,
pin,
cin
);
output [16:0] pout;
input [15:0] a;
input [15:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cas... | 7.022218 |
module cass_18bit (
pout,
a,
pin,
cin
);
output [17:0] pout;
input [15:0] a;
input [16:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
... | 6.757213 |
module cass_19bit (
pout,
a,
pin,
cin
);
output [18:0] pout;
input [15:0] a;
input [17:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
... | 6.666081 |
module cass_20bit (
pout,
a,
pin,
cin
);
output [19:0] pout;
input [15:0] a;
input [18:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(... | 6.560783 |
module cass_21bit (
pout,
a,
pin,
cin
);
output [20:0] pout;
input [15:0] a;
input [19:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
... | 6.786658 |
module cass_22bit (
pout,
a,
pin,
cin
);
output [21:0] pout;
input [15:0] a;
input [20:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
... | 6.857238 |
module cass_23bit (
pout,
a,
pin,
cin
);
output [22:0] pout;
input [15:0] a;
input [21:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
... | 6.786241 |
module cass_25bit (
pout,
a,
pin,
cin
);
output [24:0] pout;
input [15:0] a;
input [23:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.ci... | 6.507961 |
module cass_27bit (
pout,
a,
pin,
cin
);
output [26:0] pout;
input [15:0] a;
input [25:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
... | 6.595239 |
module cass_30bit (
pout,
a,
pin,
cin
);
output [29:0] pout;
input [15:0] a;
input [28:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.... | 6.567409 |
module cass_31bit (
pout,
a,
pin,
cin
);
output [30:0] pout;
input [15:0] a;
input [29:0] pin;
input cin;
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16,c17,c18,c19,c20,c21,c22,c23,c24,c25,c26,c27,c28,c29,c30;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
... | 7.017559 |
module booth_array_4bit (
prod,
a,
b
);
output [7:0] prod;
input [3:0] a, b;
wire cr1, cr2, cr3, cr4;
wire [3:0] mdr1, mdr2, mdr3, mdr4;
wire [3:0] poutr1;
wire [4:0] poutr2;
wire [5:0] poutr3;
wire [6:0] poutr4;
ctrl c1 (
.md (mdr1),
.cin(cr1),
.a (a),
.xi ({b[3],... | 7.16085 |
module cass (
pout,
cout,
a,
pin,
cin
);
output pout, cout;
input a, pin, cin;
assign pout = a ^ pin ^ cin;
assign cout = (a & pin) | (a & cin) | (pin & cin);
endmodule
| 7.129421 |
module cass_4bit (
pout,
a,
pin,
cin
);
output [3:0] pout;
input [3:0] a;
input [2:0] pin;
input cin;
wire c1, c2, c3;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
... | 7.509654 |
module cass_5bit (
pout,
a,
pin,
cin
);
output [4:0] pout;
input [3:0] a;
input [3:0] pin;
input cin;
wire c1, c2, c3, c4;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a(a[1... | 7.407323 |
module cass_6bit (
pout,
a,
pin,
cin
);
output [5:0] pout;
input [3:0] a;
input [4:0] pin;
input cin;
wire c1, c2, c3, c4, c5;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
.a... | 7.247962 |
module cass_7bit (
pout,
a,
pin,
cin
);
output [6:0] pout;
input [3:0] a;
input [5:0] pin;
input cin;
wire c1, c2, c3, c4, c5, c6;
cass ca1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass ca2 (
.pout(pout[1]),
.cout(c2),
... | 7.596903 |
module cass_16bit (
pout,
a,
pin,
cin
);
output [15:0] pout;
input [15:0] a, pin;
input cin;
cass c1 (
.pout(pout[0]),
.cout(c1),
.a(a[0]),
.pin(1'b0),
.cin(cin)
);
cass c2 (
.pout(pout[1]),
.cout(c2),
.a(a[1]),
.pin(pin[0]),
.cin(c... | 6.689494 |
module booth_code_25_bit (
A,
code,
h,
product,
sn
);
// &Ports; @22
input [24:0] A;
input [2 : 0] code;
output [1 : 0] h;
output [24:0] product;
output sn;
// &Regs; @23
reg [1 : 0] h;
reg [ 24:0] product;
reg sn;
// &Wires; @24
wire [ 24:0] A;
wire [2 : 0] c... | 6.7345 |
module booth_code_33_bit (
A,
code,
h,
product,
sn
);
// &Ports; @22
input [32:0] A;
input [2 : 0] code;
output [1 : 0] h;
output [32:0] product;
output sn;
// &Regs; @23
reg [1 : 0] h;
reg [ 32:0] product;
reg sn;
// &Wires; @24
wire [ 32:0] A;
wire [2 : 0] c... | 7.463438 |
module booth_code_54_bit (
A,
code,
h,
product,
sn
);
// &Ports; @22
input [53:0] A;
input [2 : 0] code;
output [1 : 0] h;
output [53:0] product;
output sn;
// &Regs; @23
reg [1 : 0] h;
reg [ 53:0] product;
reg sn;
// &Wires; @24
wire [ 53:0] A;
wire [2 : 0] c... | 7.580571 |
module Booth_ControlUnit (
input q0,
input q1,
output reg [1:0] BoothOp
);
always @(*) begin
$display("q1 = %b , q0=%b", q1, q0);
case ({
q1, q0
})
2'b01: begin
BoothOp = 2'b01;
$display("%b", BoothOp);
end
2'b10: begin
BoothOp = 2'b10;
... | 6.555426 |
module Booth_ControlUnit_tb;
// Inputs
reg q0;
reg q1;
wire [1:0] q1q0;
// Instantiate the Unit Under Test (UUT)
Booth_ControlUnit uut (
.q0 (q0),
.q1 (q1),
.q1q0(q1q0)
);
initial begin
// Initialize Inputs
q0 = 0;
q1 = 0;
#100;
q0 = 1;
q1 = 0;
#100;
... | 6.555426 |
module: Booth_ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Booth_ControlUnit_test;
// Inputs
reg q0;
reg q1;
// Outputs
wire [1:0] q1q0;
// Instantiate the Un... | 6.667857 |
module booth_cu (
input L,
input lsb,
output reg [1:0] booth_op
);
always @(*) begin
case ({
lsb, L
})
2'b01: begin
booth_op <= 2'b01;
end
2'b10: begin
booth_op <= 2'b10;
end
default: booth_op <= 2'b00;
endcase
end
endmodule
| 7.050264 |
module BOOTH_datapath (
output wire q0,
qm1,
eqz,
output wire [9:0] data_out,
input wire [4:0] data_in,
input wire LdA,
LdQ,
LdM,
clrA,
clrQ,
clrff,
sftA,
sftQ,
sftDff,
add_sub,
EnableALU,
clk,
LdCount,
decr
);
wire [4:0] A, M, Q, Z;
wire ... | 6.79379 |
module booth_encoder (
Booth_b_DI,
Sel_1x_SO,
Sel_2x_SO,
Sel_sign_SO
);
input wire [2:0] Booth_b_DI;
output wire Sel_1x_SO;
output wire Sel_2x_SO;
output wire Sel_sign_SO;
wire Sel_xnor_S;
assign Sel_1x_SO = ^Booth_b_DI[1:0];
assign Sel_xnor_S = ~(^Booth_b_DI[2:1]);
assign Sel_2x_SO ... | 7.829276 |
module booth_encoder (
x,
single,
double,
neg
);
input [2:0] x;
output single, double, neg;
wire notx0, notx1, notx2, w0, w1;
not #(387.77, 363.86) not0 (notx0, x[0]);
not #(387.77, 363.86) not1 (notx1, x[1]);
not #(387.77, 363.86) not2 (notx2, x[2]);
xor #(350.51, 306.96) xor0 (single, ... | 7.829276 |
module booth_selector (
double,
shifted,
single,
y,
neg,
p
);
input double, shifted, single, y, neg;
output p;
assign #(1125.88, 1235.74) p = (neg ^ ((y & single) | (shifted & double)));
endmodule
| 7.153136 |
module ripple_carry_adder #(
parameter width = 4
) (
a,
b,
cin,
sum,
cout
);
input [width - 1:0] a, b;
input cin;
wire [width -1:0] c;
output [width - 1:0] sum;
output cout;
genvar i;
generate
for (i = 0; i < width; i = i + 1) begin : for_rca
case (i)
1'b0: full_... | 7.682509 |
module half_adder (
a,
b,
sum,
cout
);
input a, b;
output sum, cout;
xor #(350.51, 306.96) xor_1 (sum, a, b);
and #(452.43, 400.56) and_1 (cout, a, b);
endmodule
| 6.966406 |
module invert (
output ib,
input b
);
assign ib = ~b;
endmodule
| 7.953624 |
module and2 (
input wire i0,
i1,
output wire o
);
assign o = i0 & i1;
endmodule
| 8.35921 |
module or2 (
input wire i0,
i1,
output wire o
);
assign o = i0 | i1;
endmodule
| 8.541431 |
module xor2 (
input wire i0,
i1,
output wire o
);
assign o = i0 ^ i1;
endmodule
| 8.782532 |
module nand2 (
input wire i0,
i1,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.360689 |
module nor2 (
input wire i0,
i1,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.781479 |
module xnor2 (
input wire i0,
i1,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
invert invert_0 (
t,
o
);
endmodule
| 7.523861 |
module and3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
and2 and2_1 (
i2,
t,
o
);
endmodule
| 7.185291 |
module or3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
or2 or2_1 (
i2,
t,
o
);
endmodule
| 7.924047 |
module nor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
or2 or2_0 (
i0,
i1,
t
);
nor2 nor2_0 (
i2,
t,
o
);
endmodule
| 7.838557 |
module nand3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
and2 and2_0 (
i0,
i1,
t
);
nand2 nand2_1 (
i2,
t,
o
);
endmodule
| 7.036906 |
module xor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xor2 xor2_1 (
i2,
t,
o
);
endmodule
| 8.362259 |
module xnor3 (
input wire i0,
i1,
i2,
output wire o
);
wire t;
xor2 xor2_0 (
i0,
i1,
t
);
xnor2 xnor2_0 (
i2,
t,
o
);
endmodule
| 7.872322 |
module fa (
input wire i0,
i1,
cin,
output wire sum,
cout
);
wire t0, t1, t2;
xor3 _i0 (
i0,
i1,
cin,
sum
);
and2 _i1 (
i0,
i1,
t0
);
and2 _i2 (
i1,
cin,
t1
);
and2 _i3 (
cin,
i0,
t2
);
or3 _i4 (
... | 7.001699 |
module Adder (
a,
b,
sum
);
input [7:0] a, b;
output [7:0] sum;
wire cout;
wire [7:0] q;
fa fa1 (
a[0],
b[0],
1'b0,
sum[0],
q[0]
);
fa fa2 (
a[1],
b[1],
q[0],
sum[1],
q[1]
);
fa fa3 (
a[2],
b[2],
q[1],
sum[... | 6.808429 |
module booth_substep (
input wire signed [7:0] a,
Q,
input wire signed q0,
input wire signed [7:0] m,
output reg signed [7:0] f8,
output reg signed [7:0] l8,
output reg cq0
);
wire [7:0] addam, subam;
Adder myadd (
a,
m,
addam
);
subtractor mysub (
a,
m,... | 6.761271 |
module booth_multiplier32 (
input wire clk,
input wire sync_rst,
input wire valid,
input wire [31:0] A,
input wire [31:0] B,
output wire [63:0] R,
output wire ready
);
// load and store A
reg [31:0] A_reg;
always @(posedge clk)
if (sync_rst) A_reg <= 32'b0;
else if (valid & re... | 6.943306 |
module booth_multiplier32_tb;
// Inputs
reg clk;
reg sync_rst;
reg valid;
reg signed [31:0] A;
reg signed [31:0] B;
reg [30:0] A_data;
reg [30:0] B_data;
// Outputs
wire [63:0] R;
wire ready;
// Instantiate the Unit Under Test (UUT)
booth_multiplier32 uut (
.clk(clk),
.sync_rst(... | 6.943306 |
module booth_multiplier_8bit (
A,
B,
P
);
input [7:0] A, B;
output [8:0] P;
full_adder_booth_encoded_8bit ROW_0 ();
full_adder_booth_encoded_8bit ROW_1 ();
full_adder_booth_encoded_8bit ROW_2 ();
full_adder_booth_encoded_8bit ROW_3 ();
full_adder_booth_encoded_8bit ROW_4 ();
full_adder_boot... | 6.943306 |
module booth_multiplier_module (
input clk,
input rst_n,
input start_sig,
input [7:0] A,
input [7:0] B,
output done_sig,
output [15:0] product,
output [ 7:0] SQ_a,
output [ 7:0] SQ_s,
output [16:0] SQ_p
);
/*******************/
reg [3:0]i;
reg [7:0]a; //result of ... | 6.943306 |
module booth_multiplier_module_improve (
input clk,
input rst_n,
input start_sig,
input [7:0] A,
input [7:0] B,
output done_sig,
output [15:0] product,
output [ 7:0] SQ_a,
output [ 7:0] SQ_s,
output [16:0] SQ_p
);
/*******************/
reg [3:0]i;
reg [7:0]a; //re... | 6.943306 |
module booth_multiplier_module_tb;
reg clk;
reg rst_n;
reg start_sig;
reg [7:0] A;
reg [7:0] B;
wire done_sig;
wire [15:0] product;
wire [7:0] SQ_a;
wire [7:0] SQ_s;
wire [16:0] SQ_p;
/*******************/
/*
booth_multiplier_module u1(
.clk(clk),
.rst_n(rst_n),
... | 6.943306 |
module Booth_multiplier_pipeline #(
parameter DATAWIDTH = 8
) (
input CLK,
input RSTn,
input [DATAWIDTH - 1 : 0] A,
input [DATAWIDTH - 1 : 0] B,
output [DATAWIDTH * 2 - 1 : 0] RESULT
);
wire [ DATAWIDTH * 2 : 0 ] P = { 8'b0, B, 1'b0 };
wire [ DATAWI... | 7.922206 |
module booth_multiplier_tb;
// Declare inputs and outputs
reg clk, load, reset;
reg signed [7:0] a, b;
wire signed [15:0] product;
// Instantiate the Unit Under Test (UUT)
booth_multiplier multiplier (
.clk(clk),
.reset(reset),
.load(load),
.Mc(a),
.Mp(b),
.product(pro... | 6.943306 |
module test;
// Registers
reg clk;
reg en;
reg [7:0] A, B;
wire [15:0] Output; // The read data
wire ready;
// Initialize varibles
initial begin
#1 en = 0;
clk = 0;
A = 8'd129;
B = 8'd1;
#2 en = 1;
#15 en = 0;
#12 $finish;
end
// Monitoring the output
alwa... | 6.888292 |
module
//===================================================================
module booth_multi_top (
clk,
rstn,
multiplier, //16bits
multiplicand, //32bits
Sum_result, //output [31:0] ... | 7.574158 |
module Booth_Norm (
input [31:0] mulcand,
input [2:0] r4input,
input sign,
output [33:0] pp
);
wire [32:0] raw;
assign raw[32:0] = (r4input[1]^r4input[0] === 0)?
((r4input[2]^r4input[0] === 0)?0:{mulcand[31:0], 1'b0}):
((sign === 0)?{1'b0, mulcand[31:0]}:{mulcand[31], mulcan... | 6.762597 |
module booth_recode (
out,
mcand,
code
);
output reg [25:0] out;
input [24:0] mcand;
input [2:0] code;
always @(mcand, code)
case (code)
3'b000: out = 26'b0;
3'b001: out = {mcand[24], mcand};
3'b010: out = {mcand[24], mcand};
3'b011: out = {mcand, 1'b0};
3'b100: o... | 6.587652 |
module booth_recoded_multiplier (
clk,
reset,
multiplicand,
multiplier,
prod
);
//Input
input clk; // Clock
input reset; // Reset
input [11:0] multiplicand, multiplier;
//Output
output [23:0] prod;
//Wire
wire [11:0] A, B, A_2comp, B_2comp;
wire [17:0] enc_op;
wire [ 5:0] cor_... | 6.624849 |
module
//===================================================================
`timescale 1ns / 1ps
`include "booth_recoded_multiplier.v"
module booth_recoded_multiplier_tb();
// Inputs
reg clk;
reg reset;
reg [11:0] multiplicand;
reg [11:0] multiplier;
// Outputs
wire [23:0] prod;
// Instantiate the Unit Under... | 7.574158 |
module booth_selector (
Booth_a_DI,
Sel_1x_SI,
Sel_2x_SI,
Sel_sign_SI,
Booth_pp_DO
);
input wire [1:0] Booth_a_DI;
input wire Sel_1x_SI;
input wire Sel_2x_SI;
input wire Sel_sign_SI;
output wire Booth_pp_DO;
assign Booth_pp_DO = ~(~((Sel_1x_SI && Booth_a_DI[1]) | (Sel_2x_SI && Booth_a_DI... | 7.153136 |
module booth_signed_multiplier_16 (
product,
A,
B
);
input signed [15:0] A, B;
output signed [31:0] product;
reg [31:0] product;
reg [1:0] temp;
integer i;
reg E1;
reg [15:0] B1;
always @(*) begin
product = 32'd0;
E1 = 1'd0;
B1 = -B;
for (i = 0; i < 16; i = i + 1) begin
... | 7.22283 |
module booth_signed_multiplier_4 (
product,
A,
B
);
input signed [3:0] A, B;
output signed [7:0] product;
reg [7:0] product;
reg [1:0] temp;
integer i;
reg E1;
reg [3:0] B1;
always @(*) begin
product = 8'd0;
E1 = 1'd0;
B1 = -B;
for (i = 0; i < 4; i = i + 1) begin
temp ... | 7.22283 |
module booth_signed_multiplier_8 (
product,
A,
B
);
input signed [7:0] A, B;
output signed [15:0] product;
reg [15:0] product;
reg [1:0] temp;
integer i;
reg E1;
reg [7:0] B1;
always @(*) begin
product = 16'd0;
E1 = 1'd0;
B1 = -B;
for (i = 0; i < 8; i = i + 1) begin
te... | 7.22283 |
module: booth
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module booth_tb;
// Inputs
reg [24:0] x;
reg [24:0] y;
// Outputs
wire [49:0] p;
// Instantiate the ... | 6.559363 |
module eight_bit_adder_subractor (
input wire cin,
input wire [7:0] i0,
i1,
output wire [7:0] sum
);
wire cout;
wire [7:0] temp;
wire [7:0] int_ip; //intermediate input - processed from the inputs and fed into fa module
//if cin == 1, int_ip = 1's complement
//else int_ip = i1
xor2 x0 (
... | 7.124161 |
module booth_substep (
input wire signed [7:0] acc, //Current value of accumulator
input wire signed [7:0] Q, //Current value of Q (initially the multiplier)
input wire signed q0, //Current value of q-1 th bit
input wire signed [7:0] multiplicand, //the multipliand
output reg signed [7:0] ne... | 6.761271 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.