code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bpsk_mod_demod_tb ();
reg clk;
reg rst;
reg [15:0] input_data;
wire [15:0] bpsk_mod_out;
reg read_ready;
BPSK_mod_demod bpsk (
input_data,
bpsk_mod_out
);
initial begin
rst = 1;
rst = 0;
clk = 1;
#20;
forever begin
clk = ~clk;
#20;
end
end
ini... | 6.722605 |
module bpsk_mod_tb ();
reg clk;
reg rst;
reg [15:0] input_data;
wire [15:0] bpsk_mod_out_re, bpsk_mod_out_im;
BPSK_Modulator_Baseband bpsk_mod (
input_data,
bpsk_mod_out_re,
bpsk_mod_out_im
);
initial begin
rst = 1;
rst = 0;
clk = 1;
#20;
forever begin
clk = ~... | 6.703733 |
module BAUD_GEN #(
parameter BAUD_RATE = 16'd9600,
parameter FLL_CNTL_PARAM = 24'd1280000,
parameter FLL_CNTL_FREQ = 16'd100,
parameter BAUD_INITIAL = 24'd96
) (
input wire clk,
input wire nrst,
output reg cntl_clk_out
);
localparam MAX_VCO_CNT = 24'sd65536;
localparam MIN_VCO_CNT = ... | 7.442923 |
module BPSK_Ctrl #(
parameter integer data_width = 32,
parameter integer frame_length = 38,
parameter integer addr_width = 32,
parameter integer ref_clk_freq = 128000000,
parameter integer baudrate = 9600
) (
input clk, //时钟信号
input rst_n, //复位信号
input send_signal, // send ... | 7.219228 |
module BAUD_GEN #(
parameter BAUD_RATE = 16'd9600,
parameter FLL_CNTL_PARAM = 24'd1280000,
parameter FLL_CNTL_FREQ = 16'd100,
parameter BAUD_INITIAL = 24'd96
) (
input wire clk,
input wire nrst,
output reg cntl_clk_out
);
localparam MAX_VCO_CNT = 24'sd65536;
localparam MIN_VCO_CNT = ... | 7.442923 |
module BPSK_Ctrl #(
parameter integer data_width = 32,
parameter integer frame_length = 38,
parameter integer addr_width = 32,
parameter integer ref_clk_freq = 128000000,
parameter integer baudrate = 9600
) (
input clk, //ʱź
input rst_n, //λź
input power_on, //=1ʱ, ֡
// RAM˿... | 7.219228 |
module BAUD_GEN #(
parameter BAUD_RATE = 16'd9600,
parameter FLL_CNTL_PARAM = 24'd1280000,
parameter FLL_CNTL_FREQ = 16'd100,
parameter BAUD_INITIAL = 24'd96
) (
input wire clk,
input wire nrst,
output reg cntl_clk_out
);
localparam MAX_VCO_CNT = 24'sd65536;
localparam MIN_VCO_CNT = ... | 7.442923 |
module BPSK_Ctrl #(
parameter integer data_width = 8,
parameter integer frame_length = 150,
parameter integer addr_width = 8,
parameter integer ref_clk_freq = 128000000,
parameter integer baudrate = 9600
) (
input clk, //ʱź
input rst_n, //λź
input send_signal, // send ź
... | 7.219228 |
module bpsk_top (
input sys_clk,
input rst_n,
output reg a
);
wire en;
wire clk_50m;
wire rst_global;
wire locked;
wire code;
wire code_vld;
wire cos_vld;
(* MARK_DEBUG="true" *)wire [... | 6.568313 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bps_module(
sysclk,
rst_n,
count_sig,
... | 7.088073 |
module Bps_select (
input clk, //系统时钟50MHz
input rst_n, //低电平复位
input en, //使能信号：串口接收活发送开始
output reg sel_data, //波特率计数中心点（采集数据的使能信号）
output reg [3:0] num //一帧数据bit0~bit9
);
parameter bps_div = 13'd5207, //(1/9600*1000000*1000/20)
... | 7.598806 |
module bps_set (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd434; //(50_000_000/9600)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (bps_sta... | 6.864722 |
module bps_set_115200 (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd434; //(50_000_000/115200)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if... | 7.078796 |
module bps_set_57600 (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd868; //(50_000_000/57600)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (... | 7.380604 |
module bps_set_9600 (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd5208; //(50_000_000/9600)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (b... | 6.571904 |
module bps_set_lora (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd434; //(50_000_000/9600)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (bp... | 8.040765 |
module BPS_timer
//----------------------------------------------------------------
// Params
//----------------------------------------------------------------
#(
parameter CLK_rate = 100000000,
parameter Baud_rate = 9600
)
//----------------------------------------------------------------
// Ports
//-----... | 6.728591 |
module BPU (
in_PC,
in_hit,
in_Clk,
in_Rst_N,
out_prediction
);
input in_Clk, in_Rst_N;
input [1:0] in_hit; // LSB defines if predictor 0 hit or not, MSB defines if predictor 1 hit or not
input [8:0] in_PC;
output out_prediction;
wire predictor_selector_Out, bimodal_prediction, gshare... | 7.844936 |
module BPU_AP (
input wire i_clk,
input wire i_rstn,
input wire i_stop, //暂停,保持指令不变输出
input wire i_flush, //冲刷
input wire i_data_vld, //取指读出的数据是否有效
input wire [`xlen_def] i_iaddr, //数据地址
input wire [`ilen_def] i_data, //数据地址舍去低2位后的数据
output wire o_inst_vld, //对齐处理完成,已经是可译码的指令
... | 7.875057 |
module BPU_BP (
input wire i_clk,
input wire i_rstn,
//预译码信息
input wire [`xlen_def] i_pc, //当前分支指令pc值
input wire i_inst_jal,
input wire i_inst_jalr,
input wire i_inst_rs1ren, //jalr 需要读rs1
input wire i_inst_bxx,
input wire [`xlen_def] i_imm, //立即数
input wire [`xlen_def] i_jal... | 7.768984 |
module bp_be_bypass
import bp_common_rv64_pkg::*;
#(
parameter depth_p = "inv"
, parameter els_p = "inv"
, parameter zero_x0_p = 0
// Generated params
, localparam reg_addr_width_lp = rv64_reg_addr_width_gp
, localparam reg_data_width_lp = rv64_reg_data_width_gp
) (
// Dispatched ... | 7.725144 |
module bp_be_fp_to_rec
import bp_common_pkg::*;
import bp_common_rv64_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_be_hardfloat_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
)
(// RAW floating point input
input [dword_width... | 9.910358 |
module bp_be_mock_ptw
import bp_common_pkg::*;
import bp_be_pkg::*;
#(parameter vtag_width_p="inv"
,parameter ptag_width_p="inv"
,localparam entry_width_lp = `bp_be_tlb_entry_width(ptag_width_p)
)
(input clk_i
, input reset_i
, inpu... | 6.85684 |
module bp_be_pipe_ctl
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
import bp_be_dcache_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
, localparam dispatch_pkt_width_lp = `bp_be_dispatch_pkt_... | 7.186845 |
module bp_be_pipe_int
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
#(
parameter vaddr_width_p = "inv"
// Generated parameters
, localparam decode_width_lp = `bp_be_decode_width
, localparam exception_width_lp = `bp_be_exception_width
// From RISC-V specifications
, localparam reg_d... | 8.733076 |
module bp_be_pipe_long
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
, localparam wb_pkt_width_lp = `bp_be_wb_pkt_width(vaddr_width_p)
, localparam decode_... | 7.625022 |
module bp_be_rec_to_fp
import bp_common_pkg::*;
import bp_common_rv64_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_be_hardfloat_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
)
(input [dp_rec_width_gp-1:0] rec_i
, input ... | 8.050903 |
module bp_be_regfile
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
, localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p... | 7.174308 |
module bp_cacc_tile_node
import bp_common_pkg::*;
import bp_common_rv64_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_cce_pkg::*;
import bsg_noc_pkg::*;
import bp_common_cfg_link_pkg::*;
import bsg_wormhole_router_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp... | 7.101469 |
module for storing branch prediction data.
Inputs: 2 asynchronous read ports and 1 synchronous write port.
Outputs: data and cache hit (for each read port)
*/
module bp_cache #(
parameter AWIDTH=32, // Address bit width
parameter DWIDTH=32, // Data bit width
parameter LINES=128 // Number of cache line... | 6.755624 |
module bp_cce_alu
import bp_cce_pkg::*;
#(
parameter width_p = "inv"
) (
input [width_p-1:0] opd_a_i
, input [width_p-1:0] opd_b_i
, input bp_cce_inst_alu_op_e alu_op_i
, output logic [width_p-1:0] res_o
);
always_comb ... | 7.089842 |
module bp_cce_branch
import bp_cce_pkg::*;
#(
parameter width_p = "inv"
, parameter cce_pc_width_p = "inv"
) (
input [ width_p-1:0] opd_a_i
, input [ width_p-1:0] opd_b_i
, input ... | 7.273019 |
module extracts information about the LRU entry of the requesting LCE
*
*/
module bp_cce_dir_lru_extract
import bp_common_pkg::*;
import bp_cce_pkg::*;
#(parameter tag_sets_per_row_p = "inv"
, parameter row_width_p = "inv"
, parameter num_lce_p = "inv"
, param... | 7.550381 |
module performs the parallel tag comparison on a row of tag sets from the directory.
*
*/
module bp_cce_dir_tag_checker
import bp_common_pkg::*;
import bp_cce_pkg::*;
#(parameter tag_sets_per_row_p = "inv"
, parameter row_width_p = "inv"
, parameter assoc_p = "i... | 7.634754 |
module is an active tie-off. That is, requests to this module will return the header
// with a zero payload. This is useful to not stall the network in the case of an erroneous
// address, or prevent deadlock at network boundaries
module bp_cce_loopback
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
... | 6.545817 |
module for the CCE.
*
* It instantiates either the microcode or FSM CCE, based on the param in bp_params_p.
*
*/
module bp_cce_wrapper
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_common_cfg_link_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_param... | 6.803591 |
module bp_fe_bht
import bp_fe_pkg::*;
#(
parameter bht_idx_width_p = "inv"
, localparam els_lp = 2 ** bht_idx_width_p
, localparam saturation_size_lp = 2
) (
input clk_i
, input reset_i
, input w_v_i
, input [bht_idx_width_p-1:0] idx_w_i
, input ... | 7.461993 |
module bp_fe_btb
import bp_fe_pkg::*;
import bp_common_rv64_pkg::*;
#(
parameter vaddr_width_p = "inv"
, parameter btb_tag_width_p = "inv"
, parameter btb_idx_width_p = "inv"
, localparam btb_offset_width_lp = 2 // bottom 2 bits are unused without compressed branches
... | 8.223668 |
module bp_FSM (
ip_state,
b_res,
clk,
rst,
op_state,
pred
);
input [1:0] ip_state;
input b_res; //Actual result of branch
input clk;
input rst;
output reg [1:0] op_state; //Output state after verifying actual result
output reg pred; //predicted operation for branch
localparam s... | 6.582959 |
module btb_input(rst,btb,index,PredictedTarget,curr_state,mux_predict);
input rst;
input [34:0]btb[0:31]
input [4:0]index;
output reg [1:0]curr_state;
output reg [31:0]PredictedTarget;
output mux_predict;
reg i;
initial
begin
for(i = 0; i < 32; i = i+1)
btable[i] <= 35'd0;
end
always@(index,rst)
begin
if(rst... | 6.831081 |
module btb_update (
btb,
index,
TargetAddress,
next_state,
predict_bit
);
input [34:0] btb[0:31];
input [4:0] index;
input [32:0] TargetAddress;
input [1:0] next_state;
input predict_bit;
always @(*) begin
btb[index] = {TargetAddress, next_state, predict_bit};
end
endmodule
| 8.458744 |
module bp_lite_to_burst
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
, parameter in_data_width_p = "inv"
, parameter out_data_width_p = "inv"
// Bitmask which etermines which m... | 9.042699 |
module bp_mem
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
, paramete... | 6.584612 |
module bp_mem_delay_model #(
parameter addr_width_p = "inv"
, parameter use_max_latency_p = 0
, parameter use_random_latency_p = 0
, parameter use_dramsim2_latency_p = 0
, parameter max_latency_p = "inv"
, parameter dram_clock_period_in_ps_p = "inv"
, parameter dram_cfg_p ... | 8.418178 |
module bp_mem_storage_sync #(
parameter data_width_p = "inv"
, parameter addr_width_p = "inv"
, parameter mem_cap_in_bytes_p = "inv"
, parameter mem_load_p = 0
, parameter mem_zero_p = 0
, parameter mem_file_p = "inv"
, parameter mem_offset_p = "in... | 7.426659 |
module bp_me_addr_to_cce_id
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
)
(input [paddr_width_p-1:0] paddr_i
, output logic [cce_id_width_p-1:0] cce_id_o
);
bp_global_addr_s global_addr_li;
... | 6.840604 |
module to convert a coordinate into a set of ids. It assumes that
// the SoC topology is a fixed 2d mesh with a set mapping. Should be made more flexible
module bp_me_cord_to_id
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(b... | 8.335771 |
module bp_me_nonsynth_lce_tr_tracer
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_nonsynth_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_unicore_half_cfg
`declare_bp_proc_params(bp_params_p)
, parameter sets_p = "inv"
, parameter block_width_p = ... | 7.105833 |
module bp_me_nonsynth_mock_lce_tag_lookup
import bp_common_pkg::*;
import bp_cce_pkg::*;
#(
parameter assoc_p = "inv"
, parameter ptag_width_p = "inv"
, localparam dir_entry_width_lp = `bp_cce_dir_entry_width(ptag_width_p)
, localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p)
) (
input [assoc_p-1:... | 7.105833 |
module bp_me_wormhole_packet_encode_lce_cmd
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_wi... | 6.597197 |
module bp_me_wormhole_packet_encode_lce_req
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_wi... | 6.597197 |
module bp_me_wormhole_packet_encode_lce_resp
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_w... | 6.597197 |
module bp_me_wormhole_packet_encode_mem_cmd
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_widt... | 6.597197 |
module bp_me_wormhole_packet_encode_mem_resp
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_wid... | 6.597197 |
module bp_nonsynth_if_verif
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_common_rv64_pkg::*;
import bp_cce_pkg::*;
import bsg_noc_pkg::*;
import bp_common_cfg_link_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_para... | 7.319939 |
module bp_nonsynth_pc_profiler
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
, parameter pc_trace_file_p = "pc"
, localparam commit_pkt_width_lp =... | 7.102586 |
module bp_nonsynth_perf
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_common_rv64_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
, localparam max_instr_lp = 2**30-1
, localparam max_clock_lp = 2**30-1
)
(i... | 7.102586 |
module bp_nonsynth_watchdog
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
, parameter timeout_cycles_p = "inv"
, parameter heartbeat_instr_p = "... | 7.091234 |
module bp_osc #(
parameter WIDTH = 8
) (
input wire clk,
input wire reset_n,
input wire [(WIDTH - 1) : 0] opa,
input wire [(WIDTH - 1) : 0] opb,
output wire dout
);
//----------------------------------------------------------------
// Registers.
//---------------------------------------... | 7.617924 |
module bp_pma_05 (
ptag_v_i,
ptag_i,
uncached_o
);
input [27:0] ptag_i;
input ptag_v_i;
output uncached_o;
wire uncached_o, is_local_addr, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10;
assign N0 = ptag_i[26] | ptag_i[27];
assign N1 = ptag_i[25] | N0;
assign is_local_addr = ~N9;
assign N9 = N... | 6.996792 |
module bp_sacc_tile_node
import bp_common_pkg::*;
import bp_common_rv64_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_cce_pkg::*;
import bsg_noc_pkg::*;
import bp_common_cfg_link_pkg::*;
import bsg_wormhole_router_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp... | 7.50845 |
module bp_stream_mmio
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_be_pkg::*;
import bp_be_dcache_pkg::*;
#(parameter bp_cfg_e cfg_p = e_bp_inv_cfg
`declare_bp_proc_params(cfg_p)
,localparam cce_mshr_width_lp = `bp_cce_mshr_width(num_lce_p, lce_assoc_p, paddr... | 6.667796 |
module bp_stream_to_lite
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
, parameter in_data_width_p = "inv"
, parameter out_data_width_p = "inv"
// Bitmask which etermines which ... | 8.237923 |
module BP_TimerSetting (
//====================================================
//======= Input ======
//====================================================
input clk, // 25 MHz clock
input rst, // Asynchronous reset
input d... | 7.40272 |
module.h"
/********** Internal Define **********/
// Direction Prediction
`define PhtDataBus 1:0
`define PhtDepthBus 255:0
`define PhtAddrBus 7:0
`define BhrDataBus 7:0
`define BHR_DATA_W 8
`define OldBhtLoc 6:0
`define BankOffsetBus 1:0
`define BankOffsetLoc 3:2
// Address Prediction
`define BtbTypeBus 1:0
`define B... | 7.097988 |
module RAS_LIFO (
/**** Global Signal ****/
input wire clk,
input wire rst_,
/**** Ras flush ****/
input wire bp_error,
input wire [`WordAddrBus] error_pc,
/**** Addr_Predictor Signal ****/
input wire ras_write_en,
input wire [`WordAddrBus] call_pc,
input wire ras_read_en,
ou... | 8.121747 |
module.h"
/********** Internal Define **********/
// Direction Prediction
`define PhtDataBus 1:0
`define PhtDepthBus 255:0
`define PhtAddrBus 7:0
`define BhrDataBus 7:0
`define BHR_DATA_W 8
`define OldBhtLoc 6:0
`define BankOffsetBus 1:0
`define BankOffsetLoc 3:2
// Address Prediction
`define BtbTypeBus 1:0
`define B... | 7.097988 |
module RAS_LIFO (
/**** Global Signal ****/
input wire clk,
input wire rst_,
/**** Addr_Predictor Signal ****/
input wire ras_write_en,
input wire ras_read_en,
output wire [`WordAddrBus] ras_read_data,
input wire [`WordAddrBus] ras_write_data
);
/**** Internal Signal ****/
reg [... | 8.121747 |
module.h"
/********** Internal Define **********/
// Direction Prediction
`define PhtDataBus 1:0
`define PhtDepthBus 255:0
`define PhtAddrBus 7:0
`define BhrDataBus 7:0
`define BHR_DATA_W 8
`define OldBhtLoc 6:0
`define BankOffsetBus 1:0
`define BankOffsetLoc 3:2
// Address Prediction
`define BtbTypeBus 1:0
`define B... | 7.097988 |
module RAS_LIFO (
/**** Global Signal ****/
input wire clk,
input wire rst_,
/**** Addr_Predictor Signal ****/
input wire ras_write_en,
input wire ras_read_en,
output wire [`WordAddrBus] ras_read_data,
input wire [`WordAddrBus] ras_write_data
);
/**** Internal Signal ****/
reg [... | 8.121747 |
module br (
input [31:0] a,
input [31:0] b,
input [2:0] comp_ctrl,
input do_branch,
input do_jump,
output branch,
output jump
);
wire signed [31:0] signed_a;
wire signed [31:0] signed_b;
wire [31:0] unsigned_a;
wire [31:0] unsigned_b;
reg taken;
assign signed_a = a;
assign s... | 7.511983 |
module BR128
(
input wire RESET,
input wire [127:0] C,
output wire OUT
`ifdef USE_POWER_PINS
,
inout VSS,
inout VDD
`endif
);
supply1 VDD;
supply0 VSS;
// empty module
// see lib file
reg int1;
reg int2;
initial begin
int1 <= 0;
int2 <= 0;
end
always @ (posedge RESET) begin
... | 6.675913 |
module BR32
(
input wire RESET,
input wire [31:0] C,
output wire OUT
`ifdef USE_POWER_PINS
,
inout VSS,
inout VDD
`endif
);
supply1 VDD;
supply0 VSS;
// empty module
// see lib file
assign OUT = RESET;
endmodule
| 6.967415 |
module BR64
(
input wire RESET,
input wire [63:0] C,
output wire OUT
`ifdef USE_POWER_PINS
,
inout VSS,
inout VDD
`endif
);
supply1 VDD;
supply0 VSS;
// empty module
// see lib file
reg int1;
initial begin
int1 <= 0;
end
always @ (posedge RESET) begin
int1 <= ~int1;
end
a... | 6.757569 |
module BrainfuckWrapper (
CLK,
RESET,
CIN,
COUT,
CRDA,
CACK,
CWR,
CRDY
);
parameter FAST_LOOPEND = 1;
parameter IA_WIDTH = 11;
parameter DA_WIDTH = 11;
parameter DD_WIDTH = 8;
parameter STACK_DEPTH_POW = 7;
input CLK;
input RESET;
input [7:0] CIN;
output [7:0] COUT;
... | 7.028321 |
module msfp_generator (
input [`BFLOAT_EXP-1:0] exponent,
input [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa,
input clk,
input reset,
input start,
output reg out_data_available,
output reg [`BFLOAT_DWIDTH-1:0] msfp11
);
wire sign, is_valid;
wire [2:0] position;
wire [`LDPE_USED_OUTPUT_WIDTH-... | 6.720074 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input mrf_we,
input [`MRF_AWIDTH-1:0] mrf_addr,
input out_data_available_external_comparator_tree,
output out_data_available_internal_comparator_tree,
output ou... | 7.063526 |
module LDPE (
input clk,
input reset,
input start,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
input out_data_available_external_comparator_tree,
output [`LDPE_USED_OUTPUT_... | 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
alwa... | 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_D... | 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addr,
input [`MRF_DWIDTH-1:0] in,
input we,
output [`MRF_DWIDTH-1:0] out
);
sp_ram #(
.AWIDTH(`MAT_BRAM_AWIDTH),
.DWIDTH(`MAT_BRAM_DWIDTH)
) mat_mem_1 (
.clk (clk),
.addr(addr),
.in (in[1*`MAT_BRAM_DWIDTH-1:(1-1)*`MA... | 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifdef SIMULATION
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
alway... | 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifdef SIMULATION
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr... | 7.048193 |
module exponent_comparator_tree_ldpe (
input [`BFLOAT_EXP-1:0] inp0,
input [`BFLOAT_EXP-1:0] inp1,
input [`BFLOAT_EXP-1:0] inp2,
input [`BFLOAT_EXP-1:0] inp3,
input [`BFLOAT_EXP-1:0] inp4,
input [`BFLOAT_EXP-1:0] inp5,
input [`BFLOAT_EXP-1:0] inp6,
input [`BFLOAT_EXP-1:0] inp7,
outpu... | 6.772452 |
module exponent_comparator_tree_tile (
input [`BFLOAT_EXP*`NUM_LDPES-1:0] inp0,
input [`BFLOAT_EXP*`NUM_LDPES-1:0] inp1,
output [`BFLOAT_EXP*`NUM_LDPES-1:0] result_final_stage,
output [`NUM_LDPES-1:0] out_data_available,
//CONTROL SIGNALS
input clk,
input [`NUM_LDPES-1:0] reset,
input [... | 6.772452 |
module comparator #(parameter DWIDTH = `BFLOAT_EXP) (
input[DWIDTH-1:0] a,
input[DWIDTH-1:0] b,
input reset,
input start,
input clk,
output reg[DWIDTH-1:0] out,
output reg out_data_available
);
always@(posedge clk) begin
if(reset==1'b1 || start==1'b0) begin
out <= a;
out... | 7.565129 |
module fp16_to_msfp11 (
input clk,
input [15:0] a,
input rst,
input start,
output reg [10:0] b,
output reg out_data_available
);
reg [10:0] b_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[10] = a[15]; //sign bit
b_temp[9:0] = 7'b0000000; //EX... | 8.274172 |
module msfp11_to_fp16 (
input reset,
input start,
input clk,
input [10:0] a,
output reg [15:0] b,
output reg out_data_available
);
reg [15:0] b_temp;
reg [ 3:0] j;
reg [ 2:0] k;
reg [ 2:0] k_temp;
always @(*) begin
if (a[9:0] == 7'b0) begin //signed zero
b_temp[15] = a[... | 6.54771 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`FLO... | 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`FLOAT_DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
inp... | 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bit... | 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [`MANTISSA:0... | 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of sm... | 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`FLOAT_DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`FLOAT_DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since... | 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`FLOAT_DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTIS... | 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round... | 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`FLOAT_DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
... | 7.326377 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`FLOAT_DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`FLOAT_DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Outpu... | 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
outp... | 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
inpu... | 7.570448 |
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