code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bpsk_mod_demod_tb ();
reg clk;
reg rst;
reg [15:0] input_data;
wire [15:0] bpsk_mod_out;
reg read_ready;
BPSK_mod_demod bpsk (
input_data,
bpsk_mod_out
);
initial begin
rst = 1;
rst = 0;
clk = 1;
#20;
forever begin
clk = ~clk;
#20;
end
end
initial begin
forever begin
input_data = 1;
#20;
input_data = 0;
#20;
end
end
endmodule
| 6.722605 |
module bpsk_mod_tb ();
reg clk;
reg rst;
reg [15:0] input_data;
wire [15:0] bpsk_mod_out_re, bpsk_mod_out_im;
BPSK_Modulator_Baseband bpsk_mod (
input_data,
bpsk_mod_out_re,
bpsk_mod_out_im
);
initial begin
rst = 1;
rst = 0;
clk = 1;
#20;
forever begin
clk = ~clk;
#20;
end
end
initial begin
forever begin
input_data = 1;
#20 input_data = 0;
#20;
end
end
endmodule
| 6.703733 |
module BAUD_GEN #(
parameter BAUD_RATE = 16'd9600,
parameter FLL_CNTL_PARAM = 24'd1280000,
parameter FLL_CNTL_FREQ = 16'd100,
parameter BAUD_INITIAL = 24'd96
) (
input wire clk,
input wire nrst,
output reg cntl_clk_out
);
localparam MAX_VCO_CNT = 24'sd65536;
localparam MIN_VCO_CNT = 24'sd16;
wire [23:0] baud_cnt_ref;
assign baud_cnt_ref = BAUD_RATE / FLL_CNTL_FREQ;
reg [23:0] baud_vco;
reg [23:0] baud_vco_cnt_loc;
always @(posedge clk)
if (!nrst) begin
baud_vco_cnt_loc <= 24'h0;
end else begin
if (baud_vco_cnt_loc < FLL_CNTL_PARAM) begin
baud_vco_cnt_loc <= baud_vco_cnt_loc + baud_vco;
cntl_clk_out <= 1'b0;
end else begin
baud_vco_cnt_loc <= baud_vco_cnt_loc - FLL_CNTL_PARAM;
cntl_clk_out <= 1'b1;
end
end
reg [23:0] baud_counter;
reg [23:0] clk_counter;
reg signed [23:0] baud_err;
wire cntl_flag;
assign cntl_flag = (clk_counter == FLL_CNTL_PARAM);
always @(posedge clk)
if (!nrst) begin
baud_counter <= 24'b0;
clk_counter <= 24'b1;
baud_err <= 24'sd0;
end else begin
clk_counter <= clk_counter + 24'h1;
if (cntl_clk_out) begin
baud_counter <= baud_counter + 24'h1;
end
if (clk_counter == FLL_CNTL_PARAM) begin
baud_err <= $signed(baud_cnt_ref) - $signed(baud_counter);
baud_counter <= 24'b0;
clk_counter <= 24'b0;
end
end
wire signed [23:0] baud_err_k, baud_vco_temp;
assign baud_err_k = (baud_err >>> 'd1) + (baud_err >>> 'd2);
assign baud_vco_temp = $signed(baud_vco) + baud_err_k;
always @(posedge clk)
if (!nrst) begin
baud_vco <= BAUD_INITIAL;
end else begin
if (cntl_flag) begin
if (baud_vco_temp >= MAX_VCO_CNT) baud_vco <= $unsigned(MAX_VCO_CNT);
else if (baud_vco_temp <= MIN_VCO_CNT) baud_vco <= $unsigned(MIN_VCO_CNT);
else baud_vco <= $unsigned(baud_vco_temp);
end
end
endmodule
| 7.442923 |
module BPSK_Ctrl #(
parameter integer data_width = 32,
parameter integer frame_length = 38,
parameter integer addr_width = 32,
parameter integer ref_clk_freq = 128000000,
parameter integer baudrate = 9600
) (
input clk, //时钟信号
input rst_n, //复位信号
input send_signal, // send 启动信号
// RAM端口
output ram_clk, //RAM时钟
input [data_width-1 : 0] ram_rd_data, //RAM中读出的数据
output wire ram_en, //RAM使能信号
output reg [addr_width-1 : 0] ram_addr, //RAM地址
output reg [ 3:0] ram_we, //RAM读写控制信号 1写 0读
output reg [data_width-1 : 0] ram_wr_data, //RAM写数据
output reg ram_rst, //RAM复位信号,高电平有效
// phase ctrl
output reg gen_en,
output reg phase_ctrl,
output reg baud
);
wire bit_signal;
wire clk_baud;
reg ram_latch_enable;
reg [data_width-1:0] data;
BAUD_GEN baud_inst (
.clk(clk),
.nrst(rst_n),
.cntl_clk_out(clk_baud)
);
always @(posedge clk) begin
if (!rst_n) baud <= 1'd0;
else if (clk_baud) baud <= ~baud;
end
BITSTREAM_GEN #(
.data_width(data_width)
) bitstream_inst (
.clk(clk),
.nrst(rst_n),
.byte_in(data),
.byte_latch(ram_latch_enable),
.is_empty(ram_en),
.en(clk_baud & send_signal),
.bit_out(bit_signal)
);
assign ram_clk = clk;
reg ram_en_legacy;
always @(posedge clk) begin
if (!rst_n) begin
data <= 32'h0;
ram_addr <= 31'd0;
ram_we <= 4'd0;
ram_wr_data <= 32'd0;
ram_rst <= 1'b0;
end else begin
ram_en_legacy <= ram_en;
if (!ram_en_legacy & ram_en) ram_latch_enable <= 1'b1;
else ram_latch_enable <= 1'b0;
if (ram_latch_enable) begin
if (ram_addr == 32'd152 - 32'd4)
ram_addr <= 32'd0; // 这里虽然是32位一个字, 但是寻址还是8bit的!!
else ram_addr <= ram_addr + 32'd4;
end
data <= ram_rd_data;
end
end
always @(posedge clk)
if (!rst_n) begin
phase_ctrl <= 1'b0;
end else begin
if (bit_signal & clk_baud) phase_ctrl <= ~phase_ctrl;
gen_en <= send_signal;
end
endmodule
| 7.219228 |
module BAUD_GEN #(
parameter BAUD_RATE = 16'd9600,
parameter FLL_CNTL_PARAM = 24'd1280000,
parameter FLL_CNTL_FREQ = 16'd100,
parameter BAUD_INITIAL = 24'd96
) (
input wire clk,
input wire nrst,
output reg cntl_clk_out
);
localparam MAX_VCO_CNT = 24'sd65536;
localparam MIN_VCO_CNT = 24'sd16;
wire [23:0] baud_cnt_ref;
assign baud_cnt_ref = BAUD_RATE / FLL_CNTL_FREQ;
reg [23:0] baud_vco;
reg [23:0] baud_vco_cnt_loc;
always @(posedge clk)
if (!nrst) begin
baud_vco_cnt_loc <= 24'h0;
end else begin
if (baud_vco_cnt_loc < FLL_CNTL_PARAM) begin
baud_vco_cnt_loc <= baud_vco_cnt_loc + baud_vco;
cntl_clk_out <= 1'b0;
end else begin
baud_vco_cnt_loc <= baud_vco_cnt_loc - FLL_CNTL_PARAM;
cntl_clk_out <= 1'b1;
end
end
reg [23:0] baud_counter;
reg [23:0] clk_counter;
reg signed [23:0] baud_err;
wire cntl_flag;
assign cntl_flag = (clk_counter == FLL_CNTL_PARAM);
always @(posedge clk)
if (!nrst) begin
baud_counter <= 24'b0;
clk_counter <= 24'b1;
baud_err <= 24'sd0;
end else begin
clk_counter <= clk_counter + 24'h1;
if (cntl_clk_out) begin
baud_counter <= baud_counter + 24'h1;
end
if (clk_counter == FLL_CNTL_PARAM) begin
baud_err <= $signed(baud_cnt_ref) - $signed(baud_counter);
baud_counter <= 24'b0;
clk_counter <= 24'b0;
end
end
wire signed [23:0] baud_err_k, baud_vco_temp;
assign baud_err_k = (baud_err >>> 'd1) + (baud_err >>> 'd2);
assign baud_vco_temp = $signed(baud_vco) + baud_err_k;
always @(posedge clk)
if (!nrst) begin
baud_vco <= BAUD_INITIAL;
end else begin
if (cntl_flag) begin
if (baud_vco_temp >= MAX_VCO_CNT) baud_vco <= $unsigned(MAX_VCO_CNT);
else if (baud_vco_temp <= MIN_VCO_CNT) baud_vco <= $unsigned(MIN_VCO_CNT);
else baud_vco <= $unsigned(baud_vco_temp);
end
end
endmodule
| 7.442923 |
module BPSK_Ctrl #(
parameter integer data_width = 32,
parameter integer frame_length = 38,
parameter integer addr_width = 32,
parameter integer ref_clk_freq = 128000000,
parameter integer baudrate = 9600
) (
input clk, //ʱź
input rst_n, //λź
input power_on, //=1ʱ, ֡
// RAM˿
output ram_clk, //RAMʱ
input [data_width-1 : 0] ram_rd_data, //RAMж
output wire ram_en, //RAMʹź
output reg [addr_width-1 : 0] ram_addr, //RAMַ
output reg [ 3:0] ram_we, //RAMдź 1д 0
output reg [data_width-1 : 0] ram_wr_data, //RAMд
output reg ram_rst, //RAMλź,ߵƽЧ
// ˫ ˫ ʵ4KramĿռ, Ϊ 0~148Ϊ֡ 256~404Ϊram1 512~660Ϊram2
input [1:0] dual_ram_num, //01b=ʹram1 10b=ʹram2 00b=֡ram0
output [1:0] interrupt_num, // 01b=ʹram1 10b=ʹram2
// phase ctrl
output reg gen_en,
output reg phase_ctrl,
output reg baud
);
localparam EMPTY_FRAME_BASEADDR = 32'h0;
localparam RAM1_BASEADDR = 32'h100;
localparam RAM2_BASEADDR = 32'h200;
wire bit_signal;
wire clk_baud;
reg ram_latch_enable;
reg [data_width-1:0] data;
BAUD_GEN baud_inst (
.clk(clk),
.nrst(rst_n),
.cntl_clk_out(clk_baud)
);
// ｫһ4800kź,
always @(posedge clk) begin
if (!rst_n) baud <= 1'd0;
else if (clk_baud) baud <= ~baud;
end
BITSTREAM_GEN #(
.data_width(data_width)
) bitstream_inst (
.clk(clk),
.nrst(rst_n),
.byte_in(data),
.byte_latch(ram_latch_enable),
.is_empty(ram_en),
.en(clk_baud & power_on),
.bit_out(bit_signal)
);
assign ram_clk = clk;
reg ram_en_legacy;
always @(posedge clk) begin
if (!rst_n) begin
data <= 32'h0;
ram_addr <= 32'd0;
ram_we <= 4'd0;
ram_wr_data <= 32'd0;
ram_rst <= 1'b0;
end else begin
ram_en_legacy <= ram_en;
if (!ram_en_legacy & ram_en) ram_latch_enable <= 1'b1;
else ram_latch_enable <= 1'b0;
if (ram_latch_enable) begin
if (ram_addr == 32'd152-32'd4 || ram_addr == RAM1_BASEADDR+32'd152-32'd4 || ram_addr == RAM2_BASEADDR+32'd152-32'd4) begin
case (dual_ram_num) //01b=ʹram1 10b=ʹram2 00b=֡ram0
2'b00: ram_addr <= EMPTY_FRAME_BASEADDR;
2'b01: ram_addr <= RAM1_BASEADDR;
2'b10: ram_addr <= RAM2_BASEADDR;
default: ram_addr <= EMPTY_FRAME_BASEADDR;
endcase
end else ram_addr <= ram_addr + 32'd4; // Ȼ32λһ, Ѱַ8bit!!
end
data <= ram_rd_data;
end
end
// жź, жźŻһ֡ij, źŽʱ(½)ʱʵʵݻûз,ʱлramַû.
wire interrupt_ram1;
wire interrupt_ram2;
assign interrupt_ram1 = (ram_addr == RAM1_BASEADDR + 32'd152 - 32'd4) && power_on;
assign interrupt_ram2 = (ram_addr == RAM2_BASEADDR + 32'd152 - 32'd4) && power_on;
assign interrupt_num = {interrupt_ram2, interrupt_ram1};
always @(posedge clk)
if (!rst_n) begin
phase_ctrl <= 1'b0;
end else begin
if (bit_signal & clk_baud) phase_ctrl <= ~phase_ctrl;
gen_en <= power_on;
end
endmodule
| 7.219228 |
module BAUD_GEN #(
parameter BAUD_RATE = 16'd9600,
parameter FLL_CNTL_PARAM = 24'd1280000,
parameter FLL_CNTL_FREQ = 16'd100,
parameter BAUD_INITIAL = 24'd96
) (
input wire clk,
input wire nrst,
output reg cntl_clk_out
);
localparam MAX_VCO_CNT = 24'sd65536;
localparam MIN_VCO_CNT = 24'sd16;
wire [23:0] baud_cnt_ref;
assign baud_cnt_ref = BAUD_RATE / FLL_CNTL_FREQ;
reg [23:0] baud_vco;
reg [23:0] baud_vco_cnt_loc;
always @(posedge clk)
if (!nrst) begin
baud_vco_cnt_loc <= 24'h0;
end else begin
if (baud_vco_cnt_loc < FLL_CNTL_PARAM) begin
baud_vco_cnt_loc <= baud_vco_cnt_loc + baud_vco;
cntl_clk_out <= 1'b0;
end else begin
baud_vco_cnt_loc <= baud_vco_cnt_loc - FLL_CNTL_PARAM;
cntl_clk_out <= 1'b1;
end
end
reg [23:0] baud_counter;
reg [23:0] clk_counter;
reg signed [23:0] baud_err;
wire cntl_flag;
assign cntl_flag = (clk_counter == FLL_CNTL_PARAM);
always @(posedge clk)
if (!nrst) begin
baud_counter <= 24'b0;
clk_counter <= 24'b1;
baud_err <= 24'sd0;
end else begin
clk_counter <= clk_counter + 24'h1;
if (cntl_clk_out) begin
baud_counter <= baud_counter + 24'h1;
end
if (clk_counter == FLL_CNTL_PARAM) begin
baud_err <= $signed(baud_cnt_ref) - $signed(baud_counter);
baud_counter <= 24'b0;
clk_counter <= 24'b0;
end
end
wire signed [23:0] baud_err_k, baud_vco_temp;
assign baud_err_k = (baud_err >>> 'd1) + (baud_err >>> 'd2);
assign baud_vco_temp = $signed(baud_vco) + baud_err_k;
always @(posedge clk)
if (!nrst) begin
baud_vco <= BAUD_INITIAL;
end else begin
if (cntl_flag) begin
if (baud_vco_temp >= MAX_VCO_CNT) baud_vco <= $unsigned(MAX_VCO_CNT);
else if (baud_vco_temp <= MIN_VCO_CNT) baud_vco <= $unsigned(MIN_VCO_CNT);
else baud_vco <= $unsigned(baud_vco_temp);
end
end
endmodule
| 7.442923 |
module BPSK_Ctrl #(
parameter integer data_width = 8,
parameter integer frame_length = 150,
parameter integer addr_width = 8,
parameter integer ref_clk_freq = 128000000,
parameter integer baudrate = 9600
) (
input clk, //ʱź
input rst_n, //λź
input send_signal, // send ź
// RAM˿
output ram_clk, //RAMʱ
input [data_width-1 : 0] ram_rd_data, //RAMж
output wire ram_en, //RAMʹź
output reg [addr_width-1 : 0] ram_addr, //RAMַ
output reg [ 0:0] ram_we, //RAMдź 1д 0
output reg [data_width-1 : 0] ram_wr_data, //RAMд
output reg ram_rst, //RAMλź,ߵƽЧ
// phase ctrl
output reg gen_en,
output reg phase_ctrl
);
wire bit_signal;
wire clk_baud;
reg ram_latch_enable;
reg [7:0] data;
BAUD_GEN baud_inst (
.clk(clk),
.nrst(rst_n),
.cntl_clk_out(clk_baud)
);
BITSTREAM_GEN bitstream_inst (
.clk(clk),
.nrst(rst_n),
.byte_in(data),
.byte_latch(ram_latch_enable),
.is_empty(ram_en),
.en(clk_baud & send_signal),
.bit_out(bit_signal)
);
assign ram_clk = clk;
reg ram_en_legacy;
always @(posedge clk) begin
if (!rst_n) begin
data <= 8'h0;
ram_addr <= 8'd0;
ram_we <= 4'd0;
ram_wr_data <= 8'd0;
ram_rst <= 1'b0;
end else begin
ram_en_legacy <= ram_en;
if (!ram_en_legacy & ram_en) ram_latch_enable <= 1'b1;
else ram_latch_enable <= 1'b0;
if (ram_latch_enable) begin
if (ram_addr == 8'd149) ram_addr <= 8'd0;
else ram_addr <= ram_addr + 8'd1;
end
data <= ram_rd_data;
end
end
always @(posedge clk)
if (!rst_n) begin
phase_ctrl <= 1'b0;
end else begin
if (bit_signal & clk_baud) phase_ctrl <= ~phase_ctrl;
gen_en <= send_signal;
end
endmodule
| 7.219228 |
module bpsk_top (
input sys_clk,
input rst_n,
output reg a
);
wire en;
wire clk_50m;
wire rst_global;
wire locked;
wire code;
wire code_vld;
wire cos_vld;
(* MARK_DEBUG="true" *)wire [15:0] cos_o;
(* MARK_DEBUG="true" *)wire [23:0] fir_out;
(* MARK_DEBUG="true" *)wire signed [ 1:0] code_c;
(* MARK_DEBUG="true" *)wire signed [23:0] duc_data;
assign rst_global = ~rst_n || ~locked;
clk_wiz_0 clk_inst (
// Clock out portsen_generator en_inst
.clk_out1(clk_50m), // output clk_out1(
// Status and control signals.clk(clk),
.reset (~rst_n), // input reset.rst(rst),
.locked (locked), // output locked
// Clock in ports.start(1'b1),
.clk_in1 (sys_clk) // input clk_in1.en (en)
);
(* keep_hierarchy="yes" *)
en_generator #(
.INTERVAL(50)
) en_inst (
.clk (clk_50m),
.rst (rst_global),
.start(1'b1),
.en (en)
);
(* keep_hierarchy="yes" *)
m_seq m_inst (
.clk(clk_50m),
.rst(rst_global),
.en (en) ,
.data_out(code) ,
.data_vld(code_vld)
);
code_change code_inst (
.code (code),
.code_o(code_c)
);
fir_compiler_0 fir_inst (
.aclk(clk_50m), // input wire aclk
.s_axis_data_tvalid(1'b1), // input wire s_axis_data_tvalid
.s_axis_data_tready(), // output wire s_axis_data_tready
.s_axis_data_tdata({{6{code_c[1]}}, code_c}), // input wire [7 : 0] s_axis_data_tdata
.m_axis_data_tvalid(), // output wire m_axis_data_tvalid
.m_axis_data_tdata(fir_out) // output wire [23 : 0] m_axis_data_tdata 19-8
);
dds_compiler_0 dds_inst (
.aclk (clk_50m), // input wire aclk
.m_axis_data_tvalid (), // output wire m_axis_data_tvalid
.m_axis_data_tdata (cos_o), // output wire [15 : 0] m_axis_data_tdata 13 - 2
.m_axis_phase_tvalid(), // output wire m_axis_phase_tvalid
.m_axis_phase_tdata () // output wire [31 : 0] m_axis_phase_tdata
);
xbip_dsp48_macro_0 dsp_product_inst (
.CLK(clk_50m), // input wire CLK
.A (fir_out[19:8]), // input wire [11 : 0] A
.B (cos_o[13:2]), // input wire [11 : 0] B
.P (duc_data) // output wire [23 : 0] P
);
endmodule
| 6.568313 |
module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module bps_module(
sysclk,
rst_n,
count_sig,
clk_bps
);
input sysclk;
input rst_n;
input count_sig;
output clk_bps;
//115200波特率 => 每个bit占用时间为 1/115200s
//50MHz sysclk计数为 50 * 10^6 * 1/115200 = 434
//在每个bit的中间时间点采样数据 即[0 216] clk_bps为低; [217 433]为高
reg [8:0]count;
always @(posedge sysclk or negedge rst_n) begin
if (!rst_n)
count <= 9'd0;
else if (count == 9'd433)
count <= 9'd0;
else if (count_sig)
count <= count + 1'b1;
else
count <= 9'd0;
end
assign clk_bps = (count == 9'd216) ? 1'b1 : 1'b0;
endmodule
| 7.088073 |
module Bps_select (
input clk, //系统时钟50MHz
input rst_n, //低电平复位
input en, //使能信号：串口接收活发送开始
output reg sel_data, //波特率计数中心点（采集数据的使能信号）
output reg [3:0] num //一帧数据bit0~bit9
);
parameter bps_div = 13'd5207, //(1/9600*1000000*1000/20)
bps_div2 = 13'd2603;
//发送/接收标志位：接收到使能信号en后，将标志位flag拉高，当计数信号num记完一帧数据后将flag拉低
reg flag;
always @(posedge clk or negedge rst_n)
if (!rst_n) flag <= 0;
else if (en) flag <= 1;
else if (num == 4'd10) //计数完成？
flag <= 0;
//波特率计数
reg [12:0] cnt;
always @(posedge clk or negedge rst_n)
if (!rst_n) cnt <= 13'd0;
else if (flag && cnt < bps_div) cnt <= cnt + 1'b1;
else cnt <= 13'd0;
//规定发送数据和接收数据的范围：一帧数据为10bit：1bit开始位+8bit数据位+1bit停止位
always @(posedge clk or negedge rst_n)
if (!rst_n) num <= 4'd0;
else if (flag && sel_data) num <= num + 1'b1;
else if (num == 4'd10) num <= 1'd0;
//数据在波特率的中间部分采集，即：发送/接收数据的使能信号
always @(posedge clk or negedge rst_n)
if (!rst_n) sel_data <= 1'b0;
else
if(cnt == bps_div2) //中间取数是为了产生尖峰脉冲，尖峰脉冲为采集数据使能信号，用来把握速率
sel_data <= 1'b1;
else sel_data <= 1'b0;
endmodule
| 7.598806 |
module bps_set (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd434; //(50_000_000/9600)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (bps_start) cnt_bps <= cnt_bps + 1'b1;
else cnt_bps <= 1'b0;
end
assign bps_clk = (cnt_bps == 13'd217) ? 1'b1 : 1'b0;
endmodule
| 6.864722 |
module bps_set_115200 (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd434; //(50_000_000/115200)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (bps_start) cnt_bps <= cnt_bps + 1'b1;
else cnt_bps <= 1'b0;
end
assign bps_clk = (cnt_bps == 13'd217) ? 1'b1 : 1'b0;
endmodule
| 7.078796 |
module bps_set_57600 (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd868; //(50_000_000/57600)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (bps_start) cnt_bps <= cnt_bps + 1'b1;
else cnt_bps <= 1'b0;
end
assign bps_clk = (cnt_bps == 13'd434) ? 1'b1 : 1'b0; //868/2=434
endmodule
| 7.380604 |
module bps_set_9600 (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd5208; //(50_000_000/9600)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (bps_start) cnt_bps <= cnt_bps + 1'b1;
else cnt_bps <= 1'b0;
end
assign bps_clk = (cnt_bps == 13'd2604) ? 1'b1 : 1'b0;
endmodule
| 6.571904 |
module bps_set_lora (
input clk,
input rst_n,
input bps_start,
output bps_clk
);
reg [12:0] cnt_bps;
parameter bps = 13'd434; //(50_000_000/9600)
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt_bps <= 13'd0;
else if (cnt_bps == bps - 1'b1) cnt_bps <= 13'd0;
else if (bps_start) cnt_bps <= cnt_bps + 1'b1;
else cnt_bps <= 1'b0;
end
assign bps_clk = (cnt_bps == 13'd217) ? 1'b1 : 1'b0;
endmodule
| 8.040765 |
module BPS_timer
//----------------------------------------------------------------
// Params
//----------------------------------------------------------------
#(
parameter CLK_rate = 100000000,
parameter Baud_rate = 9600
)
//----------------------------------------------------------------
// Ports
//----------------------------------------------------------------
(
clk_i
, clk_BPS_o
);
// Inputs
input clk_i;
// Outputs
output reg clk_BPS_o = 0;
//----------------------------------------------------------------
// Registers / Wires
//----------------------------------------------------------------
reg [12:0] BPS_counter = 0;
//----------------------------------------------------------------
// Circuits
//----------------------------------------------------------------
always @(posedge clk_i) begin
if (BPS_counter == (CLK_rate / Baud_rate / 2 - 1)) begin
clk_BPS_o = ~clk_BPS_o;
BPS_counter = 0;
end else BPS_counter = BPS_counter + 1;
end
endmodule
| 6.728591 |
module BPU (
in_PC,
in_hit,
in_Clk,
in_Rst_N,
out_prediction
);
input in_Clk, in_Rst_N;
input [1:0] in_hit; // LSB defines if predictor 0 hit or not, MSB defines if predictor 1 hit or not
input [8:0] in_PC;
output out_prediction;
wire predictor_selector_Out, bimodal_prediction, gshare_prediction;
assign out_prediction = (predictor_selector_Out) ? gshare_prediction : bimodal_prediction;
predictor_sel predictor_sel_Inst0 (
.in_hit(in_hit),
.in_Clk(in_Clk),
.in_Rst_N(in_Rst_N),
.out_selection(predictor_selector_Out)
);
bimodal bimodal_Inst0 (
.in_PC(in_PC),
.in_hit(in_hit[0]),
.in_Clk(in_Clk),
.in_Rst_N(in_Clk),
.out_prediction(bimodal_prediction)
);
gshare gshare_Inst0 (
.in_PC(in_PC),
.in_hit(in_hit[1]),
.in_Clk(in_Clk),
.in_Rst_N(in_Rst_N),
.out_prediction(gshare_prediction)
);
endmodule
| 7.844936 |
module BPU_AP (
input wire i_clk,
input wire i_rstn,
input wire i_stop, //暂停,保持指令不变输出
input wire i_flush, //冲刷
input wire i_data_vld, //取指读出的数据是否有效
input wire [`xlen_def] i_iaddr, //数据地址
input wire [`ilen_def] i_data, //数据地址舍去低2位后的数据
output wire o_inst_vld, //对齐处理完成,已经是可译码的指令
output wire [`xlen_def] o_inst_pc, //指令pc
output wire [`ilen_def] o_inst //对齐处理后的指令
);
reg [15:0] leftover_buffer; //16位剩余缓存
reg leftover_ok; //剩余缓存是否保存有数据
reg[`xlen_def] last_iaddr;//上次读取的地址,合并上次数据与当前数据后的指令的地址仍为上次的数据地址
//地址的最后2位代表对齐模式,这里只处理16位对齐，只需要第2位即可
wire align16_mode = i_iaddr[1] | leftover_ok;
always @(posedge i_clk or negedge i_rstn) begin
if (~i_rstn) begin
leftover_ok <= 0;
end else if (i_flush) begin
leftover_ok <= 0;
end else if (i_data_vld & (~i_stop)) begin //读取的数据有效
last_iaddr <= i_iaddr;
if (align16_mode) begin
leftover_ok <= 1;
leftover_buffer <= i_data[31:16];
end else begin
leftover_ok <= 0;
end
end
end
assign o_inst_vld = align16_mode ? leftover_ok & i_data_vld : i_data_vld;
assign o_inst_pc = align16_mode ? last_iaddr : i_iaddr; //指令pc
assign o_inst = align16_mode ? {i_data[15:0], leftover_buffer} : i_data;
endmodule
| 7.875057 |
module BPU_BP (
input wire i_clk,
input wire i_rstn,
//预译码信息
input wire [`xlen_def] i_pc, //当前分支指令pc值
input wire i_inst_jal,
input wire i_inst_jalr,
input wire i_inst_rs1ren, //jalr 需要读rs1
input wire i_inst_bxx,
input wire [`xlen_def] i_imm, //立即数
input wire [`xlen_def] i_jalr_rs1rdata, //jalr rs1读取的值
//允许进行跳转
output wire o_prdt_taken,
output wire [`xlen_def] o_prdt_pc //预分支地址
);
//如果是jal，则直接跳转,如果是bxx，立即数为负则跳转
//对于jalr,如果rs1=0,直接跳转跳转或者不存在jalr rs1读冲突
assign o_prdt_taken = i_inst_jalr | i_inst_jal | (i_inst_bxx & i_imm[`xlen-1]);
//rs1+imm或者pc+imm
assign o_prdt_pc = i_inst_jalr ? (i_inst_rs1ren ? i_jalr_rs1rdata + i_imm : i_imm) : i_pc + i_imm;
//i_inst_rs1ren ? i_imm : ((i_inst_jalr ? i_jalr_rs1rdata : i_pc) + i_imm);
endmodule
| 7.768984 |
module bp_be_bypass
import bp_common_rv64_pkg::*;
#(
parameter depth_p = "inv"
, parameter els_p = "inv"
, parameter zero_x0_p = 0
// Generated params
, localparam reg_addr_width_lp = rv64_reg_addr_width_gp
, localparam reg_data_width_lp = rv64_reg_data_width_gp
) (
// Dispatched instruction operands
input [els_p-1:0][reg_addr_width_lp-1:0] id_addr_i
, input [els_p-1:0][reg_data_width_lp-1:0] id_i
// Completed rd writes in the pipeline
, input [depth_p-1:0] fwd_rd_v_i
, input [depth_p-1:0][reg_addr_width_lp-1:0] fwd_rd_addr_i
, input [depth_p-1:0][reg_data_width_lp-1:0] fwd_rd_i
// The latest valid rs1, rs2 data
, output [els_p-1:0][reg_data_width_lp-1:0] bypass_o
);
// synopsys translate_off
initial begin : parameter_validation
assert (depth_p > 0 && depth_p != "inv")
else $error("depth_p must be positive, else there is nothing to bypass. \
Did you remember to set it?");
end
// synopsys translate_on
// Intermediate connections
logic [els_p-1:0][ depth_p:0] match_vector;
logic [els_p-1:0][ depth_p:0] match_vector_onehot;
logic [els_p-1:0][ depth_p:0][reg_data_width_lp-1:0] data_vector;
logic [els_p-1:0][reg_data_width_lp-1:0] bypass_lo;
// Datapath
for (genvar j = 0; j < els_p; j++) begin : els
// Find the youngest valid data to forward
bsg_priority_encode_one_hot_out #(
.width_p(depth_p + 1)
, .lo_to_hi_p(1)
) match_one_hot (
.i(match_vector[j])
, .o(match_vector_onehot[j])
);
// Bypass data with a simple crossbar
// Completion data has priority over dispatched data, so dispatched data goes to MSB
bsg_crossbar_o_by_i #(
.i_els_p(depth_p + 1)
, .o_els_p(1)
, .width_p(reg_data_width_lp)
) crossbar (
.i({id_i[j], fwd_rd_i})
, .sel_oi_one_hot_i(match_vector_onehot[j])
, .o(bypass_lo[j])
);
assign bypass_o[j] = ((zero_x0_p == 1) & (id_addr_i[j] == '0)) ? '0 : bypass_lo[j];
end
always_comb
for (integer j = 0; j < els_p; j++)
for (integer i = 0; i < depth_p + 1; i++)
// Dispatched data always matches the dispatched data, otherwise check for:
// * Register address match
// * The completing instruction is writing and the dispatched instruction is reading
// * Do not forward x0 data, RISC-V defines this as always 0
match_vector[j][i] = ((i == depth_p) || ((id_addr_i[j] == fwd_rd_addr_i[i]) & fwd_rd_v_i[i]));
endmodule
| 7.725144 |
module bp_be_fp_to_rec
import bp_common_pkg::*;
import bp_common_rv64_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_be_hardfloat_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
)
(// RAW floating point input
input [dword_width_p-1:0] raw_i
// Precision of the raw input value
, input raw_sp_not_dp_i
, output rec_sp_not_dp_o
, output [dp_rec_width_gp-1:0] rec_o
);
// The control bits control tininess, which is fixed in RISC-V
wire [`floatControlWidth-1:0] control_li = `flControl_default;
// We also convert from 32 bit inputs to 64 bit recoded inputs.
// This double rounding behavior was formally proved correct in
// "Innocuous Double Rounding of Basic Arithmetic Operations" by Pierre Roux
bp_hardfloat_rec_sp_s in_sp_rec_li;
wire [sp_float_width_gp-1:0] in_sp_li = raw_i[0+:sp_float_width_gp];
fNToRecFN
#(.expWidth(sp_exp_width_gp)
,.sigWidth(sp_sig_width_gp)
)
in32_rec
(.in(in_sp_li)
,.out(in_sp_rec_li)
);
bp_hardfloat_rec_dp_s in_dp_rec_li;
wire [dp_float_width_gp-1:0] in_dp_li = raw_i[0+:dp_float_width_gp];
fNToRecFN
#(.expWidth(dp_exp_width_gp)
,.sigWidth(dp_sig_width_gp)
)
in64_rec
(.in(in_dp_li)
,.out(in_dp_rec_li)
);
//
// Unsafe upconvert
//
localparam bias_adj_lp = (1 << dp_exp_width_gp) - (1 << sp_exp_width_gp);
bp_hardfloat_rec_sp_s sp_rec;
bp_hardfloat_rec_dp_s sp2dp_rec;
assign sp_rec = in_sp_rec_li;
wire [dp_exp_width_gp:0] adjusted_exp = sp_rec.exp + bias_adj_lp;
wire [2:0] exp_code = sp_rec.exp[sp_exp_width_gp-:3];
wire special = (exp_code == '0) || (exp_code >= 3'd6);
assign sp2dp_rec = '{sign : sp_rec.sign
,exp : special ? {exp_code, adjusted_exp[0+:dp_exp_width_gp-2]} : adjusted_exp
,fract: sp_rec.fract << (dp_sig_width_gp-sp_sig_width_gp)
};
wire nanbox_v_li = &raw_i[word_width_p+:word_width_p];
wire encode_as_sp = nanbox_v_li | raw_sp_not_dp_i;
assign rec_sp_not_dp_o = encode_as_sp;
assign rec_o = encode_as_sp ? sp2dp_rec : in_dp_rec_li;
endmodule
| 9.910358 |
module bp_be_mock_ptw
import bp_common_pkg::*;
import bp_be_pkg::*;
#(parameter vtag_width_p="inv"
,parameter ptag_width_p="inv"
,localparam entry_width_lp = `bp_be_tlb_entry_width(ptag_width_p)
)
(input clk_i
, input reset_i
, input miss_v_i
, input [vtag_width_p-1:0] vtag_i
, output logic v_o
, output logic [vtag_width_p-1:0] vtag_o
, output logic [entry_width_lp-1:0] entry_o
);
`declare_bp_be_tlb_entry_s(ptag_width_p);
typedef enum [1:0] { eWait, eBusy, eDone, eStuck } state_e;
state_e state, state_n;
bp_be_tlb_entry_s entry_n;
assign entry_n.ptag = {(ptag_width_p-vtag_width_p)'(0), vtag_i};
assign entry_n.extent = '0;
assign entry_n.u = '0;
assign entry_n.g = '0;
assign entry_n.l = '0;
assign entry_n.x = '0;
assign rdy_o = (state == eWait);
assign v_o = (state == eDone);
logic [7:0] counter;
always_ff @(posedge clk_i) begin
if(reset_i) begin
state <= eWait;
counter <= '0;
end
else begin
state <= state_n;
counter <= counter + 'b1;
end
end
always_comb begin
case(state)
eWait: state_n = (miss_v_i)? eBusy : eWait;
eBusy: state_n = (counter == '0)? eDone : eBusy;
eDone: state_n = (miss_v_i)? eWait : eDone;
default: state_n = eStuck;
endcase
end
bsg_dff_reset_en #(.width_p(vtag_width_p))
vtag_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(miss_v_i)
,.data_i(vtag_i)
,.data_o(vtag_o)
);
bsg_dff_reset_en #(.width_p(entry_width_lp))
entry_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(miss_v_i)
,.data_i(entry_n)
,.data_o(entry_o)
);
endmodule
| 6.85684 |
module bp_be_pipe_ctl
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
import bp_be_dcache_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
, localparam dispatch_pkt_width_lp = `bp_be_dispatch_pkt_width(vaddr_width_p)
, localparam branch_pkt_width_lp = `bp_be_branch_pkt_width(vaddr_width_p)
)
(input clk_i
, input reset_i
, input [dispatch_pkt_width_lp-1:0] reservation_i
, input flush_i
, output [dpath_width_p-1:0] data_o
, output [branch_pkt_width_lp-1:0] br_pkt_o
, output v_o
);
// Suppress unused signal warning
wire unused0 = clk_i;
wire unused1 = reset_i;
`declare_bp_be_internal_if_structs(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p);
bp_be_dispatch_pkt_s reservation;
bp_be_decode_s decode;
bp_be_branch_pkt_s br_pkt;
assign reservation = reservation_i;
assign decode = reservation.decode;
wire [vaddr_width_p-1:0] pc = reservation.pc[0+:vaddr_width_p];
wire [dword_width_p-1:0] rs1 = reservation.rs1[0+:dword_width_p];
wire [dword_width_p-1:0] rs2 = reservation.rs2[0+:dword_width_p];
wire [dword_width_p-1:0] imm = reservation.imm[0+:dword_width_p];
assign br_pkt_o = br_pkt;
logic btaken;
always_comb
if (decode.pipe_ctl_v)
case (decode.fu_op)
e_ctrl_op_beq : btaken = (rs1 == rs2);
e_ctrl_op_bne : btaken = (rs1 != rs2);
e_ctrl_op_blt : btaken = ($signed(rs1) < $signed(rs2));
e_ctrl_op_bltu : btaken = (rs1 < rs2);
e_ctrl_op_bge : btaken = ($signed(rs1) >= $signed(rs2));
e_ctrl_op_bgeu : btaken = rs1 >= rs2;
e_ctrl_op_jalr
,e_ctrl_op_jal : btaken = 1'b1;
default : btaken = 1'b0;
endcase
else
begin
btaken = 1'b0;
end
wire [vaddr_width_p-1:0] baddr = decode.baddr_sel ? rs1 : pc;
wire [vaddr_width_p-1:0] taken_tgt = baddr + imm;
wire [vaddr_width_p-1:0] ntaken_tgt = pc + 4'd4;
assign data_o = vaddr_width_p'($signed(ntaken_tgt));
assign v_o = reservation.v & ~reservation.poison & reservation.decode.pipe_ctl_v;
assign br_pkt.v = reservation.v & ~reservation.poison & ~flush_i;
assign br_pkt.branch = reservation.v & ~reservation.poison & reservation.decode.pipe_ctl_v;
assign br_pkt.btaken = reservation.v & ~reservation.poison & reservation.decode.pipe_ctl_v & btaken;
assign br_pkt.npc = btaken ? {taken_tgt[vaddr_width_p-1:1], 1'b0} : ntaken_tgt;
endmodule
| 7.186845 |
module bp_be_pipe_int
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
#(
parameter vaddr_width_p = "inv"
// Generated parameters
, localparam decode_width_lp = `bp_be_decode_width
, localparam exception_width_lp = `bp_be_exception_width
// From RISC-V specifications
, localparam reg_data_width_lp = rv64_reg_data_width_gp
, localparam reg_addr_width_lp = rv64_reg_addr_width_gp
) (
input clk_i
, input reset_i
// Common pipeline interface
, input [ decode_width_lp-1:0] decode_i
, input [ vaddr_width_p-1:0] pc_i
, input [reg_data_width_lp-1:0] rs1_i
, input [reg_data_width_lp-1:0] rs2_i
, input [reg_data_width_lp-1:0] imm_i
// Pipeline results
, output [reg_data_width_lp-1:0] data_o
, output [vaddr_width_p-1:0] br_tgt_o
);
// Cast input and output ports
bp_be_decode_s decode;
assign decode = decode_i;
// Suppress unused signal warning
wire unused0 = clk_i;
wire unused1 = reset_i;
// Sign-extend PC for calculation
wire [reg_data_width_lp-1:0] pc_sext_li = reg_data_width_lp'($signed(pc_i));
// Submodule connections
logic [reg_data_width_lp-1:0] src1, src2, baddr, alu_result;
logic [reg_data_width_lp-1:0] pc_plus4;
logic [reg_data_width_lp-1:0] data_lo;
// Perform the actual ALU computation
bp_be_int_alu alu (
.src1_i(src1)
, .src2_i(src2)
, .op_i(decode.fu_op)
, .opw_v_i(decode.opw_v)
, .result_o(alu_result)
);
always_comb begin
src1 = decode.src1_sel ? pc_sext_li : rs1_i;
src2 = decode.src2_sel ? imm_i : rs2_i;
baddr = decode.baddr_sel ? src1 : pc_sext_li;
pc_plus4 = pc_sext_li + reg_data_width_lp'(4);
end
assign data_o = decode.result_sel ? pc_plus4 : alu_result;
// TODO: Split into branch unit, will break other pipelines if pc+4 is data gated
wire btaken = (decode.br_v & alu_result[0]) | decode.jmp_v;
assign br_tgt_o = (decode.pipe_int_v & btaken) ? baddr + imm_i : pc_plus4;
endmodule
| 8.733076 |
module bp_be_pipe_long
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
, localparam wb_pkt_width_lp = `bp_be_wb_pkt_width(vaddr_width_p)
, localparam decode_width_lp = `bp_be_decode_width
, localparam word_width_lp = rv64_word_width_gp
)
(input clk_i
, input reset_i
, input [decode_width_lp-1:0] decode_i
, input [instr_width_p-1:0] instr_i
, input [dword_width_p-1:0] rs1_i
, input [dword_width_p-1:0] rs2_i
, input v_i
, output ready_o
, input flush_i
, output [wb_pkt_width_lp-1:0] wb_pkt_o
, output v_o
);
`declare_bp_be_internal_if_structs(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p);
bp_be_decode_s decode;
rv64_instr_s instr;
bp_be_wb_pkt_s wb_pkt;
assign decode = decode_i;
assign instr = instr_i;
assign wb_pkt_o = wb_pkt;
wire signed_div_li = decode.fu_op inside {e_mul_op_div, e_mul_op_rem};
wire rem_not_div_li = decode.fu_op inside {e_mul_op_rem, e_mul_op_remu};
logic [dword_width_p-1:0] op_a, op_b;
always_comb
begin
op_a = rs1_i;
op_b = rs2_i;
unique case (decode.fu_op)
`RV64_DIVW, `RV64_REMW:
begin
op_a = $signed(rs1_i[0+:word_width_lp]);
op_b = $signed(rs2_i[0+:word_width_lp]);
end
`RV64_DIVUW, `RV64_REMUW:
begin
op_a = rs1_i[0+:word_width_lp];
op_b = rs2_i[0+:word_width_lp];
end
default : begin end
endcase
end
// We actual could exit early here
logic [dword_width_p-1:0] quotient_lo, remainder_lo;
logic idiv_ready_lo;
logic v_lo;
bsg_idiv_iterative
#(.width_p(dword_width_p))
idiv
(.clk_i(clk_i)
,.reset_i(reset_i)
,.dividend_i(op_a)
,.divisor_i(op_b)
,.signed_div_i(signed_div_li)
,.v_i(v_i)
,.ready_o(idiv_ready_lo)
,.quotient_o(quotient_lo)
,.remainder_o(remainder_lo)
,.v_o(v_lo)
// Because we currently freeze the pipe while a long latency op is executing,
// we ack immediately
,.yumi_i(v_lo)
);
logic opw_v_r;
bp_be_fu_op_s fu_op_r;
logic [reg_addr_width_p-1:0] rd_addr_r;
logic rd_w_v_r;
bsg_dff_reset_en
#(.width_p(1+reg_addr_width_p+$bits(bp_be_fu_op_s)+1))
wb_reg
(.clk_i(clk_i)
,.reset_i(reset_i | flush_i)
,.en_i(v_i | v_lo)
,.data_i({v_i, instr.fields.rtype.rd_addr, decode.fu_op, decode.opw_v})
,.data_o({rd_w_v_r, rd_addr_r, fu_op_r, opw_v_r})
);
logic [dword_width_p-1:0] rd_data_lo;
always_comb
if (opw_v_r && fu_op_r inside {e_mul_op_div, e_mul_op_divu})
rd_data_lo = $signed(quotient_lo[0+:word_width_lp]);
else if (opw_v_r && fu_op_r inside {e_mul_op_rem, e_mul_op_remu})
rd_data_lo = $signed(remainder_lo[0+:word_width_lp]);
else if (~opw_v_r && fu_op_r inside {e_mul_op_div, e_mul_op_divu})
rd_data_lo = quotient_lo;
else
rd_data_lo = remainder_lo;
assign wb_pkt.rd_w_v = rd_w_v_r;
assign wb_pkt.rd_addr = rd_addr_r;
assign wb_pkt.rd_data = rd_data_lo;
assign v_o = v_lo & rd_w_v_r;
// Actually a "busy" signal
assign ready_o = idiv_ready_lo & ~v_i;
endmodule
| 7.625022 |
module bp_be_rec_to_fp
import bp_common_pkg::*;
import bp_common_rv64_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_be_hardfloat_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
)
(input [dp_rec_width_gp-1:0] rec_i
, input raw_sp_not_dp_i
, output [dword_width_p-1:0] raw_o
);
// The control bits control tininess, which is fixed in RISC-V
wire [`floatControlWidth-1:0] control_li = `flControl_default;
localparam bias_adj_lp = (1 << sp_exp_width_gp) - (1 << dp_exp_width_gp);
bp_hardfloat_rec_dp_s dp_rec;
bp_hardfloat_rec_sp_s dp2sp_rec;
assign dp_rec = rec_i;
wire [sp_exp_width_gp:0] adjusted_exp = dp_rec.exp + bias_adj_lp;
wire [2:0] exp_code = dp_rec.exp[dp_exp_width_gp-:3];
wire special = (exp_code == '0) || (exp_code >= 3'd6);
assign dp2sp_rec = '{sign : dp_rec.sign
,exp : special ? {exp_code, adjusted_exp[0+:sp_exp_width_gp-2]} : adjusted_exp
,fract: dp_rec.fract >> (dp_sig_width_gp-sp_sig_width_gp)
};
logic [word_width_p-1:0] sp_raw_lo;
recFNToFN
#(.expWidth(sp_exp_width_gp)
,.sigWidth(sp_sig_width_gp)
)
out_sp_rec
(.in(dp2sp_rec)
,.out(sp_raw_lo)
);
logic [dword_width_p-1:0] dp_raw_lo;
recFNToFN
#(.expWidth(dp_exp_width_gp)
,.sigWidth(dp_sig_width_gp)
)
out_dp_rec
(.in(dp_rec)
,.out(dp_raw_lo)
);
assign raw_o = raw_sp_not_dp_i ? {32'hffff_ffff, sp_raw_lo} : dp_raw_lo;
endmodule
| 8.050903 |
module bp_be_regfile
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
, localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, cce_pc_width_p, cce_instr_width_p)
)
(input clk_i
, input reset_i
// Pipeline control signals
, input [cfg_bus_width_lp-1:0] cfg_bus_i
, output [dword_width_p-1:0] cfg_data_o
// rd write bus
, input rd_w_v_i
, input [reg_addr_width_p-1:0] rd_addr_i
, input [dword_width_p-1:0] rd_data_i
// rs1 read bus
, input rs1_r_v_i
, input [reg_addr_width_p-1:0] rs1_addr_i
, output [dword_width_p-1:0] rs1_data_o
// rs2 read bus
, input rs2_r_v_i
, input [reg_addr_width_p-1:0] rs2_addr_i
, output [dword_width_p-1:0] rs2_data_o
);
`declare_bp_cfg_bus_s(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, cce_pc_width_p, cce_instr_width_p);
bp_cfg_bus_s cfg_bus;
assign cfg_bus = cfg_bus_i;
// Intermediate connections
logic rs1_read_v , rs2_read_v;
logic [dword_width_p-1:0] rs1_reg_data , rs2_reg_data;
logic [reg_addr_width_p-1:0] rs1_addr_r , rs2_addr_r, rd_addr_r;
logic [reg_addr_width_p-1:0] rs1_reread_addr, rs2_reread_addr;
logic [dword_width_p-1:0] rd_data_r;
localparam rf_els_lp = 2**reg_addr_width_p;
bsg_mem_2r1w_sync
#(.width_p(dword_width_p), .els_p(rf_els_lp))
rf
(.clk_i(clk_i)
,.reset_i(reset_i)
,.w_v_i(cfg_bus.irf_w_v | rd_w_v_i)
,.w_addr_i(cfg_bus.irf_w_v ? cfg_bus.irf_addr : rd_addr_i)
,.w_data_i(cfg_bus.irf_w_v ? cfg_bus.irf_data : rd_data_i)
,.r0_v_i(cfg_bus.irf_r_v | rs1_read_v)
,.r0_addr_i(cfg_bus.irf_r_v ? cfg_bus.irf_addr : rs1_reread_addr)
,.r0_data_o(rs1_reg_data)
,.r1_v_i(rs2_read_v)
,.r1_addr_i(rs2_reread_addr)
,.r1_data_o(rs2_reg_data)
);
assign cfg_data_o = rs1_reg_data;
// Save the last issued register addresses
bsg_dff_reset_en
#(.width_p(2*reg_addr_width_p))
rs_addr_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(rs1_r_v_i | rs2_r_v_i)
,.data_i({rs1_addr_i, rs2_addr_i})
,.data_o({rs1_addr_r, rs2_addr_r})
);
logic fwd_rs1_r, fwd_rs2_r;
wire fwd_rs1 = rd_w_v_i & (rd_addr_i == rs1_reread_addr);
wire fwd_rs2 = rd_w_v_i & (rd_addr_i == rs2_reread_addr);
bsg_dff
#(.width_p(2+dword_width_p))
rw_fwd_reg
(.clk_i(clk_i)
,.data_i({fwd_rs1, fwd_rs2, rd_data_i})
,.data_o({fwd_rs1_r, fwd_rs2_r, rd_data_r})
);
always_comb
begin
// Technically, this is unnecessary, since most hardened SRAMs still write correctly
// on read-write conflicts, and the read is handled by forwarding. But this avoids
// nasty warnings and possible power sink.
rs1_read_v = ~fwd_rs1 & ~cfg_bus.irf_r_v & ~cfg_bus.irf_w_v;
rs2_read_v = ~fwd_rs2 & ~cfg_bus.irf_r_v & ~cfg_bus.irf_w_v;
// If we have issued a new instruction, use input address to read,
// else use last request address to read
rs1_reread_addr = rs1_r_v_i ? rs1_addr_i : rs1_addr_r;
rs2_reread_addr = rs2_r_v_i ? rs2_addr_i : rs2_addr_r;
end
// Forward if we read/wrote, else pass out the register data
assign rs1_data_o = fwd_rs1_r ? rd_data_r : rs1_reg_data;
assign rs2_data_o = fwd_rs2_r ? rd_data_r : rs2_reg_data;
endmodule
| 7.174308 |
module bp_cacc_tile_node
import bp_common_pkg::*;
import bp_common_rv64_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_cce_pkg::*;
import bsg_noc_pkg::*;
import bp_common_cfg_link_pkg::*;
import bsg_wormhole_router_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
, localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p)
, localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p)
, parameter accelerator_type_p = 1
)
(input core_clk_i
, input core_reset_i
, input coh_clk_i
, input coh_reset_i
, input [coh_noc_cord_width_p-1:0] my_cord_i
// Connected to other tiles on east and west
, input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i
, output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o
, input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i
, output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o
, input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_i
, output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_resp_link_o
);
`declare_bp_lce_cce_if(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
// Declare the routing links
`declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s);
// Tile-side coherence connections
bp_coh_ready_and_link_s accel_lce_req_link_li, accel_lce_req_link_lo;
bp_coh_ready_and_link_s accel_lce_cmd_link_li, accel_lce_cmd_link_lo;
bp_coh_ready_and_link_s accel_lce_resp_link_li, accel_lce_resp_link_lo;
bp_cacc_tile
#(.bp_params_p(bp_params_p))
accel_tile
(.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.my_cord_i(my_cord_i)
,.lce_req_link_i(accel_lce_req_link_li)
,.lce_req_link_o(accel_lce_req_link_lo)
,.lce_cmd_link_i(accel_lce_cmd_link_li)
,.lce_cmd_link_o(accel_lce_cmd_link_lo)
,.lce_resp_link_i(accel_lce_resp_link_li)
,.lce_resp_link_o(accel_lce_resp_link_lo)
);
bp_nd_socket
#(.flit_width_p(coh_noc_flit_width_p)
,.dims_p(coh_noc_dims_p)
,.cord_dims_p(coh_noc_dims_p)
,.cord_markers_pos_p(coh_noc_cord_markers_pos_p)
,.len_width_p(coh_noc_len_width_p)
,.routing_matrix_p(StrictYX | YX_Allow_W)
,.async_clk_p(async_coh_clk_p)
,.els_p(3)
)
cac_coh_socket
(.tile_clk_i(core_clk_i)
,.tile_reset_i(core_reset_i)
,.network_clk_i(coh_clk_i)
,.network_reset_i(coh_reset_i)
,.my_cord_i(my_cord_i)
,.network_link_i({coh_lce_req_link_i, coh_lce_cmd_link_i, coh_lce_resp_link_i})
,.network_link_o({coh_lce_req_link_o, coh_lce_cmd_link_o, coh_lce_resp_link_o})
,.tile_link_i({accel_lce_req_link_lo, accel_lce_cmd_link_lo, accel_lce_resp_link_lo})
,.tile_link_o({accel_lce_req_link_li, accel_lce_cmd_link_li, accel_lce_resp_link_li})
);
endmodule
| 7.101469 |
module for storing branch prediction data.
Inputs: 2 asynchronous read ports and 1 synchronous write port.
Outputs: data and cache hit (for each read port)
*/
module bp_cache #(
parameter AWIDTH=32, // Address bit width
parameter DWIDTH=32, // Data bit width
parameter LINES=128 // Number of cache lines
) (
input clk,
input reset,
// IO for 1st read port
input [AWIDTH-1:0] ra0,
output [DWIDTH-1:0] dout0,
output hit0,
// IO for 2nd read port
input [AWIDTH-1:0] ra1,
output [DWIDTH-1:0] dout1,
output hit1,
// IO for write port
input [AWIDTH-1:0] wa,
input [DWIDTH-1:0] din,
input we
);
// TODO: Your code
assign dout0 = '0;
assign dout1 = '0;
assign hit0 = 1'b0;
assign hit1 = 1'b0;
endmodule
| 6.755624 |
module bp_cce_alu
import bp_cce_pkg::*;
#(
parameter width_p = "inv"
) (
input [width_p-1:0] opd_a_i
, input [width_p-1:0] opd_b_i
, input bp_cce_inst_alu_op_e alu_op_i
, output logic [width_p-1:0] res_o
);
always_comb begin : alu
unique case (alu_op_i)
e_alu_add: res_o = opd_a_i + opd_b_i;
e_alu_sub: res_o = opd_a_i - opd_b_i;
e_alu_lsh: res_o = opd_a_i << opd_b_i;
e_alu_rsh: res_o = opd_a_i >> opd_b_i;
e_alu_and: res_o = opd_a_i & opd_b_i;
e_alu_or: res_o = opd_a_i | opd_b_i;
e_alu_xor: res_o = opd_a_i ^ opd_b_i;
e_alu_neg: res_o = ~opd_a_i;
e_alu_not: res_o = !opd_a_i;
e_alu_nand: res_o = !(opd_a_i & opd_b_i);
e_alu_nor: res_o = !(opd_a_i | opd_b_i);
default: res_o = '0;
endcase
end
endmodule
| 7.089842 |
module bp_cce_branch
import bp_cce_pkg::*;
#(
parameter width_p = "inv"
, parameter cce_pc_width_p = "inv"
) (
input [ width_p-1:0] opd_a_i
, input [ width_p-1:0] opd_b_i
, input branch_i
, input predicted_taken_i
, input bp_cce_inst_branch_op_e branch_op_i
, input [cce_pc_width_p-1:0] execute_pc_i
, input [cce_pc_width_p-1:0] branch_target_i
, output logic mispredict_o
, output logic [cce_pc_width_p-1:0] pc_o
);
wire equal = (opd_a_i == opd_b_i);
wire not_equal = ~equal;
wire less = (opd_a_i < opd_b_i);
wire [cce_pc_width_p-1:0] execute_pc_plus_one = cce_pc_width_p'(execute_pc_i + 'd1);
logic branch_res;
always_comb begin : branch
unique case (branch_op_i)
e_branch_eq: branch_res = equal;
e_branch_neq: branch_res = not_equal;
e_branch_lt: branch_res = less;
e_branch_le: branch_res = (less | equal);
default: branch_res = '0;
endcase
// Misprediction happens if:
// a) branch was predicted not taken, but branch should have been taken
// b) branch was predicted taken, but branch should not have been taken
mispredict_o = (((branch_i & branch_res) & !predicted_taken_i)
| (!(branch_i & branch_res) & predicted_taken_i));
// Output correct next PC (for all instructions)
// If the current instruction is a branch and the branch evaluates to taken, the next PC
// is the branch target. Else, the next PC is the current PC plus one.
pc_o = (branch_i & branch_res) ? branch_target_i : execute_pc_plus_one;
end
endmodule
| 7.273019 |
module extracts information about the LRU entry of the requesting LCE
*
*/
module bp_cce_dir_lru_extract
import bp_common_pkg::*;
import bp_cce_pkg::*;
#(parameter tag_sets_per_row_p = "inv"
, parameter row_width_p = "inv"
, parameter num_lce_p = "inv"
, parameter assoc_p = "inv"
, parameter rows_per_set_p = "inv"
, parameter tag_width_p = "inv"
, localparam lg_num_lce_lp = `BSG_SAFE_CLOG2(num_lce_p)
, localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p)
, localparam lg_rows_per_set_lp = `BSG_SAFE_CLOG2(rows_per_set_p)
)
(
// input row from directory RAM, per tag set valid bit, and row number
input [row_width_p-1:0] row_i
, input [tag_sets_per_row_p-1:0] row_v_i
, input [lg_rows_per_set_lp-1:0] row_num_i
// requesting LCE and LRU way for the request
, input [lg_num_lce_lp-1:0] lce_i
, input [lg_assoc_lp-1:0] lru_way_i
, output logic lru_v_o
, output logic lru_cached_excl_o
, output bp_coh_states_e lru_coh_state_o
, output logic [tag_width_p-1:0] lru_tag_o
);
initial begin
assert(tag_sets_per_row_p == 2) else
$error("unsupported configuration: number of sets per row must equal 2");
end
`declare_bp_cce_dir_entry_s(tag_width_p);
// Directory RAM row cast
dir_entry_s [tag_sets_per_row_p-1:0][assoc_p-1:0] row;
assign row = row_i;
// LRU output is valid if:
// 1. tag set input is valid
// 2. target LCE's tag set is stored on the input row
assign lru_v_o = (row_v_i[lce_i[0]]) & ((lce_i >> 1) == row_num_i);
//logic [`bp_coh_bits-1:0] lru_coh_state;
bp_coh_states_e lru_coh_state;
assign lru_coh_state = (row_v_i)
? row[lce_i[0]][lru_way_i].state
: e_COH_I;
assign lru_coh_state_o = lru_coh_state;
assign lru_cached_excl_o = |lru_coh_state & ~lru_coh_state[`bp_coh_shared_bit];
assign lru_tag_o = (row_v_i)
? row[lce_i[0]][lru_way_i].tag
: '0;
endmodule
| 7.550381 |
module performs the parallel tag comparison on a row of tag sets from the directory.
*
*/
module bp_cce_dir_tag_checker
import bp_common_pkg::*;
import bp_cce_pkg::*;
#(parameter tag_sets_per_row_p = "inv"
, parameter row_width_p = "inv"
, parameter assoc_p = "inv"
, parameter tag_width_p = "inv"
, localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p)
)
(
// input row from directory RAM
input [row_width_p-1:0] row_i
, input [tag_sets_per_row_p-1:0] row_v_i
, input [tag_width_p-1:0] tag_i
, output logic [tag_sets_per_row_p-1:0] sharers_hits_o
, output logic [tag_sets_per_row_p-1:0][lg_assoc_lp-1:0] sharers_ways_o
, output bp_coh_states_e [tag_sets_per_row_p-1:0] sharers_coh_states_o
);
initial begin
assert(tag_sets_per_row_p == 2) else
$error("unsupported configuration: number of sets per row must equal 2");
end
`declare_bp_cce_dir_entry_s(tag_width_p);
// Directory RAM row cast
dir_entry_s [tag_sets_per_row_p-1:0][assoc_p-1:0] row;
assign row = row_i;
// one bit per way per tag set indicating if a target block is cached in valid state
logic [tag_sets_per_row_p-1:0][assoc_p-1:0] row_hits;
// compute hit per way per tag set
for (genvar i = 0; i < tag_sets_per_row_p; i++) begin : row_hits_tag_set
for (genvar j = 0; j < assoc_p; j++) begin : row_hits_way
assign row_hits[i][j] = row_v_i[i] & (row[i][j].tag == tag_i) & |(row[i][j].state);
end
end
// extract way and valid bit per tag set
for (genvar i = 0; i < tag_sets_per_row_p; i++) begin : sharers_ways_gen
bsg_encode_one_hot
#(.width_p(assoc_p)
)
row_hits_to_way_ids_and_v
(.i(row_hits[i])
,.addr_o(sharers_ways_o[i])
,.v_o(sharers_hits_o[i])
);
end
// extract coherence state for tag sets that have block cached
for (genvar i = 0; i < tag_sets_per_row_p; i++) begin : sharers_states_gen
assign sharers_coh_states_o[i] = (sharers_hits_o[i])
? row[i][sharers_ways_o[i]].state
: e_COH_I;
end
endmodule
| 7.634754 |
module is an active tie-off. That is, requests to this module will return the header
// with a zero payload. This is useful to not stall the network in the case of an erroneous
// address, or prevent deadlock at network boundaries
module bp_cce_loopback
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_common_cfg_link_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_bedrock_mem_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, cce)
)
(input clk_i
, input reset_i
, input [cce_mem_msg_width_lp-1:0] mem_cmd_i
, input mem_cmd_v_i
, output mem_cmd_ready_o
, output [cce_mem_msg_width_lp-1:0] mem_resp_o
, output mem_resp_v_o
, input mem_resp_yumi_i
);
`declare_bp_bedrock_mem_if(paddr_width_p, dword_width_p, lce_id_width_p, lce_assoc_p, cce);
bp_bedrock_cce_mem_msg_s mem_cmd_cast_i;
bp_bedrock_cce_mem_msg_s mem_resp_cast_o;
assign mem_cmd_cast_i = mem_cmd_i;
assign mem_resp_o = mem_resp_cast_o;
bsg_two_fifo
#(.width_p($bits(mem_cmd_cast_i.header)))
loopback_buffer
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(mem_cmd_cast_i.header)
,.v_i(mem_cmd_v_i)
,.ready_o(mem_cmd_ready_o)
,.data_o(mem_resp_cast_o.header)
,.v_o(mem_resp_v_o)
,.yumi_i(mem_resp_yumi_i)
);
assign mem_resp_cast_o.data = '0;
endmodule
| 6.545817 |
module for the CCE.
*
* It instantiates either the microcode or FSM CCE, based on the param in bp_params_p.
*
*/
module bp_cce_wrapper
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_common_cfg_link_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
// Interface Widths
, localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, cce_pc_width_p, cce_instr_width_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
)
(input clk_i
, input reset_i
// Configuration Interface
, input [cfg_bus_width_lp-1:0] cfg_bus_i
, output [cce_instr_width_p-1:0] cfg_cce_ucode_data_o
// LCE-CCE Interface
, input [lce_cce_req_width_lp-1:0] lce_req_i
, input lce_req_v_i
, output logic lce_req_yumi_o
, input [lce_cce_resp_width_lp-1:0] lce_resp_i
, input lce_resp_v_i
, output logic lce_resp_yumi_o
// ready->valid
, output logic [lce_cmd_width_lp-1:0] lce_cmd_o
, output logic lce_cmd_v_o
, input lce_cmd_ready_i
// CCE-MEM Interface
, input [cce_mem_msg_width_lp-1:0] mem_resp_i
, input mem_resp_v_i
, output logic mem_resp_yumi_o
// ready->valid
, output logic [cce_mem_msg_width_lp-1:0] mem_cmd_o
, output logic mem_cmd_v_o
, input mem_cmd_ready_i
);
// Config Interface
`declare_bp_cfg_bus_s(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, cce_pc_width_p, cce_instr_width_p);
// Config bus casting
bp_cfg_bus_s cfg_bus_cast_i;
assign cfg_bus_cast_i = cfg_bus_i;
if (ucode_cce_p == 1) begin : ucode
bp_cce
#(.bp_params_p(bp_params_p))
cce
(.*);
end else begin : fsm
bp_cce_fsm
#(.bp_params_p(bp_params_p))
cce
(.*);
end
endmodule
| 6.803591 |
module bp_fe_bht
import bp_fe_pkg::*;
#(
parameter bht_idx_width_p = "inv"
, localparam els_lp = 2 ** bht_idx_width_p
, localparam saturation_size_lp = 2
) (
input clk_i
, input reset_i
, input w_v_i
, input [bht_idx_width_p-1:0] idx_w_i
, input correct_i
, input r_v_i
, input [bht_idx_width_p-1:0] idx_r_i
, output predict_o
);
logic [els_lp-1:0][saturation_size_lp-1:0] mem;
assign predict_o = r_v_i ? mem[idx_r_i][1] : 1'b0;
always_ff @(posedge clk_i)
if (reset_i) mem <= '{default: 2'b01};
else if (w_v_i) begin
//2-bit saturating counter(high_bit:prediction direction,low_bit:strong/weak prediction)
case ({
correct_i, mem[idx_w_i][1], mem[idx_w_i][0]
})
//wrong prediction
3'b000: mem[idx_w_i] <= {mem[idx_w_i][1] ^ mem[idx_w_i][0], 1'b1}; //2'b01
3'b001: mem[idx_w_i] <= {mem[idx_w_i][1] ^ mem[idx_w_i][0], 1'b1}; //2'b11
3'b010: mem[idx_w_i] <= {mem[idx_w_i][1] ^ mem[idx_w_i][0], 1'b1}; //2'b11
3'b011: mem[idx_w_i] <= {mem[idx_w_i][1] ^ mem[idx_w_i][0], 1'b1}; //2'b01
//correct prediction
3'b100: mem[idx_w_i] <= mem[idx_w_i]; //2'b00
3'b101: mem[idx_w_i] <= {mem[idx_w_i][1], ~mem[idx_w_i][0]}; //2'b00
3'b110: mem[idx_w_i] <= mem[idx_w_i]; //2'b10
3'b111: mem[idx_w_i] <= {mem[idx_w_i][1], ~mem[idx_w_i][0]}; //2'b10
endcase
end
endmodule
| 7.461993 |
module bp_fe_btb
import bp_fe_pkg::*;
import bp_common_rv64_pkg::*;
#(
parameter vaddr_width_p = "inv"
, parameter btb_tag_width_p = "inv"
, parameter btb_idx_width_p = "inv"
, localparam btb_offset_width_lp = 2 // bottom 2 bits are unused without compressed branches
// TODO: Should be a parameterizable struct
// From RISC-V specifications
, localparam eaddr_width_lp = rv64_eaddr_width_gp
) (
input clk_i
, input reset_i
// Synchronous read
, input [vaddr_width_p-1:0] r_addr_i
, input r_v_i
, output [vaddr_width_p-1:0] br_tgt_o
, output br_tgt_v_o
, input [btb_tag_width_p-1:0] w_tag_i
, input [btb_idx_width_p-1:0] w_idx_i
, input w_v_i
, input [ vaddr_width_p-1:0] br_tgt_i
);
localparam btb_els_lp = 2 ** btb_idx_width_p;
logic [btb_tag_width_p-1:0] tag_mem_li, tag_mem_lo;
logic [btb_idx_width_p-1:0] tag_mem_addr_li;
logic tag_mem_v_lo;
logic [vaddr_width_p-1:0] tgt_mem_li, tgt_mem_lo;
logic [btb_idx_width_p-1:0] tgt_mem_addr_li;
logic [btb_tag_width_p-1:0] w_tag_n, w_tag_r;
logic [btb_tag_width_p-1:0] r_tag_n, r_tag_r;
logic [btb_idx_width_p-1:0] r_idx_n, r_idx_r;
logic r_v_r;
assign tag_mem_li = w_tag_i;
assign tgt_mem_li = br_tgt_i[0+:vaddr_width_p];
assign tag_mem_addr_li = w_v_i ? w_idx_i : r_addr_i[btb_offset_width_lp+:btb_idx_width_p];
logic [btb_els_lp-1:0] v_r, v_n;
bsg_mem_1rw_sync #(
.width_p(btb_tag_width_p + vaddr_width_p)
, .els_p (btb_els_lp)
) tag_mem (
.clk_i (clk_i)
, .reset_i(reset_i)
, .v_i(r_v_i | w_v_i)
, .w_i(w_v_i)
, .data_i({tag_mem_li, tgt_mem_li})
, .addr_i(tag_mem_addr_li)
, .data_o({tag_mem_lo, tgt_mem_lo})
);
assign tag_mem_v_lo = v_r[r_idx_r];
assign br_tgt_o = tgt_mem_lo;
assign br_tgt_v_o = tag_mem_v_lo & r_v_r & (tag_mem_lo == r_tag_r);
always_ff @(posedge clk_i) begin
if (reset_i) begin
r_v_r <= '0;
r_tag_r <= '0;
r_idx_r <= '0;
end else begin
// Read didn't actually happen if there was a write
r_v_r <= r_v_i & ~w_v_i;
r_tag_r <= r_addr_i[btb_offset_width_lp+btb_idx_width_p+:btb_tag_width_p];
r_idx_r <= r_addr_i[btb_offset_width_lp+:btb_idx_width_p];
end
if (reset_i) v_r <= '0;
else if (w_v_i) v_r[tag_mem_addr_li] <= 1'b1;
else v_r <= v_r;
end
/*
always_ff @(posedge clk_i)
begin
if (w_v_i)
begin
$display("[BTB] WRITE INDEX: %x TAG: %x TARGET: %x"
, tag_mem_addr_li
, tag_mem_li
, tgt_mem_li
);
end
if (br_tgt_v_o)
begin
$display("[BTB] READ INDEX: %x TAG: %x TARGET: %x"
, '0
, r_tag_r
, br_tgt_o
);
end
end
*/
endmodule
| 8.223668 |
module bp_FSM (
ip_state,
b_res,
clk,
rst,
op_state,
pred
);
input [1:0] ip_state;
input b_res; //Actual result of branch
input clk;
input rst;
output reg [1:0] op_state; //Output state after verifying actual result
output reg pred; //predicted operation for branch
localparam strong_nt = 2'b00, weak_nt = 2'b01, weak_t = 2'b10, strong_t = 2'b11;
reg [1:0] curr, next;
//State Assigment
always @(posedge clk, posedge rst) begin
if (rst) curr <= strong_nt;
else next <= curr;
end
//Output and Next state computation
//Same always block as we have considered Moore machine
always @(*) begin
case (curr)
strong_nt: //00
begin
pred <= 1'b0;
if (b_res) next <= weak_nt; //00-->01
else next <= strong_nt; //00-->00
end
weak_nt: //01
begin
pred <= 1'b0;
if (b_res) next <= strong_t; //01-->11
else next <= strong_nt; //01-->00
end
weak_t: //10
begin
pred <= 1'b1;
if (b_res) next <= strong_t; //10-->11
else next <= strong_nt; //10-->00
end
strong_t: //11
begin
pred <= 1'b1;
if (b_res) next <= strong_t; //11-->11
else next <= weak_t; //11-->10
end
default: begin
pred <= 1'b0;
next <= strong_nt;
end
endcase
op_state = next;
end
endmodule
| 6.582959 |
module btb_input(rst,btb,index,PredictedTarget,curr_state,mux_predict);
input rst;
input [34:0]btb[0:31]
input [4:0]index;
output reg [1:0]curr_state;
output reg [31:0]PredictedTarget;
output mux_predict;
reg i;
initial
begin
for(i = 0; i < 32; i = i+1)
btable[i] <= 35'd0;
end
always@(index,rst)
begin
if(rst) begin
for(i = 0; i < 32; i = i+1)
btable[i] <= 35'd0;
end
else
{PredictedTarget,curr_state,mux_predict} = btable[index];
end
endmodule
| 6.831081 |
module btb_update (
btb,
index,
TargetAddress,
next_state,
predict_bit
);
input [34:0] btb[0:31];
input [4:0] index;
input [32:0] TargetAddress;
input [1:0] next_state;
input predict_bit;
always @(*) begin
btb[index] = {TargetAddress, next_state, predict_bit};
end
endmodule
| 8.458744 |
module bp_lite_to_burst
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
, parameter in_data_width_p = "inv"
, parameter out_data_width_p = "inv"
// Bitmask which etermines which message types have a data payload
// Constructed as (1 << e_payload_msg1 | 1 << e_payload_msg2)
, parameter payload_mask_p = 0
`declare_bp_bedrock_mem_if_widths(paddr_width_p, in_data_width_p, lce_id_width_p, lce_assoc_p, in)
`declare_bp_bedrock_mem_if_widths(paddr_width_p, out_data_width_p, lce_id_width_p, lce_assoc_p, out)
)
(input clk_i
, input reset_i
// Master BP Lite
// ready-valid-and
, input [in_mem_msg_width_lp-1:0] mem_i
, input mem_v_i
, output logic mem_ready_o
// Client BP Burst
// ready-valid-and
, output logic [out_mem_msg_header_width_lp-1:0] mem_header_o
, output logic mem_header_v_o
, input logic mem_header_ready_i
// ready-valid-and
, output logic [out_data_width_p-1:0] mem_data_o
, output logic mem_data_v_o
, input mem_data_ready_i
);
`declare_bp_bedrock_mem_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, in);
`declare_bp_bedrock_mem_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, out);
bp_bedrock_in_mem_msg_s mem_cast_i;
assign mem_cast_i = mem_i;
localparam in_data_bytes_lp = in_data_width_p/8;
localparam out_data_bytes_lp = out_data_width_p/8;
localparam burst_words_lp = in_data_width_p/out_data_width_p;
localparam burst_offset_width_lp = `BSG_SAFE_CLOG2(out_data_bytes_lp);
// We could make this a two fifo to get more throughput
bp_bedrock_in_mem_msg_header_s header_lo;
bsg_one_fifo
#(.width_p($bits(bp_bedrock_in_mem_msg_header_s)))
header_fifo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(mem_cast_i.header)
,.v_i(mem_v_i)
,.ready_o(mem_ready_o)
,.data_o(mem_header_o)
,.v_o(mem_header_v_o)
,.yumi_i(mem_header_ready_i & mem_header_v_o)
);
wire has_data = payload_mask_p[mem_cast_i.header.msg_type];
localparam data_len_width_lp = `BSG_SAFE_CLOG2(burst_words_lp);
wire [data_len_width_lp-1:0] num_burst_cmds = (1'b1 << mem_cast_i.header.size) / out_data_bytes_lp;
logic [out_data_width_p-1:0] data_lo;
bsg_parallel_in_serial_out_dynamic
#(.width_p(out_data_width_p), .max_els_p(burst_words_lp))
piso
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(mem_cast_i.data)
,.len_i(num_burst_cmds - 1'b1)
,.v_i(mem_v_i & has_data)
,.data_o(mem_data_o)
,.v_o(mem_data_v_o)
,.yumi_i(mem_data_ready_i & mem_data_v_o)
// We rely on the header fifo to handle ready/valid handshaking
,.len_v_o(/* Unused */)
,.ready_o(/* Unused */)
);
//synopsys translate_off
initial
begin
assert (in_data_width_p >= out_data_width_p)
else $error("Master data cannot be smaller than client");
assert (in_data_width_p % out_data_width_p == 0)
else $error("Master data must be a multiple of client data");
end
always_ff @(negedge clk_i)
begin
//if (mem_ready_o & mem_v_i)
// $display("[%t] Msg received: %p", $time, mem_cast_i);
//if (mem_yumi_i)
// $display("[%t] Stream sent: %p %x CNT: %x", $time, mem_header_cast_o, mem_data_o, current_cnt);
end
//synopsys translate_on
endmodule
| 9.042699 |
module bp_mem
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
, parameter mem_cap_in_bytes_p = "inv"
, parameter mem_zero_p = 0
, parameter mem_load_p = 0
, parameter mem_file_p = "inv"
, parameter mem_offset_p = 0
, parameter use_max_latency_p = 0
, parameter use_random_latency_p = 0
, parameter use_dramsim2_latency_p = 0
, parameter max_latency_p = "inv"
, parameter dram_clock_period_in_ps_p = "inv"
, parameter dram_cfg_p = "inv"
, parameter dram_sys_cfg_p = "inv"
, parameter dram_capacity_p = "inv"
, localparam num_block_bytes_lp = cce_block_width_p / 8
)
(input clk_i
, input reset_i
// BP side
// ready->valid (ready then valid)
, input [cce_mem_msg_width_lp-1:0] mem_cmd_i
, input mem_cmd_v_i
, output mem_cmd_ready_o
, output [cce_mem_msg_width_lp-1:0] mem_resp_o
, output mem_resp_v_o
, input mem_resp_yumi_i
);
logic dram_v_li, dram_w_li;
logic [paddr_width_p-1:0] dram_addr_li;
logic [num_block_bytes_lp-1:0] dram_wmask_li;
logic [cce_block_width_p-1:0] dram_data_li, dram_data_lo;
logic dram_v_lo, delayed_dram_v_lo;
logic dram_ready_lo, delayed_dram_yumi_li;
bp_mem_transducer
#(.bp_params_p(bp_params_p)
,.dram_offset_p(mem_offset_p)
)
transducer
(.clk_i(clk_i)
,.reset_i(reset_i)
,.mem_cmd_i(mem_cmd_i)
,.mem_cmd_v_i(mem_cmd_v_i)
,.mem_cmd_ready_o(mem_cmd_ready_o)
,.mem_resp_o(mem_resp_o)
,.mem_resp_v_o(mem_resp_v_o)
,.mem_resp_yumi_i(mem_resp_yumi_i)
,.ready_i(dram_ready_lo)
,.v_o(dram_v_li)
,.w_o(dram_w_li)
,.addr_o(dram_addr_li)
,.data_o(dram_data_li)
,.write_mask_o(dram_wmask_li)
,.data_i(dram_data_lo)
,.v_i(delayed_dram_v_lo)
,.yumi_o(delayed_dram_yumi_li)
);
bp_mem_delay_model
#(.addr_width_p(paddr_width_p)
,.use_max_latency_p(use_max_latency_p)
,.use_random_latency_p(use_random_latency_p)
,.use_dramsim2_latency_p(use_dramsim2_latency_p)
,.max_latency_p(max_latency_p)
,.dram_clock_period_in_ps_p(dram_clock_period_in_ps_p)
,.dram_cfg_p(dram_cfg_p)
,.dram_sys_cfg_p(dram_sys_cfg_p)
,.dram_capacity_p(dram_capacity_p)
)
delay_model
(.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(dram_v_li)
,.w_i(dram_w_li)
,.addr_i(dram_addr_li)
,.ready_o(dram_ready_lo)
,.v_o(delayed_dram_v_lo)
,.yumi_i(delayed_dram_yumi_li)
);
bp_mem_storage_sync
#(.data_width_p(cce_block_width_p)
,.addr_width_p(paddr_width_p)
,.mem_cap_in_bytes_p(mem_cap_in_bytes_p)
,.mem_zero_p(mem_zero_p)
,.mem_load_p(mem_load_p)
,.mem_file_p(mem_file_p)
,.mem_offset_p(mem_offset_p)
)
dram
(.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(dram_v_li)
,.w_i(dram_w_li)
,.addr_i(dram_addr_li)
,.data_i(dram_data_li)
,.write_mask_i(dram_wmask_li)
,.data_o(dram_data_lo)
);
endmodule
| 6.584612 |
module bp_mem_delay_model #(
parameter addr_width_p = "inv"
, parameter use_max_latency_p = 0
, parameter use_random_latency_p = 0
, parameter use_dramsim2_latency_p = 0
, parameter max_latency_p = "inv"
, parameter dram_clock_period_in_ps_p = "inv"
, parameter dram_cfg_p = "inv"
, parameter dram_sys_cfg_p = "inv"
, parameter dram_capacity_p = "inv"
) (
input clk_i
, input reset_i
, input [addr_width_p-1:0] addr_i
, input v_i
, input w_i
, output ready_o
, output v_o
, input yumi_i
);
localparam latency_width_lp = `BSG_SAFE_CLOG2(max_latency_p + 1);
enum logic {
e_idle,
e_service
}
state_n, state_r;
always_ff @(posedge clk_i)
if (reset_i) state_r <= e_idle;
else state_r <= state_n;
always_comb
case (state_r)
e_idle : state_n = v_i ? e_service : e_idle;
e_service: state_n = yumi_i ? e_idle : e_service;
default : state_n = e_idle;
endcase
logic [latency_width_lp-1:0] current_latency;
logic [latency_width_lp-1:0] latency_cnt;
wire clr_counter = yumi_i;
wire inc_counter = (state_r == e_service) & (latency_cnt < current_latency);
bsg_counter_clear_up #(
.max_val_p (max_latency_p)
, .init_val_p(0)
) latency_counter (
.clk_i (clk_i)
, .reset_i(reset_i)
, .clear_i(clr_counter)
, .up_i(inc_counter)
, .count_o(latency_cnt)
);
if (use_max_latency_p) begin : max_latency
assign current_latency = max_latency_p;
assign ready_o = (state_r == e_idle);
assign v_o = (latency_cnt == current_latency);
end else if (use_random_latency_p) begin : random_latency
logic [31:0] lfsr_reg;
bsg_lfsr #(
.width_p(32)
) latency_lfsr (
.clk(clk_i)
, .reset_i(reset_i)
, .yumi_i(yumi_i)
, .o(lfsr_reg)
);
assign current_latency = lfsr_reg | 1'b1;
assign ready_o = (state_r == e_idle);
assign v_o = (latency_cnt == current_latency);
end else if (use_dramsim2_latency_p) begin : dramsim2
`ifdef DRAMSIM2
logic dramsim_valid, dramsim_accepted;
logic pending_req_r, pending_req_w_r, pending_resp_r;
bsg_dff_reset_en #(
.width_p(1)
) pending_resp_reg (
.clk_i(clk_i)
, .reset_i(reset_i)
, .en_i(dramsim_valid | yumi_i)
, .data_i(dramsim_valid)
, .data_o(pending_resp_r)
);
logic w_r, v_r;
bsg_dff_reset_en #(
.width_p(2)
) pending_req_reg (
.clk_i(clk_i)
, .reset_i(reset_i)
, .en_i(dramsim_accepted | v_i)
, .data_i({w_i, v_i})
, .data_o({pending_req_w_r, pending_req_r})
);
initial init(dram_clock_period_in_ps_p, dram_cfg_p, dram_sys_cfg_p, dram_capacity_p);
always_ff @(negedge clk_i) begin
if (pending_req_r & ~pending_req_w_r) dramsim_accepted <= mem_read_req(addr_i);
else if (pending_req_r & pending_req_w_r) dramsim_accepted <= mem_write_req(addr_i);
dramsim_valid <= tick();
end
assign ready_o = (state_r == e_idle);
assign v_o = pending_resp_r;
`else
$fatal("DRAMSIM2 delay model selection, but DRAMSIM2 is not set");
`endif
end
`ifdef DRAMSIM2
import "DPI-C" context function void init(
input longint clock_period
, input string dram_cfg_name
, input string system_cfg_name
, input longint dram_capacity
);
import "DPI-C" context function bit tick();
import "DPI-C" context function bit mem_read_req(input longint addr);
import "DPI-C" context function bit mem_write_req(input longint addr);
`endif
endmodule
| 8.418178 |
module bp_mem_storage_sync #(
parameter data_width_p = "inv"
, parameter addr_width_p = "inv"
, parameter mem_cap_in_bytes_p = "inv"
, parameter mem_load_p = 0
, parameter mem_zero_p = 0
, parameter mem_file_p = "inv"
, parameter mem_offset_p = "inv"
, localparam num_data_bytes_lp = data_width_p / 8
, localparam mem_cap_in_words_lp = mem_cap_in_bytes_p / num_data_bytes_lp
, localparam byte_els_lp = `BSG_SAFE_CLOG2(mem_cap_in_bytes_p)
) (
input clk_i
, input reset_i
, input v_i
, input w_i
, input [ addr_width_p-1:0] addr_i
, input [ data_width_p-1:0] data_i
, input [num_data_bytes_lp-1:0] write_mask_i
, output [data_width_p-1:0] data_o
);
wire unused = &{reset_i};
logic [7:0] mem[0:mem_cap_in_bytes_p-1];
logic [data_width_p-1:0] data_li, data_lo;
logic [addr_width_p-1:0] addr_r;
always_comb
for (integer i = 0; i < num_data_bytes_lp; i++) data_lo[i*8+:8] = mem[addr_r+byte_els_lp'(i)];
assign data_li = data_i;
import "DPI-C" context function string rebase_hexfile(
input string memfile_name
, input longint dram_base
);
string hex_file;
initial begin
if (mem_load_p) begin
for (integer i = 0; i < mem_cap_in_bytes_p; i++) mem[i] = '0;
hex_file = rebase_hexfile(mem_file_p, mem_offset_p);
$readmemh(hex_file, mem);
end else if (mem_zero_p) begin
for (integer i = 0; i < mem_cap_in_bytes_p; i++) mem[i] = '0;
end
end
always @(posedge clk_i) begin
if (v_i & w_i)
// byte-maskable writes
begin
for (integer i = 0; i < num_data_bytes_lp; i++) begin
if (write_mask_i[i]) mem[addr_i+i] <= data_li[i*8+:8];
end
end
if (v_i & ~w_i) addr_r <= addr_i;
end
assign data_o = data_lo;
endmodule
| 7.426659 |
module bp_me_addr_to_cce_id
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
)
(input [paddr_width_p-1:0] paddr_i
, output logic [cce_id_width_p-1:0] cce_id_o
);
bp_global_addr_s global_addr_li;
bp_local_addr_s local_addr_li;
assign global_addr_li = paddr_i;
assign local_addr_li = paddr_i;
// CCE: CC -> MC -> CAC -> SAC -> IOC
localparam max_cc_cce_lp = num_core_p;
localparam max_mc_cce_lp = max_cc_cce_lp + num_l2e_p;
localparam max_cac_cce_lp = max_mc_cce_lp + num_cacc_p;
localparam max_sac_cce_lp = max_cac_cce_lp + num_sacc_p;
localparam max_ioc_cce_lp = max_sac_cce_lp + num_io_p;
wire external_io_v_li = (global_addr_li.did > '1);
wire local_addr_v_li = (paddr_i < dram_base_addr_gp);
wire dram_addr_v_li = (paddr_i >= dram_base_addr_gp) && (paddr_i < coproc_base_addr_gp);
wire core_local_addr_v_li = local_addr_v_li && (local_addr_li.cce < num_core_p);
localparam block_offset_lp = `BSG_SAFE_CLOG2(cce_block_width_p/8);
localparam lg_lce_sets_lp = `BSG_SAFE_CLOG2(lce_sets_p);
localparam lg_num_cce_lp = `BSG_SAFE_CLOG2(num_cce_p);
// convert miss address (excluding block offset bits) into CCE ID
// For now, assume all CCE's have ID [0,num_core_p-1] and addresses are striped
// at the cache block granularity
logic [lg_lce_sets_lp-1:0] hash_addr_li;
logic [lg_num_cce_lp-1:0] cce_dst_id_lo;
assign hash_addr_li = {<< {paddr_i[block_offset_lp+:lg_lce_sets_lp]}};
bsg_hash_bank
#(.banks_p(num_cce_p) // number of CCE's to spread way groups over
,.width_p(lg_lce_sets_lp) // width of address input
)
addr_to_cce_id
(.i(hash_addr_li)
,.bank_o(cce_dst_id_lo)
,.index_o()
);
always_comb begin
cce_id_o = '0;
if (external_io_v_li || (core_local_addr_v_li && (local_addr_li.dev == host_dev_gp)))
// Stripe by 4kiB page, start at io CCE id
cce_id_o = (num_io_p > 1)
? max_sac_cce_lp + paddr_i[page_offset_width_p+:`BSG_SAFE_CLOG2(num_io_p)]
: max_sac_cce_lp;
else if (local_addr_v_li)
// Split uncached I/O region by max 128 cores
cce_id_o = local_addr_li.cce;
else if (dram_addr_v_li)
// Stripe by cache line
cce_id_o[0+:lg_num_cce_lp] = cce_dst_id_lo;
else
cce_id_o = (num_sacc_p > 1)
? max_cac_cce_lp + paddr_i[paddr_width_p-io_noc_did_width_p-1-:`BSG_SAFE_CLOG2(num_sacc_p)]
: max_cac_cce_lp;
end
endmodule
| 6.840604 |
module to convert a coordinate into a set of ids. It assumes that
// the SoC topology is a fixed 2d mesh with a set mapping. Should be made more flexible
module bp_me_cord_to_id
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
)
(input [coh_noc_cord_width_p-1:0] cord_i
, output logic [core_id_width_p-1:0] core_id_o
, output logic [cce_id_width_p-1:0] cce_id_o
, output logic [lce_id_width_p-1:0] lce_id0_o
, output logic [lce_id_width_p-1:0] lce_id1_o
);
wire [coh_noc_x_cord_width_p-1:0] xcord_li = cord_i[0+:coh_noc_x_cord_width_p];
wire [coh_noc_y_cord_width_p-1:0] ycord_li = cord_i[coh_noc_x_cord_width_p+:coh_noc_y_cord_width_p];
// CCE: CC -> MC -> CAC -> SAC -> IOC
localparam max_cc_cce_lp = num_core_p;
localparam max_mc_cce_lp = max_cc_cce_lp + num_l2e_p;
localparam max_cac_cce_lp = max_mc_cce_lp + num_cacc_p;
localparam max_sac_cce_lp = max_cac_cce_lp + num_sacc_p;
localparam max_ic_cce_lp = max_sac_cce_lp + num_io_p;
// LCE: CC -> CAC -> MC -> SAC -> IOC
localparam max_cc_lce_lp = num_core_p*2;
localparam max_cac_lce_lp = max_cc_lce_lp + num_cacc_p;
localparam max_mc_lce_lp = max_cac_lce_lp + num_l2e_p;
localparam max_sac_lce_lp = max_mc_lce_lp + num_sacc_p;
localparam max_ic_lce_lp = max_sac_lce_lp + num_io_p;
wire cord_in_cc_li = (xcord_li >= sac_x_dim_p) & (xcord_li < sac_x_dim_p+cc_x_dim_p)
& (ycord_li >= ic_y_dim_p) & (ycord_li < ic_y_dim_p+cc_y_dim_p);
wire cord_in_mc_li = (ycord_li >= ic_y_dim_p+cc_y_dim_p);
wire cord_in_cac_li = (xcord_li >= cc_x_dim_p+sac_x_dim_p);
wire cord_in_sac_li = (xcord_li < sac_x_dim_p);
wire cord_in_io_li = (ycord_li < ic_y_dim_p);
assign core_id_o = cce_id_o;
always_comb
if (cord_in_cc_li)
begin
cce_id_o = (xcord_li-sac_x_dim_p) + cc_x_dim_p * (ycord_li-ic_y_dim_p);
lce_id0_o = (cce_id_o << 1'b1) + 1'b0;
lce_id1_o = (cce_id_o << 1'b1) + 1'b1;
end
else if (cord_in_mc_li)
begin
cce_id_o = max_cc_cce_lp + (xcord_li-sac_x_dim_p);
lce_id0_o = max_cac_lce_lp + (xcord_li-sac_x_dim_p);
lce_id1_o = 'X;
end
else if (cord_in_cac_li)
begin
cce_id_o = max_mc_cce_lp + (ycord_li-ic_y_dim_p);
lce_id0_o = max_cc_lce_lp + (ycord_li-ic_y_dim_p);
lce_id1_o = 'X;
end
else if (cord_in_sac_li)
begin
cce_id_o = max_cac_cce_lp + (ycord_li-ic_y_dim_p);
lce_id0_o = max_mc_lce_lp + (ycord_li-ic_y_dim_p);
lce_id1_o = 'X;
end
else // if (cord_in_io_li)
begin
cce_id_o = max_sac_cce_lp + (xcord_li-sac_x_dim_p);
lce_id0_o = max_sac_lce_lp + (xcord_li-sac_x_dim_p);
lce_id1_o = 'X;
end
endmodule
| 8.335771 |
module bp_me_nonsynth_lce_tr_tracer
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_nonsynth_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_unicore_half_cfg
`declare_bp_proc_params(bp_params_p)
, parameter sets_p = "inv"
, parameter block_width_p = "inv"
, localparam lce_trace_file_p = "lce_tr"
, localparam lg_sets_lp = `BSG_SAFE_CLOG2(sets_p)
, localparam block_size_in_bytes_lp=(block_width_p / 8)
, localparam block_offset_bits_lp=`BSG_SAFE_CLOG2(block_size_in_bytes_lp)
, localparam lce_opcode_width_lp=$bits(bp_me_nonsynth_lce_opcode_e)
, localparam tr_ring_width_lp=`bp_me_nonsynth_lce_tr_pkt_width(paddr_width_p, dword_width_p)
)
(
input clk_i
,input reset_i
,input freeze_i
,input [lce_id_width_p-1:0] lce_id_i
,input [tr_ring_width_lp-1:0] tr_pkt_i
,input tr_pkt_v_i
,input tr_pkt_yumi_i
,input [tr_ring_width_lp-1:0] tr_pkt_o_i
,input tr_pkt_v_o_i
,input tr_pkt_ready_i
);
// Trace Replay Interface
`declare_bp_me_nonsynth_lce_tr_pkt_s(paddr_width_p, dword_width_p);
bp_me_nonsynth_lce_tr_pkt_s tr_cmd, tr_resp;
assign tr_cmd = tr_pkt_i;
assign tr_resp = tr_pkt_o_i;
integer file;
string file_name;
always_ff @(negedge reset_i) begin
file_name = $sformatf("%s_%x.trace", lce_trace_file_p, lce_id_i);
file = $fopen(file_name, "w");
end
time tr_start_t;
always_ff @(negedge clk_i) begin
if (reset_i) begin
tr_start_t <= '0;
end else begin // ~reset_i
tr_start_t <= tr_start_t;
// Trace Replay
if (tr_pkt_v_i & tr_pkt_yumi_i) begin
tr_start_t <= $time;
$fdisplay(file, "[%t]: LCE[%0d] TR cmd op[%b] uc[%b] addr[%H] set[%d] %H"
, $time, lce_id_i, tr_cmd.cmd, tr_cmd.uncached, tr_cmd.paddr
, tr_cmd.paddr[block_offset_bits_lp +: lg_sets_lp], tr_cmd.data
);
end
if (tr_pkt_v_o_i & tr_pkt_ready_i) begin
$fdisplay(file, "[%t]: LCE[%0d] TR resp cmd[%b] uc[%b] addr[%H] set[%d] %H time[%0t]"
, $time, lce_id_i, tr_resp.cmd, tr_resp.uncached, tr_resp.paddr
, tr_resp.paddr[block_offset_bits_lp +: lg_sets_lp]
, tr_resp.data, $time-tr_start_t
);
end
end // ~reset_i
end // always_ff
endmodule
| 7.105833 |
module bp_me_nonsynth_mock_lce_tag_lookup
import bp_common_pkg::*;
import bp_cce_pkg::*;
#(
parameter assoc_p = "inv"
, parameter ptag_width_p = "inv"
, localparam dir_entry_width_lp = `bp_cce_dir_entry_width(ptag_width_p)
, localparam lg_assoc_lp = `BSG_SAFE_CLOG2(assoc_p)
) (
input [assoc_p-1:0][dir_entry_width_lp-1:0] tag_set_i
, input [ptag_width_p-1:0] ptag_i
, output logic hit_o
, output logic dirty_o
, output logic [lg_assoc_lp-1:0] way_o
, output bp_coh_states_e state_o
);
`declare_bp_cce_dir_entry_s(ptag_width_p);
dir_entry_s [assoc_p-1:0] tags;
assign tags = tag_set_i;
logic [assoc_p-1:0] hits;
genvar i;
generate
for (i = 0; i < assoc_p; i = i + 1) begin
assign hits[i] = ((tags[i].tag == ptag_i) && (tags[i].state != e_COH_I));
end
endgenerate
logic way_v_lo;
logic [lg_assoc_lp-1:0] way_lo;
bsg_encode_one_hot #(
.width_p(assoc_p)
) hits_to_way_id (
.i(hits)
, .addr_o(way_lo)
, .v_o(way_v_lo)
);
// suppress unused warning
wire unused0 = way_v_lo;
// hit_o is set if tag matched and coherence state was any valid state
assign hit_o = |hits;
assign way_o = way_lo;
assign dirty_o = (tags[way_o].state == e_COH_M);
assign state_o = tags[way_o].state;
endmodule
| 7.105833 |
module bp_me_wormhole_packet_encode_lce_cmd
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
, localparam lce_cmd_packet_width_lp =
`bsg_wormhole_concentrator_packet_width(coh_noc_cord_width_p, coh_noc_len_width_p, coh_noc_cid_width_p, lce_cmd_width_lp)
)
(input [lce_cmd_width_lp-1:0] payload_i
, output [lce_cmd_packet_width_lp-1:0] packet_o
);
`declare_bp_lce_cce_if(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
`declare_bsg_wormhole_concentrator_packet_s(coh_noc_cord_width_p, coh_noc_len_width_p, coh_noc_cid_width_p, lce_cmd_width_lp, lce_cmd_packet_s);
bp_lce_cmd_s payload_cast_i;
lce_cmd_packet_s packet_cast_o;
assign payload_cast_i = payload_i;
assign packet_o = packet_cast_o;
localparam lce_cmd_cmd_len_lp =
`BSG_CDIV(lce_cmd_packet_width_lp-$bits(payload_cast_i.data), coh_noc_flit_width_p) - 1;
localparam lce_cmd_data_len_lp =
`BSG_CDIV(lce_cmd_packet_width_lp, coh_noc_flit_width_p) - 1;
localparam lce_cmd_uc_data_len_lp =
`BSG_CDIV(lce_cmd_packet_width_lp-(cce_block_width_p-dword_width_p), coh_noc_flit_width_p) - 1;
logic [coh_noc_cord_width_p-1:0] lce_cord_li;
logic [coh_noc_cid_width_p-1:0] lce_cid_li;
bp_me_lce_id_to_cord
#(.bp_params_p(bp_params_p))
router_cord
(.lce_id_i(payload_cast_i.header.dst_id)
,.lce_cord_o(lce_cord_li)
,.lce_cid_o(lce_cid_li)
);
always_comb begin
packet_cast_o.payload = payload_cast_i;
packet_cast_o.cid = lce_cid_li;
packet_cast_o.cord = lce_cord_li;
case (payload_cast_i.header.msg_type)
e_lce_cmd_sync
,e_lce_cmd_set_clear
,e_lce_cmd_transfer
,e_lce_cmd_writeback
,e_lce_cmd_set_tag
,e_lce_cmd_set_tag_wakeup
,e_lce_cmd_invalidate_tag
,e_lce_cmd_uc_st_done: packet_cast_o.len = coh_noc_len_width_p'(lce_cmd_cmd_len_lp);
e_lce_cmd_data : packet_cast_o.len = coh_noc_len_width_p'(lce_cmd_data_len_lp);
e_lce_cmd_uc_data : packet_cast_o.len = coh_noc_len_width_p'(lce_cmd_uc_data_len_lp);
default: packet_cast_o = '0;
endcase
end
endmodule
| 6.597197 |
module bp_me_wormhole_packet_encode_lce_req
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
, localparam lce_cce_req_packet_width_lp =
`bsg_wormhole_concentrator_packet_width(coh_noc_cord_width_p, coh_noc_len_width_p, coh_noc_cid_width_p, lce_cce_req_width_lp)
)
(input [lce_cce_req_width_lp-1:0] payload_i
, output [lce_cce_req_packet_width_lp-1:0] packet_o
);
`declare_bp_lce_cce_if(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p);
`declare_bsg_wormhole_concentrator_packet_s(coh_noc_cord_width_p, coh_noc_len_width_p, coh_noc_cid_width_p, lce_cce_req_width_lp, lce_cce_req_packet_s);
bp_lce_cce_req_s payload_cast_i;
lce_cce_req_packet_s packet_cast_o;
assign payload_cast_i = payload_i;
assign packet_o = packet_cast_o;
// TODO: remove commented code after testing. Normal request and UC Rd have length = header = full msg - dword_width_p
// UC Store is header + dword_width_p = full length
localparam lce_cce_req_req_len_lp =
`BSG_CDIV(lce_cce_req_packet_width_lp-$bits(payload_cast_i.data), coh_noc_flit_width_p) - 1;
//`BSG_CDIV(lce_cce_req_packet_width_lp-$bits(payload_cast_i.msg.req.pad), coh_noc_flit_width_p) - 1;
localparam lce_cce_req_uc_wr_len_lp =
`BSG_CDIV(lce_cce_req_packet_width_lp, coh_noc_flit_width_p) - 1;
localparam lce_cce_req_uc_rd_len_lp =
`BSG_CDIV(lce_cce_req_packet_width_lp-$bits(payload_cast_i.data), coh_noc_flit_width_p) - 1;
//`BSG_CDIV(lce_cce_req_packet_width_lp-$bits(payload_cast_i.msg.uc_req.data), coh_noc_flit_width_p) - 1;
logic [coh_noc_cord_width_p-1:0] cce_cord_li;
logic [coh_noc_cid_width_p-1:0] cce_cid_li;
bp_me_cce_id_to_cord
#(.bp_params_p(bp_params_p))
router_cord
(.cce_id_i(payload_cast_i.header.dst_id)
,.cce_cord_o(cce_cord_li)
,.cce_cid_o(cce_cid_li)
);
always_comb begin
packet_cast_o.payload = payload_cast_i;
packet_cast_o.cid = cce_cid_li;
packet_cast_o.cord = cce_cord_li;
case (payload_cast_i.header.msg_type)
e_lce_req_type_rd
,e_lce_req_type_wr : packet_cast_o.len = coh_noc_len_width_p'(lce_cce_req_req_len_lp);
e_lce_req_type_uc_rd: packet_cast_o.len = coh_noc_len_width_p'(lce_cce_req_uc_wr_len_lp);
e_lce_req_type_uc_wr: packet_cast_o.len = coh_noc_len_width_p'(lce_cce_req_uc_wr_len_lp);
default: packet_cast_o = '0;
endcase
end
endmodule
| 6.597197 |
module bp_me_wormhole_packet_encode_lce_resp
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
, localparam lce_cce_resp_packet_width_lp =
`bsg_wormhole_concentrator_packet_width(coh_noc_cord_width_p, coh_noc_len_width_p, coh_noc_cid_width_p, lce_cce_resp_width_lp)
)
(input [lce_cce_resp_width_lp-1:0] payload_i
, output [lce_cce_resp_packet_width_lp-1:0] packet_o
);
`declare_bp_lce_cce_if(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p);
`declare_bsg_wormhole_concentrator_packet_s(coh_noc_cord_width_p, coh_noc_len_width_p, coh_noc_cid_width_p, lce_cce_resp_width_lp, lce_cce_resp_packet_s);
bp_lce_cce_resp_s payload_cast_i;
lce_cce_resp_packet_s packet_cast_o;
assign payload_cast_i = payload_i;
assign packet_o = packet_cast_o;
localparam lce_cce_resp_ack_len_lp =
`BSG_CDIV(lce_cce_resp_packet_width_lp-$bits(payload_cast_i.data), coh_noc_flit_width_p) - 1;
localparam lce_cce_resp_wb_len_lp =
`BSG_CDIV(lce_cce_resp_packet_width_lp, coh_noc_flit_width_p) - 1;
logic [coh_noc_cord_width_p-1:0] cce_cord_li;
logic [coh_noc_cid_width_p-1:0] cce_cid_li;
bp_me_cce_id_to_cord
#(.bp_params_p(bp_params_p))
router_cord
(.cce_id_i(payload_cast_i.header.dst_id)
,.cce_cord_o(cce_cord_li)
,.cce_cid_o(cce_cid_li)
);
always_comb begin
packet_cast_o.payload = payload_cast_i;
packet_cast_o.cid = cce_cid_li;
packet_cast_o.cord = cce_cord_li;
case (payload_cast_i.header.msg_type)
e_lce_cce_sync_ack
,e_lce_cce_inv_ack
,e_lce_cce_coh_ack : packet_cast_o.len = coh_noc_len_width_p'(lce_cce_resp_ack_len_lp);
e_lce_cce_resp_wb : packet_cast_o.len = coh_noc_len_width_p'(lce_cce_resp_wb_len_lp);
e_lce_cce_resp_null_wb: packet_cast_o.len = coh_noc_len_width_p'(lce_cce_resp_ack_len_lp);
default: packet_cast_o = '0;
endcase
end
endmodule
| 6.597197 |
module bp_me_wormhole_packet_encode_mem_cmd
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
, parameter flit_width_p = "inv"
, parameter cord_width_p = "inv"
, parameter cid_width_p = "inv"
, parameter len_width_p = "inv"
, localparam mem_cmd_packet_width_lp =
`bp_mem_wormhole_packet_width(flit_width_p, cord_width_p, len_width_p, cid_width_p, cce_mem_msg_width_lp-cce_block_width_p, cce_block_width_p)
)
(input [cce_mem_msg_width_lp-1:0] mem_cmd_i
, input [cord_width_p-1:0] src_cord_i
, input [cid_width_p-1:0] src_cid_i
, input [cord_width_p-1:0] dst_cord_i
, input [cid_width_p-1:0] dst_cid_i
, output [mem_cmd_packet_width_lp-1:0] packet_o
);
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
`declare_bp_mem_wormhole_packet_s(flit_width_p, cord_width_p, len_width_p, cid_width_p, cce_mem_msg_width_lp-cce_block_width_p, cce_block_width_p, bp_cmd_wormhole_packet_s);
bp_cce_mem_msg_s mem_cmd_cast_i;
bp_cmd_wormhole_packet_s packet_cast_o;
assign mem_cmd_cast_i = mem_cmd_i;
assign packet_o = packet_cast_o;
localparam mem_cmd_req_len_lp =
`BSG_CDIV(mem_cmd_packet_width_lp-$bits(mem_cmd_cast_i.data), mem_noc_flit_width_p) - 1;
localparam mem_cmd_data_len_1_lp =
`BSG_CDIV(mem_cmd_packet_width_lp-$bits(mem_cmd_cast_i.data) + 8*1, mem_noc_flit_width_p) - 1;
localparam mem_cmd_data_len_2_lp =
`BSG_CDIV(mem_cmd_packet_width_lp-$bits(mem_cmd_cast_i.data) + 8*2, mem_noc_flit_width_p) - 1;
localparam mem_cmd_data_len_4_lp =
`BSG_CDIV(mem_cmd_packet_width_lp-$bits(mem_cmd_cast_i.data) + 8*4, mem_noc_flit_width_p) - 1;
localparam mem_cmd_data_len_8_lp =
`BSG_CDIV(mem_cmd_packet_width_lp-$bits(mem_cmd_cast_i.data) + 8*8, mem_noc_flit_width_p) - 1;
localparam mem_cmd_data_len_16_lp =
`BSG_CDIV(mem_cmd_packet_width_lp-$bits(mem_cmd_cast_i.data) + 8*16, mem_noc_flit_width_p) - 1;
localparam mem_cmd_data_len_32_lp =
`BSG_CDIV(mem_cmd_packet_width_lp-$bits(mem_cmd_cast_i.data) + 8*32, mem_noc_flit_width_p) - 1;
localparam mem_cmd_data_len_64_lp =
`BSG_CDIV(mem_cmd_packet_width_lp-$bits(mem_cmd_cast_i.data) + 8*64, mem_noc_flit_width_p) - 1;
logic [len_width_p-1:0] data_cmd_len_li;
always_comb begin
packet_cast_o = '0;
packet_cast_o.data = mem_cmd_cast_i.data;
packet_cast_o.msg = mem_cmd_cast_i[0+:cce_mem_msg_width_lp-cce_block_width_p];
packet_cast_o.src_cord = src_cord_i;
packet_cast_o.src_cid = src_cid_i;
packet_cast_o.cord = dst_cord_i;
packet_cast_o.cid = dst_cid_i;
case (mem_cmd_cast_i.header.size)
e_mem_size_1 : data_cmd_len_li = len_width_p'(mem_cmd_data_len_1_lp);
e_mem_size_2 : data_cmd_len_li = len_width_p'(mem_cmd_data_len_2_lp);
e_mem_size_4 : data_cmd_len_li = len_width_p'(mem_cmd_data_len_4_lp);
e_mem_size_8 : data_cmd_len_li = len_width_p'(mem_cmd_data_len_8_lp);
e_mem_size_16: data_cmd_len_li = len_width_p'(mem_cmd_data_len_16_lp);
e_mem_size_32: data_cmd_len_li = len_width_p'(mem_cmd_data_len_32_lp);
e_mem_size_64: data_cmd_len_li = len_width_p'(mem_cmd_data_len_64_lp);
default: data_cmd_len_li = '0;
endcase
case (mem_cmd_cast_i.header.msg_type)
e_cce_mem_rd
,e_cce_mem_wr
,e_cce_mem_uc_rd: packet_cast_o.len = len_width_p'(mem_cmd_req_len_lp);
e_cce_mem_uc_wr
,e_cce_mem_wb : packet_cast_o.len = data_cmd_len_li;
default: packet_cast_o = '0;
endcase
end
endmodule
| 6.597197 |
module bp_me_wormhole_packet_encode_mem_resp
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
, parameter flit_width_p = "inv"
, parameter cord_width_p = "inv"
, parameter cid_width_p = "inv"
, parameter len_width_p = "inv"
, localparam mem_resp_packet_width_lp =
`bp_mem_wormhole_packet_width(flit_width_p, cord_width_p, len_width_p, cid_width_p, cce_mem_msg_width_lp-cce_block_width_p, cce_block_width_p)
)
(input [cce_mem_msg_width_lp-1:0] mem_resp_i
, input [cord_width_p-1:0] src_cord_i
, input [cid_width_p-1:0] src_cid_i
, input [cord_width_p-1:0] dst_cord_i
, input [cid_width_p-1:0] dst_cid_i
, output [mem_resp_packet_width_lp-1:0] packet_o
);
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
`declare_bp_mem_wormhole_packet_s(flit_width_p, cord_width_p, len_width_p, cid_width_p, cce_mem_msg_width_lp-cce_block_width_p, cce_block_width_p, bp_resp_wormhole_packet_s);
bp_cce_mem_msg_s mem_resp_cast_i;
bp_resp_wormhole_packet_s packet_cast_o;
assign mem_resp_cast_i = mem_resp_i;
assign packet_o = packet_cast_o;
localparam mem_resp_ack_len_lp =
`BSG_CDIV(mem_resp_packet_width_lp-$bits(mem_resp_cast_i.data), mem_noc_flit_width_p) - 1;
localparam mem_resp_data_len_1_lp =
`BSG_CDIV(mem_resp_packet_width_lp-$bits(mem_resp_cast_i.data) + 8*1, mem_noc_flit_width_p) - 1;
localparam mem_resp_data_len_2_lp =
`BSG_CDIV(mem_resp_packet_width_lp-$bits(mem_resp_cast_i.data) + 8*2, mem_noc_flit_width_p) - 1;
localparam mem_resp_data_len_4_lp =
`BSG_CDIV(mem_resp_packet_width_lp-$bits(mem_resp_cast_i.data) + 8*4, mem_noc_flit_width_p) - 1;
localparam mem_resp_data_len_8_lp =
`BSG_CDIV(mem_resp_packet_width_lp-$bits(mem_resp_cast_i.data) + 8*8, mem_noc_flit_width_p) - 1;
localparam mem_resp_data_len_16_lp =
`BSG_CDIV(mem_resp_packet_width_lp-$bits(mem_resp_cast_i.data) + 8*16, mem_noc_flit_width_p) - 1;
localparam mem_resp_data_len_32_lp =
`BSG_CDIV(mem_resp_packet_width_lp-$bits(mem_resp_cast_i.data) + 8*32, mem_noc_flit_width_p) - 1;
localparam mem_resp_data_len_64_lp =
`BSG_CDIV(mem_resp_packet_width_lp-$bits(mem_resp_cast_i.data) + 8*64, mem_noc_flit_width_p) - 1;
logic [len_width_p-1:0] data_resp_len_li;
always_comb begin
packet_cast_o = '0;
packet_cast_o.data = mem_resp_cast_i.data;
packet_cast_o.msg = mem_resp_cast_i[0+:cce_mem_msg_width_lp-cce_block_width_p];
packet_cast_o.src_cord = src_cord_i;
packet_cast_o.src_cid = src_cid_i;
packet_cast_o.cord = dst_cord_i;
packet_cast_o.cid = dst_cid_i;
case (mem_resp_cast_i.header.size)
e_mem_size_1 : data_resp_len_li = len_width_p'(mem_resp_data_len_1_lp);
e_mem_size_2 : data_resp_len_li = len_width_p'(mem_resp_data_len_2_lp);
e_mem_size_4 : data_resp_len_li = len_width_p'(mem_resp_data_len_4_lp);
e_mem_size_8 : data_resp_len_li = len_width_p'(mem_resp_data_len_8_lp);
e_mem_size_16: data_resp_len_li = len_width_p'(mem_resp_data_len_16_lp);
e_mem_size_32: data_resp_len_li = len_width_p'(mem_resp_data_len_32_lp);
e_mem_size_64: data_resp_len_li = len_width_p'(mem_resp_data_len_64_lp);
default: data_resp_len_li = '0;
endcase
case (mem_resp_cast_i.header.msg_type)
e_cce_mem_rd
,e_cce_mem_wr
,e_cce_mem_uc_rd: packet_cast_o.len = data_resp_len_li;
e_cce_mem_uc_wr
,e_cce_mem_wb : packet_cast_o.len = len_width_p'(mem_resp_ack_len_lp);
default: packet_cast_o = '0;
endcase
end
endmodule
| 6.597197 |
module bp_nonsynth_if_verif
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_common_rv64_pkg::*;
import bp_cce_pkg::*;
import bsg_noc_pkg::*;
import bp_common_cfg_link_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_fe_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
, localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, cce_pc_width_p, cce_instr_width_p)
)
();
bp_proc_param_s proc_param;
assign proc_param = all_cfgs_gp[bp_params_p];
`declare_bp_cfg_bus_s(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, cce_pc_width_p, cce_instr_width_p);
`declare_bp_fe_be_if(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p);
`declare_bp_lce_cce_if(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p);
initial
begin
$display("########### BP Parameters ##############");
// This throws an std::length_error in Verilator 4.031 based on the length of
// this (admittedly massive) parameter
`ifndef VERILATOR
$display("bp_params_e %s: bp_proc_param_s %p", bp_params_p.name(), proc_param);
`endif
$display("########### TOP IF ##############");
$display("bp_cfg_bus_s bits: struct %d width %d", $bits(bp_cfg_bus_s), cfg_bus_width_lp);
$display("########### FE-BE IF ##############");
$display("bp_fe_queue_s bits: struct %d width %d", $bits(bp_fe_queue_s), fe_queue_width_lp);
$display("bp_fe_cmd_s bits: struct %d width %d", $bits(bp_fe_cmd_s), fe_cmd_width_lp);
$display("########### LCE-CCE IF ##############");
$display("bp_lce_cce_req_s bits: struct %d width %d", $bits(bp_lce_cce_req_s), lce_cce_req_width_lp);
$display("bp_lce_cmd_s bits: struct %d width %d", $bits(bp_lce_cmd_s), lce_cmd_width_lp);
$display("bp_lce_cce_resp_s bits: struct %d width %d", $bits(bp_lce_cce_resp_s), lce_cce_resp_width_lp);
$display("########### CCE-MEM IF ##############");
$display("bp_cce_mem_msg_s bits: struct %d width %d", $bits(bp_cce_mem_msg_s), cce_mem_msg_width_lp);
if (!(num_cce_p inside {1,2,3,4,6,7,8,12,14,15,16,24,28,30,31,32})) begin
$fatal("Error: unsupported number of CCE's");
end
end
if (ic_y_dim_p != 1)
$fatal("Error: Must have exactly 1 row of I/O routers");
if (mc_y_dim_p != 0)
$fatal("Error: L2 expansion nodes not yet supported, MC must have 0 rows");
if (sac_x_dim_p > 1)
$fatal("Error: Must have <= 1 column of streaming accelerators");
if (cac_x_dim_p > 1)
$fatal("Error: Must have <= 1 column of coherent accelerators");
if ((cce_block_width_p == 256) && (dcache_assoc_p == 8 || icache_assoc_p == 8))
$fatal("Error: We can't maintain 64-bit dwords with a 256-bit cache block size and 8-way cache associativity");
if ((cce_block_width_p == 128) && (dcache_assoc_p == 4 || dcache_assoc_p == 8 || icache_assoc_p == 4 || icache_assoc_p == 8))
$fatal("Error: We can't maintain 64-bit dwords with a 128-bit cache block size and 4-way or 8-way cache associativity");
if (vaddr_width_p != 39)
$warning("Warning: VM will not work without 39 bit vaddr");
if (paddr_width_p != 40)
$warning("Warning: paddr != 40 has not been tested");
if ((cce_block_width_p != icache_block_width_p) && (cce_block_width_p != dcache_block_width_p) && (cce_block_width_p != acache_block_width_p))
$warning("Warning: Different cache block widths not yet supported");
endmodule
| 7.319939 |
module bp_nonsynth_pc_profiler
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
, parameter pc_trace_file_p = "pc"
, localparam commit_pkt_width_lp = `bp_be_commit_pkt_width(vaddr_width_p)
)
(input clk_i
, input reset_i
, input freeze_i
, input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i
// Commit packet
, input [commit_pkt_width_lp-1:0] commit_pkt
, input [num_core_p-1:0] program_finish_i
);
`declare_bp_be_internal_if_structs(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p);
bp_be_commit_pkt_s commit_pkt_cast_i;
assign commit_pkt_cast_i = commit_pkt;
integer histogram [longint];
integer file;
string file_name;
wire reset_li = reset_i | freeze_i;
always_ff @(negedge reset_li)
begin
file_name = $sformatf("%s_%x.histogram", pc_trace_file_p, mhartid_i);
file = $fopen(file_name, "w");
end
logic [dword_width_p-1:0] count;
always_ff @(posedge clk_i)
begin
if (reset_i)
count <= '0;
else
count <= count + 1'b1;
if (commit_pkt_cast_i.v)
if (histogram.exists(commit_pkt_cast_i.pc))
histogram[commit_pkt_cast_i.pc] <= histogram[commit_pkt_cast_i.pc] + 1'b1;
else
histogram[commit_pkt_cast_i.pc] <= 1'b1;
end
logic [num_core_p-1:0] program_finish_r;
bsg_dff_reset
#(.width_p(num_core_p))
program_finish_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(program_finish_i)
,.data_o(program_finish_r)
);
always_ff @(negedge clk_i)
if (program_finish_i[mhartid_i] & ~program_finish_r[mhartid_i])
foreach (histogram[key])
$fwrite(file, "[%x] %x\n", key, histogram[key]);
endmodule
| 7.102586 |
module bp_nonsynth_perf
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_common_rv64_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
, localparam max_instr_lp = 2**30-1
, localparam max_clock_lp = 2**30-1
)
(input clk_i
, input reset_i
, input freeze_i
, input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i
, input [31:0] warmup_instr_i
, input commit_v_i
, input is_debug_mode_i
);
logic [29:0] warmup_cnt;
logic warm;
bsg_counter_clear_up
#(.max_val_p(2**30-1), .init_val_p(0))
warmup_counter
(.clk_i(clk_i)
,.reset_i(reset_i | freeze_i)
,.clear_i(1'b0)
,.up_i(commit_v_i & ~warm)
,.count_o(warmup_cnt)
);
assign warm = (warmup_cnt == warmup_instr_i);
logic [63:0] clk_cnt_r;
logic [63:0] instr_cnt_r;
logic [num_core_p-1:0] program_finish_r;
always_ff @(posedge clk_i)
begin
if (reset_i | freeze_i | ~warm | is_debug_mode_i)
begin
clk_cnt_r <= '0;
instr_cnt_r <= '0;
end
else
begin
clk_cnt_r <= clk_cnt_r + 64'b1;
instr_cnt_r <= instr_cnt_r + commit_v_i;
end
end
logic [`BSG_SAFE_CLOG2(max_instr_lp+1)-1:0] instr_cnt;
bsg_counter_clear_up
#(.max_val_p(max_instr_lp), .init_val_p(0))
instr_counter
(.clk_i(clk_i)
,.reset_i(reset_i | freeze_i | is_debug_mode_i)
,.clear_i(1'b0)
,.up_i(commit_v_i)
,.count_o(instr_cnt)
);
logic [`BSG_SAFE_CLOG2(max_clock_lp+1)-1:0] clk_cnt;
bsg_counter_clear_up
#(.max_val_p(max_clock_lp), .init_val_p(0))
clk_counter
(.clk_i(clk_i)
,.reset_i(reset_i | freeze_i | is_debug_mode_i)
,.clear_i(1'b0)
,.up_i(commit_v_i)
,.count_o(clk_cnt)
);
final
begin
$display("[CORE%0x STATS]", mhartid_i);
$display("\tclk : %d", clk_cnt_r);
$display("\tinstr : %d", instr_cnt_r);
$display("\tmIPC : %d", instr_cnt_r * 1000 / clk_cnt_r);
end
endmodule
| 7.102586 |
module bp_nonsynth_watchdog
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_common_rv64_pkg::*;
import bp_be_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
, parameter timeout_cycles_p = "inv"
, parameter heartbeat_instr_p = "inv"
// Something super big
, parameter max_instr_lp = 2**30
)
(input clk_i
, input reset_i
, input freeze_i
, input [`BSG_SAFE_CLOG2(num_core_p)-1:0] mhartid_i
, input [vaddr_width_p-1:0] npc_i
, input instret_i
);
logic [vaddr_width_p-1:0] npc_r;
bsg_dff_reset
#(.width_p(vaddr_width_p))
npc_reg
(.clk_i(clk_i)
,.reset_i(reset_i | freeze_i)
,.data_i(npc_i)
,.data_o(npc_r)
);
wire npc_change = (npc_i != npc_r);
logic [`BSG_SAFE_CLOG2(timeout_cycles_p)-1:0] stall_cnt;
bsg_counter_clear_up
#(.max_val_p(timeout_cycles_p), .init_val_p(0))
stall_counter
(.clk_i(clk_i)
,.reset_i(reset_i | freeze_i)
,.clear_i(npc_change)
,.up_i(1'b1)
,.count_o(stall_cnt)
);
logic [`BSG_SAFE_CLOG2(max_instr_lp+1)-1:0] instr_cnt;
bsg_counter_clear_up
#(.max_val_p(max_instr_lp), .init_val_p(0))
instr_counter
(.clk_i(clk_i)
,.reset_i(reset_i | freeze_i)
,.clear_i(1'b0)
,.up_i(instret_i)
,.count_o(instr_cnt)
);
always_ff @(negedge clk_i)
if (reset_i === '0 && (stall_cnt >= timeout_cycles_p))
begin
$display("FAIL! Core %x stalled for %d cycles!", mhartid_i, stall_cnt);
$finish();
end
else if (reset_i === '0 && (npc_r === 'X))
begin
$display("FAIL! Core %x PC has become X!", mhartid_i);
$finish();
end
always_ff @(negedge clk_i)
begin
if (reset_i === '0 && (instr_cnt > '0) && (instr_cnt % heartbeat_instr_p == '0))
begin
$display("BEAT: %d instructions completed (%d total)", heartbeat_instr_p, instr_cnt);
end
end
endmodule
| 7.091234 |
module bp_osc #(
parameter WIDTH = 8
) (
input wire clk,
input wire reset_n,
input wire [(WIDTH - 1) : 0] opa,
input wire [(WIDTH - 1) : 0] opb,
output wire dout
);
//----------------------------------------------------------------
// Registers.
//----------------------------------------------------------------
reg dout_reg;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [WIDTH : 0] sum;
reg cin;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign dout = dout_reg;
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
dout_reg <= 1'b0;
end else begin
dout_reg <= cin;
end
end
//----------------------------------------------------------------
// adder_osc
//
// Adder logic that generates the oscillator.
//
// NOTE: This logic contains a combinational loop and does
// not play well with an event driven simulator.
//----------------------------------------------------------------
always @* begin : adder_osc
cin = ~sum[WIDTH];
sum = opa + opb + cin;
end
endmodule
| 7.617924 |
module bp_pma_05 (
ptag_v_i,
ptag_i,
uncached_o
);
input [27:0] ptag_i;
input ptag_v_i;
output uncached_o;
wire uncached_o, is_local_addr, N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10;
assign N0 = ptag_i[26] | ptag_i[27];
assign N1 = ptag_i[25] | N0;
assign is_local_addr = ~N9;
assign N9 = N8 | ptag_i[19];
assign N8 = N7 | ptag_i[20];
assign N7 = N6 | ptag_i[21];
assign N6 = N5 | ptag_i[22];
assign N5 = N4 | ptag_i[23];
assign N4 = N3 | ptag_i[24];
assign N3 = N2 | ptag_i[25];
assign N2 = ptag_i[27] | ptag_i[26];
assign uncached_o = ptag_v_i & N10;
assign N10 = is_local_addr | N1;
endmodule
| 6.996792 |
module bp_sacc_tile_node
import bp_common_pkg::*;
import bp_common_rv64_pkg::*;
import bp_common_aviary_pkg::*;
import bp_be_pkg::*;
import bp_cce_pkg::*;
import bsg_noc_pkg::*;
import bp_common_cfg_link_pkg::*;
import bsg_wormhole_router_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
`declare_bp_lce_cce_if_widths(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
, localparam coh_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(coh_noc_flit_width_p)
, localparam mem_noc_ral_link_width_lp = `bsg_ready_and_link_sif_width(mem_noc_flit_width_p)
, parameter accelerator_type_p = 1
)
(input core_clk_i
, input core_reset_i
, input coh_clk_i
, input coh_reset_i
, input [coh_noc_cord_width_p-1:0] my_cord_i
// Connected to other tiles on east and west
, input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_i
, output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_req_link_o
, input [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_i
, output [S:W][coh_noc_ral_link_width_lp-1:0] coh_lce_cmd_link_o
);
`declare_bp_lce_cce_if(cce_id_width_p, lce_id_width_p, paddr_width_p, lce_assoc_p, dword_width_p, cce_block_width_p)
`declare_bp_me_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p)
// Declare the routing links
`declare_bsg_ready_and_link_sif_s(coh_noc_flit_width_p, bp_coh_ready_and_link_s);
// Tile-side coherence connections
bp_coh_ready_and_link_s accel_lce_req_link_li, accel_lce_req_link_lo;
bp_coh_ready_and_link_s accel_lce_cmd_link_li, accel_lce_cmd_link_lo;
bp_sacc_tile
#(.bp_params_p(bp_params_p))
accel_tile
(.clk_i(core_clk_i)
,.reset_i(core_reset_i)
,.my_cord_i(my_cord_i)
,.lce_req_link_i(accel_lce_req_link_li)
,.lce_req_link_o(accel_lce_req_link_lo)
,.lce_cmd_link_i(accel_lce_cmd_link_li)
,.lce_cmd_link_o(accel_lce_cmd_link_lo)
);
bp_nd_socket
#(.flit_width_p(coh_noc_flit_width_p)
,.dims_p(coh_noc_dims_p)
,.cord_dims_p(coh_noc_dims_p)
,.cord_markers_pos_p(coh_noc_cord_markers_pos_p)
,.len_width_p(coh_noc_len_width_p)
,.routing_matrix_p(StrictYX)
,.async_clk_p(async_coh_clk_p)
,.els_p(2)
)
sac_coh_socket
(.tile_clk_i(core_clk_i)
,.tile_reset_i(core_reset_i)
,.network_clk_i(coh_clk_i)
,.network_reset_i(coh_reset_i)
,.my_cord_i(my_cord_i)
,.network_link_i({coh_lce_req_link_i, coh_lce_cmd_link_i})
,.network_link_o({coh_lce_req_link_o, coh_lce_cmd_link_o})
,.tile_link_i({accel_lce_req_link_lo, accel_lce_cmd_link_lo})
,.tile_link_o({accel_lce_req_link_li, accel_lce_cmd_link_li})
);
endmodule
| 7.50845 |
module bp_stream_mmio
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_cce_pkg::*;
import bp_be_pkg::*;
import bp_be_dcache_pkg::*;
#(parameter bp_cfg_e cfg_p = e_bp_inv_cfg
`declare_bp_proc_params(cfg_p)
,localparam cce_mshr_width_lp = `bp_cce_mshr_width(num_lce_p, lce_assoc_p, paddr_width_p)
`declare_bp_me_if_widths(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p, cce_mshr_width_lp)
,parameter stream_data_width_p = 32
)
(input clk_i
,input reset_i
,input [cce_mem_data_cmd_width_lp-1:0] io_data_cmd_i
,input io_data_cmd_v_i
,output io_data_cmd_yumi_o
,output [mem_cce_resp_width_lp-1:0] io_resp_o
,output io_resp_v_o
,input io_resp_ready_i
,input stream_v_i
,input [stream_data_width_p-1:0] stream_data_i
,output stream_ready_o
,output stream_v_o
,output [stream_data_width_p-1:0] stream_data_o
,input stream_yumi_i
);
`declare_bp_me_if(paddr_width_p, cce_block_width_p, num_lce_p, lce_assoc_p, cce_mshr_width_lp);
// Temporarily support cce_data_size less than stream_data_width_p only
// Temporarily support response of 64-bits data only
bp_cce_mem_data_cmd_s io_data_cmd;
bp_mem_cce_resp_s io_resp;
assign io_data_cmd = io_data_cmd_i;
// streaming out fifo
logic out_fifo_v_li, out_fifo_ready_lo;
logic [stream_data_width_p-1:0] out_fifo_data_li;
bsg_two_fifo
#(.width_p(stream_data_width_p)
) out_fifo
(.clk_i (clk_i)
,.reset_i(reset_i)
,.data_i (out_fifo_data_li)
,.v_i (out_fifo_v_li)
,.ready_o(out_fifo_ready_lo)
,.data_o (stream_data_o)
,.v_o (stream_v_o)
,.yumi_i (stream_yumi_i)
);
// cmd_queue fifo
logic queue_fifo_v_li, queue_fifo_ready_lo;
assign io_resp.payload = io_data_cmd.payload;
assign io_resp.addr = io_data_cmd.addr;
assign io_resp.msg_type = io_data_cmd.msg_type;
assign io_resp.nc_size = io_data_cmd.nc_size;
assign io_resp.non_cacheable = io_data_cmd.non_cacheable;
bsg_fifo_1r1w_small
#(.width_p(mem_cce_resp_width_lp)
,.els_p (16)
) queue_fifo
(.clk_i (clk_i)
,.reset_i(reset_i)
,.data_i (io_resp)
,.v_i (queue_fifo_v_li)
,.ready_o(queue_fifo_ready_lo)
,.data_o (io_resp_o)
,.v_o (io_resp_v_o)
,.yumi_i (io_resp_v_o & io_resp_ready_i)
);
logic [1:0] state_r, state_n;
always_ff @(posedge clk_i)
if (reset_i)
begin
state_r <= '0;
end
else
begin
state_r <= state_n;
end
logic io_data_cmd_yumi_lo;
assign io_data_cmd_yumi_o = io_data_cmd_yumi_lo;
always_comb
begin
state_n = state_r;
io_data_cmd_yumi_lo = 1'b0;
queue_fifo_v_li = 1'b0;
out_fifo_v_li = 1'b0;
out_fifo_data_li = io_data_cmd.data;
if (state_r == 0)
begin
if (io_data_cmd_v_i & out_fifo_ready_lo & queue_fifo_ready_lo)
begin
out_fifo_v_li = 1'b1;
out_fifo_data_li = io_data_cmd.addr;
state_n = 1;
end
end
else if (state_r == 1)
begin
if (io_data_cmd_v_i & out_fifo_ready_lo & queue_fifo_ready_lo)
begin
out_fifo_v_li = 1'b1;
io_data_cmd_yumi_lo = 1'b1;
queue_fifo_v_li = 1'b1;
state_n = 0;
end
end
end
// resp fifo
assign stream_ready_o = 1'b1;
endmodule
| 6.667796 |
module bp_stream_to_lite
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_default_cfg
`declare_bp_proc_params(bp_params_p)
, parameter in_data_width_p = "inv"
, parameter out_data_width_p = "inv"
// Bitmask which etermines which message types have a data payload
// Constructed as (1 << e_payload_msg1 | 1 << e_payload_msg2)
, parameter payload_mask_p = 0
`declare_bp_bedrock_mem_if_widths(paddr_width_p, in_data_width_p, lce_id_width_p, lce_assoc_p, in)
`declare_bp_bedrock_mem_if_widths(paddr_width_p, out_data_width_p, lce_id_width_p, lce_assoc_p, out)
)
(input clk_i
, input reset_i
// Master BP Stream
// ready-valid-and
, input [in_mem_msg_header_width_lp-1:0] mem_header_i
, input [in_data_width_p-1:0] mem_data_i
, input mem_v_i
, output logic mem_ready_o
, input mem_lock_i
// Client BP Lite
// ready-valid-and
, output logic [out_mem_msg_width_lp-1:0] mem_o
, output logic mem_v_o
, input mem_ready_i
);
`declare_bp_bedrock_mem_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, in);
`declare_bp_bedrock_mem_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, out);
localparam in_data_bytes_lp = in_data_width_p/8;
localparam out_data_bytes_lp = out_data_width_p/8;
localparam stream_words_lp = out_data_width_p/in_data_width_p;
localparam stream_offset_width_lp = `BSG_SAFE_CLOG2(out_data_bytes_lp);
bp_bedrock_in_mem_msg_header_s header_lo;
bsg_one_fifo
#(.width_p($bits(bp_bedrock_in_mem_msg_header_s)))
header_fifo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(mem_header_i)
// We ready on ready/and failing on the stream after the first
,.v_i(mem_v_i)
,.data_o(header_lo)
,.yumi_i(mem_ready_i & mem_v_o)
// We use the sipo ready/valid
,.ready_o(/* Unused */)
,.v_o(/* Unused */)
);
bp_bedrock_in_mem_msg_header_s mem_header_cast_i;
assign mem_header_cast_i = mem_header_i;
wire has_data = payload_mask_p[mem_header_cast_i.msg_type];
localparam data_len_width_lp = `BSG_SAFE_CLOG2(stream_words_lp);
wire [data_len_width_lp-1:0] num_stream_cmds = has_data
? `BSG_MAX(((1'b1 << mem_header_cast_i.size) / in_data_bytes_lp), 1'b1)
: 1'b1;
logic [out_data_width_p-1:0] data_lo;
logic data_ready_lo, len_ready_lo;
bsg_serial_in_parallel_out_dynamic
#(.width_p(in_data_width_p), .max_els_p(stream_words_lp))
sipo
(.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(mem_data_i)
,.len_i(num_stream_cmds-1'b1)
,.ready_o(mem_ready_o)
,.v_i(mem_v_i)
,.data_o(data_lo)
,.v_o(mem_v_o)
,.yumi_i(mem_ready_i & mem_v_o)
// We rely on fifo ready signal
,.len_ready_o(/* Unused */)
);
wire unused = &{mem_lock_i};
bp_bedrock_out_mem_msg_s mem_cast_o;
assign mem_cast_o = '{header: header_lo, data: data_lo};
assign mem_o = mem_cast_o;
//synopsys translate_off
initial
begin
assert (in_data_width_p < out_data_width_p)
else $error("Master data cannot be larger than client");
assert (out_data_width_p % in_data_width_p == 0)
else $error("Client data must be a multiple of master data");
end
always_ff @(negedge clk_i)
begin
// if (mem_v_i)
// $display("[%t] Stream received: %p %x", $time, mem_header_cast_i, mem_data_i);
// if (mem_ready_i & mem_v_o)
// $display("[%t] Msg sent: %p", $time, mem_cast_o);
end
//synopsys translate_on
endmodule
| 8.237923 |
module BP_TimerSetting (
//====================================================
//======= Input ======
//====================================================
input clk, // 25 MHz clock
input rst, // Asynchronous reset
input debounced_U, // Debounced Up Button
input debounced_D, // Debounced Down Button
input debounced_R, // Debounced Right Button
input debounced_L, // Debounced Left Button
//====================================================
//======= Output ======
//====================================================
//-----------7 segment display-----
output [3:0] cur_sec,
output led
);
//===================================================
//======= TODO =====
wire A, B, C, D;
wire a, b, c, d;
wire [3:0] w0;
wire [3:0] w1;
wire judge;
wire w2;
wire ww;
wire [7:0] wi;
//䪺dff
DFF(
A, wi[0], clk, rst
); DFF(
B, wi[1], clk, rst
); DFF(
C, wi[2], clk, rst
); DFF(
D, wi[3], clk, rst
);
//k䪺dff
DFF(
a, wi[4], clk, rst
); DFF(
b, wi[5], clk, rst
); DFF(
c, wi[6], clk, rst
); DFF(
d, wi[7], clk, rst
);
//a,b,c,d,A,B,C,DWMUX
MUX21(
judge, A, a, cur_sec[0]
); MUX21(
judge, B, b, cur_sec[1]
); MUX21(
judge, C, c, cur_sec[2]
); MUX21(
judge, D, d, cur_sec[3]
);
//DFF input emux
wire [7:0] wm;
MUX21(
judge, w0[0], A, wi[0]
); MUX21(
judge, w0[1], B, wi[1]
); MUX21(
judge, w0[2], C, wi[2]
); MUX21(
judge, w0[3], D, wi[3]
); MUX21(
judge, a, w1[0], wi[4]
); MUX21(
judge, b, w1[1], wi[5]
); MUX21(
judge, c, w1[2], wi[6]
); MUX21(
judge, d, w1[3], wi[7]
);
assign led = judge;
//debounced_U , debounced_DP_ (2MUX)
//RIGHT
MUX21(
debounced_U, D | ~A, wm[0], w0[0]
); MUX21(
debounced_D, ~A & (B | C | D), A, wm[0]
); MUX21(
debounced_U, (~A & B) | (A & ~B & ~D), wm[1], w0[1]
); MUX21(
debounced_D, (A & B) | (~A & D) | (~A & ~B & C), B, wm[1]
); MUX21(
debounced_U, (~B & C) | (~A & C) | (A & B & ~C), wm[2], w0[2]
); MUX21(
debounced_D, (A & C) | (B & C) | (~A & D), C, wm[2]
); MUX21(
debounced_U, (D) | (A & B & C), wm[3], w0[3]
); MUX21(
debounced_D, D & A, D, wm[3]
);
//LEFT
MUX21(
debounced_U, d | ~a, wm[4], w1[0]
); MUX21(
debounced_D, ~a & (b | c | d), a, wm[4]
); MUX21(
debounced_U, (~a & b) | (a & ~b & ~d), wm[5], w1[1]
); MUX21(
debounced_D, (a & b) | (~a & d) | (~a & ~b & c), b, wm[5]
); MUX21(
debounced_U, (~b & c) | (~a & c) | (a & b & ~c), wm[6], w1[2]
); MUX21(
debounced_D, (a & c) | (b & c) | (~a & d), c, wm[6]
); MUX21(
debounced_U, (d) | (a & b & c), wm[7], w1[3]
); MUX21(
debounced_D, d & a, d, wm[7]
);
//P_
MUX21(
debounced_R, 1'b1, judge, ww
); MUX21(
debounced_L, 1'b0, ww, w2
); DFF(
judge, w2, clk, rst
);
//===================================================
endmodule
| 7.40272 |
module.h"
/********** Internal Define **********/
// Direction Prediction
`define PhtDataBus 1:0
`define PhtDepthBus 255:0
`define PhtAddrBus 7:0
`define BhrDataBus 7:0
`define BHR_DATA_W 8
`define OldBhtLoc 6:0
`define BankOffsetBus 1:0
`define BankOffsetLoc 3:2
// Address Prediction
`define BtbTypeBus 1:0
`define BtbIndexBus 7:0
`define BtbTagBus 9:0
`define PcIndexLoc 9:2
`define PcTagLoc 19:10
`define BtbDataBus 43:0
`define BtbTagLoc 43:34
//`define BtbValidLoc 44
`define BtbTypeLoc 33:32
`define BtbAddrLoc 31:0
`define BtbDepthBus 255:0
`define TYPE_RELATIVE 2'b01
`define TYPE_CALL 2'b10
`define TYPE_RETURN 2'b11
`define TYPE_NOP 2'b00
`define BtbChoiceBus 1:0
`define CHOOSE_WAY_0 2'b00
`define CHOOSE_WAY_1 2'b01
`define CHOOSE_WAY_2 2'b10
`define CHOOSE_WAY_3 2'b11
// RAS
`define RasDepthBus 7:0
`define RasDataBus 31:0
`define RasAddrBus 2:0
module branch_prediction(
/******* global signal *******/
input wire clk,
input wire rst_,
/******* IF signal *******/
input wire [`WordAddrBus] if_bp_pc,
output wire bp_if_en,
output wire [`WordAddrBus] bp_if_target,
output wire bp_if_delot_en,
output wire [`WordAddrBus] bp_if_delot_pc,
/******* I-cache signal *******/
input wire icache_bp_stall,
output wire [`Ptab2addrBus] bp_icache_ptab_addr,
output wire [`WordAddrBus] bp_icache_branch_pc,
/******* IB signal *******/
input wire [`PtabAddrBus] ib_ptab_addr,
/******* ID signal *******/
input wire id_update_en,
input wire [`WordAddrBus] id_update_pc,
input wire [`BtbTypeBus] id_update_branch_type,
input wire [`WordAddrBus] id_update_target,
input wire [`PtabAddrBus] id_ptab_addr,
/******* IS signal *******/
input wire [`PtabAddrBus] is_ptab_addr,
/******* EX signal *******/
input wire [`Ptab2addrBus] ex_ptab_addr,
output wire [`Ptab2dataBus] ex_ptab_data,
input wire ex_bp_error,
input wire ex_bp_bhr,
input wire ex_update_en,
input wire [`WordAddrBus] ex_update_pc,
input wire ex_real_dir,
/****** Handshake ******/
output wire bp_allin //to IF, together with i$_allin
);
/****** Internal Signal ******/
wire [`WordAddrBus] dir_pc;
wire [3:0] bp_dir;
wire bp_dir_en;
wire [`WordAddrBus] addr_pc;
wire [`WordAddrBus] branch_pc;
wire bp_ptab_full;
wire bp_dir_stall;
wire bp_addr_stall;
/****** Combinational Logic ******/
//pc_in
assign dir_pc = if_bp_pc;
assign addr_pc = (bp_dir==4'b0001)? dir_pc :
(bp_dir==4'b0010)? dir_pc + 4:
(bp_dir==4'b0100)? dir_pc + 8: dir_pc + 12;
//pc_out
assign bp_icache_branch_pc = branch_pc;
//stall
assign bp_dir_stall = icache_bp_stall| bp_ptab_full;
assign bp_addr_stall = icache_bp_stall| bp_ptab_full;
//handshake
assign bp_dir_en = (|bp_dir);
assign bp_allin = (!bp_ptab_full) && ( bp_if_en || (!bp_dir_en));
//global history direction predictor
dir_predictor bp_direction(
.clk(clk),
.rst_(rst_),
.stall(bp_dir_stall),
.bp_pc(dir_pc),
.bp_dir(bp_dir),
.bp_error(ex_bp_error),
.backup_ghr(ex_bp_bhr),
.real_dir(ex_real_dir),
.update_en(ex_update_en),
.update_pc(ex_update_pc)
);
addr_predictor bp_addr(
.clk(clk),
.rst_(rst_),
.stall(bp_addr_stall),
.bp_pc(addr_pc),
.bp_dir(bp_dir),
.target_addr(bp_if_target),
.branch_pc(branch_pc),
.bp_en(bp_if_en),
.bp_delot_pc(bp_if_delot_pc),
.bp_delot_en(bp_if_delot_en),
.update_pc(id_update_pc),
.update_target(id_update_target),
.update_branch_type(id_update_branch_type),
.update_en(id_update_en),
.ex_bp_error(ex_bp_error)
);
PTAB ptab(
.clk(clk),
.rst_(rst_),
.bp_error(ex_bp_error),
.ex_ptab_addr(ex_ptab_addr),
.ex_ptab_data(ex_ptab_data),
.is_ptab_addr(is_ptab_addr),
.id_ptab_addr(id_ptab_addr),
.ib_ptab_addr(ib_ptab_addr),
.bp_en(|bp_dir),
.bp_target_addr(bp_if_target),
.bp_now_addr(branch_pc),
.bp_ptab_full(bp_ptab_full),
.bp_ptab_addr(bp_icache_ptab_addr)
);
endmodule
| 7.097988 |
module RAS_LIFO (
/**** Global Signal ****/
input wire clk,
input wire rst_,
/**** Ras flush ****/
input wire bp_error,
input wire [`WordAddrBus] error_pc,
/**** Addr_Predictor Signal ****/
input wire ras_write_en,
input wire [`WordAddrBus] call_pc,
input wire ras_read_en,
output wire [`WordAddrBus] ras_read_data,
input wire [`WordAddrBus] ras_write_data
);
/**** Internal Signal ****/
reg [ `RasDataBus] ras_data [`RasDepthBus];
reg [ `RasAddrBus] ras_pointer;
reg [`RepeatCounterBus] repeat_counter;
reg [ `WordAddrBus] last_pc;
integer reset_counter;
wire repeat_en;
wire repeat_taken;
wire ras_flush;
/****** Combinational Logic ******/
//Read Channel
assign ras_read_data = (ras_read_en & ras_write_en) ? ras_write_data:
(ras_read_en) ? ras_data[ras_pointer] : `WORD_DATA_W'b0;
assign repeat_taken = |repeat_counter;
//Write Channel
assign repeat_en = (call_pc == last_pc);
assign ras_flush = (bp_error && (ras_data[0] == error_pc + 'd8))?'b1:
(bp_error && (ras_data[1] == error_pc + 'd8) && ras_pointer > 1)?'b1:
(bp_error && (ras_data[2] == error_pc + 'd8) && ras_pointer > 2)?'b1:
(bp_error && (ras_data[3] == error_pc + 'd8) && ras_pointer > 3)?'b1:
(bp_error && (ras_data[4] == error_pc + 'd8) && ras_pointer > 4)?'b1:
(bp_error && (ras_data[5] == error_pc + 'd8) && ras_pointer > 5)?'b1:
(bp_error && (ras_data[6] == error_pc + 'd8) && ras_pointer > 6)?'b1:
(bp_error && (ras_data[7] == error_pc + 'd8))?'b1:'b0;
/****** Sequential Logic *******/
always @(posedge clk) begin
if (!rst_) begin
ras_pointer <= 3'b0;
repeat_counter <= 8'b0;
last_pc <= `WORD_ADDR_W'b0;
for (reset_counter = 0; reset_counter < 8; reset_counter = reset_counter + 1) begin
ras_data[reset_counter] <= 32'b0;
end
end else begin
case ({
ras_read_en, ras_write_en
})
2'b00: begin
//keep the data
end
2'b01: begin
ras_pointer <= (!repeat_en) ? (ras_pointer + 3'b1) : ras_pointer;
repeat_counter <= (!repeat_en) ? (repeat_counter + 8'b1) : repeat_counter;
ras_data[ras_pointer] <= (!repeat_en) ? ras_write_data : ras_data[ras_pointer];
last_pc <= call_pc;
end
2'b10: begin
ras_pointer <= (repeat_taken) ? ras_pointer : (ras_pointer - 3'b1);
repeat_counter <= (repeat_taken) ? (repeat_counter - 8'b1) : repeat_counter;
end
2'b11: begin
//keep the data
end
endcase
end
end
endmodule
| 8.121747 |
module.h"
/********** Internal Define **********/
// Direction Prediction
`define PhtDataBus 1:0
`define PhtDepthBus 255:0
`define PhtAddrBus 7:0
`define BhrDataBus 7:0
`define BHR_DATA_W 8
`define OldBhtLoc 6:0
`define BankOffsetBus 1:0
`define BankOffsetLoc 3:2
// Address Prediction
`define BtbTypeBus 1:0
`define BtbIndexBus 7:0
`define BtbTagBus 9:0
`define PcIndexLoc 9:2
`define PcTagLoc 19:10
`define BtbDataBus 43:0
`define BtbTagLoc 43:34
//`define BtbValidLoc 44
`define BtbTypeLoc 33:32
`define BtbAddrLoc 31:0
`define BtbDepthBus 255:0
`define TYPE_RELATIVE 2'b01
`define TYPE_CALL 2'b10
`define TYPE_RETURN 2'b11
`define TYPE_NOP 2'b00
`define BtbChoiceBus 1:0
`define CHOOSE_WAY_0 2'b00
`define CHOOSE_WAY_1 2'b01
`define CHOOSE_WAY_2 2'b10
`define CHOOSE_WAY_3 2'b11
// RAS
`define RasDepthBus 7:0
`define RasDataBus 31:0
`define RasAddrBus 2:0
module branch_prediction(
/******* global signal *******/
input wire clk,
input wire rst_,
input wire flush,
/******* IF signal *******/
input wire [`WordAddrBus] if_bp_pc,
output wire bp_if_en,
output wire [`WordAddrBus] bp_if_target,
output wire bp_if_delot_en,
output wire [`WordAddrBus] bp_if_delot_pc,
/******* I-cache signal *******/
input wire icache_bp_stall,
output wire [`Ptab2addrBus] bp_icache_ptab_addr,
output wire [`WordAddrBus] bp_icache_branch_pc,
/******* IB signal *******/
input wire [`PtabAddrBus] ib_ptab_addr,
/******* ID signal *******/
input wire id_update_en,
input wire [`WordAddrBus] id_update_pc,
input wire [`BtbTypeBus] id_update_branch_type,
input wire [`WordAddrBus] id_update_target,
input wire [`PtabAddrBus] id_ptab_addr,
/******* IS signal *******/
input wire [`PtabAddrBus] is_ptab_addr,
/******* EX signal *******/
input wire [`Ptab2addrBus] ex_ptab_addr,
output wire [`Ptab2dataBus] ex_ptab_data,
input wire ex_bp_error,
input wire ex_bp_bhr,
input wire ex_update_en,
input wire [`WordAddrBus] ex_update_pc,
input wire ex_real_dir,
/****** Handshake ******/
output wire bp_allin //to IF, together with i$_allin
);
/****** Internal Signal ******/
wire [`WordAddrBus] dir_pc;
wire [3:0] bp_dir;
wire bp_dir_en;
wire [`WordAddrBus] addr_pc;
wire [`WordAddrBus] branch_pc;
wire bp_ptab_full;
wire bp_dir_stall;
wire bp_addr_stall;
/****** Combinational Logic ******/
//pc_in
assign dir_pc = if_bp_pc;
assign addr_pc = (bp_dir==4'b0001)? dir_pc :
(bp_dir==4'b0010)? dir_pc + 4:
(bp_dir==4'b0100)? dir_pc + 8: dir_pc + 12;
//pc_out
assign bp_icache_branch_pc = branch_pc;
//stall
assign bp_dir_stall = icache_bp_stall| bp_ptab_full;
assign bp_addr_stall = icache_bp_stall| bp_ptab_full;
//handshake
assign bp_dir_en = (|bp_dir);
assign bp_allin = (!bp_ptab_full) && ( bp_if_en || (!bp_dir_en));
//global history direction predictor
dir_predictor bp_direction(
.clk(clk),
.rst_(rst_),
.stall(bp_dir_stall),
.bp_pc(dir_pc),
.bp_dir(bp_dir),
.flush(flush),
.backup_ghr(ex_bp_bhr),
.real_dir(ex_real_dir),
.update_en(ex_update_en),
.update_pc(ex_update_pc)
);
addr_predictor bp_addr(
.clk(clk),
.rst_(rst_),
.stall(bp_addr_stall),
.bp_pc(addr_pc),
.bp_dir(bp_dir),
.target_addr(bp_if_target),
.branch_pc(branch_pc),
.bp_en(bp_if_en),
.bp_delot_pc(bp_if_delot_pc),
.bp_delot_en(bp_if_delot_en),
.update_pc(id_update_pc),
.update_target(id_update_target),
.update_branch_type(id_update_branch_type),
.update_en(id_update_en),
.flush(flush)
);
PTAB ptab(
.clk(clk),
.rst_(rst_),
.flush(flush),
.ex_ptab_addr(ex_ptab_addr),
.ex_ptab_data(ex_ptab_data),
.is_ptab_addr(is_ptab_addr),
.id_ptab_addr(id_ptab_addr),
.ib_ptab_addr(ib_ptab_addr),
.bp_en(|bp_dir),
.bp_target_addr(bp_if_target),
.bp_now_addr(branch_pc),
.bp_ptab_full(bp_ptab_full),
.bp_ptab_addr(bp_icache_ptab_addr)
);
endmodule
| 7.097988 |
module RAS_LIFO (
/**** Global Signal ****/
input wire clk,
input wire rst_,
/**** Addr_Predictor Signal ****/
input wire ras_write_en,
input wire ras_read_en,
output wire [`WordAddrBus] ras_read_data,
input wire [`WordAddrBus] ras_write_data
);
/**** Internal Signal ****/
reg [`RasDataBus] ras_data [`RasDepthBus];
reg [`RasAddrBus] ras_front;
reg [`RasAddrBus] ras_rear;
integer reset_counter;
/****** Combinational Logic ******/
//Read Channel
assign ras_read_data = (ras_read_en & ras_write_en) ? ras_write_data:
(ras_read_en) ? ((ras_front==ras_rear && ras_rear == 3'b000)?`WORD_DATA_W'b0:
((ras_front != ras_rear && ras_front==3'b000)?ras_data[3'b111]:ras_data[ras_front-1])): `WORD_DATA_W'b0;
//Write Channel
/****** Sequential Logic *******/
always @(posedge clk) begin
if (!rst_) begin
ras_front <= 3'b0;
ras_rear <= 3'b0;
for (reset_counter = 0; reset_counter < 8; reset_counter = reset_counter + 1) begin
ras_data[reset_counter] <= 32'b0;
end
end else begin
case ({
ras_read_en, ras_write_en
})
2'b00: begin
//keep the data
end
2'b01: begin
ras_front <= (ras_front == ras_rear && ras_front == 3'b111) ? 3'b000 : ras_front + 1;
ras_rear <= (ras_rear == ras_front + 1 && ras_rear == 3'b111) ? 3'b000:
(ras_rear == ras_front + 1 || (ras_rear == 3'b000 && ras_front == 3'b111)) ? ras_rear + 1 : ras_rear;
ras_data[ras_front] <= ras_write_data;
end
2'b10: begin
ras_front <= (ras_front == ras_rear)?3'b000:
(ras_front == 3'b000)?3'b111:ras_front-1;
ras_rear <= (ras_front == ras_rear) ? 3'b000 : ras_rear;
end
2'b11: begin
//keep the data
end
endcase
end
end
endmodule
| 8.121747 |
module.h"
/********** Internal Define **********/
// Direction Prediction
`define PhtDataBus 1:0
`define PhtDepthBus 255:0
`define PhtAddrBus 7:0
`define BhrDataBus 7:0
`define BHR_DATA_W 8
`define OldBhtLoc 6:0
`define BankOffsetBus 1:0
`define BankOffsetLoc 3:2
// Address Prediction
`define BtbTypeBus 1:0
`define BtbIndexBus 7:0
`define BtbTagBus 9:0
`define PcIndexLoc 9:2
`define PcTagLoc 19:10
`define BtbDataBus 43:0
`define BtbTagLoc 43:34
//`define BtbValidLoc 44
`define BtbTypeLoc 33:32
`define BtbAddrLoc 31:0
`define BtbDepthBus 255:0
`define TYPE_RELATIVE 2'b01
`define TYPE_CALL 2'b10
`define TYPE_RETURN 2'b11
`define TYPE_NOP 2'b00
`define BtbChoiceBus 1:0
`define CHOOSE_WAY_0 2'b00
`define CHOOSE_WAY_1 2'b01
`define CHOOSE_WAY_2 2'b10
`define CHOOSE_WAY_3 2'b11
// RAS
`define RasDepthBus 7:0
`define RasDataBus 31:0
`define RasAddrBus 2:0
module branch_prediction(
/******* global signal *******/
input wire clk,
input wire rst_,
input wire flush,
/******* IF signal *******/
input wire [`WordAddrBus] if_bp_pc,
output wire bp_if_en,
output wire [`WordAddrBus] bp_if_target,
output wire bp_if_delot_en,
output wire [`WordAddrBus] bp_if_delot_pc,
/******* I-cache signal *******/
output wire [`Ptab2addrBus] bp_icache_ptab_addr,
output wire [`WordAddrBus] bp_icache_branch_pc,
/******* IB signal *******/
input wire [`PtabAddrBus] ib_ptab_addr,
/******* ID signal *******/
input wire id_update_en,
input wire [`WordAddrBus] id_update_pc,
input wire [`BtbTypeBus] id_update_branch_type,
input wire [`WordAddrBus] id_update_target,
input wire [`PtabAddrBus] id_ptab_addr,
/******* IS signal *******/
input wire [`PtabAddrBus] is_ptab_addr,
/******* EX signal *******/
input wire [`Ptab2addrBus] ex_ptab_addr,
output wire [`Ptab2dataBus] ex_ptab_data,
input wire ex_bp_error,
input wire ex_bp_bhr,
input wire ex_update_en,
input wire [`WordAddrBus] ex_update_pc,
input wire ex_real_dir,
/****** Handshake ******/
input wire if_valid_ns,
output wire bp_allin //to IF, together with i$_allin
);
/****** Internal Signal ******/
wire [`WordAddrBus] dir_pc;
wire [3:0] bp_dir;
wire bp_dir_en;
wire [`WordAddrBus] addr_pc;
wire [`WordAddrBus] branch_pc;
wire bp_ptab_full;
wire bp_dir_stall;
wire bp_addr_stall;
/****** Combinational Logic ******/
//pc_in
assign dir_pc = if_bp_pc;
assign addr_pc = (bp_dir==4'b0001)? dir_pc :
(bp_dir==4'b0010)? dir_pc + 4:
(bp_dir==4'b0100)? dir_pc + 8: dir_pc + 12;
//pc_out
//assign bp_icache_branch_pc = branch_pc;
assign bp_icache_branch_pc = addr_pc;
//stall
assign bp_dir_stall = (!if_valid_ns)| bp_ptab_full;
assign bp_addr_stall = (!if_valid_ns)| bp_ptab_full;
//handshake
assign bp_dir_en = (|bp_dir);
assign bp_allin = (!bp_ptab_full) && ( bp_if_en || (!bp_dir_en));
//global history direction predictor
dir_predictor bp_direction(
.clk(clk),
.rst_(rst_),
.stall(bp_dir_stall),
.bp_pc(dir_pc),
.bp_dir(bp_dir),
.flush(flush),
.backup_ghr(ex_bp_bhr),
.real_dir(ex_real_dir),
.update_en(ex_update_en),
.update_pc(ex_update_pc)
);
addr_predictor bp_addr(
.clk(clk),
.rst_(rst_),
.stall(bp_addr_stall),
.bp_pc(addr_pc),
.bp_dir(bp_dir),
.target_addr(bp_if_target),
.branch_pc(branch_pc),
.bp_en(bp_if_en),
.bp_delot_pc(bp_if_delot_pc),
.bp_delot_en(bp_if_delot_en),
.update_pc(id_update_pc),
.update_target(id_update_target),
.update_branch_type(id_update_branch_type),
.update_en(id_update_en),
.flush(flush)
);
PTAB ptab(
.clk(clk),
.rst_(rst_),
.flush(flush),
.ex_ptab_addr(ex_ptab_addr),
.ex_ptab_data(ex_ptab_data),
.is_ptab_addr(is_ptab_addr),
.id_ptab_addr(id_ptab_addr),
.ib_ptab_addr(ib_ptab_addr),
.bp_dir_en(bp_dir_en),
.bp_addr_en(bp_if_en),
.bp_target_addr(bp_if_target),
.bp_now_addr(branch_pc),
.bp_ptab_full(bp_ptab_full),
.bp_ptab_addr(bp_icache_ptab_addr)
);
endmodule
| 7.097988 |
module RAS_LIFO (
/**** Global Signal ****/
input wire clk,
input wire rst_,
/**** Addr_Predictor Signal ****/
input wire ras_write_en,
input wire ras_read_en,
output wire [`WordAddrBus] ras_read_data,
input wire [`WordAddrBus] ras_write_data
);
/**** Internal Signal ****/
reg [`RasDataBus] ras_data [`RasDepthBus];
reg [`RasAddrBus] ras_front;
reg [`RasAddrBus] ras_rear;
integer reset_counter;
/****** Combinational Logic ******/
//Read Channel
assign ras_read_data = (ras_read_en & ras_write_en) ? ras_write_data:
(ras_read_en) ? ((ras_front==ras_rear && ras_rear == 3'b000)?`WORD_DATA_W'b0:
((ras_front != ras_rear && ras_front==3'b000)?ras_data[3'b111]:ras_data[ras_front-1])): `WORD_DATA_W'b0;
//Write Channel
/****** Sequential Logic *******/
always @(posedge clk) begin
if (!rst_) begin
ras_front <= 3'b0;
ras_rear <= 3'b0;
for (reset_counter = 0; reset_counter < 8; reset_counter = reset_counter + 1) begin
ras_data[reset_counter] <= 32'b0;
end
end else begin
case ({
ras_read_en, ras_write_en
})
2'b00: begin
//keep the data
end
2'b01: begin
ras_front <= (ras_front == ras_rear && ras_front == 3'b111) ? 3'b000 : ras_front + 1;
ras_rear <= (ras_rear == ras_front + 1 && ras_rear == 3'b111) ? 3'b000:
(ras_rear == ras_front + 1 || (ras_rear == 3'b000 && ras_front == 3'b111)) ? ras_rear + 1 : ras_rear;
ras_data[ras_front] <= ras_write_data;
end
2'b10: begin
ras_front <= (ras_front == ras_rear)?3'b000:
(ras_front == 3'b000)?3'b111:ras_front-1;
ras_rear <= (ras_front == ras_rear) ? 3'b000 : ras_rear;
end
2'b11: begin
//keep the data
end
endcase
end
end
endmodule
| 8.121747 |
module br (
input [31:0] a,
input [31:0] b,
input [2:0] comp_ctrl,
input do_branch,
input do_jump,
output branch,
output jump
);
wire signed [31:0] signed_a;
wire signed [31:0] signed_b;
wire [31:0] unsigned_a;
wire [31:0] unsigned_b;
reg taken;
assign signed_a = a;
assign signed_b = b;
assign unsigned_a = a;
assign unsigned_b = b;
always @(*) begin
case (comp_ctrl)
3'h0: taken = (signed_a == signed_b);
3'h1: taken = ~(signed_a == signed_b);
3'h2: taken = 1'b0;
3'h3: taken = 1'b0;
3'h4: taken = (signed_a < signed_b);
3'h5: taken = (signed_a >= signed_b);
3'h6: taken = (unsigned_a < unsigned_b);
3'h7: taken = (unsigned_a >= unsigned_b);
default: taken = 0;
endcase
end
assign branch = taken && do_branch;
assign jump = do_jump;
endmodule
| 7.511983 |
module BR128
(
input wire RESET,
input wire [127:0] C,
output wire OUT
`ifdef USE_POWER_PINS
,
inout VSS,
inout VDD
`endif
);
supply1 VDD;
supply0 VSS;
// empty module
// see lib file
reg int1;
reg int2;
initial begin
int1 <= 0;
int2 <= 0;
end
always @ (posedge RESET) begin
int1 <= ~int1;
end
always @ (posedge int1) begin
int2 <= ~int2;
end
assign OUT = int2;
endmodule
| 6.675913 |
module BR32
(
input wire RESET,
input wire [31:0] C,
output wire OUT
`ifdef USE_POWER_PINS
,
inout VSS,
inout VDD
`endif
);
supply1 VDD;
supply0 VSS;
// empty module
// see lib file
assign OUT = RESET;
endmodule
| 6.967415 |
module BR64
(
input wire RESET,
input wire [63:0] C,
output wire OUT
`ifdef USE_POWER_PINS
,
inout VSS,
inout VDD
`endif
);
supply1 VDD;
supply0 VSS;
// empty module
// see lib file
reg int1;
initial begin
int1 <= 0;
end
always @ (posedge RESET) begin
int1 <= ~int1;
end
assign OUT = int1;
endmodule
| 6.757569 |
module BrainfuckWrapper (
CLK,
RESET,
CIN,
COUT,
CRDA,
CACK,
CWR,
CRDY
);
parameter FAST_LOOPEND = 1;
parameter IA_WIDTH = 11;
parameter DA_WIDTH = 11;
parameter DD_WIDTH = 8;
parameter STACK_DEPTH_POW = 7;
input CLK;
input RESET;
input [7:0] CIN;
output [7:0] COUT;
input CRDA;
output CACK;
output CWR;
input CRDY;
wire [IA_WIDTH - 1:0] IA;
wire [7:0] IDIN;
wire IEN;
// Data bus
wire [DA_WIDTH - 1:0] DA;
wire [DD_WIDTH - 1:0] DDIN;
wire [DD_WIDTH - 1:0] DDOUT;
wire DEN;
wire DWE;
BrainfuckCPU #(
.FAST_LOOPEND(FAST_LOOPEND),
.IA_WIDTH(IA_WIDTH),
.DA_WIDTH(DA_WIDTH),
.DD_WIDTH(DD_WIDTH),
.STACK_DEPTH_POW(STACK_DEPTH_POW)
) cpu (
.CLK(CLK),
.RESET(RESET),
.IA(IA),
.IDIN(IDIN),
.IEN(IEN),
.DA(DA),
.DDIN(DDIN),
.DDOUT(DDOUT),
.DEN(DEN),
.DWE(DWE),
.CIN(CIN),
.COUT(COUT),
.CRDA(CRDA),
.CACK(CACK),
.CWR(CWR),
.CRDY(CRDY)
);
IRAM #(
.IA_WIDTH(IA_WIDTH)
) iram (
.CLK(CLK),
.A(IA),
.DOUT(IDIN),
.EN(IEN)
);
DRAM #(
.DA_WIDTH(DA_WIDTH),
.DD_WIDTH(DD_WIDTH)
) dram (
.CLK(CLK),
.A(DA),
.DIN(DDOUT),
.DOUT(DDIN),
.EN(DEN),
.WE(DWE)
);
endmodule
| 7.028321 |
module msfp_generator (
input [`BFLOAT_EXP-1:0] exponent,
input [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa,
input clk,
input reset,
input start,
output reg out_data_available,
output reg [`BFLOAT_DWIDTH-1:0] msfp11
);
wire sign, is_valid;
wire [2:0] position;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa_sign_adjusted;
assign sign = mantisa[`LDPE_USED_OUTPUT_WIDTH-1];
assign mantisa_sign_adjusted = (sign) ? (-mantisa) : mantisa;
wire out_data_available_lzd;
leading_zero_detector_6bit ldetector (
.reset(reset),
.start(start),
.clk(clk),
.a(mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0]),
.is_valid(is_valid),
.position(position),
.out_data_available(out_data_available_lzd)
);
wire [4:0] normalize_amt;
assign normalize_amt = (is_valid) ? position : 0;
wire [`BFLOAT_MANTISA_WITH_LO-1:0] significand_to_be_normalised;
assign significand_to_be_normalised = (is_valid) ? mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0] : 0;
wire out_data_available_barrel_shifter_left;
wire [`BFLOAT_MANTISA_WITH_LO-1:0] mantisa_shifted;
barrel_shifter_left bshift_left (
.clk(clk),
.reset(reset),
.start(out_data_available_lzd),
.out_data_available(out_data_available_barrel_shifter_left),
.shift_amt(normalize_amt),
.significand(significand_to_be_normalised),
.shifted_sig(mantisa_shifted)
);
wire [`BFLOAT_EXP-1:0] normalized_exponent;
assign normalized_exponent = {1'b0, exponent} - {1'b0, normalize_amt};
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
msfp11 <= 'bX;
out_data_available <= 0;
end else begin
out_data_available <= out_data_available_barrel_shifter_left;
msfp11 <= {sign, normalized_exponent, mantisa_shifted[`BFLOAT_MANTISA-1:0]};
end
end
endmodule
| 6.720074 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input mrf_we,
input [`MRF_AWIDTH-1:0] mrf_addr,
input out_data_available_external_comparator_tree,
output out_data_available_internal_comparator_tree,
output out_data_available_dot_prod,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] result,
output [`BFLOAT_EXP-1:0] max_exp
);
// Port A of BRAMs is used for feed DSPs and Port B is used to load matrix from off-chip memory
wire [`MRF_DWIDTH-1:0] mrf_outa_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outa_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outa_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
MRF mrf (
.clk (clk),
.addr(mrf_addr),
.in (mrf_in),
.we (mrf_we),
.out (mrf_outa_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.start(start),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.out_data_available_external_comparator_tree(out_data_available_external_comparator_tree),
.out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree),
.out_data_available_dot_prod(out_data_available_dot_prod),
.ldpe_result(ldpe_result),
.max_exp(max_exp)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input start,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
input out_data_available_external_comparator_tree,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result,
output out_data_available_internal_comparator_tree,
output out_data_available_dot_prod,
output [`BFLOAT_EXP-1:0] max_exp
);
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ax_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ay_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] bx_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] by_in_sub_ldpe;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] sub_ldpe_result;
wire [`DSPS_PER_LDPE-1:0] out_data_available_ax;
fp16_to_msfp11 fp_converter_ax_1 (
.rst(reset),
.start(start),
.a(ax[1*`FLOAT_DWIDTH-1:(1-1)*`FLOAT_DWIDTH]),
.b(ax_in_sub_ldpe[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ax[1-1]),
.clk(clk)
);
fp16_to_msfp11 fp_converter_ax_2 (
.rst(reset),
.start(start),
.a(ax[2*`FLOAT_DWIDTH-1:(2-1)*`FLOAT_DWIDTH]),
.b(ax_in_sub_ldpe[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ax[2-1]),
.clk(clk)
);
wire [`DSPS_PER_LDPE-1:0] out_data_available_ay;
fp16_to_msfp11 fp_converter_ay_1 (
.rst(reset),
.start(start),
.a(ay[1*`FLOAT_DWIDTH-1:(1-1)*`FLOAT_DWIDTH]),
.b(ay_in_sub_ldpe[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ay[1-1]),
.clk(clk)
);
fp16_to_msfp11 fp_converter_ay_2 (
.rst(reset),
.start(start),
.a(ay[2*`FLOAT_DWIDTH-1:(2-1)*`FLOAT_DWIDTH]),
.b(ay_in_sub_ldpe[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ay[2-1]),
.clk(clk)
);
wire [`DSPS_PER_LDPE-1:0] out_data_available_bx;
fp16_to_msfp11 fp_converter_bx_1 (
.rst(reset),
.start(start),
.a(bx[1*`FLOAT_DWIDTH-1:(1-1)*`FLOAT_DWIDTH]),
.b(bx_in_sub_ldpe[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_bx[1-1]),
.clk(clk)
);
fp16_to_msfp11 fp_converter_bx_2 (
.rst(reset),
.start(start),
.a(bx[2*`FLOAT_DWIDTH-1:(2-1)*`FLOAT_DWIDTH]),
.b(bx_in_sub_ldpe[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_bx[2-1]),
.clk(clk)
);
wire [`DSPS_PER_LDPE-1:0] out_data_available_by;
fp16_to_msfp11 fp_converter_by_1 (
.rst(reset),
.start(start),
.a(by[1*`FLOAT_DWIDTH-1:(1-1)*`FLOAT_DWIDTH]),
.b(by_in_sub_ldpe[1*`BFLOAT_DWIDTH-1:(1-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_by[1-1]),
.clk(clk)
);
fp16_to_msfp11 fp_converter_by_2 (
.rst(reset),
.start(start),
.a(by[2*`FLOAT_DWIDTH-1:(2-1)*`FLOAT_DWIDTH]),
.b(by_in_sub_ldpe[2*`BFLOAT_DWIDTH-1:(2-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_by[2-1]),
.clk(clk)
);
wire start_subldpe;
assign start_subldpe = out_data_available_ax[0];
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.start(start_subldpe),
.ax(ax_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.out_data_available_external_comparator_tree(out_data_available_external_comparator_tree),
.out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree),
.out_data_available_dot_prod(out_data_available_dot_prod),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH]),
.max_exp(max_exp)
);
assign ldpe_result = (start==1'b0) ? 'bX : sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
sum <= 0;
out_data_available <= 0;
end else begin
out_data_available <= 1;
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addr,
input [`MRF_DWIDTH-1:0] in,
input we,
output [`MRF_DWIDTH-1:0] out
);
sp_ram #(
.AWIDTH(`MAT_BRAM_AWIDTH),
.DWIDTH(`MAT_BRAM_DWIDTH)
) mat_mem_1 (
.clk (clk),
.addr(addr),
.in (in[1*`MAT_BRAM_DWIDTH-1:(1-1)*`MAT_BRAM_DWIDTH]),
.we (we),
.out (out[1*`MAT_BRAM_DWIDTH-1:(1-1)*`MAT_BRAM_DWIDTH])
);
sp_ram #(
.AWIDTH(`MAT_BRAM_AWIDTH),
.DWIDTH(`MAT_BRAM_DWIDTH)
) mat_mem_2 (
.clk (clk),
.addr(addr),
.in (in[2*`MAT_BRAM_DWIDTH-1:(2-1)*`MAT_BRAM_DWIDTH]),
.we (we),
.out (out[2*`MAT_BRAM_DWIDTH-1:(2-1)*`MAT_BRAM_DWIDTH])
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifdef SIMULATION
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifdef SIMULATION
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module exponent_comparator_tree_ldpe (
input [`BFLOAT_EXP-1:0] inp0,
input [`BFLOAT_EXP-1:0] inp1,
input [`BFLOAT_EXP-1:0] inp2,
input [`BFLOAT_EXP-1:0] inp3,
input [`BFLOAT_EXP-1:0] inp4,
input [`BFLOAT_EXP-1:0] inp5,
input [`BFLOAT_EXP-1:0] inp6,
input [`BFLOAT_EXP-1:0] inp7,
output [`BFLOAT_EXP-1:0] result_final_stage,
output out_data_available,
//CONTROL SIGNALS
input clk,
input reset,
input start
);
/*
reg[3:0] num_cycles_comparator;
always@(posedge clk) begin
if((reset==1'b1) || (start==1'b0)) begin
num_cycles_comparator<=0;
out_data_available<=0;
end
else begin
if(num_cycles_comparator==`NUM_COMPARATOR_TREE_CYCLES-1) begin
out_data_available<=1;
end
else begin
num_cycles_comparator <= num_cycles_comparator + 1;
end
end
end
*/
wire [(`BFLOAT_EXP)-1:0] comparator_output_0_stage_1;
wire out_data_available_0_stage_1;
comparator #(
.DWIDTH(`BFLOAT_EXP)
) comparator_units_initial_0 (
.a(inp0),
.b(inp1),
.clk(clk),
.reset(reset),
.start(start),
.out_data_available(out_data_available_0_stage_1),
.out(comparator_output_0_stage_1)
);
wire [(`BFLOAT_EXP)-1:0] comparator_output_1_stage_1;
wire out_data_available_1_stage_1;
comparator #(
.DWIDTH(`BFLOAT_EXP)
) comparator_units_initial_1 (
.a(inp2),
.b(inp3),
.clk(clk),
.reset(reset),
.start(start),
.out_data_available(out_data_available_1_stage_1),
.out(comparator_output_1_stage_1)
);
wire [(`BFLOAT_EXP)-1:0] comparator_output_0_stage_2;
wire out_data_available_0_stage_2;
comparator #(
.DWIDTH(`BFLOAT_EXP)
) comparator_units_0_stage_1 (
.a(comparator_output_0_stage_1),
.b(comparator_output_1_stage_1),
.clk(clk),
.reset(reset),
.start(out_data_available_0_stage_1),
.out_data_available(out_data_available_0_stage_2),
.out(comparator_output_0_stage_2)
);
assign result_final_stage = comparator_output_0_stage_2;
assign out_data_available = out_data_available_0_stage_2;
endmodule
| 6.772452 |
module exponent_comparator_tree_tile (
input [`BFLOAT_EXP*`NUM_LDPES-1:0] inp0,
input [`BFLOAT_EXP*`NUM_LDPES-1:0] inp1,
output [`BFLOAT_EXP*`NUM_LDPES-1:0] result_final_stage,
output [`NUM_LDPES-1:0] out_data_available,
//CONTROL SIGNALS
input clk,
input [`NUM_LDPES-1:0] reset,
input [`NUM_LDPES-1:0] start
);
/*
reg[3:0] num_cycles_comparator;
always@(posedge clk) begin
if((reset[0]==1'b1) || (start[0]==1'b0)) begin
num_cycles_comparator<=0;
out_data_available<=0;
end
else begin
if(num_cycles_comparator==`NUM_COMPARATOR_TREE_CYCLES_FOR_TILE-1) begin
out_data_available<={`NUM_LDPES{1'b1}};
end
else begin
num_cycles_comparator <= num_cycles_comparator + 1;
end
end
end
*/
wire [(`BFLOAT_EXP)*`NUM_LDPES-1:0] comparator_output_0_stage_1;
wire [`NUM_LDPES-1:0] out_data_available_0_stage_1;
comparator #(
.DWIDTH(`BFLOAT_EXP)
) comparator_units_initial_0_1 (
.a(inp0[1*`BFLOAT_EXP-1:(1-1)*`BFLOAT_EXP]),
.b(inp1[1*`BFLOAT_EXP-1:(1-1)*`BFLOAT_EXP]),
.clk(clk),
.reset(reset[1-1]),
.start(start[1-1]),
.out_data_available(out_data_available_0_stage_1[1-1]),
.out(comparator_output_0_stage_1[1*(`BFLOAT_EXP)-1:(1-1)*(`BFLOAT_EXP)])
);
comparator #(
.DWIDTH(`BFLOAT_EXP)
) comparator_units_initial_0_2 (
.a(inp0[2*`BFLOAT_EXP-1:(2-1)*`BFLOAT_EXP]),
.b(inp1[2*`BFLOAT_EXP-1:(2-1)*`BFLOAT_EXP]),
.clk(clk),
.reset(reset[2-1]),
.start(start[2-1]),
.out_data_available(out_data_available_0_stage_1[2-1]),
.out(comparator_output_0_stage_1[2*(`BFLOAT_EXP)-1:(2-1)*(`BFLOAT_EXP)])
);
assign result_final_stage[1*`BFLOAT_EXP-1:0*`BFLOAT_EXP] = comparator_output_0_stage_1[1*(`BFLOAT_EXP)-1:0*(`BFLOAT_EXP)];
assign result_final_stage[2*`BFLOAT_EXP-1:1*`BFLOAT_EXP] = comparator_output_0_stage_1[2*(`BFLOAT_EXP)-1:1*(`BFLOAT_EXP)];
assign out_data_available = out_data_available_0_stage_1;
endmodule
| 6.772452 |
module comparator #(parameter DWIDTH = `BFLOAT_EXP) (
input[DWIDTH-1:0] a,
input[DWIDTH-1:0] b,
input reset,
input start,
input clk,
output reg[DWIDTH-1:0] out,
output reg out_data_available
);
always@(posedge clk) begin
if(reset==1'b1 || start==1'b0) begin
out <= a;
out_data_available <= 0;
end
else begin
out <= (a>b) ? a : b;
out_data_available <= 1;
end
end
endmodule
| 7.565129 |
module fp16_to_msfp11 (
input clk,
input [15:0] a,
input rst,
input start,
output reg [10:0] b,
output reg out_data_available
);
reg [10:0] b_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[10] = a[15]; //sign bit
b_temp[9:0] = 7'b0000000; //EXPONENT AND MANTISSA
end else begin
b_temp[4:0] = a[9:5]; //MANTISSA
b_temp[9:5] = a[14:10]; //EXPONENT NOTE- EXPONENT SIZE IS SAME IN BOTH
b_temp[10] = a[15]; //SIGN
end
end
always @(posedge clk) begin
if ((rst == 1'b1) || (start == 1'b0)) begin
b <= 'bX;
out_data_available <= 0;
end else begin
b <= b_temp;
out_data_available <= 1;
end
end
endmodule
| 8.274172 |
module msfp11_to_fp16 (
input reset,
input start,
input clk,
input [10:0] a,
output reg [15:0] b,
output reg out_data_available
);
reg [15:0] b_temp;
reg [ 3:0] j;
reg [ 2:0] k;
reg [ 2:0] k_temp;
always @(*) begin
if (a[9:0] == 7'b0) begin //signed zero
b_temp[15] = a[10]; //sign bit
b_temp[14:0] = 15'b0;
end else begin
/*
if ( a[9:5] == 5'b0 ) begin //denormalized (covert to normalized)
for (j=0; j<=4; j=j+1) begin
if (a[j] == 1'b1) begin
k_temp = j;
end
end
k = 1 - k_temp;
b_temp [9:0] = ( (a [4:0] << (k+1'b1)) & 5'b11111 ) << 5;
//b_temp [14:10] = 5'd31 - 5'd31 - k; //PROBLEM - DISCUSS THIS ************ SHOULD BE +k
b_temp [14:10] = 5'd31 - 5'd31 + k;
b_temp [15] = a[10];
end
*/
if (a[9:5] == 5'b11111) begin //Infinity/ NAN //removed else here
b_temp[9:0] = a[4:0] << 5;
b_temp[14:10] = 5'b11111;
b_temp[15] = a[10];
end else begin //Normalized Number
b_temp[9:0] = a[4:0] << 5;
b_temp[14:10] = 5'd31 - 5'd31 + a[6:2];
b_temp[15] = a[10];
end
end
end
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
out_data_available <= 0;
b <= 'bX;
end else begin
b <= b_temp;
out_data_available <= 1;
end
end
endmodule
| 6.54771 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`FLOAT_DWIDTH-1:0] A ; // Input A, a 32-bit floating point number
input [`FLOAT_DWIDTH-1:0] B ; // Input B, a 32-bit floating point number
input operation ;
// Output ports
output Sa ; // A's sign
output Sb ; // B's sign
output [2*`EXPONENT-1:0] ShiftDet ;
output [4:0] InputExc ; // Input numbers are exceptions
output [`FLOAT_DWIDTH-2:0] Aout ;
output [`FLOAT_DWIDTH-2:0] Bout ;
output Opout ;
// Internal signals // If signal is high...
wire ANaN ; // A is a NaN (Not-a-Number)
wire BNaN ; // B is a NaN
wire AInf ; // A is infinity
wire BInf ; // B is infinity
wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA
assign ANaN = &(A[`FLOAT_DWIDTH-2:`FLOAT_DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`FLOAT_DWIDTH-2:`FLOAT_DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`FLOAT_DWIDTH-2:`FLOAT_DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`FLOAT_DWIDTH-2:`FLOAT_DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ;
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`FLOAT_DWIDTH-2:`MANTISSA] + ~(B[`FLOAT_DWIDTH-2:`MANTISSA]) + 1) ;
assign DBA = (B[`FLOAT_DWIDTH-2:`MANTISSA] + ~(A[`FLOAT_DWIDTH-2:`MANTISSA]) + 1) ;
assign Sa = A[`FLOAT_DWIDTH-1] ; // A's sign bit
assign Sb = B[`FLOAT_DWIDTH-1] ; // B's sign bit
assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data
assign Opout = operation ;
assign Aout = A[`FLOAT_DWIDTH-2:0] ;
assign Bout = B[`FLOAT_DWIDTH-2:0] ;
endmodule
| 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`FLOAT_DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`FLOAT_DWIDTH-2:0] B ; // Input B, a 32-bit floating point number
input [2*`EXPONENT-1:0] ShiftDet ;
// Output ports
output [`EXPONENT-1:0] CExp ; // Common Exponent
output MaxAB ; // Incidates larger of A and B (0/A, 1/B)
output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin ; // Smaller mantissa
output [`MANTISSA-1:0] Mmax ; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`FLOAT_DWIDTH-2:0] < B[`FLOAT_DWIDTH-2:0]) ;
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ;
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ;
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ;
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ;
endmodule
| 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
wire bf16;
`ifdef BFLOAT16
assign bf16 = 1'b1;
`else
assign bf16 = 1'b0;
`endif
// Internal signals
reg [`MANTISSA:0] Lvl1;
reg [`MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
//integer i; // Loop variable
wire [`MANTISSA:0] temp_0;
assign temp_0 = 0;
always @(*) begin
if (bf16 == 1'b1) begin
//hardcoding for bfloat16
//For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7.
//Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits.
//Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
Lvl1 <= (|Shift[`EXPONENT-3:1]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
end else begin
//for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made.
Lvl1 <= Shift[2] ? {temp_0} : {1'b1, MminP};
end
end
assign Stage1 = {temp_0, Lvl1}; //2*MANTISSA + 2 width
always @(*) begin // Rotate {0 | 4 } bits
if (bf16 == 1'b1) begin
case (Shift[0])
// Rotate by 0
1'b0: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
1'b1: begin
Lvl2[0] <= Stage1[0+4];
Lvl2[1] <= Stage1[1+4];
Lvl2[2] <= Stage1[2+4];
Lvl2[3] <= Stage1[3+4];
Lvl2[4] <= Stage1[4+4];
Lvl2[5] <= Stage1[5+4];
Lvl2[6] <= Stage1[6+4];
Lvl2[7] <= Stage1[7+4];
Lvl2[8] <= Stage1[8+4];
Lvl2[9] <= Stage1[9+4];
Lvl2[10] <= Stage1[10+4];
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
endcase
end else begin
case (Shift[1:0]) // Rotate {0 | 4 | 8} bits
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
Lvl2[0] <= Stage1[0+4];
Lvl2[1] <= Stage1[1+4];
Lvl2[2] <= Stage1[2+4];
Lvl2[3] <= Stage1[3+4];
Lvl2[4] <= Stage1[4+4];
Lvl2[5] <= Stage1[5+4];
Lvl2[6] <= Stage1[6+4];
Lvl2[7] <= Stage1[7+4];
Lvl2[8] <= Stage1[8+4];
Lvl2[9] <= Stage1[9+4];
Lvl2[10] <= Stage1[10+4];
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
// Rotate by 8
2'b10: begin
Lvl2[0] <= Stage1[0+8];
Lvl2[1] <= Stage1[1+8];
Lvl2[2] <= Stage1[2+8];
Lvl2[3] <= Stage1[3+8];
Lvl2[4] <= Stage1[4+8];
Lvl2[5] <= Stage1[5+8];
Lvl2[6] <= Stage1[6+8];
Lvl2[7] <= Stage1[7+8];
Lvl2[8] <= Stage1[8+8];
Lvl2[9] <= Stage1[9+8];
Lvl2[10] <= Stage1[10+8];
Lvl2[`MANTISSA:`MANTISSA-7] <= 0;
end
// Rotate by 12
2'b11: begin
Lvl2[`MANTISSA:0] <= 0;
end
endcase
end
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [`MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
//integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
Lvl3[0] <= Stage2[0+1];
Lvl3[1] <= Stage2[1+1];
Lvl3[2] <= Stage2[2+1];
Lvl3[3] <= Stage2[3+1];
Lvl3[4] <= Stage2[4+1];
Lvl3[5] <= Stage2[5+1];
Lvl3[6] <= Stage2[6+1];
Lvl3[7] <= Stage2[7+1];
Lvl3[8] <= Stage2[8+1];
Lvl3[9] <= Stage2[9+1];
Lvl3[10] <= Stage2[10+1];
Lvl3[`MANTISSA] <= 0;
end
// Rotate by 2
2'b10: begin
Lvl3[0] <= Stage2[0+2];
Lvl3[1] <= Stage2[1+2];
Lvl3[2] <= Stage2[2+2];
Lvl3[3] <= Stage2[3+2];
Lvl3[4] <= Stage2[4+2];
Lvl3[5] <= Stage2[5+2];
Lvl3[6] <= Stage2[6+2];
Lvl3[7] <= Stage2[7+2];
Lvl3[8] <= Stage2[8+2];
Lvl3[9] <= Stage2[9+2];
Lvl3[10] <= Stage2[10+2];
Lvl3[`MANTISSA:`MANTISSA-1] <= 0;
end
// Rotate by 3
2'b11: begin
Lvl3[0] <= Stage2[0+3];
Lvl3[1] <= Stage2[1+3];
Lvl3[2] <= Stage2[2+3];
Lvl3[3] <= Stage2[3+3];
Lvl3[4] <= Stage2[4+3];
Lvl3[5] <= Stage2[5+3];
Lvl3[6] <= Stage2[6+3];
Lvl3[7] <= Stage2[7+3];
Lvl3[8] <= Stage2[8+3];
Lvl3[9] <= Stage2[9+3];
Lvl3[10] <= Stage2[10+3];
Lvl3[`MANTISSA:`MANTISSA-2] <= 0;
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`FLOAT_DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
wire [`EXPONENT-1:0] temp_1;
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
assign temp_1 = 0;
// Perform effective operation
//SAMIDH_UNSURE 5--> 8
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`FLOAT_DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`FLOAT_DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here)
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`FLOAT_DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`FLOAT_DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`FLOAT_DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`FLOAT_DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`FLOAT_DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
wire [ `EXPONENT:0] temp_2;
assign temp_2 = 0;
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`FLOAT_DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`FLOAT_DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`FLOAT_DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`FLOAT_DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`FLOAT_DWIDTH-2:`MANTISSA]) & |(a[`FLOAT_DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`FLOAT_DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`FLOAT_DWIDTH-2:`MANTISSA]) & ~|(a[`FLOAT_DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`FLOAT_DWIDTH-2:`MANTISSA]) & ~|(b[`FLOAT_DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`FLOAT_DWIDTH-1]; // A's sign
assign Sb = b[`FLOAT_DWIDTH-1]; // B's sign
assign Ea = a[`FLOAT_DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`FLOAT_DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
// EXPONENT = 5
// EXPONENT -1 = 4
// NEED to subtract 2^4 -1 = 15
wire [`EXPONENT-1 : 0] bias;
assign bias = ((1 << (`EXPONENT - 1)) - 1);
assign RoundE = NormE - bias;
assign RoundEP = NormE - bias - 1;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`FLOAT_DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
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