code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
wire [ `EXPONENT:0] temp_2;
assign temp_2 = 0;
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
// EXPONENT = 5
// EXPONENT -1 = 4
// NEED to subtract 2^4 -1 = 15
wire [`EXPONENT-1 : 0] bias;
assign bias = ((1 << (`EXPONENT - 1)) - 1);
assign RoundE = NormE - bias;
assign RoundEP = NormE - bias - 1;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module array_mux_2to1 #(
parameter size = 10
) (
clk,
reset,
start,
out,
in0,
in1,
sel,
out_data_available
);
input [size-1:0] in0, in1;
input sel, clk;
input reset, start;
output reg [size-1:0] out;
output reg out_data_available;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
out <= 'bX;
out_data_available <= 0;
end else begin
out <= (sel) ? in1 : in0;
out_data_available <= 1;
end
end
endmodule
| 7.273845 |
module barrel_shifter_right (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_arr_0;
array_mux_2to1 #(
.size(7)
) M0 (
.clk(clk),
.reset(reset),
.start(start),
.out(out0),
.in0({significand[5:0], 1'b0}),
.in1({1'b0, significand[5:0]}),
.sel(shift_amt[0]),
.out_data_available(out_data_available_arr_0)
);
//level 1
wire [8:0] out1;
wire out_data_available_arr_1;
array_mux_2to1 #(
.size(9)
) M1 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_0),
.out(out1),
.in0({out0[6:0], 2'b0}),
.in1({2'b0, out0[6:0]}),
.sel(shift_amt[1]),
.out_data_available(out_data_available_arr_1)
);
//level 2
wire [12:0] out2;
array_mux_2to1 #(
.size(13)
) M2 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_1),
.out(out2),
.in0({out1[8:0], 4'b0}),
.in1({4'b0, out1[8:0]}),
.sel(shift_amt[2]),
.out_data_available(out_data_available)
);
//shifted significand
assign shifted_sig = (reset == 1'b1) ? 'bX : out2[12:7];
endmodule
| 8.606549 |
module barrel_shifter_left (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_arr_0;
array_mux_2to1 #(
.size(7)
) M0 (
.clk(clk),
.reset(reset),
.start(start),
.out(out0),
.in0({1'b0, significand[5:0]}),
.in1({significand[5:0], 1'b0}),
.sel(shift_amt[0]),
.out_data_available(out_data_available_arr_0)
);
//level 1
wire [8:0] out1;
wire out_data_available_arr_1;
array_mux_2to1 #(
.size(9)
) M1 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_0),
.out(out1),
.in0({2'b0, out0[6:0]}),
.in1({out0[6:0], 2'b0}),
.sel(shift_amt[1]),
.out_data_available(out_data_available_arr_1)
);
//level 2
wire [12:0] out2;
array_mux_2to1 #(
.size(13)
) M2 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_1),
.out(out2),
.in0({4'b0, out1[8:0]}),
.in1({out1[8:0], 4'b0}),
.sel(shift_amt[2]),
.out_data_available(out_data_available)
);
//shifted significand
assign shifted_sig = (reset == 1'b1) ? 'bX : out2[5:0];
endmodule
| 8.606549 |
module leading_zero_detector_6bit (
input clk,
input [5:0] a,
input reset,
input start,
output reg [2:0] position,
output reg is_valid,
output reg out_data_available
);
wire [1:0] posi_upper, posi_lower;
wire valid_upper, valid_lower;
reg [3:0] num_cycles;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
num_cycles <= 0;
out_data_available <= 0;
end else begin
if (num_cycles == `NUM_LZD_CYCLES) begin
out_data_available <= 1;
end else begin
num_cycles <= num_cycles + 1;
end
end
end
leading_zero_detector_4bit lzd4_upper (
.clk(clk),
.reset(reset),
.start(start),
.a(a[5:2]),
.position(posi_upper),
.is_valid(valid_upper)
);
leading_zero_detector_4bit lzd4_lower (
.clk(clk),
.reset(reset),
.start(start),
.a({a[1:0], 2'b00}),
.position(posi_lower),
.is_valid(valid_lower)
);
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
is_valid <= 0;
position <= 'bX;
end else begin
is_valid <= valid_upper | valid_lower;
position[2] <= ~valid_upper;
position[1] <= valid_upper ? posi_upper[1] : posi_lower[1];
position[0] <= valid_upper ? posi_upper[0] : posi_lower[0];
end
end
endmodule
| 6.847206 |
module leading_zero_detector_4bit (
input clk,
input [3:0] a,
input reset,
input start,
output reg [1:0] position,
output reg is_valid
);
wire posi_upper, posi_lower;
wire valid_upper, valid_lower;
leading_zero_detector_2bit lzd2_upper (
.clk(clk),
.reset(reset),
.start(start),
.a(a[3:2]),
.position(posi_upper),
.is_valid(valid_upper)
);
leading_zero_detector_2bit lzd2_lower (
.clk(clk),
.reset(reset),
.start(start),
.a(a[1:0]),
.position(posi_lower),
.is_valid(valid_lower)
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= valid_upper | valid_lower;
position[1] <= ~valid_upper;
position[0] <= valid_upper ? posi_upper : posi_lower;
end
end
endmodule
| 6.847206 |
module leading_zero_detector_2bit (
input clk,
input [1:0] a,
input reset,
input start,
output reg position,
output reg is_valid
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= a[1] | a[0];
position <= ~a[1];
end
end
endmodule
| 6.847206 |
module msfp_generator (
input [`BFLOAT_EXP-1:0] exponent,
input [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa,
input clk,
input reset,
input start,
output reg out_data_available,
output reg [`BFLOAT_DWIDTH-1:0] msfp11
);
wire sign, is_valid;
wire [2:0] position;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] mantisa_sign_adjusted;
assign sign = mantisa[`LDPE_USED_OUTPUT_WIDTH-1];
assign mantisa_sign_adjusted = (sign) ? (-mantisa) : mantisa;
wire out_data_available_lzd;
leading_zero_detector_6bit ldetector (
.reset(reset),
.start(start),
.clk(clk),
.a(mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0]),
.is_valid(is_valid),
.position(position),
.out_data_available(out_data_available_lzd)
);
wire [4:0] normalize_amt;
assign normalize_amt = (is_valid) ? position : 0;
wire [`BFLOAT_MANTISA_WITH_LO-1:0] significand_to_be_normalised;
assign significand_to_be_normalised = (is_valid) ? mantisa_sign_adjusted[`BFLOAT_MANTISA_WITH_LO-1:0] : 0;
wire out_data_available_barrel_shifter_left;
wire [`BFLOAT_MANTISA_WITH_LO-1:0] mantisa_shifted;
barrel_shifter_left bshift_left (
.clk(clk),
.reset(reset),
.start(out_data_available_lzd),
.out_data_available(out_data_available_barrel_shifter_left),
.shift_amt(normalize_amt),
.significand(significand_to_be_normalised),
.shifted_sig(mantisa_shifted)
);
wire [`BFLOAT_EXP-1:0] normalized_exponent;
assign normalized_exponent = {1'b0, exponent} - {1'b0, normalize_amt};
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
msfp11 <= 'bX;
out_data_available <= 0;
end else begin
out_data_available <= out_data_available_barrel_shifter_left;
msfp11 <= {sign, normalized_exponent, mantisa_shifted[`BFLOAT_MANTISA-1:0]};
end
end
endmodule
| 6.720074 |
module compute_unit (
input clk,
input start,
input reset,
input [`VRF_DWIDTH-1:0] vec,
input [`MRF_DWIDTH-1:0] mrf_in,
input [`MRF_AWIDTH-1:0] mrf_addr_for_dram, //new
input mrf_we,
mrf_we_for_dram, //new
input [`MRF_AWIDTH-1:0] mrf_addr,
input out_data_available_external_comparator_tree,
output out_data_available_internal_comparator_tree,
output out_data_available_dot_prod,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] result,
output [`MRF_DWIDTH-1:0] mrf_outa_to_dram, //new
output [`BFLOAT_EXP-1:0] max_exp
);
// Port B of BRAMs is used for feed DSPs and Port A is used to interact with DRAM
wire [`MRF_DWIDTH-1:0] mrf_outb_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ax_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] ay_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] bx_wire;
wire [`LDPE_USED_INPUT_WIDTH-1:0] by_wire;
// Wire connecting LDPE output to Output BRAM input
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] inb_fake_wire;
// First 4 BRAM outputs are given to ax of 4 DSPs and next 4 BRAM outputs are given to bx of DSPs
// Connection MRF and LDPE wires for matrix data
// 'X' pin is used for matrix
/* If there are 4 DSPSs, bit[31:0] of mrf output contain ax values for the 4 DSPs, bit[63:32] contain bx values and so on. With a group of ax values, bit[7:0] contain ax value for DSP1, bit[15:8] contain ax value for DSP2 and so on. */
assign ax_wire = mrf_outb_wire[1*`LDPE_USED_INPUT_WIDTH-1:0*`LDPE_USED_INPUT_WIDTH];
assign bx_wire = mrf_outb_wire[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
// Connection of VRF and LDPE wires for vector data
// 'Y' pin is used for vector
assign ay_wire = vec[`LDPE_USED_INPUT_WIDTH-1:0];
assign by_wire = vec[2*`LDPE_USED_INPUT_WIDTH-1:1*`LDPE_USED_INPUT_WIDTH];
wire [`MRF_DWIDTH-1:0] mrf_in_fake;
MRF mrf (
.clk (clk),
.addra(mrf_addr_for_dram),
.addrb(mrf_addr),
.ina (mrf_in),
.inb (mrf_in_fake),
.wea (mrf_we_for_dram),
.web (mrf_we),
.outa (mrf_outa_to_dram),
.outb (mrf_outb_wire)
);
LDPE ldpe (
.clk(clk),
.reset(reset),
.start(start),
.ax(ax_wire),
.ay(ay_wire),
.bx(bx_wire),
.by(by_wire),
.out_data_available_external_comparator_tree(out_data_available_external_comparator_tree),
.out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree),
.out_data_available_dot_prod(out_data_available_dot_prod),
.ldpe_result(ldpe_result),
.max_exp(max_exp)
);
assign result = ldpe_result;
endmodule
| 7.063526 |
module LDPE (
input clk,
input reset,
input start,
input [`LDPE_USED_INPUT_WIDTH-1:0] ax,
input [`LDPE_USED_INPUT_WIDTH-1:0] ay,
input [`LDPE_USED_INPUT_WIDTH-1:0] bx,
input [`LDPE_USED_INPUT_WIDTH-1:0] by,
input out_data_available_external_comparator_tree,
output [`LDPE_USED_OUTPUT_WIDTH-1:0] ldpe_result,
output out_data_available_internal_comparator_tree,
output out_data_available_dot_prod,
output [`BFLOAT_EXP-1:0] max_exp
);
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ax_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] ay_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] bx_in_sub_ldpe;
wire [`BFLOAT_DWIDTH*`DSPS_PER_LDPE-1:0] by_in_sub_ldpe;
wire [`LDPE_USED_OUTPUT_WIDTH-1:0] sub_ldpe_result;
wire [`DSPS_PER_LDPE-1:0] out_data_available_ax;
genvar i;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_ax (
.rst(reset),
.start(start),
.a(ax[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(ax_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ax[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_ay;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_ay (
.rst(reset),
.start(start),
.a(ay[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(ay_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_ay[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_bx;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_bx (
.rst(reset),
.start(start),
.a(bx[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(bx_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_bx[i-1]),
.clk(clk)
);
end
endgenerate
wire [`DSPS_PER_LDPE-1:0] out_data_available_by;
generate
for (i = 1; i <= `DSPS_PER_LDPE; i = i + 1) begin
fp16_to_msfp11 fp_converter_by (
.rst(reset),
.start(start),
.a(by[i*`FLOAT_DWIDTH-1:(i-1)*`FLOAT_DWIDTH]),
.b(by_in_sub_ldpe[i*`BFLOAT_DWIDTH-1:(i-1)*`BFLOAT_DWIDTH]),
.out_data_available(out_data_available_by[i-1]),
.clk(clk)
);
end
endgenerate
wire start_subldpe;
assign start_subldpe = out_data_available_ax[0];
SUB_LDPE sub_1 (
.clk(clk),
.reset(reset),
.start(start_subldpe),
.ax(ax_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.ay(ay_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.bx(bx_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.by(by_in_sub_ldpe[1*`SUB_LDPE_USED_INPUT_WIDTH-1:(1-1)*`SUB_LDPE_USED_INPUT_WIDTH]),
.out_data_available_external_comparator_tree(out_data_available_external_comparator_tree),
.out_data_available_internal_comparator_tree(out_data_available_internal_comparator_tree),
.out_data_available_dot_prod(out_data_available_dot_prod),
.result(sub_ldpe_result[1*`DSP_USED_OUTPUT_WIDTH-1:(1-1)*`DSP_USED_OUTPUT_WIDTH]),
.max_exp(max_exp)
);
assign ldpe_result = (start==1'b0) ? 'bX : sub_ldpe_result[(0+1)*`DSP_USED_OUTPUT_WIDTH-1:0*`DSP_USED_OUTPUT_WIDTH];
endmodule
| 6.706602 |
module myadder #(
parameter INPUT_WIDTH = `DSP_USED_INPUT_WIDTH,
parameter OUTPUT_WIDTH = `DSP_USED_OUTPUT_WIDTH
) (
input [INPUT_WIDTH-1:0] a,
input [INPUT_WIDTH-1:0] b,
input reset,
input start,
input clk,
output reg [OUTPUT_WIDTH-1:0] sum,
output reg out_data_available
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
sum <= 0;
out_data_available <= 0;
end else begin
out_data_available <= 1;
sum <= {a[INPUT_WIDTH-1], a} + {b[INPUT_WIDTH-1], b};
end
end
endmodule
| 7.085258 |
module VRF #(parameter VRF_AWIDTH = `VRF_AWIDTH, parameter VRF_DWIDTH = `VRF_DWIDTH) (
input clk,
input [VRF_AWIDTH-1:0] addra, addrb,
input [VRF_DWIDTH-1:0] ina, inb,
input wea, web,
output [VRF_DWIDTH-1:0] outa, outb
);
dp_ram # (
.AWIDTH(VRF_AWIDTH),
.DWIDTH(VRF_DWIDTH)
) vec_mem (
.clk(clk),
.addra(addra),
.ina(ina),
.wea(wea),
.outa(outa),
.addrb(addrb),
.inb(inb),
.web(web),
.outb(outb)
);
endmodule
| 7.796665 |
module MRF (
input clk,
input [`MRF_AWIDTH-1:0] addra,
addrb,
input [`MRF_DWIDTH-1:0] ina,
inb,
input wea,
web,
output [`MRF_DWIDTH-1:0] outa,
outb
);
dp_ram #(
.AWIDTH(`MRF_AWIDTH),
.DWIDTH(`MRF_DWIDTH)
) vec_mem (
.clk (clk),
.addra(addra),
.ina (ina),
.wea (wea),
.outa (outa),
.addrb(addrb),
.inb (inb),
.web (web),
.outb (outb)
);
endmodule
| 7.36217 |
module dp_ram #(
parameter AWIDTH = 10,
parameter DWIDTH = 16
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
`else
defparam u_dual_port_ram.ADDR_WIDTH = AWIDTH; defparam u_dual_port_ram.DATA_WIDTH = DWIDTH;
dual_port_ram u_dual_port_ram (
.addr1(addra),
.we1 (wea),
.data1(ina),
.out1 (outa),
.addr2(addrb),
.we2 (web),
.data2(inb),
.out2 (outb),
.clk (clk)
);
`endif
endmodule
| 6.618586 |
module sp_ram #(
parameter AWIDTH = 9,
parameter DWIDTH = 32
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
`ifndef hard_mem
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
`else
defparam u_single_port_ram.ADDR_WIDTH = AWIDTH; defparam u_single_port_ram.DATA_WIDTH = DWIDTH;
single_port_ram u_single_port_ram (
.addr(addr),
.we (we),
.data(in),
.out (out),
.clk (clk)
);
`endif
endmodule
| 7.048193 |
module comparator #(parameter DWIDTH = `BFLOAT_EXP) (
input[DWIDTH-1:0] a,
input[DWIDTH-1:0] b,
input reset,
input start,
input clk,
output reg[DWIDTH-1:0] out,
output reg out_data_available
);
always@(posedge clk) begin
if(reset==1'b1 || start==1'b0) begin
out <= a;
out_data_available <= 0;
end
else begin
out <= (a>b) ? a : b;
out_data_available <= 1;
end
end
endmodule
| 7.565129 |
module fp16_to_msfp11 (
input clk,
input [15:0] a,
input rst,
input start,
output reg [10:0] b,
output reg out_data_available
);
reg [10:0] b_temp;
always @(*) begin
if (a[14:0] == 15'b0) begin //signed zero
b_temp[10] = a[15]; //sign bit
b_temp[9:0] = 7'b0000000; //EXPONENT AND MANTISSA
end else begin
b_temp[4:0] = a[9:5]; //MANTISSA
b_temp[9:5] = a[14:10]; //EXPONENT NOTE- EXPONENT SIZE IS SAME IN BOTH
b_temp[10] = a[15]; //SIGN
end
end
always @(posedge clk) begin
if ((rst == 1'b1) || (start == 1'b0)) begin
b <= 'bX;
out_data_available <= 0;
end else begin
b <= b_temp;
out_data_available <= 1;
end
end
endmodule
| 8.274172 |
module msfp11_to_fp16 (
input reset,
input start,
input clk,
input [10:0] a,
output reg [15:0] b,
output reg out_data_available
);
reg [15:0] b_temp;
reg [ 3:0] j;
reg [ 2:0] k;
reg [ 2:0] k_temp;
always @(*) begin
if (a[9:0] == 7'b0) begin //signed zero
b_temp[15] = a[10]; //sign bit
b_temp[14:0] = 15'b0;
end else begin
/*
if ( a[9:5] == 5'b0 ) begin //denormalized (covert to normalized)
for (j=0; j<=4; j=j+1) begin
if (a[j] == 1'b1) begin
k_temp = j;
end
end
k = 1 - k_temp;
b_temp [9:0] = ( (a [4:0] << (k+1'b1)) & 5'b11111 ) << 5;
//b_temp [14:10] = 5'd31 - 5'd31 - k; //PROBLEM - DISCUSS THIS ************ SHOULD BE +k
b_temp [14:10] = 5'd31 - 5'd31 + k;
b_temp [15] = a[10];
end
*/
if (a[9:5] == 5'b11111) begin //Infinity/ NAN //removed else here
b_temp[9:0] = a[4:0] << 5;
b_temp[14:10] = 5'b11111;
b_temp[15] = a[10];
end else begin //Normalized Number
b_temp[9:0] = a[4:0] << 5;
b_temp[14:10] = 5'd31 - 5'd31 + a[6:2];
b_temp[15] = a[10];
end
end
end
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
out_data_available <= 0;
b <= 'bX;
end else begin
b <= b_temp;
out_data_available <= 1;
end
end
endmodule
| 6.54771 |
module is responsible for taking the inputs
// apart and checking the parts for exceptions.
// The exponent difference is also calculated in this module.
//
module FPAddSub_PrealignModule(
A,
B,
operation,
Sa,
Sb,
ShiftDet,
InputExc,
Aout,
Bout,
Opout
);
// Input ports
input [`DWIDTH-1:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] B ; // Input B, a 32-bit floating point number
input operation ;
// Output ports
output Sa ; // A's sign
output Sb ; // B's sign
output [2*`EXPONENT-1:0] ShiftDet ;
output [4:0] InputExc ; // Input numbers are exceptions
output [`DWIDTH-2:0] Aout ;
output [`DWIDTH-2:0] Bout ;
output Opout ;
// Internal signals // If signal is high...
wire ANaN ; // A is a NaN (Not-a-Number)
wire BNaN ; // B is a NaN
wire AInf ; // A is infinity
wire BInf ; // B is infinity
wire [`EXPONENT-1:0] DAB ; // ExpA - ExpB
wire [`EXPONENT-1:0] DBA ; // ExpB - ExpA
assign ANaN = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(A[`MANTISSA-1:0]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & |(B[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(A[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(A[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(B[`DWIDTH-2:`DWIDTH-1-`EXPONENT]) & ~|(B[`MANTISSA-1:0]) ; // All one exponent and all zero mantissa - Infinity
// Put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf} ;
//assign DAB = (A[30:23] - B[30:23]) ;
//assign DBA = (B[30:23] - A[30:23]) ;
assign DAB = (A[`DWIDTH-2:`MANTISSA] + ~(B[`DWIDTH-2:`MANTISSA]) + 1) ;
assign DBA = (B[`DWIDTH-2:`MANTISSA] + ~(A[`DWIDTH-2:`MANTISSA]) + 1) ;
assign Sa = A[`DWIDTH-1] ; // A's sign bit
assign Sb = B[`DWIDTH-1] ; // B's sign bit
assign ShiftDet = {DBA[`EXPONENT-1:0], DAB[`EXPONENT-1:0]} ; // Shift data
assign Opout = operation ;
assign Aout = A[`DWIDTH-2:0] ;
assign Bout = B[`DWIDTH-2:0] ;
endmodule
| 7.391888 |
module determines the larger input operand and
// sets the mantissas, shift and common exponent accordingly.
//
module FPAddSub_AlignModule (
A,
B,
ShiftDet,
CExp,
MaxAB,
Shift,
Mmin,
Mmax
);
// Input ports
input [`DWIDTH-2:0] A ; // Input A, a 32-bit floating point number
input [`DWIDTH-2:0] B ; // Input B, a 32-bit floating point number
input [2*`EXPONENT-1:0] ShiftDet ;
// Output ports
output [`EXPONENT-1:0] CExp ; // Common Exponent
output MaxAB ; // Incidates larger of A and B (0/A, 1/B)
output [`EXPONENT-1:0] Shift ; // Number of steps to smaller mantissa shift right
output [`MANTISSA-1:0] Mmin ; // Smaller mantissa
output [`MANTISSA-1:0] Mmax ; // Larger mantissa
// Internal signals
//wire BOF ; // Check for shifting overflow if B is larger
//wire AOF ; // Check for shifting overflow if A is larger
assign MaxAB = (A[`DWIDTH-2:0] < B[`DWIDTH-2:0]) ;
//assign BOF = ShiftDet[9:5] < 25 ; // Cannot shift more than 25 bits
//assign AOF = ShiftDet[4:0] < 25 ; // Cannot shift more than 25 bits
// Determine final shift value
//assign Shift = MaxAB ? (BOF ? ShiftDet[9:5] : 5'b11001) : (AOF ? ShiftDet[4:0] : 5'b11001) ;
assign Shift = MaxAB ? ShiftDet[2*`EXPONENT-1:`EXPONENT] : ShiftDet[`EXPONENT-1:0] ;
// Take out smaller mantissa and append shift space
assign Mmin = MaxAB ? A[`MANTISSA-1:0] : B[`MANTISSA-1:0] ;
// Take out larger mantissa
assign Mmax = MaxAB ? B[`MANTISSA-1:0]: A[`MANTISSA-1:0] ;
// Common exponent
assign CExp = (MaxAB ? B[`MANTISSA+`EXPONENT-1:`MANTISSA] : A[`MANTISSA+`EXPONENT-1:`MANTISSA]) ;
endmodule
| 6.986217 |
module FPAddSub_AlignShift1 (
//bf16,
MminP,
Shift,
Mmin
);
// Input ports
//input bf16;
input [`MANTISSA-1:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [`EXPONENT-3:0] Shift ; // Shift amount. Last 2 bits of shifting are done in next stage. Hence, we have [`EXPONENT - 2] bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
wire bf16;
`ifdef BFLOAT16
assign bf16 = 1'b1;
`else
assign bf16 = 1'b0;
`endif
// Internal signals
reg [ `MANTISSA:0] Lvl1;
reg [ `MANTISSA:0] Lvl2;
wire [2*`MANTISSA+1:0] Stage1;
integer i; // Loop variable
wire [ `MANTISSA:0] temp_0;
assign temp_0 = 0;
always @(*) begin
if (bf16 == 1'b1) begin
//hardcoding for bfloat16
//For bfloat16, we can shift the mantissa by a max of 7 bits since mantissa has a width of 7.
//Hence if either, bit[3]/bit[4]/bit[5]/bit[6]/bit[7] is 1, we can make it 0. This corresponds to bits [5:1] in our updated shift which doesn't contain last 2 bits.
//Lvl1 <= (Shift[1]|Shift[2]|Shift[3]|Shift[4]|Shift[5]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
Lvl1 <= (|Shift[`EXPONENT-3:1]) ? {temp_0} : {1'b1, MminP}; // MANTISSA + 1 width
end else begin
//for half precision fp16, 10 bits can be shifted. Hence, only shifts till 10 (01010)can be made.
Lvl1 <= Shift[2] ? {temp_0} : {1'b1, MminP};
end
end
assign Stage1 = {temp_0, Lvl1}; //2*MANTISSA + 2 width
always @(*) begin // Rotate {0 | 4 } bits
if (bf16 == 1'b1) begin
case (Shift[0])
// Rotate by 0
1'b0: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
1'b1: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
endcase
end else begin
case (Shift[1:0]) // Rotate {0 | 4 | 8} bits
// Rotate by 0
2'b00: Lvl2 <= Stage1[`MANTISSA:0];
// Rotate by 4
2'b01: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+4];
end
Lvl2[`MANTISSA:`MANTISSA-3] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 0; i <= `MANTISSA; i = i + 1) begin
Lvl2[i] <= Stage1[i+8];
end
Lvl2[`MANTISSA:`MANTISSA-7] <= 0;
end
// Rotate by 12
2'b11: Lvl2[`MANTISSA:0] <= 0;
//2'b11: begin for (i=0; i<=`MANTISSA; i=i+1) begin Lvl2[i] <= Stage1[i+12]; end Lvl2[`MANTISSA:`MANTISSA-12] <= 0; end
endcase
end
end
// Assign output to next shift stage
assign Mmin = Lvl2;
endmodule
| 6.969233 |
module FPAddSub_AlignShift2 (
MminP,
Shift,
Mmin
);
// Input ports
input [`MANTISSA:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [1:0] Shift; // Shift amount. Last 2 bits
// Output ports
output [`MANTISSA:0] Mmin; // The smaller mantissa
// Internal Signal
reg [ `MANTISSA:0] Lvl3;
wire [2*`MANTISSA+1:0] Stage2;
integer j; // Loop variable
assign Stage2 = {11'b0, MminP};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`MANTISSA:0];
// Rotate by 1
2'b01: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+1];
end
Lvl3[`MANTISSA] <= 0;
end
// Rotate by 2
2'b10: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+2];
end
Lvl3[`MANTISSA:`MANTISSA-1] <= 0;
end
// Rotate by 3
2'b11: begin
for (j = 0; j <= `MANTISSA; j = j + 1) begin
Lvl3[j] <= Stage2[j+3];
end
Lvl3[`MANTISSA:`MANTISSA-2] <= 0;
end
endcase
end
// Assign output
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.969233 |
module FPAddSub_ExecutionModule (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
Sum,
PSgn,
Opr
);
// Input ports
input [`MANTISSA-1:0] Mmax; // The larger mantissa
input [`MANTISSA:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
output [`DWIDTH:0] Sum; // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
wire [`EXPONENT-1:0] temp_1;
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
assign temp_1 = 0;
// Perform effective operation
//SAMIDH_UNSURE 5--> 8
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, temp_1} - {Mmin, temp_1}) : ({1'b1, Mmax, temp_1} + {Mmin, temp_1}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
endmodule
| 6.632792 |
module FPAddSub_NormalizeModule (
Sum,
Mmin,
Shift
);
// Input ports
input [`DWIDTH:0] Sum; // Mantissa sum including hidden 1 and GRS
// Output ports
output [`DWIDTH:0] Mmin; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount
//Changes in this doesn't matter since even Bfloat16 can't go beyond 7 shift to the mantissa (only 3 bits valid here)
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[16] ? 5'b00000 :
Sum[15] ? 5'b00001 :
Sum[14] ? 5'b00010 :
Sum[13] ? 5'b00011 :
Sum[12] ? 5'b00100 :
Sum[11] ? 5'b00101 :
Sum[10] ? 5'b00110 :
Sum[9] ? 5'b00111 :
Sum[8] ? 5'b01000 :
Sum[7] ? 5'b01001 :
Sum[6] ? 5'b01010 :
Sum[5] ? 5'b01011 :
Sum[4] ? 5'b01100 : 5'b01101
// Sum[19] ? 5'b01101 :
// Sum[18] ? 5'b01110 :
// Sum[17] ? 5'b01111 :
// Sum[16] ? 5'b10000 :
// Sum[15] ? 5'b10001 :
// Sum[14] ? 5'b10010 :
// Sum[13] ? 5'b10011 :
// Sum[12] ? 5'b10100 :
// Sum[11] ? 5'b10101 :
// Sum[10] ? 5'b10110 :
// Sum[9] ? 5'b10111 :
// Sum[8] ? 5'b11000 :
// Sum[7] ? 5'b11001 : 5'b11010
);
reg [`DWIDTH:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[8:0], 8'b00000000} : Sum;
end
// Assign outputs
assign Mmin = Lvl1; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift1 (
MminP,
Shift,
Mmin
);
// Input ports
input [`DWIDTH:0] MminP; // Smaller mantissa after 16|12|8|4 shift
input [3:0] Shift; // Shift amount
// Output ports
output [`DWIDTH:0] Mmin; // The smaller mantissa
reg [ `DWIDTH:0] Lvl2;
wire [2*`DWIDTH+1:0] Stage1;
reg [ `DWIDTH:0] Lvl3;
wire [2*`DWIDTH+1:0] Stage2;
integer i; // Loop variable
assign Stage1 = {MminP, MminP};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: Lvl2 <= Stage1[`DWIDTH:0];
// Rotate by 4
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-4];
end
Lvl2[3:0] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-8];
end
Lvl2[7:0] <= 0;
end
// Rotate by 12
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl2[i-`DWIDTH-1] <= Stage1[i-12];
end
Lvl2[11:0] <= 0;
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[`DWIDTH:0];
// Rotate by 1
2'b01: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-1];
end
Lvl3[0] <= 0;
end
// Rotate by 2
2'b10: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-2];
end
Lvl3[1:0] <= 0;
end
// Rotate by 3
2'b11: begin
for (i = 33; i >= 17; i = i - 1) begin
Lvl3[i-`DWIDTH-1] <= Stage2[i-3];
end
Lvl3[2:0] <= 0;
end
endcase
end
// Assign outputs
assign Mmin = Lvl3; // Take out smaller mantissa
endmodule
| 6.905513 |
module FPAddSub_NormalizeShift2 (
PSSum,
CExp,
Shift,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [`DWIDTH:0] PSSum; // The Pre-Shift-Sum
input [`EXPONENT-1:0] CExp;
input [4:0] Shift; // Amount to be shifted
// Output ports
output [`MANTISSA-1:0] NormM; // Normalized mantissa
output [`EXPONENT:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [`EXPONENT:0] ExpOF; // MSB set in sum indicates overflow
wire [`EXPONENT:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = PSSum[`DWIDTH]; // Check MSB in unnormalized sum
assign ZeroSum = ~|PSSum; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[`EXPONENT]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = PSSum[`DWIDTH-1:`EXPONENT+1]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = PSSum[`EXPONENT];
assign R = PSSum[`EXPONENT-1];
assign S = |PSSum[`EXPONENT-2:0];
endmodule
| 6.905513 |
module FPAddSub_RoundModule (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
Z,
EOF
);
// Input ports
input ZeroSum; // Sum is zero
input [`EXPONENT:0] NormE; // Normalized exponent
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
// Output ports
output [`DWIDTH-1:0] Z; // Final result
output EOF;
// Internal signals
wire [ `MANTISSA:0] RoundUpM; // Rounded up sum with room for overflow
wire [`MANTISSA-1:0] RoundM; // The final rounded sum
wire [ `EXPONENT:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire FSgn;
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
wire [ `EXPONENT:0] temp_2;
assign temp_2 = 0;
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[`MANTISSA-1:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[`MANTISSA]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? temp_2 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[`EXPONENT-1:0], RoundM[`MANTISSA-1:0]};
// Indicate exponent overflow
assign EOF = RoundE[`EXPONENT];
endmodule
| 7.753919 |
module FPAddSub_ExceptionModule (
Z,
NegE,
R,
S,
InputExc,
EOF,
P,
Flags
);
// Input ports
input [`DWIDTH-1:0] Z; // Final product
input NegE; // Negative exponent?
input R; // Round bit
input S; // Sticky bit
input [4:0] InputExc; // Exceptions in inputs A and B
input EOF;
// Output ports
output [`DWIDTH-1:0] P; // Final result
output [4:0] Flags; // Exception flags
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~|(Z[`MANTISSA+`EXPONENT-1:`MANTISSA]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.326377 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [`DWIDTH-1:0] a; // Input A, a 32-bit floating point number
input [`DWIDTH-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [`EXPONENT-1:0] Ea; // A's exponent
output [`EXPONENT-1:0] Eb; // B's exponent
output [2*`MANTISSA+1:0] Mp; // Mantissa product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [`MANTISSA-1:0] Ma;
wire [`MANTISSA-1:0] Mb;
assign ANaN = &(a[`DWIDTH-2:`MANTISSA]) & |(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and not all zero mantissa - NaN
assign BNaN = &(b[`DWIDTH-2:`MANTISSA]) & |(b[`MANTISSA-1:0]); // All one exponent and not all zero mantissa - NaN
assign AInf = &(a[`DWIDTH-2:`MANTISSA]) & ~|(a[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
assign BInf = &(b[`DWIDTH-2:`MANTISSA]) & ~|(b[`DWIDTH-2:`MANTISSA]) ; // All one exponent and all zero mantissa - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[`DWIDTH-1]; // A's sign
assign Sb = b[`DWIDTH-1]; // B's sign
assign Ea = a[`DWIDTH-2:`MANTISSA]; // Store A's exponent in Ea, unless A is an exception
assign Eb = b[`DWIDTH-2:`MANTISSA]; // Store B's exponent in Eb, unless B is an exception
// assign Ma = a[`MANTISSA_MSB:`MANTISSA_LSB];
// assign Mb = b[`MANTISSA_MSB:`MANTISSA_LSB];
//assign Mp = ({4'b0001, a[`MANTISSA-1:0]}*{4'b0001, b[`MANTISSA-1:9]}) ;
assign Mp = ({1'b1, a[`MANTISSA-1:0]} * {1'b1, b[`MANTISSA-1:0]});
//We multiply part of the mantissa here
//Full mantissa of A
//Bits MANTISSA_MUL_SPLIT_MSB:MANTISSA_MUL_SPLIT_LSB of B
// wire [`ACTUAL_MANTISSA-1:0] inp_A;
// wire [`ACTUAL_MANTISSA-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(`MANTISSA-(`MANTISSA_MUL_SPLIT_MSB-`MANTISSA_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[`MANTISSA_MUL_SPLIT_MSB:`MANTISSA_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_MANTISSA,`ACTUAL_MANTISSA) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [`MANTISSA-1:0] NormM; // Normalized mantissa
input [`EXPONENT:0] NormE; // Normalized exponent
// Output Ports
output [`EXPONENT:0] RoundE;
output [`EXPONENT:0] RoundEP;
output [`MANTISSA:0] RoundM;
output [`MANTISSA:0] RoundMP;
// EXPONENT = 5
// EXPONENT -1 = 4
// NEED to subtract 2^4 -1 = 15
wire [`EXPONENT-1 : 0] bias;
assign bias = ((1 << (`EXPONENT - 1)) - 1);
assign RoundE = NormE - bias;
assign RoundEP = NormE - bias - 1;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [`MANTISSA:0] RoundM; // Normalized mantissa
input [`MANTISSA:0] RoundMP; // Normalized exponent
input [`EXPONENT:0] RoundE; // Normalized mantissa + 1
input [`EXPONENT:0] RoundEP; // Normalized exponent + 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [`DWIDTH-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [`EXPONENT:0] FinalE; // Rounded exponent
wire [`MANTISSA:0] FinalM;
wire [`MANTISSA:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted mantissa if there is overflow)
assign FinalM = (PreShiftM[`MANTISSA] ? {1'b0, PreShiftM[`MANTISSA:1]} : PreShiftM[`MANTISSA:0]);
assign FinalE = (PreShiftM[`MANTISSA] ? RoundEP : RoundE) ; // Increment exponent if a shift was done
assign Z = {Sp, FinalE[`EXPONENT-1:0], FinalM[`MANTISSA-1:0]}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module array_mux_2to1 #(
parameter size = 10
) (
clk,
reset,
start,
out,
in0,
in1,
sel,
out_data_available
);
input [size-1:0] in0, in1;
input sel, clk;
input reset, start;
output reg [size-1:0] out;
output reg out_data_available;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
out <= 'bX;
out_data_available <= 0;
end else begin
out <= (sel) ? in1 : in0;
out_data_available <= 1;
end
end
endmodule
| 7.273845 |
module barrel_shifter_right (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_arr_0;
array_mux_2to1 #(
.size(7)
) M0 (
.clk(clk),
.reset(reset),
.start(start),
.out(out0),
.in0({significand[5:0], 1'b0}),
.in1({1'b0, significand[5:0]}),
.sel(shift_amt[0]),
.out_data_available(out_data_available_arr_0)
);
//level 1
wire [8:0] out1;
wire out_data_available_arr_1;
array_mux_2to1 #(
.size(9)
) M1 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_0),
.out(out1),
.in0({out0[6:0], 2'b0}),
.in1({2'b0, out0[6:0]}),
.sel(shift_amt[1]),
.out_data_available(out_data_available_arr_1)
);
//level 2
wire [12:0] out2;
array_mux_2to1 #(
.size(13)
) M2 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_1),
.out(out2),
.in0({out1[8:0], 4'b0}),
.in1({4'b0, out1[8:0]}),
.sel(shift_amt[2]),
.out_data_available(out_data_available)
);
//shifted significand
assign shifted_sig = (reset == 1'b1) ? 'bX : out2[12:7];
endmodule
| 8.606549 |
module barrel_shifter_left (
input clk,
input reset,
input start,
input [4:0] shift_amt,
input [5:0] significand,
output [5:0] shifted_sig,
output out_data_available
);
//3-level distributed barrel shifter using 10 2:1 MUX array
//level 0
wire [6:0] out0;
wire out_data_available_arr_0;
array_mux_2to1 #(
.size(7)
) M0 (
.clk(clk),
.reset(reset),
.start(start),
.out(out0),
.in0({1'b0, significand[5:0]}),
.in1({significand[5:0], 1'b0}),
.sel(shift_amt[0]),
.out_data_available(out_data_available_arr_0)
);
//level 1
wire [8:0] out1;
wire out_data_available_arr_1;
array_mux_2to1 #(
.size(9)
) M1 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_0),
.out(out1),
.in0({2'b0, out0[6:0]}),
.in1({out0[6:0], 2'b0}),
.sel(shift_amt[1]),
.out_data_available(out_data_available_arr_1)
);
//level 2
wire [12:0] out2;
array_mux_2to1 #(
.size(13)
) M2 (
.clk(clk),
.reset(reset),
.start(out_data_available_arr_1),
.out(out2),
.in0({4'b0, out1[8:0]}),
.in1({out1[8:0], 4'b0}),
.sel(shift_amt[2]),
.out_data_available(out_data_available)
);
//shifted significand
assign shifted_sig = (reset == 1'b1) ? 'bX : out2[5:0];
endmodule
| 8.606549 |
module leading_zero_detector_6bit (
input clk,
input [5:0] a,
input reset,
input start,
output reg [2:0] position,
output reg is_valid,
output reg out_data_available
);
wire [1:0] posi_upper, posi_lower;
wire valid_upper, valid_lower;
reg [3:0] num_cycles;
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
num_cycles <= 0;
out_data_available <= 0;
end else begin
if (num_cycles == `NUM_LZD_CYCLES) begin
out_data_available <= 1;
end else begin
num_cycles <= num_cycles + 1;
end
end
end
leading_zero_detector_4bit lzd4_upper (
.clk(clk),
.reset(reset),
.start(start),
.a(a[5:2]),
.position(posi_upper),
.is_valid(valid_upper)
);
leading_zero_detector_4bit lzd4_lower (
.clk(clk),
.reset(reset),
.start(start),
.a({a[1:0], 2'b00}),
.position(posi_lower),
.is_valid(valid_lower)
);
always @(posedge clk) begin
if ((reset == 1'b1) || (start == 1'b0)) begin
is_valid <= 0;
position <= 'bX;
end else begin
is_valid <= valid_upper | valid_lower;
position[2] <= ~valid_upper;
position[1] <= valid_upper ? posi_upper[1] : posi_lower[1];
position[0] <= valid_upper ? posi_upper[0] : posi_lower[0];
end
end
endmodule
| 6.847206 |
module leading_zero_detector_4bit (
input clk,
input [3:0] a,
input reset,
input start,
output reg [1:0] position,
output reg is_valid
);
wire posi_upper, posi_lower;
wire valid_upper, valid_lower;
leading_zero_detector_2bit lzd2_upper (
.clk(clk),
.reset(reset),
.start(start),
.a(a[3:2]),
.position(posi_upper),
.is_valid(valid_upper)
);
leading_zero_detector_2bit lzd2_lower (
.clk(clk),
.reset(reset),
.start(start),
.a(a[1:0]),
.position(posi_lower),
.is_valid(valid_lower)
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= valid_upper | valid_lower;
position[1] <= ~valid_upper;
position[0] <= valid_upper ? posi_upper : posi_lower;
end
end
endmodule
| 6.847206 |
module leading_zero_detector_2bit (
input clk,
input [1:0] a,
input reset,
input start,
output reg position,
output reg is_valid
);
always @(posedge clk) begin
if ((reset == 1) || (start == 0)) begin
is_valid <= 0;
end else begin
is_valid <= a[1] | a[0];
position <= ~a[1];
end
end
endmodule
| 6.847206 |
module brake_sm (
input wire clk,
input wire brake,
input wire [2:0] left_signal,
input wire [2:0] right_signal,
output reg [2:0] left_lights,
output reg [1:0] center_lights,
output reg [2:0] right_lights
);
// State parameters
parameter idle_state = 2'd0;
parameter brake_state = 2'd1;
parameter brake_timeout1 = 2'd2;
parameter brake_timeout2 = 2'd3;
// Output parameters
parameter center_0 = 2'b00;
parameter center_2 = 2'b11;
reg brake_active;
reg [1:0] state, next_state;
initial begin
state = idle_state;
end
// Registered always block
always @(posedge clk) begin
state <= next_state;
end
// Combinational always block
// Next state logic
always @(brake, state) begin
case (state)
idle_state: begin
if (brake) begin
next_state = brake_state;
end else begin
next_state = idle_state;
end
end
brake_state: begin
if (brake) begin
next_state = brake_state;
end else begin
next_state = brake_timeout1;
end
end
brake_timeout1: begin
if (brake) begin
next_state = brake_state;
end else begin
next_state = brake_timeout2;
end
end
brake_timeout2: begin
if (brake) begin
next_state = brake_state;
end else begin
next_state = idle_state;
end
end
default: begin
next_state = idle_state;
end
endcase
end
// Combinational always block
// Internal logic, Moore Machine
always @(state) begin
case (state)
idle_state: brake_active = 1'b0;
brake_state: brake_active = 1'b1;
brake_timeout1: brake_active = 1'b1;
brake_timeout2: brake_active = 1'b1;
default: brake_active = 1'b0;
endcase
end
// Combinational always block
// Output logic, Mealy Machine
always @(left_signal, right_signal, brake_active) begin
// When brakes are active, invert turn signals, turn on center
if (brake_active) begin
left_lights = ~left_signal;
center_lights = center_2;
right_lights = ~right_signal;
end // When inactive, pass through turn signal, turn off center
else begin
left_lights = left_signal;
center_lights = center_0;
right_lights = right_signal;
end
end
endmodule
| 8.827864 |
module sram #(
parameter ADDR_WIDTH = 8,
DATA_WIDTH = 8,
DEPTH = 256,
MEMFILE = ""
) (
input wire clk,
input wire [ADDR_WIDTH-1:0] i_addr,
input wire i_write,
input wire [DATA_WIDTH-1:0] i_data,
output reg [DATA_WIDTH-1:0] o_data
);
reg [DATA_WIDTH-1:0] memory_array[0:DEPTH-1];
initial begin
if (MEMFILE > 0) begin
$display("Loading memory init file '" + MEMFILE + "' into array.");
$readmemh(MEMFILE, memory_array);
end
end
always @(posedge clk) begin
if (i_write) begin
memory_array[i_addr] <= i_data;
end else begin
o_data <= memory_array[i_addr];
end
end
endmodule
| 7.388143 |
module bram0 #(
parameter ADDR_WIDTH = 13 //width of addresses buses
//parameter ramN = "filedir passed as a parameter" //Number of ram
) (
input CLK,
input [(ADDR_WIDTH-1):0] W_ADDR,
input [(ADDR_WIDTH-1):0] R_ADDR,
input WRITE_EN,
input READ_EN,
input [7:0] DIN,
output reg [7:0] DOUT
);
reg [7:0] mem[2**(ADDR_WIDTH-3):0];
integer idx;
initial begin
//$display(ramN);
//$readmemh(ramN, mem);
$readmemh("../../firmware/build/output/data0.txt", mem);
$dumpfile("PPCSoC_tb.vcd");
//for (idx = 0; idx < 10; idx = idx + 1) $dumpvars(0, mem[idx]);
//$dumpvars(0, mem[4096]);
$dumpvars(0, mem[2]);
end
always @(negedge CLK) begin
if (WRITE_EN) mem[W_ADDR[ADDR_WIDTH-1:2]] <= DIN;
if (READ_EN) DOUT <= mem[R_ADDR[ADDR_WIDTH-1:2]];
end
endmodule
| 6.865968 |
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLK) begin
if (EN) begin
if (WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule
| 7.357455 |
module bram16 #(
parameter init_file = "none",
parameter adr_width = 11
) (
input sys_clk,
input sys_rst,
input [15:0] do,
output reg [15:0] di,
input we,
input [15:0] a
);
//-----------------------------------------------------------------
// Storage depth in 16 bit words
//-----------------------------------------------------------------
parameter word_width = adr_width - 1;
parameter word_depth = (1 << word_width);
//-----------------------------------------------------------------
// Actual RAM
//-----------------------------------------------------------------
reg [15:0] ram [0:word_depth-1];
wire [word_width-1:0] adr;
always @(posedge sys_clk) begin
if (we) begin
ram[adr] <= do;
end
di <= ram[adr];
end
assign adr = a[adr_width-1:1];
//-----------------------------------------------------------------
// RAM initialization
//-----------------------------------------------------------------
initial
begin
if (init_file != "none")
begin
$readmemh(init_file, ram);
end
end
endmodule
| 8.517978 |
module af2048x8_2048x8 (
DIN,
PUSH,
POP,
clock0,
clock1,
Async_Flush,
Almost_Full,
Almost_Empty,
Full,
Empty,
Full_Watermark,
Empty_Watermark,
Overrun_Error,
Underrun_Error,
DOUT
);
parameter WR_DATA_WIDTH = 8;
parameter RD_DATA_WIDTH = 8;
parameter UPAE_DBITS = 11'd10;
parameter UPAF_DBITS = 11'd10;
input clock0, clock1;
input PUSH, POP;
input [WR_DATA_WIDTH-1:0] DIN;
input Async_Flush;
output [RD_DATA_WIDTH-1:0] DOUT;
output Almost_Full, Almost_Empty;
output Full, Empty;
output Full_Watermark, Empty_Watermark;
output Overrun_Error, Underrun_Error;
AFIFO_18K_BLK #(
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS(UPAE_DBITS),
.UPAF_DBITS(UPAF_DBITS)
) FIFO_INST (
.DIN(DIN),
.PUSH(PUSH),
.POP(POP),
.Push_Clk(clock0),
.Pop_Clk(clock1),
.Async_Flush(Async_Flush),
.Overrun_Error(Overrun_Error),
.Full_Watermark(Full_Watermark),
.Almost_Full(Almost_Full),
.Full(Full),
.Underrun_Error(Underrun_Error),
.Empty_Watermark(Empty_Watermark),
.Almost_Empty(Almost_Empty),
.Empty(Empty),
.DOUT(DOUT)
);
endmodule
| 6.662899 |
module TB;
localparam PERIOD = 30;
localparam ADDR_INCR = 1;
reg clk0;
reg clk1;
reg flush;
reg pop;
wire [`DATA_WIDTH1-1:0] dout;
reg push;
reg [`DATA_WIDTH0-1:0] din;
wire almost_full, almost_empty;
wire full, empty;
wire full_watermark, empty_watermark;
wire overrun_error, underrun_error;
initial begin
clk0 = 0;
clk1 = 0;
pop = 0;
push = 0;
flush = 1;
din = 0;
#40 flush = 0;
end
initial forever #(PERIOD / 3.0) clk0 = ~clk0;
initial forever #(PERIOD / 2.0) clk1 = ~clk1;
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
reg done;
initial done = 1'b0;
reg read_test;
initial read_test = 0;
reg [`DATA_WIDTH1-1:0] expected;
initial expected = 0;
always @(posedge clk1) begin
expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
end
wire error = ((a != 0) && read_test) ? dout !== expected : 0;
integer error_cnt = 0;
always @(posedge clk1) begin
if (error) error_cnt <= error_cnt + 1'b1;
end
initial
#(50) begin
@(posedge clk0)
// Write data
for (
a = 0; a < (1 << `ADDR_WIDTH0); a = a + ADDR_INCR
) begin
@(negedge clk0) begin
din = a | (a << 20) | 20'h55000;
push = 1;
end
@(posedge clk0) begin
#(PERIOD / 10) push = 0;
end
end
// Read data
read_test = 1;
for (a = 0; a < (1 << `ADDR_WIDTH1); a = a + ADDR_INCR) begin
@(posedge clk1) begin
#(PERIOD / 10) pop = 0;
if (dout !== expected) begin
$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
end else begin
$display("%d: OK: act=%x exp=%x at %x", $time, dout, expected, a);
end
end
@(negedge clk1) begin
pop = 1;
end
end
done = 1'b1;
end
// Scan for simulation finish
always @(posedge clk1) begin
if (done) $finish_and_return((error_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"af1024x18_1024x18": begin
af1024x18_1024x18 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk0),
.clock1(clk1),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"af1024x16_1024x16": begin
af1024x16_1024x16 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk0),
.clock1(clk1),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"af2048x9_2048x9": begin
af2048x9_2048x9 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk0),
.clock1(clk1),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"af2048x8_2048x8": begin
af2048x8_2048x8 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk0),
.clock1(clk1),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
endcase
endmodule
| 7.277485 |
module TB;
localparam PERIOD = 30;
localparam ADDR_INCR = 1;
reg clk;
reg flush;
reg pop;
wire [`DATA_WIDTH1-1:0] dout;
reg push;
reg [`DATA_WIDTH0-1:0] din;
wire almost_full, almost_empty;
wire full, empty;
wire full_watermark, empty_watermark;
wire overrun_error, underrun_error;
initial begin
clk = 0;
pop = 0;
push = 0;
flush = 1;
din = 0;
#40 flush = 0;
end
initial forever #(PERIOD / 3.0) clk = ~clk;
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
reg done;
initial done = 1'b0;
reg read_test;
initial read_test = 0;
reg [`DATA_WIDTH1-1:0] expected;
initial expected = 0;
always @(posedge clk) begin
expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
end
wire error = ((a != 0) && read_test) ? dout !== expected : 0;
integer error_cnt = 0;
always @(posedge clk) begin
if (error) error_cnt <= error_cnt + 1'b1;
end
initial
#(50) begin
@(posedge clk)
// Write data
for (
a = 0; a < (1 << `ADDR_WIDTH0); a = a + ADDR_INCR
) begin
@(negedge clk) begin
din = a | (a << 20) | 20'h55000;
push = 1;
end
@(posedge clk) begin
#(PERIOD / 10) push = 0;
end
end
// Read data
read_test = 1;
for (a = 0; a < (1 << `ADDR_WIDTH1); a = a + ADDR_INCR) begin
@(posedge clk) begin
#(PERIOD / 10) pop = 0;
if (dout !== expected) begin
$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
end else begin
$display("%d: OK: act=%x exp=%x at %x", $time, dout, expected, a);
end
end
@(negedge clk) begin
pop = 1;
end
end
done = 1'b1;
end
// Scan for simulation finish
always @(posedge clk) begin
if (done) $finish_and_return((error_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"f1024x18_1024x18": begin
f1024x18_1024x18 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"f1024x16_1024x16": begin
f1024x16_1024x16 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"f2048x9_2048x9": begin
f2048x9_2048x9 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"f2048x8_2048x8": begin
f2048x8_2048x8 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
endcase
endmodule
| 7.277485 |
module dpram_18x1024_x2 (
clk_a_0,
WEN_a_0,
REN_a_0,
WR_ADDR_a_0,
RD_ADDR_a_0,
WDATA_a_0,
RDATA_a_0,
clk_b_0,
WEN_b_0,
REN_b_0,
WR_ADDR_b_0,
RD_ADDR_b_0,
WDATA_b_0,
RDATA_b_0,
clk_a_1,
WEN_a_1,
REN_a_1,
WR_ADDR_a_1,
RD_ADDR_a_1,
WDATA_a_1,
RDATA_a_1,
clk_b_1,
WEN_b_1,
REN_b_1,
WR_ADDR_b_1,
RD_ADDR_b_1,
WDATA_b_1,
RDATA_b_1
);
parameter ADDR_WIDTH0 = 10;
parameter DATA_WIDTH0 = 18;
parameter BE1_WIDTH0 = 2;
parameter BE2_WIDTH0 = 2;
parameter ADDR_WIDTH1 = 10;
parameter DATA_WIDTH1 = 18;
parameter BE1_WIDTH1 = 2;
parameter BE2_WIDTH1 = 2;
input wire clk_a_0;
input wire WEN_a_0;
input wire REN_a_0;
input wire [ADDR_WIDTH0-1 : 0] WR_ADDR_a_0;
input wire [ADDR_WIDTH0-1 : 0] RD_ADDR_a_0;
input wire [DATA_WIDTH0-1 : 0] WDATA_a_0;
output wire [DATA_WIDTH0-1 : 0] RDATA_a_0;
input wire clk_b_0;
input wire WEN_b_0;
input wire REN_b_0;
input wire [ADDR_WIDTH0-1 : 0] WR_ADDR_b_0;
input wire [ADDR_WIDTH0-1 : 0] RD_ADDR_b_0;
input wire [DATA_WIDTH0-1 : 0] WDATA_b_0;
output wire [DATA_WIDTH0-1 : 0] RDATA_b_0;
input wire clk_a_1;
input wire WEN_a_1;
input wire REN_a_1;
input wire [ADDR_WIDTH1-1 : 0] WR_ADDR_a_1;
input wire [ADDR_WIDTH1-1 : 0] RD_ADDR_a_1;
input wire [DATA_WIDTH1-1 : 0] WDATA_a_1;
output wire [DATA_WIDTH1-1 : 0] RDATA_a_1;
input wire clk_b_1;
input wire WEN_b_1;
input wire REN_b_1;
input wire [ADDR_WIDTH1-1 : 0] WR_ADDR_b_1;
input wire [ADDR_WIDTH1-1 : 0] RD_ADDR_b_1;
input wire [DATA_WIDTH1-1 : 0] WDATA_b_1;
output wire [DATA_WIDTH1-1 : 0] RDATA_b_1;
DPRAM_18K_BLK #(
.ADDR_WIDTH(ADDR_WIDTH0),
.DATA_WIDTH(DATA_WIDTH0),
.BE1_WIDTH (BE1_WIDTH0),
.BE2_WIDTH (BE2_WIDTH0)
) dpram_x18_inst0 (
.CLK1_i(clk_a_0),
.WEN1_i(WEN_a_0),
.REN1_i(REN_a_0),
.WR1_ADDR_i(WR_ADDR_a_0),
.RD1_ADDR_i(RD_ADDR_a_0),
.WDATA1_i(WDATA_a_0),
.RDATA1_o(RDATA_a_0),
.CLK2_i(clk_b_0),
.WEN2_i(WEN_b_0),
.REN2_i(REN_b_0),
.WR2_ADDR_i(WR_ADDR_b_0),
.RD2_ADDR_i(RD_ADDR_b_0),
.WDATA2_i(WDATA_b_0),
.RDATA2_o(RDATA_b_0)
);
DPRAM_18K_BLK #(
.ADDR_WIDTH(ADDR_WIDTH1),
.DATA_WIDTH(DATA_WIDTH1),
.BE1_WIDTH (BE1_WIDTH1),
.BE2_WIDTH (BE2_WIDTH1)
) dpram_x18_inst1 (
.CLK1_i(clk_a_1),
.WEN1_i(WEN_a_1),
.REN1_i(REN_a_1),
.WR1_ADDR_i(WR_ADDR_a_1),
.RD1_ADDR_i(RD_ADDR_a_1),
.WDATA1_i(WDATA_a_1),
.RDATA1_o(RDATA_a_1),
.CLK2_i(clk_b_1),
.WEN2_i(WEN_b_1),
.REN2_i(REN_b_1),
.WR2_ADDR_i(WR_ADDR_b_1),
.RD2_ADDR_i(RD_ADDR_b_1),
.WDATA2_i(WDATA_b_1),
.RDATA2_o(RDATA_b_1)
);
endmodule
| 6.662554 |
module dpram_18x1024_9x2048 (
clk_a_0,
WEN_a_0,
REN_a_0,
WR_ADDR_a_0,
RD_ADDR_a_0,
WDATA_a_0,
RDATA_a_0,
clk_b_0,
WEN_b_0,
REN_b_0,
WR_ADDR_b_0,
RD_ADDR_b_0,
WDATA_b_0,
RDATA_b_0,
clk_a_1,
WEN_a_1,
REN_a_1,
WR_ADDR_a_1,
RD_ADDR_a_1,
WDATA_a_1,
RDATA_a_1,
clk_b_1,
WEN_b_1,
REN_b_1,
WR_ADDR_b_1,
RD_ADDR_b_1,
WDATA_b_1,
RDATA_b_1
);
parameter ADDR_WIDTH0 = 10;
parameter DATA_WIDTH0 = 18;
parameter BE1_WIDTH0 = 2;
parameter BE2_WIDTH0 = 2;
parameter ADDR_WIDTH1 = 11;
parameter DATA_WIDTH1 = 9;
parameter BE1_WIDTH1 = 1;
parameter BE2_WIDTH1 = 1;
input wire clk_a_0;
input wire WEN_a_0;
input wire REN_a_0;
input wire [ADDR_WIDTH0-1 : 0] WR_ADDR_a_0;
input wire [ADDR_WIDTH0-1 : 0] RD_ADDR_a_0;
input wire [DATA_WIDTH0-1 : 0] WDATA_a_0;
output wire [DATA_WIDTH0-1 : 0] RDATA_a_0;
input wire clk_b_0;
input wire WEN_b_0;
input wire REN_b_0;
input wire [ADDR_WIDTH0-1 : 0] WR_ADDR_b_0;
input wire [ADDR_WIDTH0-1 : 0] RD_ADDR_b_0;
input wire [DATA_WIDTH0-1 : 0] WDATA_b_0;
output wire [DATA_WIDTH0-1 : 0] RDATA_b_0;
input wire clk_a_1;
input wire WEN_a_1;
input wire REN_a_1;
input wire [ADDR_WIDTH1-1 : 0] WR_ADDR_a_1;
input wire [ADDR_WIDTH1-1 : 0] RD_ADDR_a_1;
input wire [DATA_WIDTH1-1 : 0] WDATA_a_1;
output wire [DATA_WIDTH1-1 : 0] RDATA_a_1;
input wire clk_b_1;
input wire WEN_b_1;
input wire REN_b_1;
input wire [ADDR_WIDTH1-1 : 0] WR_ADDR_b_1;
input wire [ADDR_WIDTH1-1 : 0] RD_ADDR_b_1;
input wire [DATA_WIDTH1-1 : 0] WDATA_b_1;
output wire [DATA_WIDTH1-1 : 0] RDATA_b_1;
DPRAM_18K_BLK #(
.ADDR_WIDTH(ADDR_WIDTH0),
.DATA_WIDTH(DATA_WIDTH0),
.BE1_WIDTH (BE1_WIDTH0),
.BE2_WIDTH (BE2_WIDTH0)
) dpram_x18_inst0 (
.CLK1_i(clk_a_0),
.WEN1_i(WEN_a_0),
.REN1_i(REN_a_0),
.WR1_ADDR_i(WR_ADDR_a_0),
.RD1_ADDR_i(RD_ADDR_a_0),
.WDATA1_i(WDATA_a_0),
.RDATA1_o(RDATA_a_0),
.CLK2_i(clk_b_0),
.WEN2_i(WEN_b_0),
.REN2_i(REN_b_0),
.WR2_ADDR_i(WR_ADDR_b_0),
.RD2_ADDR_i(RD_ADDR_b_0),
.WDATA2_i(WDATA_b_0),
.RDATA2_o(RDATA_b_0)
);
DPRAM_18K_BLK #(
.ADDR_WIDTH(ADDR_WIDTH1),
.DATA_WIDTH(DATA_WIDTH1),
.BE1_WIDTH (BE1_WIDTH1),
.BE2_WIDTH (BE2_WIDTH1)
) dpram_x18_inst1 (
.CLK1_i(clk_a_1),
.WEN1_i(WEN_a_1),
.REN1_i(REN_a_1),
.WR1_ADDR_i(WR_ADDR_a_1),
.RD1_ADDR_i(RD_ADDR_a_1),
.WDATA1_i(WDATA_a_1),
.RDATA1_o(RDATA_a_1),
.CLK2_i(clk_b_1),
.WEN2_i(WEN_b_1),
.REN2_i(REN_b_1),
.WR2_ADDR_i(WR_ADDR_b_1),
.RD2_ADDR_i(RD_ADDR_b_1),
.WDATA2_i(WDATA_b_1),
.RDATA2_o(RDATA_b_1)
);
endmodule
| 6.662554 |
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
initial
begin : init_block
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
`else
always @(WE or DI or DATAwr) begin : combo1
integer j;
// DATA = 0; // While this line is better coding sytle, it leads to incorrect synthsis for some tools
for(j = 0; j < WE_WIDTH; j = j + 1) begin
if (WE[j]) DATA[j*CHUNKSIZE +: CHUNKSIZE] = DI[j*CHUNKSIZE +: CHUNKSIZE];
else DATA[j*CHUNKSIZE +: CHUNKSIZE] = DATAwr[j*CHUNKSIZE +: CHUNKSIZE];
end
end
`endif // !`ifdef __ICARUS__
always @(posedge CLK) begin
if (EN) begin
if (|WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule
| 6.650974 |
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
initial
begin : init_block
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
`else
always @(WE or DI or DATAwr) begin : combo1
integer j;
// DATA = 0; // While this line is better coding sytle, it leads to incorrect synthsis for some tools
for(j = 0; j < WE_WIDTH; j = j + 1) begin
if (WE[j]) DATA[j*CHUNKSIZE +: CHUNKSIZE] = DI[j*CHUNKSIZE +: CHUNKSIZE];
else DATA[j*CHUNKSIZE +: CHUNKSIZE] = DATAwr[j*CHUNKSIZE +: CHUNKSIZE];
end
end
`endif // !`ifdef __ICARUS__
always @(posedge CLK) begin
if (EN) begin
if (|WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule
| 6.650974 |
module BRAM1BE(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input [WE_WIDTH-1:0] WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;
reg [DATA_WIDTH-1:0] DATA;
wire [DATA_WIDTH-1:0] DATAwr;
assign DATAwr = RAM[ADDR] ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
initial
begin : init_block
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASK, IMASK;
always @(WE or DI or DATAwr) begin : combo1
integer j;
MASK = 0;
IMASK = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WE[j]) MASK = (MASK << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASK = (MASK << 8);
end
IMASK = ~MASK;
DATA = (DATAwr & IMASK) | (DI & MASK);
end
`else
always @(WE or DI or DATAwr) begin : combo1
integer j;
// DATA = 0; // While this line is better coding sytle, it leads to incorrect synthsis for some tools
for(j = 0; j < WE_WIDTH; j = j + 1) begin
if (WE[j]) DATA[j*CHUNKSIZE +: CHUNKSIZE] = DI[j*CHUNKSIZE +: CHUNKSIZE];
else DATA[j*CHUNKSIZE +: CHUNKSIZE] = DATAwr[j*CHUNKSIZE +: CHUNKSIZE];
end
end
`endif // !`ifdef __ICARUS__
always @(posedge CLK) begin
if (EN) begin
if (|WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DATA;
DO_R <= `BSV_ASSIGNMENT_DELAY DATA;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end
// Output driver
assign DO = (PIPELINED) ? DO_R2 : DO_R;
endmodule
| 6.650974 |
module BRAM1Load(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter FILENAME = "";
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
parameter BINARY = 0;
input CLK;
input EN;
input WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;
// synopsys translate_off
initial
begin : init_block
`ifdef BSV_NO_INITIAL_BLOCKS
`else
integer i;
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
if (BINARY)
$readmemb(FILENAME, RAM, 0, MEMSIZE-1);
else
$readmemh(FILENAME, RAM, 0, MEMSIZE-1);
end
// synopsys translate_on
always @(posedge CLK) begin
if (EN) begin
if (WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
DO_R <= `BSV_ASSIGNMENT_DELAY DI;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end
// Output driver
assign DO = (PIPELINED) ? DO_R2 : DO_R;
endmodule
| 7.231042 |
module bram1w4r #(
parameter DATA_WIDTH = 32,
RAM_SIZE = 1024
) (
clk,
we,
waddr,
data_i,
raddr1,
data_o1,
raddr2,
data_o2,
raddr3,
data_o3,
raddr4,
data_o4
);
input clk, we;
input [31:0] waddr, raddr1, raddr2, raddr3, raddr4;
input [DATA_WIDTH-1 : 0] data_i;
output [DATA_WIDTH-1 : 0] data_o1, data_o2, data_o3, data_o4;
bram2p bram1 (
.clka(clk),
.wea(we),
.ena(1'b1),
.addra(waddr),
.data_ia(data_i),
.data_oa(),
.clkb(clk),
.web(1'b0),
.enb(1'b1),
.addrb(raddr1),
.data_ib(32'd0),
.data_ob(data_o1)
);
bram2p bram2 (
.clka(clk),
.wea(we),
.ena(1'b1),
.addra(waddr),
.data_ia(data_i),
.data_oa(),
.clkb(clk),
.web(1'b0),
.enb(1'b1),
.addrb(raddr2),
.data_ib(32'd0),
.data_ob(data_o2)
);
bram2p bram3 (
.clka(clk),
.wea(we),
.ena(1'b1),
.addra(waddr),
.data_ia(data_i),
.data_oa(),
.clkb(clk),
.web(1'b0),
.enb(1'b1),
.addrb(raddr3),
.data_ib(32'd0),
.data_ob(data_o3)
);
bram2p bram4 (
.clka(clk),
.wea(we),
.ena(1'b1),
.addra(waddr),
.data_ia(data_i),
.data_oa(),
.clkb(clk),
.web(1'b0),
.enb(1'b1),
.addrb(raddr4),
.data_ib(32'd0),
.data_ob(data_o4)
);
endmodule
| 6.705907 |
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLK) begin
if (EN) begin
if (WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule
| 7.357455 |
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [DATA_WIDTH-1:0] DO_R;
reg [DATA_WIDTH-1:0] DO_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DO_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLK) begin
if (EN) begin
if (WE) begin
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
DO_R <= `BSV_ASSIGNMENT_DELAY DI;
end
else begin
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR];
end
end
DO_R2 <= `BSV_ASSIGNMENT_DELAY DO_R;
end
// Output driver
assign DO = (PIPELINED) ? DO_R2 : DO_R;
endmodule
| 7.357455 |
module bram1_tb #(
parameter ABITS = 8,
DBITS = 8,
TRANSP = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
localparam [ABITS-1:0] INIT_ADDR_2 = 2 ** ABITS - 1;
localparam [ABITS-1:0] INIT_ADDR_3 = (2 ** ABITS - 1) / 2;
localparam [DBITS-1:0] INIT_DATA_0 = 128'h51e152a7300e309ccb8cd06d34558f49;
localparam [DBITS-1:0] INIT_DATA_1 = 128'h07b1fe94a530ddf3027520f9d23ab43e;
localparam [DBITS-1:0] INIT_DATA_2 = 128'h3cedc6de43ef3f607af3193658d0eb0b;
localparam [DBITS-1:0] INIT_DATA_3 = 128'hf6bc5514a8abf1e2810df966bcc13b46;
bram1 #(
// .ABITS(ABITS),
// .DBITS(DBITS),
// .TRANSP(TRANSP)
) uut (
.clk (clk),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN (WR_EN),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA)
);
reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16) ^ (TRANSP << 8);
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [ABITS-1:0] randaddr1;
reg [ABITS-1:0] randaddr2;
reg [ABITS-1:0] randaddr3;
function [31:0] getaddr(input [3:0] n);
begin
case (n)
0: getaddr = 0;
1: getaddr = 2 ** ABITS - 1;
2: getaddr = 'b101 << (ABITS / 3);
3: getaddr = 'b101 << (2 * ABITS / 3);
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2 * ABITS / 4);
6: getaddr = 'b11011 << (3 * ABITS / 4);
7: getaddr = randaddr1;
8: getaddr = randaddr2;
9: getaddr = randaddr3;
default: begin
getaddr = 1 << (2 * n - 16);
if (!getaddr) getaddr = xorshift64_state;
end
endcase
end
endfunction
reg [DBITS-1:0] memory[0:2**ABITS-1];
reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
reg error_ind = 0;
integer i, j;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram1_tb);
memory[INIT_ADDR_0] = INIT_DATA_0;
memory[INIT_ADDR_1] = INIT_DATA_1;
memory[INIT_ADDR_2] = INIT_DATA_2;
memory[INIT_ADDR_3] = INIT_DATA_3;
xorshift64_next;
xorshift64_next;
xorshift64_next;
xorshift64_next;
randaddr1 = xorshift64_state;
xorshift64_next;
randaddr2 = xorshift64_state;
xorshift64_next;
randaddr3 = xorshift64_state;
xorshift64_next;
clk <= 0;
for (i = 0; i < 512; i = i + 1) begin
if (i == 0) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_0;
end else if (i == 1) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_1;
end else if (i == 2) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_2;
end else if (i == 3) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_3;
end else begin
if (DBITS > 64) WR_DATA <= (xorshift64_state << (DBITS - 64)) ^ xorshift64_state;
else WR_DATA <= xorshift64_state;
xorshift64_next;
WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN <= xorshift64_state[55];
xorshift64_next;
end
#1;
clk <= 1;
#1;
clk <= 0;
if (TRANSP) begin
if (WR_EN) memory[WR_ADDR] = WR_DATA;
expected_rd = memory[RD_ADDR];
end else begin
expected_rd = memory[RD_ADDR];
if (WR_EN) memory[WR_ADDR] = WR_DATA;
end
for (j = 0; j < DBITS; j = j + 1)
expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN,
RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
if (expected_rd_masked !== RD_DATA) begin
->error;
error_ind = ~error_ind;
end
end
end
endmodule
| 7.32327 |
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule
| 6.804739 |
module BRAM2K (
input [11:0] addra,
input clka,
input [7:0] dina,
input ena,
input wea,
input clkb,
input enb,
input [11:0] addrb,
output reg [7:0] doutb
);
reg [7:0] BRAM8[2047:0];
initial #5 doutb <= 0;
always @(posedge clka) begin
if (ena & wea) BRAM8[addra] <= dina;
end
always @(posedge clkb) begin
doutb <= (enb) ? BRAM8[addrb] : 8'b0;
end
endmodule
| 7.551636 |
module BRAM2Load(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter FILENAME = "";
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
parameter BINARY = 0;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
(* RAM_STYLE = "BLOCK" *)
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
// synopsys translate_off
initial
begin : init_block
`ifdef BSV_NO_INITIAL_BLOCKS
`else
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
end
// synopsys translate_on
initial
begin : init_rom_block
if (BINARY)
$readmemb(FILENAME, RAM, 0, MEMSIZE-1);
else
$readmemh(FILENAME, RAM, 0, MEMSIZE-1);
end
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule
| 6.538112 |
module show you how to infer a two-port 1024x32 BRAM in
// your circuit using the standard Verilog code.
//
module bram2p
#(parameter DATA_WIDTH = 32, RAM_SIZE = 1024)
(clka, wea, ena, addra, data_ia, data_oa, // BRAM port A
clkb, web, enb, addrb, data_ib, data_ob); // BRAM port B
input clka, wea, ena;
input clkb, web, enb;
input [31:0] addra, addrb;
input [DATA_WIDTH-1 : 0] data_ia, data_ib;
output [DATA_WIDTH-1 : 0] data_oa, data_ob;
reg [DATA_WIDTH-1 : 0] data_oa, data_ob;
reg [DATA_WIDTH-1 : 0] RAM [RAM_SIZE - 1:0];
// ------------------------------------
// BRAM Port-A read operation
// ------------------------------------
always@(posedge clka)
begin
if (ena & wea)
data_oa <= data_ia;
else
data_oa <= RAM[addra];
end
// ------------------------------------
// BRAM Port-B read operation
// ------------------------------------
always@(posedge clkb)
begin
if (enb & web)
data_ob <= data_ib;
else
data_ob <= RAM[addrb];
end
// ------------------------------------
// BRAM Port-A write operation
// ------------------------------------
always@(posedge clka)
begin
if (ena & wea)
RAM[addra] <= data_ia;
end
// ------------------------------------
// BRAM Port-A write operation
// ------------------------------------
always@(posedge clkb)
begin
if (enb & web)
RAM[addrb] <= data_ib;
end
endmodule
| 6.896868 |
module bram2rgb (
//input wire [19:0] addr,
//input wire [7:0] cdata,
//input wire pclk,
input wire clk,
xrst,
en,
input wire [23:0] in_from_ram,
output reg [19:0] ram_addr = 0,
output reg vd_2s,
hd_2s,
output reg [23:0] rgb24bit = 0,
output reg den_2s = 0
);
reg [1:0] den_shift;
//output reg [19:0] ram_addr=0,
reg vd, hd;
//reg [23:0] rgb24bit=0;
reg den = 0;
//assign den_2s = den_shift[1];
// addr : 0 ~ xmax*ymax*3 -1
//Vact TtlLines Vblank VFreq HFreq PixeFreq Httl Hact Hblank
// 480 525 45 60.0 31.50 25.200 800 640 160
//VGA 640x480 800x525x60=25.2MHz
wire [15:0] hsync = 16'd96;
wire [15:0] hbp = 16'd48;
wire [15:0] hdata = 16'd640;
wire [15:0] hfp = 16'd16;
wire hsp = 1;
wire [15:0] vsync = 16'd2;
wire [15:0] vbp = 16'd33;
wire [15:0] vdata = 16'd480;
wire [15:0] vfp = 16'd10;
wire vsp = 1;
reg [2:0] ramaddr_sw = 0;
reg sw = 0;
reg [15:0] hcnt, vcnt;
reg [7:0] shift;
reg [17:0] ram_addr_ini = 0;
// wire xrst = !RST;
//wire ram_addrw = (vcnt - 35) * hdata + hcnt - 145; // ok.
reg vcnt_sw = 0;
reg hcnt_sw = 0;
always @(posedge clk or negedge xrst) begin //=
den_shift <= {den_shift[0], den};
if (!xrst) begin
hcnt <= 0;
vcnt <= 0;
shift <= 0;
rgb24bit <= 0;
den <= 0;
hd <= 0;
vd <= 0;
ram_addr <= 0;
end else if (en) begin
if (hcnt < hsync + hbp + hdata + hfp - 16'd1) begin // maybe hcnt:640~800. hsync
//hcnt_sw <= hcnt_sw + 1;
hcnt <= hcnt + 1'b1;
end else begin
hcnt <= 0;
if (vcnt < vsync + vbp + vdata + vfp - 16'd1) begin
//vcnt_sw <= vcnt_sw + 1;
vcnt <= vcnt + 1'b1;
end else begin
//ram_addr <= 0;
vcnt <= 0;
shift <= shift + 0; // stop to shifting
end
end
if (hcnt < hsync) hd <= hsp;
else hd <= !hsp; // synchronize signals
if (vcnt < vsync) vd <= vsp;
else vd <= !vsp;
if (vd) begin
ram_addr_ini <= 0;
ram_addr <= 0;
end
if (hcnt == hsync - 1 && vcnt >= vsync + vbp) begin
sw <= sw + 1'b1;
if (sw) begin
if (ram_addr_ini < 57600) ram_addr_ini <= ram_addr_ini + 320;
if (ram_addr < 57600) ram_addr <= ram_addr_ini;
end
end
if(hsync+hbp<=hcnt && hcnt<hsync+hbp+hdata && vsync+vbp<=vcnt && vcnt<vsync+vbp+vdata) begin// valid
den <= 1;
if (hsync + hbp <= hcnt && hcnt < hsync + hbp + 640 && vcnt < vsync + vbp + 360) begin
if (ram_addr < 57600) hcnt_sw <= hcnt_sw + 1'b1;
ram_addr <= ram_addr + hcnt_sw;
rgb24bit <= in_from_ram;
end else rgb24bit <= 24'h000000;
end else begin
den <= 0;
end
end
end //=
// reg [19:0] ram_addr_1s = 0;
// reg [19:0] ram_addr_2s = 0;
reg vd_1s = 0, hd_1s = 0;
reg [23:0] rgb24bit_1s = 0;
reg den_1s = 0;
always @(posedge clk) begin
vd_1s <= vd;
hd_1s <= hd;
vd_2s <= vd_1s;
hd_2s <= hd_1s;
//rgb24bit_1s<=rgb24bit;rgb24bit_2s<=rgb24bit_1s;
den_1s <= den;
den_2s <= den_1s;
end
endmodule
| 7.345716 |
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_D1_R;
reg [DATA_WIDTH-1:0] DOB_D1_R;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
end
end
end
always @(posedge CLKB) begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
end
end
end
// Pipeline
always @(posedge CLKA)
DOA_D1_R <= DOA_R;
always @(posedge CLKB)
DOB_D1_R <= DOB_R;
// Output drivers
assign DOA = (PIPELINED) ? DOA_D1_R : DOA_R;
assign DOB = (PIPELINED) ? DOB_D1_R : DOB_R;
endmodule
| 6.804739 |
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule
| 6.804739 |
module bram3 #(
parameter ADDR_WIDTH = 13 //width of addresses buses
) (
input CLK,
input [(ADDR_WIDTH-1):0] W_ADDR,
input [(ADDR_WIDTH-1):0] R_ADDR,
input WRITE_EN,
input READ_EN,
input [7:0] DIN,
output reg [7:0] DOUT
);
reg [7:0] mem[2**(ADDR_WIDTH-3):0];
integer idx;
initial begin
$readmemh("../../firmware/build/output/data0.txt", mem);
$dumpfile("PPCSoC_tb.vcd");
//for (idx = 4070; idx < 4095; idx = idx + 1) $dumpvars(0, mem[idx]);
$dumpvars(0, mem[200]);
end
always @(negedge CLK) begin
if (WRITE_EN) mem[W_ADDR[ADDR_WIDTH-1:2]] <= DIN;
if (READ_EN) DOUT <= mem[R_ADDR[ADDR_WIDTH-1:2]];
end
endmodule
| 6.753298 |
module bram32 #(
parameter init_file = "none",
parameter adr_width = 11
) (
input sys_clk,
input sys_rst,
input [31:0] do,
output reg [31:0] di,
input we,
input [15:0] a
);
//-----------------------------------------------------------------
// Storage depth in 32 bit words
//-----------------------------------------------------------------
parameter word_width = adr_width - 2;
parameter word_depth = (1 << word_width);
//-----------------------------------------------------------------
// Actual RAM
//-----------------------------------------------------------------
reg [31:0] ram [0:word_depth-1];
wire [word_width-1:0] adr;
always @(posedge sys_clk) begin
if (we) begin
ram[adr] <= do;
end
di <= ram[adr];
end
assign adr = a[adr_width-1:2];
//-----------------------------------------------------------------
// RAM initialization
//-----------------------------------------------------------------
initial
begin
if (init_file != "none")
begin
$readmemh(init_file, ram);
end
end
endmodule
| 7.815549 |
module BRAM32K_16 (
doa,
dia,
addra,
cea,
clka,
wea,
dob,
dib,
addrb,
ceb,
clkb,
web
);
output [15:0] doa;
output [15:0] dob;
input [15:0] dia;
input [15:0] dib;
input [11:0] addra;
input [11:0] addrb;
input [1:0] wea;
input [1:0] web;
input cea;
input ceb;
input clka;
input clkb;
EG_LOGIC_BRAM #(
.DATA_WIDTH_A(16),
.DATA_WIDTH_B(16),
.ADDR_WIDTH_A(12),
.ADDR_WIDTH_B(12),
.DATA_DEPTH_A(4096),
.DATA_DEPTH_B(4096),
.BYTE_ENABLE(8),
.BYTE_A(2),
.BYTE_B(2),
.MODE("DP"),
.REGMODE_A("NOREG"),
.REGMODE_B("NOREG"),
.WRITEMODE_A("NORMAL"),
.WRITEMODE_B("NORMAL"),
.RESETMODE("SYNC"),
.IMPLEMENT("32K"),
.INIT_FILE("NONE"),
.FILL_ALL("NONE")
) inst (
.dia (dia),
.dib (dib),
.addra(addra),
.addrb(addrb),
.cea (cea),
.ceb (ceb),
.ocea (1'b0),
.oceb (1'b0),
.clka (clka),
.clkb (clkb),
.wea (1'b0),
.bea (wea),
.web (1'b0),
.beb (web),
.rsta (1'b0),
.rstb (1'b0),
.doa (doa),
.dob (dob)
);
endmodule
| 6.590082 |
module af2048x18_2048x18 (
DIN,
PUSH,
POP,
clock0,
clock1,
Async_Flush,
Almost_Full,
Almost_Empty,
Full,
Empty,
Full_Watermark,
Empty_Watermark,
Overrun_Error,
Underrun_Error,
DOUT
);
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter UPAE_DBITS = 12'd10;
parameter UPAF_DBITS = 12'd10;
input clock0, clock1;
input PUSH, POP;
input [WR_DATA_WIDTH-1:0] DIN;
input Async_Flush;
output [RD_DATA_WIDTH-1:0] DOUT;
output Almost_Full, Almost_Empty;
output Full, Empty;
output Full_Watermark, Empty_Watermark;
output Overrun_Error, Underrun_Error;
AFIFO_36K_BLK #(
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS(UPAE_DBITS),
.UPAF_DBITS(UPAF_DBITS)
) FIFO_INST (
.DIN(DIN),
.PUSH(PUSH),
.POP(POP),
.Push_Clk(clock0),
.Pop_Clk(clock1),
.Async_Flush(Async_Flush),
.Overrun_Error(Overrun_Error),
.Full_Watermark(Full_Watermark),
.Almost_Full(Almost_Full),
.Full(Full),
.Underrun_Error(Underrun_Error),
.Empty_Watermark(Empty_Watermark),
.Almost_Empty(Almost_Empty),
.Empty(Empty),
.DOUT(DOUT)
);
endmodule
| 6.743763 |
module af4096x9_4096x9 (
DIN,
PUSH,
POP,
clock0,
clock1,
Async_Flush,
Almost_Full,
Almost_Empty,
Full,
Empty,
Full_Watermark,
Empty_Watermark,
Overrun_Error,
Underrun_Error,
DOUT
);
parameter WR_DATA_WIDTH = 9;
parameter RD_DATA_WIDTH = 9;
parameter UPAE_DBITS = 12'd10;
parameter UPAF_DBITS = 12'd10;
input clock0, clock1;
input PUSH, POP;
input [WR_DATA_WIDTH-1:0] DIN;
input Async_Flush;
output [RD_DATA_WIDTH-1:0] DOUT;
output Almost_Full, Almost_Empty;
output Full, Empty;
output Full_Watermark, Empty_Watermark;
output Overrun_Error, Underrun_Error;
AFIFO_36K_BLK #(
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS(UPAE_DBITS),
.UPAF_DBITS(UPAF_DBITS)
) FIFO_INST (
.DIN(DIN),
.PUSH(PUSH),
.POP(POP),
.Push_Clk(clock0),
.Pop_Clk(clock1),
.Async_Flush(Async_Flush),
.Overrun_Error(Overrun_Error),
.Full_Watermark(Full_Watermark),
.Almost_Full(Almost_Full),
.Full(Full),
.Underrun_Error(Underrun_Error),
.Empty_Watermark(Empty_Watermark),
.Almost_Empty(Almost_Empty),
.Empty(Empty),
.DOUT(DOUT)
);
endmodule
| 6.606759 |
module TB;
localparam PERIOD = 30;
localparam ADDR_INCR = 1;
reg clk0;
reg clk1;
reg flush;
reg pop;
wire [`DATA_WIDTH1-1:0] dout;
reg push;
reg [`DATA_WIDTH0-1:0] din;
wire almost_full, almost_empty;
wire full, empty;
wire full_watermark, empty_watermark;
wire overrun_error, underrun_error;
initial begin
clk0 = 0;
clk1 = 0;
pop = 0;
push = 0;
flush = 1;
din = 0;
#40 flush = 0;
end
initial forever #(PERIOD / 3.0) clk0 = ~clk0;
initial forever #(PERIOD / 2.0) clk1 = ~clk1;
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
reg done;
initial done = 1'b0;
reg read_test;
initial read_test = 0;
reg [`DATA_WIDTH1-1:0] expected;
initial expected = 0;
always @(posedge clk1) begin
expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
end
wire error = ((a != 0) && read_test) ? dout !== expected : 0;
integer error_cnt = 0;
always @(posedge clk1) begin
if (error) error_cnt <= error_cnt + 1'b1;
end
initial
#(50) begin
@(posedge clk0)
// Write data
for (
a = 0; a < (1 << `ADDR_WIDTH0); a = a + ADDR_INCR
) begin
@(negedge clk0) begin
din = a | (a << 20) | 20'h55000;
push = 1;
end
@(posedge clk0) begin
#(PERIOD / 10) push = 0;
end
end
// Read data
read_test = 1;
for (a = 0; a < (1 << `ADDR_WIDTH1); a = a + ADDR_INCR) begin
@(posedge clk1) begin
#(PERIOD / 10) pop = 0;
if (dout !== expected) begin
$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
end else begin
$display("%d: OK: act=%x exp=%x at %x", $time, dout, expected, a);
end
end
@(negedge clk1) begin
pop = 1;
end
end
done = 1'b1;
end
// Scan for simulation finish
always @(posedge clk1) begin
if (done) $finish_and_return((error_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"af1024x36_1024x36": begin
af1024x36_1024x36 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk0),
.clock1(clk1),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"af2048x18_2048x18": begin
af2048x18_2048x18 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk0),
.clock1(clk1),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"af4096x9_4096x9": begin
af4096x9_4096x9 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk0),
.clock1(clk1),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
endcase
endmodule
| 7.277485 |
module spram_36x1024 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 36;
parameter RD_DATA_WIDTH = 36;
parameter BE_WIDTH = 4;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(4'b1111),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.683816 |
module spram_32x1024 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 32;
parameter RD_DATA_WIDTH = 32;
parameter BE_WIDTH = 4;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(4'b1111),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.91401 |
module spram_18x2048 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 11;
parameter RD_ADDR_WIDTH = 11;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(2'b11),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.524103 |
module spram_16x2048 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 11;
parameter RD_ADDR_WIDTH = 11;
parameter WR_DATA_WIDTH = 16;
parameter RD_DATA_WIDTH = 16;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(2'b11),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.696585 |
module spram_9x4096 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 12;
parameter RD_ADDR_WIDTH = 12;
parameter WR_DATA_WIDTH = 9;
parameter RD_DATA_WIDTH = 9;
parameter BE_WIDTH = 1;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(1'b1),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.700121 |
module spram_8x4096 (
WEN_i,
REN_i,
clock0,
clock1,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 12;
parameter RD_ADDR_WIDTH = 12;
parameter WR_DATA_WIDTH = 8;
parameter RD_DATA_WIDTH = 8;
parameter BE_WIDTH = 1;
input wire WEN_i;
input wire REN_i;
input wire clock0;
input wire clock1;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
RAM_36K_BLK #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE_WIDTH(BE_WIDTH)
) spram_x36_inst (
.WEN_i(WEN_i),
.WR_BE_i(1'b1),
.REN_i(REN_i),
.WR_CLK_i(clock0),
.RD_CLK_i(clock1),
.WR_ADDR_i(WR_ADDR_i),
.RD_ADDR_i(RD_ADDR_i),
.WDATA_i(WDATA_i),
.RDATA_o(RDATA_o)
);
endmodule
| 6.803316 |
module TB;
localparam PERIOD = 50;
localparam ADDR_INCR = 1;
reg clk;
reg rce;
reg [`ADDR_WIDTH-1:0] ra;
wire [`DATA_WIDTH-1:0] rq;
reg wce;
reg [`ADDR_WIDTH-1:0] wa;
reg [`DATA_WIDTH-1:0] wd;
initial clk = 0;
initial ra = 0;
initial rce = 0;
initial forever #(PERIOD / 2.0) clk = ~clk;
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
reg done;
initial done = 1'b0;
reg [`DATA_WIDTH-1:0] expected;
always @(posedge clk) begin
expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH{1'b1}};
end
wire error = ((a != 0) && read_test) ? rq !== expected : 0;
integer error_cnt = 0;
always @(posedge clk) begin
if (error) error_cnt <= error_cnt + 1'b1;
end
reg read_test;
initial read_test = 0;
initial
#(1) begin
// Write data
for (a = 0; a < (1 << `ADDR_WIDTH); a = a + ADDR_INCR) begin
@(negedge clk) begin
wa = a;
wd = a | (a << 20) | 20'h55000;
wce = 1;
end
@(posedge clk) begin
#(PERIOD / 10) wce = 0;
end
end
// Read data
read_test = 1;
for (a = 0; a < (1 << `ADDR_WIDTH); a = a + ADDR_INCR) begin
@(negedge clk) begin
ra = a;
rce = 1;
end
@(posedge clk) begin
#(PERIOD / 10) rce = 0;
if (rq !== expected) begin
$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, rq, expected, a);
end else begin
$display("%d: OK: act=%x exp=%x at %x", $time, rq, expected, a);
end
end
end
done = 1'b1;
end
// Scan for simulation finish
always @(posedge clk) begin
if (done) $finish_and_return((error_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"spram_36x1024": begin
spram_36x1024 #() bram (
.clock0(clk),
.clock1(clk),
.REN_i(rce),
.RD_ADDR_i(ra),
.RDATA_o(rq),
.WEN_i(wce),
.WR_ADDR_i(wa),
.WDATA_i(wd)
);
end
"spram_32x1024": begin
spram_32x1024 #() bram (
.clock0(clk),
.clock1(clk),
.REN_i(rce),
.RD_ADDR_i(ra),
.RDATA_o(rq),
.WEN_i(wce),
.WR_ADDR_i(wa),
.WDATA_i(wd)
);
end
"spram_18x2048": begin
spram_18x2048 #() bram (
.clock0(clk),
.clock1(clk),
.REN_i(rce),
.RD_ADDR_i(ra),
.RDATA_o(rq),
.WEN_i(wce),
.WR_ADDR_i(wa),
.WDATA_i(wd)
);
end
"spram_16x2048": begin
spram_16x2048 #() bram (
.clock0(clk),
.clock1(clk),
.REN_i(rce),
.RD_ADDR_i(ra),
.RDATA_o(rq),
.WEN_i(wce),
.WR_ADDR_i(wa),
.WDATA_i(wd)
);
end
"spram_9x4096": begin
spram_9x4096 #() bram (
.clock0(clk),
.clock1(clk),
.REN_i(rce),
.RD_ADDR_i(ra),
.RDATA_o(rq),
.WEN_i(wce),
.WR_ADDR_i(wa),
.WDATA_i(wd)
);
end
"spram_8x4096": begin
spram_8x4096 #() bram (
.clock0(clk),
.clock1(clk),
.REN_i(rce),
.RD_ADDR_i(ra),
.RDATA_o(rq),
.WEN_i(wce),
.WR_ADDR_i(wa),
.WDATA_i(wd)
);
end
endcase
endmodule
| 7.277485 |
module TB;
localparam PERIOD = 30;
localparam ADDR_INCR = 1;
reg clk;
reg flush;
reg pop;
wire [`DATA_WIDTH1-1:0] dout;
reg push;
reg [`DATA_WIDTH0-1:0] din;
wire almost_full, almost_empty;
wire full, empty;
wire full_watermark, empty_watermark;
wire overrun_error, underrun_error;
initial begin
clk = 0;
pop = 0;
push = 0;
flush = 1;
din = 0;
#40 flush = 0;
end
initial forever #(PERIOD / 3.0) clk = ~clk;
initial begin
$dumpfile(`STRINGIFY(`VCD));
$dumpvars;
end
integer a;
reg done;
initial done = 1'b0;
reg read_test;
initial read_test = 0;
reg [`DATA_WIDTH1-1:0] expected;
initial expected = 0;
always @(posedge clk) begin
expected <= (a | (a << 20) | 20'h55000) & {`DATA_WIDTH1{1'b1}};
end
wire error = ((a != 0) && read_test) ? dout !== expected : 0;
integer error_cnt = 0;
always @(posedge clk) begin
if (error) error_cnt <= error_cnt + 1'b1;
end
initial
#(50) begin
@(posedge clk)
// Write data
for (
a = 0; a < (1 << `ADDR_WIDTH0); a = a + ADDR_INCR
) begin
@(negedge clk) begin
din = a | (a << 20) | 20'h55000;
push = 1;
end
@(posedge clk) begin
#(PERIOD / 10) push = 0;
end
end
// Read data
read_test = 1;
for (a = 0; a < (1 << `ADDR_WIDTH1); a = a + ADDR_INCR) begin
@(posedge clk) begin
#(PERIOD / 10) pop = 0;
if (dout !== expected) begin
$display("%d: FAIL: mismatch act=%x exp=%x at %x", $time, dout, expected, a);
end else begin
$display("%d: OK: act=%x exp=%x at %x", $time, dout, expected, a);
end
end
@(negedge clk) begin
pop = 1;
end
end
done = 1'b1;
end
// Scan for simulation finish
always @(posedge clk) begin
if (done) $finish_and_return((error_cnt == 0) ? 0 : -1);
end
case (
`STRINGIFY(`TOP)
)
"f1024x36_1024x36": begin
f1024x36_1024x36 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"f2048x18_2048x18": begin
f2048x18_2048x18 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
"f4096x9_4096x9": begin
f4096x9_4096x9 #() afifo (
.DIN(din),
.PUSH(push),
.POP(pop),
.clock0(clk),
.Async_Flush(flush),
.Almost_Full(almost_full),
.Almost_Empty(almost_empty),
.Full(full),
.Empty(empty),
.Full_Watermark(full_watermark),
.Empty_Watermark(empty_watermark),
.Overrun_Error(overrun_error),
.Underrun_Error(underrun_error),
.DOUT(dout)
);
end
endcase
endmodule
| 7.277485 |
module dpram_36x1024 (
clock0,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
clock1,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 36;
parameter BE1_WIDTH = 4;
parameter BE2_WIDTH = 4;
input wire clock0;
input wire WEN1_i;
input wire REN1_i;
input wire [ADDR_WIDTH-1 : 0] WR1_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD1_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA1_i;
output wire [DATA_WIDTH-1 : 0] RDATA1_o;
input wire clock1;
input wire WEN2_i;
input wire REN2_i;
input wire [ADDR_WIDTH-1 : 0] WR2_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD2_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA2_i;
output wire [DATA_WIDTH-1 : 0] RDATA2_o;
DPRAM_36K_BLK #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.BE1_WIDTH (BE1_WIDTH),
.BE2_WIDTH (BE2_WIDTH)
) dpram_x36_inst (
.CLK1_i(clock0),
.WEN1_i(WEN1_i),
.WR1_BE_i(4'b1111),
.REN1_i(REN1_i),
.WR1_ADDR_i(WR1_ADDR_i),
.RD1_ADDR_i(RD1_ADDR_i),
.WDATA1_i(WDATA1_i),
.RDATA1_o(RDATA1_o),
.CLK2_i(clock1),
.WEN2_i(WEN2_i),
.WR2_BE_i(4'b1111),
.REN2_i(REN2_i),
.WR2_ADDR_i(WR2_ADDR_i),
.RD2_ADDR_i(RD2_ADDR_i),
.WDATA2_i(WDATA2_i),
.RDATA2_o(RDATA2_o)
);
endmodule
| 6.801704 |
module dpram_18x2048 (
clock0,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
clock1,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 11;
parameter DATA_WIDTH = 18;
parameter BE1_WIDTH = 2;
parameter BE2_WIDTH = 2;
input wire clock0;
input wire WEN1_i;
input wire REN1_i;
input wire [ADDR_WIDTH-1 : 0] WR1_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD1_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA1_i;
output wire [DATA_WIDTH-1 : 0] RDATA1_o;
input wire clock1;
input wire WEN2_i;
input wire REN2_i;
input wire [ADDR_WIDTH-1 : 0] WR2_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD2_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA2_i;
output wire [DATA_WIDTH-1 : 0] RDATA2_o;
DPRAM_36K_BLK #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.BE1_WIDTH (BE1_WIDTH),
.BE2_WIDTH (BE2_WIDTH)
) dpram_x36_inst (
.CLK1_i(clock0),
.WEN1_i(WEN1_i),
.WR1_BE_i(2'b11),
.REN1_i(REN1_i),
.WR1_ADDR_i(WR1_ADDR_i),
.RD1_ADDR_i(RD1_ADDR_i),
.WDATA1_i(WDATA1_i),
.RDATA1_o(RDATA1_o),
.CLK2_i(clock1),
.WEN2_i(WEN2_i),
.WR2_BE_i(2'b11),
.REN2_i(REN2_i),
.WR2_ADDR_i(WR2_ADDR_i),
.RD2_ADDR_i(RD2_ADDR_i),
.WDATA2_i(WDATA2_i),
.RDATA2_o(RDATA2_o)
);
endmodule
| 6.602544 |
module dpram_9x4096 (
clock0,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
clock1,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 12;
parameter DATA_WIDTH = 9;
parameter BE1_WIDTH = 1;
parameter BE2_WIDTH = 1;
input wire clock0;
input wire WEN1_i;
input wire REN1_i;
input wire [ADDR_WIDTH-1 : 0] WR1_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD1_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA1_i;
output wire [DATA_WIDTH-1 : 0] RDATA1_o;
input wire clock1;
input wire WEN2_i;
input wire REN2_i;
input wire [ADDR_WIDTH-1 : 0] WR2_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD2_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA2_i;
output wire [DATA_WIDTH-1 : 0] RDATA2_o;
DPRAM_36K_BLK #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.BE1_WIDTH (BE1_WIDTH),
.BE2_WIDTH (BE2_WIDTH)
) dpram_x36_inst (
.CLK1_i(clock0),
.WEN1_i(WEN1_i),
.WR1_BE_i(1'b1),
.REN1_i(REN1_i),
.WR1_ADDR_i(WR1_ADDR_i),
.RD1_ADDR_i(RD1_ADDR_i),
.WDATA1_i(WDATA1_i),
.RDATA1_o(RDATA1_o),
.CLK2_i(clock1),
.WEN2_i(WEN2_i),
.WR2_BE_i(1'b1),
.REN2_i(REN2_i),
.WR2_ADDR_i(WR2_ADDR_i),
.RD2_ADDR_i(RD2_ADDR_i),
.WDATA2_i(WDATA2_i),
.RDATA2_o(RDATA2_o)
);
endmodule
| 7.1368 |
module BRAM4k8bit (
CLK,
ADDR,
WE,
EN,
DIN,
DOUT
);
input CLK;
input WE;
input EN;
input [11:0] ADDR;
input [7:0] DIN;
output reg [7:0] DOUT;
reg [7:0] mem[4095:0];
always @(posedge CLK) begin
if (EN) begin
if (WE) begin
mem[ADDR] <= DIN;
end
DOUT <= mem[ADDR];
end
end
endmodule
| 6.616116 |
module bram64x256 (
input clk,
input wr,
input [7:0] adr,
input [63:0] din,
output [63:0] dout
);
reg [63:0] ram[255:0];
reg [63:0] rDout;
assign dout = rDout;
always @(posedge clk) begin
if (wr) ram[adr] <= din;
rDout <= ram[adr];
end
endmodule
| 7.235974 |
module BRAM6k9bit (
CLK,
ADDR,
WE,
EN,
DIN,
DINP,
DOUT,
DOUTP
);
input CLK;
input WE;
input EN;
input [12:0] ADDR;
input [7:0] DIN;
input DINP;
output [7:0] DOUT;
output DOUTP;
wire [7:0] ram0_DOUT, ram1_DOUT, ram2_DOUT;
wire ram0_DOUTP, ram1_DOUTP, ram2_DOUTP;
reg [3:0] ram_EN;
always @* begin
#1;
ram_EN = 0;
ram_EN[ADDR[12:11]] = EN;
end
//
// Output mux...
//
reg [1:0] dly_ADDR, next_dly_ADDR;
always @(posedge CLK) begin
dly_ADDR = next_dly_ADDR;
end
always @* begin
#1;
next_dly_ADDR = ADDR[12:11];
end
reg [7:0] DOUT;
reg DOUTP;
always @* begin
#1;
DOUT = 8'h0;
DOUTP = 1'b0;
case (dly_ADDR)
2'h0: begin
DOUT = ram0_DOUT;
DOUTP = ram0_DOUTP;
end
2'h1: begin
DOUT = ram1_DOUT;
DOUTP = ram1_DOUTP;
end
2'h2: begin
DOUT = ram2_DOUT;
DOUTP = ram2_DOUTP;
end
endcase
end
//
// Instantiate the 2Kx8 RAM's...
//
RAMB16_S9 ram0 (
.CLK (CLK),
.ADDR(ADDR[10:0]),
.DI (DIN),
.DIP (DINP),
.DO (ram0_DOUT),
.DOP (ram0_DOUTP),
.EN (ram_EN[0]),
.SSR (1'b0),
.WE (WE)
);
RAMB16_S9 ram1 (
.CLK (CLK),
.ADDR(ADDR[10:0]),
.DI (DIN),
.DIP (DINP),
.DO (ram1_DOUT),
.DOP (ram1_DOUTP),
.EN (ram_EN[1]),
.SSR (1'b0),
.WE (WE)
);
RAMB16_S9 ram2 (
.CLK (CLK),
.ADDR(ADDR[10:0]),
.DI (DIN),
.DIP (DINP),
.DO (ram2_DOUT),
.DOP (ram2_DOUTP),
.EN (ram_EN[2]),
.SSR (1'b0),
.WE (WE)
);
endmodule
| 6.598609 |
module BRam8x512x512 (
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0:0] wea;
input [17:0] addra;
input [7:0] dina;
input clkb;
input [17:0] addrb;
output reg [7:0] doutb;
reg [7 : 0] mem[0 : 2 ** 18 - 1];
always @(posedge clka) begin
if (wea) mem[addra] <= dina;
else mem[addra] <= mem[addra];
end
always @(posedge clkb) doutb <= mem[addrb];
endmodule
| 6.795288 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 (1'b0),
.sel(reset),
.o (resetout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(resetout),
.reset(1'b0),
.set(set),
.q(q)
);
endmodule
| 7.286889 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
tri0 gsrn = glbl.gsrn;
always @(gsrn) begin
if (!gsrn) assign q = INI;
else deassign q;
end
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module RAM256X8 (
B1ADDR,
B1DATA,
CLK3,
A1ADDR,
A1DATA,
A1EN,
CLK2
);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter TRANSP3 = 1;
input CLK2;
input CLK3;
input [7:0] A1ADDR;
input [7:0] A1DATA;
input A1EN;
input [7:0] B1ADDR;
output [7:0] B1DATA;
wire c2 = CLK2 == CLKPOL2;
wire c3 = CLK3 == CLKPOL3;
reg [7:0] memory[0:255];
reg [7:0] b1_buffer;
always @(posedge c2) if (A1EN) memory[A1ADDR] <= A1DATA;
always @(posedge c3) b1_buffer <= TRANSP3 ? B1ADDR : memory[B1ADDR];
assign B1DATA = TRANSP3 ? memory[b1_buffer] : b1_buffer;
endmodule
| 6.860788 |
module ramtb ();
reg clk;
reg rst;
reg tx;
// output port
wire wr_en_1; // enable BRAM1
wire [31:0] wr_add_1; // address of BRAM1
wire [31:0] wr_data_1; // write data
wire wr_en_2; // enable BRAM2
wire [31:0] wr_add_2; // write address BRAM2
wire [31:0] wr_data_2; // write data on BRAM2
counter uut (
clk,
rst,
tx,
wr_en_1,
wr_add_1,
wr_data_1,
wr_en_2,
wr_add_2,
wr_data_2
);
// input port
initial begin
clk = 0;
rst = 1;
tx = 0;
#10 rst = 0;
#30 tx = 1;
#10 tx = 0;
#115 tx = 1;
#10 tx = 0;
end
always begin
#5 clk = !clk;
end
endmodule
| 6.767128 |
module AFIFO_18K_BLK (
DIN,
PUSH,
POP,
Push_Clk,
Pop_Clk,
Async_Flush,
Overrun_Error,
Full_Watermark,
Almost_Full,
Full,
Underrun_Error,
Empty_Watermark,
Almost_Empty,
Empty,
DOUT
);
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter UPAE_DBITS = 11'd10;
parameter UPAF_DBITS = 11'd10;
input wire Push_Clk, Pop_Clk;
input wire PUSH, POP;
input wire [WR_DATA_WIDTH-1:0] DIN;
input wire Async_Flush;
output wire [RD_DATA_WIDTH-1:0] DOUT;
output wire Almost_Full, Almost_Empty;
output wire Full, Empty;
output wire Full_Watermark, Empty_Watermark;
output wire Overrun_Error, Underrun_Error;
BRAM2x18_AFIFO #(
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS1 (UPAE_DBITS),
.UPAF_DBITS1 (UPAF_DBITS),
.UPAE_DBITS2 (),
.UPAF_DBITS2 ()
) U1 (
.DIN1(DIN),
.PUSH1(PUSH),
.POP1(POP),
.Push_Clk1(Push_Clk),
.Pop_Clk1(Pop_Clk),
.Async_Flush1(Async_Flush),
.Overrun_Error1(Overrun_Error),
.Full_Watermark1(Full_Watermark),
.Almost_Full1(Almost_Full),
.Full1(Full),
.Underrun_Error1(Underrun_Error),
.Empty_Watermark1(Empty_Watermark),
.Almost_Empty1(Almost_Empty),
.Empty1(Empty),
.DOUT1(DOUT),
.DIN2(),
.PUSH2(),
.POP2(),
.Push_Clk2(),
.Pop_Clk2(),
.Async_Flush2(),
.Overrun_Error2(),
.Full_Watermark2(),
.Almost_Full2(),
.Full2(),
.Underrun_Error2(),
.Empty_Watermark2(),
.Almost_Empty2(),
.Empty2(),
.DOUT2()
);
endmodule
| 6.825329 |
module RAM_18K_BLK (
WEN_i,
REN_i,
WR_CLK_i,
RD_CLK_i,
WR_BE_i,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wire REN_i;
input wire WR_CLK_i;
input wire RD_CLK_i;
input wire [BE_WIDTH-1:0] WR_BE_i;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
BRAM2x18_SP #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE1_WIDTH(BE_WIDTH),
.BE2_WIDTH()
) U1 (
.RESET_ni(1'b1),
.WEN1_i(WEN_i),
.REN1_i(REN_i),
.WR1_CLK_i(WR_CLK_i),
.RD1_CLK_i(RD_CLK_i),
.WR1_BE_i(WR_BE_i),
.WR1_ADDR_i(WR_ADDR_i),
.RD1_ADDR_i(RD_ADDR_i),
.WDATA1_i(WDATA_i),
.RDATA1_o(RDATA_o),
.WEN2_i(),
.REN2_i(),
.WR2_CLK_i(),
.RD2_CLK_i(),
.WR2_BE_i(),
.WR2_ADDR_i(),
.RD2_ADDR_i(),
.WDATA2_i(),
.RDATA2_o()
);
endmodule
| 6.833245 |
module DPRAM_18K_BLK (
CLK1_i,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
CLK2_i,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 18;
parameter BE1_WIDTH = 2;
parameter BE2_WIDTH = 2;
input wire CLK1_i;
input wire WEN1_i;
input wire REN1_i;
input wire [ADDR_WIDTH-1 : 0] WR1_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD1_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA1_i;
output wire [DATA_WIDTH-1 : 0] RDATA1_o;
input wire CLK2_i;
input wire WEN2_i;
input wire REN2_i;
input wire [ADDR_WIDTH-1 : 0] WR2_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD2_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA2_i;
output wire [DATA_WIDTH-1 : 0] RDATA2_o;
(* is_inferred = 1 *)
BRAM2x18_DP #(
.CFG_ABITS(ADDR_WIDTH),
.CFG_DBITS(DATA_WIDTH),
.CFG_ENABLE_B(BE1_WIDTH),
.CFG_ENABLE_D(BE2_WIDTH)
) bram2x18_inst (
.A1ADDR(RD1_ADDR_i),
.A1DATA(RDATA1_o),
.A1EN (REN1_i),
.B1ADDR(WR1_ADDR_i),
.B1DATA(WDATA1_i),
.B1EN ({WEN1_i, WEN1_i}),
.CLK1 (CLK1_i),
.C1ADDR(RD2_ADDR_i),
.C1DATA(RDATA2_o),
.C1EN (REN2_i),
.D1ADDR(WR2_ADDR_i),
.D1DATA(WDATA2_i),
.D1EN ({WEN2_i, WEN2_i}),
.CLK2 (CLK2_i),
.E1ADDR(),
.E1DATA(),
.E1EN (),
.F1ADDR(),
.F1DATA(),
.F1EN (),
.CLK3 (),
.G1ADDR(),
.G1DATA(),
.G1EN (),
.H1ADDR(),
.H1DATA(),
.H1EN (),
.CLK4 ()
);
endmodule
| 6.841924 |
module RAM_18K_BLK (
WEN_i,
REN_i,
WR_CLK_i,
RD_CLK_i,
WR_BE_i,
WR_ADDR_i,
RD_ADDR_i,
WDATA_i,
RDATA_o
);
parameter WR_ADDR_WIDTH = 10;
parameter RD_ADDR_WIDTH = 10;
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter BE_WIDTH = 2;
input wire WEN_i;
input wire REN_i;
input wire WR_CLK_i;
input wire RD_CLK_i;
input wire [BE_WIDTH-1:0] WR_BE_i;
input wire [WR_ADDR_WIDTH-1 : 0] WR_ADDR_i;
input wire [RD_ADDR_WIDTH-1 : 0] RD_ADDR_i;
input wire [WR_DATA_WIDTH-1 : 0] WDATA_i;
output wire [RD_DATA_WIDTH-1 : 0] RDATA_o;
BRAM2x18_SP #(
.WR_ADDR_WIDTH(WR_ADDR_WIDTH),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.BE1_WIDTH(BE_WIDTH),
.BE2_WIDTH()
) U1 (
.RESET_ni(1'b1),
.WEN1_i(WEN_i),
.REN1_i(REN_i),
.WR1_CLK_i(WR_CLK_i),
.RD1_CLK_i(RD_CLK_i),
.WR1_BE_i(WR_BE_i),
.WR1_ADDR_i(WR_ADDR_i),
.RD1_ADDR_i(RD_ADDR_i),
.WDATA1_i(WDATA_i),
.RDATA1_o(RDATA_o),
.WEN2_i(),
.REN2_i(),
.WR2_CLK_i(),
.RD2_CLK_i(),
.WR2_BE_i(),
.WR2_ADDR_i(),
.RD2_ADDR_i(),
.WDATA2_i(),
.RDATA2_o()
);
endmodule
| 6.833245 |
module DPRAM_18K_BLK (
CLK1_i,
WEN1_i,
REN1_i,
WR1_ADDR_i,
RD1_ADDR_i,
WDATA1_i,
RDATA1_o,
CLK2_i,
WEN2_i,
REN2_i,
WR2_ADDR_i,
RD2_ADDR_i,
WDATA2_i,
RDATA2_o
);
parameter ADDR_WIDTH = 10;
parameter DATA_WIDTH = 18;
parameter BE1_WIDTH = 2;
parameter BE2_WIDTH = 2;
input wire CLK1_i;
input wire WEN1_i;
input wire REN1_i;
input wire [ADDR_WIDTH-1 : 0] WR1_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD1_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA1_i;
output wire [DATA_WIDTH-1 : 0] RDATA1_o;
input wire CLK2_i;
input wire WEN2_i;
input wire REN2_i;
input wire [ADDR_WIDTH-1 : 0] WR2_ADDR_i;
input wire [ADDR_WIDTH-1 : 0] RD2_ADDR_i;
input wire [DATA_WIDTH-1 : 0] WDATA2_i;
output wire [DATA_WIDTH-1 : 0] RDATA2_o;
(* is_inferred = 1 *)
BRAM2x18_DP #(
.CFG_ABITS(ADDR_WIDTH),
.CFG_DBITS(DATA_WIDTH),
.CFG_ENABLE_B(BE1_WIDTH),
.CFG_ENABLE_D(BE2_WIDTH)
) bram2x18_inst (
.A1ADDR(RD1_ADDR_i),
.A1DATA(RDATA1_o),
.A1EN (REN1_i),
.B1ADDR(WR1_ADDR_i),
.B1DATA(WDATA1_i),
.B1EN ({WEN1_i, WEN1_i}),
.CLK1 (CLK1_i),
.C1ADDR(RD2_ADDR_i),
.C1DATA(RDATA2_o),
.C1EN (REN2_i),
.D1ADDR(WR2_ADDR_i),
.D1DATA(WDATA2_i),
.D1EN ({WEN2_i, WEN2_i}),
.CLK2 (CLK2_i),
.E1ADDR(),
.E1DATA(),
.E1EN (),
.F1ADDR(),
.F1DATA(),
.F1EN (),
.CLK3 (),
.G1ADDR(),
.G1DATA(),
.G1EN (),
.H1ADDR(),
.H1DATA(),
.H1EN (),
.CLK4 ()
);
endmodule
| 6.841924 |
module AFIFO_18K_BLK (
DIN,
PUSH,
POP,
Push_Clk,
Pop_Clk,
Async_Flush,
Overrun_Error,
Full_Watermark,
Almost_Full,
Full,
Underrun_Error,
Empty_Watermark,
Almost_Empty,
Empty,
DOUT
);
parameter WR_DATA_WIDTH = 18;
parameter RD_DATA_WIDTH = 18;
parameter UPAE_DBITS = 11'd10;
parameter UPAF_DBITS = 11'd10;
input wire Push_Clk, Pop_Clk;
input wire PUSH, POP;
input wire [WR_DATA_WIDTH-1:0] DIN;
input wire Async_Flush;
output wire [RD_DATA_WIDTH-1:0] DOUT;
output wire Almost_Full, Almost_Empty;
output wire Full, Empty;
output wire Full_Watermark, Empty_Watermark;
output wire Overrun_Error, Underrun_Error;
BRAM2x18_AFIFO #(
.WR_DATA_WIDTH(WR_DATA_WIDTH),
.RD_DATA_WIDTH(RD_DATA_WIDTH),
.UPAE_DBITS1 (UPAE_DBITS),
.UPAF_DBITS1 (UPAF_DBITS),
.UPAE_DBITS2 (),
.UPAF_DBITS2 ()
) U1 (
.DIN1(DIN),
.PUSH1(PUSH),
.POP1(POP),
.Push_Clk1(Push_Clk),
.Pop_Clk1(Pop_Clk),
.Async_Flush1(Async_Flush),
.Overrun_Error1(Overrun_Error),
.Full_Watermark1(Full_Watermark),
.Almost_Full1(Almost_Full),
.Full1(Full),
.Underrun_Error1(Underrun_Error),
.Empty_Watermark1(Empty_Watermark),
.Almost_Empty1(Almost_Empty),
.Empty1(Empty),
.DOUT1(DOUT),
.DIN2(),
.PUSH2(),
.POP2(),
.Push_Clk2(),
.Pop_Clk2(),
.Async_Flush2(),
.Overrun_Error2(),
.Full_Watermark2(),
.Almost_Full2(),
.Full2(),
.Underrun_Error2(),
.Empty_Watermark2(),
.Almost_Empty2(),
.Empty2(),
.DOUT2()
);
endmodule
| 6.825329 |
module BRAM_12 (
BRAM_PORTA_addr,
BRAM_PORTA_clk,
BRAM_PORTA_din,
BRAM_PORTA_dout,
BRAM_PORTA_en,
BRAM_PORTA_we,
BRAM_PORTA_rst,
BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_en,
BRAM_PORTB_we,
BRAM_PORTB_rst
);
parameter DWIDTH = 32;
parameter AWIDTH = 10;
input [AWIDTH-1:0] BRAM_PORTA_addr;
input BRAM_PORTA_clk;
input [DWIDTH-1:0] BRAM_PORTA_din;
output [DWIDTH-1:0] BRAM_PORTA_dout;
input BRAM_PORTA_en;
input BRAM_PORTA_we;
input BRAM_PORTA_rst;
wire [AWIDTH-1:0] BRAM_PORTA_1_ADDR;
wire BRAM_PORTA_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTA_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTA_1_DOUT;
wire BRAM_PORTA_1_EN;
wire [3:0] BRAM_PORTA_1_WE;
wire BRAM_PORTA_1_RST;
input [AWIDTH-1:0] BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [DWIDTH-1:0] BRAM_PORTB_din;
output [DWIDTH-1:0] BRAM_PORTB_dout;
input BRAM_PORTB_en;
input [3:0] BRAM_PORTB_we;
input BRAM_PORTB_rst;
wire [AWIDTH-1:0] BRAM_PORTB_1_ADDR;
wire BRAM_PORTB_1_CLK;
wire [DWIDTH-1:0] BRAM_PORTB_1_DIN;
wire [DWIDTH-1:0] BRAM_PORTB_1_DOUT;
wire BRAM_PORTB_1_EN;
wire [3:0] BRAM_PORTB_1_WE;
wire BRAM_PORTB_1_RST;
assign BRAM_PORTA_1_ADDR = BRAM_PORTA_addr;
assign BRAM_PORTA_1_CLK = BRAM_PORTA_clk;
assign BRAM_PORTA_1_DIN = BRAM_PORTA_din;
assign BRAM_PORTA_1_EN = BRAM_PORTA_en;
assign BRAM_PORTA_1_WE = {BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we, BRAM_PORTA_we};
assign BRAM_PORTA_dout = BRAM_PORTA_1_DOUT;
assign BRAM_PORTA_1_RST = BRAM_PORTA_rst;
assign BRAM_PORTB_1_ADDR = BRAM_PORTB_addr;
assign BRAM_PORTB_1_CLK = BRAM_PORTB_clk;
assign BRAM_PORTB_1_DIN = BRAM_PORTB_din;
assign BRAM_PORTB_1_EN = BRAM_PORTB_en;
assign BRAM_PORTB_1_WE = BRAM_PORTB_we;
assign BRAM_PORTB_dout = BRAM_PORTB_1_DOUT;
assign BRAM_PORTB_1_RST = BRAM_PORTB_rst;
BRAM_blk_mem_12 blk_mem_gen_12 (
.addra(BRAM_PORTA_1_ADDR),
.clka (BRAM_PORTA_1_CLK),
.dina (BRAM_PORTA_1_DIN),
.douta(BRAM_PORTA_1_DOUT),
.ena (BRAM_PORTA_1_EN),
.wea (BRAM_PORTA_1_WE),
.rsta (BRAM_PORTA_1_RST),
.addrb(BRAM_PORTB_1_ADDR),
.clkb (BRAM_PORTB_1_CLK),
.dinb (BRAM_PORTB_1_DIN),
.doutb(BRAM_PORTB_1_DOUT),
.enb (BRAM_PORTB_1_EN),
.web (BRAM_PORTB_1_WE),
.rstb (BRAM_PORTB_1_RST)
);
endmodule
| 6.745427 |
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