code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module branch_met (
Yes,
ccc,
N,
V,
Z,
clk,
op
);
input [2:0] ccc;
input N, V, Z, clk;
input [3:0] op;
output reg Yes;
localparam NEQ = 3'b000;
localparam EQ = 3'b001;
localparam GT = 3'b010;
localparam LT = 3'b011;
localparam GTE = 3'b100;
localparam LTE = 3'b101;
loc... | 7.344115 |
module branch_mux (
input [2:0] fun3,
input a,
b,
c,
d,
e,
f,
output reg flag
);
always @(*) begin
case (fun3)
3'b000: flag = a;
3'b001: flag = b;
3'b100: flag = c;
3'b101: flag = d;
3'b110: flag = e;
3'b111: flag = f;
endcase
end
endmodu... | 7.223074 |
module Branch_MUX_Logic_gen (
input [1:0] Prediction_in,
input [6:0] Opcode,
output reg Prediction_out
);
always @(Prediction_in, Opcode) begin
case (Opcode)
`RV32_BRANCH: begin
if (Prediction_in == 2'b11 || Prediction_in == 2'b10) begin
Prediction_out = 1'b1;
end els... | 8.632097 |
module Branch_offset_generator (
input [24:0] Inst_in,
input [ 6:0] Opcode,
output [31:0] Branch_offset
);
wire [11:0] Branch_add_out;
wire [19:0] JAL_add_out;
wire [31:0] Branch_add_sign_extend;
wire [31:0] JAL_add_sign_extend;
Four_input_concatenator #(1, 1, 6, 4) concat4_1 (
Inst_in[2... | 7.094256 |
module Branch_Or_Jump (
Reverse,
branchZero,
ChangeType,
branch_Or_Jump
);
input Reverse;
input branchZero;
input [1:0] ChangeType;
output reg [1:0] branch_Or_Jump;
always @(*) begin
case (ChangeType)
`Sequence: begin
branch_Or_Jump <= `Sequence;
end
`Branch: beg... | 7.371317 |
module to have only one branch control signal, instead of eight.
Also, it performs all the branch comparations and decides if the branch is taken or not.
In short, all the branch processing is made inside of this module.*/
//INPUTS
/*
iBControlSignal : wire from the \CPU\Control_PIPEM - defines if this module is activ... | 8.961846 |
module branch_predict (
input clk,
input rstn,
// 记录
input record_we, // 是否记录分支历史
input [ 9:2] record_pc, // 记录的 pc
input record_data, // 记录是否跳转
input [31:0] record_pc_result, // 记录跳转后 pc
// 查询
input [ 9:1] chk_branch_pc,
output p... | 6.779337 |
module branch_predictor (
StateMSB,
BR,
Taken,
clk,
rst_n
);
input clk, rst_n;
input BR, Taken;
output StateMSB;
reg [1:0] state, nxt_state;
assign StateMSB = state[1];
parameter Taken1 = 2'b00;
parameter Taken2 = 2'b01;
parameter NotTaken1 = 2'b10;
parameter NotTaken2 = 2'b11;
... | 6.779337 |
module branch_predict_1 (
clk,
rst,
instrD,
immD,
pcD,
pcM,
branchM,
actual_takeM,
branchD,
pred_takeD
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 100000000, PHASE 0.000, INSE... | 6.779337 |
module bs (
b,
condition,
flag_reg,
b_s
); //module that generate branch signal at ID_MEM stage
input b;
input [2:0] condition;
input [2:0] flag_reg;
output b_s;
localparam [2:0] NE = 3'b000;
localparam [2:0] E = 3'b001;
localparam [2:0] GT = 3'b010;
localparam [2:0] LT = 3'b011;
lo... | 7.544248 |
module branch_select (
DATA1,
DATA2,
SELECT,
MUX_OUT
);
input [31:0] DATA1, DATA2;
input [3:0] SELECT;
output reg MUX_OUT;
wire BEQ, BNE, BLT, BGE, BLTU, BGEU;
assign BEQ = DATA1 == DATA2;
assign BNE = DATA1 != DATA2;
assign BLT = DATA1 < DATA2;
assign BGE = DATA1 >= DATA2;
assi... | 7.57908 |
module branch_shiftleft2 (
shift_in,
shift_out
);
input [31:0] shift_in;
output [31:0] shift_out;
assign shift_out[31:0] = {shift_in[29:0], 2'b00};
endmodule
| 7.227006 |
module branch_src_selector (
input [1:0] forward_data1,
input [1:0] forward_data2,
input [ 1:0] EX_MEM_Mem2Reg,
input [31:0] rdata1,
input [31:0] rdata2,
input [31:0] alu_result,
input [31:0] EX_MEM_ALU_Result,
input [31:0] ReadData,
input [31:0] WB_Data
);
endmodule
| 7.782756 |
module branch_stack (
input clk,
input rst,
input is_br_i, //[Dispatch] A new branch is dispatched, mask should be updated.
input is_cond_i, //[Dispatch]
input is_taken_i, //[Dispatch]
input [`BR_STATE_W-1:0] br_state_i, //[ROB] Branch prediction wrong or correct?
input [`BR_MASK_W-1... | 6.861829 |
module branch_t;
wire [31:0] next_inst;
reg [31:0] address, sign_extend, instruction;
reg jump_sig, branch_sig, alu_status;
branch branch (
next_inst,
address,
sign_extend,
instruction,
jump_sig,
branch_sig,
alu_status
);
initial begin
#10 address = 32'd0;
... | 6.744515 |
module branch_testbench;
reg [31:0] rs1, rs2;
reg [2:0] func;
wire taken;
BRANCH #(
.DWIDTH(32)
) uut (
.rs1_in(rs1),
.rs2_in(rs2),
.func (func),
.taken (taken)
);
task check_taken;
input [3:0] test_num;
input expected, got;
begin
if (expected !== got) b... | 6.670304 |
module branch_unit_tb ();
localparam PERIOD = 100;
reg [3:0] CCR;
reg branch, clk;
reg [1:0] jmp_type;
wire is_taken;
BranchUnit BU (
.CCR(CCR),
.branch(branch),
.jmp_type(jmp_type),
.is_taken(is_taken)
);
always begin
#(PERIOD / 2);
clk = ~clk;
end
initial begi... | 7.184281 |
module branch_wait ( /*AUTOARG*/
// Outputs
pending_branches_arry,
// Inputs
clk,
rst,
alu_valid,
alu_branch,
alu_wfid,
f_salu_branch_en,
f_salu_branch_wfid
);
input clk, rst;
// Issued alu info
input alu_valid, alu_branch;
input [`WF_ID_LENGTH-1:0] alu_wfid;
// Salu... | 7.425678 |
module single_port_memory #(
parameter ADDR_WIDTH = 5,
DATA_WIDTH = 32
) (
input wire clk,
input wire wt_en,
input wire [ADDR_WIDTH - 1:0] wtaddr,
input wire [DATA_WIDTH - 1:0] wtdata,
input wire [ADDR_WIDTH - 1:0] raddr1,
output wire [DATA_WIDTH - ... | 8.344917 |
module double_port_memory #(
parameter ADDR_WIDTH = 5,
DATA_WIDTH = 32
) (
input wire clk,
input wire wt_en,
input wire [ADDR_WIDTH - 1:0] wtaddr,
input wire [DATA_WIDTH - 1:0] wtdata,
input wire [ADDR_WIDTH - 1:0] raddr1,
input wire [ADDR_WIDTH - 1:... | 8.44126 |
module triple_port_memory #(
parameter ADDR_WIDTH = 5,
DATA_WIDTH = 32
) (
input wire clk,
input wire wt_en,
input wire [ADDR_WIDTH - 1:0] wtaddr,
input wire [DATA_WIDTH - 1:0] wtdata,
input wire [ADDR_WIDTH - 1:0] raddr1,
input wire [ADDR_WIDTH - 1:... | 8.595564 |
module log_update (
input wire branch,
input wire [9:0] old,
output reg [9:0] new_
);
reg [1:0] tar;
reg [1:0] learn;
always @(*) begin
case (old[9:8])
2'b00: begin
tar = old[1:0];
new_ = {old[8], branch, old[7:2], learn};
end
2'b01: begin
tar ... | 7.493504 |
module para #(
parameter ADDR_WIDTH = 32,
HASH_DEPTH = 6,
PARA_WIDTH = 10
) (
input wire clk,
input wire rstn,
input wire erEn, // whether we need to erase
input wire [ADDR_WIDTH - 1:0] erPC, // erase place
input wire erLower, // how to era... | 7.748448 |
module BrCondArea ( // @[:@3.2]
input [31:0] io_rs1, // @[:@6.4]
input [31:0] io_rs2, // @[:@6.4]
input [ 2:0] io_br_type, // @[:@6.4]
output io_taken // @[:@6.4]
);
wire [32:0] _T_13; // @[BrCond.scala 37:21:@8.4]
wire [32:0] _T_14; // @[BrCond.scala 37:21:@9.4]
wire [... | 7.719641 |
module Control ( // @[:@43.2]
input [31:0] io_inst, // @[:@46.4]
output [ 2:0] io_br_type // @[:@46.4]
);
wire [31:0] _T_35; // @[Lookup.scala 9:38:@48.4]
wire _T_36; // @[Lookup.scala 9:38:@49.4]
wire _T_40; // @[Lookup.scala 9:38:@51.4]
wire _T_44; // @[Lookup.scala 9:38:@53.4]
wire [31:0]... | 7.518923 |
module brdclk ( // Clock in ports
input CLK_IN1_P,
input CLK_IN1_N,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFGDS clkin1_buf (
.O (clkin1),
.I (CLK_IN1_P),
.IB(CLK_IN1_N)
);
// Clocking primitive
//------------... | 6.569787 |
module brdclk_pll ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//---------------------... | 6.849456 |
module Breadboard(a,b,opcode,clk,select);
//---------------------------------------------
//Parameters
//---------------------------------------------
input [15:0] a , b;
input [3:0] opcode;
input clk;
input [11:0] select;
wire [15:0] andG, nandout;
wire [15:0] or_output, nor_output;
wire [15:0] xor_output,xnor_outpu... | 7.122972 |
module Test_FSM() ;
//---------------------------------------------
//Inputs
//---------------------------------------------
reg [15:0] a , b;
reg [3:0] opcode;
reg clk;
reg [11:0] select;
//---------------------------------------------
//Declare FSM
//---------------------------------------------
Br... | 7.075415 |
module breakout_DE2 (
input CLOCK_50, // 50 MHz
input [0:0] KEY,
input [17:0] SW,
output VGA_CLK, // VGA Clock
output VGA_HS, // VGA H_SYNC
output VGA_VS, // VGA V_SYNC
output VGA_BLANK, // VGA BLANK
output VGA_SYNC, // VGA SYNC
... | 9.670132 |
module breakout_top (
input clk,
rst_n,
input [1:0] key, //move the paddle
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vga_out_hs
);
//FSM for the whole pong game
localparam [1:0] newgame = 0, play = 1, newball = 2, over = 3;
wire cl... | 7.787505 |
module breakout_top_an (
clk,
btnC,
btnU,
btnD,
Hsync,
Vsync,
vgaRed,
vgaGreen,
vgaBlue,
an,
seg
);
input clk, btnC, btnU, btnD;
output Hsync, Vsync;
output [3:0] vgaRed, vgaGreen, vgaBlue;
output [3:0] an;
output [6:0] seg;
// signals
wire [10:0] pixel_x, pixe... | 7.974994 |
module,
// which provide a hardware-level single
// break point support.
//
`timescale 1ns / 1ps
module Breakpoint (
input valid, // indicate whether the hit is taken.
input sampler, // drive the updating of break point
input [2:0] digit_sel, // select a digit to write in ... | 8.141716 |
module BreakpointUnit (
input clock,
input reset,
input io_status_debug,
input io_status_cease,
input io_status_wfi,
input [31:0] io_status_isa,
input [ 1:0] io_status_dprv,
input [ 1:0] io_status_prv,
input io_status_sd,
input ... | 8.021329 |
module BreakpointUnit_4 (
input clock,
input reset,
input io_status_debug,
input io_status_cease,
input io_status_wfi,
input [31:0] io_status_isa,
input [ 1:0] io_status_dprv,
input [ 1:0] io_status_prv,
input io_status_sd,
input... | 8.021329 |
module Breath (
input wire system_clk,
output wire [15:0] light
);
wire rst_n;
assign rst_n = 1;
reg [6:0] cnt1 = 0;
reg [9:0] cnt2 = 0;
reg [9:0] cnt3 = 0;
wire delay_1us;
wire delay_1ms;
wire delay_1s;
//ʱ1us
always @(posedge system_clk or negedge rst_n) begin
if (!rst_n) cnt1 <= 6'b0;... | 6.615179 |
module breathe (
input clk,
output reg breathe_sin,
output reg breathe_cos
);
parameter PREDIVIDER = 5;
// Predivider to select blink frequency
reg [PREDIVIDER:0] prediv = 0;
always @(posedge clk) prediv <= prediv + 1;
// Minsky circle algorithm
reg [20:0] sine = 0;
reg [20:0] cosine = 1 ... | 6.811201 |
module breath_led #(
parameter CNT_1US_MAX = 6'd49,
parameter CNT_1MS_MAX = 10'd999,
parameter CNT_1S_MAX = 10'd999
) (
input wire sys_clk, //系统时钟50Mhz
input wire sys_rst_n, //全局复位
output reg led_out //输出信号，控制led灯
);
//********************************************************************/... | 7.325783 |
module Bregister (
clk, // <i
Lb, // <i
busIn, // <i
Bvalue // >o
);
input clk, Lb;
input [7:0] busIn;
output [7:0] Bvalue;
reg [7:0] Bvalue;
initial begin
Bvalue = 8'd0;
end
always @(posedge clk) begin
if (Lb) begin
Bvalue = busIn;
end else begin
Bvalue = ... | 6.770721 |
module bReg (
clk,
alu_dataOut_2,
bReg_out
);
input clk;
input [31:0] alu_dataOut_2;
output reg [31:0] bReg_out;
always @(posedge clk) begin
bReg_out <= alu_dataOut_2;
end
endmodule
| 6.827944 |
module ppa_black (
gin,
pin,
gout,
pout
);
input [1:0] gin, pin;
output gout, pout;
and2 U1 (
pout,
pin[1],
pin[0]
);
ao21 U2 (
gout,
gin[0],
pin[1],
gin[1]
);
endmodule
| 7.287792 |
module ppa_buffer (
pin,
gin,
pout,
gout
);
input pin, gin;
output pout, gout;
buffer U1 (
pout,
pin
);
buffer U2 (
gout,
gin
);
endmodule
| 7.359153 |
module ppa_pre (
a_in,
b_in,
pout,
gout
);
input a_in, b_in;
output pout, gout;
xor2 U1 (
pout,
a_in,
b_in
);
and2 U2 (
gout,
a_in,
b_in
);
endmodule
| 7.554997 |
module ppa_grey (
gin,
pin,
gout
);
input [1:0] gin;
input pin;
output gout;
ao21 U1 (
gout,
gin[0],
pin,
gin[1]
);
endmodule
| 7.351436 |
module ppa_post (
pin,
gin,
sum
);
input pin, gin;
output sum;
xor2 U1 (
sum,
pin,
gin
);
endmodule
| 7.071112 |
module: BrentKung32Bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BrentKung32Bit_tb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg Cin;
// Outputs
wire [31:0] S;
wire Cout;... | 7.154462 |
module brent_kung16bit (
a,
b,
sum,
cin,
carry
);
input [15:0] a;
input [15:0] b;
input cin;
output [15:0] sum;
output carry;
wire [15:0] p;
wire [15:0] g;
wire [ 7:0] p2;
wire [ 7:0] g2;
wire [ 3:0] p3;
wire [ 3:0] g3;
wire [ 1:0] g4;
wire [ 1:0] p4;
wire [15:0] c;
wir... | 6.630644 |
module test_brent_kung_16;
// Inputs
reg [15:0] in1;
reg [15:0] in2;
reg cin;
// Outputs
wire [15:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
brent_kung_16 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
... | 7.224884 |
module: UBBKA_31_0_31_0
Operand-1 length: 32
Operand-2 length: 32
Two-operand addition algorithm: Brent-Kung adder
----------------------------------------------------------------------------*/
// Modified by: Amir Yazdanbakhsh
// Email: a.yazdanbakhsh@gatech.edu
`timescale 1ns/1ps
module GPGenerator(Go, Po, A,... | 7.632614 |
module CarryOperator (
Go,
Po,
Gi1,
Pi1,
Gi2,
Pi2
);
output Go;
output Po;
input Gi1;
input Gi2;
input Pi1;
input Pi2;
assign Go = Gi1 | (Gi2 & Pi1);
assign Po = Pi1 & Pi2;
endmodule
| 7.456973 |
module test_brent_kung_4;
// Inputs
reg [3:0] in1;
reg [3:0] in2;
reg cin;
// Outputs
wire [3:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
brent_kung_4 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2... | 7.224884 |
module test_brent_kung_8;
// Inputs
reg [7:0] in1;
reg [7:0] in2;
reg cin;
// Outputs
wire [7:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
brent_kung_8 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2... | 7.224884 |
module Brent_kung_adder #(
parameter WIDTH = 16,
VALENCY = 2
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:1] S,
output Cout
);
wire [WIDTH:0] G, P, Gi;
Bitwise_PG #(WIDTH) bit_PG (
A,
B,
Cin,
G,
P
);
Brent_kung_grp_PG #(WIDTH, VAL... | 7.72098 |
module Brent_kung_grp_PG #(
parameter WIDTH = 16,
VALENCY = 2
) (
input [WIDTH:0] G,
input [WIDTH:0] P,
output [WIDTH:0] Gi
);
wire [WIDTH-1:0] gt1[0:$clog2(WIDTH)], pt1[0:$clog2(WIDTH)];
assign gt1[0] = G;
assign pt1[0] = P;
assign Gi[0] = G[0];
genvar i, j, k;
generate
for (i... | 7.073151 |
module: bresenham
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bresenhamTest;
// Inputs
reg clk;
reg reset;
reg [7:0] x_0;
reg [7:0] y_0;
reg [7:0] x_1;
reg [7:0] y_1;
re... | 7.157795 |
module tb ();
reg clk = 0;
reg reset = 0;
wire baud;
brg dut (
clk,
reset,
baud
);
always #41.667 clk = ~clk;
initial begin
$dumpfile("dumpvars.vcd");
$dumpvars;
#10 reset = 1'b1;
#100 reset = 1'b0;
#100000 $finish;
end
endmodule
| 7.195167 |
module Bricks_Left (
Bricks_Left,
Bricks_Left_7SEG,
flag_reg
);
input [139:0] flag_reg;
output reg [7:0] Bricks_Left;
output [15:0] Bricks_Left_7SEG;
integer i;
always @(flag_reg) begin
Bricks_Left = 0;
for (i = 0; i < 140; i = i + 1) begin
if (!flag_reg[i]) Bricks_Left = Bricks_L... | 6.616715 |
module bricktest (
clk,
reset,
h_video,
v_video,
tick60hz,
pix_x,
pix_y,
ball_y_t,
brick_on,
brick_rgb,
direction,
BRICK_Y_T,
brick_rgbin,
brick_p
);
input clk, reset, tick60hz, h_video, v_video;
input [2:0] brick_rgbin;
input [9:0] pix_x, pix_y, ball_y_t;
... | 6.501346 |
module bridgetop_tb ();
parameter [2:0] SINGLE = 3'd0,INCR = 3'd1, WRAP4 = 3'd2, INCR4 = 3'd3, WRAP8 = 3'd4, INCR8 = 3'd5, WRAP16 = 3'd6, INCR16 = 3'd7;
reg Hclk;
reg Hresetn;
reg [2:0] Hburst;
reg [2:0] Hsize;
wire [31:0] Hrdata;
wire [1:0] Hresp;
wire Hreadyout;
wire Hwrite;
wire Hreadyin;
wi... | 6.742151 |
module bridge_1x2 (
input clk, // clock
input resetn, // reset, active low
// master : cpu data
input cpu_data_en, // cpu data access enable
input [ 7 : 0] cpu_data_wen, // cpu data write byte enable
input [63 : 0] cpu_data_addr, ... | 7.579477 |
module bridge_1_2 (
input no_dcache,
// cpu
input cpu_req,
input cpu_wr,
input [1 : 0] cpu_size,
input [ 31:0] cpu_addr,
input [ 31:0] cpu_wdata,
output [ 31:0] cpu_rdata,
output cpu_addr_ok,
output cpu_data_ok,
// ram (cache opti... | 7.250689 |
module bridge (
praddr,
prwd,
dev0_rd,
dev1_rd,
dev2_rd,
wecpu,
IRQ,
prrd,
dev_wd,
dev_addr,
wedev0,
wedev2,
HWInt
);
input [31:0] praddr, prwd, dev0_rd, dev1_rd, dev2_rd;
input wecpu, IRQ;
output [31:0] prrd, dev_wd;
output [31:0] dev_addr;
output wedev0, w... | 8.006498 |
module bridge_2x1 (
input no_dcache,
input ram_data_req,
input ram_data_wr,
input [1 : 0] ram_data_size,
input [ 31:0] ram_data_addr,
input [ 31:0] ram_data_wdata,
output [ 31:0] ram_data_rdata,
output ram_data_addr_ok,
output ram_data_data_ok,
... | 6.742313 |
module bridge_2_1 (
input no_dcache,
input ram_req,
input ram_wr,
input [1 : 0] ram_size,
input [ 31:0] ram_addr,
input [ 31:0] ram_wdata,
output [ 31:0] ram_rdata,
output ram_addr_ok,
output ram_data_ok,
input conf_req,
input ... | 6.584196 |
module bridge_4 #(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1,
parameter SYNC_RESET = 0
) (
input wire ... | 8.518203 |
module bridge_64b_to_16b (
input rstn,
input clk_125,
input [63:0] tx_data_64b,
input tx_st_64b,
input tx_end_64b,
input tx_dwen_64b,
output tx_rdy_64b,
output tx_val,
input tx_rdy_16b,
output reg [15:0] tx_data_16b,
output reg tx_st_16b,
output reg tx_end_16b
);
assi... | 6.992944 |
module bridge_div (
bri_div_start,
rst_n, //λ
clk_sys,
clk_dds, //ʱ
load, //װطƵ
divcount, //Ƶ
clk_4f_en //ʱ
);
input bri_div_start;
input rst_n;
input clk_sys;
input clk_dds;
input load;
input [5:0] divcount;
output clk_4f_en;
reg clk_4f;
reg [5:0] count;
re... | 6.941733 |
module bridge_top (
hclk,
hresetn,
hwrite,
hready_in,
htrans,
hwdata,
haddr,
pwrite,
penable,
psel,
paddr,
pwdata,
prdata,
hrdata,
hresp,
hready_out
);
input hclk, hresetn, hwrite, hready_in;
input [1:0] htrans;
input [31:0] hwdata, haddr;
output ... | 6.537546 |
module brief_compare #(
parameter DATA_WIDTH = 14
) (
input wire clk,
input wire [DATA_WIDTH-1:0] compare_A,
input wire [DATA_WIDTH-1:0] compare_B,
output reg compare_out
);
always @(posedge clk)
if (compare_A < compare_B) compare_out <= 1'b1;
else compare_out <= 1'b0;
endmodule
| 8.901087 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input io_axiClk
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.574801 |
module StreamArbiter_3 (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [19:0] io_inputs_0_payload_addr,
input [ 3:0] io_inputs_0_payload_id,
input [ 7:0] io_inputs_0_payload_len,
input [ 2:0] io_inputs_0_payload_size,
input [ 1:0] io_inputs_0_payload_burst,
... | 6.929245 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
output reg io_pop_valid,
input io_pop_ready,
input io_flush,
output [2:0] io_occupancy,
input io_axiClk,
input resetCtrl_axiReset
);
wire... | 7.046487 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [31:0] io_axi_arw_payload_addr,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
input [ 3:0] io_axi_arw_payload_cache,
input [ 2:0] io_axi_arw_payload_prot,
... | 6.942764 |
module Axi4ReadOnlyErrorSlave (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 1:0] io_axi_ar_payload_burst,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
out... | 7.858199 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_a... | 6.712921 |
module BufferCC_12 (
input io_dataIn,
output io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= bu... | 7.001425 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
i... | 6.706229 |
module BufferCC_10 (
input io_dataIn,
output io_dataOut,
input io_axiClk
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.968109 |
module StreamArbiter_3 (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [19:0] io_inputs_0_payload_addr,
input [ 3:0] io_inputs_0_payload_id,
input [ 7:0] io_inputs_0_payload_len,
input [ 2:0] io_inputs_0_payload_size,
input [ 1:0] io_inputs_0_payload_burst,
... | 6.929245 |
module StreamFifoLowLatency_1 (
input io_push_valid,
output io_push_ready,
output reg io_pop_valid,
input io_pop_ready,
input io_flush,
output [2:0] io_occupancy,
input io_axiClk,
input resetCtrl_axiReset
);
wir... | 7.046487 |
module Axi4ReadOnlyErrorSlave_1 (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 2:0] io_axi_ar_payload_size,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
ou... | 7.858199 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [31:0] io_axi_arw_payload_addr,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
input [ 3:0] io_axi_arw_payload_cache,
input [ 2:0] io_axi_arw_payload_prot,
... | 6.942764 |
module Axi4ReadOnlyErrorSlave (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 1:0] io_axi_ar_payload_burst,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
out... | 7.858199 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input io_axiClk,
... | 7.790686 |
module InterruptCtrl (
input [3:0] io_inputs,
input [3:0] io_clears,
input [3:0] io_masks,
output [3:0] io_pendings,
input io_axiClk,
input resetCtrl_axiReset
);
reg [3:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge io_axiClk or posedge resetCtr... | 7.510624 |
module Timer (
input io_tick,
input io_clear,
input [31:0] io_limit,
output io_full,
output [31:0] io_value,
input io_axiClk,
input resetCtrl_axiReset
);
wire [31:0] _zz_counter;
wire [ 0:0] _zz_counter_1;
reg [31:0] counter;
wire limit... | 6.729771 |
module BufferCC_8 (
input io_dataIn_clear,
input io_dataIn_tick,
output io_dataOut_clear,
output io_dataOut_tick,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0_clear;
(* async_reg = "true" *)reg buffers_0_tick;
(* async_reg = "true" *)reg buffers_1_... | 6.740109 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input io_axiClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= ... | 6.82712 |
module BufferCC_3 (
input [6:0] io_dataIn,
output [6:0] io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg [6:0] buffers_0;
(* async_reg = "true" *)reg [6:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_... | 6.792516 |
module BufferCC_1 (
input [9:0] io_dataIn,
output [9:0] io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg [9:0] buffers_0;
(* async_reg = "true" *)reg [9:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk or posedge resetCtr... | 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_ax... | 6.712921 |
module bridge (
input [31:0] PrAddr, //cpu传入的地址
input [31:0] PrWD, //cpu欲写入的内容
input [31:0] dev0_rd,
dev1_rd,
dev2_rd, //外部设备欲写入的数据
input IRQ, //计时器的中断信号
input wecpu, //来自cpu的写使能
output we_dev0,
we_dev2, //给计时器和输出设备的写使能
output [5:0] HWInt, //6个中断信号
output [31:0] PrRD,... | 8.006498 |
module brightness (
input [5:0] value, /* the pixel's absolute value */
input [5:0] mask, /* a rolling brightness mask */
input enable,
output out
);
/* apply the brightness mask to the calculated sub-pixel value */
wire masked_value = (value & mask) != 0;
assign out = masked_value && enable;
e... | 8.194426 |
module brimm_gen (
input wire [`INSN_LEN-1:0] inst,
output wire [`DATA_LEN-1:0] brimm
);
wire [`DATA_LEN-1:0] br_offset = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0};
wire [`DATA_LEN-1:0] jal_offset = {
{12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], 1'b0
};
wire [`DA... | 7.360356 |
module brimestone #(
parameter DATA_WIDTH_P = 32,
parameter DATA_ADDR_WIDTH_P = 32,
parameter ADDR_WIDTH_P = 5,
parameter CNTRL_WIDTH_P = 3,
parameter ALU_CNTRL_WIDTH_P = 3,
parameter FUNCT_WIDTH_P = 6,
parameter OP_WIDTH_P = 6
) (
input wire clk,
input wire reset,
input wire i_e... | 7.295892 |
module trisc (
cond,
out_sig,
clk,
reset_n
);
//independent parameters
parameter ncs = 3; //number of bits to select cw+1 inputs i.e 2^ncs = (cw+1)
parameter aw = 8; //address width
parameter dw = 20; //data width for internal control
parameter ow = 28; //control output size
//dependan... | 8.543763 |
module bri_dump_sw (
rst_n,
clk_sys,
change,
pluse_start,
pluse_start1,
pluse_start2,
off_test,
off_test1,
off_test2,
dump_start,
dump_start1,
dump_start2,
phase_ctr,
phase_ctr1,
phase_ctr2,
reset_out,
reset_out1,
reset_out2,
dumpoff_ctr,
d... | 6.508231 |
module brj_addr_calc (
instr,
next_pc,
dest_addr
);
// TODO : ARE SHIFTS NEEDED?? (ie SL by 1)
// inputs
input [15:0] instr;
input [15:0] next_pc;
// outputs
output [15:0] dest_addr;
// wires
wire [4:0] op;
wire co, G, P;
reg [15:0] sextVal;
// assigns
assign op = instr[15:11];
... | 8.092937 |
module Broadcaster #(
parameter WIDTH0 = 32
, parameter WIDTH1 = 32
, parameter BURST = "yes"
) (
input iValid_AM
, output oReady_AM
, input [WIDTH1+WIDTH0-1:0] iData_AM
, output oValid_BM0
, input iR... | 7.041826 |
module BroadcasterN #(
parameter SIZE = 8
, parameter WIDTH = 32
, parameter BURST = "yes"
) (
input iValid_AM
, output oReady_AM
, input [SIZE*WIDTH-1:0] iData_AM
, output [ SIZE-1:0] oValid_BM
, input [ SIZE-1:0] iReady_BM
, outpu... | 7.831177 |
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