code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module branch_met (
Yes,
ccc,
N,
V,
Z,
clk,
op
);
input [2:0] ccc;
input N, V, Z, clk;
input [3:0] op;
output reg Yes;
localparam NEQ = 3'b000;
localparam EQ = 3'b001;
localparam GT = 3'b010;
localparam LT = 3'b011;
localparam GTE = 3'b100;
localparam LTE = 3'b101;
localparam OV = 3'b110;
localparam UN = 3'b111;
always @(*) begin
Yes = 0;
if (op == 4'b1100) begin
case (ccc)
NEQ: begin
if (Z == 1'b0) begin
Yes = 1;
end
end
EQ: begin
if (Z == 1'b1) begin
Yes = 1;
end
end
GT: begin
if (Z == 1'b0 && N == 1'b0) Yes = 1;
end
LT: begin
if (N == 1'b1) Yes = 1;
end
GTE: begin
if (Z == 1'b1 || (Z == 1'b0 && N == 1'b0)) Yes = 1;
end
LTE: begin
if (N == 1'b1 || Z == 1'b1) Yes = 1;
end
OV: begin
if (V == 1'b1) Yes = 1;
end
UN: begin
Yes = 1;
end
default: begin
Yes = 0;
end
endcase
end
end
endmodule
| 7.344115 |
module branch_mux (
input [2:0] fun3,
input a,
b,
c,
d,
e,
f,
output reg flag
);
always @(*) begin
case (fun3)
3'b000: flag = a;
3'b001: flag = b;
3'b100: flag = c;
3'b101: flag = d;
3'b110: flag = e;
3'b111: flag = f;
endcase
end
endmodule
| 7.223074 |
module Branch_MUX_Logic_gen (
input [1:0] Prediction_in,
input [6:0] Opcode,
output reg Prediction_out
);
always @(Prediction_in, Opcode) begin
case (Opcode)
`RV32_BRANCH: begin
if (Prediction_in == 2'b11 || Prediction_in == 2'b10) begin
Prediction_out = 1'b1;
end else if (Prediction_in == 2'b00 || Prediction_in == 2'b01) begin
Prediction_out = 1'b0;
end
end
`RV32_JAL: Prediction_out = 1'b1;
default: Prediction_out = 1'b0;
endcase
end
endmodule
| 8.632097 |
module Branch_offset_generator (
input [24:0] Inst_in,
input [ 6:0] Opcode,
output [31:0] Branch_offset
);
wire [11:0] Branch_add_out;
wire [19:0] JAL_add_out;
wire [31:0] Branch_add_sign_extend;
wire [31:0] JAL_add_sign_extend;
Four_input_concatenator #(1, 1, 6, 4) concat4_1 (
Inst_in[24],
Inst_in[0],
Inst_in[23:18],
Inst_in[4:1],
Branch_add_out
);
Four_input_concatenator #(1, 1, 8, 10) concat4_2 (
Inst_in[24],
Inst_in[13],
Inst_in[12:5],
Inst_in[23:14],
JAL_add_out
);
Sign_extender #(12, 32) sign_extend1 (
Branch_add_out,
Branch_add_sign_extend
);
Sign_extender #(20, 32) sign_extend2 (
JAL_add_out,
JAL_add_sign_extend
);
Jump_add_selector jump_add_selector (
Branch_add_sign_extend,
JAL_add_sign_extend,
Opcode,
Branch_offset
);
endmodule
| 7.094256 |
module Branch_Or_Jump (
Reverse,
branchZero,
ChangeType,
branch_Or_Jump
);
input Reverse;
input branchZero;
input [1:0] ChangeType;
output reg [1:0] branch_Or_Jump;
always @(*) begin
case (ChangeType)
`Sequence: begin
branch_Or_Jump <= `Sequence;
end
`Branch: begin
$display("branchZero = %x Reverse = %x", branchZero, Reverse);
if (Reverse ^ branchZero) begin
branch_Or_Jump <= `Branch;
end else begin
branch_Or_Jump <= `NotBranch;
end
end
`Jump: begin
branch_Or_Jump <= `Jump;
end
default: begin
branch_Or_Jump <= `Sequence;
end
endcase
end
endmodule
| 7.371317 |
module to have only one branch control signal, instead of eight.
Also, it performs all the branch comparations and decides if the branch is taken or not.
In short, all the branch processing is made inside of this module.*/
//INPUTS
/*
iBControlSignal : wire from the \CPU\Control_PIPEM - defines if this module is active or inactive
iOpcode,
iA,
iB,
iRt
*/
//OUTPUTS
//Implemented in 1/21'b016
/*******************************************************************************************************/
module Branch_PIPEM (
iBControlSignal,
iOpcode,
iA,
iB,
iRt,
oBranch,
oLink
);
input wire iBControlSignal;
input wire [5:0] iOpcode;
input wire [31:0] iA, iB;
input wire [4:0] iRt;
output wire oBranch, oLink;
always @ (*) begin
if (iBControlSignal == 1)
begin
case (iOpcode)
OPCBEQ:
begin
oBranch = iA == iB;
oLink = 1'b0;
end
OPCBNE:
begin
oBranch = iA != iB;
oLink = 1'b0;
end
OPCBGTZ:
begin
case (iRt)
RTZERO:
begin
oBranch = iA > ZERO;
oLink = 1'b0;
end
default:
begin
oBranch = 1'b0;
oLink = 1'b0;
end
endcase
end
OPCBLEZ:
begin
case (iRt)
RTZERO:
begin
oBranch = iA <= ZERO;
oLink = 1'b0;
end
default:
begin
oBranch = 1'b0;
oLink = 1'b0;
end
endcase
end
OPCBGE_LTZ:
begin
case (iRt)
RTBGEZ:
begin
oBranch = iA >= ZERO;
oLink = 1'b0;
end
RTBGEZAL:
begin
oBranch = iA >= ZERO;
oLink = 1'b1;
end
RTBLTZ:
begin
oBranch = iA < iB;
oLink = 1'b0;
end
RTBLTZAL:
begin
oBranch = iA < iB;
oLink = 1'b1;
end
default:
begin
oBranch = 1'b0;
oLink = 1'b0;
end
endcase
end
endcase
end
else
begin
case (iOpcode)
OPCJAL:
begin
oBranch = 1'b0;
oLink = 1'b0;
end
default:
begin
oBranch = 1'b0;
oLink = 1'b0;
end
endcase
end
end
endmodule
| 8.961846 |
module branch_predict (
input clk,
input rstn,
// 记录
input record_we, // 是否记录分支历史
input [ 9:2] record_pc, // 记录的 pc
input record_data, // 记录是否跳转
input [31:0] record_pc_result, // 记录跳转后 pc
// 查询
input [ 9:1] chk_branch_pc,
output predict, // 预测结果
output [31:0] predict_pc // 预测的 pc
);
reg [31:0] btb [0:255]; // BTB 表
reg [ 1:0] record [0:255]; // (hash 后) 饱和计数器
reg [ 2:0] history [ 0:31]; // (hash 后) 分支历史
wire [ 4:0] chk_pc_hash = chk_branch_pc[6:2];
wire [ 4:0] record_pc_hash = record_pc[6:2];
assign predict_pc = btb[chk_branch_pc[9:2]];
assign predict = !chk_branch_pc[1] & rstn & record[{chk_pc_hash, history[chk_pc_hash]}][1] & (predict_pc != 0);
always @(posedge clk) begin
if (record_we) begin
if (record_data) begin
btb[record_pc] <= record_pc_result;
end
history[record_pc_hash] <= {history[record_pc_hash][1:0], record_data};
if (record_data && record[{record_pc_hash, history[record_pc_hash]}] != 2'b11)
record[{
record_pc_hash, history[record_pc_hash]
}] <= record[{record_pc_hash, history[record_pc_hash]}] + 1;
else if (!record_data && record[{record_pc_hash, history[record_pc_hash]}] != 2'b00)
record[{
record_pc_hash, history[record_pc_hash]
}] <= record[{record_pc_hash, history[record_pc_hash]}] - 1;
end
end
endmodule
| 6.779337 |
module branch_predictor (
StateMSB,
BR,
Taken,
clk,
rst_n
);
input clk, rst_n;
input BR, Taken;
output StateMSB;
reg [1:0] state, nxt_state;
assign StateMSB = state[1];
parameter Taken1 = 2'b00;
parameter Taken2 = 2'b01;
parameter NotTaken1 = 2'b10;
parameter NotTaken2 = 2'b11;
// State assignment logic
always @(posedge clk, negedge rst_n) begin
if (~rst_n) state <= Taken1;
else state <= nxt_state;
$display("State is: %b", state);
end
always @(state, BR, Taken) begin
nxt_state = Taken1;
case (state)
Taken1: if (BR & ~Taken) nxt_state = Taken2;
Taken2:
if (~BR) nxt_state = Taken2;
else if (BR & ~Taken) nxt_state = NotTaken1;
NotTaken1:
if (BR & Taken) nxt_state = Taken2;
else if (~BR) nxt_state = NotTaken1;
else nxt_state = NotTaken2;
NotTaken2:
if (BR & Taken) nxt_state = NotTaken1;
else nxt_state = NotTaken2;
default: nxt_state = Taken1;
endcase
end
endmodule
| 6.779337 |
module branch_predict_1 (
clk,
rst,
instrD,
immD,
pcD,
pcM,
branchM,
actual_takeM,
branchD,
pred_takeD
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0" *) input clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME rst, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) input rst;
input [31:0] instrD;
input [31:0] immD;
input [31:0] pcD;
input [31:0] pcM;
input branchM;
input actual_takeM;
output branchD;
output pred_takeD;
wire actual_takeM;
wire branchD;
wire branchD_INST_0_i_1_n_0;
wire branchM;
wire clk;
wire [31:0] instrD;
wire [31:0] pcD;
wire [31:0] pcM;
wire pred_takeD;
wire rst;
LUT4 #(
.INIT(16'h0002)
) branchD_INST_0 (
.I0(branchD_INST_0_i_1_n_0),
.I1(instrD[30]),
.I2(instrD[29]),
.I3(instrD[31]),
.O (branchD)
);
LUT6 #(
.INIT(64'hAAAAAAAAAAAAAABA)
) branchD_INST_0_i_1 (
.I0(instrD[28]),
.I1(instrD[18]),
.I2(instrD[26]),
.I3(instrD[17]),
.I4(instrD[19]),
.I5(instrD[27]),
.O (branchD_INST_0_i_1_n_0)
);
branch_predict_1_branch_predict inst (
.actual_takeM(actual_takeM),
.branchD(branchD),
.branchM(branchM),
.clk(clk),
.pcD(pcD[11:2]),
.pcM(pcM[11:2]),
.pred_takeD(pred_takeD),
.rst(rst)
);
endmodule
| 6.779337 |
module bs (
b,
condition,
flag_reg,
b_s
); //module that generate branch signal at ID_MEM stage
input b;
input [2:0] condition;
input [2:0] flag_reg;
output b_s;
localparam [2:0] NE = 3'b000;
localparam [2:0] E = 3'b001;
localparam [2:0] GT = 3'b010;
localparam [2:0] LT = 3'b011;
localparam [2:0] GE = 3'b100;
localparam [2:0] LE = 3'b101;
localparam [2:0] OV = 3'b110;
localparam [2:0] TRUE = 3'b111;
assign b_s = (b != 1'b1)? 0:
((condition == NE)&&(flag_reg[0] == 0))? 1:
((condition == E)&&(flag_reg[0] == 1))? 1:
((condition == GT)&&(|flag_reg[1:0] == 0))? 1:
((condition == LT)&&(flag_reg[1] == 1))? 1:
((condition == GE)&&((flag_reg[0] == 1)||(|flag_reg[1:0] == 0)))? 1:
((condition == LE)&&(|flag_reg[1:0] == 1))? 1:
((condition == OV)&&(|flag_reg[2] == 1))? 1:
(condition == TRUE)? 1 : 0;
endmodule
| 7.544248 |
module branch_select (
DATA1,
DATA2,
SELECT,
MUX_OUT
);
input [31:0] DATA1, DATA2;
input [3:0] SELECT;
output reg MUX_OUT;
wire BEQ, BNE, BLT, BGE, BLTU, BGEU;
assign BEQ = DATA1 == DATA2;
assign BNE = DATA1 != DATA2;
assign BLT = DATA1 < DATA2;
assign BGE = DATA1 >= DATA2;
assign BLTU = $unsigned(DATA1) < $unsigned(DATA2);
assign BGEU = $unsigned(DATA1) >= $unsigned(DATA2);
// TODO: implement the function
always @(*) begin
#2
if (SELECT[3]) begin
case (SELECT[2:0])
// for JAL and JALR
3'b010: MUX_OUT = 1'b1;
// for BEQ
3'b000: MUX_OUT = BEQ;
// for BNE
3'b001: MUX_OUT = BNE;
// for BLT
3'b100: MUX_OUT = BLT;
// for BGE
3'b101: MUX_OUT = BGE;
// for BLTU
3'b110: MUX_OUT = BLTU;
// for BGEU
3'b111: MUX_OUT = BGEU;
default: MUX_OUT = 1'b0;
endcase
end else begin
#2 MUX_OUT = 1'b0;
end
end
endmodule
| 7.57908 |
module branch_shiftleft2 (
shift_in,
shift_out
);
input [31:0] shift_in;
output [31:0] shift_out;
assign shift_out[31:0] = {shift_in[29:0], 2'b00};
endmodule
| 7.227006 |
module branch_src_selector (
input [1:0] forward_data1,
input [1:0] forward_data2,
input [ 1:0] EX_MEM_Mem2Reg,
input [31:0] rdata1,
input [31:0] rdata2,
input [31:0] alu_result,
input [31:0] EX_MEM_ALU_Result,
input [31:0] ReadData,
input [31:0] WB_Data
);
endmodule
| 7.782756 |
module branch_stack (
input clk,
input rst,
input is_br_i, //[Dispatch] A new branch is dispatched, mask should be updated.
input is_cond_i, //[Dispatch]
input is_taken_i, //[Dispatch]
input [`BR_STATE_W-1:0] br_state_i, //[ROB] Branch prediction wrong or correct?
input [`BR_MASK_W-1:0] br_dep_mask_i, //[ROB] The mask of currently resolved branch.
input [`BR_MASK_W-1:0] rs_iss2br_mask_i,
input [`MT_NUM-1:0][`PRF_IDX_W:0] bak_mp_next_data_i, //[Map Table] Back up data from map table.
input [`FL_PTR_W:0] bak_fl_head_i, //[Free List] Back up head of free list.
input [`SQ_IDX_W:0] bak_sq_tail_i,
// <11/14>
input cdb_vld_i,
input [`PRF_IDX_W-1:0] cdb_tag_i,
output logic [`BR_MASK_W-1:0] br_mask_o, //[ROB] Send current mask value to ROB to save in an ROB entry.
output logic [`BR_MASK_W-1:0] br_bit_o, //[RS] Output corresponding branch bit immediately after knowing wrong or correct.
output logic full_o, //[ROB] Tell ROB that stack is full and no further branch dispatch is allowed.
output logic [`MT_NUM-1:0][`PRF_IDX_W:0] rc_mt_all_data_o, //[Map Table] Recovery data for map table.
output logic [`FL_PTR_W:0] rc_fl_head_o, //[Free List] Recovery head value for free list.
output logic [`SQ_IDX_W:0] rc_sq_tail_o
);
logic [`BR_MASK_W-1:0] br_mask;
logic [`BR_MASK_W-1:0][`MT_NUM-1:0][`PRF_IDX_W:0] unslctd_mt_data;
logic [`BR_MASK_W-1:0][`FL_PTR_W:0] unslctd_fl_data;
logic [`BR_MASK_W-1:0][`SQ_IDX_W:0] unslctd_sq_data;
assign br_mask_o = br_mask;
// This is a Selector. Select one stack data out when predict wrong.
always_comb begin
rc_mt_all_data_o = 0;
rc_fl_head_o = 0;
rc_sq_tail_o = 0;
if (br_state_i == `BR_PR_WRONG) begin
for (int i = 0; i < `BR_MASK_W; i++) begin
if (br_bit_o[i] == 1) begin
rc_mt_all_data_o = unslctd_mt_data[i];
rc_fl_head_o = unslctd_fl_data[i];
rc_sq_tail_o = unslctd_sq_data[i];
//break;
end
end
end else begin
rc_mt_all_data_o = 0;
rc_fl_head_o = 0;
rc_sq_tail_o = 0;
end
end
br_mask_ctrl br_mask_ctrl0 (
.clk(clk),
.rst(rst),
.is_br_i(is_br_i),
.is_cond_i(is_cond_i),
.is_taken_i(is_taken_i),
.br_state_i(br_state_i),
.br_dep_mask_i(br_dep_mask_i),
.rs_iss2br_mask_i(rs_iss2br_mask_i),
.br_mask_o(br_mask),
.br_bit_o(br_bit_o),
.full_o(full_o)
);
br_stack_ent bse[`BR_MASK_W-1:0] (
.clk(clk),
.rst(rst),
.mask_bit_i(br_mask),
.br_1hot_bit_i(br_bit_o),
.br_state_i(br_state_i),
.cdb_vld_i(cdb_vld_i),
.cdb_tag_i(cdb_tag_i),
.bak_mp_next_data_i(bak_mp_next_data_i),
.bak_fl_head_i(bak_fl_head_i),
.bak_sq_tail_i(bak_sq_tail_i),
.rc_mt_all_data_o(unslctd_mt_data),
.rc_fl_head_o(unslctd_fl_data),
.rc_sq_tail_o(unslctd_sq_data)
);
endmodule
| 6.861829 |
module branch_t;
wire [31:0] next_inst;
reg [31:0] address, sign_extend, instruction;
reg jump_sig, branch_sig, alu_status;
branch branch (
next_inst,
address,
sign_extend,
instruction,
jump_sig,
branch_sig,
alu_status
);
initial begin
#10 address = 32'd0;
sign_extend = 32'd2;
alu_status = 1'b1;
branch_sig = 1'b1;
jump_sig = 1'b0;
#10 address = 32'd0;
instruction = 32'd0;
branch_sig = 1'b0;
jump_sig = 1'b1;
#10 address = 32'd20;
instruction = 32'd30;
branch_sig = 1'b0;
jump_sig = 1'b1;
#10 address = 32'd10;
instruction = 32'd0;
sign_extend = -2'd2;
jump_sig = 1'b0;
branch_sig = 1'b1;
end
endmodule
| 6.744515 |
module branch_testbench;
reg [31:0] rs1, rs2;
reg [2:0] func;
wire taken;
BRANCH #(
.DWIDTH(32)
) uut (
.rs1_in(rs1),
.rs2_in(rs2),
.func (func),
.taken (taken)
);
task check_taken;
input [3:0] test_num;
input expected, got;
begin
if (expected !== got) begin
$display("FAIL - test %d, expected: %h, got: %h", test_num, expected, got);
$finish;
end else begin
$display("PASS - test %d, got: %h", test_num, got);
end
end
endtask
task check_bge;
begin
$display("====CHECK BGE====");
rs1 = 32'h0000_0001;
rs2 = 32'h0000_0001;
func = `FNC_BGE;
#1 check_taken(1, 1'b1, taken);
rs1 = 32'h0000_0001;
rs2 = 32'h0000_0002;
#1 check_taken(2, 1'b0, taken);
rs1 = 32'h0000_0001;
rs2 = 32'hffff_fff0;
#1 check_taken(3, 1'b1, taken);
rs1 = 32'h0000_0002;
rs2 = 32'h0000_0001;
#1 check_taken(4, 1'b1, taken);
end
endtask
task check_bgeu;
begin
$display("====CHECK BGEU====");
rs1 = 32'h0000_0001;
rs2 = 32'h0000_0001;
func = `FNC_BGEU;
#1 check_taken(1, 1'b1, taken);
rs1 = 32'h0000_0001;
rs2 = 32'h0000_0002;
#1 check_taken(2, 1'b0, taken);
rs1 = 32'h0000_0001;
rs2 = 32'hffff_fff0;
#1 check_taken(3, 1'b0, taken);
rs1 = 32'h0000_0002;
rs2 = 32'h0000_0001;
#1 check_taken(4, 1'b1, taken);
end
endtask
initial begin
check_bge();
check_bgeu();
$display("ALL BRANCH TESTS PASSED!");
$finish;
end
endmodule
| 6.670304 |
module branch_unit_tb ();
localparam PERIOD = 100;
reg [3:0] CCR;
reg branch, clk;
reg [1:0] jmp_type;
wire is_taken;
BranchUnit BU (
.CCR(CCR),
.branch(branch),
.jmp_type(jmp_type),
.is_taken(is_taken)
);
always begin
#(PERIOD / 2);
clk = ~clk;
end
initial begin
clk = 0;
CCR = 4'b0000;
branch = 1'b1;
jmp_type = 2'b00;
#PERIOD;
if (!(is_taken)) $display("#1, success not taken branch");
else $display("#1, fail taken branch");
#PERIOD;
CCR = 4'b0001;
branch = 1'b1;
jmp_type = 2'b00;
#PERIOD;
if (is_taken == 1'b1) $display("#2, success taken branch");
else $display("#2, fail not taken branch");
#PERIOD;
CCR = 4'b0001;
branch = 1'b0;
jmp_type = 2'b00;
#PERIOD;
if (!(is_taken)) $display("#3, success not taken branch");
else $display("#3, fail taken branch");
#PERIOD;
/////////////////////////////
CCR = 4'b0000;
branch = 1'b1;
jmp_type = 2'b01;
#PERIOD;
if (!(is_taken)) $display("#4, success not taken branch");
else $display("#4, fail taken branch");
#PERIOD;
CCR = 4'b0011;
branch = 1'b1;
jmp_type = 2'b01;
#PERIOD;
if (is_taken == 1'b1) $display("#5, success taken branch");
else $display("#5, fail not taken branch");
#PERIOD;
CCR = 4'b0011;
branch = 1'b0;
jmp_type = 2'b01;
#PERIOD;
if (!(is_taken)) $display("#6, success not taken branch");
else $display("#6, fail taken branch");
#PERIOD;
//////////////////////////////
CCR = 4'b0000;
branch = 1'b1;
jmp_type = 2'b10;
#PERIOD;
if (!(is_taken)) $display("#7, success not taken branch");
else $display("#7, fail taken branch");
#PERIOD;
CCR = 4'b0111;
branch = 1'b1;
jmp_type = 2'b10;
#PERIOD;
if (is_taken == 1'b1) $display("#8, success taken branch");
else $display("#8, fail not taken branch");
#PERIOD;
CCR = 4'b0101;
branch = 1'b0;
jmp_type = 2'b10;
#PERIOD;
if (!(is_taken)) $display("#9, success not taken branch");
else $display("#9, fail taken branch");
#PERIOD;
/////////////////////////////////
CCR = 4'b0000;
branch = 1'b1;
jmp_type = 2'b11;
#PERIOD;
if (is_taken == 1'b1) $display("#10, success taken branch");
else $display("#10, fail not taken branch");
#PERIOD;
CCR = 4'b1111;
branch = 1'b1;
jmp_type = 2'b11;
#PERIOD;
if (is_taken == 1'b1) $display("#11, success taken branch");
else $display("#11, fail not taken branch");
#PERIOD;
CCR = 4'b1111;
branch = 1'b0;
jmp_type = 2'b11;
#PERIOD;
if (!(is_taken)) $display("#12, success not taken branch");
else $display("#12, fail taken branch");
#PERIOD;
$finish;
end
endmodule
| 7.184281 |
module branch_wait ( /*AUTOARG*/
// Outputs
pending_branches_arry,
// Inputs
clk,
rst,
alu_valid,
alu_branch,
alu_wfid,
f_salu_branch_en,
f_salu_branch_wfid
);
input clk, rst;
// Issued alu info
input alu_valid, alu_branch;
input [`WF_ID_LENGTH-1:0] alu_wfid;
// Salu signals with outcome of branch
input f_salu_branch_en;
input [`WF_ID_LENGTH-1:0] f_salu_branch_wfid;
// Output - list of pending branches
output [`WF_PER_CU-1:0] pending_branches_arry;
/**
* Branch wait is a reg that marks all wf with a pending branch.
* Pending branches start when a branch instruction is issued
* and end when salu signals the outcome of the branch
**/
wire alu_branch_valid;
wire [`WF_PER_CU-1:0] alu_branch_decoded, salu_branch_decoded;
wire [`WF_PER_CU-1:0] pending_branch, next_pending_branch;
assign pending_branches_arry = pending_branch;
// Decoder for the issued branch
decoder_6b_40b_en alu_brach_decoder (
.addr_in(alu_wfid),
.out(alu_branch_decoded),
.en(alu_branch_valid)
);
// Decoder for the finished branch by fetch
decoder_6b_40b_en issue_Value_decoder (
.addr_in(f_salu_branch_wfid),
.out(salu_branch_decoded),
.en(f_salu_branch_en)
);
dff pending_branch_ff[`WF_PER_CU-1:0] (
.q (pending_branch),
.d (next_pending_branch),
.clk(clk),
.rst(rst)
);
assign alu_branch_valid = alu_valid && alu_branch;
assign next_pending_branch = (pending_branch | (alu_branch_decoded)) & ~(salu_branch_decoded);
endmodule
| 7.425678 |
module single_port_memory #(
parameter ADDR_WIDTH = 5,
DATA_WIDTH = 32
) (
input wire clk,
input wire wt_en,
input wire [ADDR_WIDTH - 1:0] wtaddr,
input wire [DATA_WIDTH - 1:0] wtdata,
input wire [ADDR_WIDTH - 1:0] raddr1,
output wire [DATA_WIDTH - 1:0] rdata1
);
reg [DATA_WIDTH - 1:0] memory[(1 << ADDR_WIDTH) - 1:0];
always @(posedge clk) if (wt_en) memory[wtaddr] <= wtdata;
assign rdata1 = memory[raddr1];
endmodule
| 8.344917 |
module double_port_memory #(
parameter ADDR_WIDTH = 5,
DATA_WIDTH = 32
) (
input wire clk,
input wire wt_en,
input wire [ADDR_WIDTH - 1:0] wtaddr,
input wire [DATA_WIDTH - 1:0] wtdata,
input wire [ADDR_WIDTH - 1:0] raddr1,
input wire [ADDR_WIDTH - 1:0] raddr2,
output wire [DATA_WIDTH - 1:0] rdata1,
output wire [DATA_WIDTH - 1:0] rdata2
);
reg [DATA_WIDTH - 1:0] memory[(1 << ADDR_WIDTH) - 1:0];
always @(posedge clk) if (wt_en) memory[wtaddr] <= wtdata;
assign rdata1 = memory[raddr1];
assign rdata2 = memory[raddr2];
endmodule
| 8.44126 |
module triple_port_memory #(
parameter ADDR_WIDTH = 5,
DATA_WIDTH = 32
) (
input wire clk,
input wire wt_en,
input wire [ADDR_WIDTH - 1:0] wtaddr,
input wire [DATA_WIDTH - 1:0] wtdata,
input wire [ADDR_WIDTH - 1:0] raddr1,
input wire [ADDR_WIDTH - 1:0] raddr2,
input wire [ADDR_WIDTH - 1:0] raddr3,
output wire [DATA_WIDTH - 1:0] rdata1,
output wire [DATA_WIDTH - 1:0] rdata2,
output wire [DATA_WIDTH - 1:0] rdata3
);
reg [DATA_WIDTH - 1:0] memory[(1 << ADDR_WIDTH) - 1:0];
always @(posedge clk) if (wt_en) memory[wtaddr] <= wtdata;
assign rdata1 = memory[raddr1];
assign rdata2 = memory[raddr2];
assign rdata3 = memory[raddr3];
endmodule
| 8.595564 |
module log_update (
input wire branch,
input wire [9:0] old,
output reg [9:0] new_
);
reg [1:0] tar;
reg [1:0] learn;
always @(*) begin
case (old[9:8])
2'b00: begin
tar = old[1:0];
new_ = {old[8], branch, old[7:2], learn};
end
2'b01: begin
tar = old[3:2];
new_ = {old[8], branch, old[7:4], learn, old[1:0]};
end
2'b10: begin
tar = old[5:4];
new_ = {old[8], branch, old[7:6], learn, old[3:0]};
end
2'b11: begin
tar = old[7:6];
new_ = {old[8], branch, learn, old[5:0]};
end
endcase
end
always @(*) begin
if (branch) begin
case (tar)
2'b00: learn = 2'b01;
2'b01: learn = 2'b10;
2'b10: learn = 2'b11;
2'b11: learn = 2'b11;
endcase
end else begin
case (tar)
2'b00: learn = 2'b00;
2'b01: learn = 2'b00;
2'b10: learn = 2'b01;
2'b11: learn = 2'b10;
endcase
end
end
endmodule
| 7.493504 |
module para #(
parameter ADDR_WIDTH = 32,
HASH_DEPTH = 6,
PARA_WIDTH = 10
) (
input wire clk,
input wire rstn,
input wire erEn, // whether we need to erase
input wire [ADDR_WIDTH - 1:0] erPC, // erase place
input wire erLower, // how to erase the pair
input wire erUpper, // how to erase the pair
input wire bdEn, // whether we need to update
input wire [ADDR_WIDTH - 1:0] bdPC, // instruction PC
input wire bdKnown, // whether we know this instruction
input wire bdBack, // instruction branch direction
input wire [ 1:0] bdType, // instruction type
input wire bdBranch, // whether a branch is needed
// wire for prediction
input wire [ADDR_WIDTH - 1:0] ifPC,
/**
* structure of para (from high to low):
* name bits function
* fact 2 the jump-or-not note
* log 8 the experience for 11-10-01-00
* each case has 2 bits
*/
output wire ifVldLower,
output wire ifVldUpper,
output wire [PARA_WIDTH - 1:0] ifParaLower,
output wire [PARA_WIDTH - 1:0] ifParaUpper
);
wire [HASH_DEPTH - 1:0] erAddrLower = {erPC[HASH_DEPTH+1:3], 1'b0};
wire [HASH_DEPTH - 1:0] erAddrUpper = {erPC[HASH_DEPTH+1:3], 1'b1};
wire [HASH_DEPTH - 1:0] bdAddr = bdPC[HASH_DEPTH+1:2];
reg [(1 << HASH_DEPTH) - 1:0] vld;
always @(posedge clk) begin
if (!rstn) vld <= 64'b0;
else if (erEn) begin
// erPC needs to be invalidated
if (erLower) begin
vld[erAddrLower] <= 1'b0;
if (erAddrLower != bdAddr && bdEn) vld[bdAddr] <= 1'b1;
end
if (erUpper) begin
vld[erAddrUpper] <= 1'b0;
if (erAddrUpper != bdAddr && bdEn) vld[bdAddr] <= 1'b1;
end
end else if (bdEn) vld[bdAddr] <= 1'b1;
end
wire [HASH_DEPTH - 1:0] waddr_ex = bdPC[HASH_DEPTH+1:2];
wire [HASH_DEPTH - 1:0] raddr_ex = bdPC[HASH_DEPTH+1:2];
wire [HASH_DEPTH - 1:0] raddr_p1 = {ifPC[HASH_DEPTH+1:3], 1'b0};
wire [HASH_DEPTH - 1:0] raddr_p2 = {ifPC[HASH_DEPTH+1:3], 1'b1};
wire [PARA_WIDTH - 1:0] wdata_ex;
wire [PARA_WIDTH - 1:0] rdata_ex;
wire [PARA_WIDTH - 1:0] rdata_p1;
wire [PARA_WIDTH - 1:0] rdata_p2;
triple_port_memory #(
.ADDR_WIDTH(HASH_DEPTH),
.DATA_WIDTH(PARA_WIDTH)
) inst_para (
.clk (clk),
.wt_en (bdEn),
.wtaddr(waddr_ex),
.wtdata(wdata_ex),
.raddr1(raddr_ex),
.rdata1(rdata_ex),
.raddr2(raddr_p1),
.rdata2(rdata_p1),
.raddr3(raddr_p2),
.rdata3(rdata_p2)
);
wire [PARA_WIDTH - 1:0] init;
log_init log_init (
.branch(bdBranch),
.back (bdBack),
.type_ (bdType),
.log (init)
);
wire [PARA_WIDTH - 1:0] update;
log_update log_update (
.branch(bdBranch),
.old (rdata_ex),
.new_ (update)
);
assign wdata_ex = bdKnown ? update : init;
assign ifVldLower = vld[raddr_p1];
assign ifVldUpper = vld[raddr_p2];
assign ifParaLower = rdata_p1;
assign ifParaUpper = rdata_p2;
endmodule
| 7.748448 |
module BrCondArea ( // @[:@3.2]
input [31:0] io_rs1, // @[:@6.4]
input [31:0] io_rs2, // @[:@6.4]
input [ 2:0] io_br_type, // @[:@6.4]
output io_taken // @[:@6.4]
);
wire [32:0] _T_13; // @[BrCond.scala 37:21:@8.4]
wire [32:0] _T_14; // @[BrCond.scala 37:21:@9.4]
wire [31:0] diff; // @[BrCond.scala 37:21:@10.4]
wire neq; // @[BrCond.scala 38:19:@11.4]
wire eq; // @[BrCond.scala 39:14:@12.4]
wire _T_17; // @[BrCond.scala 40:26:@13.4]
wire _T_18; // @[BrCond.scala 40:45:@14.4]
wire isSameSign; // @[BrCond.scala 40:35:@15.4]
wire _T_19; // @[BrCond.scala 41:34:@16.4]
wire lt; // @[BrCond.scala 41:17:@18.4]
wire ltu; // @[BrCond.scala 42:17:@21.4]
wire ge; // @[BrCond.scala 43:14:@22.4]
wire geu; // @[BrCond.scala 44:14:@23.4]
wire _T_78; // @[BrCond.scala 46:18:@24.4]
wire _T_79; // @[BrCond.scala 46:29:@25.4]
wire _T_80; // @[BrCond.scala 47:18:@26.4]
wire _T_81; // @[BrCond.scala 47:29:@27.4]
wire _T_82; // @[BrCond.scala 46:36:@28.4]
wire _T_83; // @[BrCond.scala 48:18:@29.4]
wire _T_84; // @[BrCond.scala 48:29:@30.4]
wire _T_85; // @[BrCond.scala 47:37:@31.4]
wire _T_86; // @[BrCond.scala 49:18:@32.4]
wire _T_87; // @[BrCond.scala 49:29:@33.4]
wire _T_88; // @[BrCond.scala 48:36:@34.4]
wire _T_89; // @[BrCond.scala 50:18:@35.4]
wire _T_90; // @[BrCond.scala 50:30:@36.4]
wire _T_91; // @[BrCond.scala 49:36:@37.4]
wire _T_92; // @[BrCond.scala 51:18:@38.4]
wire _T_93; // @[BrCond.scala 51:30:@39.4]
wire _T_94; // @[BrCond.scala 50:38:@40.4]
assign _T_13 = io_rs1 - io_rs2; // @[BrCond.scala 37:21:@8.4]
assign _T_14 = $unsigned(_T_13); // @[BrCond.scala 37:21:@9.4]
assign diff = _T_14[31:0]; // @[BrCond.scala 37:21:@10.4]
assign neq = diff != 32'h0; // @[BrCond.scala 38:19:@11.4]
assign eq = neq == 1'h0; // @[BrCond.scala 39:14:@12.4]
assign _T_17 = io_rs1[31]; // @[BrCond.scala 40:26:@13.4]
assign _T_18 = io_rs2[31]; // @[BrCond.scala 40:45:@14.4]
assign isSameSign = _T_17 == _T_18; // @[BrCond.scala 40:35:@15.4]
assign _T_19 = diff[31]; // @[BrCond.scala 41:34:@16.4]
assign lt = isSameSign ? _T_19 : _T_17; // @[BrCond.scala 41:17:@18.4]
assign ltu = isSameSign ? _T_19 : _T_18; // @[BrCond.scala 42:17:@21.4]
assign ge = lt == 1'h0; // @[BrCond.scala 43:14:@22.4]
assign geu = ltu == 1'h0; // @[BrCond.scala 44:14:@23.4]
assign _T_78 = io_br_type == 3'h3; // @[BrCond.scala 46:18:@24.4]
assign _T_79 = _T_78 & eq; // @[BrCond.scala 46:29:@25.4]
assign _T_80 = io_br_type == 3'h6; // @[BrCond.scala 47:18:@26.4]
assign _T_81 = _T_80 & neq; // @[BrCond.scala 47:29:@27.4]
assign _T_82 = _T_79 | _T_81; // @[BrCond.scala 46:36:@28.4]
assign _T_83 = io_br_type == 3'h2; // @[BrCond.scala 48:18:@29.4]
assign _T_84 = _T_83 & lt; // @[BrCond.scala 48:29:@30.4]
assign _T_85 = _T_82 | _T_84; // @[BrCond.scala 47:37:@31.4]
assign _T_86 = io_br_type == 3'h5; // @[BrCond.scala 49:18:@32.4]
assign _T_87 = _T_86 & ge; // @[BrCond.scala 49:29:@33.4]
assign _T_88 = _T_85 | _T_87; // @[BrCond.scala 48:36:@34.4]
assign _T_89 = io_br_type == 3'h1; // @[BrCond.scala 50:18:@35.4]
assign _T_90 = _T_89 & ltu; // @[BrCond.scala 50:30:@36.4]
assign _T_91 = _T_88 | _T_90; // @[BrCond.scala 49:36:@37.4]
assign _T_92 = io_br_type == 3'h4; // @[BrCond.scala 51:18:@38.4]
assign _T_93 = _T_92 & geu; // @[BrCond.scala 51:30:@39.4]
assign _T_94 = _T_91 | _T_93; // @[BrCond.scala 50:38:@40.4]
assign io_taken = _T_94;
endmodule
| 7.719641 |
module Control ( // @[:@43.2]
input [31:0] io_inst, // @[:@46.4]
output [ 2:0] io_br_type // @[:@46.4]
);
wire [31:0] _T_35; // @[Lookup.scala 9:38:@48.4]
wire _T_36; // @[Lookup.scala 9:38:@49.4]
wire _T_40; // @[Lookup.scala 9:38:@51.4]
wire _T_44; // @[Lookup.scala 9:38:@53.4]
wire [31:0] _T_47; // @[Lookup.scala 9:38:@54.4]
wire _T_48; // @[Lookup.scala 9:38:@55.4]
wire _T_52; // @[Lookup.scala 9:38:@57.4]
wire _T_56; // @[Lookup.scala 9:38:@59.4]
wire _T_60; // @[Lookup.scala 9:38:@61.4]
wire _T_64; // @[Lookup.scala 9:38:@63.4]
wire _T_68; // @[Lookup.scala 9:38:@65.4]
wire _T_72; // @[Lookup.scala 9:38:@67.4]
wire [2:0] _T_508; // @[Lookup.scala 11:37:@430.4]
wire [2:0] _T_509; // @[Lookup.scala 11:37:@431.4]
wire [2:0] _T_510; // @[Lookup.scala 11:37:@432.4]
wire [2:0] _T_511; // @[Lookup.scala 11:37:@433.4]
wire [2:0] _T_512; // @[Lookup.scala 11:37:@434.4]
wire [2:0] _T_513; // @[Lookup.scala 11:37:@435.4]
wire [2:0] _T_514; // @[Lookup.scala 11:37:@436.4]
wire [2:0] _T_515; // @[Lookup.scala 11:37:@437.4]
wire [2:0] _T_516; // @[Lookup.scala 11:37:@438.4]
wire [2:0] ctrlSignals_5; // @[Lookup.scala 11:37:@439.4]
assign _T_35 = io_inst & 32'h7f; // @[Lookup.scala 9:38:@48.4]
assign _T_36 = 32'h37 == _T_35; // @[Lookup.scala 9:38:@49.4]
assign _T_40 = 32'h17 == _T_35; // @[Lookup.scala 9:38:@51.4]
assign _T_44 = 32'h6f == _T_35; // @[Lookup.scala 9:38:@53.4]
assign _T_47 = io_inst & 32'h707f; // @[Lookup.scala 9:38:@54.4]
assign _T_48 = 32'h67 == _T_47; // @[Lookup.scala 9:38:@55.4]
assign _T_52 = 32'h63 == _T_47; // @[Lookup.scala 9:38:@57.4]
assign _T_56 = 32'h1063 == _T_47; // @[Lookup.scala 9:38:@59.4]
assign _T_60 = 32'h4063 == _T_47; // @[Lookup.scala 9:38:@61.4]
assign _T_64 = 32'h5063 == _T_47; // @[Lookup.scala 9:38:@63.4]
assign _T_68 = 32'h6063 == _T_47; // @[Lookup.scala 9:38:@65.4]
assign _T_72 = 32'h7063 == _T_47; // @[Lookup.scala 9:38:@67.4]
assign _T_508 = _T_72 ? 3'h4 : 3'h0; // @[Lookup.scala 11:37:@430.4]
assign _T_509 = _T_68 ? 3'h1 : _T_508; // @[Lookup.scala 11:37:@431.4]
assign _T_510 = _T_64 ? 3'h5 : _T_509; // @[Lookup.scala 11:37:@432.4]
assign _T_511 = _T_60 ? 3'h2 : _T_510; // @[Lookup.scala 11:37:@433.4]
assign _T_512 = _T_56 ? 3'h6 : _T_511; // @[Lookup.scala 11:37:@434.4]
assign _T_513 = _T_52 ? 3'h3 : _T_512; // @[Lookup.scala 11:37:@435.4]
assign _T_514 = _T_48 ? 3'h0 : _T_513; // @[Lookup.scala 11:37:@436.4]
assign _T_515 = _T_44 ? 3'h0 : _T_514; // @[Lookup.scala 11:37:@437.4]
assign _T_516 = _T_40 ? 3'h0 : _T_515; // @[Lookup.scala 11:37:@438.4]
assign ctrlSignals_5 = _T_36 ? 3'h0 : _T_516; // @[Lookup.scala 11:37:@439.4]
assign io_br_type = ctrlSignals_5;
endmodule
| 7.518923 |
module brdclk ( // Clock in ports
input CLK_IN1_P,
input CLK_IN1_N,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFGDS clkin1_buf (
.O (clkin1),
.I (CLK_IN1_P),
.IB(CLK_IN1_N)
);
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_DIVIDE_F (125.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010)
) mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_unused),
.CLKINSTOPPED(clkinstopped_unused),
.CLKFBSTOPPED(clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0)
);
// Output buffering
//-----------------------------------
BUFG clkf_buf (
.O(clkfbout_buf),
.I(clkfbout)
);
BUFG clkout1_buf (
.O(CLK_OUT1),
.I(clkout0)
);
endmodule
| 6.569787 |
module brdclk_pll ( // Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCM_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (8.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (100),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (8.000),
.REF_JITTER1 (0.010)
) mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED(clkinstopped_unused),
.CLKFBSTOPPED(clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0)
);
// Output buffering
//-----------------------------------
BUFG clkf_buf (
.O(clkfbout_buf),
.I(clkfbout)
);
BUFG clkout1_buf (
.O(CLK_OUT1),
.I(clkout0)
);
BUFG clkout2_buf (
.O(CLK_OUT2),
.I(clkout1)
);
endmodule
| 6.849456 |
module Breadboard(a,b,opcode,clk,select);
//---------------------------------------------
//Parameters
//---------------------------------------------
input [15:0] a , b;
input [3:0] opcode;
input clk;
input [11:0] select;
wire [15:0] andG, nandout;
wire [15:0] or_output, nor_output;
wire [15:0] xor_output,xnor_output;
wire [15:0] notout;
wire [15:0] addsub;
wire [15:0] shLeft, shRight;
wire [15:0] muxOut;
//---------------------------------------------
//Local Variables
//---------------------------------------------
reg overflow;
reg [15:0] finalOutput;
//==Create the two Flip-Flops, and plug them into the circuit
decoder regular_decoder(opcode, select);
DFF A(clk, a, dff_a_out) ;
DFF B(clk, b, dff_b_out) ;
andnand_gate and_nand_1 (a, b, clk, andG, nandout);
orMod or_mod_1 (a,b,clk,or_output,nor_output);
xorMod xor_mod_1(a,b,clk,xor_output,xnor_output);
not_gate not_gate_1 (a,clk, notout);
ripple_carry_adder_subtractor rpc_adder_sub_1(addsub, 1'b0, overflow, a, b, select[8]);
shifter shifter_1(a, clk, shLeft, shRight);
accum accumulater_1(muxOut, finalOutput);
//==The MUX with its inputs, the select, and its output
mainMux mux(addsub,shRight,shLeft,andG,or_output,xor_output,xnor_output,nandout,nor_output,notout,RESET,select,muxOut);
state={A.dff_a_out,B.dff_b_out};//Set the state equal to the value of the flip flops
endmodule
| 7.122972 |
module Test_FSM() ;
//---------------------------------------------
//Inputs
//---------------------------------------------
reg [15:0] a , b;
reg [3:0] opcode;
reg clk;
reg [11:0] select;
//---------------------------------------------
//Declare FSM
//---------------------------------------------
Breadboard ALU(a,b,opcode,clk,select);
//---------------------------------------------
//The Display Thread with Clock Control
//---------------------------------------------
initial
begin
forever
begin
#5
clk = 0 ;
#5
clk = 1 ;
end
end
//---------------------------------------------
//The Display Thread with Clock Control
//---------------------------------------------
initial
begin
#1 ///Offset the Square Wave
$display(" A | B |OPCOD|Current|OUTPUT|NEXTSTATE");
$display("----------+----+-----+-------+------+---------|");
forever
begin
#5
$display(" %16b | %16b | %4b | %b| %b|",a,b,opcode,ALU.state,ALU.finalOutput,ALU.state);
oldval=ALU.state;
end
end
//---------------------------------------------
// The Input Stimulous.
// Flipping the switch up and down.
//---------------------------------------------
initial
begin
#2 //Offset the Square Wave
#10 opcode = opADD; a = 16'0000000000000001; b = 16'0000000000000001;
#10 opcode = opSUB; a = 16'0000000000000010; b = 16'0000000000000001;
#10 opcode = opSHLEFT; a = 16'0100000000000010;
#10 opcode = opSHRIGHT; a = 16'0100000000000010;
#10 opcode = opNOT; a = 16'0000000000000010;
#10 opcode = opOR; a = 16'0000000000000010; b = 16'0000000000000011;
#10 opcode = opNOR; a = 16'0000000000000010; b = 16'0000000000000011;
#10 opcode = opXOR; a = 16'0000000000000010; b = 16'0000000000000011;
#10 opcode = opXNOR; a = 16'0000000000000010; b = 16'0000000000000011;
#10 opcode = opAND; a = 16'0000000000000010; b = 16'0000000000000011;
#10 opcode = opNAND; a = 16'0000000000000010; b = 16'0000000000000011;
$finish;
end
endmodule
| 7.075415 |
module breakout_DE2 (
input CLOCK_50, // 50 MHz
input [0:0] KEY,
input [17:0] SW,
output VGA_CLK, // VGA Clock
output VGA_HS, // VGA H_SYNC
output VGA_VS, // VGA V_SYNC
output VGA_BLANK, // VGA BLANK
output VGA_SYNC, // VGA SYNC
output [ 9:0] VGA_R, // VGA Red[9:0]
output [ 9:0] VGA_G, // VGA Green[9:0]
output [ 9:0] VGA_B, // VGA Blue[9:0]
output [17:0] LEDR,
output [2:0] LEDG,
// Audio IO
input AUD_ADCDAT,
inout AUD_BCLK,
inout AUD_ADCLRCK,
inout AUD_DACLRCK,
inout I2C_SDAT,
output AUD_XCK,
output AUD_DACDAT,
output I2C_SCLK,
// Keyboard stuff
inout PS2_CLK,
inout PS2_DAT,
// Score to 7 segment hex display
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
//LCD Module 16X2
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA // LCD Data bus 8 bits
);
assign LEDR[2:0] = SW[2:0];
assign LEDR[17:16] = SW[17:16];
wire [2:0] color;
wire [7:0] plot_x;
wire [6:0] plot_y;
wire plot;
processor(
.clk(CLOCK_50),
.reset(~KEY[0]),
.SW(SW[2:0]),
.MODE(SW[17:16]),
//.game_start (SW[0]),
//.right_button (SW[1]),
//.left_button (SW[2]),
.plot_x(plot_x),
.plot_y(plot_y),
.color(color),
.plot(plot),
.LEDG(LEDG[2:0]),
// Audio
.AUD_ADCDAT(AUD_ADCDAT),
.AUD_BCLK(AUD_BCLK),
.AUD_ADCLRCK(AUD_ADCLRCK),
.AUD_DACLRCK(AUD_DACLRCK),
.I2C_SDAT(I2C_SDAT),
.AUD_XCK(AUD_XCK),
.AUD_DACDAT(AUD_DACDAT),
.I2C_SCLK(I2C_SCLK),
// Keyboard
.PS2_CLK(PS2_CLK),
.PS2_DAT(PS2_DAT),
// score to seven segment hex display
.HEX0(HEX0),
.HEX1(HEX1),
.HEX2(HEX2),
// LCD Display
.LCD_ON(LCD_ON),
.LCD_BLON(LCD_BLON),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_RS(LCD_RS),
.LCD_DATA(LCD_DATA)
);
vga_adapter VGA (
.resetn(KEY[0]),
.clock(CLOCK_50),
.colour(color),
.x(plot_x),
.y(plot_y),
.plot(plot),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK),
.VGA_SYNC(VGA_SYNC),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "breakout_background.mif";
// score stuff with RAM
endmodule
| 9.670132 |
module breakout_top (
input clk,
rst_n,
input [1:0] key, //move the paddle
output [4:0] vga_out_r,
output [5:0] vga_out_g,
output [4:0] vga_out_b,
output vga_out_vs,
vga_out_hs
);
//FSM for the whole pong game
localparam [1:0] newgame = 0, play = 1, newball = 2, over = 3;
wire clk_out;
wire video_on;
wire [11:0] pixel_x, pixel_y;
wire graph_on;
wire [4:0] text_on;
wire miss, won;
reg won_q, won_d;
wire [2:0] rgb_graph, rgb_text;
reg [2:0] rgb;
reg [1:0] state_q, state_d;
reg pause, restart;
reg [2:0] ball_q = 0, ball_d;
reg timer_start;
wire timer_tick, timer_up;
//register operation for updating balls left and the current state of game
always @(posedge clk_out, negedge rst_n) begin
if (!rst_n) begin
state_q <= 0;
ball_q <= 0;
won_q <= 0;
end else begin
state_q <= state_d;
ball_q <= ball_d;
won_q <= won_d;
end
end
//FSM next-state logic
always @* begin
state_d = state_q;
ball_d = ball_q;
pause = 0;
restart = 0;
timer_start = 0;
won_d = won_q;
case (state_q)
newgame: begin
restart = 1; //3 balls will be restored at the start
ball_d = 3;
won_d = 0;
if (key != 2'b11) begin //only when any of the button is pressed will the game start
ball_d = ball_q - 1;
state_d = play;
end
end
play:
if(miss || won) begin //game continues until the player misses the ball or the ball went past through the left border(all walls broken)
won_d = won;
if (miss) ball_d = (ball_q == 0) ? 0 : ball_q - 1;
if (ball_q == 0 || won) state_d = over;
else state_d = newball;
timer_start = 1;
end
newball: begin //after the player misses, 2 seconds will be alloted before the game can start again(as long as there are still balls left)
pause = 1;
if (timer_up && key != 2'b11) state_d = play;
end
over: begin
pause = 1;
if (timer_up) state_d = newgame;
end
default: state_d = newgame;
endcase
end
//rgb multiplexing
always @* begin
rgb = 0;
if (!video_on) rgb = 0;
else begin
if (text_on[4] || (text_on[3] && state_q == newgame) || (text_on[2] && state_q == over))
rgb = rgb_text; //{ball_on,rule_on,gameover_on,win_on,logo_on};
else if (graph_on) rgb = rgb_graph;
else if (text_on[0])
rgb = rgb_text; //logo is at the last hierarchy since this must be the most underneath text
else rgb = 3'b011; //background
end
end
assign vga_out_r = {5{rgb[2]}};
assign vga_out_g = {6{rgb[1]}};
assign vga_out_b = {5{rgb[0]}};
assign timer_tick = (pixel_x == 0 && pixel_y == 500);
dcm_25MHz m0 ( // Clock in ports
.clk (clk), // IN
// Clock out ports
.clk_out(clk_out), // OUT
// Status and control signals
.RESET (RESET), // IN
.LOCKED (LOCKED)
);
vga_core m1 (
.clk(clk_out),
.rst_n(rst_n), //clock must be 25MHz for 640x480
.hsync(vga_out_hs),
.vsync(vga_out_vs),
.video_on(video_on),
.pixel_x(pixel_x),
.pixel_y(pixel_y)
);
pong_animated m2 //control logic for any graphs on the game
(
.clk(clk_out),
.rst_n(rst_n),
.video_on(video_on),
.pause(pause), //pause=stop state after missing a ball , restart=stop state at the beginning of new game
.restart(restart),
.key(key),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.rgb(rgb_graph),
.graph_on(graph_on),
.miss(miss), //miss=ball went past the paddle , won=when ball went past the left border
.won(won)
);
pong_text m3 //control logic for any text on the game
(
.clk(clk_out),
.rst_n(rst_n),
.video_on(video_on),
.won(won_q),
.pixel_x(pixel_x),
.pixel_y(pixel_y),
.ball(ball_q),
.rgb_text(rgb_text),
.text_on(text_on) //{score_on,rule_on,gameover_on,logo_on}
);
timer m4 //2 second timer which will be used for "resting" before restarting the game
(
.clk(clk_out),
.rst_n(rst_n),
.timer_start(timer_start),
.timer_tick(timer_tick),
.timer_up(timer_up)
);
endmodule
| 7.787505 |
module breakout_top_an (
clk,
btnC,
btnU,
btnD,
Hsync,
Vsync,
vgaRed,
vgaGreen,
vgaBlue,
an,
seg
);
input clk, btnC, btnU, btnD;
output Hsync, Vsync;
output [3:0] vgaRed, vgaGreen, vgaBlue;
output [3:0] an;
output [6:0] seg;
// signals
wire [10:0] pixel_x, pixel_y;
wire video_on, pixel_tick;
reg [3:0] vgaRed_reg, vgaGreen_reg, vgaBlue_reg;
wire [3:0] vgaRed_next, vgaGreen_next, vgaBlue_next;
wire [15:0] score;
//----------------------- BODY ---------------------------//
// VGA Sync Circuit
vga_sync sync_unit (
.clk(clk),
.reset(btnC),
.Hsync(Hsync),
.Vsync(Vsync),
.video_on(video_on),
.p_tick(pixel_tick),
.pixel_x(pixel_x),
.pixel_y(pixel_y)
);
// Graphic Generator
breakout_graph_animate breakout_graph_an_unit (
.clk(clk),
.reset(btnC),
.btnU(btnU),
.btnD(btnD),
.video_on(video_on),
.pix_x(pixel_x),
.pix_y(pixel_y),
.vgaRed(vgaRed_next),
.vgaGreen(vgaGreen_next),
.vgaBlue(vgaBlue_next),
.score(score)
);
// Seven segment display
b_10 b_10_counter (
.clk (clk),
.btnC(btnC),
.sw (score),
.an (an),
.seg (seg)
);
// RBG Buffer
always @(posedge clk)
if (pixel_tick) begin
vgaRed_reg <= vgaRed_next;
vgaGreen_reg <= vgaGreen_next;
vgaBlue_reg <= vgaBlue_next;
end
// Output
assign vgaRed = vgaRed_reg;
assign vgaGreen = vgaGreen_reg;
assign vgaBlue = vgaBlue_reg;
endmodule
| 7.974994 |
module,
// which provide a hardware-level single
// break point support.
//
`timescale 1ns / 1ps
module Breakpoint (
input valid, // indicate whether the hit is taken.
input sampler, // drive the updating of break point
input [2:0] digit_sel, // select a digit to write in a 4-word address.
input [3:0] hex_digit, // hexadecimal digit to write.
input [29:0] pc, // the program counter to be compared, 4B-aligned.
output [31:0] break_point,
output hit
);
reg [31:0] bp_pc;
assign break_point = bp_pc;
assign hit = valid & (bp_pc == { pc, 2'b00 });
wire [4:0] bit_offset = { digit_sel, 2'b00 };
always @(posedge sampler) begin
bp_pc[ bit_offset +: 4 ] <= hex_digit;
end
endmodule
| 8.141716 |
module BreakpointUnit (
input clock,
input reset,
input io_status_debug,
input io_status_cease,
input io_status_wfi,
input [31:0] io_status_isa,
input [ 1:0] io_status_dprv,
input [ 1:0] io_status_prv,
input io_status_sd,
input [26:0] io_status_zero2,
input [ 1:0] io_status_sxl,
input [ 1:0] io_status_uxl,
input io_status_sd_rv32,
input [ 7:0] io_status_zero1,
input io_status_tsr,
input io_status_tw,
input io_status_tvm,
input io_status_mxr,
input io_status_sum,
input io_status_mprv,
input [ 1:0] io_status_xs,
input [ 1:0] io_status_fs,
input [ 1:0] io_status_mpp,
input [ 1:0] io_status_vs,
input io_status_spp,
input io_status_mpie,
input io_status_hpie,
input io_status_spie,
input io_status_upie,
input io_status_mie,
input io_status_hie,
input io_status_sie,
input io_status_uie,
input [38:0] io_pc,
input [38:0] io_ea,
output io_xcpt_if,
output io_xcpt_ld,
output io_xcpt_st,
output io_debug_if,
output io_debug_ld,
output io_debug_st
);
assign io_xcpt_if = 1'h0; // @[Breakpoint.scala 74:14]
assign io_xcpt_ld = 1'h0; // @[Breakpoint.scala 75:14]
assign io_xcpt_st = 1'h0; // @[Breakpoint.scala 76:14]
assign io_debug_if = 1'h0; // @[Breakpoint.scala 77:15]
assign io_debug_ld = 1'h0; // @[Breakpoint.scala 78:15]
assign io_debug_st = 1'h0; // @[Breakpoint.scala 79:15]
endmodule
| 8.021329 |
module BreakpointUnit_4 (
input clock,
input reset,
input io_status_debug,
input io_status_cease,
input io_status_wfi,
input [31:0] io_status_isa,
input [ 1:0] io_status_dprv,
input [ 1:0] io_status_prv,
input io_status_sd,
input [26:0] io_status_zero2,
input [ 1:0] io_status_sxl,
input [ 1:0] io_status_uxl,
input io_status_sd_rv32,
input [ 7:0] io_status_zero1,
input io_status_tsr,
input io_status_tw,
input io_status_tvm,
input io_status_mxr,
input io_status_sum,
input io_status_mprv,
input [ 1:0] io_status_xs,
input [ 1:0] io_status_fs,
input [ 1:0] io_status_mpp,
input [ 1:0] io_status_vs,
input io_status_spp,
input io_status_mpie,
input io_status_hpie,
input io_status_spie,
input io_status_upie,
input io_status_mie,
input io_status_hie,
input io_status_sie,
input io_status_uie,
input [38:0] io_pc,
input [38:0] io_ea,
output io_xcpt_if,
output io_xcpt_ld,
output io_xcpt_st,
output io_debug_if,
output io_debug_ld,
output io_debug_st
);
assign io_xcpt_if = 1'h0; // @[Breakpoint.scala 74:14]
assign io_xcpt_ld = 1'h0; // @[Breakpoint.scala 75:14]
assign io_xcpt_st = 1'h0; // @[Breakpoint.scala 76:14]
assign io_debug_if = 1'h0; // @[Breakpoint.scala 77:15]
assign io_debug_ld = 1'h0; // @[Breakpoint.scala 78:15]
assign io_debug_st = 1'h0; // @[Breakpoint.scala 79:15]
endmodule
| 8.021329 |
module Breath (
input wire system_clk,
output wire [15:0] light
);
wire rst_n;
assign rst_n = 1;
reg [6:0] cnt1 = 0;
reg [9:0] cnt2 = 0;
reg [9:0] cnt3 = 0;
wire delay_1us;
wire delay_1ms;
wire delay_1s;
//ʱ1us
always @(posedge system_clk or negedge rst_n) begin
if (!rst_n) cnt1 <= 6'b0;
else if (cnt1 < 7'd100) cnt1 <= cnt1 + 1'b1;
else cnt1 <= 6'b0;
end
assign delay_1us = (cnt1 == 7'd99) ? 1'b1 : 1'b0; //100M/1000
//ʱ1ms
always @(posedge system_clk or negedge rst_n) begin
if (!rst_n) cnt2 <= 10'b0;
else if (delay_1us) begin
if (cnt2 < 10'd999) cnt2 <= cnt2 + 1'b1;
else cnt2 <= 10'b0;
end
end
assign delay_1ms = ((delay_1us == 1'b1) && (cnt2 == 10'd999)) ? 1'b1 : 1'b0;
//ʱ1s
always @(posedge system_clk or negedge rst_n) begin
if (!rst_n) cnt3 <= 10'b0;
else if (delay_1ms) begin
if (cnt3 < 10'd999) cnt3 <= cnt3 + 1'b1;
else cnt3 <= 10'b0;
end
end
assign delay_1s = ((delay_1ms == 1'b1) && (cnt3 == 10'd999)) ? 1'b1 : 1'b0;
reg display_state = 0;
//state change
always @(posedge system_clk or negedge rst_n) begin
if (!rst_n) display_state <= 1'b0;
else if (delay_1s) //ÿһлһledʾ״̬
display_state <= ~display_state;
else display_state <= display_state;
end
reg pwm = 0;
//pwmźŵIJ
always @(posedge system_clk or negedge rst_n) begin
if (!rst_n) pwm <= 1'b0;
else
case (display_state)
1'b0: pwm <= (cnt2 < cnt3) ? 1'b1 : 1'b0;
1'b1: pwm <= (cnt2 < cnt3) ? 1'b0 : 1'b1;
default: pwm <= pwm;
endcase
end
assign light = {15{pwm}};
endmodule
| 6.615179 |
module breathe (
input clk,
output reg breathe_sin,
output reg breathe_cos
);
parameter PREDIVIDER = 5;
// Predivider to select blink frequency
reg [PREDIVIDER:0] prediv = 0;
always @(posedge clk) prediv <= prediv + 1;
// Minsky circle algorithm
reg [20:0] sine = 0;
reg [20:0] cosine = 1 << 19;
always @(posedge clk)
if (prediv == 0) begin
cosine = $signed(cosine) - ($signed(sine) >>> 17);
sine = $signed(sine) + ($signed(cosine) >>> 17);
end
// Exponential function approximation
wire [ 7:0] scaled_sin = 8'd167 + sine[20:13];
wire [31:0] exp_sin = {1'b1, scaled_sin[2:0]} << scaled_sin[7:3];
wire [ 7:0] scaled_cos = 8'd167 + cosine[20:13];
wire [31:0] exp_cos = {1'b1, scaled_cos[2:0]} << scaled_cos[7:3];
// Sigma-delta modulator
reg [31:0] phase_sin = 0;
reg [31:0] phase_cos = 0;
wire [32:0] phase_sin_new = phase_sin + exp_sin;
wire [32:0] phase_cos_new = phase_cos + exp_cos;
always @(posedge clk) begin
phase_sin <= phase_sin_new[31:0];
phase_cos <= phase_cos_new[31:0];
breathe_sin <= phase_sin_new[32];
breathe_cos <= phase_cos_new[32];
end
endmodule
| 6.811201 |
module breath_led #(
parameter CNT_1US_MAX = 6'd49,
parameter CNT_1MS_MAX = 10'd999,
parameter CNT_1S_MAX = 10'd999
) (
input wire sys_clk, //系统时钟50Mhz
input wire sys_rst_n, //全局复位
output reg led_out //输出信号，控制led灯
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//reg define
reg [5:0] cnt_1us;
reg [9:0] cnt_1ms;
reg [9:0] cnt_1s;
reg cnt_1s_flag;
//********************************************************************/
//***************************** Main Code ****************************//
//********************************************************************//
//cnt_1us:1us计数器
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_1us <= 6'b0;
else if (cnt_1us == CNT_1US_MAX) cnt_1us <= 6'b0;
else cnt_1us <= cnt_1us + 1'b1;
//cnt_1ms:1ms计数器
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_1ms <= 10'b0;
else if (cnt_1ms == CNT_1MS_MAX && cnt_1us == CNT_1US_MAX) cnt_1ms <= 10'b0;
else if (cnt_1us == CNT_1US_MAX) cnt_1ms <= cnt_1ms + 1'b1;
//cnt_1s:1s计数器
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_1s <= 10'b0;
else if (cnt_1s == CNT_1S_MAX && cnt_1ms == CNT_1MS_MAX && cnt_1us == CNT_1US_MAX)
cnt_1s <= 10'b0;
else if (cnt_1ms == CNT_1MS_MAX && cnt_1us == CNT_1US_MAX) cnt_1s <= cnt_1s + 1'b1;
//cnt_1s_flag:1s计数器标志信号
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_1s_flag <= 1'b0;
else if (cnt_1s == CNT_1S_MAX && cnt_1ms == CNT_1MS_MAX && cnt_1us == CNT_1US_MAX)
cnt_1s_flag <= ~cnt_1s_flag;
//led_out:输出信号连接到外部的led灯
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) led_out <= 1'b0;
else if ((cnt_1s_flag == 1'b1 && cnt_1ms < cnt_1s) || (cnt_1s_flag == 1'b0 && cnt_1ms > cnt_1s))
led_out <= 1'b0;
else led_out <= 1'b1;
endmodule
| 7.325783 |
module Bregister (
clk, // <i
Lb, // <i
busIn, // <i
Bvalue // >o
);
input clk, Lb;
input [7:0] busIn;
output [7:0] Bvalue;
reg [7:0] Bvalue;
initial begin
Bvalue = 8'd0;
end
always @(posedge clk) begin
if (Lb) begin
Bvalue = busIn;
end else begin
Bvalue = Bvalue;
end
end
endmodule
| 6.770721 |
module bReg (
clk,
alu_dataOut_2,
bReg_out
);
input clk;
input [31:0] alu_dataOut_2;
output reg [31:0] bReg_out;
always @(posedge clk) begin
bReg_out <= alu_dataOut_2;
end
endmodule
| 6.827944 |
module ppa_black (
gin,
pin,
gout,
pout
);
input [1:0] gin, pin;
output gout, pout;
and2 U1 (
pout,
pin[1],
pin[0]
);
ao21 U2 (
gout,
gin[0],
pin[1],
gin[1]
);
endmodule
| 7.287792 |
module ppa_buffer (
pin,
gin,
pout,
gout
);
input pin, gin;
output pout, gout;
buffer U1 (
pout,
pin
);
buffer U2 (
gout,
gin
);
endmodule
| 7.359153 |
module ppa_pre (
a_in,
b_in,
pout,
gout
);
input a_in, b_in;
output pout, gout;
xor2 U1 (
pout,
a_in,
b_in
);
and2 U2 (
gout,
a_in,
b_in
);
endmodule
| 7.554997 |
module ppa_grey (
gin,
pin,
gout
);
input [1:0] gin;
input pin;
output gout;
ao21 U1 (
gout,
gin[0],
pin,
gin[1]
);
endmodule
| 7.351436 |
module ppa_post (
pin,
gin,
sum
);
input pin, gin;
output sum;
xor2 U1 (
sum,
pin,
gin
);
endmodule
| 7.071112 |
module: BrentKung32Bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module BrentKung32Bit_tb;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg Cin;
// Outputs
wire [31:0] S;
wire Cout;
// Instantiate the Unit Under Test (UUT)
BrentKung32Bit uut (
.A(A),
.B(B),
.Cin(Cin),
.S(S),
.Cout(Cout)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
Cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
A = 32'hFFFF0000;
B = 32'h0000FFFF;
Cin = 1;
#300;
A = 32'd2017701177;
B = 32'd1701853;
Cin = 0;
#300;
A = 32'hFFABCEDC;
B = 32'hEF821EDA;
Cin = 1;
end
endmodule
| 7.154462 |
module brent_kung16bit (
a,
b,
sum,
cin,
carry
);
input [15:0] a;
input [15:0] b;
input cin;
output [15:0] sum;
output carry;
wire [15:0] p;
wire [15:0] g;
wire [ 7:0] p2;
wire [ 7:0] g2;
wire [ 3:0] p3;
wire [ 3:0] g3;
wire [ 1:0] g4;
wire [ 1:0] p4;
wire [15:0] c;
wire g5, p5;
assign c[0] = cin;
// Propagation 1st order
assign p[0] = a[0] ^ b[0];
assign p[1] = a[1] ^ b[1];
assign p[2] = a[2] ^ b[2];
assign p[3] = a[3] ^ b[3];
assign p[4] = a[4] ^ b[4];
assign p[5] = a[5] ^ b[5];
assign p[6] = a[6] ^ b[6];
assign p[7] = a[7] ^ b[7];
assign p[8] = a[8] ^ b[8];
assign p[9] = a[9] ^ b[9];
assign p[10] = a[10] ^ b[10];
assign p[11] = a[11] ^ b[11];
assign p[12] = a[12] ^ b[12];
assign p[13] = a[13] ^ b[13];
assign p[14] = a[14] ^ b[14];
assign p[15] = a[15] ^ b[15];
// Generation 1st order
assign g[0] = a[0] & b[0];
assign g[1] = a[1] & b[1];
assign g[2] = a[2] & b[2];
assign g[3] = a[3] & b[3];
assign g[4] = a[4] & b[4];
assign g[5] = a[5] & b[5];
assign g[6] = a[6] & b[6];
assign g[7] = a[7] & b[7];
assign g[8] = a[8] & b[8];
assign g[9] = a[9] & b[9];
assign g[10] = a[10] & b[10];
assign g[11] = a[11] & b[11];
assign g[12] = a[12] & b[12];
assign g[13] = a[13] & b[13];
assign g[14] = a[14] & b[14];
assign g[15] = a[15] & b[15];
//Propagation 2nd order
assign p2[0] = p[0] & p[1];
assign p2[1] = p[3] & p[2];
assign p2[2] = p[5] & p[4];
assign p2[3] = p[7] & p[6];
assign p2[4] = p[9] & p[8];
assign p2[5] = p[11] & p[10];
assign p2[6] = p[13] & p[12];
assign p2[7] = p[15] & p[14];
//generation second order
assign g2[0] = g[1] | (p[1] & g[0]);
assign g2[1] = g[3] | (p[3] & g[2]);
assign g2[2] = g[5] | (p[5] & g[4]);
assign g2[3] = g[7] | (p[7] & g[6]);
assign g2[4] = g[9] | (p[9] & g[8]);
assign g2[5] = g[11] | (p[11] & g[10]);
assign g2[6] = g[13] | (p[13] & g[12]);
assign g2[7] = g[15] | (p[15] & g[14]);
//third order propagation
assign p3[0] = p2[1] & p2[0];
assign p3[1] = p2[2] & p2[3];
assign p3[2] = p2[4] & p2[5];
assign p3[3] = p2[6] & p2[7];
// third order generation
assign g3[0] = g2[1] | (p2[1] & g2[0]);
assign g3[1] = g2[3] | (p2[3] & g2[2]);
assign g3[2] = g2[5] | (p2[5] & g2[4]);
assign g3[3] = g2[7] | (p2[7] & g2[6]);
//fourth order
assign g4[0] = g3[1] | (p3[1] & g3[0]);
assign g4[1] = g3[3] | (p3[3] & g3[2]);
assign p4[0] = p3[1] & p3[0];
assign p4[1] = p3[3] & p3[2];
// fifth order
assign p5 = p4[0] & p4[1];
assign g5 = g4[1] | (p4[1] & g4[0]);
// intermediate carry
assign c[1] = g[0] | (p[0] & c[0]);
assign c[2] = g2[0] | (p2[0] & c[0]);
assign c[4] = g3[0] | (p3[0] & c[0]);
assign c[8] = g4[0] | (p4[0] & c[0]);
assign carry = g5 | (p5 & c[0]);
assign c[3] = g[2] | (p[2] & c[2]);
assign c[5] = g[4] | (p[4] & c[4]);
assign c[6] = g2[2] | (p2[2] & c[4]);
assign c[7] = g[6] | (p[6] & c[6]);
assign c[9] = g[8] | (p[8] & c[8]);
assign c[10] = g2[4] | (p2[4] & c[8]);
assign c[11] = g[10] | (p[10] & c[10]);
assign c[12] = g3[2] | (p3[2] & c[8]);
assign c[13] = g[12] | (p[12] & c[12]);
assign c[14] = g[13] | (p[13] & c[13]);
assign c[15] = g[14] | (p[14] & c[14]);
//sum
assign sum[0] = p[0] ^ c[0];
assign sum[1] = p[1] ^ c[1];
assign sum[2] = p[2] ^ c[2];
assign sum[3] = p[3] ^ c[3];
assign sum[4] = p[4] ^ c[4];
assign sum[5] = p[5] ^ c[5];
assign sum[6] = p[6] ^ c[6];
assign sum[7] = p[7] ^ c[7];
assign sum[8] = p[8] ^ c[8];
assign sum[9] = p[9] ^ c[9];
assign sum[10] = p[10] ^ c[10];
assign sum[11] = p[11] ^ c[11];
assign sum[12] = p[12] ^ c[12];
assign sum[13] = p[13] ^ c[13];
assign sum[14] = p[14] ^ c[14];
assign sum[15] = p[15] ^ c[15];
endmodule
| 6.630644 |
module test_brent_kung_16;
// Inputs
reg [15:0] in1;
reg [15:0] in2;
reg cin;
// Outputs
wire [15:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
brent_kung_16 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 16'b0000000000000001;
in2 = 16'b0000000000000000;
cin = 1'b0;
#10 in1 = 16'b0000000000001010;
in2 = 16'b0000000000000011;
cin = 1'b0;
#10 in1 = 16'b1101000000000000;
in2 = 16'b1010000000000000;
cin = 1'b1;
end
initial begin
//$monitor("time=",$time,, "in1=%b in2=%b cin=%b : sum=%b cout=%b",in1,in2,cin,sum,cout);
$monitor("time=", $time,, "in1=%d in2=%d cin=%d : sum=%d cout=%d", in1, in2, cin, sum, cout);
end
endmodule
| 7.224884 |
module: UBBKA_31_0_31_0
Operand-1 length: 32
Operand-2 length: 32
Two-operand addition algorithm: Brent-Kung adder
----------------------------------------------------------------------------*/
// Modified by: Amir Yazdanbakhsh
// Email: a.yazdanbakhsh@gatech.edu
`timescale 1ns/1ps
module GPGenerator(Go, Po, A, B);
output Go;
output Po;
input A;
input B;
assign Go = A & B;
assign Po = A ^ B;
endmodule
| 7.632614 |
module CarryOperator (
Go,
Po,
Gi1,
Pi1,
Gi2,
Pi2
);
output Go;
output Po;
input Gi1;
input Gi2;
input Pi1;
input Pi2;
assign Go = Gi1 | (Gi2 & Pi1);
assign Po = Pi1 & Pi2;
endmodule
| 7.456973 |
module test_brent_kung_4;
// Inputs
reg [3:0] in1;
reg [3:0] in2;
reg cin;
// Outputs
wire [3:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
brent_kung_4 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 4'b0001;
in2 = 4'b0000;
cin = 1'b0;
#10 in1 = 4'b1010;
in2 = 4'b0011;
cin = 1'b0;
#10 in1 = 4'b1101;
in2 = 4'b1010;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%b in2=%b cin=%b : sum=%b cout=%b", in1, in2, cin, sum, cout);
end
endmodule
| 7.224884 |
module test_brent_kung_8;
// Inputs
reg [7:0] in1;
reg [7:0] in2;
reg cin;
// Outputs
wire [7:0] sum;
wire cout;
// Instantiate the Unit test (UUT)
brent_kung_8 uut (
.sum (sum),
.cout(cout),
.in1 (in1),
.in2 (in2),
.cin (cin)
);
initial begin
in1 = 0;
in2 = 0;
cin = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in1 = 8'b00000001;
in2 = 8'b00000000;
cin = 1'b0;
#10 in1 = 4'b00001010;
in2 = 8'b00000011;
cin = 1'b0;
#10 in1 = 4'b11010000;
in2 = 8'b10100000;
cin = 1'b1;
end
initial begin
$monitor("time=", $time,, "in1=%b in2=%b cin=%b : sum=%b cout=%b", in1, in2, cin, sum, cout);
end
endmodule
| 7.224884 |
module Brent_kung_adder #(
parameter WIDTH = 16,
VALENCY = 2
) (
input [WIDTH:1] A,
input [WIDTH:1] B,
input Cin,
output [WIDTH:1] S,
output Cout
);
wire [WIDTH:0] G, P, Gi;
Bitwise_PG #(WIDTH) bit_PG (
A,
B,
Cin,
G,
P
);
Brent_kung_grp_PG #(WIDTH, VALENCY) grp_PG (
G,
P,
Gi
);
Final_sum #(WIDTH) sum_logic (
P,
Gi,
S
);
assign Cout = Gi[WIDTH];
endmodule
| 7.72098 |
module Brent_kung_grp_PG #(
parameter WIDTH = 16,
VALENCY = 2
) (
input [WIDTH:0] G,
input [WIDTH:0] P,
output [WIDTH:0] Gi
);
wire [WIDTH-1:0] gt1[0:$clog2(WIDTH)], pt1[0:$clog2(WIDTH)];
assign gt1[0] = G;
assign pt1[0] = P;
assign Gi[0] = G[0];
genvar i, j, k;
generate
for (i = 1; i <= $clog2(WIDTH); i = i + 1) begin : Upper_Levels
assign gt1[i][0] = G[0];
for (j = 2 ** i - 1; j < WIDTH; j = j + 2 ** i) begin : Upper_cells_gen
for (k = j - 1; k >= j - (2 ** i - 1); k = k - 1) begin : wire_connnections
assign gt1[i][k] = gt1[i-1][k];
assign pt1[i][k] = pt1[i-1][k];
end
if (j == 2 ** i - 1) begin
Gray_cell #(VALENCY) GC (
{gt1[i-1][j], gt1[i-1][j-2**(i-1)]},
{pt1[i-1][j], pt1[i-1][j-2**(i-1)]},
gt1[i][j]
);
assign Gi[j] = gt1[i][j];
end else
Black_cell #(VALENCY) BC (
{gt1[i-1][j], gt1[i-1][j-2**(i-1)]},
{pt1[i-1][j], pt1[i-1][j-2**(i-1)]},
gt1[i][j],
pt1[i][j]
);
end
end
endgenerate
generate
for (i = $clog2(WIDTH) - 1; i > 0; i = i - 1) begin : Lower_levels
for (j = WIDTH - (2 ** (i - 1) + 1); j > 0; j = j - 2 ** i) begin : GC_cells_gen
if (j >= 2 ** i)
Gray_cell #(VALENCY) GC_lower (
{gt1[$clog2(WIDTH)][j], Gi[j-2**(i-1)]},
{pt1[$clog2(WIDTH)][j], 1'b0},
Gi[j]
);
end
end
endgenerate
Gray_cell #(VALENCY) GC1 (
{G[WIDTH], Gi[WIDTH-1]},
{P[WIDTH], 1'b0},
Gi[WIDTH]
);
endmodule
| 7.073151 |
module: bresenham
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bresenhamTest;
// Inputs
reg clk;
reg reset;
reg [7:0] x_0;
reg [7:0] y_0;
reg [7:0] x_1;
reg [7:0] y_1;
reg input_valid;
// Outputs
wire [7:0] x_out;
wire [7:0] y_out;
wire output_valid;
wire ready_for_data;
// Instantiate the Unit Under Test (UUT)
bresenham uut (
.clk(clk),
.reset(reset),
.x_0(x_0),
.y_0(y_0),
.x_1(x_1),
.y_1(y_1),
.input_valid(input_valid),
.x_out(x_out),
.y_out(y_out),
.output_valid(output_valid),
.ready_for_data(ready_for_data)
);
always begin #50; clk = ~ clk; end
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
x_0 = 0;
y_0 = 0;
x_1 = 0;
y_1 = 0;
input_valid = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 1;
#60;
reset = 0;
#100;
// x_0 = 0;
// x_1 = 5;
// y_0 = 0;
// y_1 = 5;
// x_0 = 0;
// x_1 = 5;
// y_0 = 0;
// y_1 = 3;
x_0 = 2;
x_1 = 9;
y_0 = 3;
y_1 = 9;
#60;
input_valid = 1;
#60;
input_valid = 0;
// Add stimulus here
end
endmodule
| 7.157795 |
module tb ();
reg clk = 0;
reg reset = 0;
wire baud;
brg dut (
clk,
reset,
baud
);
always #41.667 clk = ~clk;
initial begin
$dumpfile("dumpvars.vcd");
$dumpvars;
#10 reset = 1'b1;
#100 reset = 1'b0;
#100000 $finish;
end
endmodule
| 7.195167 |
module Bricks_Left (
Bricks_Left,
Bricks_Left_7SEG,
flag_reg
);
input [139:0] flag_reg;
output reg [7:0] Bricks_Left;
output [15:0] Bricks_Left_7SEG;
integer i;
always @(flag_reg) begin
Bricks_Left = 0;
for (i = 0; i < 140; i = i + 1) begin
if (!flag_reg[i]) Bricks_Left = Bricks_Left + 1;
end
end
BCD bcd1 (
Bricks_Left_7SEG,
{3'b000, Bricks_Left}
);
endmodule
| 6.616715 |
module bricktest (
clk,
reset,
h_video,
v_video,
tick60hz,
pix_x,
pix_y,
ball_y_t,
brick_on,
brick_rgb,
direction,
BRICK_Y_T,
brick_rgbin,
brick_p
);
input clk, reset, tick60hz, h_video, v_video;
input [2:0] brick_rgbin;
input [9:0] pix_x, pix_y, ball_y_t;
output brick_on;
output [2:0] brick_rgb;
output reg brick_p;
output reg [2:0] direction;
input [9:0] BRICK_Y_T;
wire [9:0] BRICK_Y_B;
always @(posedge clk, posedge reset)
if (reset) begin
brick_p <= 1'b1;
direction <= 3'b000;
end else begin
if ((ball_y_t < BRICK_Y_B + 6) && (brick_p > 1'b0)) begin
brick_p <= 1'b0;
direction <= 3'b100;
end else direction <= 3'b000;
end
assign brick_on = (brick_p) ? (BRICK_Y_T <= pix_y) && (pix_y <= BRICK_Y_B) : 1'b0;
// brick rgb output
assign brick_rgb = brick_rgbin;
assign BRICK_Y_B = BRICK_Y_T + 20;
endmodule
| 6.501346 |
module bridgetop_tb ();
parameter [2:0] SINGLE = 3'd0,INCR = 3'd1, WRAP4 = 3'd2, INCR4 = 3'd3, WRAP8 = 3'd4, INCR8 = 3'd5, WRAP16 = 3'd6, INCR16 = 3'd7;
reg Hclk;
reg Hresetn;
reg [2:0] Hburst;
reg [2:0] Hsize;
wire [31:0] Hrdata;
wire [1:0] Hresp;
wire Hreadyout;
wire Hwrite;
wire Hreadyin;
wire [1:0] Htrans;
wire [31:0] Haddr;
wire [31:0] Hwdata;
wire Pwrite;
wire Penable;
wire [2:0] Pselx;
wire [31:0] Paddr;
wire [31:0] Pwdata;
wire [31:0] Prdata;
wire [31:0] Paddr_out;
wire [31:0] Pwdata_out;
wire Pwrite_out;
wire Penable_out;
wire [2:0] Pselx_out;
wire [31:0] Pdata;
ahb_master MASTER (
.Hclk(Hclk),
.Hresetn(Hresetn),
.Hresp(Hresp),
.Hreadyout(Hreadyout),
.Hrdata(Hrdata),
.Hwrite(Hwrite),
.Hreadyin(Hreadyin),
.Htrans(Htrans),
.Haddr(Haddr),
.Hwdata(Hwdata),
.Hburst(Hburst),
.Hsize(Hsize)
);
bridge_top BRIDGE_TOP (
.Hclk(Hclk),
.Hresetn(Hresetn),
.Hwrite(Hwrite),
.Hreadyin(Hreadyin),
.Htrans(Htrans),
.Haddr(Haddr),
.Hwdata(Hwdata),
.Pwrite(Pwrite),
.Penable(Penable),
.Pselx(Pselx),
.Paddr(Paddr),
.Pwdata(Pwdata),
.Hreadyout(Hreadyout),
.Hresp(Hresp),
.Hrdata(Hrdata),
.Prdata(Prdata)
);
apb_slaveinterface SLAVE (
.Pwrite(Pwrite),
.Penable(Penable),
.Pselx(Pselx),
.Paddr(Paddr),
.Pwdata(Pwdata),
.Prdata(Prdata),
.Pwrite_out(Pwrite_out),
.Penable_out(Penable_out),
.Pselx_out(Pselx_out),
.Paddr_out(Paddr_out),
.Pwdata_out(Pwdata_out),
.Pdata(Pdata)
);
initial begin
Hclk = 1'b0;
Hresetn = 1'b1;
forever #10 Hclk = ~Hclk;
end
initial begin
Hresetn = 1'b0;
#20 Hresetn = 1'b1;
Hburst = SINGLE;
Hsize = 3'd0;
MASTER.write;
#10 Hburst = SINGLE;
Hsize = 3'd0;
MASTER.read;
#10 Hburst = INCR4;
Hsize = 3'd1;
MASTER.write;
#10 Hburst = INCR8;
Hsize = 3'd1;
MASTER.read;
#10 MASTER.b2b;
#100 $finish;
end
//If burst, addr will be sent only if hreadyout is 1
endmodule
| 6.742151 |
module bridge_1x2 (
input clk, // clock
input resetn, // reset, active low
// master : cpu data
input cpu_data_en, // cpu data access enable
input [ 7 : 0] cpu_data_wen, // cpu data write byte enable
input [63 : 0] cpu_data_addr, // cpu data address
input [63 : 0] cpu_data_wdata, // cpu data write data
output [63 : 0] cpu_data_rdata, // cpu data read data
// slave : data ram
output data_sram_en, // access data_sram enable
output [ 7 : 0] data_sram_wen, // write enable
output [63 : 0] data_sram_addr, // address
output [63 : 0] data_sram_wdata, // data in
input [63 : 0] data_sram_rdata, // data out
// slave : confreg
output conf_en, // access confreg enable
output [ 7 : 0] conf_wen, // access confreg enable
output [63 : 0] conf_addr, // address
output [63 : 0] conf_wdata, // write data
input [63 : 0] conf_rdata // read data
);
wire sel_sram; // cpu data is from data ram
wire sel_conf; // cpu data is from confreg
reg sel_sram_r; // reg of sel_dram
reg sel_conf_r; // reg of sel_conf
assign sel_conf = (cpu_data_addr & `CONF_ADDR_MASK) == `CONF_ADDR_BASE;
assign sel_sram = !sel_conf;
// data sram
assign data_sram_en = cpu_data_en & sel_sram;
assign data_sram_wen = cpu_data_wen;
assign data_sram_addr = cpu_data_addr;
assign data_sram_wdata = cpu_data_wdata;
// confreg
assign conf_en = cpu_data_en & sel_conf;
assign conf_wen = cpu_data_wen;
assign conf_addr = cpu_data_addr;
assign conf_wdata = cpu_data_wdata;
always @(posedge clk) begin
if (!resetn) begin
sel_sram_r <= 1'b0;
sel_conf_r <= 1'b0;
end else begin
sel_sram_r <= sel_sram;
sel_conf_r <= sel_conf;
end
end
assign cpu_data_rdata = {64{sel_sram_r}} & data_sram_rdata | {64{sel_conf_r}} & conf_rdata;
endmodule
| 7.579477 |
module bridge_1_2 (
input no_dcache,
// cpu
input cpu_req,
input cpu_wr,
input [1 : 0] cpu_size,
input [ 31:0] cpu_addr,
input [ 31:0] cpu_wdata,
output [ 31:0] cpu_rdata,
output cpu_addr_ok,
output cpu_data_ok,
// ram (cache optional)
output ram_req,
output ram_wr,
output [1 : 0] ram_size,
output [ 31:0] ram_addr,
output [ 31:0] ram_wdata,
input [ 31:0] ram_rdata,
input ram_addr_ok,
input ram_data_ok,
// confreg
output conf_req,
output conf_wr,
output [1 : 0] conf_size,
output [ 31:0] conf_addr,
output [ 31:0] conf_wdata,
input [ 31:0] conf_rdata,
input conf_addr_ok,
input conf_data_ok
);
assign cpu_rdata = no_dcache ? conf_rdata : ram_rdata ;
assign cpu_addr_ok = no_dcache ? conf_addr_ok : ram_addr_ok;
assign cpu_data_ok = no_dcache ? conf_data_ok : ram_data_ok;
assign ram_req = no_dcache ? 0 : cpu_req ;
assign ram_wr = no_dcache ? 0 : cpu_wr ;
assign ram_size = no_dcache ? 0 : cpu_size ;
assign ram_addr = no_dcache ? 0 : cpu_addr ;
assign ram_wdata = no_dcache ? 0 : cpu_wdata;
assign conf_req = no_dcache ? cpu_req : 0;
assign conf_wr = no_dcache ? cpu_wr : 0;
assign conf_size = no_dcache ? cpu_size : 0;
assign conf_addr = no_dcache ? cpu_addr : 0;
assign conf_wdata = no_dcache ? cpu_wdata : 0;
endmodule
| 7.250689 |
module bridge (
praddr,
prwd,
dev0_rd,
dev1_rd,
dev2_rd,
wecpu,
IRQ,
prrd,
dev_wd,
dev_addr,
wedev0,
wedev2,
HWInt
);
input [31:0] praddr, prwd, dev0_rd, dev1_rd, dev2_rd;
input wecpu, IRQ;
output [31:0] prrd, dev_wd;
output [31:0] dev_addr;
output wedev0, wedev2; // 0 timer 2 dataOut
output [5:0] HWInt;
wire HitDev0, HitDev1, HitDev2; // 0 timer 2 dataOut
assign HitDev0 = (praddr == 32'h0000_7F00 || praddr == 32'h0000_7F04 || praddr == 32'h0000_7F08) ? 1 : 0;
assign HitDev1 = (praddr == 32'h0000_7F0C) ? 1 : 0;
assign HitDev2 = (praddr == 32'h0000_7F10 || praddr == 32'h0000_7F14) ? 1 : 0;
assign wedev0 = wecpu & HitDev0;
assign wedev2 = wecpu & HitDev2;
assign prrd = (HitDev0) ? dev0_rd : (HitDev1) ? dev1_rd : (HitDev2) ? dev2_rd : dev0_rd;
assign dev_addr = praddr;
assign dev_wd = prwd;
assign HWInt = {5'b0, IRQ};
endmodule
| 8.006498 |
module bridge_2x1 (
input no_dcache,
input ram_data_req,
input ram_data_wr,
input [1 : 0] ram_data_size,
input [ 31:0] ram_data_addr,
input [ 31:0] ram_data_wdata,
output [ 31:0] ram_data_rdata,
output ram_data_addr_ok,
output ram_data_data_ok,
input conf_data_req,
input conf_data_wr,
input [1 : 0] conf_data_size,
input [ 31:0] conf_data_addr,
input [ 31:0] conf_data_wdata,
output [ 31:0] conf_data_rdata,
output conf_data_addr_ok,
output conf_data_data_ok,
output wrap_data_req,
output wrap_data_wr,
output [1 : 0] wrap_data_size,
output [ 31:0] wrap_data_addr,
output [ 31:0] wrap_data_wdata,
input [ 31:0] wrap_data_rdata,
input wrap_data_addr_ok,
input wrap_data_data_ok
);
assign ram_data_rdata = no_dcache ? 0 : wrap_data_rdata ;
assign ram_data_addr_ok = no_dcache ? 0 : wrap_data_addr_ok;
assign ram_data_data_ok = no_dcache ? 0 : wrap_data_data_ok;
assign conf_data_rdata = no_dcache ? wrap_data_rdata : 0;
assign conf_data_addr_ok = no_dcache ? wrap_data_addr_ok : 0;
assign conf_data_data_ok = no_dcache ? wrap_data_data_ok : 0;
assign wrap_data_req = no_dcache ? conf_data_req : ram_data_req ;
assign wrap_data_wr = no_dcache ? conf_data_wr : ram_data_wr ;
assign wrap_data_size = no_dcache ? conf_data_size : ram_data_size ;
assign wrap_data_addr = no_dcache ? conf_data_addr : ram_data_addr ;
assign wrap_data_wdata = no_dcache ? conf_data_wdata : ram_data_wdata;
endmodule
| 6.742313 |
module bridge_2_1 (
input no_dcache,
input ram_req,
input ram_wr,
input [1 : 0] ram_size,
input [ 31:0] ram_addr,
input [ 31:0] ram_wdata,
output [ 31:0] ram_rdata,
output ram_addr_ok,
output ram_data_ok,
input conf_req,
input conf_wr,
input [1 : 0] conf_size,
input [ 31:0] conf_addr,
input [ 31:0] conf_wdata,
output [ 31:0] conf_rdata,
output conf_addr_ok,
output conf_data_ok,
output wrap_req,
output wrap_wr,
output [1 : 0] wrap_size,
output [ 31:0] wrap_addr,
output [ 31:0] wrap_wdata,
input [ 31:0] wrap_rdata,
input wrap_addr_ok,
input wrap_data_ok
);
assign ram_rdata = no_dcache ? 0 : wrap_rdata ;
assign ram_addr_ok = no_dcache ? 0 : wrap_addr_ok;
assign ram_data_ok = no_dcache ? 0 : wrap_data_ok;
assign conf_rdata = no_dcache ? wrap_rdata : 0;
assign conf_addr_ok = no_dcache ? wrap_addr_ok : 0;
assign conf_data_ok = no_dcache ? wrap_data_ok : 0;
assign wrap_req = no_dcache ? conf_req : ram_req ;
assign wrap_wr = no_dcache ? conf_wr : ram_wr ;
assign wrap_size = no_dcache ? conf_size : ram_size ;
assign wrap_addr = no_dcache ? conf_addr : ram_addr ;
assign wrap_wdata = no_dcache ? conf_wdata : ram_wdata;
endmodule
| 6.584196 |
module bridge_4 #(
parameter DATA_WIDTH = 32,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 10,
parameter BURSTCOUNT_WIDTH = 1,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1,
parameter SYNC_RESET = 0
) (
input wire clk, // clk.clk
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [ DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [ DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [ HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [ 3:0] s0_byteenable, // .byteenable
input wire s0_debugaccess, // .debugaccess
input wire m0_waitrequest, // m0.waitrequest
input wire [ DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [ DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [ HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [ 3:0] m0_byteenable, // .byteenable
output wire m0_debugaccess // .debugaccess
);
endmodule
| 8.518203 |
module bridge_64b_to_16b (
input rstn,
input clk_125,
input [63:0] tx_data_64b,
input tx_st_64b,
input tx_end_64b,
input tx_dwen_64b,
output tx_rdy_64b,
output tx_val,
input tx_rdy_16b,
output reg [15:0] tx_data_16b,
output reg tx_st_16b,
output reg tx_end_16b
);
assign tx_rdy_64b = tx_rdy_16b && (~tx_end_64b);
reg tx_rdy_16b_d;
reg [1:0] cnt;
reg xmit_processing;
reg tx_st_64b_d;
reg tx_val_reg1;
reg tx_val_reg2;
reg mimic_tx_dwen;
assign tx_val = (tx_val_reg1 & (~tx_st_64b)) || tx_val_reg2;
assign mimic_tx_dwen_tmp = mimic_tx_dwen && tx_end_64b;
always @(posedge clk_125 or negedge rstn)
if (!rstn) begin
tx_rdy_16b_d <= 0;
tx_st_64b_d <= 0;
tx_val_reg1 <= 1'b1;
tx_val_reg2 <= 1'b0;
xmit_processing <= 1'b0;
cnt <= 0;
mimic_tx_dwen <= 0;
end else begin
if (tx_st_64b) begin //only support for 3
if (tx_data_64b[61]) begin //for 4DW application
if (tx_data_64b[62]) //with data
mimic_tx_dwen <= tx_data_64b[32];
else //without data
mimic_tx_dwen <= 1'b0;
end else begin
if (tx_data_64b[62]) //with data
mimic_tx_dwen <= ~tx_data_64b[32];
else //without data
mimic_tx_dwen <= 1'b1;
end
end
tx_rdy_16b_d <= tx_rdy_16b;
tx_st_64b_d <= tx_st_64b;
if (tx_st_64b) begin
xmit_processing <= 1'b1;
tx_val_reg1 <= 0;
cnt <= 0;
end else if (tx_end_64b && (cnt == 3)) begin
xmit_processing <= 1'b0;
tx_val_reg1 <= 1'b1;
end
if (tx_rdy_16b && (~tx_rdy_16b_d)) cnt <= 0;
else if (xmit_processing || tx_st_64b) cnt <= cnt + 1;
else cnt <= 0;
tx_val_reg2 <= xmit_processing && (cnt == 2);
end
always @(*) begin
case (cnt)
2'd0: begin
tx_st_16b = tx_st_64b;
tx_data_16b = tx_data_64b[63:48];
tx_end_16b = 1'b0;
end
2'd1: begin
tx_st_16b = 1'b0;
tx_data_16b = tx_data_64b[47:32];
tx_end_16b = mimic_tx_dwen_tmp && tx_end_64b; //tx_dwen_64b && tx_end_64b;
end
2'd2: begin
tx_st_16b = 1'b0;
tx_data_16b = tx_data_64b[31:16];
tx_end_16b = 1'b0;
end
default: begin
tx_st_16b = 1'b0;
tx_data_16b = tx_data_64b[15:0];
tx_end_16b = (~ mimic_tx_dwen_tmp) && tx_end_64b;//(~ tx_dwen_64b) && tx_end_64b;
end
endcase
end
endmodule
| 6.992944 |
module bridge_div (
bri_div_start,
rst_n, //λ
clk_sys,
clk_dds, //ʱ
load, //װطƵ
divcount, //Ƶ
clk_4f_en //ʱ
);
input bri_div_start;
input rst_n;
input clk_sys;
input clk_dds;
input load;
input [5:0] divcount;
output clk_4f_en;
reg clk_4f;
reg [5:0] count;
reg [2:0] datahalf;
reg [5:0] dataall;
reg clear1_n;
reg clear2_n;
reg clk_4f_reg1;
reg clk_4f_reg2;
always @(posedge clk_sys) begin
if (load == 1'b1) begin
datahalf <= divcount[2:0];
dataall <= divcount[5:3] + divcount[2:0];
end else begin
datahalf <= datahalf;
dataall <= dataall;
end
end
always @(negedge rst_n or posedge clk_dds) begin
if (rst_n == 1'b0) begin
count <= 4'b1;
clk_4f <= 1'b0;
end else begin
if (bri_div_start == 1'b1) begin
if (clear1_n == 1'b0) begin
count <= count + 1;
clk_4f <= ~clk_4f;
end else if (clear2_n == 1'b0) begin
count <= 1'b1;
clk_4f <= ~clk_4f;
end else begin
count <= count + 1;
clk_4f <= clk_4f;
end
end else begin
count <= 4'b1;
clk_4f <= 1'b0;
end
end
end
always @(count or datahalf or dataall) begin
case (count)
datahalf: {clear2_n, clear1_n} = 2'b10;
dataall: {clear2_n, clear1_n} = 2'b01;
default: {clear2_n, clear1_n} = 2'b11;
endcase
end
always @(negedge rst_n or posedge clk_dds) begin
if (rst_n == 1'b0) {clk_4f_reg1, clk_4f_reg2} <= 2'b0;
else begin
clk_4f_reg1 <= clk_4f;
clk_4f_reg2 <= clk_4f_reg1;
end
end
assign clk_4f_en = clk_4f_reg1 & (~clk_4f_reg2);
endmodule
| 6.941733 |
module bridge_top (
hclk,
hresetn,
hwrite,
hready_in,
htrans,
hwdata,
haddr,
pwrite,
penable,
psel,
paddr,
pwdata,
prdata,
hrdata,
hresp,
hready_out
);
input hclk, hresetn, hwrite, hready_in;
input [1:0] htrans;
input [31:0] hwdata, haddr;
output pwrite, penable;
output [2:0] psel;
output [31:0] paddr, pwdata;
input [31:0] prdata;
output [31:0] hrdata;
output [1:0] hresp;
output hready_out;
wire hwrite_reg, valid;
wire [31:0] hwdata_0, hwdata_1, haddr_0, haddr_1;
wire [2:0] temp_sel;
ahb_slave M1 (
.hclk(hclk),
.hresetn(hresetn),
.hwrite(hwrite),
.hready_in(hready_in),
.htrans(htrans),
.hwdata(hwdata),
.haddr(haddr),
.hwrite_reg(hwrite_reg),
.valid(valid),
.hwdata_0(hwdata_0),
.hwdata_1(hwdata_1),
.haddr_0(haddr_0),
.haddr_1(haddr_1),
.temp_sel(temp_sel)
);
apb_fsm M2 (
.hclk(hclk),
.hresetn(hresetn),
.hwrite(hwrite),
.valid(valid),
.hwrite_reg(hwrite_reg),
.hwdata_0(hwdata_0),
.hwdata_1(hwdata_1),
.haddr_0(haddr_0),
.haddr_1(haddr_1),
.temp_sel(temp_sel),
.pwrite(pwrite),
.penable(penable),
.psel(psel),
.paddr(paddr),
.pwdata(pwdata),
.prdata(prdata),
.hrdata(hrdata),
.hresp(hresp),
.hready_out(hready_out)
);
endmodule
| 6.537546 |
module brief_compare #(
parameter DATA_WIDTH = 14
) (
input wire clk,
input wire [DATA_WIDTH-1:0] compare_A,
input wire [DATA_WIDTH-1:0] compare_B,
output reg compare_out
);
always @(posedge clk)
if (compare_A < compare_B) compare_out <= 1'b1;
else compare_out <= 1'b0;
endmodule
| 8.901087 |
module BufferCC_1 (
input io_dataIn,
output io_dataOut,
input io_axiClk
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.574801 |
module StreamArbiter_3 (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [19:0] io_inputs_0_payload_addr,
input [ 3:0] io_inputs_0_payload_id,
input [ 7:0] io_inputs_0_payload_len,
input [ 2:0] io_inputs_0_payload_size,
input [ 1:0] io_inputs_0_payload_burst,
input io_inputs_0_payload_write,
output io_output_valid,
input io_output_ready,
output [19:0] io_output_payload_addr,
output [ 3:0] io_output_payload_id,
output [ 7:0] io_output_payload_len,
output [ 2:0] io_output_payload_size,
output [ 1:0] io_output_payload_burst,
output io_output_payload_write,
output [ 0:0] io_chosenOH,
input io_axiClk,
input resetCtrl_axiReset
);
wire [1:0] _zz__zz_maskProposal_0_2;
wire [1:0] _zz__zz_maskProposal_0_2_1;
wire [0:0] _zz__zz_maskProposal_0_2_2;
wire [0:0] _zz_maskProposal_0_3;
reg locked;
wire maskProposal_0;
reg maskLocked_0;
wire maskRouted_0;
wire [0:0] _zz_maskProposal_0;
wire [1:0] _zz_maskProposal_0_1;
wire [1:0] _zz_maskProposal_0_2;
wire io_output_fire;
assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1);
assign _zz__zz_maskProposal_0_2_2 = maskLocked_0;
assign _zz__zz_maskProposal_0_2_1 = {1'd0, _zz__zz_maskProposal_0_2_2};
assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[1 : 1] | _zz_maskProposal_0_2[0 : 0]);
assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0);
assign _zz_maskProposal_0 = io_inputs_0_valid;
assign _zz_maskProposal_0_1 = {_zz_maskProposal_0, _zz_maskProposal_0};
assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~_zz__zz_maskProposal_0_2));
assign maskProposal_0 = _zz_maskProposal_0_3[0];
assign io_output_fire = (io_output_valid && io_output_ready);
assign io_output_valid = (io_inputs_0_valid && maskRouted_0);
assign io_output_payload_addr = io_inputs_0_payload_addr;
assign io_output_payload_id = io_inputs_0_payload_id;
assign io_output_payload_len = io_inputs_0_payload_len;
assign io_output_payload_size = io_inputs_0_payload_size;
assign io_output_payload_burst = io_inputs_0_payload_burst;
assign io_output_payload_write = io_inputs_0_payload_write;
assign io_inputs_0_ready = (maskRouted_0 && io_output_ready);
assign io_chosenOH = maskRouted_0;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
locked <= 1'b0;
maskLocked_0 <= 1'b1;
end else begin
if (io_output_valid) begin
maskLocked_0 <= maskRouted_0;
end
if (io_output_valid) begin
locked <= 1'b1;
end
if (io_output_fire) begin
locked <= 1'b0;
end
end
end
endmodule
| 6.929245 |
module StreamFifoLowLatency (
input io_push_valid,
output io_push_ready,
output reg io_pop_valid,
input io_pop_ready,
input io_flush,
output [2:0] io_occupancy,
input io_axiClk,
input resetCtrl_axiReset
);
wire [1:0] _zz_pushPtr_valueNext;
wire [0:0] _zz_pushPtr_valueNext_1;
wire [1:0] _zz_popPtr_valueNext;
wire [0:0] _zz_popPtr_valueNext_1;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
reg [1:0] pushPtr_valueNext;
reg [1:0] pushPtr_value;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
reg [1:0] popPtr_valueNext;
reg [1:0] popPtr_value;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire when_Stream_l1086;
wire when_Stream_l1099;
wire [1:0] ptrDif;
assign _zz_pushPtr_valueNext_1 = pushPtr_willIncrement;
assign _zz_pushPtr_valueNext = {1'd0, _zz_pushPtr_valueNext_1};
assign _zz_popPtr_valueNext_1 = popPtr_willIncrement;
assign _zz_popPtr_valueNext = {1'd0, _zz_popPtr_valueNext_1};
always @(*) begin
pushPtr_willIncrement = 1'b0;
if (pushing) begin
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
if (io_flush) begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = (pushPtr_value == 2'b11);
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
pushPtr_valueNext = (pushPtr_value + _zz_pushPtr_valueNext);
if (pushPtr_willClear) begin
pushPtr_valueNext = 2'b00;
end
end
always @(*) begin
popPtr_willIncrement = 1'b0;
if (popping) begin
popPtr_willIncrement = 1'b1;
end
end
always @(*) begin
popPtr_willClear = 1'b0;
if (io_flush) begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = (popPtr_value == 2'b11);
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
always @(*) begin
popPtr_valueNext = (popPtr_value + _zz_popPtr_valueNext);
if (popPtr_willClear) begin
popPtr_valueNext = 2'b00;
end
end
assign ptrMatch = (pushPtr_value == popPtr_value);
assign empty = (ptrMatch && (!risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (!full);
assign when_Stream_l1086 = (!empty);
always @(*) begin
if (when_Stream_l1086) begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
assign when_Stream_l1099 = (pushing != popping);
assign ptrDif = (pushPtr_value - popPtr_value);
assign io_occupancy = {(risingOccupancy && ptrMatch), ptrDif};
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
pushPtr_value <= 2'b00;
popPtr_value <= 2'b00;
risingOccupancy <= 1'b0;
end else begin
pushPtr_value <= pushPtr_valueNext;
popPtr_value <= popPtr_valueNext;
if (when_Stream_l1099) begin
risingOccupancy <= pushing;
end
if (io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
endmodule
| 7.046487 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [31:0] io_axi_arw_payload_addr,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
input [ 3:0] io_axi_arw_payload_cache,
input [ 2:0] io_axi_arw_payload_prot,
input io_axi_arw_payload_write,
input io_axi_w_valid,
output io_axi_w_ready,
input [31:0] io_axi_w_payload_data,
input [ 3:0] io_axi_w_payload_strb,
input io_axi_w_payload_last,
output io_axi_b_valid,
input io_axi_b_ready,
output [ 1:0] io_axi_b_payload_resp,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output [ 1:0] io_axi_r_payload_resp,
output io_axi_r_payload_last,
input io_axiClk,
input resetCtrl_axiReset
);
reg consumeData;
reg sendReadRsp;
reg sendWriteRsp;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_arw_fire;
wire io_axi_w_fire;
wire when_Axi4ErrorSlave_l92;
wire io_axi_b_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_arw_ready = (!((consumeData || sendWriteRsp) || sendReadRsp));
assign io_axi_arw_fire = (io_axi_arw_valid && io_axi_arw_ready);
assign io_axi_w_ready = consumeData;
assign io_axi_w_fire = (io_axi_w_valid && io_axi_w_ready);
assign when_Axi4ErrorSlave_l92 = (io_axi_w_fire && io_axi_w_payload_last);
assign io_axi_b_valid = sendWriteRsp;
assign io_axi_b_payload_resp = 2'b11;
assign io_axi_b_fire = (io_axi_b_valid && io_axi_b_ready);
assign io_axi_r_valid = sendReadRsp;
assign io_axi_r_payload_resp = 2'b11;
assign io_axi_r_payload_last = remainingZero;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
consumeData <= 1'b0;
sendReadRsp <= 1'b0;
sendWriteRsp <= 1'b0;
end else begin
if (io_axi_arw_fire) begin
consumeData <= io_axi_arw_payload_write;
sendReadRsp <= (!io_axi_arw_payload_write);
end
if (when_Axi4ErrorSlave_l92) begin
consumeData <= 1'b0;
sendWriteRsp <= 1'b1;
end
if (io_axi_b_fire) begin
sendWriteRsp <= 1'b0;
end
if (sendReadRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendReadRsp <= 1'b0;
end
end
end
end
end
always @(posedge io_axiClk) begin
if (io_axi_arw_fire) begin
remaining <= io_axi_arw_payload_len;
end
if (sendReadRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 6.942764 |
module Axi4ReadOnlyErrorSlave (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 1:0] io_axi_ar_payload_burst,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output [ 1:0] io_axi_r_payload_resp,
output io_axi_r_payload_last,
input io_axiClk,
input resetCtrl_axiReset
);
reg sendRsp;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_ar_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_ar_ready = (!sendRsp);
assign io_axi_ar_fire = (io_axi_ar_valid && io_axi_ar_ready);
assign io_axi_r_valid = sendRsp;
assign io_axi_r_payload_resp = 2'b11;
assign io_axi_r_payload_last = remainingZero;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
sendRsp <= 1'b0;
end else begin
if (io_axi_ar_fire) begin
sendRsp <= 1'b1;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendRsp <= 1'b0;
end
end
end
end
end
always @(posedge io_axiClk) begin
if (io_axi_ar_fire) begin
remaining <= io_axi_ar_payload_len;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 7.858199 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.712921 |
module BufferCC_12 (
input io_dataIn,
output io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 7.001425 |
module Apb3Gpio (
input [ 3:0] io_apb_PADDR,
input [ 0:0] io_apb_PSEL,
input io_apb_PENABLE,
output io_apb_PREADY,
input io_apb_PWRITE,
input [31:0] io_apb_PWDATA,
output reg [31:0] io_apb_PRDATA,
output io_apb_PSLVERROR,
input [31:0] io_gpio_read,
output [31:0] io_gpio_write,
output [31:0] io_gpio_writeEnable,
output [31:0] io_value,
input io_axiClk,
input resetCtrl_axiReset
);
wire [31:0] io_gpio_read_buffercc_io_dataOut;
wire ctrl_askWrite;
wire ctrl_askRead;
wire ctrl_doWrite;
wire ctrl_doRead;
reg [31:0] io_gpio_write_driver;
reg [31:0] io_gpio_writeEnable_driver;
BufferCC_6 io_gpio_read_buffercc (
.io_dataIn (io_gpio_read), //i
.io_dataOut (io_gpio_read_buffercc_io_dataOut), //o
.io_axiClk (io_axiClk), //i
.resetCtrl_axiReset(resetCtrl_axiReset) //i
);
assign io_value = io_gpio_read_buffercc_io_dataOut;
assign io_apb_PREADY = 1'b1;
always @(*) begin
io_apb_PRDATA = 32'h0;
case (io_apb_PADDR)
4'b0000: begin
io_apb_PRDATA[31 : 0] = io_value;
end
4'b0100: begin
io_apb_PRDATA[31 : 0] = io_gpio_write_driver;
end
4'b1000: begin
io_apb_PRDATA[31 : 0] = io_gpio_writeEnable_driver;
end
default: begin
end
endcase
end
assign io_apb_PSLVERROR = 1'b0;
assign ctrl_askWrite = ((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PWRITE);
assign ctrl_askRead = ((io_apb_PSEL[0] && io_apb_PENABLE) && (!io_apb_PWRITE));
assign ctrl_doWrite = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && io_apb_PWRITE);
assign ctrl_doRead = (((io_apb_PSEL[0] && io_apb_PENABLE) && io_apb_PREADY) && (!io_apb_PWRITE));
assign io_gpio_write = io_gpio_write_driver;
assign io_gpio_writeEnable = io_gpio_writeEnable_driver;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
io_gpio_writeEnable_driver <= 32'h0;
end else begin
case (io_apb_PADDR)
4'b1000: begin
if (ctrl_doWrite) begin
io_gpio_writeEnable_driver <= io_apb_PWDATA[31 : 0];
end
end
default: begin
end
endcase
end
end
always @(posedge io_axiClk) begin
case (io_apb_PADDR)
4'b0100: begin
if (ctrl_doWrite) begin
io_gpio_write_driver <= io_apb_PWDATA[31 : 0];
end
end
default: begin
end
endcase
end
endmodule
| 6.706229 |
module BufferCC_10 (
input io_dataIn,
output io_dataOut,
input io_axiClk
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.968109 |
module StreamArbiter_3 (
input io_inputs_0_valid,
output io_inputs_0_ready,
input [19:0] io_inputs_0_payload_addr,
input [ 3:0] io_inputs_0_payload_id,
input [ 7:0] io_inputs_0_payload_len,
input [ 2:0] io_inputs_0_payload_size,
input [ 1:0] io_inputs_0_payload_burst,
input io_inputs_0_payload_write,
output io_output_valid,
input io_output_ready,
output [19:0] io_output_payload_addr,
output [ 3:0] io_output_payload_id,
output [ 7:0] io_output_payload_len,
output [ 2:0] io_output_payload_size,
output [ 1:0] io_output_payload_burst,
output io_output_payload_write,
output [ 0:0] io_chosenOH,
input io_axiClk,
input resetCtrl_axiReset
);
wire [1:0] _zz__zz_maskProposal_0_2;
wire [1:0] _zz__zz_maskProposal_0_2_1;
wire [0:0] _zz__zz_maskProposal_0_2_2;
wire [0:0] _zz_maskProposal_0_3;
reg locked;
wire maskProposal_0;
reg maskLocked_0;
wire maskRouted_0;
wire [0:0] _zz_maskProposal_0;
wire [1:0] _zz_maskProposal_0_1;
wire [1:0] _zz_maskProposal_0_2;
wire io_output_fire;
assign _zz__zz_maskProposal_0_2 = (_zz_maskProposal_0_1 - _zz__zz_maskProposal_0_2_1);
assign _zz__zz_maskProposal_0_2_2 = maskLocked_0;
assign _zz__zz_maskProposal_0_2_1 = {1'd0, _zz__zz_maskProposal_0_2_2};
assign _zz_maskProposal_0_3 = (_zz_maskProposal_0_2[1 : 1] | _zz_maskProposal_0_2[0 : 0]);
assign maskRouted_0 = (locked ? maskLocked_0 : maskProposal_0);
assign _zz_maskProposal_0 = io_inputs_0_valid;
assign _zz_maskProposal_0_1 = {_zz_maskProposal_0, _zz_maskProposal_0};
assign _zz_maskProposal_0_2 = (_zz_maskProposal_0_1 & (~_zz__zz_maskProposal_0_2));
assign maskProposal_0 = _zz_maskProposal_0_3[0];
assign io_output_fire = (io_output_valid && io_output_ready);
assign io_output_valid = (io_inputs_0_valid && maskRouted_0);
assign io_output_payload_addr = io_inputs_0_payload_addr;
assign io_output_payload_id = io_inputs_0_payload_id;
assign io_output_payload_len = io_inputs_0_payload_len;
assign io_output_payload_size = io_inputs_0_payload_size;
assign io_output_payload_burst = io_inputs_0_payload_burst;
assign io_output_payload_write = io_inputs_0_payload_write;
assign io_inputs_0_ready = (maskRouted_0 && io_output_ready);
assign io_chosenOH = maskRouted_0;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
locked <= 1'b0;
maskLocked_0 <= 1'b1;
end else begin
if (io_output_valid) begin
maskLocked_0 <= maskRouted_0;
end
if (io_output_valid) begin
locked <= 1'b1;
end
if (io_output_fire) begin
locked <= 1'b0;
end
end
end
endmodule
| 6.929245 |
module StreamFifoLowLatency_1 (
input io_push_valid,
output io_push_ready,
output reg io_pop_valid,
input io_pop_ready,
input io_flush,
output [2:0] io_occupancy,
input io_axiClk,
input resetCtrl_axiReset
);
wire [1:0] _zz_pushPtr_valueNext;
wire [0:0] _zz_pushPtr_valueNext_1;
wire [1:0] _zz_popPtr_valueNext;
wire [0:0] _zz_popPtr_valueNext_1;
reg pushPtr_willIncrement;
reg pushPtr_willClear;
reg [1:0] pushPtr_valueNext;
reg [1:0] pushPtr_value;
wire pushPtr_willOverflowIfInc;
wire pushPtr_willOverflow;
reg popPtr_willIncrement;
reg popPtr_willClear;
reg [1:0] popPtr_valueNext;
reg [1:0] popPtr_value;
wire popPtr_willOverflowIfInc;
wire popPtr_willOverflow;
wire ptrMatch;
reg risingOccupancy;
wire empty;
wire full;
wire pushing;
wire popping;
wire when_Stream_l995;
wire when_Stream_l1008;
wire [1:0] ptrDif;
assign _zz_pushPtr_valueNext_1 = pushPtr_willIncrement;
assign _zz_pushPtr_valueNext = {1'd0, _zz_pushPtr_valueNext_1};
assign _zz_popPtr_valueNext_1 = popPtr_willIncrement;
assign _zz_popPtr_valueNext = {1'd0, _zz_popPtr_valueNext_1};
always @(*) begin
pushPtr_willIncrement = 1'b0;
if (pushing) begin
pushPtr_willIncrement = 1'b1;
end
end
always @(*) begin
pushPtr_willClear = 1'b0;
if (io_flush) begin
pushPtr_willClear = 1'b1;
end
end
assign pushPtr_willOverflowIfInc = (pushPtr_value == 2'b11);
assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement);
always @(*) begin
pushPtr_valueNext = (pushPtr_value + _zz_pushPtr_valueNext);
if (pushPtr_willClear) begin
pushPtr_valueNext = 2'b00;
end
end
always @(*) begin
popPtr_willIncrement = 1'b0;
if (popping) begin
popPtr_willIncrement = 1'b1;
end
end
always @(*) begin
popPtr_willClear = 1'b0;
if (io_flush) begin
popPtr_willClear = 1'b1;
end
end
assign popPtr_willOverflowIfInc = (popPtr_value == 2'b11);
assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement);
always @(*) begin
popPtr_valueNext = (popPtr_value + _zz_popPtr_valueNext);
if (popPtr_willClear) begin
popPtr_valueNext = 2'b00;
end
end
assign ptrMatch = (pushPtr_value == popPtr_value);
assign empty = (ptrMatch && (!risingOccupancy));
assign full = (ptrMatch && risingOccupancy);
assign pushing = (io_push_valid && io_push_ready);
assign popping = (io_pop_valid && io_pop_ready);
assign io_push_ready = (!full);
assign when_Stream_l995 = (!empty);
always @(*) begin
if (when_Stream_l995) begin
io_pop_valid = 1'b1;
end else begin
io_pop_valid = io_push_valid;
end
end
assign when_Stream_l1008 = (pushing != popping);
assign ptrDif = (pushPtr_value - popPtr_value);
assign io_occupancy = {(risingOccupancy && ptrMatch), ptrDif};
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
pushPtr_value <= 2'b00;
popPtr_value <= 2'b00;
risingOccupancy <= 1'b0;
end else begin
pushPtr_value <= pushPtr_valueNext;
popPtr_value <= popPtr_valueNext;
if (when_Stream_l1008) begin
risingOccupancy <= pushing;
end
if (io_flush) begin
risingOccupancy <= 1'b0;
end
end
end
endmodule
| 7.046487 |
module Axi4ReadOnlyErrorSlave_1 (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 2:0] io_axi_ar_payload_size,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output io_axi_r_payload_last,
input io_axiClk,
input resetCtrl_axiReset
);
reg sendRsp;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_ar_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_ar_ready = (!sendRsp);
assign io_axi_ar_fire = (io_axi_ar_valid && io_axi_ar_ready);
assign io_axi_r_valid = sendRsp;
assign io_axi_r_payload_last = remainingZero;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
sendRsp <= 1'b0;
end else begin
if (io_axi_ar_fire) begin
sendRsp <= 1'b1;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendRsp <= 1'b0;
end
end
end
end
end
always @(posedge io_axiClk) begin
if (io_axi_ar_fire) begin
remaining <= io_axi_ar_payload_len;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 7.858199 |
module Axi4SharedErrorSlave (
input io_axi_arw_valid,
output io_axi_arw_ready,
input [31:0] io_axi_arw_payload_addr,
input [ 7:0] io_axi_arw_payload_len,
input [ 2:0] io_axi_arw_payload_size,
input [ 3:0] io_axi_arw_payload_cache,
input [ 2:0] io_axi_arw_payload_prot,
input io_axi_arw_payload_write,
input io_axi_w_valid,
output io_axi_w_ready,
input [31:0] io_axi_w_payload_data,
input [ 3:0] io_axi_w_payload_strb,
input io_axi_w_payload_last,
output io_axi_b_valid,
input io_axi_b_ready,
output [ 1:0] io_axi_b_payload_resp,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output [ 1:0] io_axi_r_payload_resp,
output io_axi_r_payload_last,
input io_axiClk,
input resetCtrl_axiReset
);
reg consumeData;
reg sendReadRsp;
reg sendWriteRsp;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_arw_fire;
wire io_axi_w_fire;
wire when_Axi4ErrorSlave_l92;
wire io_axi_b_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_arw_ready = (!((consumeData || sendWriteRsp) || sendReadRsp));
assign io_axi_arw_fire = (io_axi_arw_valid && io_axi_arw_ready);
assign io_axi_w_ready = consumeData;
assign io_axi_w_fire = (io_axi_w_valid && io_axi_w_ready);
assign when_Axi4ErrorSlave_l92 = (io_axi_w_fire && io_axi_w_payload_last);
assign io_axi_b_valid = sendWriteRsp;
assign io_axi_b_payload_resp = 2'b11;
assign io_axi_b_fire = (io_axi_b_valid && io_axi_b_ready);
assign io_axi_r_valid = sendReadRsp;
assign io_axi_r_payload_resp = 2'b11;
assign io_axi_r_payload_last = remainingZero;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
consumeData <= 1'b0;
sendReadRsp <= 1'b0;
sendWriteRsp <= 1'b0;
end else begin
if (io_axi_arw_fire) begin
consumeData <= io_axi_arw_payload_write;
sendReadRsp <= (!io_axi_arw_payload_write);
end
if (when_Axi4ErrorSlave_l92) begin
consumeData <= 1'b0;
sendWriteRsp <= 1'b1;
end
if (io_axi_b_fire) begin
sendWriteRsp <= 1'b0;
end
if (sendReadRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendReadRsp <= 1'b0;
end
end
end
end
end
always @(posedge io_axiClk) begin
if (io_axi_arw_fire) begin
remaining <= io_axi_arw_payload_len;
end
if (sendReadRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 6.942764 |
module Axi4ReadOnlyErrorSlave (
input io_axi_ar_valid,
output io_axi_ar_ready,
input [31:0] io_axi_ar_payload_addr,
input [ 7:0] io_axi_ar_payload_len,
input [ 1:0] io_axi_ar_payload_burst,
input [ 3:0] io_axi_ar_payload_cache,
input [ 2:0] io_axi_ar_payload_prot,
output io_axi_r_valid,
input io_axi_r_ready,
output [31:0] io_axi_r_payload_data,
output [ 1:0] io_axi_r_payload_resp,
output io_axi_r_payload_last,
input io_axiClk,
input resetCtrl_axiReset
);
reg sendRsp;
reg [7:0] remaining;
wire remainingZero;
wire io_axi_ar_fire;
assign remainingZero = (remaining == 8'h0);
assign io_axi_ar_ready = (!sendRsp);
assign io_axi_ar_fire = (io_axi_ar_valid && io_axi_ar_ready);
assign io_axi_r_valid = sendRsp;
assign io_axi_r_payload_resp = 2'b11;
assign io_axi_r_payload_last = remainingZero;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
sendRsp <= 1'b0;
end else begin
if (io_axi_ar_fire) begin
sendRsp <= 1'b1;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
if (remainingZero) begin
sendRsp <= 1'b0;
end
end
end
end
end
always @(posedge io_axiClk) begin
if (io_axi_ar_fire) begin
remaining <= io_axi_ar_payload_len;
end
if (sendRsp) begin
if (io_axi_r_ready) begin
remaining <= (remaining - 8'h01);
end
end
end
endmodule
| 7.858199 |
module FlowCCByToggle (
input io_input_valid,
input io_input_payload_last,
input [0:0] io_input_payload_fragment,
output io_output_valid,
output io_output_payload_last,
output [0:0] io_output_payload_fragment,
input io_jtag_tck,
input io_axiClk,
input resetCtrl_systemReset
);
wire inputArea_target_buffercc_io_dataOut;
wire outHitSignal;
reg inputArea_target = 0;
reg inputArea_data_last;
reg [0:0] inputArea_data_fragment;
wire outputArea_target;
reg outputArea_hit;
wire outputArea_flow_valid;
wire outputArea_flow_payload_last;
wire [0:0] outputArea_flow_payload_fragment;
reg outputArea_flow_m2sPipe_valid;
reg outputArea_flow_m2sPipe_payload_last;
reg [0:0] outputArea_flow_m2sPipe_payload_fragment;
BufferCC_5 inputArea_target_buffercc (
.io_dataIn (inputArea_target), //i
.io_dataOut (inputArea_target_buffercc_io_dataOut), //o
.io_axiClk (io_axiClk), //i
.resetCtrl_systemReset(resetCtrl_systemReset) //i
);
assign outputArea_target = inputArea_target_buffercc_io_dataOut;
assign outputArea_flow_valid = (outputArea_target != outputArea_hit);
assign outputArea_flow_payload_last = inputArea_data_last;
assign outputArea_flow_payload_fragment = inputArea_data_fragment;
assign io_output_valid = outputArea_flow_m2sPipe_valid;
assign io_output_payload_last = outputArea_flow_m2sPipe_payload_last;
assign io_output_payload_fragment = outputArea_flow_m2sPipe_payload_fragment;
always @(posedge io_jtag_tck) begin
if (io_input_valid) begin
inputArea_target <= (!inputArea_target);
inputArea_data_last <= io_input_payload_last;
inputArea_data_fragment <= io_input_payload_fragment;
end
end
always @(posedge io_axiClk) begin
outputArea_hit <= outputArea_target;
if (outputArea_flow_valid) begin
outputArea_flow_m2sPipe_payload_last <= outputArea_flow_payload_last;
outputArea_flow_m2sPipe_payload_fragment <= outputArea_flow_payload_fragment;
end
end
always @(posedge io_axiClk or posedge resetCtrl_systemReset) begin
if (resetCtrl_systemReset) begin
outputArea_flow_m2sPipe_valid <= 1'b0;
end else begin
outputArea_flow_m2sPipe_valid <= outputArea_flow_valid;
end
end
endmodule
| 7.790686 |
module InterruptCtrl (
input [3:0] io_inputs,
input [3:0] io_clears,
input [3:0] io_masks,
output [3:0] io_pendings,
input io_axiClk,
input resetCtrl_axiReset
);
reg [3:0] pendings;
assign io_pendings = (pendings & io_masks);
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
pendings <= 4'b0000;
end else begin
pendings <= ((pendings & (~io_clears)) | io_inputs);
end
end
endmodule
| 7.510624 |
module Timer (
input io_tick,
input io_clear,
input [31:0] io_limit,
output io_full,
output [31:0] io_value,
input io_axiClk,
input resetCtrl_axiReset
);
wire [31:0] _zz_counter;
wire [ 0:0] _zz_counter_1;
reg [31:0] counter;
wire limitHit;
reg inhibitFull;
assign _zz_counter_1 = (!limitHit);
assign _zz_counter = {31'd0, _zz_counter_1};
assign limitHit = (counter == io_limit);
assign io_full = ((limitHit && io_tick) && (!inhibitFull));
assign io_value = counter;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
inhibitFull <= 1'b0;
end else begin
if (io_tick) begin
inhibitFull <= limitHit;
end
if (io_clear) begin
inhibitFull <= 1'b0;
end
end
end
always @(posedge io_axiClk) begin
if (io_tick) begin
counter <= (counter + _zz_counter);
end
if (io_clear) begin
counter <= 32'h0;
end
end
endmodule
| 6.729771 |
module BufferCC_8 (
input io_dataIn_clear,
input io_dataIn_tick,
output io_dataOut_clear,
output io_dataOut_tick,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0_clear;
(* async_reg = "true" *)reg buffers_0_tick;
(* async_reg = "true" *)reg buffers_1_clear;
(* async_reg = "true" *)reg buffers_1_tick;
assign io_dataOut_clear = buffers_1_clear;
assign io_dataOut_tick = buffers_1_tick;
always @(posedge io_axiClk) begin
buffers_0_clear <= io_dataIn_clear;
buffers_0_tick <= io_dataIn_tick;
buffers_1_clear <= buffers_0_clear;
buffers_1_tick <= buffers_0_tick;
end
endmodule
| 6.740109 |
module BufferCC_5 (
input io_dataIn,
output io_dataOut,
input io_axiClk,
input resetCtrl_systemReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.82712 |
module BufferCC_3 (
input [6:0] io_dataIn,
output [6:0] io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg [6:0] buffers_0;
(* async_reg = "true" *)reg [6:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk) begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
endmodule
| 6.792516 |
module BufferCC_1 (
input [9:0] io_dataIn,
output [9:0] io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg [9:0] buffers_0;
(* async_reg = "true" *)reg [9:0] buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
buffers_0 <= 10'h0;
buffers_1 <= 10'h0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.574801 |
module BufferCC (
input io_dataIn,
output io_dataOut,
input io_axiClk,
input resetCtrl_axiReset
);
(* async_reg = "true" *)reg buffers_0;
(* async_reg = "true" *)reg buffers_1;
assign io_dataOut = buffers_1;
always @(posedge io_axiClk or posedge resetCtrl_axiReset) begin
if (resetCtrl_axiReset) begin
buffers_0 <= 1'b0;
buffers_1 <= 1'b0;
end else begin
buffers_0 <= io_dataIn;
buffers_1 <= buffers_0;
end
end
endmodule
| 6.712921 |
module bridge (
input [31:0] PrAddr, //cpu传入的地址
input [31:0] PrWD, //cpu欲写入的内容
input [31:0] dev0_rd,
dev1_rd,
dev2_rd, //外部设备欲写入的数据
input IRQ, //计时器的中断信号
input wecpu, //来自cpu的写使能
output we_dev0,
we_dev2, //给计时器和输出设备的写使能
output [5:0] HWInt, //6个中断信号
output [31:0] PrRD, //写入cpu的内容
output [31:0] DEV_WD,
output [1:0] DEV_addr
);
//向外设分发写使能信号
assign we_dev0 = wecpu && (PrAddr[31:4] == 'h0000_7F0);
assign we_dev2 = wecpu && (PrAddr[31:4] == 'h0000_7F2);
//向外设分发写入数据
assign DEV_WD = PrWD;
//选择PrRD的外设来源
wire Hit_dev0, Hit_dev1, Hit_dev2;
assign Hit_dev0 = (PrAddr[31:4] == 'h0000_7F0);
assign Hit_dev1 = (PrAddr[31:4] == 'h0000_7F1);
assign Hit_dev2 = (PrAddr[31:4] == 'h0000_7F2);
assign PrRD = (Hit_dev0) ? dev0_rd : (Hit_dev1) ? dev1_rd : (Hit_dev2) ? dev2_rd : 32'hffff_ffff;
assign DEV_addr = PrAddr[3:2];
//从Timer来的中断请求
assign HWInt = {5'b0, IRQ};
endmodule
| 8.006498 |
module brightness (
input [5:0] value, /* the pixel's absolute value */
input [5:0] mask, /* a rolling brightness mask */
input enable,
output out
);
/* apply the brightness mask to the calculated sub-pixel value */
wire masked_value = (value & mask) != 0;
assign out = masked_value && enable;
endmodule
| 8.194426 |
module brimm_gen (
input wire [`INSN_LEN-1:0] inst,
output wire [`DATA_LEN-1:0] brimm
);
wire [`DATA_LEN-1:0] br_offset = {{20{inst[31]}}, inst[7], inst[30:25], inst[11:8], 1'b0};
wire [`DATA_LEN-1:0] jal_offset = {
{12{inst[31]}}, inst[19:12], inst[20], inst[30:25], inst[24:21], 1'b0
};
wire [`DATA_LEN-1:0] jalr_offset = {{21{inst[31]}}, inst[30:21], 1'b0};
wire [6:0] opcode = inst[6:0];
assign brimm = (opcode == `RV32_BRANCH) ? br_offset :
(opcode == `RV32_JAL) ? jal_offset :
(opcode == `RV32_JALR) ? jalr_offset :
`DATA_LEN'b0;
endmodule
| 7.360356 |
module brimestone #(
parameter DATA_WIDTH_P = 32,
parameter DATA_ADDR_WIDTH_P = 32,
parameter ADDR_WIDTH_P = 5,
parameter CNTRL_WIDTH_P = 3,
parameter ALU_CNTRL_WIDTH_P = 3,
parameter FUNCT_WIDTH_P = 6,
parameter OP_WIDTH_P = 6
) (
input wire clk,
input wire reset,
input wire i_enable
);
wire mem_wr_en;
wire [DATA_ADDR_WIDTH_P-1:0] mem_addr;
wire [DATA_WIDTH_P-1:0] mem_wr_data;
wire [DATA_WIDTH_P-1:0] mem_rd_data;
memory #(
.DATA_WIDTH_P(DATA_WIDTH_P),
.DATA_ADDR_WIDTH_P(DATA_WIDTH_P)
) data_memory (
.clk(clk),
.reset(reset),
.i_mem_wr_en(mem_wr_en),
.i_mem_addr(mem_addr),
.i_mem_wr_data(mem_wr_data),
.o_mem_rd_data(mem_rd_data)
);
core #(
.DATA_WIDTH_P(DATA_WIDTH_P),
.DATA_ADDR_WIDTH_P(DATA_ADDR_WIDTH_P),
.ADDR_WIDTH_P(ADDR_WIDTH_P),
.CNTRL_WIDTH_P(CNTRL_WIDTH_P),
.ALU_CNTRL_WIDTH_P(ALU_CNTRL_WIDTH_P),
.FUNCT_WIDTH_P(FUNCT_WIDTH_P),
.OP_WIDTH_P(OP_WIDTH_P)
) core_i (
.clk(clk),
.reset(reset),
.i_enable(i_enable),
// data memory interface
.i_mem_rd_data(mem_rd_data),
.o_mem_wr_en(mem_wr_en),
.o_mem_addr(mem_addr),
.o_mem_wr_data(mem_wr_data)
);
endmodule
| 7.295892 |
module trisc (
cond,
out_sig,
clk,
reset_n
);
//independent parameters
parameter ncs = 3; //number of bits to select cw+1 inputs i.e 2^ncs = (cw+1)
parameter aw = 8; //address width
parameter dw = 20; //data width for internal control
parameter ow = 28; //control output size
//dependant parameters (based on independant parameters
parameter cw = (1 << ncs) - 1; //number of conditional inputs (cw+1 must be a power of 2)
parameter pms = (1 << aw); // program memory size. depends on address width ( pms = 2 ^ aw )
// ow + dw defines the width of one memory block of program memory
input [cw-1:0] cond; // one conditional input is from down counter
input [0:0] clk, reset_n;
output [ow-1:0] out_sig;
//output of program memory
wire [aw-1:0] prog_ctr_a; // program counte address
wire [aw-1:0] sub_a; // subroutine address
wire [aw-1:0] branch_a; // branch address
wire [ncs-1:0] cond_sel;
wire [3:0] nal_sel;
wire [0:0] pp; // push/pop_n
wire [0:0] cl; //count/load_n
wire [0:0] ce; //counter enable
wire [0:0] sse; // subroutine stack enable
wire [0:0] cse; // counter stack enable
wire [0:0] cc; // output of conditinal select mux
//output of NAL
wire [aw-1:0] next_inst_a; //address of next instruction to execute
wire [aw:0] dc; // down counter
wire [aw:0] lc; // output of loop counter lifo
wire [aw:0] cm; // output of counter mux
wire [aw:0] ctr_o; // output of down counter register
wire [aw-1:0] inc_o; // output of incrementer
// program memory
prog_mem mem (
.addr(next_inst_a),
.clk (clk),
.dout({out_sig, nal_sel, cond_sel, cse, sse, ce, cl, pp, branch_a})
);
nal #(
.dw(aw)
) next_addr (
next_inst_a,
ctr_o[aw-1:0],
branch_a,
sub_a,
prog_ctr_a,
cc,
nal_sel[1:0],
nal_sel[3:2],
reset_n
);
lifo #(
.dw(aw + 1)
) loop_cnt (
ctr_o,
lc,
clk,
cse,
pp,
reset_n
);
mux2 #(
.dw(aw + 1)
) counter_m (
cm,
{1'b0, branch_a},
lc,
cl
);
down_counter #(
.dw(aw + 1)
) dn_ctr (
cm,
dc
);
register_e #(
.dw(aw + 1)
) ctr (
dc,
ctr_o,
clk,
reset_n,
ce
);
mux8 #(
.dw(1)
) cond_m (
cc,
ctr_o[aw],
cond[0],
cond[1],
cond[2],
cond[3],
cond[4],
cond[5],
cond[6],
cond_sel
);
incrementer #(
.dw(aw)
) inc (
next_inst_a,
inc_o
);
register #(
.dw(aw)
) prog_ctr (
inc_o,
prog_ctr_a,
clk,
reset_n
);
lifo #(
.dw(aw)
) sub (
prog_ctr_a,
sub_a,
clk,
sse,
pp,
reset_n
);
endmodule
| 8.543763 |
module bri_dump_sw (
rst_n,
clk_sys,
change,
pluse_start,
pluse_start1,
pluse_start2,
off_test,
off_test1,
off_test2,
dump_start,
dump_start1,
dump_start2,
phase_ctr,
phase_ctr1,
phase_ctr2,
reset_out,
reset_out1,
reset_out2,
dumpoff_ctr,
dumpoff_ctr1,
dumpoff_ctr2,
tetw_pluse,
tetw_pluse1,
tetw_pluse2,
turn_delay,
turn_delay1,
turn_delay2
);
input rst_n;
input clk_sys;
input change;
output turn_delay;
input turn_delay1;
input turn_delay2;
reg turn_delay;
output tetw_pluse;
reg tetw_pluse;
input tetw_pluse1;
input tetw_pluse2;
output pluse_start;
input pluse_start1;
input pluse_start2;
reg pluse_start;
output off_test;
input off_test1;
input off_test2;
reg off_test;
output dump_start;
input dump_start1;
input dump_start2;
reg dump_start;
output reset_out;
input reset_out1;
input reset_out2;
reg reset_out;
output phase_ctr;
input phase_ctr1;
input phase_ctr2;
reg phase_ctr;
output dumpoff_ctr;
input dumpoff_ctr1;
input dumpoff_ctr2;
reg dumpoff_ctr;
always @(posedge clk_sys) begin
if (rst_n == 1'b0) begin
reset_out <= 1'b0;
pluse_start <= 1'b0;
dump_start <= 1'b0;
phase_ctr <= 1'b0;
dumpoff_ctr <= 1'b0;
off_test <= 1'b0;
tetw_pluse <= 1'b0;
end else begin
if (change == 1'b1) begin
reset_out <= reset_out1;
pluse_start <= pluse_start1;
dump_start <= dump_start1;
phase_ctr <= phase_ctr1;
dumpoff_ctr <= dumpoff_ctr1;
off_test <= off_test1;
tetw_pluse <= tetw_pluse1;
turn_delay <= turn_delay1;
end else begin
reset_out <= reset_out2;
pluse_start <= pluse_start2;
dump_start <= dump_start2;
phase_ctr <= phase_ctr2;
dumpoff_ctr <= dumpoff_ctr2;
off_test <= off_test2;
tetw_pluse <= tetw_pluse2;
turn_delay <= turn_delay2;
end
end
end
endmodule
| 6.508231 |
module brj_addr_calc (
instr,
next_pc,
dest_addr
);
// TODO : ARE SHIFTS NEEDED?? (ie SL by 1)
// inputs
input [15:0] instr;
input [15:0] next_pc;
// outputs
output [15:0] dest_addr;
// wires
wire [4:0] op;
wire co, G, P;
reg [15:0] sextVal;
// assigns
assign op = instr[15:11];
// Instantiations
add16 add (
.A(sextVal),
.B(next_pc),
.CI(1'b0),
.Sum(dest_addr),
.CO(co),
.Ggroup(G),
.Pgroup(P)
);
always @(*) begin
case (op)
5'b01100: begin // BEQZ
sextVal = {{8{instr[7]}}, instr[7:0]};
end
5'b01101: begin // BNEZ
sextVal = {{8{instr[7]}}, instr[7:0]};
end
5'b01111: begin // BLTZ
sextVal = {{8{instr[7]}}, instr[7:0]};
end
5'b00100: begin // J
sextVal = {{5{instr[10]}}, instr[10:0]};
end
5'b00110: begin // JAL
sextVal = {{5{instr[10]}}, instr[10:0]};
end
default: begin
sextVal = 16'b0;
end
endcase
end
endmodule
| 8.092937 |
module Broadcaster #(
parameter WIDTH0 = 32
, parameter WIDTH1 = 32
, parameter BURST = "yes"
) (
input iValid_AM
, output oReady_AM
, input [WIDTH1+WIDTH0-1:0] iData_AM
, output oValid_BM0
, input iReady_BM0
, output [ WIDTH0-1:0] oData_BM0
, output oValid_BM1
, input iReady_BM1
, output [ WIDTH1-1:0] oData_BM1
, input iRST
, input iCLK
);
wire wvld;
wire wrdy;
wire wrdy0;
wire wrdy1;
wire [WIDTH0-1:0] wdata0;
wire [WIDTH1-1:0] wdata1;
assign oReady_AM = wrdy;
assign {wdata1, wdata0} = iData_AM;
//Valid
assign wvld = iValid_AM && wrdy;
//Ready
assign wrdy = wrdy0 && wrdy1;
//Register
Register #(
.WIDTH(WIDTH0),
.BURST(BURST)
) rg0 (
.iValid_AM(wvld),
.oReady_AM(wrdy0),
.iData_AM (wdata0)
, .oValid_BM(oValid_BM0),
.iReady_BM(iReady_BM0),
.oData_BM (oData_BM0)
, .iRST (iRST),
.iCLK (iCLK)
);
Register #(
.WIDTH(WIDTH1),
.BURST(BURST)
) rg1 (
.iValid_AM(wvld),
.oReady_AM(wrdy1),
.iData_AM (wdata1)
, .oValid_BM(oValid_BM1),
.iReady_BM(iReady_BM1),
.oData_BM (oData_BM1)
, .iRST (iRST),
.iCLK (iCLK)
);
endmodule
| 7.041826 |
module BroadcasterN #(
parameter SIZE = 8
, parameter WIDTH = 32
, parameter BURST = "yes"
) (
input iValid_AM
, output oReady_AM
, input [SIZE*WIDTH-1:0] iData_AM
, output [ SIZE-1:0] oValid_BM
, input [ SIZE-1:0] iReady_BM
, output [SIZE*WIDTH-1:0] oData_BM
, input iRST
, input iCLK
);
genvar gi;
wire wvld;
wire wrdy;
wire [ SIZE-1:0] wrdy_n;
wire [SIZE*WIDTH-1:0] wdata;
assign oReady_AM = wrdy;
assign wdata = iData_AM;
//Valid
assign wvld = iValid_AM && wrdy;
//Ready
assign wrdy = &wrdy_n;
generate
for (gi = 0; gi < SIZE; gi = gi + 1)
//Register
Register #(
.WIDTH(WIDTH)
, .BURST(BURST)
) rg (
.iValid_AM(wvld)
, .oReady_AM(wrdy_n[gi])
, .iData_AM(wdata[gi*WIDTH+:WIDTH])
, .oValid_BM(oValid_BM[gi])
, .iReady_BM(iReady_BM[gi])
, .oData_BM(oData_BM[gi*WIDTH+:WIDTH])
, .iRST(iRST)
, .iCLK(iCLK)
);
endgenerate
endmodule
| 7.831177 |
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