code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_concentrate_static #(parameter `BSG_INV_PARAM(pattern_els_p), width_lp=$bits(pattern_els_p), set_els_lp=`BSG_COUNTONES_SYNTH(pattern_els_p))
(input [width_lp-1:0] i
,output [set_els_lp-1:0] o
);
genvar j;
if (pattern_els_p[0])
assign o[0]=i[0];
for (j = 1; j < width_lp; j=j+1)
begin : r... | 7.372169 |
module bsg_concentrate_static_03 (
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_05 (
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[2];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_09 (
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[3];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_0f (
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_11 (
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[4];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_17 (
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[4];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_1b (
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[4];
assign o[2] = i[3];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_1d (
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[4];
assign o[2] = i[3];
assign o[1] = i[2];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_1f (
i,
o
);
input [4:0] i;
output [4:0] o;
wire [4:0] o;
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_3 (
i,
o
);
input [2:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_5 (
i,
o
);
input [2:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[2];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_7 (
i,
o
);
input [2:0] i;
output [2:0] o;
wire [2:0] o;
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module is a counter with dynamic limit that repeats counting
// from zero to overflow value. (it would get limit_i+1 different
// values during this counting).
// module renamed from bsg_counter_w_overflow
`include "bsg_defines.v"
module bsg_counter_dynamic_limit #(parameter `BSG_INV_PARAM(width_p ))
( in... | 7.329296 |
module implements simple counter with enable signal and dynamic
// overflow limit.
//
// The counter outputs 0 ~ (limit-1) value
//module renamed from bsg_counter_en_overflow
`include "bsg_defines.v"
module bsg_counter_dynamic_limit_en #(parameter `BSG_INV_PARAM(width_p ))
( input clk... | 6.58146 |
module bsg_counter_overflow_en #(parameter `BSG_INV_PARAM(max_val_p )
, parameter `BSG_INV_PARAM(init_val_p )
, parameter ptr_width_lp = `BSG_SAFE_CLOG2(max_val_p)
)
( input clk_i
, input reset_i
, input en_i
... | 6.639718 |
module bsg_counter_overflow_set_en #( parameter `BSG_INV_PARAM(max_val_p )
, parameter lg_max_val_lp = `BSG_SAFE_CLOG2(max_val_p+1)
)
( input clk_i
, input en_i
, input set_i
, input [lg_max_val_lp-1... | 6.639718 |
module june 2018
`include "bsg_defines.v"
module bsg_counter_up_down #( parameter `BSG_INV_PARAM(max_val_p )
, parameter `BSG_INV_PARAM(init_val_p )
, parameter `BSG_INV_PARAM(max_step_p )
//localpar... | 8.380223 |
module bsg_counting_leading_zeros #(
parameter `BSG_INV_PARAM(width_p)
, parameter num_zero_width_lp=`BSG_WIDTH(width_p)
)
(
input [width_p-1:0] a_i
,output logic [num_zero_width_lp-1:0] num_zero_o
);
logic [width_p:0] reversed;
genvar i;
for (i = 0; i < width_p; i++) begin
assign reversed[i] = a_i... | 7.368551 |
module is a counter for credits, that every decimation_p
// credits it would assert token_o signal once.
// It also supports a ready_i signal which declares when it can
// assert token_o. For normal use it could be set to one.
`include "bsg_defines.v"
module bsg_credit_to_token #( parameter `BSG_INV_PARAM(decimation... | 7.329296 |
module bsg_cycle_counter #(
parameter width_p = 32
, init_val_p = 0
) (
input clk_i
, input reset_i
, output logic [width_p-1:0] ctr_r_o
);
always @(posedge clk_i)
if (reset_i) ctr_r_o <= init_val_p;
else ctr_r_o <= ctr_r_o + 1;
endmodule
| 6.833862 |
module bsg_ddr_sampler #(
width_p = "inv"
) (
input clk
, input reset
, input [width_p-1:0] to_be_sampled_i
, output logic [width_p-1:0] pos_edge_value_o
, output logic [width_p-1:0] neg_edge_value_o
, output logic [width_p-1:0] pos_edge_synchronized_o
, ou... | 7.282722 |
module bsg_decode #(parameter `BSG_INV_PARAM(num_out_p))
(
input [`BSG_SAFE_CLOG2(num_out_p)-1:0] i
,output logic [num_out_p-1:0] o
);
if (num_out_p == 1) begin
// suppress unused signal warning
wire unused = i;
assign o = 1'b1;
end
else begin
assign o = (num_out_p) ' (1'b1 << i);
end
endm... | 6.988658 |
module bsg_decode_num_out_p10 (
i,
o
);
input [3:0] i;
output [9:0] o;
wire [9:0] o;
assign o = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_num_out_p2 (
i,
o
);
input [0:0] i;
output [1:0] o;
wire [1:0] o;
assign o = {1'b0, 1'b1} << i[0];
endmodule
| 6.955703 |
module bsg_decode_num_out_p3 (
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
assign o = {1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_num_out_p4 (
i,
o
);
input [1:0] i;
output [3:0] o;
wire [3:0] o;
assign o = {1'b0, 1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_num_out_p5 (
i,
o
);
input [2:0] i;
output [4:0] o;
wire [4:0] o;
assign o = {1'b0, 1'b0, 1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_num_out_p8 (
i,
o
);
input [2:0] i;
output [7:0] o;
wire [7:0] o;
assign o = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_with_v #(parameter `BSG_INV_PARAM(num_out_p))
(
input [`BSG_SAFE_CLOG2(num_out_p)-1:0] i
,input v_i
,output [num_out_p-1:0] o
);
wire [num_out_p-1:0] lo;
bsg_decode #(.num_out_p(num_out_p)
) bd
(.i
,.o(lo)
);
assign o ... | 7.148573 |
module bsg_dff_async_reset
#(parameter `BSG_INV_PARAM(width_p )
,parameter reset_val_p = 0
,parameter harden_p = 0
)
(input clk_i
,input async_reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
logic [width_p-1:0] data_r;
assign data_o = da... | 7.198195 |
module bsg_dff_chain #(
//the width of the input signal
parameter `BSG_INV_PARAM( width_p )
//the stages of the chained DFF register
//can be 0
,parameter num_stages_p = 1
)
(
... | 6.915153 |
module bsg_dff_en #(
parameter width_p = "inv"
, parameter harden_p = 1 // mbt fixme: maybe this should not be a default
, parameter strength_p = 1
) (
input clk_i
, input [width_p-1:0] data_i
, input en_i
, output logic [width_p-1:0] data_o
);
logic [width_p-1:0] data_r;
assign data_... | 6.9523 |
module bsg_dff_en_bypass
#(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
, parameter strength_p=0
)
(
input clk_i
, input en_i
, input [width_p-1:0] data_i
, output logic [width_p-1:0] data_o
);
logic [width_p-1:0] data_r;
bsg_dff_en #(
.width_p(width_p)
,.harden... | 7.758381 |
module bsg_dff_en_width_p1 (
clock_i,
data_i,
en_i,
data_o
);
input [0:0] data_i;
output [0:0] data_o;
input clock_i;
input en_i;
reg [0:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p16_harden_p0 (
clk_i,
data_i,
en_i,
data_o
);
input [15:0] data_i;
output [15:0] data_o;
input clk_i;
input en_i;
wire [15:0] data_o;
reg
data_o_15_sv2v_reg,
data_o_14_sv2v_reg,
data_o_13_sv2v_reg,
data_o_12_sv2v_reg,
data_o_11_sv2v_reg... | 6.557007 |
module bsg_dff_en_width_p32 (
clock_i,
data_i,
en_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clock_i;
input en_i;
reg [31:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[31] <= data_i[31];
end
end
always @(posedge clock_i) begin
... | 6.557007 |
module bsg_dff_en_width_p33 (
clock_i,
data_i,
en_i,
data_o
);
input [32:0] data_i;
output [32:0] data_o;
input clock_i;
input en_i;
reg [32:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[32] <= data_i[32];
end
end
always @(posedge clock_i) begin
... | 6.557007 |
module bsg_dff_en_width_p36 (
clk_i,
data_i,
en_i,
data_o
);
input [35:0] data_i;
output [35:0] data_o;
input clk_i;
input en_i;
reg [35:0] data_o;
always @(posedge clk_i) begin
if (en_i) begin
{data_o[35:0]} <= {data_i[35:0]};
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p5 (
clk_i,
data_i,
en_i,
data_o
);
input [4:0] data_i;
output [4:0] data_o;
input clk_i;
input en_i;
reg [4:0] data_o;
always @(posedge clk_i) begin
if (en_i) begin
{data_o[4:0]} <= {data_i[4:0]};
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p64 (
clk_i,
data_i,
en_i,
data_o
);
input [63:0] data_i;
output [63:0] data_o;
input clk_i;
input en_i;
reg [63:0] data_o;
always @(posedge clk_i) begin
if (en_i) begin
{data_o[63:0]} <= {data_i[63:0]};
end
end
endmodule
| 6.557007 |
module bsg_dff_gatestack #(
width_p = "inv",
harden_p = 1
) (
input [width_p-1:0] i0
, input [width_p-1:0] i1
, output logic [width_p-1:0] o
);
initial $display("%m: warning module not actually hardened.");
genvar j;
for (j = 0; j < width_p; j = j + 1) begin
always_ff @(posedge i1[j]) ... | 6.610787 |
module bsg_dff_negedge_reset #(`BSG_INV_PARAM(width_p), harden_p=0)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(negedge clk_i)
begin
if (reset_i)
data_r <= widt... | 7.238159 |
module bsg_dmc_clk_rst_gen
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p = 2
,parameter `BSG_INV_PARAM(num_lines_p ))
(input bsg_tag_s async_reset_tag_i
,input bsg_tag_s [num_lines_p-1:0] bsg_dly_tag_i
,input bsg_tag_s [num_lines_p-1:0] bsg_dly_trigger_tag_i
,input ... | 9.147596 |
module bsg_dmc_phy_bit_slice (
input clk_1x_i
, input clk_2x_i
, input dqs_p_i
, input dqs_n_i
, input wrdata_en_90_i
, input [1:0] wrdata_90_i
, output dq_o
, output dq_oe_n_o
, input dq_i
, input [1:0] write_pointer_i
... | 6.572972 |
module bsg_dmc_phy_byte_lane (
input reset_i
, input clk_1x_i
, input clk_2x_i
, input wrdata_en_i
, input [15:0] wrdata_i
, input [ 1:0] wrdata_mask_i
, output dm_oe_n_o
, output dm_o
,... | 6.572972 |
module is simply a 4-input mux. The edge balancing
// properties are process specific. A 250nm harded version
// can be found at:
//
// bsg_ip_cores/hard/bsg_clk_gen/bsg_edge_balanced_mux4.v
//
// This module should be replaced by the hardened version
// when being synthesized.
//
`include "bsg_defines.v"
module ... | 8.176708 |
module bsg_edge_detect #(
parameter falling_not_rising_p = 0
) (
input clk_i
, input reset_i
, input sig_i
, output detect_o
);
logic sig_r;
bsg_dff_reset #(
.width_p(1)
) sig_reg (
.clk_i (clk_i)
, .reset_i(reset_i)
, .data_i(sig_i)
, .data_o(sig_r)
);... | 7.356085 |
module expands each bit in the input vector by the factor of
* expand_p.
*
* @author tommy
*
*
* example
* ------------------------
* in_width_p=2, expand_p=4
* ------------------------
* i=00 -> o=0000_0000
* i=01 -> o=0000_1111
* i=10 -> o=1111_0000
* i=11 -> o=1111_1111
*
*/
`include "b... | 7.2345 |
module is a small fifo which has a bsg_channel_narrow
// on its output, that would send out each data in several steps
// based on the input and output width. width_p is the FIFO data
// width and width_out_p is the output width. els_p is the number
// of elements in fifo and lsb_to_msb_p determined the directions
// o... | 8.28436 |
module converts between the valid-credit (input) and
// valid-ready (output) handshakes, by using a fifo to keep
// the data
`include "bsg_defines.v"
module bsg_fifo_1r1w_small_credit_on_input #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p ... | 7.684328 |
module defines functional coverages of module bsg_fifo_1r1w_small_hardened
//
//
`include "bsg_defines.v"
module bsg_fifo_1r1w_small_hardened_cov
#(parameter els_p = "inv"
,localparam ptr_width_lp = `BSG_SAFE_CLOG2(els_p)
)
(input clk_i
,input reset_i
// interface signals
,input v_i
,input yumi_i
... | 8.303558 |
module bsg_fifo_reorder
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter lg_els_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input clk_i
, input reset_i
// FIFO allocates the next available addr
, output fifo_alloc_v_o
, output [lg_els_lp-1:0] fifo_alloc_id_o
, i... | 7.177236 |
module bsg_flatten_2D_array #(parameter `BSG_INV_PARAM( width_p )
, parameter `BSG_INV_PARAM(items_p ))
(input [width_p-1:0] i [items_p-1:0]
, output [width_p*items_p-1:0] o
);
genvar j;
for (j = 0; j < items_p; j=j+1)
begin
assign o[j*width_p+:w... | 8.193276 |
module converts between the various link-level flow-control
// protocols.
//
// fixme: many of the cases have not been tested. naming convention might
// be better. more asserts would be good. send_v_and_ready_p does not seem to
// be implemented. clocked versions should be handled by separate module.
//
// USAGE:
//
... | 7.684328 |
module or set of
// modules which have ready-and-valid or ready-then-valid
// (base on the ready_THEN_valid_p parameter) input protocol
// and valid-then-yumi protocol for the output. Based on the
// count_free_p it will count the number of free elements or
// number of existing elements in the connected module.
`inc... | 7.889231 |
module bsg_fpu_classify
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
, parameter width_lp=(e_p+m_p+1)
, parameter out_width_lp=width_lp
)
(
input [width_lp-1:0] a_i
, output [out_width_lp-1:0] class_o
);
logic zero;
logic nan;
logic sig_nan;
logic infty;
logic ... | 8.351391 |
module bsg_fpu_clz
#(parameter `BSG_INV_PARAM(width_p)
, localparam lg_width_lp=`BSG_SAFE_CLOG2(width_p)
)
(
input [width_p-1:0] i
, output logic [lg_width_lp-1:0] num_zero_o
);
logic [width_p-1:0] reversed;
for (genvar j = 0; j < width_p; j++) begin
assign reversed[j] = i[width_p-1-j];
... | 7.030453 |
module bsg_fpu_cmp
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
)
(
input [e_p+m_p:0] a_i
, input [e_p+m_p:0] b_i
// comparison
, output logic eq_o
, output logic lt_o
, output logic le_o
, output logic lt_le_invalid_o
, output logic eq_invalid_o
/... | 7.637011 |
module bsg_fpu_f2i
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
, localparam width_lp=(e_p+m_p+1)
, localparam bias_lp={1'b0, {(e_p-1){1'b1}}}
)
(
input [width_lp-1:0] a_i // input float
, input signed_i
, output logic [width_lp-1:0] z_o // output int
, output logi... | 7.28622 |
module bsg_fpu_i2f
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
, localparam width_lp = (e_p+m_p+1)
, localparam bias_lp = {1'b0, {(e_p-1){1'b1}}}
)
(
input clk_i
, input reset_i
, input en_i
, input v_i
, input signed_i
, input [width_lp-1:0] a_i
,... | 9.058685 |
module bsg_fpu_preprocess
#(parameter `BSG_INV_PARAM(e_p )
, parameter `BSG_INV_PARAM(m_p )
)
(
input [e_p+m_p:0] a_i
, output logic zero_o
, output logic nan_o
, output logic sig_nan_o
, output logic infty_o
, output logic exp_zero_o
, output logic man_zero_o
, output logic de... | 7.572097 |
module bsg_fpu_sticky
#(parameter `BSG_INV_PARAM(width_p))
(
input [width_p-1:0] i // input
, input [`BSG_WIDTH(width_p)-1:0] shamt_i // shift amount
, output logic sticky_o
);
logic [width_p-1:0] scan_out;
bsg_scan #(
.width_p(width_p)
,.or_p(1)
,.lo_to_hi_p(1)
) scan0 (
.i(i)... | 6.504975 |
module bsg_front_side_bus_hop_in
#(parameter `BSG_INV_PARAM( width_p)
, parameter fan_out_p=2
)
(input clk_i
, input reset_i
// from previous hop
, output ready_o
, input v_i
, input [width_p-1:0] data_i
// 0 is to the next hop
// 1 is to t... | 9.484205 |
module bsg_front_side_bus_hop_in_no_fc #(parameter `BSG_INV_PARAM(width_p))
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
// 0 is to the next switch
// 1 is to the local switch
, output [1:0][width_p-1:0] data_o
, output [1:0] v_o
, inpu... | 9.484205 |
module bsg_front_side_bus_hop_out #(parameter `BSG_INV_PARAM(width_p))
(input clk_i
, input reset_i
// 0 = previous switch
// 1 = local node
, input [1:0] v_i // late
, input [1:0][width_p-1:0] data_i // late
, output ready_o // to prev switch; early
, outpu... | 9.484205 |
module bsg_fsb_murn_gateway
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter `BSG_INV_PARAM(id_width_p)
// resets with core reset
// rather than by a command.
, parameter enabled_at_start_p=0
// once the node is enabled
// look at all packets;
// useful if we w... | 8.529928 |
module bsg_fsb_murn_gateway
import bsg_fsb_pkg::*;
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(id_p)
// resets with core reset
// rather than by a command.
, parameter enabled_at_start_p=0
// once the node is enabled
// look at all packets;
// useful if we would like to
... | 8.529928 |
module converts the bsg_fsb node signals between different
//clock domains.
//
//default: FSB on Right,
// NODE on Left
`include "bsg_defines.v"
`ifndef FSB_LEGACY
module bsg_fsb_node_async_buffer
#( parameter `BSG_INV_PARAM(ring_width_p)
,parameter fifo_els_p = 2
)
(
/////////////... | 6.747013 |
module bsg_fsb_node_async_buffer
import bsg_fsb_pkg::*;
#( parameter `BSG_INV_PARAM(ring_width_p)
,parameter fifo_els_p = 2
)
(
/////////////////////////////////////////////
// signals on the node side
input L_clk_i
, input L_reset_i
// control
, output L_en_o // FIXME... | 8.176575 |
module is design to level shift all signals that connect the FSB to a
// node. This allows FSB nodes to exist in different power domains than the FSB.
// There are 2 types of level shifters:
//
// 1) Source - level shifting cell must be in the same power domain as the
// signal's source
// 2) Sink ... | 10.624995 |
module is design to level shift all signals that connect the FSB to a
// node. This allows FSB nodes to exist in different power domains than the FSB.
// There are 2 types of level shifters:
//
// 1) Source - level shifting cell must be in the same power domain as the
// signal's source
// 2) Sink ... | 10.624995 |
module bsg_fsb_to_htif_connector
import bsg_fsb_pkg::RingPacketType;
#(parameter htif_width_p
,parameter fsb_width_p=$size(RingPacketType)
,parameter `BSG_INV_PARAM(destid_p)
)
(input clk_i
,input reset_i
,input fsb_v_i
,input [fsb_width_p-1:0] fsb_data_i
,output fsb_ready_o
... | 7.002691 |
module bsg_gateway_fmc_rx (
input reset_i
, output clk_div_o
, output [87:0] data_o
, output cal_done_o
// fmc rx clk in
, input F17_P,
F17_N
// fmc rx data in
, input F31_P,
F31_N
, input F33_P,
F33_N
, input F30_P,
F30_N
, input F32_P,
F32_N
, input ... | 6.571748 |
module bsg_gateway_fmc_rx_clk (
input clk_p_i,
clk_n_i
, output clk_p_o,
clk_n_o
, output clk_serdes_strobe_o
, output clk_div_o
);
logic iodelay_clk_p_lo, iodelay_clk_n_lo;
logic ibufds_clk_p_lo, ibufds_clk_n_lo;
logic bufio_clk_div_lo;
IBUFDS_DIFF_OUT #(
.DIFF_TERM("TRUE")
... | 6.571748 |
module bsg_gateway_fmc_rx_data (
input reset_i
, input clk_p_i,
clk_n_i
, input [10:0] data_p_i,
data_n_i
, input clk_div_i
, input clk_serdes_strobe_i
, output cal_done_o
, output [87:0] data_o
);
logic [87:0] iserdes_data_lo;
logic [10:0] ibufds_data_lo, iodelay_data_lo;
lo... | 6.571748 |
module bsg_gateway_fmc_rx_data_bitslip_ctrl (
input clk_i
, input reset_i
, input [7:0] data_i
, output bitslip_o
, output done_o
);
logic [7:0] data_pattern;
assign data_pattern = 8'h2C;
enum logic [2:0] {
IDLE = 3'b001
,BITSLIP = 3'b010
,DONE = 3'b100
}
c_state, ... | 6.571748 |
module bsg_gateway_fmc_tx
(input reset_i
,output clk_div_o
,input [87:0] data_i
,output cal_done_o
// fmc tx clk in
,input FCLK0_M2C_P, FCLK0_M2C_N
`ifdef BSG_ML605_FMC
// fmc tx clk out
,output FCLK1_M2C_P, FCLK1_M2C_N
// fmc tx data out [0]
,output F0_P, F0_N
`else
`ifdef BSG_ZEDBOARD_FMC
// fm... | 6.571748 |
module bsg_gateway_fmc_tx_data (
input reset_i
, input clk_p_i,
clk_n_i
, input clk_div_i
, input clk_serdes_strobe_i
, input [87:0] data_i
, output cal_done_o
, output [10:0] data_p_o,
data_n_o
);
logic [9:0] cnt_r;
always_ff @(posedge clk_div_i)
if (reset_i == 1'b1) cnt_r... | 6.571748 |
module bsg_gateway_iodelay (
input [3:0] clk_output_i
, input [7:0] data_a_output_i
, input [7:0] data_b_output_i
, input [7:0] data_c_output_i
, input [7:0] data_d_output_i
, input [3:0] valid_output_i
, input reset_i
, output [3:0] clk_output_o
, output [7:0] data_a_output_o
, ... | 7.854181 |
module bsg_gateway_iodelay_output #(
parameter tap_i = 0
) (
input bit_i
, output bit_o
);
IODELAY2 #(
.COUNTER_WRAPAROUND("WRAPAROUND"), // "STAY_AT_LIMIT" or "WRAPAROUND"
.DATA_RATE("DDR"), // "SDR" or "DDR"
.DELAY_SRC("ODATAIN"), // "IO", "ODATAIN" or "IDATAIN"
.IDELAY2_V... | 7.854181 |
module bsg_gateway_ldo (
input reset_i
, input clk_i
, output logic rstin_o
, output logic spi_out_o
, output logic spi_clk_o
, output logic spi_rst_o
);
logic [10:0] spi_stream_lo;
assign spi_stream_lo = 11'b10110001111;
logic [3:0] state_r, state_n;
logic [7:0] counter_r, counter_n;
... | 6.934047 |
module bsg_gateway_pll_control (
input reset_i
, input enable_i
, input clk_i
// Command data
, input [31:0] data_i
// tag enable control
, output logic [2:0] spi_rst_o
);
reg [2:0] spi_rst_r, spi_rst_n;
assign spi_rst_o = spi_rst_r;
always @(posedge clk_i) begin
if (reset_i) beg... | 6.895893 |
module bsg_gateway_pll_spi (
input clk_i
, input reset_i
// Init RAM
, input init_en_i
, input [15:0] init_data_i
// SPI Out
, input spi_en_i
, output logic spi_ready_o
, output logic spi_cs_o
, output logic spi_out_o
// MB Control
, input mb_en_i
, input mb_reset_i
... | 6.895893 |
module bsg_gateway_serdes #(
parameter width = 8
, parameter num_channel = 4
, parameter tap_array = {8'd35, 8'd35, 8'd35, 8'd35}
) (
// Output Side
input io_master_clk_i
, input clk_2x_i
, input [num_channel-1:0] io_serdes_clk_i
, input [num_channel-1:0] io_strobe_i
, input core_cal... | 8.153424 |
module bsg_gateway_serdes_output #(
parameter width = 8
) (
input io_master_clk_i
, input io_serdes_clk_i
, input io_strobe_i
, input D8_i
, input D7_i
, input D6_i
, input D5_i
, input D4_i
, input D3_i
, input D2_i
, input D1_i
, output Q_o
);
logic ... | 8.153424 |
module bsg_gateway_tag #(
parameter ring_width_p = "inv"
, parameter num_clk_p = "inv"
) (
input clk_i
, input reset_i
, output done_o
// microblaze control
, input mb_control_i
, input [num_clk_p-1:0] mb_select_i
, input [7:0] mb_counter_i
, input [7:0] mb_load_i
, input [2:... | 7.789465 |
module bsg_gray_to_binary #(
parameter width_p = -1
) (
input [width_p-1:0] gray_i
, output [width_p-1:0] binary_o
);
// or alternatively
// the entertaining:
// assign binary_o[width_p-1:0] = ({1'b0, binary_o[width_p-1:1]} ^ gray_i[width_p-1:0]);
/*
assign binary_o[width_p-1] = gray_i[wid... | 6.794758 |
module bsg_hash_bank_banks_p2_width_p5 (
i,
bank_o,
index_o
);
input [4:0] i;
output [0:0] bank_o;
output [3:0] index_o;
wire [0:0] bank_o;
wire [3:0] index_o;
wire index_o_3_, index_o_2_, index_o_1_, index_o_0_;
assign bank_o[0] = i[4];
assign index_o_3_ = i[3];
assign index_o[3] = inde... | 6.743449 |
module cordic_stage #(
parameter stage_p = 1
, parameter width_p = 12
) (
input clk
, input [width_p+7:0] x
, input [width_p+7:0] y
, output [width_p+7:0] x_n
, output [width_p+7:0] y_n
);
wire [width_p+7:0] x_shift = x >>> stage_p;
wire [width_p+7:0] y_shift = $signed(y) >>> stage_p;... | 6.628248 |
module bsg_hypotenuse #(
parameter width_p = 12
) (
input clk
, input [width_p-1:0] x_i
, input [width_p-1:0] y_i
, output [width_p:0] o
);
logic [width_p-1:0] x_set, y_set;
logic [width_p+7:0] ans_next;
logic [width_p+7:0] x[width_p+1:0];
logic [width_p+7:0] y[width_p+1:0];
logic [width_... | 8.61031 |
module bsg_iddr_phy #(
parameter width_p = "inv"
) (
input clk_i
, input [width_p-1:0] data_i
, output [2*width_p-1:0] data_o
);
logic [2*width_p-1:0] data_r;
logic [ width_p-1:0] data_p;
assign data_o = data_r;
always @(posedge clk_i) data_p <= data_i;
always @(negedge clk_i) data_r <= {d... | 7.071844 |
module maintains of a pool of IDs, and supports allocation and deallocation of these IDs.
*
*/
`include "bsg_defines.v"
module bsg_id_pool
#(parameter `BSG_INV_PARAM(els_p)
, parameter id_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input clk_i,
input reset_i
// next available id
, output logic... | 7.219616 |
module maintains of a pool of IDs, and supports allocation and deallocation of these IDs,
* and also live tracking of which ones are active.
*
* Only one item can be allocated per cycle (for now), but any number can be deallocated per cycle.
*
* order of precedence:
*
* actives_id_r_o is before a... | 7.219616 |
module bsg_launch_sync_sync_posedge_1_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [0:0] iclk_data_i;
output [0:0] iclk_data_o;
output [0:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [0:0] iclk_data_o, oclk_data_o, bsg... | 6.954266 |
module bsg_launch_sync_sync_posedge_4_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [3:0] iclk_data_i;
output [3:0] iclk_data_o;
output [3:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [3:0] iclk_data_o, oclk_data_o, bsg... | 6.954266 |
module bsg_less_than #(parameter `BSG_INV_PARAM(width_p)) (
input [width_p-1:0] a_i
,input [width_p-1:0] b_i
,output logic o // a is less than b
);
assign o = (a_i < b_i);
endmodule
| 7.976699 |
module bsg_level_shift_up_down_sink #(parameter `BSG_INV_PARAM(width_p ))
(
input [width_p-1:0] v0_data_i,
input v1_en_i,
output logic [width_p-1:0] v1_data_o
);
genvar i;
for (i = 0; i < width_p; i++)
begin : n
A2LVLU_X2N_A7P5PP96PTS_C18 level_shift_sink (
.EN(v1_en_i),... | 7.573656 |
module bsg_level_shift_up_down_source #(parameter `BSG_INV_PARAM(width_p ))
(
input v0_en_i,
input [width_p-1:0] v0_data_i,
output logic [width_p-1:0] v1_data_o
);
genvar i;
for (i = 0; i < width_p; i++)
begin : n
A2LVLUO_X2N_A7P5PP96PTS_C18 level_shift_source (
.EN(v0_e... | 7.573656 |
module bsg_lfsr #(parameter `BSG_INV_PARAM(width_p)
, init_val_p = 1 // an initial value of zero is typically the null point for LFSR's.
, xor_mask_p = 0)
(input clk
, input reset_i
, input yumi_i
, output logic [width_p-1:0] o
);
logic [width_p-1:0] o_r, o_n, ... | 7.636994 |
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