code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_concentrate_static #(parameter `BSG_INV_PARAM(pattern_els_p), width_lp=$bits(pattern_els_p), set_els_lp=`BSG_COUNTONES_SYNTH(pattern_els_p))
(input [width_lp-1:0] i
,output [set_els_lp-1:0] o
);
genvar j;
if (pattern_els_p[0])
assign o[0]=i[0];
for (j = 1; j < width_lp; j=j+1)
begin : rof
if (pattern_els_p[j])
assign o[`BSG_COUNTONES_SYNTH(pattern_els_p[j-1:0])] = i[j];
end
endmodule
| 7.372169 |
module bsg_concentrate_static_03 (
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_05 (
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[2];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_09 (
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[3];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_0f (
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_11 (
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[4];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_17 (
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[4];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_1b (
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[4];
assign o[2] = i[3];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_1d (
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[4];
assign o[2] = i[3];
assign o[1] = i[2];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_1f (
i,
o
);
input [4:0] i;
output [4:0] o;
wire [4:0] o;
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_3 (
i,
o
);
input [2:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_5 (
i,
o
);
input [2:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[2];
assign o[0] = i[0];
endmodule
| 7.372169 |
module bsg_concentrate_static_7 (
i,
o
);
input [2:0] i;
output [2:0] o;
wire [2:0] o;
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule
| 7.372169 |
module is a counter with dynamic limit that repeats counting
// from zero to overflow value. (it would get limit_i+1 different
// values during this counting).
// module renamed from bsg_counter_w_overflow
`include "bsg_defines.v"
module bsg_counter_dynamic_limit #(parameter `BSG_INV_PARAM(width_p ))
( input clk_i
, input reset_i
, input [width_p-1:0] limit_i
, output logic [width_p-1:0] counter_o
);
always_ff @ (posedge clk_i)
if (reset_i)
counter_o <= 0;
else if (counter_o == limit_i)
counter_o <= 0;
else
counter_o <= counter_o + width_p'(1);
endmodule
| 7.329296 |
module implements simple counter with enable signal and dynamic
// overflow limit.
//
// The counter outputs 0 ~ (limit-1) value
//module renamed from bsg_counter_en_overflow
`include "bsg_defines.v"
module bsg_counter_dynamic_limit_en #(parameter `BSG_INV_PARAM(width_p ))
( input clk_i
, input reset_i
, input en_i
, input [width_p-1:0] limit_i
, output logic [width_p-1:0] counter_o
, output overflowed_o
);
wire [width_p-1:0] counter_plus_1 = counter_o + width_p'(1);
assign overflowed_o = ( counter_plus_1 == limit_i );
always_ff @ (posedge clk_i)
if (reset_i)
counter_o <= 0;
else if (en_i) begin
if(overflowed_o ) counter_o <= 0;
else counter_o <= counter_plus_1 ;
end
endmodule
| 6.58146 |
module bsg_counter_overflow_en #(parameter `BSG_INV_PARAM(max_val_p )
, parameter `BSG_INV_PARAM(init_val_p )
, parameter ptr_width_lp = `BSG_SAFE_CLOG2(max_val_p)
)
( input clk_i
, input reset_i
, input en_i
, output logic [ptr_width_lp-1:0] count_o
, output logic overflow_o
);
assign overflow_o = (count_o == max_val_p);
always_ff @(posedge clk_i)
begin
if (reset_i | overflow_o)
count_o <= init_val_p;
else if (en_i)
count_o <= count_o + 1'b1;
end
endmodule
| 6.639718 |
module bsg_counter_overflow_set_en #( parameter `BSG_INV_PARAM(max_val_p )
, parameter lg_max_val_lp = `BSG_SAFE_CLOG2(max_val_p+1)
)
( input clk_i
, input en_i
, input set_i
, input [lg_max_val_lp-1:0] val_i
, output logic [lg_max_val_lp-1:0] count_o
, output logic overflow_o
);
assign overflow_o = (count_o == max_val_p);
always_ff @(posedge clk_i)
begin
if (set_i)
count_o <= val_i;
else if (overflow_o)
count_o <= {lg_max_val_lp{1'b0}};
else if (en_i)
count_o <= count_o + 1'b1;
end
endmodule
| 6.639718 |
module june 2018
`include "bsg_defines.v"
module bsg_counter_up_down #( parameter `BSG_INV_PARAM(max_val_p )
, parameter `BSG_INV_PARAM(init_val_p )
, parameter `BSG_INV_PARAM(max_step_p )
//localpara
, parameter step_width_lp =
`BSG_WIDTH(max_step_p)
, parameter ptr_width_lp =
`BSG_WIDTH(max_val_p))
( input clk_i
, input reset_i
, input [step_width_lp-1:0] up_i
, input [step_width_lp-1:0] down_i
, output logic [ptr_width_lp-1:0] count_o
);
// keeping track of number of entries and updating read and
// write pointers, and displaying errors in case of overflow
// or underflow
always_ff @(posedge clk_i)
begin
if (reset_i)
count_o <= init_val_p;
else
// It was tested on Design Compiler that using a
// simple minus and plus operation results in smaller
// design, rather than using xor or other ideas
// between down_i and up_i
count_o <= count_o - down_i + up_i;
end
//synopsys translate_off
always_ff @ (negedge clk_i) begin
if ((count_o==max_val_p) & up_i & ~down_i & (reset_i === 1'b0))
$display("%m error: counter overflow at time %t", $time);
if ((count_o==0) & down_i & ~up_i & (reset_i === 1'b0))
$display("%m error: counter underflow at time %t", $time);
end
//synopsys translate_on
endmodule
| 8.380223 |
module bsg_counting_leading_zeros #(
parameter `BSG_INV_PARAM(width_p)
, parameter num_zero_width_lp=`BSG_WIDTH(width_p)
)
(
input [width_p-1:0] a_i
,output logic [num_zero_width_lp-1:0] num_zero_o
);
logic [width_p:0] reversed;
genvar i;
for (i = 0; i < width_p; i++) begin
assign reversed[i] = a_i[width_p-1-i];
end
assign reversed[width_p] = 1'b1;
bsg_priority_encode #(
.width_p(width_p+1)
,.lo_to_hi_p(1)
) pe0 (
.i(reversed)
,.addr_o(num_zero_o)
,.v_o()
);
endmodule
| 7.368551 |
module is a counter for credits, that every decimation_p
// credits it would assert token_o signal once.
// It also supports a ready_i signal which declares when it can
// assert token_o. For normal use it could be set to one.
`include "bsg_defines.v"
module bsg_credit_to_token #( parameter `BSG_INV_PARAM(decimation_p )
, parameter `BSG_INV_PARAM(max_val_p )
)
( input clk_i
, input reset_i
, input credit_i
, input ready_i
, output token_o
);
localparam counter_width_lp = `BSG_WIDTH(max_val_p);
localparam step_width_lp = `BSG_WIDTH(decimation_p);
logic [counter_width_lp-1:0] count;
logic [step_width_lp-1:0] up,down;
logic token_ready, token_almost_ready;
bsg_counter_up_down_variable #(.max_val_p(max_val_p)
,.init_val_p(0)
,.max_step_p(decimation_p)
) credit_counter
( .clk_i(clk_i)
, .reset_i(reset_i)
, .up_i(up)
, .down_i(down)
, .count_o(count)
);
// counting the number of credits, and each token would decrease the count
// by deciation_p.
assign up = {{(step_width_lp-1){1'b0}},credit_i};
assign down = token_o ? step_width_lp'($unsigned(decimation_p)) : step_width_lp'(0);
// if count is one less than decimation_p but credit_i is also asserted and
// ready signal is high, we don't need to wait for next time ready_i signal
// is asserted and we can send a token. In this condition count would be set
// to zero using down and up signal.
assign token_ready = (count >= decimation_p);
assign token_almost_ready = (count >= $unsigned(decimation_p-1));
assign token_o = ready_i & (token_ready | (token_almost_ready & credit_i));
endmodule
| 7.329296 |
module bsg_cycle_counter #(
parameter width_p = 32
, init_val_p = 0
) (
input clk_i
, input reset_i
, output logic [width_p-1:0] ctr_r_o
);
always @(posedge clk_i)
if (reset_i) ctr_r_o <= init_val_p;
else ctr_r_o <= ctr_r_o + 1;
endmodule
| 6.833862 |
module bsg_ddr_sampler #(
width_p = "inv"
) (
input clk
, input reset
, input [width_p-1:0] to_be_sampled_i
, output logic [width_p-1:0] pos_edge_value_o
, output logic [width_p-1:0] neg_edge_value_o
, output logic [width_p-1:0] pos_edge_synchronized_o
, output logic [width_p-1:0] neg_edge_synchronized_o
);
bsg_launch_sync_sync #(
.width_p(width_p)
, .use_negedge_for_launch_p(0)
) positive_edge (
.iclk_i(clk)
, .iclk_reset_i(reset)
, .oclk_i(clk)
, .iclk_data_i(to_be_sampled_i)
, .iclk_data_o(pos_edge_value_o)
, .oclk_data_o(pos_edge_synchronized_o)
);
bsg_launch_sync_sync #(
.width_p(width_p)
, .use_negedge_for_launch_p(1)
) negative_edge (
.iclk_i(clk)
, .iclk_reset_i(reset)
, .oclk_i(clk)
, .iclk_data_i(to_be_sampled_i)
, .iclk_data_o(neg_edge_value_o)
, .oclk_data_o(neg_edge_synchronized_o)
);
endmodule
| 7.282722 |
module bsg_decode #(parameter `BSG_INV_PARAM(num_out_p))
(
input [`BSG_SAFE_CLOG2(num_out_p)-1:0] i
,output logic [num_out_p-1:0] o
);
if (num_out_p == 1) begin
// suppress unused signal warning
wire unused = i;
assign o = 1'b1;
end
else begin
assign o = (num_out_p) ' (1'b1 << i);
end
endmodule
| 6.988658 |
module bsg_decode_num_out_p10 (
i,
o
);
input [3:0] i;
output [9:0] o;
wire [9:0] o;
assign o = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_num_out_p2 (
i,
o
);
input [0:0] i;
output [1:0] o;
wire [1:0] o;
assign o = {1'b0, 1'b1} << i[0];
endmodule
| 6.955703 |
module bsg_decode_num_out_p3 (
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
assign o = {1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_num_out_p4 (
i,
o
);
input [1:0] i;
output [3:0] o;
wire [3:0] o;
assign o = {1'b0, 1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_num_out_p5 (
i,
o
);
input [2:0] i;
output [4:0] o;
wire [4:0] o;
assign o = {1'b0, 1'b0, 1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_num_out_p8 (
i,
o
);
input [2:0] i;
output [7:0] o;
wire [7:0] o;
assign o = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1} << i;
endmodule
| 6.955703 |
module bsg_decode_with_v #(parameter `BSG_INV_PARAM(num_out_p))
(
input [`BSG_SAFE_CLOG2(num_out_p)-1:0] i
,input v_i
,output [num_out_p-1:0] o
);
wire [num_out_p-1:0] lo;
bsg_decode #(.num_out_p(num_out_p)
) bd
(.i
,.o(lo)
);
assign o = { (num_out_p) { v_i } } & lo;
endmodule
| 7.148573 |
module bsg_dff_async_reset
#(parameter `BSG_INV_PARAM(width_p )
,parameter reset_val_p = 0
,parameter harden_p = 0
)
(input clk_i
,input async_reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
logic [width_p-1:0] data_r;
assign data_o = data_r;
always_ff @(posedge clk_i or posedge async_reset_i)
if (async_reset_i)
data_r <= (width_p)'(reset_val_p);
else
data_r <= data_i;
endmodule
| 7.198195 |
module bsg_dff_chain #(
//the width of the input signal
parameter `BSG_INV_PARAM( width_p )
//the stages of the chained DFF register
//can be 0
,parameter num_stages_p = 1
)
(
input clk_i
,input [width_p-1:0] data_i
,output[width_p-1:0] data_o
);
if( num_stages_p == 0) begin:pass_through
wire unused = clk_i;
assign data_o = data_i;
end:pass_through
else begin:chained
// data_i -- delayed[0]
//
// data_o -- delayed[num_stages_p]
logic [num_stages_p:0][width_p-1:0] data_delayed;
assign data_delayed[0] = data_i ;
assign data_o = data_delayed[num_stages_p] ;
genvar i;
for(i=1; i<= num_stages_p; i++) begin
bsg_dff #( .width_p ( width_p ) )
ch_reg (
.clk_i ( clk_i )
,.data_i ( data_delayed[ i-1 ] )
,.data_o ( data_delayed[ i ] )
);
end
end:chained
endmodule
| 6.915153 |
module bsg_dff_en #(
parameter width_p = "inv"
, parameter harden_p = 1 // mbt fixme: maybe this should not be a default
, parameter strength_p = 1
) (
input clk_i
, input [width_p-1:0] data_i
, input en_i
, output logic [width_p-1:0] data_o
);
logic [width_p-1:0] data_r;
assign data_o = data_r;
always_ff @(posedge clk_i) begin
if (en_i) begin
data_r <= data_i;
end
end
endmodule
| 6.9523 |
module bsg_dff_en_bypass
#(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=0
, parameter strength_p=0
)
(
input clk_i
, input en_i
, input [width_p-1:0] data_i
, output logic [width_p-1:0] data_o
);
logic [width_p-1:0] data_r;
bsg_dff_en #(
.width_p(width_p)
,.harden_p(harden_p)
,.strength_p(strength_p)
) dff (
.clk_i(clk_i)
,.en_i(en_i)
,.data_i(data_i)
,.data_o(data_r)
);
assign data_o = en_i
? data_i
: data_r;
endmodule
| 7.758381 |
module bsg_dff_en_width_p1 (
clock_i,
data_i,
en_i,
data_o
);
input [0:0] data_i;
output [0:0] data_o;
input clock_i;
input en_i;
reg [0:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p16_harden_p0 (
clk_i,
data_i,
en_i,
data_o
);
input [15:0] data_i;
output [15:0] data_o;
input clk_i;
input en_i;
wire [15:0] data_o;
reg
data_o_15_sv2v_reg,
data_o_14_sv2v_reg,
data_o_13_sv2v_reg,
data_o_12_sv2v_reg,
data_o_11_sv2v_reg,
data_o_10_sv2v_reg,
data_o_9_sv2v_reg,
data_o_8_sv2v_reg,
data_o_7_sv2v_reg,
data_o_6_sv2v_reg,
data_o_5_sv2v_reg,
data_o_4_sv2v_reg,
data_o_3_sv2v_reg,
data_o_2_sv2v_reg,
data_o_1_sv2v_reg,
data_o_0_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if (en_i) begin
data_o_15_sv2v_reg <= data_i[15];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_14_sv2v_reg <= data_i[14];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_13_sv2v_reg <= data_i[13];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_12_sv2v_reg <= data_i[12];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_11_sv2v_reg <= data_i[11];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_10_sv2v_reg <= data_i[10];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_9_sv2v_reg <= data_i[9];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if (en_i) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p32 (
clock_i,
data_i,
en_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clock_i;
input en_i;
reg [31:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[31] <= data_i[31];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[30] <= data_i[30];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[29] <= data_i[29];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[28] <= data_i[28];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[27] <= data_i[27];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[26] <= data_i[26];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[25] <= data_i[25];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[24] <= data_i[24];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[23] <= data_i[23];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[22] <= data_i[22];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[21] <= data_i[21];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[20] <= data_i[20];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[19] <= data_i[19];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[18] <= data_i[18];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[17] <= data_i[17];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[16] <= data_i[16];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[15] <= data_i[15];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[14] <= data_i[14];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[13] <= data_i[13];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[12] <= data_i[12];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[11] <= data_i[11];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[10] <= data_i[10];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[9] <= data_i[9];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[8] <= data_i[8];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[7] <= data_i[7];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[6] <= data_i[6];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[5] <= data_i[5];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[4] <= data_i[4];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[3] <= data_i[3];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[2] <= data_i[2];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[1] <= data_i[1];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p33 (
clock_i,
data_i,
en_i,
data_o
);
input [32:0] data_i;
output [32:0] data_o;
input clock_i;
input en_i;
reg [32:0] data_o;
always @(posedge clock_i) begin
if (en_i) begin
data_o[32] <= data_i[32];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[31] <= data_i[31];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[30] <= data_i[30];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[29] <= data_i[29];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[28] <= data_i[28];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[27] <= data_i[27];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[26] <= data_i[26];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[25] <= data_i[25];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[24] <= data_i[24];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[23] <= data_i[23];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[22] <= data_i[22];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[21] <= data_i[21];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[20] <= data_i[20];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[19] <= data_i[19];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[18] <= data_i[18];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[17] <= data_i[17];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[16] <= data_i[16];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[15] <= data_i[15];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[14] <= data_i[14];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[13] <= data_i[13];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[12] <= data_i[12];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[11] <= data_i[11];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[10] <= data_i[10];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[9] <= data_i[9];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[8] <= data_i[8];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[7] <= data_i[7];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[6] <= data_i[6];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[5] <= data_i[5];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[4] <= data_i[4];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[3] <= data_i[3];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[2] <= data_i[2];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[1] <= data_i[1];
end
end
always @(posedge clock_i) begin
if (en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p36 (
clk_i,
data_i,
en_i,
data_o
);
input [35:0] data_i;
output [35:0] data_o;
input clk_i;
input en_i;
reg [35:0] data_o;
always @(posedge clk_i) begin
if (en_i) begin
{data_o[35:0]} <= {data_i[35:0]};
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p5 (
clk_i,
data_i,
en_i,
data_o
);
input [4:0] data_i;
output [4:0] data_o;
input clk_i;
input en_i;
reg [4:0] data_o;
always @(posedge clk_i) begin
if (en_i) begin
{data_o[4:0]} <= {data_i[4:0]};
end
end
endmodule
| 6.557007 |
module bsg_dff_en_width_p64 (
clk_i,
data_i,
en_i,
data_o
);
input [63:0] data_i;
output [63:0] data_o;
input clk_i;
input en_i;
reg [63:0] data_o;
always @(posedge clk_i) begin
if (en_i) begin
{data_o[63:0]} <= {data_i[63:0]};
end
end
endmodule
| 6.557007 |
module bsg_dff_gatestack #(
width_p = "inv",
harden_p = 1
) (
input [width_p-1:0] i0
, input [width_p-1:0] i1
, output logic [width_p-1:0] o
);
initial $display("%m: warning module not actually hardened.");
genvar j;
for (j = 0; j < width_p; j = j + 1) begin
always_ff @(posedge i1[j]) o[j] <= i0[j];
end
endmodule
| 6.610787 |
module bsg_dff_negedge_reset #(`BSG_INV_PARAM(width_p), harden_p=0)
(input clk_i
,input reset_i
,input [width_p-1:0] data_i
,output [width_p-1:0] data_o
);
reg [width_p-1:0] data_r;
assign data_o = data_r;
always @(negedge clk_i)
begin
if (reset_i)
data_r <= width_p'(0);
else
data_r <= data_i;
end
endmodule
| 7.238159 |
module bsg_dmc_clk_rst_gen
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p = 2
,parameter `BSG_INV_PARAM(num_lines_p ))
(input bsg_tag_s async_reset_tag_i
,input bsg_tag_s [num_lines_p-1:0] bsg_dly_tag_i
,input bsg_tag_s [num_lines_p-1:0] bsg_dly_trigger_tag_i
,input bsg_tag_s bsg_ds_tag_i
// asynchronous reset for dram controller
,output async_reset_o
// clock input and delayed clock output (for dqs), generating 90-degree phase
// shift
,input [num_lines_p-1:0] clk_i
,output [num_lines_p-1:0] clk_o
// 2x clock input from clock generator and 1x clock output
,input clk_2x_i
,output clk_1x_o);
localparam debug_level_lp = 0;
genvar i;
bsg_tag_client_unsync #(.width_p(1)) btc_async_reset
(.bsg_tag_i ( async_reset_tag_i )
,.data_async_r_o ( async_reset_o ));
// Clock Generator (CG) Instance
for(i=0;i<num_lines_p;i++) begin: dly_lines
bsg_dly_line #(.num_adgs_p(num_adgs_p)) dly_line_inst
(.bsg_tag_i ( bsg_dly_tag_i[i] )
,.bsg_tag_trigger_i ( bsg_dly_trigger_tag_i[i] )
,.async_reset_i ( async_reset_o )
,.clk_i ( clk_i[i] )
,.clk_o ( clk_o[i] ));
end
`declare_bsg_clk_gen_ds_tag_payload_s(2)
bsg_clk_gen_ds_tag_payload_s ds_tag_payload_r;
wire ds_tag_payload_new_r;
// fixme: maybe wire up a default and deal with reset issue?
// downsampler bsg_tag interface
bsg_tag_client #
(.width_p ( $bits(bsg_clk_gen_ds_tag_payload_s) )
,.harden_p ( 1 ))
btc_ds
(.bsg_tag_i ( bsg_ds_tag_i )
,.recv_clk_i ( clk_2x_i )
,.recv_new_r_o ( ds_tag_payload_new_r ) // we don't require notification
,.recv_data_r_o ( ds_tag_payload_r ));
if (debug_level_lp > 1)
always_ff @(negedge clk_2x_i) begin
if (ds_tag_payload_new_r)
$display("## bsg_clk_gen downsampler received configuration state: %b",ds_tag_payload_r);
end
// clock downsampler
//
// we allow the clock downsample reset to be accessed via bsg_tag; this way
// we can turn it off by holding reset high to save power.
//
bsg_counter_clock_downsample #
(.width_p ( 2 )
,.harden_p ( 1 ))
clk_gen_ds_inst
(.clk_i ( clk_2x_i )
,.reset_i ( ds_tag_payload_r.reset )
,.val_i ( 2'd0 )
,.clk_r_o ( clk_1x_o ));
endmodule
| 9.147596 |
module bsg_dmc_phy_bit_slice (
input clk_1x_i
, input clk_2x_i
, input dqs_p_i
, input dqs_n_i
, input wrdata_en_90_i
, input [1:0] wrdata_90_i
, output dq_o
, output dq_oe_n_o
, input dq_i
, input [1:0] write_pointer_i
, input [1:0] read_pointer_i
, output rddata_even_o
, output rddata_odd_o
);
bsg_dmc_phy_tx_bit_slice tx_bit_slice (
.clk_2x_i (clk_2x_i)
, .wrdata_en_90_i(wrdata_en_90_i)
, .wrdata_90_i (wrdata_90_i)
, .dq_o (dq_o)
, .dq_oe_n_o (dq_oe_n_o)
);
bsg_dmc_phy_rx_bit_slice rx_bit_slice (
.clk_1x_i (clk_1x_i)
, .write_pointer_i(write_pointer_i)
, .read_pointer_i (read_pointer_i)
, .dq_i (dq_i)
, .dqs_p_i (dqs_p_i)
, .dqs_n_i (dqs_n_i)
, .rddata_even_o (rddata_even_o)
, .rddata_odd_o (rddata_odd_o)
);
endmodule
| 6.572972 |
module bsg_dmc_phy_byte_lane (
input reset_i
, input clk_1x_i
, input clk_2x_i
, input wrdata_en_i
, input [15:0] wrdata_i
, input [ 1:0] wrdata_mask_i
, output dm_oe_n_o
, output dm_o
, output [ 7:0] dq_oe_n_o
, output [ 7:0] dq_o
, output logic dqs_p_oe_n_o
, output logic dqs_p_o
, output logic dqs_n_oe_n_o
, output logic dqs_n_o
, input rp_inc_i
, output [15:0] rddata_o
, input [ 7:0] dq_i
, input dqs_p_i
, input dqs_n_i
);
wire clk_1x_p = clk_1x_i;
wire clk_2x_p = clk_2x_i;
wire clk_2x_n = ~clk_2x_i;
logic wrdata_en_90, wrdata_en_180;
logic [15:0] wrdata_90, wrdata_180;
logic [1:0] wrdata_mask_90, wrdata_mask_180;
logic [1:0] write_pointer, read_pointer;
genvar i;
always_ff @(posedge clk_2x_n) begin
wrdata_en_90 <= wrdata_en_i;
wrdata_90 <= wrdata_i;
wrdata_mask_90 <= wrdata_mask_i;
end
always_ff @(posedge clk_2x_p) begin
wrdata_en_180 <= wrdata_en_i;
end
always_ff @(posedge clk_2x_p) begin
dqs_p_oe_n_o <= ~(wrdata_en_i | wrdata_en_180);
dqs_n_oe_n_o <= ~(wrdata_en_i | wrdata_en_180);
end
always_ff @(posedge clk_2x_p) begin
if (wrdata_en_i || wrdata_en_180) begin
dqs_p_o <= ~dqs_p_o;
dqs_n_o <= ~dqs_n_o;
end else begin
dqs_p_o <= 1'b1;
dqs_n_o <= 1'b0;
end
end
always_ff @(posedge dqs_n_i or posedge reset_i) begin
if (reset_i) write_pointer <= 'b0;
else write_pointer <= write_pointer + 1'b1;
end
always_ff @(posedge clk_1x_p) begin
if (reset_i) read_pointer <= 'b0;
else if (rp_inc_i) read_pointer <= read_pointer + 1'b1;
end
for (i = 0; i < 8; i++) begin : bs
bsg_dmc_phy_bit_slice dq_bit_slice (
.clk_1x_i (clk_1x_i)
, .clk_2x_i (clk_2x_i)
, .dqs_p_i (dqs_p_i)
, .dqs_n_i (dqs_n_i)
, .wrdata_en_90_i (wrdata_en_90)
, .wrdata_90_i ({wrdata_90[8+i], wrdata_90[i]})
, .dq_o (dq_o[i])
, .dq_oe_n_o (dq_oe_n_o[i])
, .dq_i (dq_i[i])
, .write_pointer_i(write_pointer)
, .read_pointer_i (read_pointer)
, .rddata_even_o (rddata_o[i])
, .rddata_odd_o (rddata_o[8+i])
);
end
bsg_dmc_phy_tx_bit_slice dm_bit_slice (
.clk_2x_i (clk_2x_i)
, .wrdata_en_90_i(wrdata_en_90)
, .wrdata_90_i (wrdata_mask_90)
, .dq_o (dm_o)
, .dq_oe_n_o (dm_oe_n_o)
);
endmodule
| 6.572972 |
module is simply a 4-input mux. The edge balancing
// properties are process specific. A 250nm harded version
// can be found at:
//
// bsg_ip_cores/hard/bsg_clk_gen/bsg_edge_balanced_mux4.v
//
// This module should be replaced by the hardened version
// when being synthesized.
//
`include "bsg_defines.v"
module bsg_edge_balanced_mux4
(input A
,input B
,input C
,input D
,input [1:0] S
,output logic Y
);
always_comb
begin
case (S)
0: Y = A;
1: Y = B;
2: Y = C;
3: Y = D;
default: Y = 1'bx;
endcase
end
endmodule
| 8.176708 |
module bsg_edge_detect #(
parameter falling_not_rising_p = 0
) (
input clk_i
, input reset_i
, input sig_i
, output detect_o
);
logic sig_r;
bsg_dff_reset #(
.width_p(1)
) sig_reg (
.clk_i (clk_i)
, .reset_i(reset_i)
, .data_i(sig_i)
, .data_o(sig_r)
);
if (falling_not_rising_p == 1) begin : falling
assign detect_o = ~sig_i & sig_r;
end else begin : rising
assign detect_o = sig_i & ~sig_r;
end
endmodule
| 7.356085 |
module expands each bit in the input vector by the factor of
* expand_p.
*
* @author tommy
*
*
* example
* ------------------------
* in_width_p=2, expand_p=4
* ------------------------
* i=00 -> o=0000_0000
* i=01 -> o=0000_1111
* i=10 -> o=1111_0000
* i=11 -> o=1111_1111
*
*/
`include "bsg_defines.v"
module bsg_expand_bitmask #(parameter `BSG_INV_PARAM(in_width_p)
,parameter `BSG_INV_PARAM(expand_p)
,localparam safe_expand_lp = `BSG_MAX(expand_p, 1))
(
input [in_width_p-1:0] i
, output logic [(in_width_p*safe_expand_lp)-1:0] o
);
always_comb
for (integer k = 0; k < in_width_p; k++)
o[safe_expand_lp*k+:safe_expand_lp] = {safe_expand_lp{i[k]}};
endmodule
| 7.2345 |
module is a small fifo which has a bsg_channel_narrow
// on its output, that would send out each data in several steps
// based on the input and output width. width_p is the FIFO data
// width and width_out_p is the output width. els_p is the number
// of elements in fifo and lsb_to_msb_p determined the directions
// of sending the data. ready_THEN_valid_p determined input
// handshake protocol.
`include "bsg_defines.v"
module bsg_fifo_1r1w_narrowed
#( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter `BSG_INV_PARAM(width_out_p )
, parameter lsb_to_msb_p = 1
, parameter ready_THEN_valid_p = 0
)
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output ready_o
, output v_o
, output [width_out_p-1:0] data_o
, input yumi_i
);
// Internal signals
logic [width_p-1:0] data;
logic yumi;
// FIFO of els_p elements of width width_p
bsg_fifo_1r1w_small #(.width_p(width_p)
,.els_p(els_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) main_fifo
( .clk_i(clk_i)
, .reset_i(reset_i)
, .data_i(data_i)
, .v_i(v_i)
, .ready_o(ready_o)
, .v_o(v_o)
, .data_o(data)
, .yumi_i(yumi)
);
// selecting from two FIFO outputs and sending one out at a time
bsg_channel_narrow #( .width_in_p(width_p)
, .width_out_p(width_out_p)
, .lsb_to_msb_p(lsb_to_msb_p)
) output_narrower
( .clk_i(clk_i)
, .reset_i(reset_i)
, .data_i(data)
, .deque_o(yumi)
, .data_o(data_o)
, .deque_i(yumi_i)
);
endmodule
| 8.28436 |
module converts between the valid-credit (input) and
// valid-ready (output) handshakes, by using a fifo to keep
// the data
`include "bsg_defines.v"
module bsg_fifo_1r1w_small_credit_on_input #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter harden_p = 0
)
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output logic credit_o
, output v_o
, output [width_p-1:0] data_o
, input yumi_i
);
// internal signal for assert
logic ready;
// Yumi can be asserted during clock period, but credit must
// be asserted at the beginning of a cycle
always_ff @ (posedge clk_i)
if (reset_i)
credit_o <= 0;
else
credit_o <= yumi_i;
// ready_o is not checked since it is guaranteed by credit
// system not to send extra inputs and every input must be
// stored
// FIFO used to keep the data values
// credit protocol must take care of not enquing while fifo
// is full, and assert an error otherwise, so it is like a
// fifo with ready_then_valid protocol
bsg_fifo_1r1w_small #( .width_p(width_p)
, .els_p(els_p)
, .ready_THEN_valid_p(1)
, .harden_p(harden_p)
) fifo
( .clk_i(clk_i)
, .reset_i(reset_i)
, .data_i(data_i)
, .v_i(v_i)
, .ready_o(ready)
, .v_o(v_o)
, .data_o(data_o)
, .yumi_i(yumi_i)
);
endmodule
| 7.684328 |
module defines functional coverages of module bsg_fifo_1r1w_small_hardened
//
//
`include "bsg_defines.v"
module bsg_fifo_1r1w_small_hardened_cov
#(parameter els_p = "inv"
,localparam ptr_width_lp = `BSG_SAFE_CLOG2(els_p)
)
(input clk_i
,input reset_i
// interface signals
,input v_i
,input yumi_i
// internal registers
,input [ptr_width_lp-1:0] rptr_r
,input [ptr_width_lp-1:0] wptr_r
,input full // registered in sub-module bsg_fifo_tracker
,input empty // registered in sub-module bsg_fifo_tracker
,input read_write_same_addr_r
);
// reset
covergroup cg_reset @(negedge clk_i);
coverpoint reset_i;
endgroup
// Partitioning covergroup into smaller ones
// empty
covergroup cg_empty @ (negedge clk_i iff ~reset_i & empty & ~full);
cp_v: coverpoint v_i;
// cannot deque when empty
cp_yumi: coverpoint yumi_i {illegal_bins ig = {1};}
cp_rptr: coverpoint rptr_r;
cp_wptr: coverpoint wptr_r;
// If read write same address happened in previous cycle, fifo should
// have one element in current cycle, which contradicts with the
// condition that fifo is empty.
cp_rwsa: coverpoint read_write_same_addr_r {illegal_bins ig = {1};}
cross_all: cross cp_v, cp_yumi, cp_rptr, cp_wptr, cp_rwsa {
// by definition, fifo empty means r/w pointers are the same
illegal_bins ig0 = cross_all with (cp_rptr != cp_wptr);
}
endgroup
// full
covergroup cg_full @ (negedge clk_i iff ~reset_i & ~empty & full);
cp_v: coverpoint v_i;
cp_yumi: coverpoint yumi_i;
cp_rptr: coverpoint rptr_r;
cp_wptr: coverpoint wptr_r;
// If read write same address happened in previous cycle, fifo should
// only have one element in current cycle, which contradicts with the
// condition that fifo is full.
cp_rwsa: coverpoint read_write_same_addr_r {illegal_bins ig = {1};}
cross_all: cross cp_v, cp_yumi, cp_rptr, cp_wptr, cp_rwsa {
// by definition, fifo full means r/w pointers are the same
illegal_bins ig0 = cross_all with (cp_rptr != cp_wptr);
}
endgroup
// fifo normal
covergroup cg_normal @ (negedge clk_i iff ~reset_i & ~empty & ~full);
cp_v: coverpoint v_i;
cp_yumi: coverpoint yumi_i;
cp_rptr: coverpoint rptr_r;
cp_wptr: coverpoint wptr_r;
cp_rwsa: coverpoint read_write_same_addr_r;
cross_all: cross cp_v, cp_yumi, cp_rptr, cp_wptr, cp_rwsa {
// by definition, r/w pointers are different when fifo is non-empty & non-full
illegal_bins ig0 = cross_all with (cp_rptr == cp_wptr);
// If read write same address happened in previous cycle, fifo should
// only have one element in current cycle. Write-pointer should be
// read-pointer plus one (or wrapped-around).
illegal_bins ig1 = cross_all with (
(cp_rwsa == 1)
&& (cp_wptr - cp_rptr != 1)
&& (cp_wptr - cp_rptr != 1-els_p)
);
}
endgroup
// create cover groups
cg_reset cov_reset = new;
cg_empty cov_empty = new;
cg_full cov_full = new;
cg_normal cov_normal = new;
// print coverages when simulation is done
final
begin
$display("");
$display("Instance: %m");
$display("---------------------- Functional Coverage Results ----------------------");
$display("Reset functional coverage is %f%%", cov_reset.get_coverage());
$display("Fifo empty functional coverage is %f%%", cov_empty.cross_all.get_coverage());
$display("Fifo full functional coverage is %f%%", cov_full.cross_all.get_coverage());
$display("Fifo normal functional coverage is %f%%", cov_normal.cross_all.get_coverage());
$display("-------------------------------------------------------------------------");
$display("");
end
endmodule
| 8.303558 |
module bsg_fifo_reorder
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter lg_els_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input clk_i
, input reset_i
// FIFO allocates the next available addr
, output fifo_alloc_v_o
, output [lg_els_lp-1:0] fifo_alloc_id_o
, input fifo_alloc_yumi_i
// random access write
// data can be written out of order
, input write_v_i
, input [lg_els_lp-1:0] write_id_i
, input [width_p-1:0] write_data_i
// dequeue written items in order
, output fifo_deq_v_o
, output [width_p-1:0] fifo_deq_data_o
// id of the currently dequeueing fifo entry. This can be used to select
// metadata from a separate memory storage, written at a different time
, output [lg_els_lp-1:0] fifo_deq_id_o
, input fifo_deq_yumi_i
// this signals that the FIFO is empty
// i.e. there is no reserved spot for returning data,
// and all valid data in the FIFO has been consumed.
, output logic empty_o
);
// fifo tracker
// enque when id is allocated.
// deque when data is dequeued.
logic [lg_els_lp-1:0] wptr_r, rptr_r;
logic full, empty;
logic enq, deq;
bsg_fifo_tracker #(
.els_p(els_p)
) tracker0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.enq_i(enq)
,.deq_i(deq)
,.wptr_r_o(wptr_r)
,.rptr_r_o(rptr_r)
,.rptr_n_o()
,.full_o(full)
,.empty_o(empty)
);
assign fifo_alloc_v_o = ~full;
assign enq = ~full & fifo_alloc_yumi_i;
assign fifo_alloc_id_o = wptr_r;
assign empty_o = empty;
// valid bit for each entry
// this valid bit is cleared, when the valid data is dequeued.
// this valid bit is set, when the valid data is written.
logic [els_p-1:0] valid_r;
logic [els_p-1:0] set_valid;
logic [els_p-1:0] clear_valid;
bsg_decode_with_v #(
.num_out_p(els_p)
) set_demux0 (
.i(write_id_i)
,.v_i(write_v_i)
,.o(set_valid)
);
bsg_decode_with_v #(
.num_out_p(els_p)
) clear_demux0 (
.i(rptr_r)
,.v_i(deq)
,.o(clear_valid)
);
bsg_dff_reset_set_clear #(
.width_p(els_p)
) dff_valid0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.set_i(set_valid)
,.clear_i(clear_valid)
,.data_o(valid_r)
);
// deque logic
wire fifo_deq_v_lo = valid_r[rptr_r] & ~empty;
assign fifo_deq_v_o = fifo_deq_v_lo;
assign deq = fifo_deq_yumi_i;
// data storage
bsg_mem_1r1w #(
.width_p(width_p)
,.els_p(els_p)
) mem0 (
.w_clk_i(clk_i)
,.w_reset_i(reset_i)
,.w_v_i(write_v_i)
,.w_addr_i(write_id_i)
,.w_data_i(write_data_i)
,.r_v_i(fifo_deq_v_lo)
,.r_addr_i(rptr_r)
,.r_data_o(fifo_deq_data_o)
);
assign fifo_deq_id_o = rptr_r;
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (fifo_alloc_yumi_i)
assert(fifo_alloc_v_o) else $error("Handshaking error. fifo_alloc_yumi_i raised without fifo_alloc_v_o.");
if (fifo_deq_yumi_i)
assert(fifo_deq_v_o) else $error("Handshaking error. fifo_deq_yumi_i raised without fifo_deq_v_o.");
if (write_v_i)
assert(~valid_r[write_id_i]) else $error("Cannot write to an already valid data.");
end
end
// synopsys translate_on
endmodule
| 7.177236 |
module bsg_flatten_2D_array #(parameter `BSG_INV_PARAM( width_p )
, parameter `BSG_INV_PARAM(items_p ))
(input [width_p-1:0] i [items_p-1:0]
, output [width_p*items_p-1:0] o
);
genvar j;
for (j = 0; j < items_p; j=j+1)
begin
assign o[j*width_p+:width_p] = i[j];
end
endmodule
| 8.193276 |
module converts between the various link-level flow-control
// protocols.
//
// fixme: many of the cases have not been tested. naming convention might
// be better. more asserts would be good. send_v_and_ready_p does not seem to
// be implemented. clocked versions should be handled by separate module.
//
// USAGE:
//
// 1. You need exactly one send_ parameter set and one recv parameter set.
// 2. A parameter x_then_y says that the signal y is combinationally dependent on x.
// 3. A parameter x_and_y says that the signal x and y are not combinationally dependent.
// So for example, yumi by definition is combinationally dependent on v,
// since the downstream module looks at the v signal and then decides to assert yumi.
// Hence, v_then_yumi is appropriate.
//
// Similarly, if you have a module that asserts v, but only if the downstream
// module indicates that it is ready, then, you would have ready_then_v.
//
// On the other hand, if both upsteam and downstream module are supposed to
// assert their signals in parallel, then it would be v_and_ready.
//
// Here is an example usage:
//
// bsg_flow_convert #(.width_p(nodes_p)
// ,.send_v_and_ready_p(1)
// ,.recv_v_and_retry_p(1)
// ) s2b
// (.v_i (v_i)
// ,.fc_o(ready_o)
//
// ,.v_o(switch_2_blockValid)
// ,.fc_i(switch_2_blockRetry)
// );
//
`include "bsg_defines.v"
module bsg_flow_convert
#(parameter send_v_and_ready_p = 0
, parameter send_v_then_yumi_p = 0
, parameter send_ready_then_v_p = 0
, parameter send_retry_then_v_p = 0
, parameter send_v_and_retry_p = 0
, parameter recv_v_and_ready_p = 0
, parameter recv_v_then_yumi_p = 0
, parameter recv_ready_then_v_p = 0
// recv and retry are independent signals
, parameter recv_v_and_retry_p = 0
// retry is dependent on retry
, parameter recv_v_then_retry_p = 0
, parameter width_p = 1
)
(input [width_p-1:0] v_i
, output [width_p-1:0] fc_o
, output [width_p-1:0] v_o
, input [width_p-1:0] fc_i
);
// if yumi needs to be made conditional on valid
if ((send_v_then_yumi_p & recv_v_and_ready_p)
| (send_v_then_yumi_p & recv_ready_then_v_p)
)
assign fc_o = fc_i & v_i;
// similar case but retry must be inverted
else if (send_v_then_yumi_p & recv_v_and_retry_p)
assign fc_o = ~fc_i & v_i;
else if (send_ready_then_v_p & recv_v_then_yumi_p)
// fixme fifo
initial begin $display("### %m a unhandled case requires fifo"); $finish(); end
else if (send_ready_then_v_p & recv_v_then_retry_p)
// fixme fifo inverted retry
initial begin $display("### %m unhandled case requires fifo"); $finish();
end
// if retry needs to be inverted to be a ready signal
// or a ready needs to be inverted to be a retry
else if (send_retry_then_v_p & recv_v_then_yumi_p)
initial begin $display("### %m unhandled case requires fifo"); $finish();
end
else if ((send_retry_then_v_p | send_v_and_retry_p) ^ (recv_v_then_retry_p | recv_v_and_retry_p))
assign fc_o = ~fc_i;
else
assign fc_o = fc_i;
// if valid needs to be made conditional on ready
if (recv_ready_then_v_p & ~send_ready_then_v_p)
assign v_o = v_i & fc_i;
else
assign v_o = v_i;
endmodule
| 7.684328 |
module or set of
// modules which have ready-and-valid or ready-then-valid
// (base on the ready_THEN_valid_p parameter) input protocol
// and valid-then-yumi protocol for the output. Based on the
// count_free_p it will count the number of free elements or
// number of existing elements in the connected module.
`include "bsg_defines.v"
module bsg_flow_counter #(parameter `BSG_INV_PARAM(els_p )
, parameter count_free_p = 0
, parameter ready_THEN_valid_p = 0
//localpara
, parameter ptr_width_lp =
`BSG_WIDTH(els_p)
)
( input clk_i
, input reset_i
, input v_i
, input ready_i
, input yumi_i
, output [ptr_width_lp-1:0] count_o
);
// internal signals
logic enque;
// In valid-ready protocol both ends assert their signal at the
// beginning of the cycle, and if the sender end finds that receiver
// was not ready it would send it again. So in the receiver side
// valid means enque if it could accept it
if (ready_THEN_valid_p) begin: gen_blk_protocol_select
assign enque = v_i;
end else begin: gen_blk_protocol_select
assign enque = v_i & ready_i;
end
generate
if (count_free_p) begin: gen_blk_0
// An up-down counter is used for counting free slots.
// it starts with number of elements and that is also
// the max value it can reach.
bsg_counter_up_down #( .max_val_p(els_p)
, .init_val_p(els_p)
, .max_step_p(1)
) counter
( .clk_i(clk_i)
, .reset_i(reset_i)
, .up_i(yumi_i)
, .down_i(enque)
, .count_o(count_o)
);
end else begin: gen_blk_0
bsg_counter_up_down #( .max_val_p(els_p)
, .init_val_p(0)
, .max_step_p(1)
) counter
( .clk_i(clk_i)
, .reset_i(reset_i)
, .up_i(enque)
, .down_i(yumi_i)
, .count_o(count_o)
);
end
endgenerate
endmodule
| 7.889231 |
module bsg_fpu_classify
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
, parameter width_lp=(e_p+m_p+1)
, parameter out_width_lp=width_lp
)
(
input [width_lp-1:0] a_i
, output [out_width_lp-1:0] class_o
);
logic zero;
logic nan;
logic sig_nan;
logic infty;
logic denormal;
logic sign;
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) prep (
.a_i(a_i)
,.zero_o(zero)
,.nan_o(nan)
,.sig_nan_o(sig_nan)
,.infty_o(infty)
,.exp_zero_o()
,.man_zero_o()
,.denormal_o(denormal)
,.sign_o(sign)
,.exp_o()
,.man_o()
);
assign class_o[0] = sign & infty;
assign class_o[1] = sign & (~infty) & (~denormal) & (~nan) & (~zero);
assign class_o[2] = sign & denormal;
assign class_o[3] = sign & zero;
assign class_o[4] = ~sign & zero;
assign class_o[5] = ~sign & denormal;
assign class_o[6] = ~sign & (~infty) & (~denormal) & (~nan) & (~zero);
assign class_o[7] = ~sign & infty;
assign class_o[8] = sig_nan;
assign class_o[9] = nan & ~sig_nan;
assign class_o[out_width_lp-1:10] = '0;
endmodule
| 8.351391 |
module bsg_fpu_clz
#(parameter `BSG_INV_PARAM(width_p)
, localparam lg_width_lp=`BSG_SAFE_CLOG2(width_p)
)
(
input [width_p-1:0] i
, output logic [lg_width_lp-1:0] num_zero_o
);
logic [width_p-1:0] reversed;
for (genvar j = 0; j < width_p; j++) begin
assign reversed[j] = i[width_p-1-j];
end
bsg_priority_encode #(
.width_p(width_p)
,.lo_to_hi_p(1)
) pe0 (
.i(reversed)
,.addr_o(num_zero_o)
,.v_o()
);
endmodule
| 7.030453 |
module bsg_fpu_cmp
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
)
(
input [e_p+m_p:0] a_i
, input [e_p+m_p:0] b_i
// comparison
, output logic eq_o
, output logic lt_o
, output logic le_o
, output logic lt_le_invalid_o
, output logic eq_invalid_o
// min-max
, output logic [e_p+m_p:0] min_o
, output logic [e_p+m_p:0] max_o
, output logic min_max_invalid_o
);
// preprocess
//
logic a_zero, a_nan, a_sig_nan, a_infty, a_sign;
logic b_zero, b_nan, b_sig_nan, b_infty, b_sign;
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) a_preprocess (
.a_i(a_i)
,.zero_o(a_zero)
,.nan_o(a_nan)
,.sig_nan_o(a_sig_nan)
,.infty_o(a_infty)
,.exp_zero_o()
,.man_zero_o()
,.denormal_o()
,.sign_o(a_sign)
,.exp_o()
,.man_o()
);
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) b_preprocess (
.a_i(b_i)
,.zero_o(b_zero)
,.nan_o(b_nan)
,.sig_nan_o(b_sig_nan)
,.infty_o(b_infty)
,.exp_zero_o()
,.man_zero_o()
,.denormal_o()
,.sign_o(b_sign)
,.exp_o()
,.man_o()
);
// compare
//
logic mag_a_lt;
bsg_less_than #(
.width_p(e_p+m_p)
) lt_mag (
.a_i(a_i[0+:e_p+m_p])
,.b_i(b_i[0+:e_p+m_p])
,.o(mag_a_lt)
);
// comparison
//
always_comb begin
if (a_nan | b_nan) begin
eq_o = 1'b0;
lt_o = 1'b0;
le_o = 1'b0;
lt_le_invalid_o = 1'b1;
eq_invalid_o = a_sig_nan | b_sig_nan;
end
else begin
if (a_zero & b_zero) begin
eq_o = 1'b1;
lt_o = 1'b0;
le_o = 1'b1;
lt_le_invalid_o = 1'b0;
eq_invalid_o = 1'b0;
end
else begin
// a and b are neither NaNs nor zeros.
// compare sign and compare magnitude.
eq_o = (a_i == b_i);
lt_le_invalid_o = 1'b0;
eq_invalid_o = 1'b0;
case ({a_sign, b_sign})
2'b00: begin
lt_o = mag_a_lt;
le_o = mag_a_lt | eq_o;
end
2'b01: begin
lt_o = 1'b0;
le_o = 1'b0;
end
2'b10: begin
lt_o = 1'b1;
le_o = 1'b1;
end
2'b11: begin
lt_o = ~mag_a_lt & ~eq_o;
le_o = ~mag_a_lt | eq_o;
end
endcase
end
end
end
// min-max
//
always_comb begin
if (a_nan & b_nan) begin
min_o = `BSG_FPU_QUIETNAN(e_p,m_p);
max_o = `BSG_FPU_QUIETNAN(e_p,m_p);
min_max_invalid_o = a_sig_nan | b_sig_nan;
end
else if (a_nan & ~b_nan) begin
min_o = b_i;
max_o = b_i;
min_max_invalid_o = a_sig_nan;
end
else if (~a_nan & b_nan) begin
min_o = a_i;
max_o = a_i;
min_max_invalid_o = b_sig_nan;
end
else begin
min_max_invalid_o = 1'b0;
if (a_zero & b_zero) begin
min_o = `BSG_FPU_ZERO(a_sign | b_sign, e_p, m_p);
max_o = `BSG_FPU_ZERO(a_sign & b_sign, e_p, m_p);
end
else if (lt_o) begin
min_o = a_i;
max_o = b_i;
end
else begin
min_o = b_i;
max_o = a_i;
end
end
end
endmodule
| 7.637011 |
module bsg_fpu_f2i
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
, localparam width_lp=(e_p+m_p+1)
, localparam bias_lp={1'b0, {(e_p-1){1'b1}}}
)
(
input [width_lp-1:0] a_i // input float
, input signed_i
, output logic [width_lp-1:0] z_o // output int
, output logic invalid_o
);
// preprocess
//
logic sign;
logic [e_p-1:0] exp;
logic [m_p-1:0] mantissa;
logic zero;
logic nan;
logic infty;
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) preprocess (
.a_i(a_i)
,.zero_o(zero)
,.nan_o(nan)
,.sig_nan_o()
,.infty_o(infty)
,.exp_zero_o()
,.man_zero_o()
,.denormal_o()
,.sign_o(sign)
,.exp_o(exp)
,.man_o(mantissa)
);
// determine if exp is in range
//
logic exp_too_big;
logic exp_too_small;
assign exp_too_big = signed_i
? (exp > (bias_lp+width_lp-2))
: (exp > (bias_lp+width_lp-1));
//? (exp > 8'd157)
//: (exp > 8'd158);
assign exp_too_small = exp < bias_lp;
// determine shift amount
//
logic [width_lp-1:0] preshift;
logic [e_p-1:0] shamt;
logic [width_lp-1:0] shifted;
assign preshift = signed_i
? {1'b0, 1'b1, mantissa, {(width_lp-2-m_p){1'b0}}}
: {1'b1, mantissa, {(width_lp-1-m_p){1'b0}}};
assign shamt = signed_i
? (e_p)'((bias_lp+width_lp-2) - exp)
: (e_p)'((bias_lp+width_lp-1) - exp);
assign shifted = preshift >> shamt[`BSG_SAFE_CLOG2(width_lp):0];
// invert
//
logic [width_lp-1:0] inverted;
logic [width_lp-1:0] post_round;
assign inverted = {width_lp{signed_i & sign}} ^ {shifted};
assign post_round = inverted + (sign);
always_comb begin
if (nan) begin
z_o = signed_i
? {1'b0, {(width_lp-1){1'b1}}}
: {(width_lp){1'b1}};
invalid_o = 1'b1;
end
else if (infty) begin
// neg_infty
// signed = 32'b80000000
// unsigned = 32'b00000000
// pos_infty
// signed = 32'b7fffffff
// unsigned = 32'bffffffff
z_o = sign
? {signed_i, {(width_lp-1){1'b0}}}
: {~signed_i, {(width_lp-1){1'b1}}};
invalid_o = 1'b1;
end
else if (~signed_i & sign) begin
z_o = '0;
invalid_o = 1'b1;
end
else if (zero) begin
z_o = '0;
invalid_o = 1'b0;
end
else if (exp_too_big) begin
z_o = sign
? {1'b1, {(width_lp-1){1'b0}}}
: {1'b0, {(width_lp-1){1'b1}}};
invalid_o = 1'b1;
end
else if (exp_too_small) begin
z_o = '0;
invalid_o = 1'b0;
end
else begin
z_o = post_round;
invalid_o = 1'b0;
end
end
endmodule
| 7.28622 |
module bsg_fpu_i2f
#(parameter `BSG_INV_PARAM(e_p)
, parameter `BSG_INV_PARAM(m_p)
, localparam width_lp = (e_p+m_p+1)
, localparam bias_lp = {1'b0, {(e_p-1){1'b1}}}
)
(
input clk_i
, input reset_i
, input en_i
, input v_i
, input signed_i
, input [width_lp-1:0] a_i
, output logic ready_o
, output logic v_o
, output logic [width_lp-1:0] z_o
, input yumi_i
);
// pipeline status / control
//
logic v_1_r;
logic stall;
assign v_o = v_1_r;
assign stall = v_1_r & ~yumi_i;
assign ready_o = ~stall & en_i;
// sign bit
//
logic sign;
assign sign = signed_i
? a_i[width_lp-1]
: 1'b0;
// calculate absolute value
logic [width_lp-1:0] abs;
// The following KEEP attribute prevents the following warning in the Xilinx
// toolchain: [Synth 8-3936] Found unconnected internal register
// 'chosen_abs_1_r_reg' and it is trimmed from '32' to '31'
// bits. [<path>/bsg_fpu_i2f.v:98] (Xilinx Vivado 2018.2)
(* keep = "true" *) logic [width_lp-1:0] chosen_abs;
bsg_abs #(
.width_p(width_lp)
) abs0 (
.a_i(a_i)
,.o(abs)
);
assign chosen_abs = signed_i
? abs
: a_i;
// count the number of leading zeros
logic [`BSG_SAFE_CLOG2(width_lp)-1:0] shamt;
logic all_zero;
bsg_fpu_clz #(
.width_p(width_lp)
) clz (
.i(chosen_abs)
,.num_zero_o(shamt)
);
assign all_zero = ~(|chosen_abs);
/////////// first pipeline stage /////////////
// The following KEEP attribute prevents the following warning in the Xilinx
// toolchain: [Synth 8-3936] Found unconnected internal register
// 'chosen_abs_1_r_reg' and it is trimmed from '32' to '31'
// bits. [<path>/bsg_fpu_i2f.v:98] (Xilinx Vivado 2018.2)
(* keep = "true" *) logic [width_lp-1:0] chosen_abs_1_r;
logic [`BSG_SAFE_CLOG2(width_lp)-1:0] shamt_1_r;
logic sign_1_r;
logic all_zero_1_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_1_r <= 1'b0;
end
else begin
if (~stall & en_i) begin
v_1_r <= v_i;
if (v_i) begin
chosen_abs_1_r <= chosen_abs;
shamt_1_r <= shamt;
sign_1_r <= sign;
all_zero_1_r <= all_zero;
end
end
end
end
//////////////////////////////////////////////
// exponent
logic [e_p-1:0] exp;
assign exp = (e_p)'((bias_lp+e_p+m_p) - shamt_1_r);
// shifted
logic [width_lp-1:0] shifted;
assign shifted = chosen_abs_1_r << shamt_1_r;
// sticky bit
logic sticky;
assign sticky = |shifted[width_lp-3-m_p:0];
// round bit
logic round_bit;
assign round_bit = shifted[width_lp-2-m_p];
// mantissa
logic [m_p-1:0] mantissa;
assign mantissa = shifted[width_lp-2:width_lp-1-m_p];
// round up condition
logic round_up;
assign round_up = round_bit & (mantissa[0] | sticky);
// round up
logic [width_lp-2:0] rounded;
assign rounded = {exp, mantissa} + round_up;
// final result
assign z_o = all_zero_1_r
? {width_lp{1'b0}}
: {sign_1_r, rounded};
endmodule
| 9.058685 |
module bsg_fpu_preprocess
#(parameter `BSG_INV_PARAM(e_p )
, parameter `BSG_INV_PARAM(m_p )
)
(
input [e_p+m_p:0] a_i
, output logic zero_o
, output logic nan_o
, output logic sig_nan_o
, output logic infty_o
, output logic exp_zero_o
, output logic man_zero_o
, output logic denormal_o
, output logic sign_o
, output logic [e_p-1:0] exp_o
, output logic [m_p-1:0] man_o
);
assign man_o = a_i[m_p-1:0];
assign exp_o = a_i[m_p+:e_p];
assign sign_o = a_i[e_p+m_p];
logic mantissa_zero;
logic exp_zero;
logic exp_ones;
assign mantissa_zero = (man_o == {m_p{1'b0}});
assign exp_zero = (exp_o == {e_p{1'b0}});
assign exp_ones = (exp_o == {e_p{1'b1}});
// outputs
assign zero_o = exp_zero & mantissa_zero;
assign nan_o = exp_ones & ~mantissa_zero;
assign sig_nan_o = nan_o & ~man_o[m_p-1];
assign infty_o = exp_ones & mantissa_zero;
assign exp_zero_o = exp_zero;
assign man_zero_o = mantissa_zero;
assign denormal_o = exp_zero & ~mantissa_zero;
endmodule
| 7.572097 |
module bsg_fpu_sticky
#(parameter `BSG_INV_PARAM(width_p))
(
input [width_p-1:0] i // input
, input [`BSG_WIDTH(width_p)-1:0] shamt_i // shift amount
, output logic sticky_o
);
logic [width_p-1:0] scan_out;
bsg_scan #(
.width_p(width_p)
,.or_p(1)
,.lo_to_hi_p(1)
) scan0 (
.i(i)
,.o(scan_out)
);
// answer
logic [width_p:0] answer;
assign answer = {scan_out, 1'b0};
// final output
assign sticky_o = shamt_i > width_p
? answer[width_p]
: answer[shamt_i];
endmodule
| 6.504975 |
module bsg_front_side_bus_hop_in
#(parameter `BSG_INV_PARAM( width_p)
, parameter fan_out_p=2
)
(input clk_i
, input reset_i
// from previous hop
, output ready_o
, input v_i
, input [width_p-1:0] data_i
// 0 is to the next hop
// 1 is to the local switch
, output [fan_out_p-1:0] v_o
, output [fan_out_p-1:0] [width_p-1:0] data_o
, input [fan_out_p-1:0] ready_i
);
logic [fan_out_p-1:0] sent_r, sent_n;
genvar i;
logic [fan_out_p-1:0] v_o_tmp;
logic [width_p-1:0] data_o_tmp;
wire fifo_v, fifo_yumi;
bsg_two_fifo #(.width_p(width_p)) fifo
(.clk_i (clk_i)
,.reset_i (reset_i)
,.data_i (data_i)
,.data_o (data_o_tmp)
,.v_o (fifo_v)
,.yumi_i (fifo_yumi)
,.ready_o (ready_o)
,.v_i (v_i)
);
for (i = 0; i < fan_out_p; i = i+1)
begin
assign data_o[i] = data_o_tmp;
assign v_o [i] = v_o_tmp[i];
// we have data and we haven't sent it
assign v_o_tmp[i] = fifo_v & ~sent_r[i];
always_ff @(posedge clk_i)
if (reset_i)
sent_r[i] <= 1'b0;
else
sent_r[i] <= sent_n[i] & ~fifo_yumi;
always_comb
begin
sent_n[i] = sent_r[i];
// if we have data,
if (v_o_tmp[i] & ready_i[i])
sent_n[i] = 1'b1;
end // always_comb
end
assign fifo_yumi = & sent_n;
endmodule
| 9.484205 |
module bsg_front_side_bus_hop_in_no_fc #(parameter `BSG_INV_PARAM(width_p))
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
// 0 is to the next switch
// 1 is to the local switch
, output [1:0][width_p-1:0] data_o
, output [1:0] v_o
, input local_accept_i
);
logic [width_p-1:0] data_r;
logic v_r;
// fixme: trade logic/speed for power
// and avoid fake transitions
assign data_o[0] = data_r;
assign v_o[0] = v_r;
// to local node
assign data_o[1] = data_r;
assign v_o[1] = v_r & local_accept_i;
bsg_dff_reset #( .width_p($bits(v_r)) )
v_reg
( .clk_i ( clk_i )
, .reset_i( reset_i )
, .data_i ( v_i )
, .data_o ( v_r )
);
bsg_dff #( .width_p($bits(data_r)) )
data_reg
( .clk_i ( clk_i )
, .data_i( data_i )
, .data_o( data_r )
);
endmodule
| 9.484205 |
module bsg_front_side_bus_hop_out #(parameter `BSG_INV_PARAM(width_p))
(input clk_i
, input reset_i
// 0 = previous switch
// 1 = local node
, input [1:0] v_i // late
, input [1:0][width_p-1:0] data_i // late
, output ready_o // to prev switch; early
, output yumi_o // to local node; late
// to next switch
, output v_o // early
, output [width_p-1:0] data_o
, input ready_i // late
);
wire fifo_v;
wire fifo_ready;
logic v1_blocked_r;
// we select the local port if the remote node is not
// sending; or if local port was blocked last cycle
wire source_sel = ~v_i[0] | v1_blocked_r;
// local send
wire yumi_o_tmp = (fifo_ready & v_i[1]) & source_sel;
assign yumi_o = yumi_o_tmp;
// update "local blocked" signal
// only when the fifo is ready
//
always_ff @(posedge clk_i)
v1_blocked_r <= reset_i
? 1'b0
: (fifo_ready
? (v_i[1] & ~source_sel)
: v1_blocked_r
);
bsg_two_fifo #(.width_p(width_p)) fifo
(.clk_i (clk_i)
,.reset_i (reset_i)
,.data_i (data_i[source_sel])
,.data_o (data_o)
,.v_o (fifo_v)
,.yumi_i (fifo_v & ready_i)
,.ready_o (fifo_ready)
,.v_i (| v_i)
);
assign v_o = fifo_v;
// tell remote note we are ready if there is
// fifo space, and we are not creating a slot
// for the local node
assign ready_o = fifo_ready & ~v1_blocked_r;
endmodule
| 9.484205 |
module bsg_fsb_murn_gateway
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter `BSG_INV_PARAM(id_width_p)
// resets with core reset
// rather than by a command.
, parameter enabled_at_start_p=0
// once the node is enabled
// look at all packets;
// useful if we would like to
// test and ignore packet formats
, parameter snoop_p=0
)
(input clk_i
// from/to switch
, input reset_i
, input v_i
, input [width_p-1:0] data_i
, output ready_o // note this inspects v_i, so technically is v_i->ready_o
// but the underlying bsg_test_node is true v_i / ready_o
// from node
, output v_o
, input ready_i
, output node_en_r_o
, output node_reset_r_o
);
`declare_bsg_fsb_pkt_s(width_p, id_width_p)
// if we are in snoop mode and don't need a wakeup
// packet, we keep it simple and avoid having
// a dependency on the packet format.
if (snoop_p & enabled_at_start_p)
begin
assign v_o = v_i;
assign ready_o = ready_i;
assign node_reset_r_o = reset_i;
assign node_en_r_o = 1'b1;
wire stop_lint_unused_warning = clk_i | (|data_i);
end
else
begin
logic node_en_r , node_en_n;
logic node_reset_r, node_reset_n;
assign node_en_r_o = node_en_r;
assign node_reset_r_o = node_reset_r;
bsg_fsb_pkt_s data_RPT;
assign data_RPT = bsg_fsb_pkt_s ' (data_i);
wire id_match = data_RPT.destid == id_p;
wire for_this_node = v_i & (id_match | snoop_p) ;
// once this switch is enabled, then switch packets are ignored in snoop mode
wire for_switch = ~(snoop_p & node_en_r) & v_i & (id_match) & (data_RPT.cmd == 1'b1);
// filter out traffic for switch
assign v_o = node_en_r & for_this_node & ~for_switch;
// we will sink packets:
// - if the node is not enabled
// - if the message is valid and node is actually ready for the packet
// - or if the message is not for us
assign ready_o = v_i // guard against X propagation
& (~node_en_r // node is sleeping
| ready_i // node actually is ready
| for_switch // message is for a switch
| ~for_this_node // message is for another node
);
// on "real" reset initialize node_en to 1, otherwise 0.
always_ff @(posedge clk_i)
node_en_r <= reset_i ? (enabled_at_start_p != 0) : node_en_n;
// if we are master, the reset is fed straight through
if (enabled_at_start_p)
always_ff @(posedge clk_i)
node_reset_r <= reset_i;
else
begin
// we start with reset set to high on the node
// so that it clears its stuff out
always_ff @(posedge clk_i)
if (reset_i)
node_reset_r <= 1'b1;
else
node_reset_r <= node_reset_n;
end
always_comb
begin
node_en_n = node_en_r;
node_reset_n = node_reset_r;
if (for_switch)
unique case(data_RPT.opcode)
RNENABLE_CMD: node_en_n = 1'b1;
RNDISABLE_CMD: node_en_n = 1'b0;
RNRESET_ENABLE_CMD: node_reset_n = 1'b1;
RNRESET_DISABLE_CMD: node_reset_n = 1'b0;
default:
begin
end
endcase // unique case (data_RPT.opcode)
end // always_comb
end // else: !if(snoop_p & enabled_at_start_p)
endmodule
| 8.529928 |
module bsg_fsb_murn_gateway
import bsg_fsb_pkg::*;
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(id_p)
// resets with core reset
// rather than by a command.
, parameter enabled_at_start_p=0
// once the node is enabled
// look at all packets;
// useful if we would like to
// test and ignore packet formats
, parameter snoop_p=0
)
(input clk_i
// from/to switch
, input reset_i
, input v_i
, input [width_p-1:0] data_i
, output ready_o // note this inspects v_i, so technically is v_i->ready_o
// but the underlying bsg_test_node is true v_i / ready_o
// from node
, output v_o
, input ready_i
, output node_en_r_o
, output node_reset_r_o
);
// if we are in snoop mode and don't need a wakeup
// packet, we keep it simple and avoid having
// a dependency on the packet format.
if (snoop_p & enabled_at_start_p)
begin
assign v_o = v_i;
assign ready_o = ready_i;
assign node_reset_r_o = reset_i;
assign node_en_r_o = 1'b1;
wire stop_lint_unused_warning = clk_i | (|data_i);
end
else
begin
logic node_en_r , node_en_n;
logic node_reset_r, node_reset_n;
assign node_en_r_o = node_en_r;
assign node_reset_r_o = node_reset_r;
bsg_fsb_pkt_s data_RPT;
assign data_RPT = bsg_fsb_pkt_s ' (data_i);
wire id_match = data_RPT.destid == id_p;
wire for_this_node = v_i & (id_match | snoop_p) ;
// once this switch is enabled, then switch packets are ignored in snoop mode
wire for_switch = ~(snoop_p & node_en_r) & v_i & (id_match) & (data_RPT.cmd == 1'b1);
// filter out traffic for switch
assign v_o = node_en_r & for_this_node & ~for_switch;
// we will sink packets:
// - if the node is not enabled
// - if the message is valid and node is actually ready for the packet
// - or if the message is not for us
assign ready_o = v_i // guard against X propagation
& (~node_en_r // node is sleeping
| ready_i // node actually is ready
| for_switch // message is for a switch
| ~for_this_node // message is for another node
);
// on "real" reset initialize node_en to 1, otherwise 0.
always_ff @(posedge clk_i)
node_en_r <= reset_i ? (enabled_at_start_p != 0) : node_en_n;
// if we are master, the reset is fed straight through
if (enabled_at_start_p)
always_ff @(posedge clk_i)
node_reset_r <= reset_i;
else
begin
// we start with reset set to high on the node
// so that it clears its stuff out
always_ff @(posedge clk_i)
if (reset_i)
node_reset_r <= 1'b1;
else
node_reset_r <= node_reset_n;
end
always_comb
begin
node_en_n = node_en_r;
node_reset_n = node_reset_r;
if (for_switch)
unique case(data_RPT.opcode)
RNENABLE_CMD: node_en_n = 1'b1;
RNDISABLE_CMD: node_en_n = 1'b0;
RNRESET_ENABLE_CMD: node_reset_n = 1'b1;
RNRESET_DISABLE_CMD: node_reset_n = 1'b0;
default:
begin
end
endcase // unique case (data_RPT.opcode)
end // always_comb
end // else: !if(snoop_p & enabled_at_start_p)
endmodule
| 8.529928 |
module converts the bsg_fsb node signals between different
//clock domains.
//
//default: FSB on Right,
// NODE on Left
`include "bsg_defines.v"
`ifndef FSB_LEGACY
module bsg_fsb_node_async_buffer
#( parameter `BSG_INV_PARAM(ring_width_p)
,parameter fifo_els_p = 2
)
(
/////////////////////////////////////////////
// signals on the node side
input L_clk_i
, input L_reset_i
// control
, output L_en_o // FIXME unused
// input channel
, output L_v_o
, output [ring_width_p-1:0] L_data_o
, input L_ready_i
// output channel
, input L_v_i
, input [ring_width_p-1:0] L_data_i
, output L_yumi_o // late
/////////////////////////////////////////////
// signals on the FSB side
, input R_clk_i
, input R_reset_i
// control
, input R_en_i // FIXME unused
// input channel
, input R_v_i
, input [ring_width_p-1:0] R_data_i
, output R_ready_o
// output channel
, output R_v_o
, output [ring_width_p-1:0] R_data_o
, input R_yumi_i // late
);
localparam fifo_lg_size_lp = `BSG_SAFE_CLOG2( fifo_els_p );
////////////////////////////////////////////////////////////////////////////////////////
// Covert FSB to NODE packet signals
// FSB == w
// NODE == r
wire R_w_full_lo ;
assign R_ready_o = ~R_w_full_lo ;
bsg_async_fifo #(.lg_size_p ( fifo_lg_size_lp )
,.width_p ( ring_width_p )
)r2l_fifo
(
.w_clk_i ( R_clk_i )
,.w_reset_i ( R_reset_i )
// not legal to w_enq_i if w_full_o is not low.
,.w_enq_i ( (~R_w_full_lo) & R_v_i )
,.w_data_i ( R_data_i )
,.w_full_o ( R_w_full_lo )
// not legal to r_deq_i if r_valid_o is not high.
,.r_clk_i ( L_clk_i )
,.r_reset_i ( L_reset_i )
,.r_deq_i ( L_v_o & L_ready_i )
,.r_data_o ( L_data_o )
,.r_valid_o ( L_v_o )
);
////////////////////////////////////////////////////////////////////////////////////////
// Covert NODE to FSB packet signals
// FSB == r
// NODE == w
wire L_w_full_lo ;
assign L_yumi_o = (~L_w_full_lo) & L_v_i ;
bsg_async_fifo #(.lg_size_p ( fifo_lg_size_lp )
,.width_p ( ring_width_p )
)l2r_fifo
(
.w_clk_i ( L_clk_i )
,.w_reset_i ( L_reset_i )
// not legal to w_enq_i if w_full_o is not low.
,.w_enq_i ( L_yumi_o )
,.w_data_i ( L_data_i )
,.w_full_o ( L_w_full_lo)
// not legal to r_deq_i if r_valid_o is not high.
,.r_clk_i ( R_clk_i )
,.r_reset_i ( R_reset_i )
,.r_deq_i ( R_yumi_i )
,.r_data_o ( R_data_o )
,.r_valid_o ( R_v_o )
);
bsg_sync_sync #(.width_p(1)) fsb_en_sync
(
.oclk_i ( L_clk_i ) //TODO
, .iclk_data_i ( R_en_i )
, .oclk_data_o ( L_en_o )
);
endmodule
| 6.747013 |
module bsg_fsb_node_async_buffer
import bsg_fsb_pkg::*;
#( parameter `BSG_INV_PARAM(ring_width_p)
,parameter fifo_els_p = 2
)
(
/////////////////////////////////////////////
// signals on the node side
input L_clk_i
, input L_reset_i
// control
, output L_en_o // FIXME unused
// input channel
, output L_v_o
, output [ring_width_p-1:0] L_data_o
, input L_ready_i
// output channel
, input L_v_i
, input [ring_width_p-1:0] L_data_i
, output L_yumi_o // late
/////////////////////////////////////////////
// signals on the FSB side
, input R_clk_i
, input R_reset_i
// control
, input R_en_i // FIXME unused
// input channel
, input R_v_i
, input [ring_width_p-1:0] R_data_i
, output R_ready_o
// output channel
, output R_v_o
, output [ring_width_p-1:0] R_data_o
, input R_yumi_i // late
);
localparam fifo_lg_size_lp = `BSG_SAFE_CLOG2( fifo_els_p );
////////////////////////////////////////////////////////////////////////////////////////
// Covert FSB to NODE packet signals
// FSB == w
// NODE == r
wire R_w_full_lo ;
assign R_ready_o = ~R_w_full_lo ;
bsg_async_fifo #(.lg_size_p ( fifo_lg_size_lp )
,.width_p ( ring_width_p )
)r2l_fifo
(
.w_clk_i ( R_clk_i )
,.w_reset_i ( R_reset_i )
// not legal to w_enq_i if w_full_o is not low.
,.w_enq_i ( (~R_w_full_lo) & R_v_i )
,.w_data_i ( R_data_i )
,.w_full_o ( R_w_full_lo )
// not legal to r_deq_i if r_valid_o is not high.
,.r_clk_i ( L_clk_i )
,.r_reset_i ( L_reset_i )
,.r_deq_i ( L_v_o & L_ready_i )
,.r_data_o ( L_data_o )
,.r_valid_o ( L_v_o )
);
////////////////////////////////////////////////////////////////////////////////////////
// Covert NODE to FSB packet signals
// FSB == r
// NODE == w
wire L_w_full_lo ;
assign L_yumi_o = (~L_w_full_lo) & L_v_i ;
bsg_async_fifo #(.lg_size_p ( fifo_lg_size_lp )
,.width_p ( ring_width_p )
)l2r_fifo
(
.w_clk_i ( L_clk_i )
,.w_reset_i ( L_reset_i )
// not legal to w_enq_i if w_full_o is not low.
,.w_enq_i ( L_yumi_o )
,.w_data_i ( L_data_i )
,.w_full_o ( L_w_full_lo)
// not legal to r_deq_i if r_valid_o is not high.
,.r_clk_i ( R_clk_i )
,.r_reset_i ( R_reset_i )
,.r_deq_i ( R_yumi_i )
,.r_data_o ( R_data_o )
,.r_valid_o ( R_v_o )
);
bsg_sync_sync #(.width_p(1)) fsb_en_sync
(
.oclk_i ( L_clk_i ) //TODO
, .iclk_data_i ( R_en_i )
, .oclk_data_o ( L_en_o )
);
endmodule
| 8.176575 |
module is design to level shift all signals that connect the FSB to a
// node. This allows FSB nodes to exist in different power domains than the FSB.
// There are 2 types of level shifters:
//
// 1) Source - level shifting cell must be in the same power domain as the
// signal's source
// 2) Sink - level shifting cell must be in the same power doamin as the
// signal's destination
//
// This is 1 of 4 modules that shift all the signals between the FSB and
// a node. Each of the modules has a different strategy about which power
// domain the level-shifters should be in:
//
// 1) bsg_fsb_node_level_shift_all_sink
// -- All level shifters in same power domain as the input pin
// 2) bsg_fsb_node_level_shift_all_source
// -- All level shifters in same power domain as the output pin
// * 3) bsg_fsb_node_level_shift_fsb_domain
// -- All level shifters in same power domain as the fsb module
// 4) bsg_fsb_node_level_shift_node_domain
// -- All level shifters in same power domain as the node module
//
`include "bsg_defines.v"
module bsg_fsb_node_level_shift_fsb_domain #(parameter `BSG_INV_PARAM(ring_width_p ))
(
input en_ls_i,
input clk_i,
input reset_i,
output clk_o,
output reset_o,
//----- ATTACHED TO FSB -----//
output fsb_v_i_o,
output [ring_width_p-1:0] fsb_data_i_o,
input fsb_yumi_o_i,
input fsb_v_o_i,
input [ring_width_p-1:0] fsb_data_o_i,
output fsb_ready_i_o,
//----- ATTACHED TO NODE -----//
output node_v_i_o,
output [ring_width_p-1:0] node_data_i_o,
input node_ready_o_i,
input node_v_o_i,
input [ring_width_p-1:0] node_data_o_i,
output node_yumi_i_o
);
// Level Shift Clock
bsg_level_shift_up_down_source #(.width_p(1)) clk_ls_inst
(
.v0_en_i(1'b1),
.v0_data_i(clk_i),
.v1_data_o(clk_o)
);
// Level Shift Reset
bsg_level_shift_up_down_source #(.width_p(1)) reset_ls_inst
(
.v0_en_i(1'b1),
.v0_data_i(reset_i),
.v1_data_o(reset_o)
);
// NODE v_o --> FSB v_i
bsg_level_shift_up_down_sink #(.width_p(1)) n2f_v_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(node_v_o_i),
.v1_data_o(fsb_v_i_o)
);
// NODE data_o --> FSB data_i
bsg_level_shift_up_down_sink #(.width_p(ring_width_p)) n2f_data_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(node_data_o_i),
.v1_data_o(fsb_data_i_o)
);
// FSB yumi_o --> NODE yumi_i
bsg_level_shift_up_down_source #(.width_p(1)) f2n_yumi_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(fsb_yumi_o_i),
.v1_data_o(node_yumi_i_o)
);
// FSB v_o --> NODE v_i
bsg_level_shift_up_down_source #(.width_p(1)) f2n_v_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(fsb_v_o_i),
.v1_data_o(node_v_i_o)
);
// FSB data_o --> NODE data_i
bsg_level_shift_up_down_source #(.width_p(ring_width_p)) f2n_data_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(fsb_data_o_i),
.v1_data_o(node_data_i_o)
);
// NODE ready_o --> FSB ready_i
bsg_level_shift_up_down_sink #(.width_p(1)) n2f_ready_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(node_ready_o_i),
.v1_data_o(fsb_ready_i_o)
);
endmodule
| 10.624995 |
module is design to level shift all signals that connect the FSB to a
// node. This allows FSB nodes to exist in different power domains than the FSB.
// There are 2 types of level shifters:
//
// 1) Source - level shifting cell must be in the same power domain as the
// signal's source
// 2) Sink - level shifting cell must be in the same power doamin as the
// signal's destination
//
// This is 1 of 4 modules that shift all the signals between the FSB and
// a node. Each of the modules has a different strategy about which power
// domain the level-shifters should be in:
//
// 1) bsg_fsb_node_level_shift_all_sink
// -- All level shifters in same power domain as the input pin
// 2) bsg_fsb_node_level_shift_all_source
// -- All level shifters in same power domain as the output pin
// 3) bsg_fsb_node_level_shift_fsb_domain
// -- All level shifters in same power domain as the fsb module
// * 4) bsg_fsb_node_level_shift_node_domain
// -- All level shifters in same power domain as the node module
//
`include "bsg_defines.v"
module bsg_fsb_node_level_shift_node_domain #(parameter `BSG_INV_PARAM(ring_width_p ))
(
input en_ls_i,
input clk_i,
input reset_i,
output clk_o,
output reset_o,
//----- ATTACHED TO FSB -----//
output fsb_v_i_o,
output [ring_width_p-1:0] fsb_data_i_o,
input fsb_yumi_o_i,
input fsb_v_o_i,
input [ring_width_p-1:0] fsb_data_o_i,
output fsb_ready_i_o,
//----- ATTACHED TO NODE -----//
output node_v_i_o,
output [ring_width_p-1:0] node_data_i_o,
input node_ready_o_i,
input node_v_o_i,
input [ring_width_p-1:0] node_data_o_i,
output node_yumi_i_o
);
// Level Shift Clock
bsg_level_shift_up_down_sink #(.width_p(1)) clk_ls_inst
(
.v1_en_i(1'b1),
.v0_data_i(clk_i),
.v1_data_o(clk_o)
);
// Level Shift Reset
bsg_level_shift_up_down_sink #(.width_p(1)) reset_ls_inst
(
.v1_en_i(1'b1),
.v0_data_i(reset_i),
.v1_data_o(reset_o)
);
// NODE v_o --> FSB v_i
bsg_level_shift_up_down_source #(.width_p(1)) n2f_v_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(node_v_o_i),
.v1_data_o(fsb_v_i_o)
);
// NODE data_o --> FSB data_i
bsg_level_shift_up_down_source #(.width_p(ring_width_p)) n2f_data_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(node_data_o_i),
.v1_data_o(fsb_data_i_o)
);
// FSB yumi_o --> NODE yumi_i
bsg_level_shift_up_down_sink #(.width_p(1)) f2n_yumi_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(fsb_yumi_o_i),
.v1_data_o(node_yumi_i_o)
);
// FSB v_o --> NODE v_i
bsg_level_shift_up_down_sink #(.width_p(1)) f2n_v_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(fsb_v_o_i),
.v1_data_o(node_v_i_o)
);
// FSB data_o --> NODE data_i
bsg_level_shift_up_down_sink #(.width_p(ring_width_p)) f2n_data_ls_inst
(
.v1_en_i(en_ls_i),
.v0_data_i(fsb_data_o_i),
.v1_data_o(node_data_i_o)
);
// NODE ready_o --> FSB ready_i
bsg_level_shift_up_down_source #(.width_p(1)) n2f_ready_ls_inst
(
.v0_en_i(en_ls_i),
.v0_data_i(node_ready_o_i),
.v1_data_o(fsb_ready_i_o)
);
endmodule
| 10.624995 |
module bsg_fsb_to_htif_connector
import bsg_fsb_pkg::RingPacketType;
#(parameter htif_width_p
,parameter fsb_width_p=$size(RingPacketType)
,parameter `BSG_INV_PARAM(destid_p)
)
(input clk_i
,input reset_i
,input fsb_v_i
,input [fsb_width_p-1:0] fsb_data_i
,output fsb_ready_o
,output fsb_v_o
,output [fsb_width_p-1:0] fsb_data_o
,input fsb_yumi_i
// FROM htif
,input htif_v_i
,input [htif_width_p-1:0] htif_data_i
,output htif_ready_o
// TO htif
,output htif_v_o
,output [htif_width_p-1:0] htif_data_o
,input htif_ready_i
);
RingPacketType pkt_in = fsb_data_i;
RingPacketType pkt_out;
assign fsb_data_o = pkt_out;
assign htif_v_o = fsb_v_i;
// toss the rest
assign htif_data_o = pkt_in.data[htif_width_p-1:0];
assign fsb_ready_o = htif_ready_i;
bsg_two_fifo #(.width_p(htif_width_lp)
)
(.clk_i (clk_i )
,.reset_i (reset_i)
,.v_i ( htif_v_i )
,.data_i ( htif_data_i )
,.ready_o ( htif_ready_o )
,.v_o ( fsb_v_o )
,.data_o ( pkt_out.data[htif_width_p-1:0] )
,.yumi_i ( fsb_yumi_i )
);
assign pkt_out.srcid = 4'b0; // fixme
assign pkt_out.destid = destid_p;
assign pkt_out.cmd = 1'b0;
assign pkt_out.opcode = 7'b0;
assign pkt_out.data[63:htif_width_p] = '0;
endmodule
| 7.002691 |
module bsg_gateway_fmc_rx (
input reset_i
, output clk_div_o
, output [87:0] data_o
, output cal_done_o
// fmc rx clk in
, input F17_P,
F17_N
// fmc rx data in
, input F31_P,
F31_N
, input F33_P,
F33_N
, input F30_P,
F30_N
, input F32_P,
F32_N
, input F28_P,
F28_N
, input F25_P,
F25_N
, input F29_P,
F29_N
, input F26_P,
F26_N
, input F21_P,
F21_N
, input F27_P,
F27_N
, input F22_P,
F22_N
);
// fmc rx clk in
logic clk_p_lo, clk_n_lo;
logic clk_div_lo, clk_serdes_strobe_lo;
bsg_gateway_fmc_rx_clk rx_clk (
.clk_p_i(F17_P),
.clk_n_i(F17_N)
, .clk_p_o(clk_p_lo),
.clk_n_o(clk_n_lo)
, .clk_serdes_strobe_o(clk_serdes_strobe_lo)
, .clk_div_o(clk_div_lo)
);
assign clk_div_o = clk_div_lo;
// fmc rx data in
logic [10:0] data_p_lo, data_n_lo;
assign data_p_lo = {F22_P, F27_P, F21_P, F26_P, F29_P, F25_P, F28_P, F32_P, F30_P, F33_P, F31_P};
assign data_n_lo = {F22_N, F27_N, F21_N, F26_N, F29_N, F25_N, F28_N, F32_N, F30_N, F33_N, F31_N};
bsg_gateway_fmc_rx_data rx_data (
.reset_i(reset_i)
, .clk_p_i(clk_p_lo),
.clk_n_i(clk_n_lo)
, .clk_div_i(clk_div_lo)
, .clk_serdes_strobe_i(clk_serdes_strobe_lo)
, .data_p_i(data_p_lo),
.data_n_i(data_n_lo)
, .cal_done_o(cal_done_o)
, .data_o(data_o)
);
endmodule
| 6.571748 |
module bsg_gateway_fmc_rx_clk (
input clk_p_i,
clk_n_i
, output clk_p_o,
clk_n_o
, output clk_serdes_strobe_o
, output clk_div_o
);
logic iodelay_clk_p_lo, iodelay_clk_n_lo;
logic ibufds_clk_p_lo, ibufds_clk_n_lo;
logic bufio_clk_div_lo;
IBUFDS_DIFF_OUT #(
.DIFF_TERM("TRUE")
) ibufds_clk (
.I (clk_p_i),
.IB(clk_n_i)
, .O (ibufds_clk_p_lo),
.OB(ibufds_clk_n_lo)
);
IODELAY2 #(
.DATA_RATE("DDR")
, .SIM_TAPDELAY_VALUE(49)
, .IDELAY_VALUE(0)
, .IDELAY2_VALUE(0)
, .ODELAY_VALUE(0)
, .IDELAY_MODE("NORMAL")
, .SERDES_MODE("MASTER")
, .IDELAY_TYPE("FIXED")
, .COUNTER_WRAPAROUND("STAY_AT_LIMIT")
, .DELAY_SRC("IDATAIN")
) iodelay_clk_p (
.IDATAIN(ibufds_clk_p_lo)
, .TOUT()
, .DOUT()
, .T(1'b1)
, .ODATAIN(1'b0)
, .DATAOUT(iodelay_clk_p_lo)
, .DATAOUT2()
, .IOCLK0(1'b0)
, .IOCLK1(1'b0)
, .CLK(1'b0)
, .CAL(1'b0)
, .INC(1'b0)
, .CE(1'b0)
, .RST(1'b0)
, .BUSY()
);
IODELAY2 #(
.DATA_RATE("DDR")
, .SIM_TAPDELAY_VALUE(49)
, .IDELAY_VALUE(0)
, .IDELAY2_VALUE(0)
, .ODELAY_VALUE(0)
, .IDELAY_MODE("NORMAL")
, .SERDES_MODE("SLAVE")
, .IDELAY_TYPE("FIXED")
, .COUNTER_WRAPAROUND("STAY_AT_LIMIT")
, .DELAY_SRC("IDATAIN")
) iodelay_clk_n (
.IDATAIN(ibufds_clk_n_lo)
, .TOUT()
, .DOUT()
, .T(1'b1)
, .ODATAIN(1'b0)
, .DATAOUT(iodelay_clk_n_lo)
, .DATAOUT2()
, .IOCLK0(1'b0)
, .IOCLK1(1'b0)
, .CLK(1'b0)
, .CAL(1'b0)
, .INC(1'b0)
, .CE(1'b0)
, .RST(1'b0)
, .BUSY()
);
BUFIO2_2CLK #(
.DIVIDE(8)
) bufio2_2clk (
.I(iodelay_clk_p_lo),
.IB(iodelay_clk_n_lo)
, .IOCLK(clk_p_o)
, .DIVCLK(bufio_clk_div_lo)
, .SERDESSTROBE(clk_serdes_strobe_o)
);
BUFIO2 #(
.I_INVERT("FALSE")
, .DIVIDE_BYPASS("FALSE")
, .USE_DOUBLER("FALSE")
) bufio2 (
.I(iodelay_clk_n_lo)
, .IOCLK(clk_n_o)
, .DIVCLK()
, .SERDESSTROBE()
);
BUFG bufg (
.I(bufio_clk_div_lo)
, .O(clk_div_o)
);
endmodule
| 6.571748 |
module bsg_gateway_fmc_rx_data (
input reset_i
, input clk_p_i,
clk_n_i
, input [10:0] data_p_i,
data_n_i
, input clk_div_i
, input clk_serdes_strobe_i
, output cal_done_o
, output [87:0] data_o
);
logic [87:0] iserdes_data_lo;
logic [10:0] ibufds_data_lo, iodelay_data_lo;
logic [10:0] iserdes_slave_shiftout_lo, iserdes_master_shiftout_lo;
logic [10:0] ctrl_bitslip_lo, ctrl_bitslip_done_lo;
genvar i;
generate
for (i = 0; i < 11; i++) begin
IBUFDS #(
.DIFF_TERM("TRUE")
) ibufds (
.I (data_p_i[i]),
.IB(data_n_i[i])
, .O (ibufds_data_lo[i])
);
IODELAY2 #(
.DATA_RATE("DDR")
, .IDELAY_VALUE(0)
, .IDELAY2_VALUE(0)
, .IDELAY_MODE("NORMAL")
, .ODELAY_VALUE(0)
, .IDELAY_TYPE("FIXED")
, .COUNTER_WRAPAROUND("WRAPAROUND")
, .DELAY_SRC("IDATAIN")
, .SERDES_MODE("MASTER")
, .SIM_TAPDELAY_VALUE(49)
) iodelay_data (
.IDATAIN(ibufds_data_lo[i])
, .TOUT()
, .DOUT()
, .T(1'b1)
, .ODATAIN(1'b0)
, .DATAOUT(iodelay_data_lo[i])
, .DATAOUT2()
, .IOCLK0(clk_p_i)
, .IOCLK1(clk_n_i)
, .CLK(clk_div_i)
, .CAL(1'b0)
, .INC(1'b0)
, .CE(1'b0)
, .RST(reset_i)
, .BUSY()
);
ISERDES2 #(
.DATA_WIDTH(8)
, .DATA_RATE("DDR")
, .BITSLIP_ENABLE("TRUE")
, .SERDES_MODE("MASTER")
, .INTERFACE_TYPE("RETIMED")
) iserdes_master (
.D(iodelay_data_lo[i])
, .CE0(1'b1)
, .CLK0(clk_p_i)
, .CLK1(clk_n_i)
, .IOCE(clk_serdes_strobe_i)
, .RST(reset_i)
, .CLKDIV(clk_div_i)
, .SHIFTIN(iserdes_slave_shiftout_lo[i])
, .BITSLIP(ctrl_bitslip_lo[i])
, .FABRICOUT()
, .Q4(iserdes_data_lo[(8*i)+7])
, .Q3(iserdes_data_lo[(8*i)+6])
, .Q2(iserdes_data_lo[(8*i)+5])
, .Q1(iserdes_data_lo[(8*i)+4])
, .DFB()
, .CFB0()
, .CFB1()
, .VALID()
, .INCDEC()
, .SHIFTOUT(iserdes_master_shiftout_lo[i])
);
ISERDES2 #(
.DATA_WIDTH(8)
, .DATA_RATE("DDR")
, .BITSLIP_ENABLE("TRUE")
, .SERDES_MODE("SLAVE")
, .INTERFACE_TYPE("RETIMED")
) iserdes_slave (
.D()
, .CE0(1'b1)
, .CLK0(clk_p_i)
, .CLK1(clk_n_i)
, .IOCE(clk_serdes_strobe_i)
, .RST(reset_i)
, .CLKDIV(clk_div_i)
, .SHIFTIN(iserdes_master_shiftout_lo[i])
, .BITSLIP(ctrl_bitslip_lo[i])
, .FABRICOUT()
, .Q4(iserdes_data_lo[(8*i)+3])
, .Q3(iserdes_data_lo[(8*i)+2])
, .Q2(iserdes_data_lo[(8*i)+1])
, .Q1(iserdes_data_lo[(8*i)+0])
, .DFB()
, .CFB0()
, .CFB1()
, .VALID()
, .INCDEC()
, .SHIFTOUT(iserdes_slave_shiftout_lo[i])
);
bsg_gateway_fmc_rx_data_bitslip_ctrl bitslip_ctrl (
.clk_i(clk_div_i)
, .reset_i(reset_i)
, .data_i(iserdes_data_lo[8*i+7 : 8*i])
, .bitslip_o(ctrl_bitslip_lo[i])
, .done_o(ctrl_bitslip_done_lo[i])
);
end
endgenerate
logic bitslip_done_lo, cal_done_r;
assign bitslip_done_lo = (&ctrl_bitslip_done_lo);
always_ff @(posedge clk_div_i)
if (reset_i == 1'b1) cal_done_r <= 1'b0;
else if (bitslip_done_lo == 1'b1 && iserdes_data_lo == {11{8'hF8}}) cal_done_r <= 1'b1;
assign cal_done_o = cal_done_r;
assign data_o = (cal_done_r == 1'b1) ? iserdes_data_lo : {11{8'd0}};
endmodule
| 6.571748 |
module bsg_gateway_fmc_rx_data_bitslip_ctrl (
input clk_i
, input reset_i
, input [7:0] data_i
, output bitslip_o
, output done_o
);
logic [7:0] data_pattern;
assign data_pattern = 8'h2C;
enum logic [2:0] {
IDLE = 3'b001
,BITSLIP = 3'b010
,DONE = 3'b100
}
c_state, n_state;
logic [1:0] cnt_r;
always_ff @(posedge clk_i)
if (reset_i == 1'b1 || c_state == BITSLIP) cnt_r <= 4'd0;
else if (c_state == IDLE) cnt_r <= cnt_r + 1;
// fsm
always_ff @(posedge clk_i) begin
if (reset_i == 1'b1) c_state <= IDLE;
else c_state <= n_state;
end
always_comb begin
n_state = c_state;
unique case (c_state)
IDLE:
if (cnt_r == 4'd3)
if (data_i == data_pattern) n_state = DONE;
else n_state = BITSLIP;
BITSLIP: n_state = IDLE;
DONE: n_state = DONE;
default: begin
end
endcase
end
assign bitslip_o = (c_state == BITSLIP) ? 1'b1 : 1'b0;
assign done_o = (c_state == DONE) ? 1'b1 : 1'b0;
endmodule
| 6.571748 |
module bsg_gateway_fmc_tx
(input reset_i
,output clk_div_o
,input [87:0] data_i
,output cal_done_o
// fmc tx clk in
,input FCLK0_M2C_P, FCLK0_M2C_N
`ifdef BSG_ML605_FMC
// fmc tx clk out
,output FCLK1_M2C_P, FCLK1_M2C_N
// fmc tx data out [0]
,output F0_P, F0_N
`else
`ifdef BSG_ZEDBOARD_FMC
// fmc tx clk out
,output F0_P, F0_N
// fmc tx data out [0]
,output F1_P, F1_N
`endif
`endif
// fmc tx data out [9:1]
,output F16_P, F16_N
,output F15_P, F15_N
,output F13_P, F13_N
,output F11_P, F11_N
,output F10_P, F10_N
,output F14_P, F14_N
,output F9_P, F9_N
,output F4_P, F4_N
,output F7_P, F7_N
,output F8_P, F8_N);
logic data_clk_div_lo;
logic data_clk_serdes_strobe_lo;
logic data_clk_p_lo, data_clk_n_lo;
bsg_gateway_fmc_tx_clk tx_clk
(.clk_p_i(FCLK0_M2C_P) ,.clk_n_i(FCLK0_M2C_N)
`ifdef BSG_ML605_FMC
,.clk_p_o(FCLK1_M2C_P) ,.clk_n_o(FCLK1_M2C_N)
`else
`ifdef BSG_ZEDBOARD_FMC
,.clk_p_o(F0_P) ,.clk_n_o(F0_N)
`endif
`endif
,.data_clk_div_o(data_clk_div_lo)
,.data_clk_serdes_strobe_o(data_clk_serdes_strobe_lo)
,.data_clk_p_o(data_clk_p_lo) ,.data_clk_n_o(data_clk_n_lo));
assign clk_div_o = data_clk_div_lo;
logic [10:0] data_p_lo, data_n_lo;
// 10 MSB bits [10:1]
assign {F8_P
,F7_P
,F4_P
,F9_P
,F14_P
,F10_P
,F11_P
,F13_P
,F15_P
,F16_P} = data_p_lo[10:1];
assign {F8_N
,F7_N
,F4_N
,F9_N
,F14_N
,F10_N
,F11_N
,F13_N
,F15_N
,F16_N} = data_n_lo[10:1];
// bit[0]
`ifdef BSG_ML605_FMC
assign F0_P = data_p_lo[0];
assign F0_N = data_n_lo[0];
`else
`ifdef BSG_ZEDBOARD_FMC
assign F1_P = data_p_lo[0];
assign F1_N = data_n_lo[0];
`endif
`endif
bsg_gateway_fmc_tx_data tx_data
(.reset_i(reset_i)
,.clk_p_i(data_clk_p_lo) ,.clk_n_i(data_clk_n_lo)
,.clk_div_i(data_clk_div_lo)
,.clk_serdes_strobe_i(data_clk_serdes_strobe_lo)
,.data_i(data_i)
,.cal_done_o(cal_done_o)
,.data_p_o(data_p_lo) ,.data_n_o(data_n_lo));
endmodule
| 6.571748 |
module bsg_gateway_fmc_tx_data (
input reset_i
, input clk_p_i,
clk_n_i
, input clk_div_i
, input clk_serdes_strobe_i
, input [87:0] data_i
, output cal_done_o
, output [10:0] data_p_o,
data_n_o
);
logic [9:0] cnt_r;
always_ff @(posedge clk_div_i)
if (reset_i == 1'b1) cnt_r <= 10'd0;
else if (cnt_r < 10'd1023) cnt_r <= cnt_r + 1;
logic [87:0] data_cal_first_pattern;
logic [87:0] data_cal_second_pattern;
assign data_cal_first_pattern = {11{8'h2C}};
assign data_cal_second_pattern = {11{8'hF8}};
logic [87:0] swap_data_lo, data_lo;
always_comb
if (cnt_r < 10'd1008) data_lo = data_cal_first_pattern;
else if (cnt_r < 10'd1009) data_lo = data_cal_second_pattern;
else if (cnt_r < 10'd1023) data_lo = {11{8'h00}};
else data_lo = data_i;
assign swap_data_lo = ~data_lo; // swapped due to pcb routing
assign cal_done_o = (cnt_r == 10'd1023) ? 1'b1 : 1'b0;
logic [10:0] oserdes_master_shiftout_1_lo, oserdes_master_shiftout_2_lo;
logic [10:0] oserdes_slave_shiftout_3_lo, oserdes_slave_shiftout_4_lo;
logic [10:0] oserdes_data_lo;
genvar i;
generate
for (i = 0; i < 11; i++) begin
OSERDES2 #(
.DATA_WIDTH (8)
, .DATA_RATE_OQ("DDR")
, .DATA_RATE_OT("DDR")
, .SERDES_MODE ("MASTER")
, .OUTPUT_MODE ("DIFFERENTIAL")
) oserdes_master_data (
.OQ(oserdes_data_lo[i])
, .OCE(1'b1)
, .CLK0(clk_p_i)
, .CLK1(clk_n_i)
, .IOCE(clk_serdes_strobe_i)
, .RST(1'b0)
, .CLKDIV(clk_div_i)
, .D4(swap_data_lo[(8*i)+7])
, .D3(swap_data_lo[(8*i)+6])
, .D2(swap_data_lo[(8*i)+5])
, .D1(swap_data_lo[(8*i)+4])
, .TQ()
, .T1(1'b0)
, .T2(1'b0)
, .T3(1'b0)
, .T4(1'b0)
, .TRAIN(1'b0)
, .TCE(1'b1)
, .SHIFTIN1(1'b1)
, .SHIFTIN2(1'b1)
, .SHIFTIN3(oserdes_slave_shiftout_3_lo[i])
, .SHIFTIN4(oserdes_slave_shiftout_4_lo[i])
, .SHIFTOUT1(oserdes_master_shiftout_1_lo[i])
, .SHIFTOUT2(oserdes_master_shiftout_2_lo[i])
, .SHIFTOUT3()
, .SHIFTOUT4()
);
OSERDES2 #(
.DATA_WIDTH (8)
, .DATA_RATE_OQ("DDR")
, .DATA_RATE_OT("DDR")
, .SERDES_MODE ("SLAVE")
, .OUTPUT_MODE ("DIFFERENTIAL")
) oserdes_slave_data (
.OQ()
, .OCE(1'b1)
, .CLK0(clk_p_i)
, .CLK1(clk_n_i)
, .IOCE(clk_serdes_strobe_i)
, .RST(1'b0)
, .CLKDIV(clk_div_i)
, .D4(swap_data_lo[(8*i)+3])
, .D3(swap_data_lo[(8*i)+2])
, .D2(swap_data_lo[(8*i)+1])
, .D1(swap_data_lo[(8*i)+0])
, .TQ()
, .T1(1'b0)
, .T2(1'b0)
, .T3(1'b0)
, .T4(1'b0)
, .TRAIN(1'b0)
, .TCE(1'b1)
, .SHIFTIN1(oserdes_master_shiftout_1_lo[i])
, .SHIFTIN2(oserdes_master_shiftout_2_lo[i])
, .SHIFTIN3(1'b1)
, .SHIFTIN4(1'b1)
, .SHIFTOUT1()
, .SHIFTOUT2()
, .SHIFTOUT3(oserdes_slave_shiftout_3_lo[i])
, .SHIFTOUT4(oserdes_slave_shiftout_4_lo[i])
);
OBUFDS obufds_data (
.I (oserdes_data_lo[i])
, .O (data_p_o[i]),
.OB(data_n_o[i])
);
end
endgenerate
endmodule
| 6.571748 |
module bsg_gateway_iodelay (
input [3:0] clk_output_i
, input [7:0] data_a_output_i
, input [7:0] data_b_output_i
, input [7:0] data_c_output_i
, input [7:0] data_d_output_i
, input [3:0] valid_output_i
, input reset_i
, output [3:0] clk_output_o
, output [7:0] data_a_output_o
, output [7:0] data_b_output_o
, output [7:0] data_c_output_o
, output [7:0] data_d_output_o
, output [3:0] valid_output_o
, output reset_o
);
parameter [7:0] clk_output_tap[3:0] = {8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] data_a_output_tap[7:0] = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] data_b_output_tap[7:0] = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] data_c_output_tap[7:0] = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] data_d_output_tap[7:0] = {8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] valid_output_tap[3:0] = {8'd0, 8'd0, 8'd0, 8'd0};
parameter [7:0] reset_tap = 8'd0;
genvar i;
for (i = 0; i < 4; i = i + 1) begin : c0
bsg_gateway_iodelay_output #(
.tap_i(clk_output_tap[i])
) clk_temp (
.bit_i(clk_output_i[i])
, .bit_o(clk_output_o[i])
);
bsg_gateway_iodelay_output #(
.tap_i(valid_output_tap[i])
) valid_temp (
.bit_i(valid_output_i[i])
, .bit_o(valid_output_o[i])
);
end
for (i = 0; i < 8; i = i + 1) begin : c1
bsg_gateway_iodelay_output #(
.tap_i(data_a_output_tap[i])
) data_a_temp (
.bit_i(data_a_output_i[i])
, .bit_o(data_a_output_o[i])
);
bsg_gateway_iodelay_output #(
.tap_i(data_b_output_tap[i])
) data_b_temp (
.bit_i(data_b_output_i[i])
, .bit_o(data_b_output_o[i])
);
bsg_gateway_iodelay_output #(
.tap_i(data_c_output_tap[i])
) data_c_temp (
.bit_i(data_c_output_i[i])
, .bit_o(data_c_output_o[i])
);
bsg_gateway_iodelay_output #(
.tap_i(data_d_output_tap[i])
) data_d_temp (
.bit_i(data_d_output_i[i])
, .bit_o(data_d_output_o[i])
);
end
for (i = 0; i < 1; i = i + 1) begin : c2
bsg_gateway_iodelay_output #(
.tap_i(reset_tap)
) reset_temp (
.bit_i(reset_i)
, .bit_o(reset_o)
);
end
endmodule
| 7.854181 |
module bsg_gateway_iodelay_output #(
parameter tap_i = 0
) (
input bit_i
, output bit_o
);
IODELAY2 #(
.COUNTER_WRAPAROUND("WRAPAROUND"), // "STAY_AT_LIMIT" or "WRAPAROUND"
.DATA_RATE("DDR"), // "SDR" or "DDR"
.DELAY_SRC("ODATAIN"), // "IO", "ODATAIN" or "IDATAIN"
.IDELAY2_VALUE(0), // Delay value when IDELAY_MODE="PCI" (0-255)
.IDELAY_MODE("NORMAL"), // "NORMAL" or "PCI"
.IDELAY_TYPE("FIXED"), // "FIXED", "DEFAULT", "VARIABLE_FROM_ZERO", "VARIABLE_FROM_HALF_MAX" or "DIFF_PHASE_DETECTOR"
.IDELAY_VALUE(0), // Amount of taps for fixed input delay (0-255)
.ODELAY_VALUE(tap_i), // Amount of taps fixed output delay (0-255)
.SERDES_MODE("NONE"), // "NONE", "MASTER" or "SLAVE"
.SIM_TAPDELAY_VALUE(50) // Per tap delay used for simulation in ps
) IODELAY2_data (
.BUSY(), // 1-bit output: Busy output after CAL
.DATAOUT(), // 1-bit output: Delayed data output to ISERDES/input register
.DATAOUT2(), // 1-bit output: Delayed data output to general FPGA fabric
.DOUT(bit_o), // 1-bit output: Delayed data output
.TOUT(), // 1-bit output: Delayed 3-state output
.CAL(1'b0), // 1-bit input: Initiate calibration input
.CE(1'b0), // 1-bit input: Enable INC input
.CLK(1'b0), // 1-bit input: Clock input
.IDATAIN(1'b0), // 1-bit input: Data input (connect to top-level port or I/O buffer)
.INC(1'b0), // 1-bit input: Increment / decrement input
.IOCLK0(1'b0), // 1-bit input: Input from the I/O clock network
.IOCLK1(1'b0), // 1-bit input: Input from the I/O clock network
.ODATAIN(bit_i), // 1-bit input: Output data input from output register or OSERDES2.
.RST(1'b0), // 1-bit input: Reset to zero or 1/2 of total delay period
.T(1'b0) // 1-bit input: 3-state input signal
);
endmodule
| 7.854181 |
module bsg_gateway_ldo (
input reset_i
, input clk_i
, output logic rstin_o
, output logic spi_out_o
, output logic spi_clk_o
, output logic spi_rst_o
);
logic [10:0] spi_stream_lo;
assign spi_stream_lo = 11'b10110001111;
logic [3:0] state_r, state_n;
logic [7:0] counter_r, counter_n;
logic [7:0] counter_2_r, counter_2_n;
logic rstin_r, rstin_n;
logic spi_rst_r, spi_rst_n;
logic spi_out_r, spi_out_n;
logic spi_clk_r, spi_clk_n;
assign rstin_o = rstin_r;
assign spi_rst_o = spi_rst_r;
assign spi_out_o = spi_out_r;
assign spi_clk_o = spi_clk_r;
always @(posedge clk_i) begin
if (reset_i) begin
state_r <= 0;
counter_r <= 0;
counter_2_r <= 0;
rstin_r <= 1;
spi_rst_r <= 0;
spi_out_r <= 0;
spi_clk_r <= 0;
end else begin
state_r <= state_n;
counter_r <= counter_n;
counter_2_r <= counter_2_n;
rstin_r <= rstin_n;
spi_rst_r <= spi_rst_n;
spi_out_r <= spi_out_n;
spi_clk_r <= spi_clk_n;
end
end
always_comb begin
state_n = state_r;
counter_n = counter_r;
counter_2_n = counter_2_r;
rstin_n = rstin_r;
spi_rst_n = spi_rst_r;
spi_out_n = spi_out_r;
spi_clk_n = spi_clk_r;
if (~reset_i) begin
if (state_r == 0) begin
if (counter_r == 16) begin
state_n = 0;
spi_rst_n = 1;
counter_n = 0;
spi_out_n = spi_stream_lo[counter_n];
end else begin
spi_rst_n = 1;
counter_n = counter_r + 1;
end
end
if (state_r == 1) begin
counter_2_n = counter_2_r + 1;
if (counter_2_r == 3) begin
spi_clk_n = 1;
end
if (counter_2_r == 7) begin
spi_clk_n = 0;
counter_n = counter_r + 1;
counter_2_n = 0;
if (counter_n == 11) begin
state_n = 2;
spi_out_n = 0;
counter_n = 0;
end else begin
spi_out_n = spi_stream_lo[counter_n];
end
end
end
if (state_r == 2) begin
if (counter_r == 16) begin
state_n = 3;
rstin_n = 1;
counter_n = 0;
end else begin
rstin_n = 0;
counter_n = counter_r + 1;
end
end
end
end
endmodule
| 6.934047 |
module bsg_gateway_pll_control (
input reset_i
, input enable_i
, input clk_i
// Command data
, input [31:0] data_i
// tag enable control
, output logic [2:0] spi_rst_o
);
reg [2:0] spi_rst_r, spi_rst_n;
assign spi_rst_o = spi_rst_r;
always @(posedge clk_i) begin
if (reset_i) begin
spi_rst_r <= 3'b111;
end else begin
spi_rst_r <= spi_rst_n;
end
end
always_comb begin
spi_rst_n = spi_rst_r;
if (enable_i == 1'b1) begin
if (data_i[31]) spi_rst_n[2] = 1'b1;
if (data_i[30]) spi_rst_n[2] = 1'b0;
if (data_i[29]) spi_rst_n[1] = 1'b1;
if (data_i[28]) spi_rst_n[1] = 1'b0;
if (data_i[27]) spi_rst_n[0] = 1'b1;
if (data_i[26]) spi_rst_n[0] = 1'b0;
end
end
endmodule
| 6.895893 |
module bsg_gateway_pll_spi (
input clk_i
, input reset_i
// Init RAM
, input init_en_i
, input [15:0] init_data_i
// SPI Out
, input spi_en_i
, output logic spi_ready_o
, output logic spi_cs_o
, output logic spi_out_o
// MB Control
, input mb_en_i
, input mb_reset_i
, input [7:0] mb_addr_i
, input [15:0] mb_data_i
);
// Init RAM
logic [15:0] data_r [255:0];
logic [15:0] data_n;
logic [7:0] counter_r, counter_n;
// SPI Out
logic spi_ready_r, spi_ready_n;
logic [31:0] spi_shift_r, spi_shift_n;
logic [7:0] big_counter_r, big_counter_n;
logic [7:0] small_counter_r, small_counter_n;
logic spi_cs_r, spi_cs_n;
logic spi_out_r, spi_out_n;
logic [7:0] mb_prev_r, mb_prev_n;
assign spi_ready_o = spi_ready_r;
assign spi_cs_o = spi_cs_r;
assign spi_out_o = spi_out_r;
always @(posedge clk_i) begin
if (reset_i) begin
counter_r <= 0;
big_counter_r <= 0;
small_counter_r <= 0;
spi_ready_r <= 1;
spi_shift_r <= 0;
spi_cs_r <= 1;
spi_out_r <= 1;
mb_prev_r <= 0;
end else begin
data_r[counter_r] <= data_n;
counter_r <= counter_n;
big_counter_r <= big_counter_n;
small_counter_r <= small_counter_n;
spi_ready_r <= spi_ready_n;
spi_shift_r <= spi_shift_n;
spi_cs_r <= spi_cs_n;
spi_out_r <= spi_out_n;
mb_prev_r <= mb_prev_n;
end
end
always_comb begin
// Init RAM
data_n = data_r[counter_r];
counter_n = counter_r;
if (init_en_i == 1'b1) begin
data_n = init_data_i;
counter_n = counter_r + 1'b1;
end
// MB Control
mb_prev_n = mb_prev_r;
if (mb_en_i) begin
if (mb_reset_i == 1'b1) begin
mb_prev_n = 0;
counter_n = 0;
end
if (mb_addr_i > mb_prev_r) begin
mb_prev_n = mb_addr_i;
counter_n = counter_r + 1;
data_n = mb_data_i;
end
end
// SPI Out
spi_ready_n = spi_ready_r;
spi_shift_n = spi_shift_r;
big_counter_n = big_counter_r;
small_counter_n = small_counter_r;
spi_out_n = 1;
spi_cs_n = 1;
if ((spi_ready_r == 1'b1) & (spi_en_i == 1'b1)) begin
spi_ready_n = 1'b0;
big_counter_n = 0;
small_counter_n = 0;
spi_shift_n = {8'b00100000, data_r[big_counter_n], 8'b00000000};
end
if (spi_ready_r == 1'b0) begin
if (big_counter_r == counter_r) begin
spi_ready_n = 1'b1;
end else begin
if (small_counter_r == 32) begin
big_counter_n = big_counter_r + 1;
spi_shift_n = {8'b00100000, data_r[big_counter_n], 8'b00000000};
small_counter_n = 0;
end else begin
spi_cs_n = 1'b0;
spi_out_n = spi_shift_r[31];
spi_shift_n = spi_shift_r << 1;
small_counter_n = small_counter_r + 1;
end
end
end
end
endmodule
| 6.895893 |
module bsg_gateway_serdes #(
parameter width = 8
, parameter num_channel = 4
, parameter tap_array = {8'd35, 8'd35, 8'd35, 8'd35}
) (
// Output Side
input io_master_clk_i
, input clk_2x_i
, input [num_channel-1:0] io_serdes_clk_i
, input [num_channel-1:0] io_strobe_i
, input core_calib_done_i
, input [39:0] data_output_i[num_channel-1:0]
, input [4:0] valid_output_i[num_channel-1:0]
, output [num_channel-1:0] token_input_o
, output [num_channel-1:0] clk_output_o
, output [7:0] data_output_o[num_channel-1:0]
, output [num_channel-1:0] valid_output_o
, input [num_channel-1:0] token_input_i
// Input side
, input [num_channel-1:0] raw_clk0_i
, output [num_channel-1:0] div_clk_o
, input [7:0] data_input_i[num_channel-1:0]
, input [num_channel-1:0] valid_input_i
, output [num_channel-1:0] token_output_o
, output [7:0] data_input_0_o[num_channel-1:0]
, output [7:0] data_input_1_o[num_channel-1:0]
, output [num_channel-1:0] valid_input_0_o
, output [num_channel-1:0] valid_input_1_o
, input [num_channel-1:0] token_output_i
);
genvar i;
for (i = 0; i < num_channel; i = i + 1) begin : all_ch
// Output channel
bsg_gateway_serdes_channel #(
.width(width)
) ch_output (
.io_master_clk_i(io_master_clk_i)
, .clk_2x_i(clk_2x_i)
, .io_serdes_clk_i(io_serdes_clk_i[i])
, .io_strobe_i(io_strobe_i[i])
, .core_calib_done_i(core_calib_done_i)
, .data_output_i (data_output_i[i])
, .valid_output_i(valid_output_i[i])
, .token_input_o (token_input_o[i])
, .clk_output_o (clk_output_o[i])
, .data_output_o (data_output_o[i])
, .valid_output_o(valid_output_o[i])
, .token_input_i (token_input_i[i])
);
// Input channel
bsg_gateway_serdes_channel_rx #(
.width(4)
, .tap (tap_array[(8*i)+:8])
) ch_input (
.raw_clk0_i(raw_clk0_i[i])
, .div_clk_o (div_clk_o[i])
, .data_input_i (data_input_i[i])
, .valid_input_i (valid_input_i[i])
, .token_output_o(token_output_o[i])
, .data_input_0_o (data_input_0_o[i])
, .data_input_1_o (data_input_1_o[i])
, .valid_input_0_o(valid_input_0_o[i])
, .valid_input_1_o(valid_input_1_o[i])
, .token_output_i (token_output_i[i])
);
end
endmodule
| 8.153424 |
module bsg_gateway_serdes_output #(
parameter width = 8
) (
input io_master_clk_i
, input io_serdes_clk_i
, input io_strobe_i
, input D8_i
, input D7_i
, input D6_i
, input D5_i
, input D4_i
, input D3_i
, input D2_i
, input D1_i
, output Q_o
);
logic oserdes_master_shiftout_1_lo;
logic oserdes_master_shiftout_2_lo;
logic oserdes_slave_shiftout_3_lo;
logic oserdes_slave_shiftout_4_lo;
// Using two OSERDES2 in cascade mode to get 2x width
OSERDES2 #(
.DATA_WIDTH (width)
, .DATA_RATE_OQ("SDR")
, .DATA_RATE_OT("SDR")
, .SERDES_MODE ("MASTER")
, .OUTPUT_MODE ("SINGLE_ENDED")
) oserdes_master (
.OQ(Q_o)
, .OCE(1'b1)
, .CLK0(io_serdes_clk_i)
, .CLK1()
, .IOCE(io_strobe_i)
, .RST(1'b0)
, .CLKDIV(io_master_clk_i)
, .D4(D8_i)
, .D3(D7_i)
, .D2(D6_i)
, .D1(D5_i)
, .TQ()
, .T1(1'b0)
, .T2(1'b0)
, .T3(1'b0)
, .T4(1'b0)
, .TRAIN(1'b0)
, .TCE(1'b1)
, .SHIFTIN1(1'b1)
, .SHIFTIN2(1'b1)
, .SHIFTIN3(oserdes_slave_shiftout_3_lo)
, .SHIFTIN4(oserdes_slave_shiftout_4_lo)
, .SHIFTOUT1(oserdes_master_shiftout_1_lo)
, .SHIFTOUT2(oserdes_master_shiftout_2_lo)
, .SHIFTOUT3()
, .SHIFTOUT4()
);
OSERDES2 #(
.DATA_WIDTH (width)
, .DATA_RATE_OQ("SDR")
, .DATA_RATE_OT("SDR")
, .SERDES_MODE ("SLAVE")
, .OUTPUT_MODE ("SINGLE_ENDED")
) oserdes_slave (
.OQ()
, .OCE(1'b1)
, .CLK0(io_serdes_clk_i)
, .CLK1()
, .IOCE(io_strobe_i)
, .RST(1'b0)
, .CLKDIV(io_master_clk_i)
, .D4(D4_i)
, .D3(D3_i)
, .D2(D2_i)
, .D1(D1_i)
, .TQ()
, .T1(1'b0)
, .T2(1'b0)
, .T3(1'b0)
, .T4(1'b0)
, .TRAIN(1'b0)
, .TCE(1'b1)
, .SHIFTIN1(oserdes_master_shiftout_1_lo)
, .SHIFTIN2(oserdes_master_shiftout_2_lo)
, .SHIFTIN3(1'b1)
, .SHIFTIN4(1'b1)
, .SHIFTOUT1()
, .SHIFTOUT2()
, .SHIFTOUT3(oserdes_slave_shiftout_3_lo)
, .SHIFTOUT4(oserdes_slave_shiftout_4_lo)
);
endmodule
| 8.153424 |
module bsg_gateway_tag #(
parameter ring_width_p = "inv"
, parameter num_clk_p = "inv"
) (
input clk_i
, input reset_i
, output done_o
// microblaze control
, input mb_control_i
, input [num_clk_p-1:0] mb_select_i
, input [7:0] mb_counter_i
, input [7:0] mb_load_i
, input [2:0] mb_mode_i
// CLK control
, output [1:0] clk_set_o[num_clk_p-1:0]
, output [num_clk_p-1:0] clk_reset_o
// Communication pins
, output tag_tdi_o
, output tag_tms_o
// LED indicator
, output logic test_output
);
// Deal with the async reset issue
logic reset_lo;
bsg_sync_sync #(
.width_p(1)
) reset_ss (
.oclk_i(clk_i)
, .iclk_data_i(reset_i)
, .oclk_data_o(reset_lo)
);
// interface to fsb_trace_replay
logic v_lo;
logic [ring_width_p-1:0] data_lo;
logic yumi_li; // late
// guaranteed not to exceed
localparam rom_addr_width_lp = 16;
localparam trace_width_lp = ring_width_p + 4;
wire [trace_width_lp-1:0] rom_data_lo;
wire [rom_addr_width_lp-1:0] rom_addr_li;
// for wait cycle
logic valid_wait_lo;
logic [31:0] cycle_wait_lo;
logic ready_wait_li;
// For tag transmit
logic valid_tag_lo;
logic [31:0] data_tag_lo;
logic ready_tag_li;
// For tag control
logic valid_control_lo;
logic [31:0] data_control_lo;
// conversion from fsb_trace_replay to bsg_tag modules
always_comb begin
valid_wait_lo = (v_lo & data_lo[ring_width_p-1] & yumi_li);
valid_tag_lo = (v_lo & data_lo[ring_width_p-2] & yumi_li);
valid_control_lo = (v_lo & data_lo[ring_width_p-3] & yumi_li);
cycle_wait_lo = data_lo[31:0];
data_tag_lo = data_lo[31:0];
data_control_lo = data_lo[31:0];
yumi_li = (ready_wait_li & ready_tag_li);
end
// trace replay module
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
, .rom_addr_width_p(rom_addr_width_lp)
) tr (
.clk_i(clk_i)
, .reset_i(reset_lo)
, .en_i(1'b1)
, .v_i()
, .data_i()
, .ready_o()
, .v_o(v_lo)
, .data_o(data_lo)
, .yumi_i(yumi_li)
, .rom_addr_o(rom_addr_li)
, .rom_data_i(rom_data_lo)
, .done_o (done_o)
, .error_o()
);
// ROM that contains commands
bsg_gateway_tag_rom #(
.width_p(trace_width_lp)
, .addr_width_p(rom_addr_width_lp)
) rom (
.addr_i(rom_addr_li)
, .data_o(rom_data_lo)
);
// For delay cycles
wait_cycle_32 w_cycle (
.reset_i(reset_lo)
, .enable_i(valid_wait_lo)
, .clk_i(clk_i)
, .cycle_i(cycle_wait_lo)
, .ready_r_o(ready_wait_li)
, .test_o(test_output)
);
// For MB control
logic mb_valid_lo;
logic [31:0] mb_data_lo;
logic mb_yumi_lo;
bsg_tag_mb #(
.num_clk_p(num_clk_p)
) mb_control (
.reset_i(reset_lo)
, .clk_i(clk_i)
// input from MB
, .mb_control_i(mb_control_i)
, .mb_select_i(mb_select_i)
, .mb_counter_i(mb_counter_i)
, .mb_load_i(mb_load_i)
, .mb_mode_i(mb_mode_i)
// output to bsg_tag
, .mb_valid_o(mb_valid_lo)
, .mb_data_o(mb_data_lo)
, .mb_yumi_i(mb_yumi_lo)
);
// For programming bsg_tag
bsg_tag_output #(
.num_clk_p(num_clk_p)
) t_output (
.reset_i(reset_lo)
, .enable_i(valid_tag_lo)
, .clk_i(clk_i)
, .data_i(data_tag_lo)
, .mb_valid_i(mb_valid_lo)
, .mb_data_i(mb_data_lo)
, .mb_yumi_o(mb_yumi_lo)
, .ready_r_o(ready_tag_li)
, .tag_tdi_o(tag_tdi_o)
);
// For output pins control
bsg_tag_control #(
.num_clk_p(num_clk_p)
) t_control (
.reset_i(reset_lo)
, .enable_i(valid_control_lo)
, .clk_i(clk_i)
, .data_i(data_control_lo)
, .clk_set_o(clk_set_o)
, .clk_reset_o(clk_reset_o)
, .tag_tms_o(tag_tms_o)
);
endmodule
| 7.789465 |
module bsg_gray_to_binary #(
parameter width_p = -1
) (
input [width_p-1:0] gray_i
, output [width_p-1:0] binary_o
);
// or alternatively
// the entertaining:
// assign binary_o[width_p-1:0] = ({1'b0, binary_o[width_p-1:1]} ^ gray_i[width_p-1:0]);
/*
assign binary_o[width_p-1] = gray_i[width_p-1];
generate
genvar i;
for (i = 0; i < width_p-1; i=i+1)
begin
assign binary_o[i] = binary_o[i+1] ^ gray_i[i];
end
endgenerate
*/
// logarithmic depth of the above
bsg_scan #(
.width_p(width_p)
, .xor_p (1)
) scan_xor (
.i(gray_i)
, .o(binary_o)
);
endmodule
| 6.794758 |
module bsg_hash_bank_banks_p2_width_p5 (
i,
bank_o,
index_o
);
input [4:0] i;
output [0:0] bank_o;
output [3:0] index_o;
wire [0:0] bank_o;
wire [3:0] index_o;
wire index_o_3_, index_o_2_, index_o_1_, index_o_0_;
assign bank_o[0] = i[4];
assign index_o_3_ = i[3];
assign index_o[3] = index_o_3_;
assign index_o_2_ = i[2];
assign index_o[2] = index_o_2_;
assign index_o_1_ = i[1];
assign index_o[1] = index_o_1_;
assign index_o_0_ = i[0];
assign index_o[0] = index_o_0_;
endmodule
| 6.743449 |
module cordic_stage #(
parameter stage_p = 1
, parameter width_p = 12
) (
input clk
, input [width_p+7:0] x
, input [width_p+7:0] y
, output [width_p+7:0] x_n
, output [width_p+7:0] y_n
);
wire [width_p+7:0] x_shift = x >>> stage_p;
wire [width_p+7:0] y_shift = $signed(y) >>> stage_p;
assign x_n = (y[width_p+7]) ? (x - y_shift) : (x + y_shift);
assign y_n = (y[width_p+7]) ? (y + x_shift) : (y - x_shift);
endmodule
| 6.628248 |
module bsg_hypotenuse #(
parameter width_p = 12
) (
input clk
, input [width_p-1:0] x_i
, input [width_p-1:0] y_i
, output [width_p:0] o
);
logic [width_p-1:0] x_set, y_set;
logic [width_p+7:0] ans_next;
logic [width_p+7:0] x[width_p+1:0];
logic [width_p+7:0] y[width_p+1:0];
logic [width_p+7:0] x_ans[width_p:0];
logic [width_p+7:0] y_ans[width_p:0];
initial
assert (width_p == 12)
else $error("warning this module has not been tested for width_p != 12");
// final_addition = 19 bit representation of 6'b100001
localparam final_add_lp = 19'b100001;
wire switch = (x_i < y_i);
assign x_set = (switch) ? y_i : x_i;
assign y_set = (switch) ? x_i : y_i;
always_ff @(posedge clk) begin
x[0] <= {1'd0, x_set, 6'd0};
y[0] <= {1'd0, y_set, 6'd0};
end
genvar i;
generate
for (i = 0; i <= width_p; i = i + 1) begin : stage
cordic_stage #(
.stage_p(i)
) cs (
.clk(clk)
, .x (x[i])
, .y (y[i])
, .x_n(x_ans[i])
, .y_n(y_ans[i])
);
always_ff @(posedge clk) begin
x[i+1] <= x_ans[i];
y[i+1] <= y_ans[i];
end
end
endgenerate
logic [width_p+18:0] scaling_ans_r, ans_n;
// multiply by scaling factor scaling factor = 12'b100110110111
always_ff @(posedge clk) scaling_ans_r <= x[13] * 12'b100110110111;
assign ans_n = scaling_ans_r[30:12] + final_add_lp;
logic [width_p:0] ans_r;
always_ff @(posedge clk) ans_r <= ans_n[18:6];
assign o = ans_r;
endmodule
| 8.61031 |
module bsg_iddr_phy #(
parameter width_p = "inv"
) (
input clk_i
, input [width_p-1:0] data_i
, output [2*width_p-1:0] data_o
);
logic [2*width_p-1:0] data_r;
logic [ width_p-1:0] data_p;
assign data_o = data_r;
always @(posedge clk_i) data_p <= data_i;
always @(negedge clk_i) data_r <= {data_i, data_p};
endmodule
| 7.071844 |
module maintains of a pool of IDs, and supports allocation and deallocation of these IDs.
*
*/
`include "bsg_defines.v"
module bsg_id_pool
#(parameter `BSG_INV_PARAM(els_p)
, parameter id_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input clk_i,
input reset_i
// next available id
, output logic [id_width_lp-1:0] alloc_id_o
, output logic alloc_v_o
, input alloc_yumi_i
// id to return
, input dealloc_v_i
, input [id_width_lp-1:0] dealloc_id_i
);
// keeps track of which id has been allocated.
logic [els_p-1:0] allocated_r;
// next id to dealloc
logic [els_p-1:0] dealloc_decode;
bsg_decode_with_v #(
.num_out_p(els_p)
) d1 (
.i(dealloc_id_i)
,.v_i(dealloc_v_i)
,.o(dealloc_decode)
);
// find the next available id.
logic [id_width_lp-1:0] alloc_id_lo;
logic alloc_v_lo;
logic [els_p-1:0] one_hot_out;
// We use this v_o instead of the v_o of bsg_encode_one_hot
// because it has better critical path
bsg_priority_encode_one_hot_out #(
.width_p(els_p)
,.lo_to_hi_p(1)
) pe0 (
.i(~allocated_r | dealloc_decode)
,.o(one_hot_out)
,.v_o(alloc_v_lo)
);
bsg_encode_one_hot #(
.width_p(els_p)
,.lo_to_hi_p(1)
) enc0 (
.i(one_hot_out)
,.addr_o(alloc_id_lo)
,.v_o()
);
assign alloc_id_o = alloc_id_lo;
assign alloc_v_o = alloc_v_lo;
// next id to alloc
wire [els_p-1:0] alloc_decode = one_hot_out & {els_p{alloc_yumi_i}};
// Immediately allocating the deallocated id is allowed.
bsg_dff_reset_set_clear #(
.width_p(els_p)
) dff_alloc0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.set_i(alloc_decode)
,.clear_i(dealloc_decode)
,.data_o(allocated_r)
);
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
if (dealloc_v_i) begin
assert(allocated_r[dealloc_id_i]) else $error("Cannot deallocate an id that hasn't been allocated.");
assert(dealloc_id_i < els_p) else $error("Cannot deallocate an id that is outside the range.");
end
if (alloc_yumi_i)
assert(alloc_v_o) else $error("Handshaking error. alloc_yumi_i raised without alloc_v_o.");
if (alloc_yumi_i & dealloc_v_i & (alloc_id_o == dealloc_id_i))
assert(allocated_r[dealloc_id_i]) else $error("Cannot immediately dellocate an allocated id.");
end
end
// synopsys translate_on
endmodule
| 7.219616 |
module maintains of a pool of IDs, and supports allocation and deallocation of these IDs,
* and also live tracking of which ones are active.
*
* Only one item can be allocated per cycle (for now), but any number can be deallocated per cycle.
*
* order of precedence:
*
* actives_id_r_o is before any request to deallocate or allocate has been processed (early)
* alloc_id_one_hot_o is before any request to deallocate has been processed (middle)
* dealloc_ids_i *can* be applied to an alloc'd ID (but not necessarily recommended) (late)
* yumi_i (late)
*
* deallocating ID in same cycle as allocating is not allowed
*
* This module is helpful on all outputs.
*
* The interface has a different priority of alloc versus dealloc versus
* bsg_id_pool; should either rename that one to bsg_id_pool_alloc_dealloc
* or consider refactoring that interface, depending on how that one seems to
* be used over time.
*/
`include "bsg_defines.v"
module bsg_id_pool_dealloc_alloc_one_hot
#(parameter `BSG_INV_PARAM(els_p))
(
input clk_i
, input reset_i
// bitvector of all active IDs, before any allocation or deallocation is done
, output [els_p-1:0] active_ids_r_o
// next available id
, output logic [els_p-1:0] alloc_id_one_hot_o
// whether any bit of the above is set
, output logic alloc_id_v_o
// whether the client accepts the proferred ID
, input alloc_yumi_i
// bitmask; can actually deallocate multiple in parallel
// can deallocate something that was just allocated (although this may
// impact critical path)
, input [els_p-1:0] dealloc_ids_i
);
// keeps track of which id has been allocated.
logic [els_p-1:0] allocated_r;
// find the next available id.
bsg_priority_encode_one_hot_out #(
.width_p(els_p)
,.lo_to_hi_p(1)
) pe0 (
.i(~allocated_r)
,.o(alloc_id_one_hot_o)
,.v_o(alloc_id_v_o)
);
// update internal state with allocated ID, if it is accepted.
wire [els_p-1:0] alloc_set = alloc_id_one_hot_o & {els_p{alloc_yumi_i}};
// bsg_id_pool_one_hot will never allocate an item that is being deallocated in the same
// cycle, to avoid critical paths.
//
// bsg_id_pool_one_hot *does* allow the outer logic to clear an item that was just allocated,
// although this may impact the critical path.
bsg_dff_reset_set_clear #(
.width_p(els_p)
,.clear_over_set_p(1)
) dff_alloc0 (
.clk_i(clk_i)
,.reset_i(reset_i)
,.set_i(alloc_set)
,.clear_i(dealloc_ids_i)
,.data_o(allocated_r)
);
assign active_ids_r_o = allocated_r;
// synopsys translate_off
always_ff @ (negedge clk_i) begin
if (~reset_i) begin
assert ((dealloc_ids_i & ~(allocated_r | alloc_set)) == '0)
else $error("Cannot deallocate an id that hasn't been allocated.");
if (alloc_yumi_i)
assert(alloc_id_v_o) else $error("Handshaking error. alloc_yumi_i raised without alloc_v_o.");
$display("bsg_id_pool_one_hot: allocated_r=%b dealloc_ids_i=%b alloc_id_v_o=%b", allocated_r, dealloc_ids_i, alloc_id_v_o);
end
end
// synopsys translate_on
endmodule
| 7.219616 |
module bsg_launch_sync_sync_posedge_1_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [0:0] iclk_data_i;
output [0:0] iclk_data_o;
output [0:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [0:0] iclk_data_o, oclk_data_o, bsg_SYNC_1_r;
wire N0, N1, N2, N3;
reg iclk_data_o_0_sv2v_reg, bsg_SYNC_1_r_0_sv2v_reg, oclk_data_o_0_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge iclk_i) begin
if (1'b1) begin
iclk_data_o_0_sv2v_reg <= N3;
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
assign N3 = (N0) ? 1'b0 : (N1) ? iclk_data_i[0] : 1'b0;
assign N0 = iclk_reset_i;
assign N1 = N2;
assign N2 = ~iclk_reset_i;
endmodule
| 6.954266 |
module bsg_launch_sync_sync_posedge_4_unit (
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [3:0] iclk_data_i;
output [3:0] iclk_data_o;
output [3:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [3:0] iclk_data_o, oclk_data_o, bsg_SYNC_1_r;
wire N0, N1, N2, N3, N4, N5, N6;
reg
iclk_data_o_3_sv2v_reg,
iclk_data_o_2_sv2v_reg,
iclk_data_o_1_sv2v_reg,
iclk_data_o_0_sv2v_reg,
bsg_SYNC_1_r_3_sv2v_reg,
bsg_SYNC_1_r_2_sv2v_reg,
bsg_SYNC_1_r_1_sv2v_reg,
bsg_SYNC_1_r_0_sv2v_reg,
oclk_data_o_3_sv2v_reg,
oclk_data_o_2_sv2v_reg,
oclk_data_o_1_sv2v_reg,
oclk_data_o_0_sv2v_reg;
assign iclk_data_o[3] = iclk_data_o_3_sv2v_reg;
assign iclk_data_o[2] = iclk_data_o_2_sv2v_reg;
assign iclk_data_o[1] = iclk_data_o_1_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[3] = bsg_SYNC_1_r_3_sv2v_reg;
assign bsg_SYNC_1_r[2] = bsg_SYNC_1_r_2_sv2v_reg;
assign bsg_SYNC_1_r[1] = bsg_SYNC_1_r_1_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[3] = oclk_data_o_3_sv2v_reg;
assign oclk_data_o[2] = oclk_data_o_2_sv2v_reg;
assign oclk_data_o[1] = oclk_data_o_1_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge iclk_i) begin
if (1'b1) begin
iclk_data_o_3_sv2v_reg <= N6;
end
end
always @(posedge iclk_i) begin
if (1'b1) begin
iclk_data_o_2_sv2v_reg <= N5;
end
end
always @(posedge iclk_i) begin
if (1'b1) begin
iclk_data_o_1_sv2v_reg <= N4;
end
end
always @(posedge iclk_i) begin
if (1'b1) begin
iclk_data_o_0_sv2v_reg <= N3;
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
bsg_SYNC_1_r_3_sv2v_reg <= iclk_data_o[3];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
bsg_SYNC_1_r_2_sv2v_reg <= iclk_data_o[2];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
bsg_SYNC_1_r_1_sv2v_reg <= iclk_data_o[1];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
oclk_data_o_3_sv2v_reg <= bsg_SYNC_1_r[3];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
oclk_data_o_2_sv2v_reg <= bsg_SYNC_1_r[2];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
oclk_data_o_1_sv2v_reg <= bsg_SYNC_1_r[1];
end
end
always @(posedge oclk_i) begin
if (1'b1) begin
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
assign {N6, N5, N4, N3} = (N0) ? {1'b0, 1'b0, 1'b0, 1'b0} : (N1) ? iclk_data_i : 1'b0;
assign N0 = iclk_reset_i;
assign N1 = N2;
assign N2 = ~iclk_reset_i;
endmodule
| 6.954266 |
module bsg_less_than #(parameter `BSG_INV_PARAM(width_p)) (
input [width_p-1:0] a_i
,input [width_p-1:0] b_i
,output logic o // a is less than b
);
assign o = (a_i < b_i);
endmodule
| 7.976699 |
module bsg_level_shift_up_down_sink #(parameter `BSG_INV_PARAM(width_p ))
(
input [width_p-1:0] v0_data_i,
input v1_en_i,
output logic [width_p-1:0] v1_data_o
);
genvar i;
for (i = 0; i < width_p; i++)
begin : n
A2LVLU_X2N_A7P5PP96PTS_C18 level_shift_sink (
.EN(v1_en_i), // active high
.A(v0_data_i[i]),
.Y(v1_data_o[i])
);
end : n
endmodule
| 7.573656 |
module bsg_level_shift_up_down_source #(parameter `BSG_INV_PARAM(width_p ))
(
input v0_en_i,
input [width_p-1:0] v0_data_i,
output logic [width_p-1:0] v1_data_o
);
genvar i;
for (i = 0; i < width_p; i++)
begin : n
A2LVLUO_X2N_A7P5PP96PTS_C18 level_shift_source (
.EN(v0_en_i), // active high
.A(v0_data_i[i]),
.Y(v1_data_o[i])
);
end : n
endmodule
| 7.573656 |
module bsg_lfsr #(parameter `BSG_INV_PARAM(width_p)
, init_val_p = 1 // an initial value of zero is typically the null point for LFSR's.
, xor_mask_p = 0)
(input clk
, input reset_i
, input yumi_i
, output logic [width_p-1:0] o
);
logic [width_p-1:0] o_r, o_n, xor_mask;
assign o = o_r;
// auto mask value
if (xor_mask_p == 0)
begin : automask
// fixme fill this in: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf
case (width_p)
32:
assign xor_mask = (1 << 31) | (1 << 29) | (1 << 26) | (1 << 25);
60:
assign xor_mask = (1 << 59) | (1 << 58);
64:
assign xor_mask = (1 << 63) | (1 << 62) | (1 << 60) | (1 << 59);
default:
initial assert(width_p==-1)
else
begin
$display("unhandled default mask for width %d in bsg_lfsr",width_p); $finish();
end
endcase // case (width_p)
end
else
begin: fi
assign xor_mask = xor_mask_p;
end
always @(posedge clk)
begin
if (reset_i)
o_r <= (width_p) ' (init_val_p);
else if (yumi_i)
o_r <= o_n;
end
assign o_n = (o_r >> 1) ^ ({width_p {o_r[0]}} & xor_mask);
endmodule
| 7.636994 |
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