code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_mem_2rw_sync_mask_write_bit #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
, parameter disable_collision_warning_p=0
, parameter enable_clock_gating_p=0
)
( input clk_i
, input reset_i
, input [width_p-1:0] a_data_i
, input [width_p-1:0] a_w_mask_i
, input [addr_width_lp-1:0] a_addr_i
, input a_v_i
, input a_w_i
, input [width_p-1:0] b_data_i
, input [width_p-1:0] b_w_mask_i
, input [addr_width_lp-1:0] b_addr_i
, input b_v_i
, input b_w_i
, output logic [width_p-1:0] a_data_o
, output logic [width_p-1:0] b_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( a_v_i | b_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_2rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
) synth
(.clk_i (clk_lo)
,.reset_i
,.a_data_i
,.a_w_mask_i
,.a_addr_i
,.a_v_i
,.a_w_i
,.b_data_i
,.b_w_mask_i
,.b_addr_i
,.b_v_i
,.b_w_i
,.a_data_o
,.b_data_o
);
// synopsys translate_off
always_ff @(negedge clk_lo)
if (a_v_i | b_v_i) begin
assert ((reset_i === 'X) || (reset_i === 1'b1) || (a_addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", a_addr_i, els_p, reset_i, a_v_i, clk_lo);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (b_addr_i < els_p))
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", b_addr_i, els_p, reset_i, b_v_i, clk_lo);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (~(a_addr_i == b_addr_i && a_v_i && b_v_i && (a_w_i ^ b_w_i))) && !read_write_same_addr_p && !disable_collision_warning_p)
else $error("%m: Attempt to read and write same address reset_i %b, %x <= %x (mask %x), %x <= %x (mask %x)",reset_i, a_addr_i,a_data_i,a_w_mask_i, b_addr_i, b_data_i, b_w_mask_i);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (~(a_addr_i == b_addr_i && a_v_i && b_v_i && (a_w_i & b_w_i))))
else $error("%m: Attempt to write and write same address reset_i %b, %x <= %x (mask %x), %x <= %x (mask %x)",reset_i, a_addr_i,a_data_i,a_w_mask_i, b_addr_i, b_data_i, b_w_mask_i);
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
if (disable_collision_warning_p)
$display("## %m %L: disable_collision_warning_p is set; you should not have this on unless you have broken code. fix it!\n");
end
// synopsys translate_on
endmodule
| 7.889919 |
module bsg_mem_2rw_sync_mask_write_bit_synth #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter disable_collision_warning_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 1
)
( input clk_i
, input reset_i
, input [width_p-1:0] a_data_i
, input [width_p-1:0] a_w_mask_i
, input [addr_width_lp-1:0] a_addr_i
, input a_v_i
, input a_w_i
, input [width_p-1:0] b_data_i
, input [width_p-1:0] b_w_mask_i
, input [addr_width_lp-1:0] b_addr_i
, input b_v_i
, input b_w_i
, output logic [width_p-1:0] a_data_o
, output logic [width_p-1:0] b_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, a_data_i, a_w_mask_i, a_addr_i, a_v_i, a_w_i};
wire unused1 = &{clk_i, b_data_i, b_w_mask_i, b_addr_i, b_v_i, b_w_i};
assign a_data_o = '0;
assign b_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// this treats the ram as an array of registers for which the
// read addr is latched on the clock, the write
// is done on the clock edge, and actually multiplexing
// of the registers for reading is done after the clock edge.
// logically, this means that reads happen in time after
// the writes, and "simultaneous" reads and writes to the
// register file are allowed -- IF read_write_same_addr is set.
// note that this behavior is generally incompatible with
// hardened 1r1w rams, so it's better not to take advantage
// of it if not necessary
// we explicitly 'X out the read address if valid is not set
// to avoid accidental use of data when the valid signal was not
// asserted. without this, the output of the register file would
// "auto-update" based on new writes to the ram, a spooky behavior
// that would never correspond to that of a hardened ram.
logic [addr_width_lp-1:0] a_addr_r, b_addr_r;
always_ff @(posedge clk_i)
begin
if (a_v_i)
a_addr_r <= a_addr_i;
else
a_addr_r <= 'X;
if (b_v_i)
b_addr_r <= b_addr_i;
else
b_addr_r <= 'X;
// if addresses match and this is forbidden, then nuke the read address
if (a_addr_i == b_addr_i && a_v_i && b_v_i && (a_w_i || b_w_i) && !read_write_same_addr_p)
begin
if (!disable_collision_warning_p)
begin
$error("X'ing matched read addresses %x %x (%m)",a_addr_i, b_addr_i);
end
a_addr_r <= 'X;
b_addr_r <= 'X;
end
// synopsys translate_on
end
assign a_data_o = mem[a_addr_r];
assign b_data_o = mem[b_addr_r];
genvar i;
for (i = 0; i < width_p; i=i+1)
begin
always_ff @(posedge clk_i)
begin
if (a_v_i & a_w_i && a_w_mask_i[i])
mem[a_addr_i][i] <= a_data_i[i];
if (b_v_i & b_w_i && b_w_mask_i[i])
mem[b_addr_i][i] <= b_data_i[i];
end
end
end
endmodule
| 7.889919 |
module bsg_mem_2rw_sync_mask_write_byte #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
, parameter disable_collision_warning_p=0
, parameter enable_clock_gating_p=0
, parameter write_mask_width_lp=(width_p>>3)
)
( input clk_i
, input reset_i
, input [width_p-1:0] a_data_i
, input [write_mask_width_lp-1:0] a_w_mask_i
, input [addr_width_lp-1:0] a_addr_i
, input a_v_i
, input a_w_i
, input [width_p-1:0] b_data_i
, input [write_mask_width_lp-1:0] b_w_mask_i
, input [addr_width_lp-1:0] b_addr_i
, input b_v_i
, input b_w_i
, output logic [width_p-1:0] a_data_o
, output logic [width_p-1:0] b_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( a_v_i | b_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_2rw_sync_mask_write_byte_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.clk_i (clk_lo)
,.reset_i
,.a_data_i
,.a_w_mask_i
,.a_addr_i
,.a_v_i
,.a_w_i
,.b_data_i
,.b_w_mask_i
,.b_addr_i
,.b_v_i
,.b_w_i
,.a_data_o
,.b_data_o
);
// synopsys translate_off
always_ff @(negedge clk_lo)
if (a_v_i || b_v_i) begin
assert ((reset_i === 'X) || (reset_i === 1'b1) || (a_addr_i < els_p) || ~a_v_i)
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", a_addr_i, els_p, reset_i, a_v_i, clk_lo);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (a_addr_i < els_p) || ~b_v_i)
else $error("Invalid address %x to %m of size %x (reset_i = %b, v_i = %b, clk_lo=%b)\n", b_addr_i, els_p, reset_i, b_v_i, clk_lo);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (~(a_addr_i == b_addr_i && a_v_i && b_v_i && (a_w_i ^ b_w_i))) && !read_write_same_addr_p && !disable_collision_warning_p)
else $error("%m: Attempt to read and write same address reset_i %b, %x <= %x (mask %x), %x <= %x (mask %x)",reset_i, a_addr_i,a_data_i,a_w_mask_i, b_addr_i,b_data_i,b_w_mask_i);
assert ((reset_i === 'X) || (reset_i === 1'b1) || (~(a_addr_i == b_addr_i && a_v_i && b_v_i && (a_w_i & b_w_i))))
else $error("%m: Attempt to write and write same address reset_i %b, %x <= %x (mask %x), %x <= %x (mask %x)",reset_i, a_addr_i,a_data_i,a_w_mask_i, b_addr_i,b_data_i,b_w_mask_i);
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
if (disable_collision_warning_p)
$display("## %m %L: disable_collision_warning_p is set; you should not have this on unless you have broken code. fix it!\n");
end
// synopsys translate_on
endmodule
| 7.889919 |
module bsg_mem_2rw_sync_mask_write_byte_synth #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 1
, parameter disable_collision_warning_p=0
, parameter write_mask_width_lp=(width_p>>3)
)
( input clk_i
, input reset_i
, input [width_p-1:0] a_data_i
, input [write_mask_width_lp-1:0] a_w_mask_i
, input [addr_width_lp-1:0] a_addr_i
, input a_v_i
, input a_w_i
, input [width_p-1:0] b_data_i
, input [write_mask_width_lp-1:0] b_w_mask_i
, input [addr_width_lp-1:0] b_addr_i
, input b_v_i
, input b_w_i
, output logic [width_p-1:0] a_data_o
, output logic [width_p-1:0] b_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, a_data_i, a_w_mask_i, a_addr_i, a_v_i, a_w_i};
wire unused1 = &{clk_i, b_data_i, b_w_mask_i, b_addr_i, b_v_i, b_w_i};
assign a_data_o = '0;
assign b_data_o = '0;
end
else
begin: nz
genvar i;
for(i=0; i<write_mask_width_lp; i=i+1)
begin: bk
bsg_mem_2rw_sync #( .width_p (8)
,.els_p (els_p)
,.addr_width_lp(addr_width_lp)
,.disable_collision_warning_p(disable_collision_warning_p)
,.harden_p(harden_p)
) mem_2rw_sync
( .clk_i (clk_i)
,.reset_i(reset_i)
,.a_data_i (a_data_i[(i*8)+:8])
,.a_addr_i (a_addr_i)
,.a_v_i (a_v_i & (a_w_i ? a_w_mask_i[i] : 1'b1))
,.a_w_i (a_w_i & a_w_mask_i[i])
,.a_data_o (a_data_o[(i*8)+:8])
,.b_data_i (b_data_i[(i*8)+:8])
,.b_addr_i (b_addr_i)
,.b_v_i (b_v_i & (b_w_i ? b_w_mask_i[i] : 1'b1))
,.b_w_i (b_w_i & b_w_mask_i[i])
,.b_data_o (b_data_o[(i*8)+:8])
);
end
end
endmodule
| 7.889919 |
module bsg_mem_2rw_sync_synth #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 1
, parameter disable_collision_warning_p=0
)
( input clk_i
, input reset_i
, input [width_p-1:0] a_data_i
, input [addr_width_lp-1:0] a_addr_i
, input a_v_i
, input a_w_i
, input [width_p-1:0] b_data_i
, input [addr_width_lp-1:0] b_addr_i
, input b_v_i
, input b_w_i
, output logic [width_p-1:0] a_data_o
, output logic [width_p-1:0] b_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, a_data_i, a_addr_i, a_v_i, a_w_i};
wire unused1 = &{clk_i, b_data_i, b_addr_i, b_v_i, b_w_i};
assign a_data_o = '0;
assign b_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// this treats the ram as an array of registers for which the
// read addr is latched on the clock, the write
// is done on the clock edge, and actually multiplexing
// of the registers for reading is done after the clock edge.
// logically, this means that reads happen in time after
// the writes, and "simultaneous" reads and writes to the
// register file are allowed -- IF read_write_same_addr is set.
// note that this behavior is generally incompatible with
// hardened 1r1w rams, so it's better not to take advantage
// of it if not necessary
// we explicitly 'X out the read address if valid is not set
// to avoid accidental use of data when the valid signal was not
// asserted. without this, the output of the register file would
// "auto-update" based on new writes to the ram, a spooky behavior
// that would never correspond to that of a hardened ram.
logic [addr_width_lp-1:0] a_addr_r, b_addr_r;
always_ff @(posedge clk_i)
begin
if (a_v_i)
a_addr_r <= a_addr_i;
else
a_addr_r <= 'X;
if (b_v_i)
b_addr_r <= b_addr_i;
else
b_addr_r <= 'X;
// synopsys translate_off
// if addresses match and this is forbidden, then nuke the read address
if (a_addr_i == b_addr_i && a_v_i && b_v_i && (a_w_i || b_w_i) && !read_write_same_addr_p)
begin
if (!disable_collision_warning_p)
begin
$error("X'ing matched read address %x (%m)",a_addr_i);
end
a_addr_r <= 'X;
b_addr_r <= 'X;
end
// synopsys translate_on
end
assign a_data_o = mem[a_addr_r];
assign b_data_o = mem[b_addr_r];
always_ff @(posedge clk_i)
begin
if (a_v_i & a_w_i)
mem[a_addr_i] <= a_data_i;
if (b_v_i & b_w_i)
mem[b_addr_i] <= b_data_i;
end
end
endmodule
| 7.889919 |
module bsg_mem_3r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r2_data_o
);
bsg_mem_3r1w_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
) synth
(.*);
//synopsys translate_off
always_ff @(negedge w_clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (!(r0_addr_i == w_addr_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
assert (!(r1_addr_i == w_addr_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
assert (!(r2_addr_i == w_addr_i && r2_v_i && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
end
initial
begin
$display("## bsg_mem_3r1w: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d (%m)",width_p,els_p,read_write_same_addr_p);
end
//synopsys translate_on
endmodule
| 7.36256 |
module bsg_mem_3r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0 // specifically write_then_read_p
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
, parameter enable_clock_gating_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r2_data_o
);
wire clk_lo;
if (enable_clock_gating_p)
begin
bsg_clkgate_optional icg
(.clk_i( clk_i )
,.en_i( w_v_i | r0_v_i | r1_v_i | r2_v_i )
,.bypass_i( 1'b0 )
,.gated_clock_o( clk_lo )
);
end
else
begin
assign clk_lo = clk_i;
end
bsg_mem_3r1w_sync_synth
#(.width_p(width_p)
,.els_p(els_p)
,.read_write_same_addr_p(read_write_same_addr_p)
) synth
(.clk_i( clk_lo )
,.reset_i
,.w_v_i
,.w_addr_i
,.w_data_i
,.r0_v_i
,.r0_addr_i
,.r0_data_o
,.r1_v_i
,.r1_addr_i
,.r1_data_o
,.r2_v_i
,.r2_addr_i
,.r2_data_o
);
//synopsys translate_off
always_ff @(negedge clk_lo)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
assert (~(r2_addr_i == w_addr_i && r2_v_i && !read_write_same_addr_p))
else $error("%m: port 2 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)"
,width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
| 7.273086 |
module directly
// they should use bsg_mem_3r1w_sync.
`include "bsg_defines.v"
module bsg_mem_3r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r2_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, w_v_i, w_addr_i, w_data_i, r0_v_i, r0_addr_i, r1_v_i, r1_addr_i, r2_v_i, r2_addr_i};
assign r0_data_o = '0;
assign r1_data_o = '0;
assign r2_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// keep consistent with bsg_ip_cores/bsg_mem/bsg_mem_3r1w_sync.v
// keep consistent with bsg_ip_cores/hard/bsg_mem/bsg_mem_3r1w_sync.v
// this treats the ram as an array of registers for which the
// read addr is latched on the clock, the write
// is done on the clock edge, and actually multiplexing
// of the registers for reading is done after the clock edge.
// logically, this means that reads happen in time after
// the writes, and "simultaneous" reads and writes to the
// register file are allowed -- IF read_write_same_addr is set.
// note that this behavior is generally incompatible with
// hardened 1r1w rams, so it's better not to take advantage
// of it if not necessary
// we explicitly 'X out the read address if valid is not set
// to avoid accidental use of data when the valid signal was not
// asserted. without this, the output of the register file would
// "auto-update" based on new writes to the ram, a spooky behavior
// that would never correspond to that of a hardened ram.
//the read logic, register the input
logic [addr_width_lp-1:0] r0_addr_r, r1_addr_r, r2_addr_r;
always_ff @(posedge clk_i)
if (r0_v_i)
r0_addr_r <= r0_addr_i;
else
r0_addr_r <= 'X;
always_ff @(posedge clk_i)
if (r1_v_i)
r1_addr_r <= r1_addr_i;
else
r1_addr_r <= 'X;
always_ff @(posedge clk_i)
if (r2_v_i)
r2_addr_r <= r2_addr_i;
else
r2_addr_r <= 'X;
assign r0_data_o = mem[ r0_addr_r ];
assign r1_data_o = mem[ r1_addr_r ];
assign r2_data_o = mem[ r2_addr_r ];
//the write logic, the memory is treated as dff array
always_ff @(posedge clk_i)
if (w_v_i)
mem[w_addr_i] <= w_data_i;
end
endmodule
| 7.532796 |
module bsg_mem_3r1w_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r2_data_o
);
wire unused = w_reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{w_clk_i, w_v_i, w_addr_i, w_data_i, r0_v_i, r0_addr_i, r1_v_i, r1_addr_i, r2_v_i, r2_addr_i};
assign r0_data_o = '0;
assign r1_data_o = '0;
assign r2_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// this implementation ignores the r_v_i
assign r2_data_o = mem[r2_addr_i];
assign r1_data_o = mem[r1_addr_i];
assign r0_data_o = mem[r0_addr_i];
wire unused = w_reset_i;
always_ff @(posedge w_clk_i)
if (w_v_i)
begin
mem[w_addr_i] <= w_data_i;
end
end
endmodule
| 7.273086 |
module bsg_mesh_stitch
import bsg_noc_pkg::*; // P=0, W, E, N, S
#(parameter `BSG_INV_PARAM(width_p ) // data width
, x_max_p = "inv"
, y_max_p = "inv"
, nets_p = 1 // optional parameter that allows for multiple networks to be routed together
)
(input [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] outs_i // for each node, each direction
, output [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:W][width_p-1:0] ins_o
// these are the edge of the greater tile
, input [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_i
, output [E:W][y_max_p-1:0][nets_p-1:0][width_p-1:0] hor_o
, input [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_i
, output [S:N][x_max_p-1:0][nets_p-1:0][width_p-1:0] ver_o
);
genvar r,c,net;
for (net = 0; net < nets_p; net=net+1)
begin: _n
for (r = 0; r < y_max_p; r=r+1)
begin: _r
assign hor_o[E][r][net] = outs_i[r][x_max_p-1][net][E];
assign hor_o[W][r][net] = outs_i[r][0 ][net][W];
for (c = 0; c < x_max_p; c=c+1)
begin: _c
assign ins_o[r][c][net][S] = (r == y_max_p-1)
? ver_i[S][c][net]
: outs_i[(r == y_max_p-1) ? r : r+1][c][net][N]; // ?: for warning
assign ins_o[r][c][net][N] = (r == 0)
? ver_i[N][c][net]
: outs_i[r ? r-1: 0][c][net][S]; // ?: to eliminate warning
assign ins_o[r][c][net][E] = (c == x_max_p-1)
? hor_i[E][r][net]
: outs_i[r][(c == x_max_p-1) ? c : (c+1)][net][W]; // ?: for warning
assign ins_o[r][c][net][W] = (c == 0)
? hor_i[W][r][net]
: outs_i[r][c ? (c-1) :0][net][E]; // ?: to eliminate warning
end // block: c
end // block: r
for (c = 0; c < x_max_p; c=c+1)
begin: _c
assign ver_o[S][c][net] = outs_i[y_max_p-1][c][net][S];
assign ver_o[N][c][net] = outs_i[0 ][c][net][N];
end
end // block: _n
endmodule
| 6.9857 |
module bsg_ml605_chipscope (
input clk_i
, input [255:0] data_i
);
logic [35:0] control_lo;
bsg_ml605_chipscope_icon icon (.CONTROL0(control_lo));
bsg_ml605_chipscope_ila ila (
.CONTROL(control_lo)
, .CLK(clk_i)
, .TRIG0(data_i)
);
endmodule
| 6.727543 |
module bsg_ml605_chipscope_icon (
CONTROL0
) /* synthesis syn_black_box syn_noprune=1 */;
output [35 : 0] CONTROL0;
endmodule
| 6.727543 |
module bsg_ml605_chipscope_ila (
CONTROL,
CLK,
TRIG0
) /* synthesis syn_black_box syn_noprune=1 */;
input [35 : 0] CONTROL;
input CLK;
input [255 : 0] TRIG0;
endmodule
| 6.727543 |
module bsg_ml605_chipset_pcie_to_vta (
input clk_i
, input reset_i
// pcie in
, input pcie_valid_i
, input [31:0] pcie_data_i
, output pcie_yumi_o
// pcie out
, output pcie_valid_o
, output [31:0] pcie_data_o
, input pcie_ready_i
// vta in
, input vta_valid_i
, input [31:0] vta_data_i
, output vta_thanks_o
// vta out
, output vta_valid_o
, output [31:0] vta_data_o
, input vta_thanks_i
);
logic credit_available_lo;
logic [2:0] credit_cnt_lo;
logic fifo_ready_lo;
logic fifo_valid_lo;
logic [31:0] fifo_data_lo;
bsg_counter_up_down #(
.max_val_p (4)
, .init_val_p(4)
) credit_cnt (
.clk_i(clk_i)
, .reset_i(reset_i)
, .up_i(vta_thanks_i)
, .down_i(pcie_valid_i & credit_available_lo)
, .count_o(credit_cnt_lo)
);
assign vta_valid_o = pcie_valid_i;
assign vta_data_o = pcie_data_i;
assign credit_available_lo = (|credit_cnt_lo);
assign pcie_yumi_o = pcie_valid_i & credit_available_lo;
bsg_fifo_1r1w_large #(
.width_p(32)
, .els_p (8)
) fifo (
.clk_i(clk_i)
, .reset_i(reset_i)
// in
, .v_i(vta_valid_i)
, .data_i(vta_data_i)
, .ready_o(fifo_ready_lo)
// out
, .v_o(fifo_valid_lo)
, .data_o(fifo_data_lo)
, .yumi_i(fifo_valid_lo & pcie_ready_i)
);
assign vta_thanks_o = fifo_ready_lo & vta_valid_i;
assign pcie_valid_o = fifo_valid_lo;
assign pcie_data_o = fifo_data_lo;
endmodule
| 6.727543 |
module bsg_ml605_fmc_rx #(
parameter IODELAY_GRP = "IODELAY_FMC"
) (
input reset_i
, input clk_i
, input clk_200_mhz_i
, output clk_div_o
, output [87:0] data_o
, output cal_done_o
// fmc rx clk out
, output FMC_LPC_CLK0_M2C_P,
FMC_LPC_CLK0_M2C_N
// fmc rx clk in
, input FMC_LPC_CLK1_M2C_P,
FMC_LPC_CLK1_M2C_N
// fmc rx data in
, input FMC_LPC_LA00_CC_P,
FMC_LPC_LA00_CC_N
, input FMC_LPC_LA16_P,
FMC_LPC_LA16_N
, input FMC_LPC_LA15_P,
FMC_LPC_LA15_N
, input FMC_LPC_LA13_P,
FMC_LPC_LA13_N
, input FMC_LPC_LA11_P,
FMC_LPC_LA11_N
, input FMC_LPC_LA10_P,
FMC_LPC_LA10_N
, input FMC_LPC_LA14_P,
FMC_LPC_LA14_N
, input FMC_LPC_LA09_P,
FMC_LPC_LA09_N
, input FMC_LPC_LA04_P,
FMC_LPC_LA04_N
, input FMC_LPC_LA07_P,
FMC_LPC_LA07_N
, input FMC_LPC_LA08_P,
FMC_LPC_LA08_N
);
// idelay controller
logic idelayctrl_ready_lo;
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL idelayctrl_inst (
.RDY(idelayctrl_ready_lo)
, .REFCLK(clk_200_mhz_i)
, .RST(reset_i)
);
// reset
logic reset_lo;
assign reset_lo = reset_i | (~idelayctrl_ready_lo);
// clk out
logic oddr_lo;
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE")
, .INIT(1'b0)
, .SRTYPE("ASYNC")
) oddr_clk (
.Q (oddr_lo)
, .C (clk_i)
, .CE(1'b1)
, .D1(1'b1)
, .D2(1'b0)
, .R (1'b0)
, .S (1'b0)
);
OBUFDS #(
.IOSTANDARD("LVDS_25")
) obufds_clk (
.I (oddr_lo)
, .O (FMC_LPC_CLK0_M2C_P),
.OB(FMC_LPC_CLK0_M2C_N)
);
// clk in
logic clk_lo, clk_div_lo;
bsg_ml605_fmc_rx_clk #(
.IODELAY_GRP(IODELAY_GRP)
) rx_clk_inst (
.clk_p_i(FMC_LPC_CLK1_M2C_P),
.clk_n_i(FMC_LPC_CLK1_M2C_N)
, .clk_o(clk_lo)
, .clk_div_o(clk_div_lo)
);
assign clk_div_o = clk_div_lo;
// data in
logic [10:0] data_p_lo, data_n_lo;
assign data_p_lo = {
FMC_LPC_LA08_P
, FMC_LPC_LA07_P
, FMC_LPC_LA04_P
, FMC_LPC_LA09_P
, FMC_LPC_LA14_P
, FMC_LPC_LA10_P
, FMC_LPC_LA11_P
, FMC_LPC_LA13_P
, FMC_LPC_LA15_P
, FMC_LPC_LA16_P
, FMC_LPC_LA00_CC_P
};
assign data_n_lo = {
FMC_LPC_LA08_N
, FMC_LPC_LA07_N
, FMC_LPC_LA04_N
, FMC_LPC_LA09_N
, FMC_LPC_LA14_N
, FMC_LPC_LA10_N
, FMC_LPC_LA11_N
, FMC_LPC_LA13_N
, FMC_LPC_LA15_N
, FMC_LPC_LA16_N
, FMC_LPC_LA00_CC_N
};
bsg_ml605_fmc_rx_data #(
.IODELAY_GRP(IODELAY_GRP)
) rx_data_inst (
.clk_i(clk_lo)
, .clk_div_i(clk_div_lo)
, .reset_i(reset_lo)
, .data_p_i(data_p_lo),
.data_n_i(data_n_lo)
, .cal_done_o(cal_done_o)
, .data_o(data_o)
);
endmodule
| 6.911638 |
module bsg_ml605_fmc_rx_clk #(
parameter IODELAY_GRP = "IODELAY_FMC"
) (
input clk_p_i,
clk_n_i
, output clk_o
, output clk_div_o
);
logic ibufds_clk_lo, iodelay_clk_lo;
IBUFDS #(
.DIFF_TERM ("TRUE")
, .IOSTANDARD("LVDS_25")
) ibufds_clk_inst (
.I (clk_p_i),
.IB(clk_n_i)
, .O (ibufds_clk_lo)
);
(* IODELAY_GROUP = IODELAY_GRP *) IODELAYE1 #(
.CINVCTRL_SEL("FALSE")
, .DELAY_SRC("I")
, .HIGH_PERFORMANCE_MODE("TRUE")
, .IDELAY_TYPE("FIXED")
, .IDELAY_VALUE(0)
, .ODELAY_TYPE("FIXED")
, .ODELAY_VALUE(0)
, .REFCLK_FREQUENCY(200.0)
, .SIGNAL_PATTERN("CLOCK")
) iodelay_clk_inst (
.CNTVALUEOUT()
, .DATAOUT(iodelay_clk_lo)
, .C(1'b0)
, .CE(1'b0)
, .CINVCTRL(1'b0)
, .CLKIN(1'b0)
, .CNTVALUEIN(5'd0)
, .DATAIN(1'b0)
, .IDATAIN(ibufds_clk_lo)
, .INC(1'b0)
, .ODATAIN(1'b0)
, .RST(1'b0)
, .T(1'b1)
);
BUFIO bufio_clk_inst (
.I(iodelay_clk_lo)
, .O(clk_o)
);
BUFR #(
.BUFR_DIVIDE("4")
, .SIM_DEVICE ("VIRTEX6")
) bufr_clk_inst (
.O (clk_div_o)
, .CE (1'b1)
, .CLR(1'b0)
, .I (iodelay_clk_lo)
);
endmodule
| 6.911638 |
module bsg_ml605_fmc_rx_data_bitslip_ctrl (
input clk_i
, input reset_i
, input [7:0] data_i
, output bitslip_o
, output done_o
);
logic [7:0] data_pattern;
assign data_pattern = 8'h2C;
enum logic [2:0] {
IDLE = 3'b001
,BITSLIP = 3'b010
,DONE = 3'b100
}
c_state, n_state;
logic [1:0] cnt_r;
always_ff @(posedge clk_i)
if (reset_i == 1'b1 || c_state == BITSLIP) cnt_r <= 4'd0;
else if (c_state == IDLE) cnt_r <= cnt_r + 1;
// fsm
always_ff @(posedge clk_i) begin
if (reset_i == 1'b1) c_state <= IDLE;
else c_state <= n_state;
end
always_comb begin
n_state = c_state;
unique case (c_state)
IDLE:
if (cnt_r == 4'd3)
if (data_i == data_pattern) n_state = DONE;
else n_state = BITSLIP;
BITSLIP: n_state = IDLE;
DONE: n_state = DONE;
default: begin
end
endcase
end
assign bitslip_o = (c_state == BITSLIP) ? 1'b1 : 1'b0;
assign done_o = (c_state == DONE) ? 1'b1 : 1'b0;
endmodule
| 6.911638 |
module bsg_ml605_fmc_tx (
input clk_i
, input clk_div_i
, input reset_i
, input [87:0] data_i
, output cal_done_o
// fmc tx clk out
, output FMC_LPC_LA17_CC_P,
FMC_LPC_LA17_CC_N
// fmc tx data out
, output FMC_LPC_LA31_P,
FMC_LPC_LA31_N
, output FMC_LPC_LA33_P,
FMC_LPC_LA33_N
, output FMC_LPC_LA30_P,
FMC_LPC_LA30_N
, output FMC_LPC_LA32_P,
FMC_LPC_LA32_N
, output FMC_LPC_LA28_P,
FMC_LPC_LA28_N
, output FMC_LPC_LA25_P,
FMC_LPC_LA25_N
, output FMC_LPC_LA29_P,
FMC_LPC_LA29_N
, output FMC_LPC_LA26_P,
FMC_LPC_LA26_N
, output FMC_LPC_LA21_P,
FMC_LPC_LA21_N
, output FMC_LPC_LA27_P,
FMC_LPC_LA27_N
, output FMC_LPC_LA22_P,
FMC_LPC_LA22_N
);
// fmc tx clk out
bsg_ml605_fmc_tx_clk tx_clk_inst (
.clk_i (clk_i)
, .clk_p_o(FMC_LPC_LA17_CC_P),
.clk_n_o(FMC_LPC_LA17_CC_N)
);
// fmc tx data out
logic [10:0] data_p_lo, data_n_lo;
assign {FMC_LPC_LA22_P
,FMC_LPC_LA27_P
,FMC_LPC_LA21_P
,FMC_LPC_LA26_P
,FMC_LPC_LA29_P
,FMC_LPC_LA25_P
,FMC_LPC_LA28_P
,FMC_LPC_LA32_P
,FMC_LPC_LA30_P
,FMC_LPC_LA33_P
,FMC_LPC_LA31_P} = data_p_lo;
assign {FMC_LPC_LA22_N
,FMC_LPC_LA27_N
,FMC_LPC_LA21_N
,FMC_LPC_LA26_N
,FMC_LPC_LA29_N
,FMC_LPC_LA25_N
,FMC_LPC_LA28_N
,FMC_LPC_LA32_N
,FMC_LPC_LA30_N
,FMC_LPC_LA33_N
,FMC_LPC_LA31_N} = data_n_lo;
bsg_ml605_fmc_tx_data tx_data_inst (
.clk_i(clk_i)
, .clk_div_i(clk_div_i)
, .reset_i(reset_i)
, .data_i(data_i)
, .cal_done_o(cal_done_o)
, .data_p_o(data_p_lo),
.data_n_o(data_n_lo)
);
endmodule
| 6.911638 |
module bsg_ml605_fmc_tx_clk (
input clk_i
, output clk_p_o,
clk_n_o
);
logic oddr_lo;
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE")
, .INIT(1'b0)
, .SRTYPE("ASYNC")
) oddr_clk_inst (
.Q (oddr_lo)
, .C (clk_i)
, .CE(1'b1)
, .D1(1'b1)
, .D2(1'b0)
, .R (1'b0)
, .S (1'b0)
);
OBUFDS #(
.IOSTANDARD("LVDS_25")
) obufds_clk_inst (
.I (oddr_lo)
, .O (clk_p_o),
.OB(clk_n_o)
);
endmodule
| 6.911638 |
module bsg_ml605_fmc_tx_data (
input clk_i
, input clk_div_i
, input reset_i
, input [87:0] data_i
, output cal_done_o
, output [10:0] data_p_o,
data_n_o
);
logic [9:0] cnt_r;
always_ff @(posedge clk_div_i)
if (reset_i == 1'b1) cnt_r <= 10'd0;
else if (cnt_r < 10'd1023) cnt_r <= cnt_r + 1;
logic [87:0] data_cal_first_pattern;
logic [87:0] data_cal_second_pattern;
assign data_cal_first_pattern = {11{8'h2C}};
assign data_cal_second_pattern = {11{8'hF8}};
logic [87:0] swap_data_lo, data_lo;
always_comb
if (cnt_r < 10'd1008) data_lo = data_cal_first_pattern;
else if (cnt_r < 10'd1009) data_lo = data_cal_second_pattern;
else if (cnt_r < 10'd1023) data_lo = {11{8'h00}};
else data_lo = data_i;
assign swap_data_lo = ~data_lo; // swapped due to pcb routing
assign cal_done_o = (cnt_r == 10'd1023) ? 1'b1 : 1'b0;
logic [10:0] oserdes_data_lo;
logic [10:0] oserdes_slave_shiftout_1_lo, oserdes_slave_shiftout_2_lo;
genvar i;
generate
for (i = 0; i < 11; i++) begin
OSERDESE1 #(
.DATA_RATE_OQ("DDR")
, .DATA_RATE_TQ("SDR")
, .DATA_WIDTH(8)
, .DDR3_DATA(1)
, .INIT_OQ(1'b0)
, .INIT_TQ(1'b0)
, .INTERFACE_TYPE("DEFAULT")
, .ODELAY_USED(0)
, .SERDES_MODE("MASTER")
, .SRVAL_OQ(1'b0)
, .SRVAL_TQ(1'b0)
, .TRISTATE_WIDTH(1)
) oserdes_master_data_inst (
.SHIFTOUT1()
, .SHIFTOUT2()
, .TFB()
, .TQ()
, .OCBEXTEND()
, .OFB()
, .OQ(oserdes_data_lo[i])
, .CLK(clk_i)
, .CLKDIV(clk_div_i)
, .CLKPERF()
, .CLKPERFDELAY()
, .D1(swap_data_lo[(8*i)+0])
, .D2(swap_data_lo[(8*i)+1])
, .D3(swap_data_lo[(8*i)+2])
, .D4(swap_data_lo[(8*i)+3])
, .D5(swap_data_lo[(8*i)+4])
, .D6(swap_data_lo[(8*i)+5])
, .OCE(1'b1)
, .ODV(1'b0)
, .RST(reset_i)
, .SHIFTIN1(oserdes_slave_shiftout_1_lo[i])
, .SHIFTIN2(oserdes_slave_shiftout_2_lo[i])
, .T1(1'b0)
, .T2(1'b0)
, .T3(1'b0)
, .T4(1'b0)
, .TCE(1'b0)
, .WC(1'b0)
);
OSERDESE1 #(
.DATA_RATE_OQ("DDR")
, .DATA_RATE_TQ("SDR")
, .DATA_WIDTH(8)
, .DDR3_DATA(1)
, .INIT_OQ(1'b0)
, .INIT_TQ(1'b0)
, .INTERFACE_TYPE("DEFAULT")
, .ODELAY_USED(0)
, .SERDES_MODE("SLAVE")
, .SRVAL_OQ(1'b0)
, .SRVAL_TQ(1'b0)
, .TRISTATE_WIDTH(1)
) oserdes_slave_data_inst (
.SHIFTOUT1(oserdes_slave_shiftout_1_lo[i])
, .SHIFTOUT2(oserdes_slave_shiftout_2_lo[i])
, .TFB()
, .TQ()
, .OCBEXTEND()
, .OFB()
, .OQ()
, .CLK(clk_i)
, .CLKDIV(clk_div_i)
, .CLKPERF()
, .CLKPERFDELAY()
, .D1()
, .D2()
, .D3(swap_data_lo[(8*i)+6])
, .D4(swap_data_lo[(8*i)+7])
, .D5()
, .D6()
, .OCE(1'b1)
, .ODV(1'b0)
, .RST(reset_i)
, .SHIFTIN1(1'b0)
, .SHIFTIN2(1'b0)
, .T1(1'b0)
, .T2(1'b0)
, .T3(1'b0)
, .T4(1'b0)
, .TCE(1'b0)
, .WC(1'b0)
);
OBUFDS #(
.IOSTANDARD("LVDS_25")
) obufds_data_inst (
.I (oserdes_data_lo[i])
, .O (data_p_o[i]),
.OB(data_n_o[i])
);
end
endgenerate
endmodule
| 6.911638 |
module bsg_ml605_pcie_async_fifo #(
parameter channel_p = 2
)
// core clk
(
input core_clk_i
// core reset
, input core_reset_i
// core data in
, input [channel_p - 1 : 0] core_valid_i
, input [31:0] core_data_i[channel_p - 1 : 0]
, output [channel_p - 1 : 0] core_ready_o
// core data out
, output [channel_p - 1 : 0] core_valid_o
, output [31:0] core_data_o[channel_p - 1 : 0]
, input [channel_p - 1 : 0] core_yumi_i
// pcie clk
, input pcie_clk_i
// pcie reset
, input pcie_reset_i
// pcie data in
, input [channel_p - 1 : 0] pcie_valid_i
, input [32*channel_p - 1 : 0] pcie_data_i
, output [channel_p - 1 : 0] pcie_ready_o
// pcie data out
, output [channel_p - 1 : 0] pcie_valid_o
, output [32*channel_p - 1 : 0] pcie_data_o
, input [channel_p - 1 : 0] pcie_ready_i
);
logic [channel_p - 1 : 0] fi_full_lo;
logic [channel_p - 1 : 0] fo_valid_lo;
logic [channel_p - 1 : 0] fo_full_lo;
logic [channel_p - 1 : 0] fi_valid_lo;
logic [31:0] fi_data_lo[channel_p - 1 : 0];
logic [channel_p - 1 : 0] btf_ready_lo;
genvar i;
generate
for (i = 0; i < channel_p; i = i + 1) begin
bsg_async_fifo #(
.lg_size_p(4)
, .width_p (32)
) fi_inst
// pcie data in
(
.w_clk_i (pcie_clk_i)
, .w_reset_i(pcie_reset_i)
, .w_enq_i (~fi_full_lo[i] & pcie_valid_i[i])
, .w_data_i (pcie_data_i[i*32+31 : i*32])
, .w_full_o (fi_full_lo[i])
// core data out
, .r_clk_i (core_clk_i)
, .r_reset_i(core_reset_i)
, .r_deq_i (fi_valid_lo[i] & btf_ready_lo[i])
, .r_data_o (fi_data_lo[i])
, .r_valid_o(fi_valid_lo[i])
);
assign pcie_ready_o[i] = ~fi_full_lo[i];
bsg_two_fifo #(
.width_p(32)
) btf_inst (
.clk_i(core_clk_i)
, .reset_i(core_reset_i)
// in
, .v_i(fi_valid_lo[i])
, .data_i(fi_data_lo[i])
, .ready_o(btf_ready_lo[i])
// out
, .v_o(core_valid_o[i])
, .data_o(core_data_o[i])
, .yumi_i(core_yumi_i[i])
);
bsg_async_fifo #(
.lg_size_p(4)
, .width_p (32)
) fo_inst
// core data in
(
.w_clk_i (core_clk_i)
, .w_reset_i(core_reset_i)
, .w_enq_i (~fo_full_lo[i] & core_valid_i[i])
, .w_data_i (core_data_i[i])
, .w_full_o (fo_full_lo[i])
// pcie data out
, .r_clk_i (pcie_clk_i)
, .r_reset_i(pcie_reset_i)
, .r_deq_i (fo_valid_lo[i] & pcie_ready_i[i])
, .r_data_o (pcie_data_o[i*32+31 : i*32])
, .r_valid_o(fo_valid_lo[i])
);
assign core_ready_o[i] = ~fo_full_lo[i];
assign pcie_valid_o[i] = fo_valid_lo[i];
end
endgenerate
endmodule
| 7.59322 |
module bsg_ml605_pio_ep_fifo #(
parameter I_WIDTH = 17
, parameter A_WIDTH = 10
, parameter LG_DEPTH = 3
) (
input clk
, input [I_WIDTH + A_WIDTH - 1:0] din
, input enque
, input deque
, input clear
, output [I_WIDTH + A_WIDTH - 1:0] dout
, output empty
, output full
, output almost_full
, output valid
);
// Some storage
reg [I_WIDTH + A_WIDTH - 1:0] storage[(2**LG_DEPTH)-1:0];
// One read pointer, one write pointer;
reg [LG_DEPTH-1:0] rptr_r, wptr_r;
// Lights up if the fifo was used incorrectly
reg error_r;
assign full = ((wptr_r + 1'b1) == rptr_r);
assign almost_full = ((wptr_r + 2'b10) == rptr_r) | full;
assign empty = (wptr_r == rptr_r);
assign valid = !empty;
assign dout = storage[rptr_r];
always @(posedge clk) if (enque) storage[wptr_r] <= din;
always @(posedge clk) begin
if (clear) begin
rptr_r <= 0;
wptr_r <= 0;
error_r <= 1'b0;
end else begin
rptr_r <= rptr_r + deque;
wptr_r <= wptr_r + enque;
error_r <= error_r | (full & enque) | (empty & deque);
end
end
endmodule
| 6.602304 |
module bsg_ml605_pio_ep_reset_ctrl #(
parameter reset_register_addr_p = "inv"
, parameter reset_register_data_p = "inv"
)
// clk
(
input clk_i
// reset
, input reset_i
// write port
, input wr_en_i
, input [10:0] wr_addr_i
, input [31:0] wr_data_i
// reset out
, output reset_o
);
logic start_lo;
assign start_lo = ( wr_en_i == 1'b1
&& wr_addr_i[8:0] == reset_register_addr_p
&& wr_data_i == reset_register_data_p)? 1'b1 : 1'b0;
enum logic [1:0] {
IDLE = 2'b01
, RESET = 2'b10
}
c_state, n_state;
always_ff @(posedge clk_i)
if (reset_i == 1'b1) c_state <= IDLE;
else c_state <= n_state;
logic [9:0] cnt_r;
always_ff @(posedge clk_i)
if (reset_i == 1'b1 || c_state == IDLE) cnt_r <= {10{1'b0}};
else cnt_r <= cnt_r + 1;
localparam logic [9:0] reset_cycles_lp = 10'd1023;
always_comb begin
n_state = c_state;
unique case (c_state)
IDLE: if (start_lo == 1'b1) n_state = RESET;
RESET: if (cnt_r == reset_cycles_lp) n_state = IDLE;
default: begin
end
endcase
end
assign reset_o = (c_state == RESET) ? 1'b1 : 1'b0;
endmodule
| 6.602304 |
module bsg_mul #(parameter `BSG_INV_PARAM(width_p)
,harden_p=1
)
(input [width_p-1:0] x_i
, input [width_p-1:0] y_i
, input signed_i
, output [width_p*2-1:0] z_o
);
bsg_mul_pipelined #(.width_p (width_p )
,.pipeline_p(0 )
,.harden_p (harden_p)
) bmp
(.clock_i(1'b0)
,.en_i(1'b0)
,.x_i
,.y_i
,.signed_i
,.z_o
);
endmodule
| 7.341023 |
module for use with HardFloat's mulAddRecFN for
// easy absorption of pipeline stages by the DSPs that get
// synthesised in some FPGAs. This helps in retiming the
// paths in FPGA implementations as only immediate registers
// are absorbed, and global retiming does not seem to do this.
//
// For Zynq 7020, pipeline_p = 3
`include "bsg_defines.v"
module bsg_mul_add_unsigned #(
parameter `BSG_INV_PARAM(width_a_p)
,parameter `BSG_INV_PARAM(width_b_p)
,parameter width_c_p = width_a_p + width_b_p
,parameter width_o_p = `BSG_SAFE_CLOG2( ((1 << width_a_p) - 1) * ((1 << width_b_p) - 1) +
((1 << width_c_p)-1) + 1 )
,parameter pipeline_p = 0
) (
input clk_i
,input [width_a_p-1 : 0] a_i
,input [width_b_p-1 : 0] b_i
,input [width_c_p-1 : 0] c_i
,output [width_o_p-1 : 0] o
);
initial assert (pipeline_p > 2) else $warning ("%m: pipeline_p is set quite low; most likely frequency will be impacted");
localparam pre_pipeline_lp = pipeline_p > 2 ? 1 : 0;
localparam post_pipeline_lp = pipeline_p > 2 ? pipeline_p -1 : pipeline_p; //for excess
wire [width_a_p-1:0] a_r;
wire [width_b_p-1:0] b_r;
wire [width_c_p-1:0] c_r;
bsg_dff_chain #(width_a_p + width_b_p + width_c_p, pre_pipeline_lp)
pre_mul_add (
.clk_i(clk_i)
,.data_i({a_i, b_i, c_i})
,.data_o({a_r, b_r, c_r})
);
wire [width_o_p-1:0] o_r = a_r * b_r + c_r;
bsg_dff_chain #(width_o_p, post_pipeline_lp)
post_mul_add (
.clk_i(clk_i)
,.data_i(o_r)
,.data_o(o)
);
endmodule
| 6.836922 |
module bsg_mul_and_csa_block_hard #(parameter [31:0] blocks_p=1
)
( input [blocks_p-1:0] x_i
, input [blocks_p-1:0] y_i
, input [blocks_p-1:0] z_and1_i
, input [blocks_p-1:0] z_and2_i
, output [blocks_p-1:0] c_o
, output [blocks_p-1:0] s_o
);
`bsg_mul_and_csa_gen_macro(5)
else `bsg_mul_and_csa_gen_macro(6)
else `bsg_mul_and_csa_gen_macro(7)
else `bsg_mul_and_csa_gen_macro(8)
else initial assert(blocks_p==-1) else $error("unhandled case %m");
endmodule
| 6.587043 |
module bsg_mul_array #(parameter `BSG_INV_PARAM(width_p), `BSG_INV_PARAM(pipeline_p))
(
input clk_i
, input rst_i
, input v_i
, input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output logic [(width_p*2)-1:0] o
);
// connections between rows
logic [width_p-1:0] a_r [width_p-3:0];
logic [width_p-1:0] b_r [width_p-3:0];
logic [width_p-1:0] s_r [width_p-2:0];
logic c_r [width_p-2:0];
logic [width_p-1:0] prod_accum [width_p-2:0];
// first partial product
logic [width_p-1:0] pp0;
bsg_and #(.width_p(width_p)) and0 (
.a_i(a_i)
, .b_i({width_p{b_i[0]}})
, .o(pp0)
);
genvar i;
for (i = 0; i < width_p-1; i++) begin
if (i == 0) begin
bsg_mul_array_row #(.width_p(width_p), .row_idx_p(i), .pipeline_p(pipeline_p[i]))
first_row (
.clk_i(clk_i)
,.rst_i(rst_i)
,.v_i(v_i)
,.a_i(a_i)
,.b_i(b_i)
,.s_i(pp0)
,.c_i(1'b0)
,.prod_accum_i(pp0[0])
,.a_o(a_r[i])
,.b_o(b_r[i])
,.s_o(s_r[i])
,.c_o(c_r[i])
,.prod_accum_o(prod_accum[i][i+1:0])
);
end
else if (i == width_p-2) begin
bsg_mul_array_row #(.width_p(width_p), .row_idx_p(i), .pipeline_p(pipeline_p[i]))
last_row (
.clk_i(clk_i)
,.rst_i(rst_i)
,.v_i(v_i)
,.a_i(a_r[i-1])
,.b_i(b_r[i-1])
,.s_i(s_r[i-1])
,.c_i(c_r[i-1])
,.prod_accum_i(prod_accum[i-1][i:0])
,.a_o() // no need to connect
,.b_o() // no need to connect
,.s_o(s_r[i])
,.c_o(c_r[i])
,.prod_accum_o(prod_accum[i])
);
end
else begin
bsg_mul_array_row #(.width_p(width_p), .row_idx_p(i), .pipeline_p(pipeline_p[i]))
mid_row (
.clk_i(clk_i)
,.rst_i(rst_i)
,.v_i(v_i)
,.a_i(a_r[i-1])
,.b_i(b_r[i-1])
,.s_i(s_r[i-1])
,.c_i(c_r[i-1])
,.prod_accum_i(prod_accum[i-1][i:0])
,.a_o(a_r[i])
,.b_o(b_r[i])
,.s_o(s_r[i])
,.c_o(c_r[i])
,.prod_accum_o(prod_accum[i][i+1:0])
);
end
end
assign o[(2*width_p)-1] = c_r[width_p-2];
assign o[(2*width_p)-2:width_p-1] = s_r[width_p-2];
assign o[width_p-2:0] = prod_accum[width_p-2][width_p-2:0];
endmodule
| 6.627847 |
module bsg_mul_array_row #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(row_idx_p)
, parameter `BSG_INV_PARAM(pipeline_p))
(
input clk_i
, input rst_i
, input v_i
, input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, input [width_p-1:0] s_i
, input c_i
, input [row_idx_p:0] prod_accum_i
, output logic [width_p-1:0] a_o
, output logic [width_p-1:0] b_o
, output logic [width_p-1:0] s_o
, output logic c_o
, output logic [row_idx_p+1:0] prod_accum_o
);
// partial product
logic [width_p-1:0] pp;
logic [width_p-1:0] ps;
logic pc;
bsg_and #(.width_p(width_p)) and0 (
.a_i(a_i)
,.b_i({width_p{b_i[row_idx_p+1]}})
,.o(pp)
);
bsg_adder_ripple_carry #(.width_p(width_p)) adder0 (
.a_i(pp)
,.b_i({c_i, s_i[width_p-1:1]})
,.s_o(ps)
,.c_o(pc)
);
// pipeline registers
logic [width_p-1:0] a_r;
logic [width_p-1:0] b_r;
logic [width_p-1:0] s_r;
logic c_r;
logic [row_idx_p+1:0] prod_accum_r;
// pipeline next values
logic [width_p-1:0] a_n;
logic [width_p-1:0] b_n;
logic [width_p-1:0] s_n;
logic c_n;
logic [row_idx_p+1:0] prod_accum_n;
if (pipeline_p) begin
always_ff @ (posedge clk_i) begin
if (rst_i) begin
a_r <= 0;
b_r <= 0;
s_r <= 0;
c_r <= 0;
prod_accum_r <= 0;
end
else begin
a_r <= a_n;
b_r <= b_n;
s_r <= s_n;
c_r <= c_n;
prod_accum_r <= prod_accum_n;
end
end
always_comb begin
if (v_i) begin
a_n = a_i;
b_n = b_i;
s_n = ps;
c_n = pc;
prod_accum_n = {ps[0], prod_accum_i};
end
else begin
a_n = a_r;
b_n = b_r;
s_n = s_r;
c_n = c_r;
prod_accum_n = prod_accum_r;
end
a_o = a_r;
b_o = b_r;
s_o = s_r;
c_o = c_r;
prod_accum_o = prod_accum_r;
end
end
else begin
always_comb begin
a_o = a_i;
b_o = b_i;
s_o = ps;
c_o = pc;
prod_accum_o = {ps[0], prod_accum_i};
end
end
endmodule
| 6.627847 |
module bsg_mul_comp42 (
input [3:0] i // 0-2: early; 3: middle
, input cr_i // middle
, output cl_o // middle
, output c_o // late
, output s_o // late
);
wire tmp;
bsg_mul_csa csa_1 (
.x_i(i[0]),
.y_i(i[1]),
.z_i(i[2]),
.c_o(cl_o),
.s_o(tmp)
);
bsg_mul_csa csa_2 (
.x_i(i[3]),
.y_i(tmp),
.z_i(cr_i),
.c_o(c_o),
.s_o(s_o)
);
endmodule
| 6.614909 |
module bsg_mul_comp42_rep #(parameter `BSG_INV_PARAM(blocks_p))
(input [3:0][blocks_p-1:0] i
,input cr_i
,output cl_o
,output [blocks_p-1:0] c_o
,output [blocks_p-1:0] s_o
);
`bsg_mul_comp42_gen_macro(5)
else `bsg_mul_comp42_gen_macro(6)
else `bsg_mul_comp42_gen_macro(7)
else `bsg_mul_comp42_gen_macro(8)
else
initial assert(blocks_p==-1) else $error("all case should be handled by this module %m");
endmodule
| 6.614909 |
module bsg_mul_SDN #(
parameter width_p = 16,
parameter rows_lp = width_p / 2 + 1
) (
input [width_p-1:0] x_i
, input signed_i
, output [rows_lp-1:0][2:0] SDN_o
);
// we do not need to signed-extend temp_x on a
// signed multiply -- it just works out that way.
wire [width_p+3-1:0] temp_x = {2'b0, x_i, 1'b0};
genvar i;
for (i = 0; i < rows_lp; i = i + 1) begin : rof
wire [2:0] trip;
if (i != rows_lp - 1) begin : fi
assign trip = temp_x[2*i+2:2*i];
end else begin : fi
// cancel out last row of computation for signed values
// by setting N, S and D to 0.
assign trip = temp_x[2*i+2:2*i] & ~{3{signed_i}};
end
assign SDN_o[i][0] = trip[2];
assign SDN_o[i][1] = ((&trip[1:0]) & ~trip[2]) | (~(|trip[1:0]) & trip[2]);
assign SDN_o[i][2] = trip[0] ^ trip[1];
end
endmodule
| 7.265123 |
module bsg_mul_csa (
input x_i
, input y_i
, input z_i
, output c_o
, output s_o
);
assign {c_o, s_o} = x_i + y_i + z_i;
endmodule
| 7.036575 |
module bsg_dff_en_rep_rep #(
parameter blocks_p = 0
, width_p = 0
, group_vec_p = 0
, harden_p = 1
) (
input clk_i
, input en_i
, input [width_p-1:0] data_i
, output [width_p-1:0] data_o
);
genvar j;
for (j = 0; j < blocks_p; j = j + 1) begin : rof
localparam group_end_lp = (group_vec_p >> ((j + 1) << 3)) & 8'hFF;
localparam group_start_lp = (group_vec_p >> ((j) << 3)) & 8'hFF;
localparam [31:0] blocks_lp = group_end_lp - group_start_lp;
bsg_dff_en #(
.width_p (blocks_lp),
.harden_p(harden_p)
) bde (
.clk_i
, .en_i
, .data_i(data_i[group_end_lp-1:group_start_lp])
, .data_o(data_o[group_end_lp-1:group_start_lp])
);
end
endmodule
| 6.610378 |
module bsg_mul_comp42_rep_rep #(
parameter blocks_p = 0
, width_p = 0
, group_vec_p = 0
, harden_p = 1
)
// we do this so that it is easy to combine vectors of results from blocks
(
input [3:0][width_p-1:0] i
, input cr_i
, output cl_o
, output [width_p-1:0] c_o
, output [width_p-1:0] s_o
);
genvar j;
wire [blocks_p:0] carries;
for (j = 0; j < blocks_p; j = j + 1) begin : rof
localparam group_end_lp = (group_vec_p >> ((j + 1) << 3)) & 8'hFF;
localparam group_start_lp = (group_vec_p >> ((j) << 3)) & 8'hFF;
wire [3:0][group_end_lp-group_start_lp-1:0] t;
assign t[0] = i[0][group_end_lp-1:group_start_lp];
assign t[1] = i[1][group_end_lp-1:group_start_lp];
assign t[2] = i[2][group_end_lp-1:group_start_lp];
assign t[3] = i[3][group_end_lp-1:group_start_lp];
bsg_mul_comp42_rep #(
.blocks_p(group_end_lp - group_start_lp)
) cr (
.i(t)
, .cr_i(carries[j])
, .cl_o(carries[j+1])
, .c_o(c_o[group_end_lp-1:group_start_lp])
, .s_o(s_o[group_end_lp-1:group_start_lp])
);
end
assign cl_o = carries[blocks_p];
assign carries[0] = cr_i;
endmodule
| 6.614909 |
module bsg_mul_B4B_rep_rep
#(parameter blocks_p = 1
, parameter width_p = 0
, parameter group_vec_p = 0
, parameter `BSG_INV_PARAM(y_p )
, parameter y_size_p = 16
, parameter S_above_vec_p = 0
, parameter dot_bar_vec_p = 0
, parameter B_vec_p = 0
, parameter one_vec_p = 0
, parameter harden_p = 1'b0
)
( input [4:0][2:0] SDN_i
, input cr_i
, input [y_size_p-1:0] y_i
, input signed_i
, output cl_o
, output [width_p-1:0] c_o
, output [width_p-1:0] s_o
);
genvar j;
wire [blocks_p:0] carries;
for (j = 0; j < blocks_p; j=j+1)
begin: rof
localparam group_end_lp = (group_vec_p >> ((j+1) << 3 )) & 8'hFF;
localparam group_start_lp = (group_vec_p >> ((j ) << 3 )) & 8'hFF;
localparam [31:0] blocks_lp = group_end_lp-group_start_lp;
bsg_mul_B4B_rep
#(.blocks_p(blocks_lp)
,.y_p (y_p+group_start_lp )
,.y_size_p (y_size_p )
,.S_above_vec_p(S_above_vec_p[4*group_end_lp-1:4*group_start_lp])
,.dot_bar_vec_p(dot_bar_vec_p[4*group_end_lp-1:4*group_start_lp])
,.B_vec_p (B_vec_p [4*group_end_lp-1:4*group_start_lp])
,.one_vec_p (one_vec_p [4*group_end_lp-1:4*group_start_lp])
,.harden_p (harden_p)
) br
(.SDN_i
,.cr_i(carries[j])
,.y_i
,.signed_i
,.cl_o(carries[j+1])
,.c_o(c_o[group_end_lp-1:group_start_lp])
,.s_o(s_o[group_end_lp-1:group_start_lp])
);
end
assign carries[0] = cr_i;
assign cl_o = carries[blocks_p];
endmodule
| 8.780484 |
module bsg_mul_B4B_rep #(parameter [31:0] blocks_p=1
,parameter `BSG_INV_PARAM(y_p )
// size is required so VCS does not freak out
,parameter [31:0] y_size_p = 16
,parameter S_above_vec_p=0
,parameter dot_bar_vec_p=0
,parameter B_vec_p=0
,parameter one_vec_p=0
,parameter harden_p=0)
( input [4:0][2:0] SDN_i
, input cr_i
, input [y_size_p-1:0] y_i
, input signed_i
, output cl_o
, output [blocks_p-1:0] c_o
, output [blocks_p-1:0] s_o
);
genvar i;
initial assert (y_p != -1) else $error("invalid input for y_p");
localparam y_shift_p = 2+7;
// sign extend if signed value
// wire [16+8:-2-7] y_pad = { 8'b0, y_i, 9'b0 };
wire [y_size_p+8+y_shift_p:0] y_pad = { { 8 { y_i[y_size_p-1] & signed_i }}, y_i, 9'b0 };
wire [blocks_p-1:0][3:0][1:0] y_in;
for (i = 0; i < blocks_p; i=i+1)
begin: wiring
// the localparams are required to overcome some absurdity in VCS
// where it is using >> 32 bit values to represent the constants
// and then they are not correctly interpreted as small signed numbers
localparam [31:0] x7 = y_shift_p+y_p+i-6;
localparam [31:0] x6 = y_shift_p+y_p+i-6-1;
localparam [31:0] x5 = y_shift_p+y_p+i-4;
localparam [31:0] x4 = y_shift_p+y_p+i-4-1;
localparam [31:0] x3 = y_shift_p+y_p+i-2;
localparam [31:0] x2 = y_shift_p+y_p+i-2-1;
localparam [31:0] x1 = y_shift_p+y_p+i;
localparam [31:0] x0 = y_shift_p+y_p+i-1;
/*
wire [3:0][1:0] y_in = {
{y_pad[x7],y_pad[x6]}
, {y_pad[x5],y_pad[x4]}
, {y_pad[x3],y_pad[x2]}
, {y_pad[x1 ],y_pad[x0]}
};
*/
assign y_in[i][0] = {y_pad[x1], y_pad[x0]};
assign y_in[i][1] = {y_pad[x3], y_pad[x2]};
assign y_in[i][2] = {y_pad[x5], y_pad[x4]};
assign y_in[i][3] = {y_pad[x7], y_pad[x6]};
end // block: rof
// this little nugget is what we replace using rp groups
bsg_mul_booth_4_block_rep #(.blocks_p (blocks_p)
,.S_above_vec_p(S_above_vec_p)
,.dot_bar_vec_p(dot_bar_vec_p)
,.B_vec_p (B_vec_p)
,.one_vec_p (one_vec_p)
) bb4bh
(.SDN_i
,.cr_i
,.y_vec_i(y_in)
,.cl_o
,.c_o
,.s_o
);
endmodule
| 8.780484 |
module bsg_mul_green_booth_dots #(parameter `BSG_INV_PARAM(width_p)
, harden_p=0
, blocks_p="inv"
, group_vec_p="inv"
)
( input [1:0][2:0] SDN_i
, input [width_p-1:0] y_i
, output [width_p+2-1:0] dot_o
);
wire [width_p+2-1:0] y_pad = { y_i, 2'b00 };
genvar i,j;
for (j = 0; j < blocks_p; j=j+1)
begin: blk
localparam group_end_lp = (group_vec_p >> ((j+1) << 3 )) & 8'hFF;
localparam group_start_lp = (group_vec_p >> ((j ) << 3 )) & 8'hFF;
localparam [31:0] blocks_lp = group_end_lp-group_start_lp;
// y_i does not need to be signed extended
// this is the last row, after all
// which should not exist for signed version.
if (j != 0 && harden_p)
begin: macro
bsg_and #(.width_p(blocks_lp)
,.harden_p(harden_p)
) ba
(.a_i ({blocks_lp { SDN_i[1][2] } } )
,.b_i (y_pad[group_start_lp+:blocks_lp])
,.o (dot_o[group_start_lp+:blocks_lp])
);
end
else
begin: notmacro
for (i = 0; i < blocks_lp; i++)
begin: b
if (j == 0 && i == 0)
begin :fi
assign dot_o[0] = SDN_i[0][0];
end
else
if (j == 0 && i == 1)
begin : fi
assign dot_o[1] = 1'b0;
end
else
begin: fi
// assign dot_o[i] = bsg_booth_dot(SDN_i[1], y_pad[i-1], y_pad[i-2]);
// note: we do not need a dot here; as only S value may be set; an AND is sufficient.
// fixme: update the diagram.
assign dot_o[group_start_lp+i] = SDN_i[1][2] & y_pad[group_start_lp+i];
end
end // block: rof
end // block: notmacro
end // block: rof
endmodule
| 7.102958 |
module bsg_mul_synth #(parameter `BSG_INV_PARAM(width_p))
(
input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output logic [(2*width_p)-1:0] o
);
assign o = a_i * b_i;
endmodule
| 6.718167 |
module bsg_murn_converter
#(parameter `BSG_INV_PARAM(nodes_p)
, parameter `BSG_INV_PARAM(ring_width_p)
)
(
input clk_i
, input [nodes_p-1:0] reset_i
// to murn node
, input [nodes_p-1:0] v_i
, output [nodes_p-1:0] ready_o
, input [ring_width_p-1:0] data_i [nodes_p-1:0]
, output [nodes_p-1:0] switch_2_blockValid
, input [nodes_p-1:0] switch_2_blockRetry
, output [ring_width_p-1:0] switch_2_blockData [nodes_p-1:0]
// from murn node
, input [nodes_p-1:0] block_2_switchValid
, output [nodes_p-1:0] block_2_switchRetry
, input [ring_width_p-1:0] block_2_switchData [nodes_p-1:0]
, output [nodes_p-1:0] v_o
, input [nodes_p-1:0] yumi_i
, output [ring_width_p-1:0] data_o [nodes_p-1:0]
);
bsg_flow_convert #(.width_p(nodes_p)
,.send_v_and_ready_p(1)
,.recv_v_and_retry_p(1)
) s2b
(.v_i (v_i)
,.fc_o(ready_o)
,.v_o(switch_2_blockValid)
,.fc_i(switch_2_blockRetry)
);
assign switch_2_blockData = data_i;
//
// the ALU module's valid out
// depends on the incoming retry (e.g. retry->valid)
// but we need to interface to a valid/yumi.
// which means we need a 2-element fifo.
//
wire [nodes_p-1:0] block_2_switchValid_2;
wire [nodes_p-1:0] block_2_switchReady;
bsg_flow_convert #(.width_p(nodes_p)
,.send_retry_then_v_p(1)
,.recv_v_and_ready_p(1)
) b2s
(.v_i (block_2_switchValid)
,.fc_o(block_2_switchRetry)
,.v_o(block_2_switchValid_2)
,.fc_i(block_2_switchReady)
);
genvar i;
for (i = 0; i < nodes_p; i++)
begin : n
bsg_two_fifo #(.width_p(ring_width_p))
twofer (.clk_i(clk_i)
,.reset_i(reset_i[i])
,.ready_o(block_2_switchReady[i])
,.data_i (block_2_switchData[i] )
,.v_i (block_2_switchValid[i])
,.v_o (v_o[i] )
,.data_o (data_o[i])
,.yumi_i (yumi_i[i] )
);
end
endmodule
| 9.902687 |
module bsg_mux #(
parameter width_p = "inv"
, els_p = 1
, harden_p = 0
, balanced_p = 0
, lg_els_lp = `BSG_SAFE_CLOG2(els_p)
) (
input [els_p-1:0][width_p-1:0] data_i
, input [lg_els_lp-1:0] sel_i
, output [width_p-1:0] data_o
);
if (els_p == 1) begin
assign data_o = data_i;
wire unused = sel_i;
end else assign data_o = data_i[sel_i];
// synopsys translate_off
initial
assert (balanced_p == 0)
else $error("%m warning: synthesizable implementation of bsg_mux does not support balanced_p");
// synopsys translate_on
endmodule
| 7.250766 |
module bsg_mux2_gatestack #(
width_p = "inv",
harden_p = 1
) (
input [width_p-1:0] i0
, input [width_p-1:0] i1
, input [width_p-1:0] i2
, output [width_p-1:0] o
);
initial $display("%m: warning module not actually hardened.");
genvar j;
for (j = 0; j < width_p; j = j + 1) begin
assign o[j] = i2[j] ? i1[j] : i0[j];
end
endmodule
| 6.945715 |
module bsg_mux2_gatestack_width_p2_harden_p1 (
i0,
i1,
i2,
o
);
input [1:0] i0;
input [1:0] i1;
input [1:0] i2;
output [1:0] o;
wire [1:0] o;
wire N0, N1, N2, N3;
assign o[0] = (N0) ? i1[0] : (N2) ? i0[0] : 1'b0;
assign N0 = i2[0];
assign o[1] = (N1) ? i1[1] : (N3) ? i0[1] : 1'b0;
assign N1 = i2[1];
assign N2 = ~i2[0];
assign N3 = ~i2[1];
endmodule
| 6.945715 |
module bsg_mux2_gatestack_width_p3_harden_p1 (
i0,
i1,
i2,
o
);
input [2:0] i0;
input [2:0] i1;
input [2:0] i2;
output [2:0] o;
wire [2:0] o;
wire N0, N1, N2, N3, N4, N5;
assign o[0] = (N0) ? i1[0] : (N3) ? i0[0] : 1'b0;
assign N0 = i2[0];
assign o[1] = (N1) ? i1[1] : (N4) ? i0[1] : 1'b0;
assign N1 = i2[1];
assign o[2] = (N2) ? i1[2] : (N5) ? i0[2] : 1'b0;
assign N2 = i2[2];
assign N3 = ~i2[0];
assign N4 = ~i2[1];
assign N5 = ~i2[2];
endmodule
| 6.945715 |
module bsg_mux2_gatestack_width_p9_harden_p1 (
i0,
i1,
i2,
o
);
input [8:0] i0;
input [8:0] i1;
input [8:0] i2;
output [8:0] o;
wire [8:0] o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17;
assign o[0] = (N0) ? i1[0] : (N9) ? i0[0] : 1'b0;
assign N0 = i2[0];
assign o[1] = (N1) ? i1[1] : (N10) ? i0[1] : 1'b0;
assign N1 = i2[1];
assign o[2] = (N2) ? i1[2] : (N11) ? i0[2] : 1'b0;
assign N2 = i2[2];
assign o[3] = (N3) ? i1[3] : (N12) ? i0[3] : 1'b0;
assign N3 = i2[3];
assign o[4] = (N4) ? i1[4] : (N13) ? i0[4] : 1'b0;
assign N4 = i2[4];
assign o[5] = (N5) ? i1[5] : (N14) ? i0[5] : 1'b0;
assign N5 = i2[5];
assign o[6] = (N6) ? i1[6] : (N15) ? i0[6] : 1'b0;
assign N6 = i2[6];
assign o[7] = (N7) ? i1[7] : (N16) ? i0[7] : 1'b0;
assign N7 = i2[7];
assign o[8] = (N8) ? i1[8] : (N17) ? i0[8] : 1'b0;
assign N8 = i2[8];
assign N9 = ~i2[0];
assign N10 = ~i2[1];
assign N11 = ~i2[2];
assign N12 = ~i2[3];
assign N13 = ~i2[4];
assign N14 = ~i2[5];
assign N15 = ~i2[6];
assign N16 = ~i2[7];
assign N17 = ~i2[8];
endmodule
| 6.945715 |
module bsg_muxi2_gatestack #(
width_p = "inv",
harden_p = 1
) (
input [width_p-1:0] i0
, input [width_p-1:0] i1
, input [width_p-1:0] i2
, output [width_p-1:0] o
);
initial $display("%m: warning module not actually hardened.");
genvar j;
for (j = 0; j < width_p; j = j + 1) begin
assign o[j] = ~(i2[j] ? i1[j] : i0[j]);
end
endmodule
| 7.211486 |
module bsg_muxi2_gatestack_width_p5_harden_p1 (
i0,
i1,
i2,
o
);
input [4:0] i0;
input [4:0] i1;
input [4:0] i2;
output [4:0] o;
wire [4:0] o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14;
assign N6 = (N0) ? i1[0] : (N5) ? i0[0] : 1'b0;
assign N0 = i2[0];
assign N8 = (N1) ? i1[1] : (N7) ? i0[1] : 1'b0;
assign N1 = i2[1];
assign N10 = (N2) ? i1[2] : (N9) ? i0[2] : 1'b0;
assign N2 = i2[2];
assign N12 = (N3) ? i1[3] : (N11) ? i0[3] : 1'b0;
assign N3 = i2[3];
assign N14 = (N4) ? i1[4] : (N13) ? i0[4] : 1'b0;
assign N4 = i2[4];
assign N5 = ~i2[0];
assign o[0] = ~N6;
assign N7 = ~i2[1];
assign o[1] = ~N8;
assign N9 = ~i2[2];
assign o[2] = ~N10;
assign N11 = ~i2[3];
assign o[3] = ~N12;
assign N13 = ~i2[4];
assign o[4] = ~N14;
endmodule
| 7.211486 |
module bsg_mux_bitwise #(parameter `BSG_INV_PARAM(width_p ))
( input [width_p-1:0] select
, input [width_p-1:0] A
, input [width_p-1:0] B
, output logic [width_p-1:0] out
);
integer i;
always_comb
for (i = 0; i < width_p; i = i + 1)
if (select[i])
out[i] = A[i];
else
out[i] = B[i];
endmodule
| 7.04739 |
module has stages of mux which interleaves input data.
* Output data width is same as the input data width.
* The unit of swapping increases in higher stage.
*
* The lowest order bit swaps odd and even words
* the highest order bit swaps the upper half of all
* the words and the lower half of all the words.
* The second lowest order bit swaps odd and even pairs of words.
* Etc.
*
* The pattern mirrors that of a FFT butterfly network.
*
* In the first stage, the swapping is done by LSB of sel_i.
*
* example (els_p = 4):
* For input = {b3,b2,b1,b0}
* ---------------------------
* sel_i = 00 => {b3,b2,b1,b0}
* sel_i = 01 => {b2,b3,b0,b1}
* sel_i = 10 => {b1,b0,b3,b2}
* sel_i = 11 => {b0,b1,b2,b3}
* ---------------------------
*
*/
`include "bsg_defines.v"
module bsg_mux_butterfly
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, lg_els_lp=`BSG_SAFE_CLOG2(els_p)
)
(
input [els_p-1:0][width_p-1:0] data_i
, input [lg_els_lp-1:0] sel_i
, output logic [els_p-1:0][width_p-1:0] data_o
);
logic [lg_els_lp:0][(els_p*width_p)-1:0] data_stage;
assign data_stage[0] = data_i;
for (genvar i = 0; i < lg_els_lp; i++) begin: mux_stage
for (genvar j = 0; j < els_p/(2**(i+1)); j++) begin: mux_swap
bsg_swap #(
.width_p(width_p*(2**i))
) swap_inst (
.data_i(data_stage[i][2*width_p*(2**i)*j+:2*width_p*(2**i)])
,.swap_i(sel_i[i])
,.data_o(data_stage[i+1][2*width_p*(2**i)*j+:2*width_p*(2**i)])
);
end
end
assign data_o = data_stage[lg_els_lp];
endmodule
| 7.361155 |
module bsg_mux_one_hot #(parameter `BSG_INV_PARAM(width_p)
, els_p=1
, harden_p=1
)
(
input [els_p-1:0][width_p-1:0] data_i
,input [els_p-1:0] sel_one_hot_i
,output [width_p-1:0] data_o
);
wire [els_p-1:0][width_p-1:0] data_masked;
genvar i,j;
`bsg_mux_one_hot_gen_macro(3,14)
else
`bsg_mux_one_hot_gen_macro(3,4)
else
begin : notmacro
for (i = 0; i < els_p; i++)
begin : mask
assign data_masked[i] = data_i[i] & { width_p { sel_one_hot_i[i] } };
end
for (i = 0; i < width_p; i++)
begin: reduce
wire [els_p-1:0] gather;
for (j = 0; j < els_p; j++)
assign gather[j] = data_masked[j][i];
assign data_o[i] = | gather;
end
end
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p10_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [19:0] data_i;
input [1:0] sel_one_hot_i;
output [9:0] data_o;
wire [ 9:0] data_o;
wire [19:0] data_masked;
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[1];
assign data_masked[18] = data_i[18] & sel_one_hot_i[1];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_o[0] = data_masked[10] | data_masked[0];
assign data_o[1] = data_masked[11] | data_masked[1];
assign data_o[2] = data_masked[12] | data_masked[2];
assign data_o[3] = data_masked[13] | data_masked[3];
assign data_o[4] = data_masked[14] | data_masked[4];
assign data_o[5] = data_masked[15] | data_masked[5];
assign data_o[6] = data_masked[16] | data_masked[6];
assign data_o[7] = data_masked[17] | data_masked[7];
assign data_o[8] = data_masked[18] | data_masked[8];
assign data_o[9] = data_masked[19] | data_masked[9];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p1_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [0:0] data_i;
input [0:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p1_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [1:0] data_i;
input [1:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
wire [1:0] data_masked;
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[1];
assign data_o[0] = data_masked[1] | data_masked[0];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p32_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [31:0] data_i;
input [0:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
assign data_o[31] = data_i[31] & sel_one_hot_i[0];
assign data_o[30] = data_i[30] & sel_one_hot_i[0];
assign data_o[29] = data_i[29] & sel_one_hot_i[0];
assign data_o[28] = data_i[28] & sel_one_hot_i[0];
assign data_o[27] = data_i[27] & sel_one_hot_i[0];
assign data_o[26] = data_i[26] & sel_one_hot_i[0];
assign data_o[25] = data_i[25] & sel_one_hot_i[0];
assign data_o[24] = data_i[24] & sel_one_hot_i[0];
assign data_o[23] = data_i[23] & sel_one_hot_i[0];
assign data_o[22] = data_i[22] & sel_one_hot_i[0];
assign data_o[21] = data_i[21] & sel_one_hot_i[0];
assign data_o[20] = data_i[20] & sel_one_hot_i[0];
assign data_o[19] = data_i[19] & sel_one_hot_i[0];
assign data_o[18] = data_i[18] & sel_one_hot_i[0];
assign data_o[17] = data_i[17] & sel_one_hot_i[0];
assign data_o[16] = data_i[16] & sel_one_hot_i[0];
assign data_o[15] = data_i[15] & sel_one_hot_i[0];
assign data_o[14] = data_i[14] & sel_one_hot_i[0];
assign data_o[13] = data_i[13] & sel_one_hot_i[0];
assign data_o[12] = data_i[12] & sel_one_hot_i[0];
assign data_o[11] = data_i[11] & sel_one_hot_i[0];
assign data_o[10] = data_i[10] & sel_one_hot_i[0];
assign data_o[9] = data_i[9] & sel_one_hot_i[0];
assign data_o[8] = data_i[8] & sel_one_hot_i[0];
assign data_o[7] = data_i[7] & sel_one_hot_i[0];
assign data_o[6] = data_i[6] & sel_one_hot_i[0];
assign data_o[5] = data_i[5] & sel_one_hot_i[0];
assign data_o[4] = data_i[4] & sel_one_hot_i[0];
assign data_o[3] = data_i[3] & sel_one_hot_i[0];
assign data_o[2] = data_i[2] & sel_one_hot_i[0];
assign data_o[1] = data_i[1] & sel_one_hot_i[0];
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p41_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [40:0] data_i;
input [0:0] sel_one_hot_i;
output [40:0] data_o;
wire [40:0] data_o;
assign data_o[40] = data_i[40] & sel_one_hot_i[0];
assign data_o[39] = data_i[39] & sel_one_hot_i[0];
assign data_o[38] = data_i[38] & sel_one_hot_i[0];
assign data_o[37] = data_i[37] & sel_one_hot_i[0];
assign data_o[36] = data_i[36] & sel_one_hot_i[0];
assign data_o[35] = data_i[35] & sel_one_hot_i[0];
assign data_o[34] = data_i[34] & sel_one_hot_i[0];
assign data_o[33] = data_i[33] & sel_one_hot_i[0];
assign data_o[32] = data_i[32] & sel_one_hot_i[0];
assign data_o[31] = data_i[31] & sel_one_hot_i[0];
assign data_o[30] = data_i[30] & sel_one_hot_i[0];
assign data_o[29] = data_i[29] & sel_one_hot_i[0];
assign data_o[28] = data_i[28] & sel_one_hot_i[0];
assign data_o[27] = data_i[27] & sel_one_hot_i[0];
assign data_o[26] = data_i[26] & sel_one_hot_i[0];
assign data_o[25] = data_i[25] & sel_one_hot_i[0];
assign data_o[24] = data_i[24] & sel_one_hot_i[0];
assign data_o[23] = data_i[23] & sel_one_hot_i[0];
assign data_o[22] = data_i[22] & sel_one_hot_i[0];
assign data_o[21] = data_i[21] & sel_one_hot_i[0];
assign data_o[20] = data_i[20] & sel_one_hot_i[0];
assign data_o[19] = data_i[19] & sel_one_hot_i[0];
assign data_o[18] = data_i[18] & sel_one_hot_i[0];
assign data_o[17] = data_i[17] & sel_one_hot_i[0];
assign data_o[16] = data_i[16] & sel_one_hot_i[0];
assign data_o[15] = data_i[15] & sel_one_hot_i[0];
assign data_o[14] = data_i[14] & sel_one_hot_i[0];
assign data_o[13] = data_i[13] & sel_one_hot_i[0];
assign data_o[12] = data_i[12] & sel_one_hot_i[0];
assign data_o[11] = data_i[11] & sel_one_hot_i[0];
assign data_o[10] = data_i[10] & sel_one_hot_i[0];
assign data_o[9] = data_i[9] & sel_one_hot_i[0];
assign data_o[8] = data_i[8] & sel_one_hot_i[0];
assign data_o[7] = data_i[7] & sel_one_hot_i[0];
assign data_o[6] = data_i[6] & sel_one_hot_i[0];
assign data_o[5] = data_i[5] & sel_one_hot_i[0];
assign data_o[4] = data_i[4] & sel_one_hot_i[0];
assign data_o[3] = data_i[3] & sel_one_hot_i[0];
assign data_o[2] = data_i[2] & sel_one_hot_i[0];
assign data_o[1] = data_i[1] & sel_one_hot_i[0];
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p4_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [7:0] data_i;
input [1:0] sel_one_hot_i;
output [3:0] data_o;
wire [3:0] data_o;
wire [7:0] data_masked;
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[1];
assign data_masked[6] = data_i[6] & sel_one_hot_i[1];
assign data_masked[5] = data_i[5] & sel_one_hot_i[1];
assign data_masked[4] = data_i[4] & sel_one_hot_i[1];
assign data_o[0] = data_masked[4] | data_masked[0];
assign data_o[1] = data_masked[5] | data_masked[1];
assign data_o[2] = data_masked[6] | data_masked[2];
assign data_o[3] = data_masked[7] | data_masked[3];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p9_els_p3 (
data_i,
sel_one_hot_i,
data_o
);
input [26:0] data_i;
input [2:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8;
wire [26:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_masked[9] = data_i[9] & sel_one_hot_i[1];
assign data_masked[26] = data_i[26] & sel_one_hot_i[2];
assign data_masked[25] = data_i[25] & sel_one_hot_i[2];
assign data_masked[24] = data_i[24] & sel_one_hot_i[2];
assign data_masked[23] = data_i[23] & sel_one_hot_i[2];
assign data_masked[22] = data_i[22] & sel_one_hot_i[2];
assign data_masked[21] = data_i[21] & sel_one_hot_i[2];
assign data_masked[20] = data_i[20] & sel_one_hot_i[2];
assign data_masked[19] = data_i[19] & sel_one_hot_i[2];
assign data_masked[18] = data_i[18] & sel_one_hot_i[2];
assign data_o[0] = N0 | data_masked[0];
assign N0 = data_masked[18] | data_masked[9];
assign data_o[1] = N1 | data_masked[1];
assign N1 = data_masked[19] | data_masked[10];
assign data_o[2] = N2 | data_masked[2];
assign N2 = data_masked[20] | data_masked[11];
assign data_o[3] = N3 | data_masked[3];
assign N3 = data_masked[21] | data_masked[12];
assign data_o[4] = N4 | data_masked[4];
assign N4 = data_masked[22] | data_masked[13];
assign data_o[5] = N5 | data_masked[5];
assign N5 = data_masked[23] | data_masked[14];
assign data_o[6] = N6 | data_masked[6];
assign N6 = data_masked[24] | data_masked[15];
assign data_o[7] = N7 | data_masked[7];
assign N7 = data_masked[25] | data_masked[16];
assign data_o[8] = N8 | data_masked[8];
assign N8 = data_masked[26] | data_masked[17];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p9_els_p4 (
data_i,
sel_one_hot_i,
data_o
);
input [35:0] data_i;
input [3:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17;
wire [35:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_masked[9] = data_i[9] & sel_one_hot_i[1];
assign data_masked[26] = data_i[26] & sel_one_hot_i[2];
assign data_masked[25] = data_i[25] & sel_one_hot_i[2];
assign data_masked[24] = data_i[24] & sel_one_hot_i[2];
assign data_masked[23] = data_i[23] & sel_one_hot_i[2];
assign data_masked[22] = data_i[22] & sel_one_hot_i[2];
assign data_masked[21] = data_i[21] & sel_one_hot_i[2];
assign data_masked[20] = data_i[20] & sel_one_hot_i[2];
assign data_masked[19] = data_i[19] & sel_one_hot_i[2];
assign data_masked[18] = data_i[18] & sel_one_hot_i[2];
assign data_masked[35] = data_i[35] & sel_one_hot_i[3];
assign data_masked[34] = data_i[34] & sel_one_hot_i[3];
assign data_masked[33] = data_i[33] & sel_one_hot_i[3];
assign data_masked[32] = data_i[32] & sel_one_hot_i[3];
assign data_masked[31] = data_i[31] & sel_one_hot_i[3];
assign data_masked[30] = data_i[30] & sel_one_hot_i[3];
assign data_masked[29] = data_i[29] & sel_one_hot_i[3];
assign data_masked[28] = data_i[28] & sel_one_hot_i[3];
assign data_masked[27] = data_i[27] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[9];
assign N0 = data_masked[27] | data_masked[18];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[10];
assign N2 = data_masked[28] | data_masked[19];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[11];
assign N4 = data_masked[29] | data_masked[20];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[12];
assign N6 = data_masked[30] | data_masked[21];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[13];
assign N8 = data_masked[31] | data_masked[22];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[14];
assign N10 = data_masked[32] | data_masked[23];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[15];
assign N12 = data_masked[33] | data_masked[24];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[16];
assign N14 = data_masked[34] | data_masked[25];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[17];
assign N16 = data_masked[35] | data_masked[26];
endmodule
| 6.691649 |
module bsg_mux_segmented #(parameter `BSG_INV_PARAM(segments_p)
,parameter `BSG_INV_PARAM(segment_width_p)
,parameter data_width_lp=segments_p*segment_width_p)
(
input [data_width_lp-1:0] data0_i
,input [data_width_lp-1:0] data1_i
,input [segments_p-1:0] sel_i
,output logic [data_width_lp-1:0] data_o
);
genvar i;
for (i = 0; i < segments_p; i++) begin
assign data_o[i*segment_width_p+:segment_width_p] = sel_i[i]
? data1_i[i*segment_width_p+:segment_width_p]
: data0_i[i*segment_width_p+:segment_width_p];
end
endmodule
| 6.641883 |
module bsg_mux_segmented_segments_p5_segment_width_p128 (
data0_i,
data1_i,
sel_i,
data_o
);
input [639:0] data0_i;
input [639:0] data1_i;
input [4:0] sel_i;
output [639:0] data_o;
wire [639:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9;
assign data_o[127:0] = (N0) ? data1_i[127:0] : (N5) ? data0_i[127:0] : 1'b0;
assign N0 = sel_i[0];
assign data_o[255:128] = (N1) ? data1_i[255:128] : (N6) ? data0_i[255:128] : 1'b0;
assign N1 = sel_i[1];
assign data_o[383:256] = (N2) ? data1_i[383:256] : (N7) ? data0_i[383:256] : 1'b0;
assign N2 = sel_i[2];
assign data_o[511:384] = (N3) ? data1_i[511:384] : (N8) ? data0_i[511:384] : 1'b0;
assign N3 = sel_i[3];
assign data_o[639:512] = (N4) ? data1_i[639:512] : (N9) ? data0_i[639:512] : 1'b0;
assign N4 = sel_i[4];
assign N5 = ~sel_i[0];
assign N6 = ~sel_i[1];
assign N7 = ~sel_i[2];
assign N8 = ~sel_i[3];
assign N9 = ~sel_i[4];
endmodule
| 6.641883 |
module bsg_mux_segmented_segments_p5_segment_width_p64 (
data0_i,
data1_i,
sel_i,
data_o
);
input [319:0] data0_i;
input [319:0] data1_i;
input [4:0] sel_i;
output [319:0] data_o;
wire [319:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9;
assign data_o[63:0] = (N0) ? data1_i[63:0] : (N5) ? data0_i[63:0] : 1'b0;
assign N0 = sel_i[0];
assign data_o[127:64] = (N1) ? data1_i[127:64] : (N6) ? data0_i[127:64] : 1'b0;
assign N1 = sel_i[1];
assign data_o[191:128] = (N2) ? data1_i[191:128] : (N7) ? data0_i[191:128] : 1'b0;
assign N2 = sel_i[2];
assign data_o[255:192] = (N3) ? data1_i[255:192] : (N8) ? data0_i[255:192] : 1'b0;
assign N3 = sel_i[3];
assign data_o[319:256] = (N4) ? data1_i[319:256] : (N9) ? data0_i[319:256] : 1'b0;
assign N4 = sel_i[4];
assign N5 = ~sel_i[0];
assign N6 = ~sel_i[1];
assign N7 = ~sel_i[2];
assign N8 = ~sel_i[3];
assign N9 = ~sel_i[4];
endmodule
| 6.641883 |
module bsg_mux_segmented_segments_p8_segment_width_p8 (
data0_i,
data1_i,
sel_i,
data_o
);
input [63:0] data0_i;
input [63:0] data1_i;
input [7:0] sel_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15;
assign data_o[7:0] = (N0) ? data1_i[7:0] : (N8) ? data0_i[7:0] : 1'b0;
assign N0 = sel_i[0];
assign data_o[15:8] = (N1) ? data1_i[15:8] : (N9) ? data0_i[15:8] : 1'b0;
assign N1 = sel_i[1];
assign data_o[23:16] = (N2) ? data1_i[23:16] : (N10) ? data0_i[23:16] : 1'b0;
assign N2 = sel_i[2];
assign data_o[31:24] = (N3) ? data1_i[31:24] : (N11) ? data0_i[31:24] : 1'b0;
assign N3 = sel_i[3];
assign data_o[39:32] = (N4) ? data1_i[39:32] : (N12) ? data0_i[39:32] : 1'b0;
assign N4 = sel_i[4];
assign data_o[47:40] = (N5) ? data1_i[47:40] : (N13) ? data0_i[47:40] : 1'b0;
assign N5 = sel_i[5];
assign data_o[55:48] = (N6) ? data1_i[55:48] : (N14) ? data0_i[55:48] : 1'b0;
assign N6 = sel_i[6];
assign data_o[63:56] = (N7) ? data1_i[63:56] : (N15) ? data0_i[63:56] : 1'b0;
assign N7 = sel_i[7];
assign N8 = ~sel_i[0];
assign N9 = ~sel_i[1];
assign N10 = ~sel_i[2];
assign N11 = ~sel_i[3];
assign N12 = ~sel_i[4];
assign N13 = ~sel_i[5];
assign N14 = ~sel_i[6];
assign N15 = ~sel_i[7];
endmodule
| 6.641883 |
module bsg_nand_width_p5_harden_p1 (
a_i,
b_i,
o
);
input [4:0] a_i;
input [4:0] b_i;
output [4:0] o;
wire [4:0] o;
wire N0, N1, N2, N3, N4;
assign o[4] = ~N0;
assign N0 = a_i[4] & b_i[4];
assign o[3] = ~N1;
assign N1 = a_i[3] & b_i[3];
assign o[2] = ~N2;
assign N2 = a_i[2] & b_i[2];
assign o[1] = ~N3;
assign N3 = a_i[1] & b_i[1];
assign o[0] = ~N4;
assign N4 = a_i[0] & b_i[0];
endmodule
| 6.856627 |
module bsg_nasti_client_resp (
clk_i,
reset_i,
nasti_r_valid_o,
nasti_r_data_o,
nasti_r_ready_i,
resp_valid_i,
resp_data_i,
resp_yumi_o
);
output [72:0] nasti_r_data_o;
input [72:0] resp_data_i;
input clk_i;
input reset_i;
input nasti_r_ready_i;
input resp_valid_i;
output nasti_r_valid_o;
output resp_yumi_o;
wire [72:0] nasti_r_data_o;
wire nasti_r_valid_o, resp_yumi_o, resp_valid_i;
assign nasti_r_data_o[71] = 1'b0;
assign nasti_r_data_o[72] = 1'b0;
assign nasti_r_valid_o = resp_valid_i;
assign nasti_r_data_o[70] = resp_data_i[69];
assign nasti_r_data_o[69] = resp_data_i[68];
assign nasti_r_data_o[68] = resp_data_i[67];
assign nasti_r_data_o[67] = resp_data_i[66];
assign nasti_r_data_o[66] = resp_data_i[65];
assign nasti_r_data_o[65] = resp_data_i[64];
assign nasti_r_data_o[64] = resp_data_i[63];
assign nasti_r_data_o[63] = resp_data_i[62];
assign nasti_r_data_o[62] = resp_data_i[61];
assign nasti_r_data_o[61] = resp_data_i[60];
assign nasti_r_data_o[60] = resp_data_i[59];
assign nasti_r_data_o[59] = resp_data_i[58];
assign nasti_r_data_o[58] = resp_data_i[57];
assign nasti_r_data_o[57] = resp_data_i[56];
assign nasti_r_data_o[56] = resp_data_i[55];
assign nasti_r_data_o[55] = resp_data_i[54];
assign nasti_r_data_o[54] = resp_data_i[53];
assign nasti_r_data_o[53] = resp_data_i[52];
assign nasti_r_data_o[52] = resp_data_i[51];
assign nasti_r_data_o[51] = resp_data_i[50];
assign nasti_r_data_o[50] = resp_data_i[49];
assign nasti_r_data_o[49] = resp_data_i[48];
assign nasti_r_data_o[48] = resp_data_i[47];
assign nasti_r_data_o[47] = resp_data_i[46];
assign nasti_r_data_o[46] = resp_data_i[45];
assign nasti_r_data_o[45] = resp_data_i[44];
assign nasti_r_data_o[44] = resp_data_i[43];
assign nasti_r_data_o[43] = resp_data_i[42];
assign nasti_r_data_o[42] = resp_data_i[41];
assign nasti_r_data_o[41] = resp_data_i[40];
assign nasti_r_data_o[40] = resp_data_i[39];
assign nasti_r_data_o[39] = resp_data_i[38];
assign nasti_r_data_o[38] = resp_data_i[37];
assign nasti_r_data_o[37] = resp_data_i[36];
assign nasti_r_data_o[36] = resp_data_i[35];
assign nasti_r_data_o[35] = resp_data_i[34];
assign nasti_r_data_o[34] = resp_data_i[33];
assign nasti_r_data_o[33] = resp_data_i[32];
assign nasti_r_data_o[32] = resp_data_i[31];
assign nasti_r_data_o[31] = resp_data_i[30];
assign nasti_r_data_o[30] = resp_data_i[29];
assign nasti_r_data_o[29] = resp_data_i[28];
assign nasti_r_data_o[28] = resp_data_i[27];
assign nasti_r_data_o[27] = resp_data_i[26];
assign nasti_r_data_o[26] = resp_data_i[25];
assign nasti_r_data_o[25] = resp_data_i[24];
assign nasti_r_data_o[24] = resp_data_i[23];
assign nasti_r_data_o[23] = resp_data_i[22];
assign nasti_r_data_o[22] = resp_data_i[21];
assign nasti_r_data_o[21] = resp_data_i[20];
assign nasti_r_data_o[20] = resp_data_i[19];
assign nasti_r_data_o[19] = resp_data_i[18];
assign nasti_r_data_o[18] = resp_data_i[17];
assign nasti_r_data_o[17] = resp_data_i[16];
assign nasti_r_data_o[16] = resp_data_i[15];
assign nasti_r_data_o[15] = resp_data_i[14];
assign nasti_r_data_o[14] = resp_data_i[13];
assign nasti_r_data_o[13] = resp_data_i[12];
assign nasti_r_data_o[12] = resp_data_i[11];
assign nasti_r_data_o[11] = resp_data_i[10];
assign nasti_r_data_o[10] = resp_data_i[9];
assign nasti_r_data_o[9] = resp_data_i[8];
assign nasti_r_data_o[8] = resp_data_i[7];
assign nasti_r_data_o[7] = resp_data_i[6];
assign nasti_r_data_o[6] = resp_data_i[70];
assign nasti_r_data_o[5] = resp_data_i[5];
assign nasti_r_data_o[4] = resp_data_i[4];
assign nasti_r_data_o[3] = resp_data_i[3];
assign nasti_r_data_o[2] = resp_data_i[2];
assign nasti_r_data_o[1] = resp_data_i[1];
assign nasti_r_data_o[0] = resp_data_i[0];
assign resp_yumi_o = resp_valid_i & nasti_r_ready_i;
endmodule
| 6.750039 |
module instantiates num_nodes_p two-element-fifos in chains
// It supports multiple bsg_noc_links in parallel
//
// Insert this module into long routings on chip, which can become critical path
//
// Node that side_A_reset_i signal shoule be close to side A
// If reset happens to be close to side B, please swap side A and side B connection,
// since side A and side B are symmetric, functionality will not be affected.
//
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
module bsg_noc_repeater_node
#(parameter `BSG_INV_PARAM(width_p )
, parameter bsg_ready_and_link_sif_width_lp = `bsg_ready_and_link_sif_width(width_p)
)
( input clk_i
, input reset_i
, input [bsg_ready_and_link_sif_width_lp-1:0] side_A_links_i
, output [bsg_ready_and_link_sif_width_lp-1:0] side_A_links_o
, input [bsg_ready_and_link_sif_width_lp-1:0] side_B_links_i
, output [bsg_ready_and_link_sif_width_lp-1:0] side_B_links_o
);
// declare the bsg_ready_and_link_sif_s struct
`declare_bsg_ready_and_link_sif_s(width_p, bsg_ready_and_link_sif_s);
// noc links
bsg_ready_and_link_sif_s links_A_cast_i, links_B_cast_i;
bsg_ready_and_link_sif_s links_A_cast_o, links_B_cast_o;
assign links_A_cast_i = side_A_links_i;
assign links_B_cast_i = side_B_links_i;
assign side_A_links_o = links_A_cast_o;
assign side_B_links_o = links_B_cast_o;
bsg_two_fifo #(.width_p(width_p))
A_to_B
(.clk_i ( clk_i )
,.reset_i ( reset_i )
,.v_i ( links_A_cast_i.v )
,.data_i ( links_A_cast_i.data )
,.ready_o ( links_A_cast_o.ready_and_rev )
,.v_o ( links_B_cast_o.v )
,.data_o ( links_B_cast_o.data )
,.yumi_i ( links_B_cast_i.ready_and_rev & links_B_cast_o.v )
);
bsg_two_fifo #(.width_p(width_p))
B_to_A
(.clk_i ( clk_i )
,.reset_i ( reset_i )
,.v_i ( links_B_cast_i.v )
,.data_i ( links_B_cast_i.data )
,.ready_o ( links_B_cast_o.ready_and_rev )
,.v_o ( links_A_cast_o.v )
,.data_o ( links_A_cast_o.data )
,.yumi_i ( links_A_cast_i.ready_and_rev & links_A_cast_o.v )
);
endmodule
| 7.670485 |
module bsg_nonsynth_ascii_writer
#(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(values_p )
, parameter `BSG_INV_PARAM(filename_p )
, parameter fopen_param_p = "w"
, parameter format_p = "%x ")
(input clk
, input reset_i
, input valid_i
, input [width_p*values_p-1:0] data_i
);
integer file = -1;
integer i;
// fixme: check error condition
always @(posedge reset_i)
if (file == -1)
begin
file = $fopen(filename_p,fopen_param_p);
end
logic [width_p*values_p-1:0] capture_data_r;
logic capture_valid_r;
// delay the data by one cycle to avoid races
// in timing simulation
always @(posedge clk)
begin
capture_data_r <= data_i;
capture_valid_r <= valid_i;
end
// format does not work as parameter
always @(negedge clk)
if (capture_valid_r && file != -1)
begin
for (i = 0; i < values_p; i++)
begin
$fwrite(file,format_p,capture_data_r[i*width_p+:width_p]);
end
$fwrite(file,"\n");
end
endmodule
| 7.918385 |
module bsg_nonsynth_axil_to_dpi
#(parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
)
(input aclk_i
, input aresetn_i
, input [addr_width_p-1:0] awaddr_i
, input [2:0] awprot_i
, input awvalid_i
, output logic awready_o
, input [data_width_p-1:0] wdata_i
, input [(data_width_p/8)-1:0] wstrb_i
, input wvalid_i
, output logic wready_o
, output logic [1:0] bresp_o
, output logic bvalid_o
, input bready_i
, input [addr_width_p-1:0] araddr_i
, input [2:0] arprot_i
, input arvalid_i
, output logic arready_o
, output logic [data_width_p-1:0] rdata_o
, output logic [1:0] rresp_o
, output logic rvalid_o
, input rready_i
);
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
aclk_gpio
(.gpio_i(aclk_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
aresetn_gpio
(.gpio_i(aresetn_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(addr_width_p), .use_input_p(1))
awaddr_gpio
(.gpio_i(awaddr_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(3), .use_input_p(1))
awprot_gpio
(.gpio_i(awprot_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
awvalid_gpio
(.gpio_i(awvalid_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
awready_gpio
(.gpio_i(), .gpio_o(awready_o));
bsg_nonsynth_dpi_gpio
#(.width_p(data_width_p), .use_input_p(1))
wdata_gpio
(.gpio_i(wdata_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(data_width_p/8), .use_input_p(1))
wstrb_gpio
(.gpio_i(wstrb_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
wvalid_gpio
(.gpio_i(wvalid_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
wready_gpio
(.gpio_i(), .gpio_o(wready_o));
bsg_nonsynth_dpi_gpio
#(.width_p(2), .use_output_p(1))
bresp_gpio
(.gpio_i(), .gpio_o(bresp_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
bvalid_gpio
(.gpio_i(), .gpio_o(bvalid_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
bready_gpio
(.gpio_i(bready_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(addr_width_p), .use_input_p(1))
araddr_gpio
(.gpio_i(araddr_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(3), .use_input_p(1))
arprot_gpio
(.gpio_i(arprot_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
arvalid_gpio
(.gpio_i(arvalid_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
arready_gpio
(.gpio_i(), .gpio_o(arready_o));
bsg_nonsynth_dpi_gpio
#(.width_p(data_width_p), .use_output_p(1))
rdata_gpio
(.gpio_i(), .gpio_o(rdata_o));
bsg_nonsynth_dpi_gpio
#(.width_p(2), .use_output_p(1))
rresp_gpio
(.gpio_i(), .gpio_o(rresp_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
rvalid_gpio
(.gpio_i(), .gpio_o(rvalid_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
rready_gpio
(.gpio_i(rready_i), .gpio_o());
endmodule
| 7.918385 |
module bsg_nonsynth_cache_axe_tracer
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter sbuf_entry_width_lp=`bsg_cache_sbuf_entry_width(addr_width_p,data_width_p,ways_p)
)
(
input clk_i
, input v_o
, input yumi_i
, input bsg_cache_decode_s decode_v_r
, input [addr_width_p-1:0] addr_v_r
, input [sbuf_entry_width_lp-1:0] sbuf_entry_li
, input [data_width_p-1:0] data_o
);
`declare_bsg_cache_sbuf_entry_s(addr_width_p, data_width_p, ways_p);
bsg_cache_sbuf_entry_s sbuf_entry;
assign sbuf_entry = sbuf_entry_li;
// synopsys translate_off
localparam logfile_lp = "bsg_cache.axe";
integer fd;
string header;
initial forever begin
@(negedge clk_i) begin
if (v_o & yumi_i) begin
if (decode_v_r.st_op) begin
fd = $fopen(logfile_lp, "a");
$fwrite(fd, "0: M[%0d] := %0d\n", addr_v_r>>2, sbuf_entry.data);
$fclose(fd);
end
if (decode_v_r.ld_op) begin
fd = $fopen(logfile_lp, "a");
$fwrite(fd, "0: M[%0d] == %0d\n", addr_v_r>>2, data_o);
$fclose(fd);
end
end
end
end
// synopsys translate_on
endmodule
| 7.918385 |
module bsg_nonsynth_clk_watcher #(
tolerance_p = 0
) (
input clk_i
);
longint my_ticks_posedge = 0;
longint my_ticks_negedge = 0;
longint last_posedge = -1;
longint last_negedge = -1;
longint cycles_posedge = -1;
longint cycles_negedge = -1;
longint temp_time;
always @(posedge clk_i) begin
temp_time = $time;
if ((temp_time-my_ticks_negedge > last_posedge+tolerance_p)
|| (temp_time-my_ticks_negedge < last_posedge-tolerance_p))
begin
if (cycles_posedge != -1)
$write(
"## clock_watcher { POSEDGE offset (after %-8d cycles) %-7d ps (n/p phase ratio=%2.3f)} (%m)\n"
, cycles_posedge,
$time - my_ticks_negedge,
(real'(last_negedge)) / (real'($time - my_ticks_negedge))
);
cycles_posedge = 0;
last_posedge = $time - my_ticks_negedge;
end else cycles_posedge = cycles_posedge + 1;
my_ticks_posedge = $time;
end // always @ (posedge clk_i)
always @(negedge clk_i) begin
temp_time = $time;
if ((temp_time-my_ticks_posedge > last_negedge+tolerance_p)
|| (temp_time-my_ticks_posedge < last_negedge-tolerance_p))
begin
if (cycles_negedge != -1)
$write(
"## clock_watcher { NEGEDGE offset (after %-7d cycles) %-7d ps (p/n phase ratio=%2.3f)} (%m)\n"
, cycles_negedge,
$time - my_ticks_posedge,
(real'(last_posedge)) / (real'($time - my_ticks_posedge))
);
cycles_negedge = 0;
last_negedge = $time - my_ticks_posedge;
end else cycles_negedge = cycles_negedge + 1;
my_ticks_negedge = $time;
end
endmodule
| 7.918385 |
module bsg_nonsynth_clock_gen
#(parameter `BSG_INV_PARAM(cycle_time_p))
(output bit o);
`ifndef VERILATOR
initial begin
$display("%m with cycle_time_p ",cycle_time_p);
assert(cycle_time_p >= 2)
else $error("cannot simulate cycle time less than 2");
end
always #(cycle_time_p/2.0) begin
o = ~o;
end
`else
initial begin
$info("[BSG INFO]: bsg_nonsynth_clock_gen is not supported in Verilator due to delay statement (#)");
$info("[BSG INFO]: Falling back to bsg_nonsynth_dpi_clock_gen");
end
bsg_nonsynth_dpi_clock_gen #(.cycle_time_p(cycle_time_p)) bcg (.*);
`endif
endmodule
| 7.918385 |
module is a basic non-synthesizable clock generator. This module is
// designed to be used with VCS and can be changed at runtime rather than
// compile time. To set the speed of the clock, add the following flag when
// executing the simulation binary:
//
// ./simv +clock-period=<period>
//
// If no flag is added to the simulation, the clock period will default to the
// value of default_clk_per_p.
//
`include "bsg_defines.v"
module bsg_nonsynth_clock_gen_plusarg #( parameter `BSG_INV_PARAM(default_clk_per_p) )
(
output logic o
);
`ifndef VERILATOR
// We start logic hi so the first pos-edge occurs at T=<clk_per>. The first
// negative edge will occur at T=<clk_per>/2.
logic clk_lo = 1'b1;
initial begin
// Here we grab the clock_period from the command line plusarg and generate
// the clock signal. If the plusarg doesn't exist, the value is unchanged
// and no error/warning is issued.
integer clock_period = default_clk_per_p;
$value$plusargs("clock-period=%d", clock_period);
$display("[INFO - %L]: Clock Period = %d", clock_period);
forever #(clock_period/2.0) clk_lo = ~clk_lo;
end
// Assign clock to output port
assign o = clk_lo;
`else
initial begin
$error("bsg_nonsynth_clock_gen_plusarg is not supported in Verilator due to delay statement (#)");
end
`endif
endmodule
| 7.308399 |
module bsg_nonsynth_delay_line # (parameter width_p=1
,parameter `BSG_INV_PARAM(delay_p))
(input [width_p-1:0] i
, output logic [width_p-1:0] o
);
always @(i)
o <= #(delay_p) i;
endmodule
| 7.918385 |
module and specify the clock period as a
// parameter. In Verilator, this is not possible because the module
// uses an unsupported delay statement. It's also more challenging
// (though not impossible) to have multiple clock domains.
//
// What I've done is create a drop-in replacement that is backed by a
// C++ API, called bsg_nonsynth_dpi_clock_gen . The user doesn't need
// to know the difference, they just use a different module name with
// the same parameters and include bsg_nonsynth_clock_gen_dpi.hpp
//
// The C++ API is callback based; When each clock-generator module is
// instantiated, it registers itself with the C++ object via an
// imported DPI function -- bsg_nonsynth_clock_gen_register. The
// bsg_timekeeper class tracks the global time (no different than
// normal verilator) and uses a priority queue to track when the next
// clock generator toggles. To advance time, the users calls
// bsg_timekeeper::next()
//
// This drop-in replacement supports multiple clock generators and
// can be embedded anywhere in the hierarchy.
`include "bsg_defines.v"
module bsg_nonsynth_dpi_clock_gen
#(parameter `BSG_INV_PARAM(longint cycle_time_p)
)
(
output bit o
);
int id;
string hierarchy;
import "DPI-C" function int bsg_dpi_clock_gen_register(input longint cycle_time_p, input string hierarchy);
localparam longint cycle_time_lp = {32'b0, cycle_time_p[31:0]};
if(cycle_time_p % 2 != 0)
$fatal(1, "BSG ERROR (%M): cycle_time_p must be divisible by 2");
if(cycle_time_p <= 0)
$fatal(1, "BSG ERROR (%M): cycle_time_p must be greater than 0");
initial begin
$display("BSG INFO: bsg_nonsynth_dpi_clock_gen (initial begin)");
$display("BSG INFO: Instantiation: %M");
$display("BSG INFO: cycle_time_p = %d", cycle_time_p);
hierarchy = $sformatf("%m");
id = bsg_dpi_clock_gen_register(cycle_time_lp, hierarchy);
end
export "DPI-C" function bsg_dpi_clock_gen_set_level;
function bit bsg_dpi_clock_gen_set_level(bit clkval);
o = clkval;
return o;
endfunction;
endmodule
| 7.568142 |
modules defines a DPI interface for a counter that can be read
// periodically using DPI
`include "bsg_defines.v"
module bsg_nonsynth_dpi_cycle_counter
#(
parameter int width_p = 1
,parameter bit debug_p = 0
)
(
input clk_i
,input reset_i
,output logic [width_p-1:0] ctr_r_o
,output logic debug_o
);
export "DPI-C" function bsg_dpi_init;
export "DPI-C" function bsg_dpi_fini;
export "DPI-C" function bsg_dpi_debug;
export "DPI-C" function bsg_dpi_width;
export "DPI-C" function bsg_dpi_cycle_counter_read;
export "DPI-C" function bsg_dpi_cycle_counter_is_window;
// Tracks whether init has been called
logic init_l;
// Print module parameters to the console and set the intial debug
// value.
initial begin
$display("BSG INFO: bsg_nonsynth_dpi_cycle_counter (initial begin)");
$display("BSG INFO: Instantiation: %M");
$display("BSG INFO: width_p = %d", width_p);
$display("BSG INFO: debug_p = %d", debug_p);
end
bsg_cycle_counter
#(.width_p(width_p)
,.init_val_p('0))
counter_inst
(.clk_i(clk_i)
,.reset_i(reset_i)
,.ctr_r_o(ctr_r_o));
// We track the polarity of the current edge so that we can notify
// the user of incorrect behavior.
logic edgepol;
always_ff @(posedge clk_i or negedge clk_i) begin
edgepol <= clk_i;
end
// Initialize this Module
function void bsg_dpi_init();
if(init_l)
$fatal(1, "BSG ERROR (%M): init() already called");
init_l = 1;
endfunction
// Terminate this Module
function void bsg_dpi_fini();
if(~init_l)
$fatal(1, "BSG ERROR (%M): fini() already called");
init_l = 0;
endfunction
// Set or unset the debug_o output bit. If a state change occurs
// (0->1 or 1->0) then module will print DEBUG ENABLED / DEBUG
// DISABLED. No messages are printed if a state change does not
// occur.
function void bsg_dpi_debug(input bit switch_i);
if(!debug_o & switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG ENABLED", $time);
else if (debug_o & !switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG DISABLED", $time);
debug_o = switch_i;
endfunction
// Returns width_p
function int bsg_dpi_width();
return width_p;
endfunction
// The function bsg_dpi returns true if the interface is in a
// valid time-window to call bsg_dpi_fifo_rx()
function bit bsg_dpi_cycle_counter_is_window();
return (clk_i & edgepol & ~reset_i);
endfunction
// Read and return the current counter value.
function void bsg_dpi_cycle_counter_read(output bit [width_p-1:0] data_bo);
if(init_l === 0) begin
$fatal(1,"BSG ERROR (%M): read() called before init()");
end
if(reset_i === 1) begin
$fatal(1, "BSG ERROR (%M): read() called while reset_i === 1");
end
if(clk_i === 0) begin
$fatal(1, "BSG ERROR (%M): read() must be called when clk_i == 1");
end
if(edgepol === 0) begin
$fatal(1, "BSG ERROR (%M): read() must be called after the positive edge of clk_i has been evaluated");
end
data_bo = ctr_r_o;
endfunction
endmodule
| 7.747359 |
module bsg_nonsynth_dpi_to_axil
#(parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
)
(input aclk_i
, input aresetn_i
, output logic [addr_width_p-1:0] awaddr_o
, output logic [2:0] awprot_o
, output logic awvalid_o
, input awready_i
, output logic [data_width_p-1:0] wdata_o
, output logic [(data_width_p/8)-1:0] wstrb_o
, output logic wvalid_o
, input wready_i
, input [1:0] bresp_i
, input bvalid_i
, output logic bready_o
, output logic [addr_width_p-1:0] araddr_o
, output logic [2:0] arprot_o
, output logic arvalid_o
, input arready_i
, input [data_width_p-1:0] rdata_i
, input [1:0] rresp_i
, input rvalid_i
, output logic rready_o
);
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
aclk_gpio
(.gpio_i(aclk_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
aresetn_gpio
(.gpio_i(aresetn_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(addr_width_p), .use_output_p(1))
awaddr_gpio
(.gpio_i(), .gpio_o(awaddr_o));
bsg_nonsynth_dpi_gpio
#(.width_p(3), .use_output_p(1))
awprot_gpio
(.gpio_i(), .gpio_o(awprot_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
awvalid_gpio
(.gpio_i(), .gpio_o(awvalid_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
awready_gpio
(.gpio_i(awready_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(data_width_p), .use_output_p(1))
wdata_gpio
(.gpio_i(), .gpio_o(wdata_o));
bsg_nonsynth_dpi_gpio
#(.width_p(data_width_p/8), .use_output_p(1))
wstrb_gpio
(.gpio_i(), .gpio_o(wstrb_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
wvalid_gpio
(.gpio_i(), .gpio_o(wvalid_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
wready_gpio
(.gpio_i(wready_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(2), .use_input_p(1))
bresp_gpio
(.gpio_i(bresp_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
bvalid_gpio
(.gpio_i(bvalid_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
bready_gpio
(.gpio_i(), .gpio_o(bready_o));
bsg_nonsynth_dpi_gpio
#(.width_p(addr_width_p), .use_output_p(1))
araddr_gpio
(.gpio_i(), .gpio_o(araddr_o));
bsg_nonsynth_dpi_gpio
#(.width_p(3), .use_output_p(1))
arprot_gpio
(.gpio_i(), .gpio_o(arprot_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
arvalid_gpio
(.gpio_i(), .gpio_o(arvalid_o));
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
arready_gpio
(.gpio_i(arready_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(data_width_p), .use_input_p(1))
rdata_gpio
(.gpio_i(rdata_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(2), .use_input_p(1))
rresp_gpio
(.gpio_i(rresp_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_input_p(1))
rvalid_gpio
(.gpio_i(rvalid_i), .gpio_o());
bsg_nonsynth_dpi_gpio
#(.width_p(1), .use_output_p(1))
rready_gpio
(.gpio_i(), .gpio_o(rready_o));
endmodule
| 7.918385 |
module bsg_nonsynth_dramsim3_map
import bsg_dramsim3_pkg::*;
#(parameter `BSG_INV_PARAM(channel_addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter `BSG_INV_PARAM(num_columns_p)
, parameter `BSG_INV_PARAM(num_rows_p)
, parameter `BSG_INV_PARAM(num_ba_p)
, parameter `BSG_INV_PARAM(num_bg_p)
, parameter `BSG_INV_PARAM(num_ranks_p)
, parameter `BSG_INV_PARAM(address_mapping_p)
, parameter `BSG_INV_PARAM(channel_select_p)
, parameter debug_p=0
, parameter lg_num_channels_lp=$clog2(num_channels_p)
, parameter lg_num_columns_lp=$clog2(num_columns_p)
, parameter lg_num_rows_lp=$clog2(num_rows_p)
, parameter lg_num_ba_lp=$clog2(num_ba_p)
, parameter lg_num_bg_lp=$clog2(num_bg_p)
, parameter lg_num_ranks_lp=$clog2(num_ranks_p)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, parameter addr_width_lp=lg_num_channels_lp+channel_addr_width_p
)
(
input logic [channel_addr_width_p-1:0] ch_addr_i
, output logic [addr_width_lp-1:0] mem_addr_o
);
localparam co_pos_lp = byte_offset_width_lp;
localparam ba_pos_lp = co_pos_lp + lg_num_columns_lp;
localparam bg_pos_lp = ba_pos_lp + lg_num_ba_lp;
localparam ra_pos_lp = bg_pos_lp + lg_num_bg_lp;
localparam ro_pos_lp = ra_pos_lp + lg_num_ranks_lp;
if (address_mapping_p == e_ro_ra_bg_ba_co_ch) begin
assign mem_addr_o
= {
ch_addr_i[channel_addr_width_p-1:byte_offset_width_lp],
{lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}},
{byte_offset_width_lp{1'b0}}
};
end
else if (address_mapping_p == e_ro_ra_bg_ba_ch_co) begin
assign mem_addr_o
= {
ch_addr_i[channel_addr_width_p-1:lg_num_columns_lp+byte_offset_width_lp],
{lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}},
ch_addr_i[lg_num_columns_lp+byte_offset_width_lp-1:byte_offset_width_lp],
{byte_offset_width_lp{1'b0}}
};
end
else if (address_mapping_p == e_ro_ch_ra_ba_bg_co) begin
assign mem_addr_o
= {
ch_addr_i[ro_pos_lp+:lg_num_rows_lp],
{lg_num_channels_lp!=0{`BSG_MAX(lg_num_channels_lp, 1)'(channel_select_p)}},
{lg_num_ranks_lp!=0{ch_addr_i[ra_pos_lp+:`BSG_MAX(lg_num_ranks_lp, 1)]}},
{lg_num_ba_lp!=0{ch_addr_i[ba_pos_lp+:`BSG_MAX(lg_num_ba_lp, 1)]}},
{lg_num_bg_lp!=0{ch_addr_i[bg_pos_lp+:`BSG_MAX(lg_num_bg_lp, 1)]}},
ch_addr_i[co_pos_lp+:lg_num_columns_lp],
{byte_offset_width_lp{1'b0}}
};
end
endmodule
| 7.918385 |
module bsg_nonsynth_dramsim3_unmap
import bsg_dramsim3_pkg::*;
#(parameter `BSG_INV_PARAM(channel_addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter `BSG_INV_PARAM(num_columns_p)
, parameter `BSG_INV_PARAM(num_rows_p)
, parameter `BSG_INV_PARAM(num_ba_p)
, parameter `BSG_INV_PARAM(num_bg_p)
, parameter `BSG_INV_PARAM(num_ranks_p)
, parameter `BSG_INV_PARAM(address_mapping_p)
, parameter `BSG_INV_PARAM(channel_select_p)
, parameter debug_p=0
, parameter lg_num_channels_lp=$clog2(num_channels_p)
, parameter lg_num_columns_lp=$clog2(num_columns_p)
, parameter lg_num_rows_lp=$clog2(num_rows_p)
, parameter lg_num_ba_lp=$clog2(num_ba_p)
, parameter lg_num_bg_lp=$clog2(num_bg_p)
, parameter lg_num_ranks_lp=$clog2(num_ranks_p)
, parameter data_mask_width_lp=(data_width_p>>3)
, parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
, parameter addr_width_lp=lg_num_channels_lp+channel_addr_width_p
)
(
input logic [addr_width_lp-1:0] mem_addr_i
, output logic [channel_addr_width_p-1:0] ch_addr_o
);
if (address_mapping_p == e_ro_ra_bg_ba_co_ch) begin
assign ch_addr_o
= {
mem_addr_i[addr_width_lp-1:byte_offset_width_lp+lg_num_channels_lp],
{byte_offset_width_lp{1'b0}}
};
end
else if (address_mapping_p == e_ro_ra_bg_ba_ch_co) begin
assign ch_addr_o
= {
mem_addr_i[addr_width_lp-1:lg_num_channels_lp+lg_num_columns_lp+byte_offset_width_lp],
mem_addr_i[lg_num_columns_lp+byte_offset_width_lp-1:byte_offset_width_lp],
{byte_offset_width_lp{1'b0}}
};
end
else if (address_mapping_p == e_ro_ch_ra_ba_bg_co) begin
localparam mem_co_pos_lp = byte_offset_width_lp;
localparam mem_bg_pos_lp = mem_co_pos_lp + lg_num_columns_lp;
localparam mem_ba_pos_lp = mem_bg_pos_lp + lg_num_bg_lp;
localparam mem_ra_pos_lp = mem_ba_pos_lp + lg_num_ba_lp;
localparam mem_ch_pos_lp = mem_ra_pos_lp + lg_num_ranks_lp;
localparam mem_ro_pos_lp = mem_ch_pos_lp + lg_num_channels_lp;
assign ch_addr_o
= {
mem_addr_i[mem_ro_pos_lp+:lg_num_rows_lp],
{lg_num_ranks_lp!=0{mem_addr_i[mem_ra_pos_lp+:`BSG_MAX(lg_num_ranks_lp, 1)]}},
{lg_num_bg_lp!=0{mem_addr_i[mem_bg_pos_lp+:`BSG_MAX(lg_num_bg_lp, 1)]}},
{lg_num_ba_lp!=0{mem_addr_i[mem_ba_pos_lp+:`BSG_MAX(lg_num_ba_lp, 1)]}},
mem_addr_i[mem_co_pos_lp+:lg_num_columns_lp],
{byte_offset_width_lp{1'b0}}
};
end
endmodule
| 7.918385 |
module bsg_nonsynth_manycore_packet_printer #(
// maximum number of outstanding words
freeze_init_p = 1'b1
, x_cord_width_p = "inv"
, y_cord_width_p = "inv"
, addr_width_p = "inv"
, data_width_p = "inv"
, debug_p = 1
, packet_width_lp =
`bsg_manycore_packet_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p)
, bsg_manycore_link_sif_width_lp =
`bsg_manycore_link_sif_width(addr_width_p, data_width_p, x_cord_width_p, y_cord_width_p)
) (
input clk_i
, input reset_i
, input [bsg_manycore_link_sif_width_lp-1:0] link_sif_i
, output [bsg_manycore_link_sif_width_lp-1:0] link_sif_o
, input [x_cord_width_p-1:0] my_x_i
, input [y_cord_width_p-1:0] my_y_i
);
logic pkt_v, pkt_yumi;
logic [ data_width_p-1:0] pkt_data;
logic [ addr_width_p-1:0] pkt_addr;
logic [(data_width_p>>3)-1:0] pkt_mask;
logic out_v_li;
bsg_manycore_endpoint_standard #(
.x_cord_width_p (x_cord_width_p)
, .y_cord_width_p (y_cord_width_p)
, .fifo_els_p (2) // since this module does not queue data
, .freeze_init_p (freeze_init_p) // input fifo is small
, .max_out_credits_p(2) // not sending data, keep it small
, .data_width_p (data_width_p)
, .addr_width_p (addr_width_p)
) endp (
.clk_i
, .reset_i
, .link_sif_i
, .link_sif_o
,.in_v_o (pkt_v)
,.in_yumi_i(pkt_yumi)
,.in_data_o(pkt_data)
,.in_mask_o(pkt_mask)
,.in_addr_o(pkt_addr)
, .out_v_i (out_v_li)
, .out_packet_i ()
, .out_ready_o ()
, .out_credits_o()
, .my_x_i
, .my_y_i
, .freeze_r_o()
);
// not transmitting anything
assign out_v_li = 1'b0;
// accept all data
assign pkt_yumi = pkt_v;
always @(negedge clk_i)
if (pkt_v) begin
$display("## bsg_nonsynth_manycore_packet_print received addr=0h%x, data=%x, at x,y=%d,%d"
, pkt_addr, pkt_data, my_x_i, my_y_i);
if (pkt_data == 32'hCAFE_C0DE) begin
$display("## bsg_nonsynth_manycore_packet_print received CAFE_CODE packet, exiting");
$finish;
end
end
endmodule
| 7.918385 |
module bsg_nonsynth_manycore_tag_master
import bsg_tag_pkg::*;
import bsg_noc_pkg::*;
#(parameter `BSG_INV_PARAM(num_pods_x_p)
, parameter `BSG_INV_PARAM(num_pods_y_p)
, parameter `BSG_INV_PARAM(wh_cord_width_p)
)
(
input clk_i
, input reset_i
// done signal for peripherals
, output logic tag_done_o
, output bsg_tag_s [num_pods_y_p-1:0][num_pods_x_p-1:0] pod_tags_o
);
// one tag client per pods
localparam num_clients_lp = (num_pods_y_p*num_pods_x_p);
localparam rom_addr_width_lp = 12;
localparam payload_width_lp = 1; // {reset}
localparam lg_payload_width_lp = `BSG_WIDTH(payload_width_lp); // number of bits used to represent the payload width
localparam max_payload_width_lp = (1<<lg_payload_width_lp)-1;
localparam rom_data_width_lp = 4+1+`BSG_SAFE_CLOG2(num_clients_lp)+1+lg_payload_width_lp+max_payload_width_lp;
// BSG TAG trace replay
logic tr_valid_lo;
logic tr_en_r_lo;
logic tr_data_lo;
logic [rom_data_width_lp-1:0] rom_data;
logic [rom_addr_width_lp-1:0] rom_addr;
bsg_tag_trace_replay #(
.rom_addr_width_p(rom_addr_width_lp)
,.rom_data_width_p(rom_data_width_lp)
,.num_masters_p(1)
,.num_clients_p(num_clients_lp)
,.max_payload_width_p(max_payload_width_lp)
,.uptime_p(0)
) tr (
.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(1'b1)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.valid_i(1'b0)
,.data_i('0)
,.ready_o()
,.valid_o(tr_valid_lo)
,.en_r_o(tr_en_r_lo)
,.tag_data_o(tr_data_lo)
,.yumi_i(tr_valid_lo)
,.done_o(tag_done_o)
,.error_o()
);
// BSG TAG boot rom
bsg_tag_boot_rom #(
.width_p(rom_data_width_lp)
,.addr_width_p(rom_addr_width_lp)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
// BSG TAG MASTER
bsg_tag_master #(
.els_p(num_clients_lp)
,.lg_width_p(lg_payload_width_lp)
) btm (
.clk_i(clk_i)
,.data_i(tr_en_r_lo & tr_valid_lo & tr_data_lo)
,.en_i(1'b1)
,.clients_r_o({pod_tags_o})
);
endmodule
| 7.918385 |
module bsg_nonsynth_mem_1r1w_sync_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_in_bytes_lp)
, parameter init_mem_p=0
)
(
input clk_i
, input reset_i
// ctrl interface
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// read channel
, output logic [width_p-1:0] data_o
);
bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma
#(.width_p(width_p)
,.els_p(els_p)
,.id_p(id_p)
,.init_mem_p(init_mem_p))
mem
(.*
,.w_mask_i('1));
endmodule
| 7.918385 |
module bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter byte_offset_width_lp=$clog2(data_width_in_bytes_lp)
, parameter init_mem_p=0
)
(
input clk_i
, input reset_i
// ctrl interface
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input [write_mask_width_lp-1:0] w_mask_i
// read channel
, output logic [width_p-1:0] data_o
);
import "DPI-C" context function
chandle bsg_mem_dma_init(longint unsigned id,
longint unsigned channel_addr_width_fp,
longint unsigned data_width_fp,
longint unsigned mem_els_fp,
longint unsigned init_mem_fp);
import "DPI-C" context function
void bsg_mem_dma_exit(longint unsigned id);
import "DPI-C" context function
byte unsigned bsg_mem_dma_get(chandle handle, longint unsigned addr);
import "DPI-C" context function
void bsg_mem_dma_set(chandle handle, longint unsigned addr, byte val);
chandle memory;
initial begin
memory
= bsg_mem_dma_init(id_p, addr_width_lp, width_p, els_p, init_mem_p);
end
final begin
bsg_mem_dma_exit(id_p);
end
////////////////
// read logic //
////////////////
logic [addr_width_lp+byte_offset_width_lp-1:0] read_byte_addr;
assign read_byte_addr = { r_addr_i, {(byte_offset_width_lp){1'b0}} };
logic [width_p-1:0] data_r;
always_ff @(negedge clk_i) begin
if (r_v_i) begin
for (integer byte_id = 0; byte_id < data_width_in_bytes_lp; byte_id++) begin
data_r[byte_id*8+:8] <= bsg_mem_dma_get(memory, read_byte_addr+byte_id);
end
end
end
// most client code expects outputs to change at the positive edge
always_ff @(posedge clk_i) begin
data_o <= data_r;
end
/////////////////
// write logic //
/////////////////
logic [addr_width_lp+byte_offset_width_lp-1:0] write_byte_addr;
assign write_byte_addr = { w_addr_i, {(byte_offset_width_lp){1'b0}} };
logic [width_p-1:0] mem_data_li;
logic write_valid;
assign write_valid = ~reset_i & w_v_i;
assign mem_data_li = w_data_i;
always_ff @(posedge clk_i) begin
for (integer byte_id = 0; byte_id < data_width_in_bytes_lp; byte_id++) begin
if (write_valid & w_mask_i[byte_id])
bsg_mem_dma_set(memory, write_byte_addr+byte_id, mem_data_li[byte_id*8+:8]);
end
end
endmodule
| 7.918385 |
module bsg_nonsynth_mem_1rw_sync_assoc
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
)
(
input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_p-1:0] addr_i
, input v_i
, input w_i
, output logic [width_p-1:0] data_o
);
wire unused = reset_i;
// associative array
//
`ifdef VERILATOR
// version 4.024 supports associative array, but not wildcard indexed.
logic [width_p-1:0] mem [longint];
`else
logic [width_p-1:0] mem [*];
`endif
// write logic
//
always_ff @ (posedge clk_i) begin
if (~reset_i & v_i & w_i) begin
mem[addr_i] <= data_i;
end
end
// read logic
//
always_ff @ (posedge clk_i) begin
if (~reset_i & v_i & ~w_i) begin
data_o <= mem[addr_i];
end
end
endmodule
| 7.918385 |
module bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter write_mask_width_lp=(data_width_p>>3)
)
(
input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_p-1:0] addr_i
, input [data_width_p-1:0] data_i
, input [write_mask_width_lp-1:0] write_mask_i
, output [data_width_p-1:0] data_o
);
for (genvar i = 0; i < write_mask_width_lp; i++) begin: bk
bsg_nonsynth_mem_1rw_sync_assoc #(
.addr_width_p(addr_width_p)
,.width_p(8)
) mem_1rw_sync (
.clk_i(clk_i)
,.reset_i(reset_i)
,.data_i(data_i[(i*8)+:8])
,.addr_i(addr_i)
,.v_i(v_i)
,.w_i(w_i & write_mask_i[i])
,.data_o(data_o[(i*8)+:8])
);
end
endmodule
| 7.918385 |
module bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter byte_offset_width_lp=`BSG_SAFE_CLOG2(data_width_in_bytes_lp)
, parameter init_mem_p=0
)
(
input clk_i
, input reset_i
// ctrl interface
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [width_p-1:0] data_i
, input [write_mask_width_lp-1:0] w_mask_i
// read channel
, output logic [width_p-1:0] data_o
);
bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma
#(.width_p(width_p)
,.els_p(els_p)
,.id_p(id_p)
,.init_mem_p(init_mem_p))
mem
(.clk_i(clk_i)
,.reset_i(reset_i)
,.r_v_i(v_i & ~w_i)
,.r_addr_i(addr_i)
,.w_v_i(v_i & w_i)
,.w_addr_i(addr_i)
,.w_data_i(data_i)
,.w_mask_i(w_mask_i)
,.data_o(data_o));
endmodule
| 7.918385 |
module generates a stream of random numbers with seed specified
as a parameter. Since the value of the seed is provided as a parameter,
each instantiation of this module produces a pre-determined stream making
it easy to reproduce the sequence.
Next random number is generated after every clock cycle if yumi_i is
asserted. Otherwise, the previous value is retained. Also, after
every reset signal the stream of random numbers is restarted.
***********************************************************************/
`include "bsg_defines.v"
module bsg_nonsynth_random_gen
#( parameter width_p = 3
, parameter seed_p = 100
)
( input clk_i
, input reset_i
, input yumi_i
, output logic[width_p-1:0] data_o
);
always_ff @(posedge clk_i)
begin
if(reset_i)
data_o <= $random(seed_p);
else
if(yumi_i)
data_o <= $random();
end
endmodule
| 6.670138 |
module bsg_nonsynth_random_yumi_gen
#(parameter `BSG_INV_PARAM(yumi_min_delay_p)
, parameter `BSG_INV_PARAM(yumi_max_delay_p)
)
(
input clk_i
, input reset_i
, input v_i
, output logic yumi_o
);
integer yumi_count_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
yumi_count_r <= $urandom_range(yumi_max_delay_p,yumi_min_delay_p);
end
else begin
if (v_i) begin
if (yumi_count_r == 0)
yumi_count_r <= $urandom_range(yumi_max_delay_p,yumi_min_delay_p);
else
yumi_count_r <= yumi_count_r - 1;
end
end
end
assign yumi_o = v_i & (yumi_count_r == 0);
endmodule
| 7.918385 |
module bsg_nonsynth_reset_gen #(parameter num_clocks_p=1
, parameter `BSG_INV_PARAM(reset_cycles_lo_p)
, parameter `BSG_INV_PARAM(reset_cycles_hi_p))
(input bit [num_clocks_p-1:0] clk_i
, output bit async_reset_o);
genvar i;
// This module relies on the input clock wires starting at 0 at
// time 0 and not transitioning from X to 0 at time 0, and causing
// a spurious negedge. To accomplish this in > VCS 2020, the input
// must be declared as a bit. Moreover, the expectation is that
// this module's input comes from a clock generation module that
// uses bit, such as bsg_nonsynth_clk_gen, AND that the wire
// between them is a bit.
// use bit instead of logic to default to 0 initialization value
// this makes it non-synthesizeable, but also allows X prop mode to work
bit [num_clocks_p-1:0][$clog2(reset_cycles_lo_p+1)-1:0] ctr_lo_r;
bit [num_clocks_p-1:0][$clog2(reset_cycles_hi_p+1)-1:0] ctr_hi_r;
bit [num_clocks_p-1:0] phase_lo_r;
bit [num_clocks_p-1:0] phase_hi_r;
wire in_phase_1 = & phase_lo_r;
wire in_phase_2 = & phase_hi_r;
for (i = 0; i < num_clocks_p; i=i+1)
begin : rof
assign phase_lo_r[i] = (ctr_lo_r[i] == reset_cycles_lo_p);
assign phase_hi_r[i] = (ctr_hi_r[i] == reset_cycles_hi_p);
always @(negedge clk_i[i])
if (~phase_lo_r[i])
ctr_lo_r[i] <= ctr_lo_r[i] + 1;
else if (~phase_hi_r[i])
ctr_hi_r[i] <= ctr_hi_r[i] + in_phase_1;
end
assign async_reset_o = (in_phase_1 ^ in_phase_2);
always @(negedge async_reset_o)
begin
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | 1->0 time = ",$stime);
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" ASYNC \\/ \\/ \\/ \\/ ");
end
always @(posedge async_reset_o)
begin
$display("__________ ___________ _______________________________");
$display("\\______ \\\\_ _____/ / _____/\\_ _____/\\__ ___/");
$display(" | _/ | __)_ \\_____ \\ | __)_ | | ");
$display(" | | \\ | \\ / \\ | \\ | | 0->1 time = ",$stime);
$display(" |____|_ //_______ //_______ //_______ / |____| ");
$display(" ASYNC \\/ \\/ \\/ \\/ ");
end
endmodule
| 7.918385 |
module bsg_nonsynth_test_rom
#(parameter `BSG_INV_PARAM(filename_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter hex_not_bin_p = 0
)
(
input [addr_width_p-1:0] addr_i
, output logic [data_width_p-1:0] data_o
);
localparam els_lp = 2**addr_width_p;
logic [data_width_p-1:0] rom [els_lp-1:0];
initial
if (hex_not_bin_p)
$readmemh(filename_p, rom);
else
$readmemb(filename_p, rom);
assign data_o = rom[addr_i];
endmodule
| 7.918385 |
module bsg_nonsynth_triwire #
(parameter `BSG_INV_PARAM(width_p)
,parameter real transport_delay_p = 0.0)
(inout [width_p-1:0] a
,inout [width_p-1:0] b);
// This initialization to z is important to prevent the signal from being
// alway x
logic [width_p-1:0] a_dly = 'bz;
logic [width_p-1:0] b_dly = 'bz;
always@(a) a_dly <= #(transport_delay_p) b_dly==={width_p{1'bz}}? a: 'bz;
always@(b) b_dly <= #(transport_delay_p) a_dly==={width_p{1'bz}}? b: 'bz;
assign b = a_dly, a = b_dly;
endmodule
| 7.918385 |
module bsg_nonsynth_val_watcher_1p #(
string_p = "unknown",
trigger_val_p = -1,
val_size_p = 32,
one_time_trigger_p = 1'b1,
p1_width_p = 32,
extra_p = 1
) (
input clk_i
, input reset_i
, input [val_size_p-1:0] val_i
, input [p1_width_p-1:0] p1_i
);
logic triggered_r, triggered_n;
always_ff @(posedge clk_i) begin
if (triggered_n) begin
if (extra_p) $display("// %m: %s %x.\n", string_p, p1_i);
else $display("// %m: %s.\n", string_p);
end
if (reset_i) triggered_r <= 0;
else triggered_r <= triggered_r | triggered_n;
end
assign triggered_n = (val_i == trigger_val_p) & (~triggered_r | ~one_time_trigger_p);
endmodule
| 7.918385 |
module bsg_nor2 #(parameter `BSG_INV_PARAM(width_p)
, harden_p=1)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [width_p-1:0] o
);
assign o = ~(a_i | b_i );
endmodule
| 7.552459 |
module bsg_nor3_width_p4_harden_p1 (
a_i,
b_i,
c_i,
o
);
input [3:0] a_i;
input [3:0] b_i;
input [3:0] c_i;
output [3:0] o;
wire [3:0] o;
wire N0, N1, N2, N3, N4, N5, N6, N7;
assign o[3] = ~N1;
assign N1 = N0 | c_i[3];
assign N0 = a_i[3] | b_i[3];
assign o[2] = ~N3;
assign N3 = N2 | c_i[2];
assign N2 = a_i[2] | b_i[2];
assign o[1] = ~N5;
assign N5 = N4 | c_i[1];
assign N4 = a_i[1] | b_i[1];
assign o[0] = ~N7;
assign N7 = N6 | c_i[0];
assign N6 = a_i[0] | b_i[0];
endmodule
| 7.158871 |
module bsg_oddr_phy_90 #(
parameter width_p = "inv"
) (
input reset_i
, input clk_2x_i
, input [2*width_p-1:0] data_i
, output logic [width_p-1:0] data_r_o
, output logic clk_r_o
);
logic odd, clk;
logic [2*width_p-1:0] data_90;
always @(negedge clk_2x_i) data_90 <= data_i;
always @(posedge clk_2x_i) begin
clk <= ~reset_i & ~clk;
clk_r_o <= clk;
end
always @(negedge clk_2x_i) odd <= ~reset_i & ~odd;
always @(negedge clk_2x_i)
if (odd) data_r_o <= data_90[0+:width_p];
else data_r_o <= data_90[width_p+:width_p];
endmodule
| 6.738984 |
module bsg_oddr_phy_180 #(
parameter width_p = "inv"
) (
input reset_i
, input clk_2x_i
, input [2*width_p-1:0] data_i
, output logic [width_p-1:0] data_r_o
, output logic clk_r_o
);
logic odd, clk;
logic [2*width_p-1:0] data_180;
always @(posedge clk_2x_i) data_180 <= data_i;
always @(negedge clk_2x_i) begin
clk <= reset_i | ~clk;
clk_r_o <= clk;
end
always @(posedge clk_2x_i) odd <= ~reset_i & ~odd;
always @(posedge clk_2x_i)
if (odd) data_r_o <= data_180[0+:width_p];
else data_r_o <= data_180[width_p+:width_p];
endmodule
| 6.738984 |
module.
//
`include "bsg_defines.v"
module bsg_one_fifo #(parameter width_p="inv"
)
(input clk_i
, input reset_i
// input side
, output ready_o // early
, input [width_p-1:0] data_i // late
, input v_i // late
// output side
, output v_o // early
, output[width_p-1:0] data_o // early
, input yumi_i // late
);
logic full_r;
assign ready_o = ~full_r;
assign v_o = full_r;
bsg_dff_reset #(.width_p(1)) dff_full
(.clk_i
,.reset_i
,.data_i(full_r ? ~yumi_i: v_i)
,.data_o(full_r)
);
bsg_dff_en #(.width_p(width_p), .harden_p(0)) dff
(.clk_i
,.data_i
// although technically it is okay to just look at v_o
// this will cause unnecessary toggling of flip flops
,.en_i(v_i & ready_o)
,.data_o
);
endmodule
| 7.709861 |
module bsg_parallel_in_serial_out_dynamic
#(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(max_els_p)
,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
)
(input clk_i
,input reset_i
// Input side
,input v_i
,input [lg_max_els_lp-1:0] len_i
,input [max_els_p-1:0][width_p-1:0] data_i
,output ready_o
// Output side
,output v_o
,output len_v_o
,output [width_p-1:0] data_o
,input yumi_i
);
logic go_fifo_yumi_li;
logic [lg_max_els_lp-1:0] len_lo;
logic [max_els_p-1:0][width_p-1:0] fifo_data_lo;
// Go fifo and data fifo share the same control logic
// They always contain same number of elements in memory
// Go fifo
bsg_two_fifo
#(.width_p(lg_max_els_lp )
) go_fifo
(.clk_i (clk_i )
,.reset_i(reset_i )
,.ready_o(ready_o )
,.data_i (len_i )
,.v_i (v_i )
,.v_o (v_o )
,.data_o (len_lo )
,.yumi_i (go_fifo_yumi_li)
);
// Data fifo
bsg_two_fifo
#(.width_p(max_els_p*width_p)
) data_fifo
(.clk_i (clk_i )
,.reset_i(reset_i )
,.ready_o( )
,.data_i (data_i )
,.v_i (v_i )
,.v_o ( )
,.data_o (fifo_data_lo )
,.yumi_i (go_fifo_yumi_li )
);
logic [lg_max_els_lp-1:0] count_r, count_lo;
logic clear_li, up_li;
logic count_r_is_zero, count_r_is_last;
// fix evaluate to Z problem in simulation
assign count_lo = count_r;
assign count_r_is_zero = (count_lo == lg_max_els_lp'(0));
assign count_r_is_last = (count_lo == len_lo );
// Indicate if output word is first word of packet
assign len_v_o = count_r_is_zero;
// Count up if current word is not last word of packet.
assign up_li = yumi_i & ~count_r_is_last;
// Clear counter when whole packet finish sending
assign clear_li = yumi_i & count_r_is_last;
assign go_fifo_yumi_li = clear_li;
// Length counter
bsg_counter_clear_up
#(.max_val_p (max_els_p-1)
,.init_val_p(0)
) ctr
(.clk_i (clk_i )
,.reset_i (reset_i )
,.clear_i (clear_li)
,.up_i (up_li )
,.count_o (count_r )
);
// Output mux
bsg_mux
#(.width_p(width_p )
,.els_p (max_els_p )
) data_mux
(.data_i (fifo_data_lo)
,.sel_i (count_lo )
,.data_o (data_o )
);
endmodule
| 8.202302 |
module is helpful on both sides.
// Note:
// A transaction starts when ready_and_o & v_i. data_i must
// stay constant for the entirety of the transaction until
// ready_and_o is asserted.
// This may make the module incompatible with upstream modules that
// multiplex multiple inputs and can change which input they multiplex
// on the fly based on arrival of new inputs.
`include "bsg_defines.v"
module bsg_parallel_in_serial_out_passthrough #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter hi_to_lo_p = 0
)
( input clk_i
, input reset_i
// Data Input Channel
, input v_i
, input [els_p-1:0][width_p-1:0] data_i
, output ready_and_o
// Data Output Channel
, output v_o
, output [width_p-1:0] data_o
, input ready_and_i
);
logic [els_p-1:0] count_r;
// For single word piso, we're just passing through the signals
if (els_p == 1)
begin : single_word
assign count_r = 1'b1;
assign ready_and_o = ready_and_i;
end
else
begin : multi_word
logic last_word;
bsg_counter_clear_up_one_hot
#(.max_val_p(els_p-1), .init_val_p(1))
counter
(.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(ready_and_o & v_i)
,.up_i(v_o & ready_and_i & ~last_word)
,.count_r_o(count_r)
);
assign last_word = count_r[els_p-1];
assign ready_and_o = ready_and_i & last_word;
end
// If send hi_to_lo, reverse the input data array
logic [els_p-1:0][width_p-1:0] data_li;
if (hi_to_lo_p == 0)
begin: lo2hi
assign data_li = data_i;
end
else
begin: hi2lo
bsg_array_reverse
#(.width_p(width_p), .els_p(els_p))
bar
(.i(data_i)
,.o(data_li)
);
end
bsg_mux_one_hot
#(.width_p(width_p), .els_p(els_p))
data_mux
(.data_i(data_li)
,.sel_one_hot_i(count_r)
,.data_o(data_o)
);
assign v_o = v_i;
//synopsys translate_off
logic [els_p-1:0][width_p-1:0] initial_data_r;
bsg_dff_en
#(.width_p(width_p*els_p))
initial_data_reg
(.clk_i(clk_i)
,.en_i(count_r[0] & v_i)
,.data_i(data_i)
,.data_o(initial_data_r)
);
always_ff @(negedge clk_i)
begin
if (~reset_i & (count_r[0] === 1'b0))
begin
assert (v_i)
else $error("v_i must be held high during the entire PISO transaction");
assert (data_i == initial_data_r)
else $error("data_i must be held constant during the entire PISO transaction");
end
end
//synopsys translate_on
endmodule
| 8.851091 |
module bsg_pg_tree
#(parameter `BSG_INV_PARAM(input_width_p)
,parameter `BSG_INV_PARAM(output_width_p)
, parameter nodes_p=1
, parameter edges_lp=nodes_p*3
, parameter int l_edge_p [nodes_p-1:0] = '{0}
, parameter int r_edge_p [nodes_p-1:0] = '{0}
, parameter int o_edge_p [nodes_p-1:0] = '{0}
, parameter int node_type_p [nodes_p-1:0] = '{0}
// for physical placement or doing even/odd complementary logic per Fig 11.16b
// currently unimplemented
, parameter int row_p [nodes_p-1:0] = '{0}
)
(input [input_width_p-1:0] p_i
,input [input_width_p-1:0] g_i
,output [output_width_p-1:0] p_o
,output [output_width_p-1:0] g_o
);
wire [edges_lp-1:0] p;
wire [edges_lp-1:0] g;
// the input wires are placed at the start of the p and g arrays
assign p[input_width_p-1:0] = p_i;
assign g[input_width_p-1:0] = g_i;
// the output wires are at the end of the p and g arrays
assign p_o = p[edges_lp-1-:output_width_p];
assign g_o = g[edges_lp-1-:output_width_p];
genvar i;
for (i=0; i < nodes_p; i=i+1)
begin: rof
if (node_type_p[i] == 0) // so called "black cell" from Weste & Harris 4th ed
begin: blk // g[l_edge_p] should be assigned to faster input of AND gate
assign p[o_edge_p[i]] = p[l_edge_p[i]] | p[r_edge_p[i]];
assign g[o_edge_p[i]] = g[r_edge_p[i]] | (g[l_edge_p[i]] & p[r_edge_p[i]]);
end
else if (node_type_p[i] == 1) // "grey cell"
begin: gry // g[l_edge_p] should be assigned to faster input of AND gate
assign p[o_edge_p[i]] = `BSG_UNDEFINED_IN_SIM(0);
assign g[o_edge_p[i]] = g[r_edge_p[i]] | (g[l_edge_p[i]] & p[r_edge_p[i]]);
end
else if (node_type_p[i] == 2) // "black_buffer"
begin: bbuf // note: only takes left side!
assign p[o_edge_p[i]] = p[l_edge_p[i]];
assign g[o_edge_p[i]] = g[l_edge_p[i]];
end
else if (node_type_p[i] == 3) // "grey_buffer"
begin: gbuf // note: only takes left side!
assign p[o_edge_p[i]] = `BSG_UNDEFINED_IN_SIM(0);
assign g[o_edge_p[i]] = g[l_edge_p[i]];
end
else
begin
initial $error("unknown node_type: ",node_type_p[i]);
end
end
endmodule
| 7.126022 |
module bsg_popcount #(parameter `BSG_INV_PARAM(width_p))
(input [width_p-1:0] i
, output [$clog2(width_p+1)-1:0] o
);
// perf fixme: better to round up to nearest power of two and then
// recurse with side full and one side minimal
//
// e.g-> 80 -> 128/2 = 64 --> (64,16)
//
// possibly slightly better is to use 2^N-1:
//
// for items that are 5..7 bits wide, we make sure to
// split into a 4 and a 1/2/3; since the four is relatively optimized.
//
localparam first_half_lp = `BSG_MAX(4,width_p - (width_p >> 1));
localparam second_half_lp = width_p - first_half_lp;
if (width_p <= 3)
begin : lt3
assign o[0] = ^i;
if (width_p == 2)
assign o[1] = & i;
else
if (width_p == 3)
assign o[1] = (&i[1:0]) | (&i[2:1]) | (i[0]&i[2]);
end
else
// http://www.wseas.us/e-library/conferences/2006hangzhou/papers/531-262.pdf
if (width_p == 4)
begin : four
// half adders
wire [1:0] s0 = { ^i[3:2], ^i[1:0]};
wire [1:0] c0 = { &i[3:2], &i[1:0]};
// low bit is xor of all bits
assign o[0] = ^s0;
// middle bit is: ab ^ cd
// or (a^b) & (c^d)
assign o[1] = (^c0) | (&s0);
// high bit is and of all bits
assign o[2] = &c0;
end
else
begin : recurse
wire [$clog2(first_half_lp+1)-1:0] lo;
wire [$clog2(second_half_lp+1)-1:0] hi;
bsg_popcount #(.width_p(first_half_lp))
left(.i(i[0+:first_half_lp])
,.o(lo)
);
bsg_popcount #(.width_p(second_half_lp))
right(.i(i[first_half_lp+:second_half_lp])
,.o(hi)
);
assign o = lo+hi;
end
endmodule
| 7.152157 |
module converts between the valid-ready (input) and
// valid-credit (output) handshakes, by keeping the count of
// available credits
`include "bsg_defines.v"
module bsg_ready_to_credit_flow_converter #( parameter `BSG_INV_PARAM(credit_initial_p )
, parameter `BSG_INV_PARAM(credit_max_val_p )
, parameter decimation_p = 1
//local parameter
, parameter ptr_width_lp =
`BSG_WIDTH(credit_max_val_p)
)
( input clk_i
, input reset_i
, input v_i
, output ready_o
, output v_o
, input credit_i
);
// if toekens are used, up and down values would not be single bits anymore
localparam step_width_lp = `BSG_WIDTH(decimation_p);
logic [step_width_lp-1:0] up,down;
// credit_counter signal
logic [ptr_width_lp-1:0] credit_cnt;
// conversion between valid-credit and valid-credit protocols
// in case of reset, credit_cnt is not zero, so the ready
// and valid signals
assign ready_o = (credit_cnt!=0);
assign v_o = v_i & ready_o;
assign up = credit_i ? step_width_lp'($unsigned(decimation_p)) : step_width_lp'(0);
assign down = {{(step_width_lp-1){1'b0}},v_o};
// counter for credits. When each data is sent it goes down
// by 1 and when it receives a credit acknowledge it goes
// up. If other side of handshake has more buffer it can
// send some credit acknowledges at first to raise the limit
bsg_counter_up_down_variable #( .max_val_p(credit_max_val_p)
, .init_val_p(credit_initial_p)
, .max_step_p(decimation_p)
) credit_counter
( .clk_i(clk_i)
, .reset_i(reset_i)
, .up_i(up)
, .down_i(down)
, .count_o(credit_cnt)
);
endmodule
| 7.684328 |
module bsg_reduce #(parameter `BSG_INV_PARAM(width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter harden_p = 0
)
(input [width_p-1:0] i
, output o
);
// synopsys translate_off
initial
assert( $countones({xor_p & 1'b1, and_p & 1'b1, or_p & 1'b1}) == 1)
else $error("bsg_scan: only one function may be selected\n");
// synopsys translate_on
if (xor_p)
begin: xorr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = ^i;
end:xorr
else if (and_p)
begin: andr
if (width_p < 4)
begin: notmacro
assign o = &i;
end else
`bsg_andr_macro(4) else
`bsg_andr_macro(6) else
`bsg_andr_macro(8) else
`bsg_andr_macro(9) else
`bsg_andr_macro(12) else
`bsg_andr_macro(16) else
begin: notmacro
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = &i;
end
end
else if (or_p)
begin: orr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = |i;
end
endmodule
| 8.049333 |
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