code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module bsg_mem_2rw_sync_mask_write_bit #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p... | 7.889919 |
module bsg_mem_2rw_sync_mask_write_bit_synth #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter disable_collision_warning_p = 0
, parameter addr_wi... | 7.889919 |
module bsg_mem_2rw_sync_mask_write_byte #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=... | 7.889919 |
module bsg_mem_2rw_sync_mask_write_byte_synth #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter h... | 7.889919 |
module bsg_mem_2rw_sync_synth #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p=0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 1
... | 7.889919 |
module bsg_mem_3r1w #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input... | 7.36256 |
module bsg_mem_3r1w_sync #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0 // specifically write_then_read_p
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
... | 7.273086 |
module directly
// they should use bsg_mem_3r1w_sync.
`include "bsg_defines.v"
module bsg_mem_3r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input clk_i
, input ... | 7.532796 |
module bsg_mem_3r1w_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
)
(input w_clk_i
, input w_reset_i
, input w_v_i
, input [addr_width_lp-... | 7.273086 |
module bsg_mesh_stitch
import bsg_noc_pkg::*; // P=0, W, E, N, S
#(parameter `BSG_INV_PARAM(width_p ) // data width
, x_max_p = "inv"
, y_max_p = "inv"
, nets_p = 1 // optional parameter that allows for multiple networks to be routed together
)
(input [y_max_p-1:0][x_max_p-1:0][nets_p-1:0][S:... | 6.9857 |
module bsg_ml605_chipscope (
input clk_i
, input [255:0] data_i
);
logic [35:0] control_lo;
bsg_ml605_chipscope_icon icon (.CONTROL0(control_lo));
bsg_ml605_chipscope_ila ila (
.CONTROL(control_lo)
, .CLK(clk_i)
, .TRIG0(data_i)
);
endmodule
| 6.727543 |
module bsg_ml605_chipscope_icon (
CONTROL0
) /* synthesis syn_black_box syn_noprune=1 */;
output [35 : 0] CONTROL0;
endmodule
| 6.727543 |
module bsg_ml605_chipscope_ila (
CONTROL,
CLK,
TRIG0
) /* synthesis syn_black_box syn_noprune=1 */;
input [35 : 0] CONTROL;
input CLK;
input [255 : 0] TRIG0;
endmodule
| 6.727543 |
module bsg_ml605_chipset_pcie_to_vta (
input clk_i
, input reset_i
// pcie in
, input pcie_valid_i
, input [31:0] pcie_data_i
, output pcie_yumi_o
// pcie out
, output pcie_valid_o
, output [31:0] pcie_data_o
, input pcie_ready_i
// vta in
, input vta_valid_i
, input ... | 6.727543 |
module bsg_ml605_fmc_rx #(
parameter IODELAY_GRP = "IODELAY_FMC"
) (
input reset_i
, input clk_i
, input clk_200_mhz_i
, output clk_div_o
, output [87:0] data_o
, output cal_done_o
// fmc rx clk out
, output FMC_LPC_CLK0_M2C_P,
FMC_LPC_CLK0_M2C_N
// fmc rx clk in
, input ... | 6.911638 |
module bsg_ml605_fmc_rx_clk #(
parameter IODELAY_GRP = "IODELAY_FMC"
) (
input clk_p_i,
clk_n_i
, output clk_o
, output clk_div_o
);
logic ibufds_clk_lo, iodelay_clk_lo;
IBUFDS #(
.DIFF_TERM ("TRUE")
, .IOSTANDARD("LVDS_25")
) ibufds_clk_inst (
.I (clk_p_i),
... | 6.911638 |
module bsg_ml605_fmc_rx_data_bitslip_ctrl (
input clk_i
, input reset_i
, input [7:0] data_i
, output bitslip_o
, output done_o
);
logic [7:0] data_pattern;
assign data_pattern = 8'h2C;
enum logic [2:0] {
IDLE = 3'b001
,BITSLIP = 3'b010
,DONE = 3'b100
}
c_state, n_... | 6.911638 |
module bsg_ml605_fmc_tx (
input clk_i
, input clk_div_i
, input reset_i
, input [87:0] data_i
, output cal_done_o
// fmc tx clk out
, output FMC_LPC_LA17_CC_P,
FMC_LPC_LA17_CC_N
// fmc tx data out
, output FMC_LPC_LA31_P,
FMC_LPC_LA31_N
, output FMC_LPC_LA33_P,
FMC_LP... | 6.911638 |
module bsg_ml605_fmc_tx_clk (
input clk_i
, output clk_p_o,
clk_n_o
);
logic oddr_lo;
ODDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE")
, .INIT(1'b0)
, .SRTYPE("ASYNC")
) oddr_clk_inst (
.Q (oddr_lo)
, .C (clk_i)
, .CE(1'b1)
, .D1(1'b1)
, .D2(1'b0)
, .... | 6.911638 |
module bsg_ml605_fmc_tx_data (
input clk_i
, input clk_div_i
, input reset_i
, input [87:0] data_i
, output cal_done_o
, output [10:0] data_p_o,
data_n_o
);
logic [9:0] cnt_r;
always_ff @(posedge clk_div_i)
if (reset_i == 1'b1) cnt_r <= 10'd0;
else if (cnt_r < 10'd1023) cnt_r <... | 6.911638 |
module bsg_ml605_pcie_async_fifo #(
parameter channel_p = 2
)
// core clk
(
input core_clk_i
// core reset
, input core_reset_i
// core data in
, input [channel_p - 1 : 0] core_valid_i
, input [31:0] core_data_i[channel_p - 1 : 0]
, output [channel_p - 1 : 0] core_ready_o
// core dat... | 7.59322 |
module bsg_ml605_pio_ep_fifo #(
parameter I_WIDTH = 17
, parameter A_WIDTH = 10
, parameter LG_DEPTH = 3
) (
input clk
, input [I_WIDTH + A_WIDTH - 1:0] din
, input enque
, input deque
, input clear
, output [I_WIDTH + A_WIDTH - 1:0] dout
, output empty
, output full
... | 6.602304 |
module bsg_ml605_pio_ep_reset_ctrl #(
parameter reset_register_addr_p = "inv"
, parameter reset_register_data_p = "inv"
)
// clk
(
input clk_i
// reset
, input reset_i
// write port
, input wr_en_i
, input [10:0] wr_addr_i
, input [31:0] wr_data_i
// reset out
, output rese... | 6.602304 |
module bsg_mul #(parameter `BSG_INV_PARAM(width_p)
,harden_p=1
)
(input [width_p-1:0] x_i
, input [width_p-1:0] y_i
, input signed_i
, output [width_p*2-1:0] z_o
);
bsg_mul_pipelined #(.width_p (width_p )
,.pipeline_p(0 )
... | 7.341023 |
module for use with HardFloat's mulAddRecFN for
// easy absorption of pipeline stages by the DSPs that get
// synthesised in some FPGAs. This helps in retiming the
// paths in FPGA implementations as only immediate registers
// are absorbed, and global retiming does not seem to do this.
//
// For Zynq 7020, pipeline... | 6.836922 |
module bsg_mul_and_csa_block_hard #(parameter [31:0] blocks_p=1
)
( input [blocks_p-1:0] x_i
, input [blocks_p-1:0] y_i
, input [blocks_p-1:0] z_and1_i
, input [blocks_p-1:0] z_and2_i
, output [blocks_p-1:0] c_o
, output [blocks_p-1:0] s_o
);
`bsg_mul... | 6.587043 |
module bsg_mul_array #(parameter `BSG_INV_PARAM(width_p), `BSG_INV_PARAM(pipeline_p))
(
input clk_i
, input rst_i
, input v_i
, input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output logic [(width_p*2)-1:0] o
);
// connections between rows
logic [width_p-1:0] a_r [width_p-3:0];
lo... | 6.627847 |
module bsg_mul_array_row #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(row_idx_p)
, parameter `BSG_INV_PARAM(pipeline_p))
(
input clk_i
, input rst_i
, input v_i
, input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, input [w... | 6.627847 |
module bsg_mul_comp42 (
input [3:0] i // 0-2: early; 3: middle
, input cr_i // middle
, output cl_o // middle
, output c_o // late
, output s_o // late
);
wire tmp;
bsg_mul_csa csa_1 (
.x_i(i[0]),
.y_i(i[1]),
.z_i(i[2]),
.c_o(cl_o),
.s_o(tmp)
);
bsg_mul_c... | 6.614909 |
module bsg_mul_comp42_rep #(parameter `BSG_INV_PARAM(blocks_p))
(input [3:0][blocks_p-1:0] i
,input cr_i
,output cl_o
,output [blocks_p-1:0] c_o
,output [blocks_p-1:0] s_o
);
`bsg_mul_comp42_gen_macro(5)
else `bsg_mul_comp42_gen_macro(6)
else `bsg_mul_comp42_gen_macro(7)
else `bsg_mul_comp42_... | 6.614909 |
module bsg_mul_SDN #(
parameter width_p = 16,
parameter rows_lp = width_p / 2 + 1
) (
input [width_p-1:0] x_i
, input signed_i
, output [rows_lp-1:0][2:0] SDN_o
);
// we do not need to signed-extend temp_x on a
// signed multiply -- it just works out that way.
wir... | 7.265123 |
module bsg_mul_csa (
input x_i
, input y_i
, input z_i
, output c_o
, output s_o
);
assign {c_o, s_o} = x_i + y_i + z_i;
endmodule
| 7.036575 |
module bsg_dff_en_rep_rep #(
parameter blocks_p = 0
, width_p = 0
, group_vec_p = 0
, harden_p = 1
) (
input clk_i
, input en_i
, input [width_p-1:0] data_i
, output [width_p-1:0] data_o
);
genvar j;
for (j = 0; j < blocks_p; j = j + 1) begin : rof
localparam group_end_lp = (gr... | 6.610378 |
module bsg_mul_comp42_rep_rep #(
parameter blocks_p = 0
, width_p = 0
, group_vec_p = 0
, harden_p = 1
)
// we do this so that it is easy to combine vectors of results from blocks
(
input [3:0][width_p-1:0] i
, input cr_i
, output cl_o
, output [width_p-1:0] c_o
, output [width_p-1:... | 6.614909 |
module bsg_mul_B4B_rep_rep
#(parameter blocks_p = 1
, parameter width_p = 0
, parameter group_vec_p = 0
, parameter `BSG_INV_PARAM(y_p )
, parameter y_size_p = 16
, parameter S_above_vec_p = 0
, parameter dot_bar_vec_p = 0
, parameter B_vec_p = 0
, parameter ... | 8.780484 |
module bsg_mul_B4B_rep #(parameter [31:0] blocks_p=1
,parameter `BSG_INV_PARAM(y_p )
// size is required so VCS does not freak out
,parameter [31:0] y_size_p = 16
,parameter S_above_vec_p=0
... | 8.780484 |
module bsg_mul_green_booth_dots #(parameter `BSG_INV_PARAM(width_p)
, harden_p=0
, blocks_p="inv"
, group_vec_p="inv"
)
( input [1:0][2:0] SDN_i
, input [width_p-1:0] ... | 7.102958 |
module bsg_mul_synth #(parameter `BSG_INV_PARAM(width_p))
(
input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output logic [(2*width_p)-1:0] o
);
assign o = a_i * b_i;
endmodule
| 6.718167 |
module bsg_murn_converter
#(parameter `BSG_INV_PARAM(nodes_p)
, parameter `BSG_INV_PARAM(ring_width_p)
)
(
input clk_i
, input [nodes_p-1:0] reset_i
// to murn node
, input [nodes_p-1:0] v_i
, output [nodes_p-1:0] ready_o
, input [ring_width_p-1:0] data_i [nodes_p-1:0]
... | 9.902687 |
module bsg_mux #(
parameter width_p = "inv"
, els_p = 1
, harden_p = 0
, balanced_p = 0
, lg_els_lp = `BSG_SAFE_CLOG2(els_p)
) (
input [els_p-1:0][width_p-1:0] data_i
, input [lg_els_lp-1:0] sel_i
, output [width_p-1:0] data_o
);
if (els_p == 1) begin
assign data_o = data_i;
w... | 7.250766 |
module bsg_mux2_gatestack #(
width_p = "inv",
harden_p = 1
) (
input [width_p-1:0] i0
, input [width_p-1:0] i1
, input [width_p-1:0] i2
, output [width_p-1:0] o
);
initial $display("%m: warning module not actually hardened.");
genvar j;
for (j = 0; j < width_p; j = j + 1) begin
... | 6.945715 |
module bsg_mux2_gatestack_width_p2_harden_p1 (
i0,
i1,
i2,
o
);
input [1:0] i0;
input [1:0] i1;
input [1:0] i2;
output [1:0] o;
wire [1:0] o;
wire N0, N1, N2, N3;
assign o[0] = (N0) ? i1[0] : (N2) ? i0[0] : 1'b0;
assign N0 = i2[0];
assign o[1] = (N1) ? i1[1] : (N3) ? i0[1] : 1'b0;
... | 6.945715 |
module bsg_mux2_gatestack_width_p3_harden_p1 (
i0,
i1,
i2,
o
);
input [2:0] i0;
input [2:0] i1;
input [2:0] i2;
output [2:0] o;
wire [2:0] o;
wire N0, N1, N2, N3, N4, N5;
assign o[0] = (N0) ? i1[0] : (N3) ? i0[0] : 1'b0;
assign N0 = i2[0];
assign o[1] = (N1) ? i1[1] : (N4) ? i0[1] :... | 6.945715 |
module bsg_mux2_gatestack_width_p9_harden_p1 (
i0,
i1,
i2,
o
);
input [8:0] i0;
input [8:0] i1;
input [8:0] i2;
output [8:0] o;
wire [8:0] o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17;
assign o[0] = (N0) ? i1[0] : (N9) ? i0[0] : 1'b0;
assign N0 ... | 6.945715 |
module bsg_muxi2_gatestack #(
width_p = "inv",
harden_p = 1
) (
input [width_p-1:0] i0
, input [width_p-1:0] i1
, input [width_p-1:0] i2
, output [width_p-1:0] o
);
initial $display("%m: warning module not actually hardened.");
genvar j;
for (j = 0; j < width_p; j = j + 1) begin
... | 7.211486 |
module bsg_muxi2_gatestack_width_p5_harden_p1 (
i0,
i1,
i2,
o
);
input [4:0] i0;
input [4:0] i1;
input [4:0] i2;
output [4:0] o;
wire [4:0] o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14;
assign N6 = (N0) ? i1[0] : (N5) ? i0[0] : 1'b0;
assign N0 = i2[0];
a... | 7.211486 |
module bsg_mux_bitwise #(parameter `BSG_INV_PARAM(width_p ))
( input [width_p-1:0] select
, input [width_p-1:0] A
, input [width_p-1:0] B
, output logic [width_p-1:0] out
);
inte... | 7.04739 |
module has stages of mux which interleaves input data.
* Output data width is same as the input data width.
* The unit of swapping increases in higher stage.
*
* The lowest order bit swaps odd and even words
* the highest order bit swaps the upper half of all
* the words and the lower half of all the words. ... | 7.361155 |
module bsg_mux_one_hot #(parameter `BSG_INV_PARAM(width_p)
, els_p=1
, harden_p=1
)
(
input [els_p-1:0][width_p-1:0] data_i
,input [els_p-1:0] sel_one_hot_i
,output [width_p-1:0] data_o
);
wire [els_p-1:0][width_p-1:0] data_masked;
genva... | 6.691649 |
module bsg_mux_one_hot_width_p10_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [19:0] data_i;
input [1:0] sel_one_hot_i;
output [9:0] data_o;
wire [ 9:0] data_o;
wire [19:0] data_masked;
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[... | 6.691649 |
module bsg_mux_one_hot_width_p1_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [0:0] data_i;
input [0:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule
| 6.691649 |
module bsg_mux_one_hot_width_p1_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [1:0] data_i;
input [1:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
wire [1:0] data_masked;
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[1];
... | 6.691649 |
module bsg_mux_one_hot_width_p32_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [31:0] data_i;
input [0:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
assign data_o[31] = data_i[31] & sel_one_hot_i[0];
assign data_o[30] = data_i[30] & sel_one_hot_i[0];
assign data_o[29] = data_i... | 6.691649 |
module bsg_mux_one_hot_width_p41_els_p1 (
data_i,
sel_one_hot_i,
data_o
);
input [40:0] data_i;
input [0:0] sel_one_hot_i;
output [40:0] data_o;
wire [40:0] data_o;
assign data_o[40] = data_i[40] & sel_one_hot_i[0];
assign data_o[39] = data_i[39] & sel_one_hot_i[0];
assign data_o[38] = data_i... | 6.691649 |
module bsg_mux_one_hot_width_p4_els_p2 (
data_i,
sel_one_hot_i,
data_o
);
input [7:0] data_i;
input [1:0] sel_one_hot_i;
output [3:0] data_o;
wire [3:0] data_o;
wire [7:0] data_masked;
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
... | 6.691649 |
module bsg_mux_one_hot_width_p9_els_p3 (
data_i,
sel_one_hot_i,
data_o
);
input [26:0] data_i;
input [2:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8;
wire [26:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign da... | 6.691649 |
module bsg_mux_one_hot_width_p9_els_p4 (
data_i,
sel_one_hot_i,
data_o
);
input [35:0] data_i;
input [3:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17;
wire [35:0] data_masked;
assign data_masked[8]... | 6.691649 |
module bsg_mux_segmented #(parameter `BSG_INV_PARAM(segments_p)
,parameter `BSG_INV_PARAM(segment_width_p)
,parameter data_width_lp=segments_p*segment_width_p)
(
input [data_width_lp-1:0] data0_i
,input [data_width_lp-1:0] data1_i
,input [segments_p-1:0] sel_i
... | 6.641883 |
module bsg_mux_segmented_segments_p5_segment_width_p128 (
data0_i,
data1_i,
sel_i,
data_o
);
input [639:0] data0_i;
input [639:0] data1_i;
input [4:0] sel_i;
output [639:0] data_o;
wire [639:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9;
assign data_o[127:0] = (N0) ? data1_i[127:... | 6.641883 |
module bsg_mux_segmented_segments_p5_segment_width_p64 (
data0_i,
data1_i,
sel_i,
data_o
);
input [319:0] data0_i;
input [319:0] data1_i;
input [4:0] sel_i;
output [319:0] data_o;
wire [319:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9;
assign data_o[63:0] = (N0) ? data1_i[63:0] ... | 6.641883 |
module bsg_mux_segmented_segments_p8_segment_width_p8 (
data0_i,
data1_i,
sel_i,
data_o
);
input [63:0] data0_i;
input [63:0] data1_i;
input [7:0] sel_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15;
assign data_o[7:0]... | 6.641883 |
module bsg_nand_width_p5_harden_p1 (
a_i,
b_i,
o
);
input [4:0] a_i;
input [4:0] b_i;
output [4:0] o;
wire [4:0] o;
wire N0, N1, N2, N3, N4;
assign o[4] = ~N0;
assign N0 = a_i[4] & b_i[4];
assign o[3] = ~N1;
assign N1 = a_i[3] & b_i[3];
assign o[2] = ~N2;
assign N2 = a_i[2] & b_... | 6.856627 |
module bsg_nasti_client_resp (
clk_i,
reset_i,
nasti_r_valid_o,
nasti_r_data_o,
nasti_r_ready_i,
resp_valid_i,
resp_data_i,
resp_yumi_o
);
output [72:0] nasti_r_data_o;
input [72:0] resp_data_i;
input clk_i;
input reset_i;
input nasti_r_ready_i;
input resp_valid_i;
output ... | 6.750039 |
module instantiates num_nodes_p two-element-fifos in chains
// It supports multiple bsg_noc_links in parallel
//
// Insert this module into long routings on chip, which can become critical path
//
// Node that side_A_reset_i signal shoule be close to side A
// If reset happens to be close to side B, please swap side A ... | 7.670485 |
module bsg_nonsynth_ascii_writer
#(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(values_p )
, parameter `BSG_INV_PARAM(filename_p )
, parameter fopen_param_p = "w"
, parameter format_p = "%x ")
(input clk
, input reset_i
, input valid_i
, input [width_p*values_p... | 7.918385 |
module bsg_nonsynth_axil_to_dpi
#(parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
)
(input aclk_i
, input aresetn_i
, input [addr_width_p-1:0] awaddr_i
, input [2:0] awprot_i
, input ... | 7.918385 |
module bsg_nonsynth_cache_axe_tracer
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(ways_p)
, parameter sbuf_entry_width_lp=`bsg_cache_sbuf_entry_width(addr_width_p,data_width_p,ways_p)
)
(
input clk_i
, i... | 7.918385 |
module bsg_nonsynth_clk_watcher #(
tolerance_p = 0
) (
input clk_i
);
longint my_ticks_posedge = 0;
longint my_ticks_negedge = 0;
longint last_posedge = -1;
longint last_negedge = -1;
longint cycles_posedge = -1;
longint cycles_negedge = -1;
longint temp_time;
always @(posedge clk_i) begin
... | 7.918385 |
module bsg_nonsynth_clock_gen
#(parameter `BSG_INV_PARAM(cycle_time_p))
(output bit o);
`ifndef VERILATOR
initial begin
$display("%m with cycle_time_p ",cycle_time_p);
assert(cycle_time_p >= 2)
else $error("cannot simulate cycle time less than 2");
end
always #(cycle_time_p/2.0) begin
... | 7.918385 |
module is a basic non-synthesizable clock generator. This module is
// designed to be used with VCS and can be changed at runtime rather than
// compile time. To set the speed of the clock, add the following flag when
// executing the simulation binary:
//
// ./simv +clock-period=<period>
//
// If no flag is added t... | 7.308399 |
module bsg_nonsynth_delay_line # (parameter width_p=1
,parameter `BSG_INV_PARAM(delay_p))
(input [width_p-1:0] i
, output logic [width_p-1:0] o
);
always @(i)
o <= #(delay_p) i;
endmodule
| 7.918385 |
module and specify the clock period as a
// parameter. In Verilator, this is not possible because the module
// uses an unsupported delay statement. It's also more challenging
// (though not impossible) to have multiple clock domains.
//
// What I've done is create a drop-in replacement that is backed by a
// C++ API, ... | 7.568142 |
modules defines a DPI interface for a counter that can be read
// periodically using DPI
`include "bsg_defines.v"
module bsg_nonsynth_dpi_cycle_counter
#(
parameter int width_p = 1
,parameter bit debug_p = 0
)
(
input clk_i
,input reset_i
,output logic [width_p-1:0] ctr_r_o
,output l... | 7.747359 |
module bsg_nonsynth_dpi_to_axil
#(parameter `BSG_INV_PARAM(addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
)
(input aclk_i
, input aresetn_i
, output logic [addr_width_p-1:0] awaddr_o
, output logic [2:0] ... | 7.918385 |
module bsg_nonsynth_dramsim3_map
import bsg_dramsim3_pkg::*;
#(parameter `BSG_INV_PARAM(channel_addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter `BSG_INV_PARAM(num_columns_p)
, parameter `BSG_INV_PARAM(num_rows_p)
, parameter `BSG_INV_... | 7.918385 |
module bsg_nonsynth_dramsim3_unmap
import bsg_dramsim3_pkg::*;
#(parameter `BSG_INV_PARAM(channel_addr_width_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(num_channels_p)
, parameter `BSG_INV_PARAM(num_columns_p)
, parameter `BSG_INV_PARAM(num_rows_p)
, parameter `BSG_IN... | 7.918385 |
module bsg_nonsynth_manycore_packet_printer #(
// maximum number of outstanding words
freeze_init_p = 1'b1
, x_cord_width_p = "inv"
, y_cord_width_p = "inv"
, addr_width_p = "inv"
, data_width_p = "inv"
, debug_p = 1
, packet_width_lp =
`bsg_manycore_packet_width(addr_width_p, data_w... | 7.918385 |
module bsg_nonsynth_manycore_tag_master
import bsg_tag_pkg::*;
import bsg_noc_pkg::*;
#(parameter `BSG_INV_PARAM(num_pods_x_p)
, parameter `BSG_INV_PARAM(num_pods_y_p)
, parameter `BSG_INV_PARAM(wh_cord_width_p)
)
(
input clk_i
, input reset_i
// done signal for peripherals
, output ... | 7.918385 |
module bsg_nonsynth_mem_1r1w_sync_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
,... | 7.918385 |
module bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CL... | 7.918385 |
module bsg_nonsynth_mem_1rw_sync_assoc
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
)
(
input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_p-1:0] addr_i
, input v_i
, input w_i
, output logic [width_p-1:0] data_o
);
w... | 7.918385 |
module bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc
#(parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter write_mask_width_lp=(data_width_p>>3)
)
(
input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_p-1:0] addr_i
, i... | 7.918385 |
module bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter `BSG_INV_PARAM(id_p)
, parameter data_width_in_bytes_lp=(width_p>>3)
, parameter write_mask_width_lp=data_width_in_bytes_lp
, parameter addr_width_lp=`BSG_SAFE_CLO... | 7.918385 |
module generates a stream of random numbers with seed specified
as a parameter. Since the value of the seed is provided as a parameter,
each instantiation of this module produces a pre-determined stream making
it easy to reproduce the sequence.
Next random number is generated after every clock cycle if yumi_i is
as... | 6.670138 |
module bsg_nonsynth_random_yumi_gen
#(parameter `BSG_INV_PARAM(yumi_min_delay_p)
, parameter `BSG_INV_PARAM(yumi_max_delay_p)
)
(
input clk_i
, input reset_i
, input v_i
, output logic yumi_o
);
integer yumi_count_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
... | 7.918385 |
module bsg_nonsynth_reset_gen #(parameter num_clocks_p=1
, parameter `BSG_INV_PARAM(reset_cycles_lo_p)
, parameter `BSG_INV_PARAM(reset_cycles_hi_p))
(input bit [num_clocks_p-1:0] clk_i
, output bit async_reset_o);
genvar i;
... | 7.918385 |
module bsg_nonsynth_test_rom
#(parameter `BSG_INV_PARAM(filename_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
, parameter hex_not_bin_p = 0
)
(
input [addr_width_p-1:0] addr_i
, output logic [data_width_p-1:0] data_o
);
localparam els_lp = 2**addr_w... | 7.918385 |
module bsg_nonsynth_triwire #
(parameter `BSG_INV_PARAM(width_p)
,parameter real transport_delay_p = 0.0)
(inout [width_p-1:0] a
,inout [width_p-1:0] b);
// This initialization to z is important to prevent the signal from being
// alway x
logic [width_p-1:0] a_dly = 'bz;
logic [width_p-1:0] b_dly = 'bz... | 7.918385 |
module bsg_nonsynth_val_watcher_1p #(
string_p = "unknown",
trigger_val_p = -1,
val_size_p = 32,
one_time_trigger_p = 1'b1,
p1_width_p = 32,
extra_p = 1
) (
input clk_i
, input reset_i
, input [val_size_p-1:0] val_i
, input [p1_width_p-1:0] p1_i
);
logic triggered_r, triggered... | 7.918385 |
module bsg_nor2 #(parameter `BSG_INV_PARAM(width_p)
, harden_p=1)
(input [width_p-1:0] a_i
, input [width_p-1:0] b_i
, output [width_p-1:0] o
);
assign o = ~(a_i | b_i );
endmodule
| 7.552459 |
module bsg_nor3_width_p4_harden_p1 (
a_i,
b_i,
c_i,
o
);
input [3:0] a_i;
input [3:0] b_i;
input [3:0] c_i;
output [3:0] o;
wire [3:0] o;
wire N0, N1, N2, N3, N4, N5, N6, N7;
assign o[3] = ~N1;
assign N1 = N0 | c_i[3];
assign N0 = a_i[3] | b_i[3];
assign o[2] = ~N3;
assign N3 ... | 7.158871 |
module bsg_oddr_phy_90 #(
parameter width_p = "inv"
) (
input reset_i
, input clk_2x_i
, input [2*width_p-1:0] data_i
, output logic [width_p-1:0] data_r_o
, output logic clk_r_o
);
logic odd, clk;
logic [2*width_p-1:0] data_90;
always @(negedge clk_2x_i) data_90 <= data_i;
always @(p... | 6.738984 |
module bsg_oddr_phy_180 #(
parameter width_p = "inv"
) (
input reset_i
, input clk_2x_i
, input [2*width_p-1:0] data_i
, output logic [width_p-1:0] data_r_o
, output logic clk_r_o
);
logic odd, clk;
logic [2*width_p-1:0] data_180;
always @(posedge clk_2x_i) data_180 <= data_i;
always ... | 6.738984 |
module.
//
`include "bsg_defines.v"
module bsg_one_fifo #(parameter width_p="inv"
)
(input clk_i
, input reset_i
// input side
, output ready_o // early
, input [width_p-1:0] data_i // late
, input v_i // late
// output side
, outp... | 7.709861 |
module bsg_parallel_in_serial_out_dynamic
#(parameter `BSG_INV_PARAM(width_p)
,parameter `BSG_INV_PARAM(max_els_p)
,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
)
(input clk_i
,input reset_i
// Input side
,input v_i
,input... | 8.202302 |
module is helpful on both sides.
// Note:
// A transaction starts when ready_and_o & v_i. data_i must
// stay constant for the entirety of the transaction until
// ready_and_o is asserted.
// This may make the module incompatible with upstream modules that
// multiplex multiple inputs and can change whi... | 8.851091 |
module bsg_pg_tree
#(parameter `BSG_INV_PARAM(input_width_p)
,parameter `BSG_INV_PARAM(output_width_p)
, parameter nodes_p=1
, parameter edges_lp=nodes_p*3
, parameter int l_edge_p [nodes_p-1:0] = '{0}
, parameter int r_edge_p [nodes_p-1:0] = '{0}
, parameter int o_edge_p [nodes_p-1:0] = '... | 7.126022 |
module bsg_popcount #(parameter `BSG_INV_PARAM(width_p))
(input [width_p-1:0] i
, output [$clog2(width_p+1)-1:0] o
);
// perf fixme: better to round up to nearest power of two and then
// recurse with side full and one side minimal
//
// e.g-> 80 -> 128/2 = 64 --> (64,16)
//
// possibly sl... | 7.152157 |
module converts between the valid-ready (input) and
// valid-credit (output) handshakes, by keeping the count of
// available credits
`include "bsg_defines.v"
module bsg_ready_to_credit_flow_converter #( parameter `BSG_INV_PARAM(credit_initial_p )
, parameter `BSG_INV_PARAM... | 7.684328 |
module bsg_reduce #(parameter `BSG_INV_PARAM(width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter harden_p = 0
)
(input [width_p-1:0] i
, output o
);
// synopsys translate_off
... | 8.049333 |
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