code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BufferSerial (
clk,
rst,
wr_en,
buf_full,
buf_in,
buf_out
);
input clk, rst;
input wr_en;
input [`width-1:0] buf_in;
output [`buf_size*`width-1:0] buf_out;
output reg buf_full;
reg[`buf_width-1:0] fifo_counter;
reg[`buf_width-1:0] wr_ptr;
reg[`width-1:0] buf_mem[`buf_size-1:0];
always @(fifo_counter) begin
buf_full = (fifo_counter == `buf_size);
end
always @(posedge clk) begin
if (rst) fifo_counter <= 0;
else if (!buf_full && wr_en) fifo_counter <= fifo_counter + `buf_width'd1;
else fifo_counter <= fifo_counter;
end
always @(posedge clk) begin
if (wr_en && !buf_full) buf_mem[wr_ptr] <= buf_in;
else buf_mem[wr_ptr] <= buf_mem[wr_ptr];
end
always @(posedge clk) begin
if (rst) wr_ptr <= 0;
else begin
if (!buf_full && wr_en) wr_ptr <= wr_ptr + `buf_width'd1;
else wr_ptr <= wr_ptr;
end
end
genvar pk_idx;
generate
for (pk_idx = 0; pk_idx < (`buf_size); pk_idx = pk_idx + 1) begin : buffer
assign buf_out[((`width)*pk_idx+((`width)-1)):((`width)*pk_idx)] = (buf_full) ? buf_mem[pk_idx][((`width)-1):0] : `width'd0;
end
endgenerate
endmodule
| 6.725941 |
module SNPS_CLOCK_GATE_HIGH_BufferTest_0 (
CLK,
EN,
ENCLK,
TE
);
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2 latch (
.E (EN),
.SE (TE),
.CK (CLK),
.ECK(ENCLK)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_BufferTest_1 (
CLK,
EN,
ENCLK,
TE
);
input CLK, EN, TE;
output ENCLK;
wire n2;
assign n2 = CLK;
TLATNTSCAX2 latch (
.E (EN),
.SE (TE),
.CK (n2),
.ECK(ENCLK)
);
endmodule
| 6.575704 |
module SNPS_CLOCK_GATE_HIGH_BufferTest_2 (
CLK,
EN,
ENCLK,
TE
);
input CLK, EN, TE;
output ENCLK;
wire n2;
assign n2 = CLK;
TLATNTSCAX2 latch (
.E (EN),
.SE (TE),
.CK (n2),
.ECK(ENCLK)
);
endmodule
| 6.575704 |
module bufferWE #(
parameter N = 16
) (
input [N - 1:0] data_in,
input clk,
w_enable,
rst,
output reg [N - 1:0] data_out
);
always @(posedge clk, negedge rst) begin
if (!rst) data_out <= 0;
else if (w_enable) data_out <= data_in;
end
endmodule
| 8.159394 |
module bufferWE_fixture;
reg clk, rst, w_enable;
reg [15:0] data_in;
wire [15:0] data_out;
initial $vcdpluson;
initial
$monitor(
$time,
" data_in = %h data_out = %h w_enable = %b Reset = %b",
data_in,
data_out,
w_enable,
rst
);
bufferWE #(
.N(16)
) c1 (
.data_in(data_in),
.clk(clk),
.w_enable(w_enable),
.rst(rst),
.data_out(data_out)
);
initial begin
rst = 0;
w_enable = 0;
data_in = 0;
#10 rst = 1;
w_enable = 1;
data_in = 16'h0E20;
#10 rst = 0;
w_enable = 1;
data_in = 16'h0B21;
#10 rst = 1;
w_enable = 1;
data_in = 16'h0B21;
#10 rst = 0;
w_enable = 1;
data_in = 16'h2388;
end
initial begin
clk = 1'b0;
forever #10 clk = ~clk;
end
initial begin
#100 $finish;
end
endmodule
| 6.63202 |
module Buffer_1 (
input clk,
input [31:0] Mux,
input [31:0] ADD_4,
input [31:0] Instruction_Memory,
output [31:0] PC,
output [31:0] ADD_ALU,
output [31:0] Register
);
assign PC = (clk) ? Mux : PC;
assign ADD_ALU = (clk) ? ADD_4 : ADD_ALU;
assign Register = (clk) ? Instruction_Memory : Register;
endmodule
| 6.929178 |
module buffer_16_12100_buffer_init_00 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_01 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_02 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_03 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_04 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_05 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_10 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_11 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_12 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_13 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_14 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_15 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_20 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_21 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_22 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_23 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_24 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_25 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_30 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_31 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_32 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_33 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_34 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_12100_buffer_init_35 (
input clk,
input wen,
input [13:0] waddr,
input [15:0] wdata,
input [13:0] raddr,
output [15:0] rdata
);
reg [13:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 7.192169 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 16;
parameter ADDR_WIDTH = 14;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_00 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_01 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_02 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_03 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_04 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_05 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_10 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_11 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_12 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_13 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_14 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_16_24200_buffer_init_15 (
input clk,
input wen,
input [14:0] waddr,
input [15:0] wdata,
input [14:0] raddr,
output [15:0] rdata
);
reg [14:0] raddr_reg;
reg [15:0] rdata_reg;
reg [15:0] pipeline_reg_0;
wire [15:0] rd_dummy_signal;
wire [15:0] wr_dummy_signal;
wire [15:0] rdata_wire;
assign rd_dummy_signal = 0;
always @(posedge clk) begin
rdata_reg <= rdata_wire;
raddr_reg <= raddr;
pipeline_reg_0 <= rdata_reg;
end
`ifdef SIMULATION_MEMORY
defparam u_dual_port_ram.DATA_WIDTH = 16; defparam u_dual_port_ram.ADDR_WIDTH = 15;
`endif
dual_port_ram u_dual_port_ram (
.addr1(waddr),
.we1 (wen),
.data1(wdata),
.out1 (wr_dummy_signal),
.addr2(raddr_reg),
.we2 (1'b0),
.data2(rd_dummy_signal),
.out2 (rdata_wire),
.clk (clk)
);
assign rdata = pipeline_reg_0;
endmodule
| 6.6434 |
module dual_port_ram (
clk,
addr1,
addr2,
data1,
data2,
we1,
we2,
out1,
out2
);
parameter DATA_WIDTH = 256;
parameter ADDR_WIDTH = 10;
input clk;
input [ADDR_WIDTH-1:0] addr1;
input [ADDR_WIDTH-1:0] addr2;
input [DATA_WIDTH-1:0] data1;
input [DATA_WIDTH-1:0] data2;
input we1;
input we2;
output reg [DATA_WIDTH-1:0] out1;
output reg [DATA_WIDTH-1:0] out2;
reg [DATA_WIDTH-1:0] ram[ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we1) begin
ram[addr1] <= data1;
end else begin
out1 <= ram[addr1];
end
end
always @(posedge clk) begin
if (we2) begin
ram[addr2] <= data2;
end else begin
out2 <= ram[addr2];
end
end
endmodule
| 8.55547 |
module buffer_1loc (
input clk,
reset, // sync hign active reset
input re,
we, //read enable and write enable
input [`WIDTH - 1:0] data_in,
output [`WIDTH - 1:0] data_out,
output full,
empty
);
reg [`WIDTH - 1:0] mem; // memory location
// flag used to represent empty or full
// 0 means empty
// 1 means full
reg flag;
assign full = flag;
assign empty = ~flag;
wire re_ql, we_ql; // qualified write enable or read enable
assign re_ql = (re & flag);
assign we_ql = (we & !flag);
// sequential logic
always @(posedge clk) begin
if (reset) begin
flag <= 0; // initial state is empty
mem <= 0;
end else begin
// only one of re_pl and we_pl can be activated at the same clock
if (re_ql) flag <= 0;
else if (we_ql) begin
mem <= data_in;
flag <= 1;
end
end
end
assign data_out = mem;
endmodule
| 7.240569 |
module Buffer_2 (
input clk,
input [31:0] Mux_Arriba,
input Jump,
input [31:0] Shft_Left2,
input [31:0] ADD_4,
input Branch,
input MemRead,
input MemtoReg,
input ALUOp,
input MemWrite,
input ALUSrc,
input [31:0] Read_Data1,
input [31:0] Read_Data2,
input [5:0] Instruction_Memory,
input [31:0] SignExtend,
input [31:0] Mux_Abajo,
output [31:0] PC,
output MuxArriba,
output [31:0] Muxarriba,
output [31:0] ADD_ALU,
output AND,
output DataMemory,
output MuxAbajo,
output ALU_Control,
output Data_Memory,
output Mux_ALU,
output [31:0] ALU,
output [31:0] ALU_Mux,
output [5:0] ALUControl,
output [31:0] Shift_left2,
output [31:0] WriteData
);
assign Muxarriba = {ADD_4[31:28], Shft_Left2};
assign PC = (clk) ? Mux_Arriba : PC;
assign MuxArriba = (clk) ? Jump : MuxArriba;
assign Muxarriba = (clk) ? Shift_left2 : Muxarriba;
assign ADD_ALU = (clk) ? ADD_4 : ADD_ALU;
assign AND = (clk) ? Branch : AND;
assign DataMemory = (clk) ? MemRead : DataMemory;
assign MuxAbajo = (clk) ? MemtoReg : MuxAbajo;
assign ALU_Control = (clk) ? ALUOp : ALU_Control;
assign Data_Memory = (clk) ? MemWrite : Data_Memory;
assign Mux_ALU = (clk) ? ALUSrc : Mux_ALU;
assign ALU = (clk) ? Read_Data1 : ALU;
assign ALU_Mux = (clk) ? Read_Data2 : ALU_Mux;
assign ALUControl = (clk) ? Instruction_Memory : ALUControl;
assign Shift_left2 = (clk) ? SignExtend : Shift_left2;
assign WriteData = (clk) ? Mux_Abajo : WriteData;
endmodule
| 7.613911 |
module buffer_2l (
input wire clk, // main clock
input wire switch, // line switch
// data writing
input wire clk_w, // write clock
input wire en_w, // write enable
input wire [ADDR_BITS-1:0] addr_w, // address to write
input wire [DATA_BITS-1:0] data_w, // data to write
// data reading
input wire clk_r, // read clock
input wire [ADDR_BITS-1:0] addr_r, // address to read
output wire [DATA_BITS-1:0] data_r // data from read
);
parameter DATA_BITS = 32, // data length
ADDR_BITS = 8; // address length
reg line = 0; // write one line and read another line
reg [DATA_BITS-1:0] data_a[0:(1<<ADDR_BITS)-1];
reg [DATA_BITS-1:0] data_b[0:(1<<ADDR_BITS)-1];
reg [DATA_BITS-1:0] data_ra, data_rb;
always @(posedge clk) begin
if (switch) line <= ~line;
end
always @(posedge clk_w) begin
if (en_w) begin
if (line) data_b[addr_w] <= data_w;
else data_a[addr_w] <= data_w;
end
end
always @(posedge clk_r) begin
data_ra <= data_a[addr_r];
data_rb <= data_b[addr_r];
end
assign data_r = line ? data_ra : data_rb;
endmodule
| 7.038379 |
module Buffer_3 (
input clk,
input [31:0] Mux_Arriba,
input Jump,
input [31:0] Shift_left2,
input [31:0] ADD_4,
input [31:0] ADD_ALU,
input AND,
input MemRead,
input MemtoReg,
input MemWrite,
input [31:0] ALU,
input [31:0] Register,
input [31:0] Mux_Abajo,
output [31:0] PC,
output MuxArriba,
output [31:0] Muxarriba,
output [31:0] Mux_Mux,
output [31:0] mux_mux,
output MuxMux,
output DataMemory,
output MuxAbajo,
output Data_Memory,
output Memory_Address,
output Memory_Write,
output [31:0] WriteData
);
assign PC = (clk) ? Mux_Arriba : PC;
assign MuxArriba = (clk) ? Jump : MuxArriba;
assign Muxarriba = (clk) ? Shift_left2 : Muxarriba;
assign Mux_Mux = (clk) ? ADD_4 : Mux_Mux;
assign mux_mux = (clk) ? ADD_ALU : mux_mux;
assign MuxMux = (clk) ? AND : MuxMux;
assign DataMemory = (clk) ? MemRead : DataMemory;
assign MuxAbajo = (clk) ? MemtoReg : MuxAbajo;
assign Data_Memory = (clk) ? MemWrite : Data_Memory;
assign Memory_Address = (clk) ? ALU : Memory_Address;
assign Memory_Write = (clk) ? Register : Memory_Write;
assign WriteData = (clk) ? Mux_Abajo : WriteData;
endmodule
| 8.275535 |
module buffer_3line (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [7:0] taps0x;
output [7:0] taps1x;
output [7:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 aclr;
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [ 7:0] sub_wire0;
wire [ 23:0] sub_wire1;
wire [ 7:0] shiftout = sub_wire0[7:0];
wire [ 15:8] sub_wire5 = sub_wire1[15:8];
wire [23:16] sub_wire4 = sub_wire1[23:16];
wire [23:16] sub_wire3 = sub_wire4[23:16];
wire [ 7:0] sub_wire2 = sub_wire1[7:0];
wire [ 7:0] taps0x = sub_wire2[7:0];
wire [ 7:0] taps2x = sub_wire3[23:16];
wire [ 7:0] taps1x = sub_wire5[15:8];
altshift_taps ALTSHIFT_TAPS_component (
.aclr(aclr),
.clock(clock),
.clken(clken),
.shiftin(shiftin),
.shiftout(sub_wire0),
.taps(sub_wire1)
);
defparam ALTSHIFT_TAPS_component.intended_device_family = "Cyclone IV E",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M9K", ALTSHIFT_TAPS_component.lpm_type =
"altshift_taps", ALTSHIFT_TAPS_component.number_of_taps = 3,
ALTSHIFT_TAPS_component.tap_distance = 1920, ALTSHIFT_TAPS_component.width = 8;
endmodule
| 6.671863 |
module buffer_3line (
aclr,
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x,
taps2x
);
input aclr;
input clken;
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [7:0] taps0x;
output [7:0] taps1x;
output [7:0] taps2x;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 aclr;
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.671863 |
module Buffer_4 (
input clk,
input [31:0] Mux_Arriba,
input Jump,
input [31:0] Shift_left2,
input [31:0] Mux_Mux,
input MemtoReg,
input [31:0] Read_Memory,
input [31:0] ALU,
input [31:0] muxabajo,
output [31:0] PC,
output MuxArriba,
output [31:0] Muxarriba,
output [31:0] muxarriba,
output MuxAbajo,
output Mux_Abajo,
output [31:0] Muxabajo,
output [31:0] WriteData
);
assign PC = (clk) ? Mux_Arriba : PC;
assign MuxArriba = (clk) ? Jump : MuxArriba;
assign Muxarriba = (clk) ? Shift_left2 : Muxarriba;
assign muxarriba = (clk) ? Mux_Mux : muxarriba;
assign MuxAbajo = (clk) ? MemtoReg : MuxAbajo;
assign Mux_Abajo = (clk) ? Read_Memory : Mux_Abajo;
assign Muxabajo = (clk) ? ALU : Muxabajo;
assign WriteData = (clk) ? muxabajo : WriteData;
endmodule
| 8.381285 |
module buffer_a #(
parameter VAR_SIZE = 8,
parameter MMU_SIZE = 10
) (
output wire signed [(VAR_SIZE*MMU_SIZE-1):0] B1,
input wire signed [(VAR_SIZE-1):0] A,
input wire clk,
input wire rst_n,
input wire stop,
input wire [1:0] cmd,
input wire [4:0] buffer,
input wire [7:0] dim_x_in,
input wire [7:0] dim_y_in,
output wire [7:0] dim_x,
output wire [7:0] dim_y
);
buffer_a_4x #(
.VAR_SIZE(VAR_SIZE),
.MMU_SIZE(MMU_SIZE)
) m_buffer_a (
.B1(B1),
.A(A),
.clk(clk),
.rst_n(rst_n),
.stop(stop),
.cmd(cmd),
.buffer(buffer),
.dim_x_in(dim_x_in),
.dim_y_in(dim_y_in),
.dim_x_out(dim_x),
.dim_y_out(dim_y)
);
endmodule
| 7.072007 |
module buffer_b #(
parameter VAR_SIZE = 8,
parameter MMU_SIZE = 10
) (
output wire signed [(VAR_SIZE*MMU_SIZE-1):0] B1,
input wire signed [(VAR_SIZE-1):0] A,
input wire clk,
input wire rst_n,
input wire stop,
input wire [1:0] cmd,
input wire [4:0] buffer,
input wire [7:0] dim_x_in,
input wire [7:0] dim_y_in,
output wire [7:0] dim_x,
output wire [7:0] dim_y
);
buffer_b_4x #(
.VAR_SIZE(VAR_SIZE),
.MMU_SIZE(MMU_SIZE)
) m_buffer_b (
.B1(B1),
.A(A),
.clk(clk),
.rst_n(rst_n),
.stop(stop),
.cmd(cmd),
.buffer(buffer),
.dim_x_in(dim_x_in),
.dim_y_in(dim_y_in),
.dim_x_out(dim_x),
.dim_y_out(dim_y)
);
endmodule
| 6.884608 |
module buffer_chain #(
parameter DATA_BITWIDTH = 8,
parameter DEPTH = 16
) (
input clk,
input rst_n,
input [DATA_BITWIDTH-1:0] data_in,
input ready_in,
output done_in,
output [DATA_BITWIDTH-1:0] data_out,
output ready_out,
input done_out
);
genvar i;
generate
wire [DATA_BITWIDTH-1:0] data[0:DEPTH];
wire ready[0:DEPTH];
wire done[0:DEPTH];
assign data[0] = data_in;
assign ready[0] = ready_in;
assign done[0] = done_in;
assign data_out = data[DEPTH];
assign ready_out = ready[DEPTH];
assign done_out = done[DEPTH];
for (i = 0; i < DEPTH; i = i + 1) begin : block_buffer
buffer #(
.DATA_BITWIDTH(DATA_BITWIDTH)
) u_buffer (
.clk(clk),
.rst_n(rst_n),
.data_in(data[i]),
.ready_in(ready[i]),
.done_in(done[i]),
.data_out(data[i+1]),
.ready_out(ready[i+1]),
.done_out(done[i+1])
);
end
endgenerate
endmodule
| 7.035836 |
module buffer_dp (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = "buffer_dp",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.maximum_depth = 512,
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.540669 |
module buffer_dp (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q
);
input [7:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
| 6.687661 |
module buffer_dual_clk (
input wire clk,
input wire subclk,
input wire set,
input wire reset,
input wire enable,
input wire [bitwidth-1:0] data,
output reg [bitwidth-1:0] q = 0,
output reg avail = 0
);
parameter bitwidth = 24;
reg [bitwidth-1:0] buffer;
reg availbuffer;
always @(posedge clk) begin
if (reset) availbuffer <= 1'b0;
else if (set & enable) begin
buffer[bitwidth-1:0] <= data[bitwidth-1:0];
availbuffer <= 1'b1;
end
end
always @(posedge subclk) begin
avail <= availbuffer;
q <= buffer;
end
endmodule
| 6.818115 |
module buffer_gate (
input a,
output y
);
assign y = ~(~a);
endmodule
| 8.295417 |
module Buffer_h #(
parameter UNITS_NUM = 5,
parameter D_WL = 22,
parameter DEPTH = 26
) (
input clk,
input rst_n,
input w_en,
input [ 7:0] w_addr,
input [ 7:0] r_addr,
input [UNITS_NUM*D_WL-1:0] d_in,
output [ D_WL-1:0] d_o
);
reg [D_WL-1:0] mem[0:DEPTH-1];
integer i;
always @(posedge clk)
if (!rst_n) for (i = 0; i < DEPTH; i = i + 1) mem[i] <= 'h0;
else if (w_en) begin
mem[w_addr] <= d_in[D_WL-1:0];
mem[w_addr+1] <= d_in[D_WL*2-1:D_WL];
mem[w_addr+2] <= d_in[D_WL*3-1:D_WL*2];
mem[w_addr+3] <= d_in[D_WL*4-1:D_WL*3];
mem[w_addr+4] <= d_in[D_WL*5-1:D_WL*4];
end
assign d_o = mem[r_addr];
endmodule
| 6.889677 |
module buffer_int #(
parameter BUF_NUM = 0,
parameter BUF_SIZE = 9
) ( // Control Interface
input clk,
input rst,
input [31:0] ctrl_word,
input go,
output done,
output error,
output idle,
// Buffer Interface
output en_o,
output we_o,
output reg [BUF_SIZE-1:0] addr_o,
output [31:0] dat_to_buf,
input [31:0] dat_from_buf,
// Write FIFO Interface
input [31:0] wr_data_i,
input [3:0] wr_flags_i,
input wr_ready_i,
output wr_ready_o,
// Read FIFO Interface
output [31:0] rd_data_o,
output [3:0] rd_flags_o,
output rd_ready_o,
input rd_ready_i
);
reg [31:0] ctrl_reg;
reg go_reg;
always @(posedge clk) go_reg <= go;
always @(posedge clk)
if (rst) ctrl_reg <= 0;
else if (go & (ctrl_word[31:28] == BUF_NUM)) ctrl_reg <= ctrl_word;
wire [BUF_SIZE-1:0] firstline = ctrl_reg[BUF_SIZE-1:0];
wire [BUF_SIZE-1:0] lastline = ctrl_reg[2*BUF_SIZE-1:BUF_SIZE];
wire read = ctrl_reg[22];
wire write = ctrl_reg[23];
wire clear = ctrl_reg[24];
//wire [2:0] port = ctrl_reg[27:25]; // Ignored in this block
//wire [3:0] buff_num = ctrl_reg[31:28]; // Ignored here ?
localparam IDLE = 3'd0;
localparam PRE_READ = 3'd1;
localparam READING = 3'd2;
localparam WRITING = 3'd3;
localparam ERROR = 3'd4;
localparam DONE = 3'd5;
reg [2:0] state;
reg rd_sop, rd_eop;
wire wr_sop, wr_eop, wr_error;
reg [1:0] rd_occ;
wire [1:0] wr_occ;
always @(posedge clk)
if (rst) begin
state <= IDLE;
rd_sop <= 0;
rd_eop <= 0;
rd_occ <= 0;
end else if (clear) begin
state <= IDLE;
rd_sop <= 0;
rd_eop <= 0;
rd_occ <= 0;
end else
case (state)
IDLE:
if (go_reg & read) begin
addr_o <= firstline;
state <= PRE_READ;
end else if (go_reg & write) begin
addr_o <= firstline;
state <= WRITING;
end
PRE_READ: begin
state <= READING;
addr_o <= addr_o + 1;
rd_occ <= 2'b00;
rd_sop <= 1;
rd_eop <= 0;
end
READING:
if (rd_ready_i) begin
rd_sop <= 0;
addr_o <= addr_o + 1;
if (addr_o == lastline) begin
rd_eop <= 1;
// FIXME assign occ here
rd_occ <= 0;
end else rd_eop <= 0;
if (rd_eop) state <= DONE;
end
WRITING: begin
if (wr_ready_i) begin
addr_o <= addr_o + 1;
if (wr_error) begin
state <= ERROR;
// Save OCC flags here
end else if ((addr_o == lastline) || wr_eop) state <= DONE;
end // if (wr_ready_i)
end // case: WRITING
endcase // case(state)
assign dat_to_buf = wr_data_i;
assign rd_data_o = dat_from_buf;
assign rd_flags_o = {rd_occ[1:0], rd_eop, rd_sop};
assign rd_ready_o = (state == READING);
assign wr_sop = wr_flags_i[0];
assign wr_eop = wr_flags_i[1];
assign wr_occ = wr_flags_i[3:2];
assign wr_error = wr_sop & wr_eop;
assign wr_ready_o = (state == WRITING);
assign we_o = (state == WRITING);
//assign we_o = (state == WRITING) && wr_ready_i; // always write to avoid timing issue
assign en_o = ~((state == READING) & ~rd_ready_i); // FIXME potential critical path
assign done = (state == DONE);
assign error = (state == ERROR);
assign idle = (state == IDLE);
endmodule
| 6.573754 |
module buffer_mod (
input clk,
spkr_done,
buffer_updated,
output reg spkr_update
);
// sets speaker_update high when speaker done signal goes high. When signal is awknowledged, it goes low again.
always @(posedge clk)
if (spkr_done) spkr_update <= 1;
else if (buffer_updated) spkr_update <= 0;
endmodule
| 6.637995 |
module buffer_ram_dp #(
parameter AW = 15, // Cantidad de bits de la direccin
parameter DW = 8, // cantidad de Bits de los datos
parameter imageFILE = "./image.men"
) (
input clk_w,
input [AW-1:0] addr_in,
input [DW-1:0] data_in,
input regwrite,
input clk_r,
input [AW-1:0] addr_out,
output reg [DW-1:0] data_out
);
// Calcular el nmero de posiciones totales de memoria
localparam NPOS = 2 ** AW; // Memoria
reg [DW-1:0] ram[0:NPOS-1];
// escritura de la memoria port 1
always @(posedge clk_w) begin
if (regwrite == 1) ram[addr_in] <= data_in;
end
// Lectura de la memoria port 2
always @(posedge clk_r) begin
data_out <= ram[addr_out];
end
initial begin
$readmemh(imageFILE, ram);
ram[15'b111111111111111] = 8'b11111111;
end
endmodule
| 8.279495 |
module buffer_testbench;
parameter DATA_WIDTH = 8;
parameter BUFFER_LENGTH = 5;
reg clk;
reg [DATA_WIDTH-1:0] in_data;
wire [DATA_WIDTH-1:0] out_data;
reg do_shift;
integer i;
buffer #(
.DATA_WIDTH(DATA_WIDTH),
.BUFFER_LENGTH(BUFFER_LENGTH)
) dut (
.clk(clk),
.in_data(in_data),
.out_data(out_data),
.do_shift(do_shift)
);
always #5 clk = ~clk;
initial begin : main
integer fd;
fd = $fopen("buffer_contains.txt", "w");
$dumpfile("buffer_testbench.vcd");
$dumpvars;
{clk, do_shift} = 0;
in_data = 'hz;
repeat (2) @(posedge clk);
do_shift = #5 1;
for (i = 0; i < BUFFER_LENGTH; i = i + 1) begin
repeat (1)
@(posedge clk) begin
in_data = i * 3;
end
end
repeat (1) @(posedge clk);
in_data = 'hz;
do_shift = 0;
for (i = 0; i < BUFFER_LENGTH; i = i + 1) begin
$fwrite(fd, "[%d]", dut.shifter[i]);
if ((i + 1) % 8 == 0) begin
$fwrite(fd, "\n");
end
end
$fclose(fd);
repeat (2) @(posedge clk);
do_shift = 1;
repeat (BUFFER_LENGTH) @(posedge clk);
#20 $finish;
end
endmodule
| 6.554918 |
module buffer_tri (
in, // Input bus
out, // Output bus
en // Enable line that determines whether the output = input or high impedance
);
/*********************/
/* Module parameters */
/*********************/
parameter BUS_WIDTH = 32;
/*************************/
/* Declaring input ports */
/*************************/
input wire [BUS_WIDTH-1:0] in;
input wire en;
/**************************/
/* Declaring output ports */
/**************************/
output wire [BUS_WIDTH-1:0] out;
/**************/
/* Out driver */
/**************/
assign out = en ? in : {(BUS_WIDTH) {1'bz}};
endmodule
| 7.856392 |
module buffer_tri_tb;
/*****************************/
/* Variables for Input Ports */
/*****************************/
reg [31:0] in;
reg en;
/******************************/
/* Variables for Output Ports */
/******************************/
wire [31:0] out;
/*****************/
/* Instanciation */
/*****************/
buffer_tri buff (
.in (in),
.out(out),
.en (en)
);
/***********/
/* Initial */
/***********/
initial begin
in = 32'h0000FFFF;
en = 0;
#1;
in = 32'h0000FFFF;
en = 1;
#1;
in = 32'hFFFF0000;
en = 0;
#1;
in = 32'hFFFF0000;
en = 1;
#1;
end
endmodule
| 6.649631 |
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