code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BypassCrossingWire (
WGET,
WVAL
);
parameter width = 1;
input [width - 1 : 0] WVAL;
output [width - 1 : 0] WGET;
assign WGET = WVAL;
endmodule
| 7.331414 |
module bypass_bit (
input clk,
bitin,
output bitout
);
always @(posedge clk) begin
assign bitout = bitin;
end
endmodule
| 8.084678 |
module working at EX
//correct RF's output data, which will be used as ALU's operand or DataMem's din
module ByPassingEX(
//current instruction
input[4:0] EX_rs,
input[4:0] EX_rt,
//previous instruction(now at MEM)
input MEM_RegWrite,
input[1:0] MEM_RegSrc,
input[4:0] MEM_WriteReg,
//pre... | 8.695516 |
module working at ID
//correct RF's output, which will be used in Branch(beq, bne) or Jump(jr, jalr)
module ByPassingID(
//current instruction
input[4:0] ID_rs,
input[4:0] ID_rt,
input[1:0] ID_Branch,
input[1:0] ID_Jump,
//previous instruction(now at EX)
input EX_RegWrite,
input[1:0] EX_... | 7.230412 |
module bypassLogic (
MW_regWrite,
XM_regWrite,
XM_MemWrite,
MW_MemToReg,
DX_rs,
DX_rt,
XM_rd,
MW_rd,
rs,
rd,
ALUinA,
ALUinB,
muxM,
muxBranchA,
muxBranchB,
bexMux,
jrMux
);
input MW_regWrite, XM_MemWrite, MW_MemToReg, XM_regWrite;
input [4:0] DX_rs... | 8.827058 |
module BypassWire (
WGET,
WVAL
);
parameter width = 1;
input [width - 1 : 0] WVAL;
output [width - 1 : 0] WGET;
assign WGET = WVAL;
endmodule
| 6.997804 |
module bypass_32b (
A32,
TYPESEL,
R32
);
input [31:0] A32;
input [2:0] TYPESEL;
output [31:0] R32;
wire [31:0] A32;
wire [ 2:0] TYPESEL;
wire [31:0] R32;
wire [15:0] real_a32;
wire [15:0] imag_a32;
wire [15:0] real_r32;
wire [15:0] imag_r32;
wire [15:0] mux0out;
wire [15:0] mux1ou... | 7.600681 |
module Bypass_Always (
input [7:0] Input_Data,
output reg [7:0] Output_Data
);
//Definition for Variables in the module
//Logical
always @(*) begin
Output_Data <= Input_Data;
end
endmodule
| 8.558605 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-17-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module by_mux #(
parameter WIDTH = 1
) (
d_in_0,
d_in_1,
d_in_2,
d_out,
addr
);
input [WIDTH-1:0] d_in_0;
input [WIDTH-1:0] d_in_1;
input [WIDTH-1:0] d_in_2;
input [1:0] addr;
output reg [31:0] d_out;
always @* begin
casez (addr)
0: d_out <= d_in_0;
1: d_out <= d_i... | 7.959444 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
11-30-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simula... | 7.206611 |
module bypass_wb_tb ();
reg [4:0] rr1_ex, rr2_ex, wr_mem, wr_wb;
reg regW_mem, regW_wb;
wire [1:0] forwardA, forwardB;
bypass_ex bx (
rr1_ex,
rr2_ex,
wr_mem,
wr_wb,
regW_mem,
regW_wb,
forwardA,
forwardB
);
initial begin
$display($time, "<<Starting the si... | 6.874504 |
module bypath (
input wire [31:0] reg_data,
input wire [31:0] ex_mem_data,
input wire [31:0] mem_wb_data,
input wire [ 1:0] sel,
output wire [31:0] out
);
/* the bypass is a 3-1 MUX */
assign out = OUT(reg_data, ex_mem_data, mem_wb_data, sel);
function [31:0] OUT;
input [31:0] a;
... | 9.048825 |
module bypath2 (
input wire [31:0] reg_data,
input wire [31:0] ex_mem_data,
input wire [31:0] mem_wb_data,
input wire [31:0] immediate,
input wire ALUSrc_flag,
input wire [ 1:0] sel,
output wire [31:0] out
);
/* the bypass is a 3-1 MUX */
assign out = OUT(reg_data, ex_mem_d... | 8.346168 |
module Bypath_Unit (
input [2:0] ID_JumpBranch,
input [4:0] ID_rsAddr,
ID_rtAddr,
input [4:0] EX_rsAddr,
EX_rtAddr,
input [4:0] MEM_rtAddr,
MEM_wrAddr,
input [4:0] WB_wrAddr,
input EX_RegWrite,
EX_MemWrite,
input [2:0] EX_JumpBranch,
input MEM_RegWrite,
MEM_MemWrite,
... | 7.471013 |
module byte2S (
out,
in,
flag
);
input flag;
input [7:0] in;
output reg [7:0] out;
reg [7:0] mem[255:0];
always @(flag)
if (flag == 'B0) $readmemh("../SBox/S_dat.txt", mem);
else $readmemh("../SBox/S-1_dat.txt", mem);
always @(in) out = mem[in];
endmodule
| 6.963694 |
module half_adder (
A,
B,
S,
C
);
input A;
input B;
output S;
output C;
assign S = A ^ B;
assign C = A & B;
endmodule
| 6.966406 |
module fourbitadder (
input [3:0] addent,
augend,
input cin,
output [3:0] s,
output cout
);
wire [2:0] cintermed;
full_adder F1 (
.A(addent[0]),
.B(augend[0]),
.Cin(cin),
.S(s[0]),
.Cout(cintermed[0])
);
full_adder F2 (
.A(addent[1]),
.B(augend[1]),
... | 6.575476 |
module bytemixcol (
/***** INPUT */
input wire [7:0] a,
input wire [7:0] b,
input wire [7:0] c,
input wire [7:0] d,
/***** OUTPUT */
output wire [7:0] en_new_out,
output wire [7:0] de_new_out
);
//internal wires
wire [7:0] w1, w2, w3, w4, w5, w6, w7, w8... | 7.648855 |
module half_adder (
A,
B,
S,
C
);
input A;
input B;
output S;
output C;
assign S = A ^ B;
assign C = A & B;
endmodule
| 6.966406 |
module fourbitadder (
input [3:0] addent,
augend,
input cin,
output [3:0] s,
output cout
);
wire [2:0] cintermed;
full_adder F1 (
.A(addent[0]),
.B(augend[0]),
.Cin(cin),
.S(s[0]),
.Cout(cintermed[0])
);
full_adder F2 (
.A(addent[1]),
.B(augend[1]),
... | 6.575476 |
module bytemultiplier_tb ();
reg [7:0] multiplier_t, multiplicand_t;
wire [15:0] product_t;
bytemultipler uut (
.multiplier(multiplier_t),
.multiplicand(multiplicand_t),
.product(product_t)
);
initial begin
$monitor("%0d %0d %0d", multiplier_t, multiplicand_t, product_t);
multiplier_... | 6.787109 |
module byteNegator (
byteIn,
byteN,
byteOut
);
input [7:0] byteIn;
input byteN;
output [7:0] byteOut;
reg [7:0] byteOut;
always @(byteIn or byteN) begin
if (byteN) begin
byteOut = ~byteIn;
end else begin
byteOut = byteIn;
end
end
endmodule
| 6.608977 |
module ByteSelector (
input clock,
input reset,
input [31:0] io_in,
input [ 1:0] io_offset,
output [ 7:0] io_out
);
wire [7:0] _GEN_0 = io_offset == 2'h2 ? io_in[23:16] : io_in[31:24]; // @[ByteSelector.scala 17:35 ByteSelector.scala 18:12 ByteSelector.scala 20:12]
wire [7:0] _... | 6.915476 |
module BytesFifo #(
parameter BIT_PER_BYTES = 8,
parameter BYTES_SIZE = 512
) (
input sysClk,
input sysRst,
input [BIT_PER_BYTES-1:0] in_data,
input in_data_valid,
output wire in_data_ready,
input out_data_ready,
output reg [BIT_PER_BYTES-1:0] out_data,
output wire out_data_vali... | 7.073562 |
module bytes_conv (
input wire clk,
input wire rst_n,
input wire [3:0] byteenable_i,
input wire [31:0] address,
input wire [31:0] data_ram_rd,
output reg [31:0] data_ram_wr,
input wire [31:0] data_master_wr,
output wire stall_o,
input wire read_i,
input wire write_i,
output r... | 8.051822 |
module bytewrite_ram_1b (clk, we, addr, di, do);
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
parameter SIZE = 32;
parameter ADDR_WIDTH = 10;
parameter COL_WIDTH = 8;
parameter NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] di... | 8.061706 |
module bytewrite_ram_32bits (
clk,
we,
addr,
din,
dout
);
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter filename = "code.hex";
localparam COL_WIDTH = 8;
localparam NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDT... | 8.061706 |
module bytewrite_sp_ram_rf #(
parameter COL_WIDTH = 8, //byte width
parameter RAM_ADDR_WIDTH = 8,
parameter RAM_DATA_WIDTH = 128, // Data Width in bits
parameter NUM_COL = RAM_DATA_WIDTH / COL_WIDTH
//-----------------------------------------------------------------
) (
input clk,
input en... | 7.853441 |
module bytewrite_tdp_ram_nc #(
//---------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL * COL_WIDTH // Data Wid... | 7.167192 |
module bytewrite_tdp_ram_readfirst2 #(
//-------------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL * COL_W... | 7.167192 |
module bytewrite_tdp_ram_rf #(
//--------------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL * COL_WIDTH // Data Width... | 7.167192 |
module bytewrite_tdp_ram_wf #(
//----------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL * COL_WIDTH // Data Width in ... | 7.167192 |
module dphy_rx_byte_align (
input clock, // byte clock
input reset, // active high sync reset
input enable, // byte clock enable
input [7:0] deser_byte, // raw bytes from iserdes
input wait_for_sync, // when high will look for a sync pattern if sync not already found
input packet_done, // ... | 6.764326 |
module byte_destuffing (
input clk,
rst,
input sop_delin,
eop_delin,
input [7:0] data_delin,
output reg sop_des,
eop_des,
output reg [7:0] data_des
);
reg [3:0] wr_pnt, rd_pnt;
reg [7:0] mem[9:0];
reg start, flag, last;
always @(posedge clk) begin
if (rst) begin
mem[0... | 6.748698 |
module byte_enabled_true_dual_port_ram #(
parameter int BYTE_WIDTH = 8,
ADDRESS_WIDTH = 6,
BYTES = 4,
DATA_WIDTH_R = BYTE_WIDTH * BYTES
) (
input [ADDRESS_WIDTH-1:0] addr1,
input [ADDRESS_WIDTH-1:0] addr2,
input [BYTES-1:0] be1,
input [BYTES-1:0] be2,
input [BYTE_WIDTH-1:0] data_in1,... | 8.632056 |
module byte_enable_generator (
clk,
reset,
// master side
write_in,
byteenable_in,
waitrequest_out,
// fabric side
byteenable_out,
waitrequest_in
);
parameter BYTEENABLE_WIDTH = 4; // valid byteenable widths are 1, 2, 4, 8, 16, 32, 64, and 128
input clk;
input reset;
in... | 8.933273 |
module five_hundred_twelve_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [63:0] byteenable_in;
output wire waitrequest_out;
output wire [63:0] byteenable_out;
inpu... | 6.522024 |
module sixty_four_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [7:0] byteenable_in;
output wire waitrequest_out;
output wire [7:0] byteenable_out;
input waitreque... | 6.848656 |
module thirty_two_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [3:0] byteenable_in;
output wire waitrequest_out;
output wire [3:0] byteenable_out;
input waitreque... | 6.672265 |
module byte_endian_converter (
ENABLE,
DATA_IN,
DATA_OUT
);
parameter DATA_WIDTH = 32; //8, 16, 32, 64
input ENABLE;
input [DATA_WIDTH-1:0] DATA_IN;
output [DATA_WIDTH-1:0] DATA_OUT;
generate
if (DATA_WIDTH == 8) begin //no byte endian is required, passthrough
assign DATA_OUT = DATA... | 8.95288 |
module Byte_Entry_Unit (
input [1:0] A1_0,
input [1:0] BEControl,
output [3:0] BE
);
assign BE = (BEControl == 2'b01 && A1_0 == 2'b00) ? 4'b0001 : // 01: ֽ
(BEControl==2'b01 && A1_0==2'b01) ? 4'b0010 :
(BEControl==2'b01 && A1_0==2'b10) ? 4'b0100 :
(BEControl==2'b01 && A1_0==2'b11) ? 4'b... | 7.007263 |
module byte_en_reg (
clk,
rst,
we,
en,
d,
q
);
parameter DATA_W = 32;
parameter INIT_VAL = {DATA_W{1'b0}};
input clk;
input rst;
input we;
input [(DATA_W-1)/8:0] en;
input [DATA_W-1:0] d;
output reg [DATA_W-1:0] q;
integer i;
always @(posedge clk or posedge rst) begin
... | 6.530968 |
module byte_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrempty,
wrfull
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output wrempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off... | 6.654152 |
module byte_mixcolum (
a,
b,
c,
d,
outx,
outy
);
input [7:0] a, b, c, d;
output [7:0] outx, outy;
reg [7:0] outx, outy;
function [7:0] xtime;
input [7:0] in;
reg [3:0] xtime_t;
begin
xtime[7:5] = in[6:4];
xtime_t[3] = in[7];
xtime_t[2] = in[7];
xti... | 7.01994 |
module byte_RCA (
a,
b,
ci,
s,
co
);
input [7:0] a, b;
input ci;
output [7:0] s;
output co;
wire [7:0] c;
full_adder fa1 (
a[0],
b[0],
ci,
s[0],
c[0]
);
full_adder fa2 (
a[1],
b[1],
c[0],
s[1],
c[1]
);
full_adder fa3 ... | 7.393572 |
module byte_RCA_last (
a,
b,
ci,
s,
co,
overflow
);
input [7:0] a, b;
input ci;
output [7:0] s;
output co, overflow;
wire [6:0] c;
full_adder fa1 (
a[0],
b[0],
ci,
s[0],
c[0]
);
full_adder fa2 (
a[1],
b[1],
c[0],
s[1],
... | 6.913012 |
module byte_reorder_8bit (
input [31:0] data_in,
output [31:0] data_out
);
assign data_out[7:0] = data_in[31:24];
assign data_out[15:8] = data_in[23:16];
assign data_out[23:16] = data_in[15:8];
assign data_out[31:24] = data_in[7:0];
endmodule
| 7.625151 |
module byte_reorder_16 (
input [31:0] data_in,
output [31:0] data_out
);
assign data_out[15:0] = data_in[31:16];
assign data_out[31:16] = data_in[15:0];
endmodule
| 7.625151 |
module byte_sel (
input wire [2:0] addr, //address
input wire [3:0] size, //0001=1Byte;0010=2Byte;0100=4Byte;1000=8Byte
input wire mask,
output wire [7:0] bsel
);
wire [7:0] bsel_source;
wire [7:0] shift1;
wire [7:0] shift2;
assign bsel_source = {7'b0, size[0]} | {6'b0, {2{size[1]}}} | {4'b0... | 7.23177 |
module byte_shifter (
input wire unsign,
input wire [2:0] addr, //地址低3位 用于指示移位大小
input wire [3:0] size, //0001:1Byte 0010:2Byte 0100=4Byte 1000=8Byte
input wire [63:0] data_in, //要送往BIU的数据
output wire [63:0] data_lsu_cache,
//对BIU信号
output wire [63:0] data_write,
input wire [63:0]... | 9.118945 |
module byte_striping_c (
input clk_2f_c,
input reset,
input valid_in,
input [31:0] Data_in,
output reg valid_0_c,
output reg [31:0] lane_0_c,
output reg valid_1_c,
output reg [31:0] lane_1_c
);
reg contador;
always @(*) begin
if (reset == 0) begin
valid_0_c <= 0;
lan... | 6.597404 |
module byte_striping_e (
clk_2f_e,
reset,
valid_in,
Data_in,
valid_0_e,
lane_0_e,
valid_1_e,
lane_1_e
);
(* src = "byte_striping_e.v:13" *)
reg _00_;
(* src = "byte_striping_e.v:13" *)
reg [31:0] _01_;
(* src = "byte_striping_e.v:13" *)
reg [31:0] _02_;
(* src = "byte_strip... | 6.597404 |
module byte_sub (
data,
out
);
input [127:0] data;
output [127:0] out;
assign out = ~data;
endmodule
| 6.617995 |
module receives 32 times 8 bits from input pins and concatenate it to
256 block to do encryption.
when it finishes receiving, transmit a pulse (done) that confirm that the block is ready to encrypt
*/
module byte_to_256(
input rst_p, // active high synchronous reset
input in_en, // High when there are more bl... | 8.579324 |
module byte_to_32bits
( input clock,
input run,
input [15:0]to_port,
input udp_rx_active,
input [7:0] udp_rx_data,
input full,
output reg fifo_wrreq,
output reg [31:0] data_out,
output reg [31:0] sequence_errors
);
parameter [15:0] port;
localparam IDLE = 1'd0, PROCESS = 1'd1;... | 7.98739 |
module byte_to_48bits
( input clock,
input run,
input [15:0]to_port,
input udp_rx_active,
input [7:0] udp_rx_data,
input full,
output reg fifo_wrreq,
output reg [47:0] data_out,
output reg [31:0] sequence_errors
);
parameter [15:0] port;
localparam IDLE = 1'd0, PROCESS = 1'd1;
... | 7.217568 |
module byte_to_hex (
input [3:0] b,
output [7:0] h
);
assign h = (b < 10 ? "0" + b : "A" + (b - 10));
endmodule
| 6.661181 |
module byte_un_striping (
input clk_2f,
input clk,
input valid_0,
input [31:0] lane_0,
input valid_1,
input [31:0] lane_1,
output reg [31:0] data_out,
output reg valid_out
);
reg [1:0] counter;
always @(posedge clk_2f) begin
if (valid_0 == 0) begin
counter <= 2'b10;
... | 6.743712 |
module byte_un_striping_c (
input clk_2f_c,
input reset,
input valid_0,
input [31:0] lane_0,
input valid_1,
input [31:0] lane_1,
output reg valid_out_c,
output reg [31:0] Data_out_c
);
reg contador;
always @(*) begin
if (reset == 0) begin
valid_out_c <= 0;
Data_out_c... | 6.743712 |
module byte_un_striping_e (
clk_2f_e,
reset,
valid_0,
lane_0,
valid_1,
lane_1,
valid_out_e,
Data_out_e
);
(* src = "byte_un_striping_e.v:13" *)
reg [31:0] _0_;
(* src = "byte_un_striping_e.v:13" *)
reg _1_;
(* src = "byte_un_striping_e.v:13" *)
reg _2_;
(* src = "byte_un_st... | 6.743712 |
module top (
input wire CLK_IN,
input wire RST_N,
output wire [2:0] RGB_LED,
output wire BZ
);
reg [23:0] counter;
reg led;
reg buzz;
always @(posedge CLK_IN) begin
if (RST_N == 1'b0) begin
counter <= 24'd0;
led <= 1'b0;
buzz <= 1'b0;
end else begin
if (counter... | 7.233807 |
module B_8xBin2BCD (
input [7:0] numBin,
output [9:0] numBCD
);
/*
8-BIT BINARY TO BCD CONVERTER
-----------------------------
[+] Using Double Dabble
[+] Flow: https://johnloomis.org/ece314/notes/devices/binary_to_BCD/bcd04.png
*/
wire [3:0] add3Out[6:0];
B_add3BCD C1 (
{1'b0, numBin[7:5]}... | 6.914008 |
module B_add3BCD (
input [3:0] numIN,
output [3:0] numOT
);
/*
Adds 3 if input > 4.
Y3 | A + BC + BD
Y2 | AD + BC'D'
Y1 | B'C + CD + AD'
Y0 | AD' + A'B'D + BCD'
*/
assign numOT[3] = ((numIN[3]) | (numIN[2] & numIN[1]) | (numIN[2] & numIN[0]));
assign numOT[2] = ((numIN[3] & numIN[0]) | (numIN[2] ... | 7.301121 |
module B_ADDR (
pc_add_4,
immediate,
B_Addr
);
input [31:0] immediate;
input [31:0] pc_add_4;
output [31:0] B_Addr;
wire Cout;
wire [31:0] immediate_left_2;
SHIFTER_32_L2 shift_addr_left_2 (
immediate,
immediate_left_2
);
CLA_32 cla_32 (
pc_add_4,
immediate_left_2,... | 8.030672 |
module B_is2Digit (
input [3:0] num,
output z
);
/*
Checks if the given 4-bit number is greater than 9.
*/
assign z = (num[3] & (num[2] | num[1] | num[0]));
endmodule
| 7.185124 |
module B_2dBCDAdder (
input CIN,
input [7:0] numA,
input [7:0] numB,
output COUT,
output [7:0] sumBCD
);
wire carry0;
B_1dBCDAdder add0 (
CIN,
numA[3:0],
numB[3:0],
carry0,
sumBCD[3:0]
);
B_1dBCDAdder add1 (
carry0,
numA[7:4],
numB[7:4],
... | 6.868066 |
module B_8xComp (
input [7:0] numA,
numB,
output LT,
EQ,
GT
);
wire [2:0] resCompL;
B_4xComp compL (
1'b0,
1'b1,
1'b0,
numA[3:0],
numB[3:0],
resCompL[2],
resCompL[1],
resCompL[0]
);
B_4xComp compH (
resCompL[2],
resCompL[1],
r... | 6.514752 |
module addnSubX #(
parameter adderWidth = 4
) (
output overflowFlag,
output carryOut,
output [adderWidth-1:0] SUM,
input carryIn,
input [adderWidth-1:0] numA,
numB,
input opSelect
); // parameter adderWidth = 4;
// carry ahead logic
//.. ISSUE: carryIn should be removed from port... | 7.624249 |
module b_block (
c_out2,
c_out1,
g3,
p3,
g2,
p2,
g1,
p1,
c_in
);
output c_out1, c_out2, g3, p3;
input g2, p2, g1, p1, c_in;
wire w1, w2;
and (p3, p2, p1);
and (w1, p2, g1);
or (g3, g2, w1);
assign c_out1 = c_in;
and (w2, p1, c_in);
or (c_out2, g1, w2);
endmod... | 8.633743 |
module B_Bus_Mux (
input clk,
input [3:0] sel,
input [27:0] AC,
input [27:0] MAR,
input [27:0] MDR,
input [7:0] PC,
input [27:0] MBRU,
input [27:0] R1,
input [27:0] R2,
input [27:0] R3,
input [27:0] R4,
input [27:0] R5,
input [27:0] R6,
input [27:0] R7,
input ... | 7.146675 |
module b_cell_1 (
input in_x,
input in_y,
input in_carry,
output out_sum,
output out_generate,
output out_propogate
);
assign out_generate = in_x & in_y;
assign out_propogate = in_x ^ in_y;
assign out_sum = out_propogate ^ in_carry;
endmodule
| 6.932702 |
module counter4x (
output [3:0] countVal4x,
output ANDr,
input ANDl,
CLK,
RESN
);
/*genvar i;
generate
//for(i=1; i<17; i=i+1) begin: m
for(i=1; i<5; i=i+1) begin: m
lab04part01_TFlipAnd (cBout[i], cBout[i-1], SW[1], SW[2]);
end //for
endgenerate*/
wire [3:0] andOut;
lab04part01_TF... | 7.585489 |
module counter16x (
output [15:0] countVal,
output ANDr,
input ANDl,
CLK,
RESN
);
wire [3:0] carryOn;
counter4x countA (
countVal[3:0],
carryOn[3],
ANDl,
CLK,
RESN
);
counter4x countB (
countVal[7:4],
carryOn[2],
carryOn[3],
CLK,
RE... | 7.072229 |
module counter32x (
output [31:0] countVal,
output ANDr,
input ANDl,
CLK,
RESN
);
wire carryOn;
counter16x count0 (
countVal[15:0],
carryOn,
ANDl,
CLK,
RESN
);
counter16x count1 (
countVal[31:16],
ANDr,
carryOn,
CLK,
RESN
);
endmo... | 7.510637 |
module counter16x_add (
output reg [15:0] countVal,
input EN,
CLK,
RESN
);
always @(posedge CLK) begin
if (EN) countVal <= countVal + 1;
if (~RESN) countVal <= 16'h0000;
else if (~EN & RESN) countVal <= countVal;
end //always
endmodule
| 6.594678 |
module counterBCD1x(
// output [3:0]countVal1xBCD,
// output incNext1d,
// input incPrev1d, CLK1d, RESN1d
// );
// reg resetF;
// wire [3:0]andOut;
// //resetF is 0 for RESN=0 OR count=1010;
// always@(negedge CLK1d) begin
// /* I have used negative edge for storing reset of the reset flip flop,
// so tha... | 7.034661 |
module counterBCD2x(
// output [7:0]countVal2xBCD,
// output incNext2d,
// input incPrev2d, CLK2d, RESN2d
// );
// wire incMiddle;
// counterBCD1x count0(countVal2xBCD[3:0], incMiddle, incPrev2d, CLK2d, RESN2d);
// counterBCD1x count1(countVal2xBCD[7:4], incNext2d, incMiddle, CLK2d, RESN2d);
// endmodule
| 7.172585 |
module counterBCD4x(
// output [15:0]countVal4xBCD,
// output incNext4d,
// input incPrev4d, CLK4d, RESN4d
// );
// wire incMiddle;
// counterBCD2x count01(countVal4xBCD[7:0], incMiddle, incPrev4d, CLK4d, RESN4d);
// counterBCD2x count23(countVal4xBCD[15:8], incNext4d, incMiddle, CLK4d, RESN4d);
// endmodule
| 6.878981 |
module counterBCD1d (
output reg [3:0] countVal1dBCD,
output reg next1d,
input /*prev1d,*/ CLK1d,
RESN1d
);
initial countVal1dBCD = 4'h0;
always @(posedge CLK1d or negedge RESN1d) begin
if (~RESN1d) begin
countVal1dBCD <= 4'h0;
next1d <= 1'b0;
end //if
else if(countVal1dBCD ... | 7.006916 |
module counterBCD2d (
output [7:0] countVal2dBCD,
output next2d,
input /*prev2d,*/ CLK2d,
CLR2d
, output [1:0] next
);
wire connect2;
counterBCD1d countA (
countVal2dBCD[3:0],
connect2 /*, prev2d*/,
CLK2d,
CLR2d
);
counterBCD1d countB (
countVal2dBCD[7:4],
... | 7.466323 |
module counterBCD4d (
output [15:0] countVal4dBCD,
output next4d,
input prev4d,
CLK4d,
CLR4d
, output [3:0] next
);
wire connect4;
counterBCD2d countA (
countVal4dBCD[7:0],
connect4, /*prev4d,*/
CLK4d,
CLR4d,
next[1:0]
);
counterBCD2d countB (
countVa... | 7.689586 |
module hexDisplay4digit (
output [ 6:0] d3,
d2,
d1,
d0,
inout [15:0] displayVal
);
hexDecoder7Seg h3 (
d3,
displayVal[15:12]
);
hexDecoder7Seg h2 (
d2,
displayVal[11:8]
);
hexDecoder7Seg h1 (
d1,
displayVal[7:4]
);
hexDecoder7Seg h0 (
d0,
... | 6.88103 |
module B_DELAY (
CLK,
Xin,
Xin_DEALY
);
//ģӿ
input CLK, Xin;
output Xin_DEALY;
wire signed [15:0] Xin;
wire signed [15:0] Xin_DEALY;
//ģ
//λĴʱ
shift30 S2 (
CLK,
Xin,
Xin_DEALY
);
endmodule
| 6.908582 |
module b_door_lock (
SW,
KEY,
CLOCK_50,
HEX0,
HEX1,
HEX2,
HEX7,
HEX4,
HEX6,
LEDR,
LEDG
);
input [17:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX7;
output [6:0] HEX4;
output [6:0] HEX6;
... | 8.436148 |
module
Instantiation: FSM_4xSequenceDetectorB name(.fOut(), .W(), .pCLK(), .nREST());
-------------------------------------------------------------------------- */
module FSM_4xSequenceDetectorB(
output reg fOut,
//output [3:0]fQ,
input W/*input*/, pCLK, nREST
);
// STATE ASSIGNMENT LIST as parameters
... | 8.053527 |
module: b_lut
//
// Implements the core logic for the xc.lut instruction.
//
module b_lut (
input wire [31:0] crs1 , // Source register 1 (LUT input)
input wire [31:0] crs2 , // Source register 2 (LUT bottom half)
input wire [31:0] crs3 , // Source register 3 (LUT top half)
output wire [31:0] result //
);
... | 7.220178 |
module: b_lut_checker
//
// Implements the core logic for the xc.lut instruction for checking
//
module b_lut_checker (
input wire [31:0] crs1 , // Source register 1 (LUT input)
input wire [31:0] crs2 , // Source register 2 (LUT bottom half)
input wire [31:0] crs3 , // Source register 3 (LUT top half)
output w... | 6.604307 |
module B_latchRSe (
input clock,
R,
S,
output Q
);
wire Qa, Qb;
assign Qa = ~((R & clock) | Qb);
assign Qb = ~((S & clock) | Qa);
assign Q = Qa;
endmodule
| 6.531514 |
module mem_DLatch (
output reg Q,
input D,
clk
);
always @(D, clk) begin
if (clk) Q <= D;
end
endmodule
| 6.943764 |
module mem_Dflippos (
output reg Q,
input D,
clk,
resetN
);
always @(posedge clk or negedge resetN) begin
if (~resetN) begin
Q <= 0;
end //if
else begin
Q <= D;
end
end
endmodule
| 7.92443 |
module mem_Dflipneg (
output reg Q,
input D,
clk
);
always @(negedge clk) begin
Q <= D;
end
endmodule
| 7.737337 |
module mem_Tflippos (
output reg Q,
input T,
clk,
reset
);
wire d;
xor (d, Q, T);
always @(posedge clk) begin
if (~reset) Q <= 1'b0;
//else if(T)
// Q <= ~Q;
else
Q <= d;
end
endmodule
| 6.817717 |
module registerNx #(
parameter regWidth = 8
) (
output [regWidth-1 : 0] Q,
input [regWidth-1 : 0] D,
input regCLK,
regRESN
);
//parameter regWidth=8;
genvar i;
generate
for (i = 0; i < regWidth; i = i + 1) begin : m
mem_Dflippos df (
Q[i],
D[i],
regCLK,
... | 9.819495 |
module shiftRegisterNx #(
parameter regWidth = 4
) (
output [(regWidth-1):0] Q,
input D,
input sregCLK,
sregRESN
);
wire [(regWidth):0] shiftAhead;
assign shiftAhead[0] = D;
assign Q[(regWidth-1):0] = shiftAhead[(regWidth):1];
genvar i;
generate
for (i = 0; i < regWidth; i = i + 1) beg... | 8.12979 |
module B_1xMUX2to1 (
input S,
X,
Y,
output M
);
assign M = ((~S & X) | (S & Y));
endmodule
| 7.289178 |
module mux2x1 #(
parameter dataW = 8
) (
output reg [(dataW-1):0] M,
input [(dataW-1):0] X,
input [(dataW-1):0] Y,
input Sel
);
always @(*) begin
if (Sel) begin
M = Y;
end else begin
M = X;
end
end
endmodule
| 7.726622 |
module b_out (
i_clk,
i_reset,
i_hsyn,
iv_b11,
iv_b12,
iv_b21,
iv_b22,
iv_fx,
iv_fy,
o_hsyn,
ov_b,
wv_b1r,
wv_b1g,
wv_b1b,
wv_b2r,
wv_b2g,
wv_b2b
);
input i_clk;
input i_reset;
input i_hsyn;
input [15:0] iv_b11, iv_b12, iv_b21, iv_b22;
inpu... | 6.551414 |
module b_predictor (
input clk,
input rst,
input direct_mispredict,
input direct_resolved,
input branch_commit,
input [31:0] pc_head, // the pc of commit branch
input [31:0] pc_branch, // the pc of branch making predict
input [31:0] pc_resolved,
output logic branch_valid,
out... | 9.767808 |
module b_reg (
input Rst,
input Clk,
input [5:0] b_sel,
input LE_sel,
input [7:0] Selector,
output [7:0] Rx,
output [7:0] Ry
);
reg [7:0] b_regs[7:0];
always @(posedge Clk, posedge Rst) begin
if (Rst) begin
b_regs[0] <= 0;
b_regs[1] <= 0;
b_regs[2] <= 0;
b_r... | 7.672496 |
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