code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module BypassCrossingWire (
WGET,
WVAL
);
parameter width = 1;
input [width - 1 : 0] WVAL;
output [width - 1 : 0] WGET;
assign WGET = WVAL;
endmodule
| 7.331414 |
module bypass_bit (
input clk,
bitin,
output bitout
);
always @(posedge clk) begin
assign bitout = bitin;
end
endmodule
| 8.084678 |
module working at EX
//correct RF's output data, which will be used as ALU's operand or DataMem's din
module ByPassingEX(
//current instruction
input[4:0] EX_rs,
input[4:0] EX_rt,
//previous instruction(now at MEM)
input MEM_RegWrite,
input[1:0] MEM_RegSrc,
input[4:0] MEM_WriteReg,
//pre-previous instruction(now at WB)
input WB_RegWrite,
input[1:0] WB_RegSrc,
input[4:0] WB_WriteReg,
//candidates
input[31:0] EX_rfOut1,
input[31:0] EX_rfOut2,
input[31:0] MEM_aluResult,
input[31:0] MEM_PC,
input[31:0] WB_rfWriteData,
//output: correct RF's output
output reg[31:0] EX_correctRFOut1,
output reg[31:0] EX_correctRFOut2
);
//EX_correctRFOut1
always @(*)
begin
//forward from previous instruction(now at MEM)
if (MEM_RegWrite && MEM_WriteReg != 5'd0 && MEM_WriteReg == EX_rs)
begin
case (MEM_RegSrc)
`REGSRC_ALU: EX_correctRFOut1 = MEM_aluResult;//from previous aluResult
`REGSRC_PCPLUS4: EX_correctRFOut1 = MEM_PC + 32'd4;//from previous PC+4
/*REGSRC_DMEM will cause stall*/
endcase
end
//forward from pre-previous instruction(now at WB)
else if (WB_RegWrite && WB_WriteReg != 5'd0 && WB_WriteReg == EX_rs)
EX_correctRFOut1 = WB_rfWriteData;
else
EX_correctRFOut1 = EX_rfOut1;
end
//EX_correctRFOut2
always @(*)
begin
//forward from previous instruction(now at MEM)
if (MEM_RegWrite && MEM_WriteReg != 5'd0 && MEM_WriteReg == EX_rt)
begin
case (MEM_RegSrc)
`REGSRC_ALU: EX_correctRFOut2 = MEM_aluResult;///from previous aluResult
`REGSRC_PCPLUS4: EX_correctRFOut2 = MEM_PC + 32'd4;//from previous PC+4
/*REGSRC_DMEM will cause stall*/
endcase
end
//forward from pre-previous instruction(now at WB)
else if (WB_RegWrite && WB_WriteReg != 5'd0 && WB_WriteReg == EX_rt)
EX_correctRFOut2 = WB_rfWriteData;
else
EX_correctRFOut2 = EX_rfOut2;
end
endmodule
| 8.695516 |
module working at ID
//correct RF's output, which will be used in Branch(beq, bne) or Jump(jr, jalr)
module ByPassingID(
//current instruction
input[4:0] ID_rs,
input[4:0] ID_rt,
input[1:0] ID_Branch,
input[1:0] ID_Jump,
//previous instruction(now at EX)
input EX_RegWrite,
input[1:0] EX_RegSrc,
input[4:0] EX_WriteReg,
//pre-previous instruction(now at MEM)
input MEM_RegWrite,
input[1:0] MEM_RegSrc,
input[4:0] MEM_WriteReg,
//candidates
input[31:0] ID_rfOut1,
input[31:0] ID_rfOut2,
input[31:0] EX_PC,
input[31:0] MEM_PC,
input[31:0] MEM_aluResult,
//output: correct RF's output
output reg[31:0] ID_correctRFOut1,
output reg[31:0] ID_correctRFOut2
);
wire useRegAtID = ID_Branch != `BRANCH_NONE || ID_Jump == `JUMP_REG;
//ID_correctRFOut1
always @(*)
begin
if (useRegAtID)//use at ID
begin
//forward from previous instruction(now at EX)
if (EX_RegWrite && EX_WriteReg != 5'd0 && EX_WriteReg == ID_rs
&& EX_RegSrc == `REGSRC_PCPLUS4)
ID_correctRFOut1 = EX_PC + 32'd4;//from previous PC+4
/*REGSRC_DMEM or REGSRC_ALU will cause stall*/
//forward from pre-previous instruction(now at WB)
else if (MEM_RegWrite && MEM_WriteReg != 5'd0 && MEM_WriteReg == ID_rs)
begin
case (MEM_RegSrc)
`REGSRC_PCPLUS4: ID_correctRFOut1 = MEM_PC + 32'd4;
`REGSRC_ALU: ID_correctRFOut1 = MEM_aluResult;
/*REGSRC_DMEM will cause stall*/
endcase
end
//use at ID but no data hazard
else
ID_correctRFOut1 = ID_rfOut1;
end
else//not use reg at ID
ID_correctRFOut1 = ID_rfOut1;
end
//ID_correctRFOut2
always @(*)
begin
if (useRegAtID)//use at ID
begin
//forward from previous instruction(now at EX)
if (EX_RegWrite && EX_WriteReg != 5'd0 && EX_WriteReg == ID_rt
&& EX_RegSrc == `REGSRC_PCPLUS4)
ID_correctRFOut2 = EX_PC + 32'd4;//from previous PC+4
/*REGSRC_DMEM or REGSRC_ALU will cause stall*/
//forward from pre-previous instruction(now at WB)
else if (MEM_RegWrite && MEM_WriteReg != 5'd0 && MEM_WriteReg == ID_rt)
begin
case (MEM_RegSrc)
`REGSRC_PCPLUS4: ID_correctRFOut2 = MEM_PC + 32'd4;
`REGSRC_ALU: ID_correctRFOut2 = MEM_aluResult;
/*REGSRC_DMEM will cause stall*/
endcase
end
//use at ID but no data hazard
else
ID_correctRFOut2 = ID_rfOut2;
end
else//not use reg at ID
ID_correctRFOut2 = ID_rfOut2;
end
endmodule
| 7.230412 |
module bypassLogic (
MW_regWrite,
XM_regWrite,
XM_MemWrite,
MW_MemToReg,
DX_rs,
DX_rt,
XM_rd,
MW_rd,
rs,
rd,
ALUinA,
ALUinB,
muxM,
muxBranchA,
muxBranchB,
bexMux,
jrMux
);
input MW_regWrite, XM_MemWrite, MW_MemToReg, XM_regWrite;
input [4:0] DX_rs, DX_rt, XM_rd, MW_rd, rs, rd; //rs and rd are from the decode stage and used for calcBranch
output [1:0] ALUinA, ALUinB, muxBranchA, muxBranchB;
output muxM;
//data hazards
wire mem1, mem2, ex1, hazard1, hazard2, hazard3, hazard4, hAm1, hAm2, hBm1, hBm2, hbm2, bp, bpB;
wire [1:0] aluinA, aluinB, bM;
or or1 (hazard1, MW_rd == DX_rs, MW_rd == DX_rt);
or or2 (hazard2, XM_rd == DX_rs, XM_rd == DX_rt);
and and1 (mem1, MW_regWrite, MW_rd != 5'b0, hazard1);
and and2 (mem2, XM_regWrite, XM_rd != 5'b0, hazard2);
and and3 (ex1, MW_MemToReg, XM_MemWrite, MW_rd != 5'b0, MW_rd == XM_rd);
and andA1 (hAm1, MW_rd == DX_rs, mem1);
and andA2 (hAm2, XM_rd == DX_rs, mem2);
or orA3 (bp, hAm1, hAm2);
assign aluinA = hAm2 ? 2'd2 : 2'b1;
assign ALUinA = bp ? aluinA : 2'b0;
//second source bypassing
and andB1 (hBm1, MW_rd == DX_rt, mem1);
and andB2 (hBm2, XM_rd == DX_rt, mem2);
or orB3 (bpB, hBm1, hBm2);
assign aluinB = hBm2 ? 2'd2 : 2'b1;
assign ALUinB = bpB ? aluinB : 2'b0;
assign muxM = ex1 ? 1'b1 : 1'b0;
//control hazards
wire c1, c2, h1, h2, h3, h4, cc1, cc2;
wire [1:0] muxC, muxC2;
or or3 (hazard3, MW_rd == rs, MW_rd == rd);
or or4 (hazard4, XM_rd == rs, XM_rd == rd);
and andc1 (c1, MW_regWrite, MW_rd != 5'b0, hazard3);
and andc2 (c2, XM_regWrite, XM_rd != 5'b0, hazard4);
//input rs
//01 take the reg value from MW latch
//10 --------------- XM
and andC1 (h1, MW_rd == rs, c1);
and andC2 (h2, XM_rd == rs, c2);
or orC (cc1, h1, h2);
assign muxC = h2 ? 2'd2 : 2'b1;
assign muxBranchA = cc1 ? muxC : 2'b0;
//input rd
and andC3 (h3, MW_rd == rd, c1);
and andC4 (h4, XM_rd == rd, c2);
or orC1 (cc2, h3, h4);
assign muxC2 = h4 ? 2'd2 : 2'b1;
assign muxBranchB = cc2 ? muxC2 : 2'b0;
//bex hazard
wire b1, b2, b3, b4;
output [1:0] bexMux;
assign b1 = MW_rd == 5'd30;
assign b2 = XM_rd == 5'd30;
and andBex1 (b3, MW_regWrite, b1);
and andBex2 (b4, XM_regWrite, b2);
//assign bM = b4 ? 2'd2 : 2'b1;
//assign bexMux = b3 ? bM : 2'b0;
assign bM = b3 ? 2'd1 : 2'b0;
assign bexMux = b4 ? 2'd2 : bM;
//jr bypass --- rdmux
wire j1, j2;
output [1:0] jrMux;
wire [1:0] j3;
and jj (j1, MW_regWrite, (MW_rd == rd), MW_rd != 5'b0);
and jjj (j2, XM_regWrite, (XM_rd == rd), XM_rd != 5'b0);
assign j3 = j1 ? 2'd1 : 2'b0;
assign jrMux = j2 ? 2'd2 : j3;
endmodule
| 8.827058 |
module BypassWire (
WGET,
WVAL
);
parameter width = 1;
input [width - 1 : 0] WVAL;
output [width - 1 : 0] WGET;
assign WGET = WVAL;
endmodule
| 6.997804 |
module bypass_32b (
A32,
TYPESEL,
R32
);
input [31:0] A32;
input [2:0] TYPESEL;
output [31:0] R32;
wire [31:0] A32;
wire [ 2:0] TYPESEL;
wire [31:0] R32;
wire [15:0] real_a32;
wire [15:0] imag_a32;
wire [15:0] real_r32;
wire [15:0] imag_r32;
wire [15:0] mux0out;
wire [15:0] mux1out;
wire [15:0] mux2out;
wire [15:0] mux3out;
wire [15:0] sgninv_0_out;
wire [15:0] sgninv_1_out;
assign real_a32 = A32[31:16];
assign imag_a32 = A32[15:0];
assign real_r32 = mux2out;
assign imag_r32 = mux3out;
assign R32[31:16] = real_r32;
assign R32[15:0] = imag_r32;
mux_2_to_1 #(
.DATA_WIDTH(16)
) mux_2_to_1_inst0 (
.D0(real_a32),
.D1(imag_a32),
.S (TYPESEL[2]),
.Y (mux0out)
);
mux_2_to_1 #(
.DATA_WIDTH(16)
) mux_2_to_1_inst1 (
.D0(imag_a32),
.D1(real_a32),
.S (TYPESEL[2]),
.Y (mux1out)
);
sgninv_16b sgninv_16b_inst0 (
.A16(mux0out),
.R16(sgninv_0_out)
);
sgninv_16b sgninv_16b_inst1 (
.A16(mux1out),
.R16(sgninv_1_out)
);
mux_2_to_1 #(
.DATA_WIDTH(16)
) mux_2_to_1_inst2 (
.D0(mux0out),
.D1(sgninv_0_out),
.S (TYPESEL[1]),
.Y (mux2out)
);
mux_2_to_1 #(
.DATA_WIDTH(16)
) mux_2_to_1_inst3 (
.D0(mux1out),
.D1(sgninv_1_out),
.S (TYPESEL[0]),
.Y (mux3out)
);
endmodule
| 7.600681 |
module Bypass_Always (
input [7:0] Input_Data,
output reg [7:0] Output_Data
);
//Definition for Variables in the module
//Logical
always @(*) begin
Output_Data <= Input_Data;
end
endmodule
| 8.558605 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
12-17-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module Bypass_Alwyas_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[7:0] result;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
Bypass_Always B1(.Input_Data(out_num), .Output_Data(result));
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611 |
module by_mux #(
parameter WIDTH = 1
) (
d_in_0,
d_in_1,
d_in_2,
d_out,
addr
);
input [WIDTH-1:0] d_in_0;
input [WIDTH-1:0] d_in_1;
input [WIDTH-1:0] d_in_2;
input [1:0] addr;
output reg [31:0] d_out;
always @* begin
casez (addr)
0: d_out <= d_in_0;
1: d_out <= d_in_1;
2: d_out <= d_in_2;
default d_out <= 0;
endcase
end
endmodule
| 7.959444 |
module counter input
CLR: module counter input
out_num: output port for the counter module
OV: overflow flag
------------------------------------------------------
History:
11-30-2015: First Version by Garfield
***********************************************/
`timescale 10 ns/100 ps
//Simulation time assignment
//Insert the modules
module Bypass_test;
//defination for Variables
reg clk;
reg reset;
reg[7:0] cntr;
wire EN;
wire CLR;
wire[7:0] out_num;
wire OV;
wire[7:0] result;
//Connection to the modules
counter C1(.clk(clk), .Reset(reset), .EN(EN),
.CLR(CLR), .counter(out_num), .OV(OV));
Bypass B1(.Input_Data(out_num), .Output_Data(result));
begin
assign EN = 1'b1;
assign CLR = 1'b0;
//Clock generation
initial
begin
clk = 0;
//Reset
forever
begin
#10 clk = !clk;
//Reverse the clock in each 10ns
end
end
//Reset operation
initial
begin
reset = 0;
//Reset enable
#14 reset = 1;
//Counter starts
end
//Couner as input
always @(posedge clk or reset)
begin
if ( !reset)
//reset statement: counter keeps at 0
begin
cntr <= 8'h00;
end
else
//Wroking, counter increasing
begin
cntr <= cntr + 8'h01;
end
end
end
endmodule
| 7.206611 |
module bypass_wb_tb ();
reg [4:0] rr1_ex, rr2_ex, wr_mem, wr_wb;
reg regW_mem, regW_wb;
wire [1:0] forwardA, forwardB;
bypass_ex bx (
rr1_ex,
rr2_ex,
wr_mem,
wr_wb,
regW_mem,
regW_wb,
forwardA,
forwardB
);
initial begin
$display($time, "<<Starting the simulation>> ");
$monitor("rr1 %b, rr2 %b, wr_m %b, wr_w %b, wren_m %b, wren_w %b, fwd_a %b, fwd_b %b", rr1_ex,
rr2_ex, wr_mem, wr_wb, regW_mem, regW_wb, forwardA, forwardB);
rr1_ex = 5'b00000;
rr2_ex = 5'b00000;
wr_mem = 5'b00000;
wr_wb = 5'b00000;
regW_mem = 1'b0;
regW_wb = 1'b0;
#20480 $stop;
end
always #20 rr1_ex[0] = ~rr1_ex[0];
always #40 rr1_ex[1] = ~rr1_ex[1];
always #80 rr2_ex[0] = ~rr2_ex[0];
always #160 rr2_ex[1] = ~rr2_ex[1];
always #320 wr_mem[0] = ~wr_mem[0];
always #640 wr_mem[1] = ~wr_mem[1];
always #1280 wr_wb[0] = ~wr_wb[0];
always #2560 wr_wb[1] = ~wr_wb[1];
always #5120 regW_mem = ~regW_mem;
always #10240 regW_wb = ~regW_wb;
endmodule
| 6.874504 |
module bypath (
input wire [31:0] reg_data,
input wire [31:0] ex_mem_data,
input wire [31:0] mem_wb_data,
input wire [ 1:0] sel,
output wire [31:0] out
);
/* the bypass is a 3-1 MUX */
assign out = OUT(reg_data, ex_mem_data, mem_wb_data, sel);
function [31:0] OUT;
input [31:0] a;
input [31:0] b;
input [31:0] c;
input [1:0] sel;
begin
case (sel)
2'b00: OUT = a;
2'b10: OUT = b;
2'b01: OUT = c;
default: OUT = a;
endcase
end
endfunction
endmodule
| 9.048825 |
module bypath2 (
input wire [31:0] reg_data,
input wire [31:0] ex_mem_data,
input wire [31:0] mem_wb_data,
input wire [31:0] immediate,
input wire ALUSrc_flag,
input wire [ 1:0] sel,
output wire [31:0] out
);
/* the bypass is a 3-1 MUX */
assign out = OUT(reg_data, ex_mem_data, mem_wb_data, immediate, ALUSrc_flag, sel);
function [31:0] OUT;
input [31:0] a;
input [31:0] b;
input [31:0] c;
input [31:0] d;
input flag;
input [1:0] sel;
begin
case ({
flag, sel
})
3'b100: OUT = d;
3'b101: OUT = d;
3'b110: OUT = d;
3'b111: OUT = d;
3'b000: OUT = a;
3'b010: OUT = b;
3'b001: OUT = c;
default: OUT = a;
endcase
end
endfunction
endmodule
| 8.346168 |
module Bypath_Unit (
input [2:0] ID_JumpBranch,
input [4:0] ID_rsAddr,
ID_rtAddr,
input [4:0] EX_rsAddr,
EX_rtAddr,
input [4:0] MEM_rtAddr,
MEM_wrAddr,
input [4:0] WB_wrAddr,
input EX_RegWrite,
EX_MemWrite,
input [2:0] EX_JumpBranch,
input MEM_RegWrite,
MEM_MemWrite,
MEM_MemtoReg,
input [2:0] MEM_JumpBranch,
input WB_RegWrite,
WB_MemtoReg,
output ID_Forward1,
ID_Forward2,
output reg [1:0] EX_ForwardA,
EX_ForwardB,
output MEM_Forwardwm
);
parameter BEQ = 3'd1, BNE = 3'd2, JR = 3'd3, J = 3'd4, JAL = 3'd7, OTHERS = 3'd0;
wire EX_RILwSw = (EX_RegWrite | EX_MemWrite) && (EX_JumpBranch == OTHERS);
wire ID_BranchJr = (ID_JumpBranch == BEQ) || (ID_JumpBranch == BNE) || (ID_JumpBranch == JR);
wire MEM_Sw = MEM_MemWrite;
wire MEM_RI = (MEM_RegWrite & ~MEM_MemWrite & ~MEM_MemtoReg) && (MEM_JumpBranch == OTHERS);
wire MEM_RIJal = (MEM_RegWrite & ~MEM_MemWrite & ~MEM_MemtoReg);
wire WB_Lw = WB_MemtoReg;
wire WB_RILwJal = WB_RegWrite;
wire MEMw_equ_IDs = (MEM_wrAddr != 0) && (MEM_wrAddr == ID_rsAddr);
wire MEMw_equ_IDt = (MEM_wrAddr != 0) && (MEM_wrAddr == ID_rtAddr);
wire MEMw_equ_EXs = (MEM_wrAddr != 0) && (MEM_wrAddr == EX_rsAddr);
wire MEMw_equ_EXt = (MEM_wrAddr != 0) && (MEM_wrAddr == EX_rtAddr);
wire WBw_equ_EXs = (WB_wrAddr != 0) && (WB_wrAddr == EX_rsAddr);
wire WBw_equ_EXt = (WB_wrAddr != 0) && (WB_wrAddr == EX_rtAddr);
wire WBw_equ_MEMt = (WB_wrAddr != 0) && (WB_wrAddr == MEM_rtAddr);
// ID_Forward
// MEM(R / I / Jal) --> ID(beq / bne / jr)
// --- wr --- - rs/rt - rs
assign ID_Forward1 = MEM_RIJal & ID_BranchJr & MEMw_equ_IDs;
assign ID_Forward2 = MEM_RIJal & ID_BranchJr & MEMw_equ_IDt;
// EX_Forward
// 1. MEM(R / I) --> EX(R / sw / I / lw) (higher priority)
// - wr - = -rs/rt- --rs--
// 2. WB(R / I / lw / Jal) --> EX(R / sw / I / lw)
// ------ wr ------ = -rs/rt- --rs--
always @(*) begin
// EX_ForwardA
if (MEM_RI & EX_RILwSw & MEMw_equ_EXs) EX_ForwardA <= 2'd1;
else if (WB_RILwJal & EX_RILwSw & WBw_equ_EXs) EX_ForwardA <= 2'd2;
else EX_ForwardA <= 2'd0;
//EX_ForwardB
if (MEM_RI & EX_RILwSw & MEMw_equ_EXt) EX_ForwardB <= 2'd1;
else if (WB_RILwJal & EX_RILwSw & WBw_equ_EXt) EX_ForwardB <= 2'd2;
else EX_ForwardB <= 2'd0;
end
// MEM_Forwardrm
// WB(lw) --> MEM(sw) (wr = rt)
// wr = rt
assign MEM_Forwardwm = WB_Lw & MEM_Sw & WBw_equ_MEMt;
endmodule
| 7.471013 |
module byte2S (
out,
in,
flag
);
input flag;
input [7:0] in;
output reg [7:0] out;
reg [7:0] mem[255:0];
always @(flag)
if (flag == 'B0) $readmemh("../SBox/S_dat.txt", mem);
else $readmemh("../SBox/S-1_dat.txt", mem);
always @(in) out = mem[in];
endmodule
| 6.963694 |
module half_adder (
A,
B,
S,
C
);
input A;
input B;
output S;
output C;
assign S = A ^ B;
assign C = A & B;
endmodule
| 6.966406 |
module fourbitadder (
input [3:0] addent,
augend,
input cin,
output [3:0] s,
output cout
);
wire [2:0] cintermed;
full_adder F1 (
.A(addent[0]),
.B(augend[0]),
.Cin(cin),
.S(s[0]),
.Cout(cintermed[0])
);
full_adder F2 (
.A(addent[1]),
.B(augend[1]),
.Cin(cintermed[0]),
.S(s[1]),
.Cout(cintermed[1])
);
full_adder F3 (
.A(addent[2]),
.B(augend[2]),
.Cin(cintermed[1]),
.S(s[2]),
.Cout(cintermed[2])
);
full_adder F4 (
.A(addent[3]),
.B(augend[3]),
.Cin(cintermed[2]),
.S(s[3]),
.Cout(cout)
);
endmodule
| 6.575476 |
module bytemixcol (
/***** INPUT */
input wire [7:0] a,
input wire [7:0] b,
input wire [7:0] c,
input wire [7:0] d,
/***** OUTPUT */
output wire [7:0] en_new_out,
output wire [7:0] de_new_out
);
//internal wires
wire [7:0] w1, w2, w3, w4, w5, w6, w7, w8;
xtime xtime1 (
.byte_in (w1),
.byte_out(w4)
);
xtime xtime2 (
.byte_in (w3),
.byte_out(w5)
);
xtime xtime3 (
.byte_in (w6),
.byte_out(w7)
);
xtime xtime4 (
.byte_in (w7),
.byte_out(w8)
);
assign w1 = a ^ b;
assign w2 = a ^ c;
assign w3 = c ^ d;
assign w6 = w2 ^ w4 ^ w5;
assign en_new_out = b ^ w3 ^ w4;
assign de_new_out = b ^ w3 ^ w4 ^ w8;
endmodule
| 7.648855 |
module half_adder (
A,
B,
S,
C
);
input A;
input B;
output S;
output C;
assign S = A ^ B;
assign C = A & B;
endmodule
| 6.966406 |
module fourbitadder (
input [3:0] addent,
augend,
input cin,
output [3:0] s,
output cout
);
wire [2:0] cintermed;
full_adder F1 (
.A(addent[0]),
.B(augend[0]),
.Cin(cin),
.S(s[0]),
.Cout(cintermed[0])
);
full_adder F2 (
.A(addent[1]),
.B(augend[1]),
.Cin(cintermed[0]),
.S(s[1]),
.Cout(cintermed[1])
);
full_adder F3 (
.A(addent[2]),
.B(augend[2]),
.Cin(cintermed[1]),
.S(s[2]),
.Cout(cintermed[2])
);
full_adder F4 (
.A(addent[3]),
.B(augend[3]),
.Cin(cintermed[2]),
.S(s[3]),
.Cout(cout)
);
endmodule
| 6.575476 |
module bytemultiplier_tb ();
reg [7:0] multiplier_t, multiplicand_t;
wire [15:0] product_t;
bytemultipler uut (
.multiplier(multiplier_t),
.multiplicand(multiplicand_t),
.product(product_t)
);
initial begin
$monitor("%0d %0d %0d", multiplier_t, multiplicand_t, product_t);
multiplier_t = 8'b0110_1001;
multiplicand_t = 8'b0001_1010;
#20;
end
endmodule
| 6.787109 |
module byteNegator (
byteIn,
byteN,
byteOut
);
input [7:0] byteIn;
input byteN;
output [7:0] byteOut;
reg [7:0] byteOut;
always @(byteIn or byteN) begin
if (byteN) begin
byteOut = ~byteIn;
end else begin
byteOut = byteIn;
end
end
endmodule
| 6.608977 |
module ByteSelector (
input clock,
input reset,
input [31:0] io_in,
input [ 1:0] io_offset,
output [ 7:0] io_out
);
wire [7:0] _GEN_0 = io_offset == 2'h2 ? io_in[23:16] : io_in[31:24]; // @[ByteSelector.scala 17:35 ByteSelector.scala 18:12 ByteSelector.scala 20:12]
wire [7:0] _GEN_1 = io_offset == 2'h1 ? io_in[15:8] : _GEN_0; // @[ByteSelector.scala 15:35 ByteSelector.scala 16:12]
assign io_out = io_offset == 2'h0 ? io_in[7:0] : _GEN_1; // @[ByteSelector.scala 13:33 ByteSelector.scala 14:12]
endmodule
| 6.915476 |
module BytesFifo #(
parameter BIT_PER_BYTES = 8,
parameter BYTES_SIZE = 512
) (
input sysClk,
input sysRst,
input [BIT_PER_BYTES-1:0] in_data,
input in_data_valid,
output wire in_data_ready,
input out_data_ready,
output reg [BIT_PER_BYTES-1:0] out_data,
output wire out_data_valid,
output wire [10:0] fillLevel,
output wire full,
output wire empty
);
reg [8:0] pHead; //full Head reg [8:0]pTail;//empty Tail
reg [8:0] pTail; //full Head reg [8:0]pTail;//empty Tail
integer ntIter;
reg writeLock;
reg [BIT_PER_BYTES-1:0] rf[BYTES_SIZE-1:0]; //add prohibit bit
reg [10:0] tBytesCounter;
assign full = (tBytesCounter == 511);
assign empty = (tBytesCounter == 0);
assign fillLevel = tBytesCounter;
assign out_data_valid = (~empty) & (~writeLock);
assign in_data_ready = (~full);
always @(posedge sysClk or posedge sysRst) begin
if (sysRst) begin
pHead <= 0;
pTail <= 0;
tBytesCounter <= 0;
end else begin
if (in_data_valid && in_data_ready) begin
pTail <= pTail + 1;
rf[pTail] <= in_data;
tBytesCounter <= tBytesCounter + 1;
writeLock = 1;
end else writeLock = 0;
if (out_data_ready && out_data_valid) begin
pHead <= pHead + 1;
out_data <= rf[pHead];
tBytesCounter <= tBytesCounter - 1;
end
end
end
endmodule
| 7.073562 |
module bytes_conv (
input wire clk,
input wire rst_n,
input wire [3:0] byteenable_i,
input wire [31:0] address,
input wire [31:0] data_ram_rd,
output reg [31:0] data_ram_wr,
input wire [31:0] data_master_wr,
output wire stall_o,
input wire read_i,
input wire write_i,
output reg read_o,
output reg write_o
);
reg state;
wire [31:0] processed_data;
wire not_word;
assign not_word = (byteenable_i != 4'b1111 && write_i);
assign stall_o = (not_word && !state);
assign processed_data = {
(byteenable_i[3] ? data_master_wr[31:24] : data_ram_rd[31:24]),
(byteenable_i[2] ? data_master_wr[23:16] : data_ram_rd[23:16]),
(byteenable_i[1] ? data_master_wr[15:8] : data_ram_rd[15:8]),
(byteenable_i[0] ? data_master_wr[7:0] : data_ram_rd[7:0])
};
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= 1'b0;
end else if (!state && not_word) begin
state <= 1'b1;
end else begin
state <= 1'b0;
end
end
always @(*) begin
read_o <= read_i;
write_o <= write_i;
data_ram_wr <= data_master_wr;
if (stall_o) begin
read_o <= 1'b1;
write_o <= 1'b0;
end else if (state) begin
read_o <= 1'b0;
write_o <= 1'b1;
data_ram_wr <= processed_data;
end
end
endmodule
| 8.051822 |
module bytewrite_ram_1b (clk, we, addr, di, do);
//Default parameters were changed because of slow test
//parameter SIZEB = 1024;
parameter SIZE = 32;
parameter ADDR_WIDTH = 10;
parameter COL_WIDTH = 8;
parameter NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] di;
output reg [NB_COL*COL_WIDTH-1:0] do;
reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
always @(posedge clk)
begin
do <= RAM[addr];
end
generate genvar i;
for (i = 0; i < NB_COL; i = i+1)
begin
always @(posedge clk)
begin
if (we[i])
RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH];
end
end
endgenerate
endmodule
| 8.061706 |
module bytewrite_ram_32bits (
clk,
we,
addr,
din,
dout
);
parameter SIZE = 1024;
parameter ADDR_WIDTH = 12;
parameter filename = "code.hex";
localparam COL_WIDTH = 8;
localparam NB_COL = 4;
input clk;
input [NB_COL-1:0] we;
input [ADDR_WIDTH-1:0] addr;
input [NB_COL*COL_WIDTH-1:0] din;
output [NB_COL*COL_WIDTH-1:0] dout;
reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0];
integer _i;
wire [ ADDR_WIDTH-1:0] addr_dly;
reg [NB_COL*COL_WIDTH-1:0] dout_int;
initial begin
`ifndef NO_RAM_INIT
$readmemh(filename, RAM);
`endif
// #10;
// // Just for debugging readmemh in case it does not work as expected
// for(_i=0;_i<6;_i=_i+1) begin
// $display("idx : %d data : %x",_i,RAM[_i]);
// end
// $display("======================");
end
always @(posedge clk) begin
dout_int <= RAM[addr];
// $display("%t -D- reading code rom : addr %x ",$realtime,addr);
end
// assign #60 dout = dout_int;
assign dout = dout_int;
// Remove the original generate statement to ease Xilinx memory bitstream patching
always @(posedge clk) begin
if (we[0]) begin
// $display("-I Write to address %x , data %x (%t)",addr,din,$realtime);
RAM[addr][(0+1)*COL_WIDTH-1:0*COL_WIDTH] <= din[(0+1)*COL_WIDTH-1:0*COL_WIDTH];
end
end
always @(posedge clk) begin
if (we[1]) RAM[addr][(1+1)*COL_WIDTH-1:1*COL_WIDTH] <= din[(1+1)*COL_WIDTH-1:1*COL_WIDTH];
end
always @(posedge clk) begin
if (we[2]) RAM[addr][(2+1)*COL_WIDTH-1:2*COL_WIDTH] <= din[(2+1)*COL_WIDTH-1:2*COL_WIDTH];
end
always @(posedge clk) begin
if (we[3]) RAM[addr][(3+1)*COL_WIDTH-1:3*COL_WIDTH] <= din[(3+1)*COL_WIDTH-1:3*COL_WIDTH];
end
endmodule
| 8.061706 |
module bytewrite_sp_ram_rf #(
parameter COL_WIDTH = 8, //byte width
parameter RAM_ADDR_WIDTH = 8,
parameter RAM_DATA_WIDTH = 128, // Data Width in bits
parameter NUM_COL = RAM_DATA_WIDTH / COL_WIDTH
//-----------------------------------------------------------------
) (
input clk,
input en,
input [NUM_COL - 1:0] wen,
input [RAM_ADDR_WIDTH - 1:0] addr,
input [RAM_DATA_WIDTH - 1:0] din,
output reg [RAM_DATA_WIDTH-1:0] dout
);
// Core Memory
reg [RAM_DATA_WIDTH-1:0] ram_block[(2**RAM_ADDR_WIDTH)-1:0];
integer i;
// Port-A Operation
always @(posedge clk) begin
if (en) begin
for (i = 0; i < NUM_COL; i = i + 1) begin
if (wen[i]) begin
ram_block[addr][i*COL_WIDTH+:COL_WIDTH] <= din[i*COL_WIDTH+:COL_WIDTH];
end
end
dout <= ram_block[addr];
end
end
endmodule
| 7.853441 |
module bytewrite_tdp_ram_nc #(
//---------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL * COL_WIDTH // Data Width in bits
//---------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block[(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for (i = 0; i < NUM_COL; i = i + 1) begin
always @(posedge clkA) begin
if (enaA) begin
if (weA[i]) begin
ram_block[addrA][i*COL_WIDTH+:COL_WIDTH] <= dinA[i*COL_WIDTH+:COL_WIDTH];
end
end
end
end
endgenerate
always @(posedge clkA) begin
if (enaA) begin
if (~|weA) doutA <= ram_block[addrA];
end
end
// Port-B Operation:
generate
for (i = 0; i < NUM_COL; i = i + 1) begin
always @(posedge clkB) begin
if (enaB) begin
if (weB[i]) begin
ram_block[addrB][i*COL_WIDTH+:COL_WIDTH] <= dinB[i*COL_WIDTH+:COL_WIDTH];
end
end
end
end
endgenerate
always @(posedge clkB) begin
if (enaB) begin
if (~|weB) doutB <= ram_block[addrB];
end
end
endmodule
| 7.167192 |
module bytewrite_tdp_ram_readfirst2 #(
//-------------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL * COL_WIDTH // Data Width in bits
//-------------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block[(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for (i = 0; i < NUM_COL; i = i + 1) begin
always @(posedge clkA) begin
if (enaA) begin
if (weA[i]) begin
ram_block[addrA][i*COL_WIDTH+:COL_WIDTH] <= dinA[i*COL_WIDTH+:COL_WIDTH];
end
end
end
end
endgenerate
always @(posedge clkA) begin
if (enaA) begin
doutA <= ram_block[addrA];
end
end
// Port-B Operation:
generate
for (i = 0; i < NUM_COL; i = i + 1) begin
always @(posedge clkB) begin
if (enaB) begin
if (weB[i]) begin
ram_block[addrB][i*COL_WIDTH+:COL_WIDTH] <= dinB[i*COL_WIDTH+:COL_WIDTH];
end
end
end
end
endgenerate
always @(posedge clkB) begin
if (enaB) begin
doutB <= ram_block[addrB];
end
end
endmodule
| 7.167192 |
module bytewrite_tdp_ram_rf #(
//--------------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL * COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block[(2**ADDR_WIDTH)-1:0];
integer i;
// Port-A Operation
always @(posedge clkA) begin
if (enaA) begin
for (i = 0; i < NUM_COL; i = i + 1) begin
if (weA[i]) begin
ram_block[addrA][i*COL_WIDTH+:COL_WIDTH] <= dinA[i*COL_WIDTH+:COL_WIDTH];
end
end
doutA <= ram_block[addrA];
end
end
// Port-B Operation:
always @(posedge clkB) begin
if (enaB) begin
for (i = 0; i < NUM_COL; i = i + 1) begin
if (weB[i]) begin
ram_block[addrB][i*COL_WIDTH+:COL_WIDTH] <= dinB[i*COL_WIDTH+:COL_WIDTH];
end
end
doutB <= ram_block[addrB];
end
end
endmodule
| 7.167192 |
module bytewrite_tdp_ram_wf #(
//----------------------------------------------------------------------
parameter NUM_COL = 4,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2**ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL * COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input clkA,
input enaA,
input [NUM_COL-1:0] weA,
input [ADDR_WIDTH-1:0] addrA,
input [DATA_WIDTH-1:0] dinA,
output reg [DATA_WIDTH-1:0] doutA,
input clkB,
input enaB,
input [NUM_COL-1:0] weB,
input [ADDR_WIDTH-1:0] addrB,
input [DATA_WIDTH-1:0] dinB,
output reg [DATA_WIDTH-1:0] doutB
);
// Core Memory
reg [DATA_WIDTH-1:0] ram_block[(2**ADDR_WIDTH)-1:0];
// Port-A Operation
generate
genvar i;
for (i = 0; i < NUM_COL; i = i + 1) begin
always @(posedge clkA) begin
if (enaA) begin
if (weA[i]) begin
ram_block[addrA][i*COL_WIDTH+:COL_WIDTH] <= dinA[i*COL_WIDTH+:COL_WIDTH];
doutA[i*COL_WIDTH+:COL_WIDTH] <= dinA[i*COL_WIDTH+:COL_WIDTH];
end else begin
doutA[i*COL_WIDTH+:COL_WIDTH] <= ram_block[addrA][i*COL_WIDTH+:COL_WIDTH];
end
end
end
end
endgenerate
// Port-B Operation:
generate
for (i = 0; i < NUM_COL; i = i + 1) begin
always @(posedge clkB) begin
if (enaB) begin
if (weB[i]) begin
ram_block[addrB][i*COL_WIDTH+:COL_WIDTH] <= dinB[i*COL_WIDTH+:COL_WIDTH];
doutB[i*COL_WIDTH+:COL_WIDTH] <= dinB[i*COL_WIDTH+:COL_WIDTH];
end else begin
doutB[i*COL_WIDTH+:COL_WIDTH] <= ram_block[addrB][i*COL_WIDTH+:COL_WIDTH];
end
end
end
end
endgenerate
endmodule
| 7.167192 |
module dphy_rx_byte_align (
input clock, // byte clock
input reset, // active high sync reset
input enable, // byte clock enable
input [7:0] deser_byte, // raw bytes from iserdes
input wait_for_sync, // when high will look for a sync pattern if sync not already found
input packet_done, // assert to reset synchronisation status
output reg valid_data, // goes high as soon as sync pattern is found (so data out on next cycle contains header)
output reg [7:0] data_out //aligned data out, typically delayed by 2 cycles
);
reg [7:0] curr_byte;
reg [7:0] last_byte;
wire [7:0] shifted_byte;
reg found_sync;
reg [2:0] sync_offs; // found offset of sync pattern
reg [2:0] data_offs; // current data offset
always @(posedge clock) begin
if (reset) begin
valid_data <= 1'b0;
last_byte <= 0;
curr_byte <= 0;
data_out <= 0;
data_offs <= 0;
end else if (enable) begin
last_byte <= curr_byte;
curr_byte <= deser_byte;
data_out <= shifted_byte;
if (packet_done) begin
valid_data <= found_sync;
end else if (wait_for_sync && found_sync && !valid_data) begin
// Waiting for sync, just found it now so use sync position as offset
valid_data <= 1'b1;
data_offs <= sync_offs;
end
end
end
localparam [7:0] sync_word = 8'b10111000;
reg was_found;
reg [2:0] offset;
integer i;
wire [15:0] concat_word = {curr_byte, last_byte};
always @(*) begin
offset = 0;
was_found = 1'b0;
found_sync = 1'b0;
sync_offs = 0;
for (i = 0; i < 8; i = i + 1) begin
if ((concat_word[(1+i)+:8] == sync_word) && ((last_byte & ~((~1) << i)) == 0)) begin
was_found = 1'b1;
offset = i;
end
end
if (was_found) begin
found_sync = 1'b1;
sync_offs = offset;
end
end
assign shifted_byte = concat_word[(1+data_offs)+:8];
endmodule
| 6.764326 |
module byte_destuffing (
input clk,
rst,
input sop_delin,
eop_delin,
input [7:0] data_delin,
output reg sop_des,
eop_des,
output reg [7:0] data_des
);
reg [3:0] wr_pnt, rd_pnt;
reg [7:0] mem[9:0];
reg start, flag, last;
always @(posedge clk) begin
if (rst) begin
mem[0] <= 0; //fifo initially becomes zero
mem[1] <= 0;
mem[2] <= 0;
mem[3] <= 0;
mem[4] <= 0;
mem[5] <= 0;
mem[6] <= 0;
mem[7] <= 0;
mem[8] <= 0;
mem[9] <= 0;
//mem[10]<=0;
//mem[11]<=0;
//mem[12]<=0;
//mem[13]<=0;
//mem[14]<=0;
//mem[15]<=0;
wr_pnt <= 0;
start <= 0;
//flag<=0; mem[10]<=0;
// mem[11]<=0;
// mem[12]<=0;
// mem[13]<=0;
// mem[14]<=0;
// mem[15]<=0;
// wr_pnt<=0;
end // write into fifo
else if(sop_delin)// if sop_delin is high data starts to come in
begin
start <= 1'b1; // valid signal to take data when both sop and eop are low
if (data_delin == 8'h7d) //if data=7d then make flad as high
flag = 1'b1;
else // if data is anything apart from 7d then directly store it in the fifo
begin
mem[wr_pnt] = data_delin;
wr_pnt = wr_pnt + 1'b1;
end
end
else if(eop_delin==0 && start==1'b1) // if eop is low and start valid id high
begin
if (data_delin == 8'h7d) // same as above
flag = 1'b1;
else begin
mem[wr_pnt] = data_delin;
wr_pnt = wr_pnt + 1'b1;
end
end
else if(eop_delin)// if eop is high the last byte of the data has to be read so this block
begin
start = 0;
if (data_delin == 8'h7d) flag = 1'b1;
else begin
mem[wr_pnt] = data_delin;
end
end
if (flag == 1'b1) begin
mem[wr_pnt] = data_delin ^ 8'h20;
wr_pnt = wr_pnt + 1'b1;
flag = 1'b0;
end
end
//if data is 7d
//always@(posedge clk)// if data is 7d and flag is high then neglect 7d and xor the succeding byte with 20
//begin
// if(flag==1'b1)
// begin
// mem[wr_pnt]=data_delin^8'h20;
// wr_pnt=wr_pnt+1'b1;
// flag=1'b0;
// end
//end
//read operation
always @(posedge clk) begin
if (rst) begin
data_des = 0;
sop_des = 0;
eop_des = 0;
rd_pnt = 0;
last = 0;
end
else if(eop_delin)// if eop_delin goes high then read starts
begin
sop_des = 1'b1;
data_des = mem[rd_pnt];
rd_pnt = rd_pnt + 1'b1;
last = 1'b1;
end else if (eop_des == 0 && last == 1'b1) begin
sop_des = 1'b0;
data_des = mem[rd_pnt];
rd_pnt = rd_pnt + 1'b1;
if (wr_pnt == rd_pnt) //as soon as fifo is completly read ,read operation goes low
eop_des = 1'b1;
end else begin
eop_des = 0;
data_des = 0;
last = 0;
end
end
endmodule
| 6.748698 |
module byte_enabled_true_dual_port_ram #(
parameter int BYTE_WIDTH = 8,
ADDRESS_WIDTH = 6,
BYTES = 4,
DATA_WIDTH_R = BYTE_WIDTH * BYTES
) (
input [ADDRESS_WIDTH-1:0] addr1,
input [ADDRESS_WIDTH-1:0] addr2,
input [BYTES-1:0] be1,
input [BYTES-1:0] be2,
input [BYTE_WIDTH-1:0] data_in1,
input [BYTE_WIDTH-1:0] data_in2,
input we1,
we2,
clk,
output [DATA_WIDTH_R-1:0] data_out1,
output [DATA_WIDTH_R-1:0] data_out2
);
localparam RAM_DEPTH = 1 << ADDRESS_WIDTH;
// model the RAM with two dimensional packed array
logic [BYTES-1:0][BYTE_WIDTH-1:0] ram[0:RAM_DEPTH-1];
reg [DATA_WIDTH_R-1:0] data_reg1;
reg [DATA_WIDTH_R-1:0] data_reg2;
// port A
always @(posedge clk) begin
if (we1) begin
// edit this code if using other than four bytes per word
if (be1[0]) ram[addr1][0] <= data_in1;
if (be1[1]) ram[addr1][1] <= data_in1;
if (be1[2]) ram[addr1][2] <= data_in1;
if (be1[3]) ram[addr1][3] <= data_in1;
end
data_reg1 <= ram[addr1];
end
assign data_out1 = data_reg1;
// port B
always @(posedge clk) begin
if (we2) begin
// edit this code if using other than four bytes per word
if (be2[0]) ram[addr2][0] <= data_in2;
if (be2[1]) ram[addr2][1] <= data_in2;
if (be2[2]) ram[addr2][2] <= data_in2;
if (be2[3]) ram[addr2][3] <= data_in2;
end
data_reg2 <= ram[addr2];
end
assign data_out2 = data_reg2;
endmodule
| 8.632056 |
module byte_enable_generator (
clk,
reset,
// master side
write_in,
byteenable_in,
waitrequest_out,
// fabric side
byteenable_out,
waitrequest_in
);
parameter BYTEENABLE_WIDTH = 4; // valid byteenable widths are 1, 2, 4, 8, 16, 32, 64, and 128
input clk;
input reset;
input write_in; // will enable state machine logic
input [BYTEENABLE_WIDTH-1:0] byteenable_in; // byteenables from master which contain unsupported groupings of byte lanes to be converted
output wire waitrequest_out; // used to stall the master when fabric asserts waitrequest or access needs to be broken down
output wire [BYTEENABLE_WIDTH-1:0] byteenable_out; // supported byte enables to the fabric
input waitrequest_in; // waitrequest from the fabric
generate
if (BYTEENABLE_WIDTH == 1) // for completeness...
begin
assign byteenable_out = byteenable_in;
assign waitrequest_out = waitrequest_in;
end else if (BYTEENABLE_WIDTH == 2) begin
sixteen_bit_byteenable_FSM the_sixteen_bit_byteenable_FSM ( // pass through for the most part like the 1 bit case, has it's own module since the 4 bit module uses it
.write_in(write_in),
.byteenable_in(byteenable_in),
.waitrequest_out(waitrequest_out),
.byteenable_out(byteenable_out),
.waitrequest_in(waitrequest_in)
);
end else if (BYTEENABLE_WIDTH == 4) begin
thirty_two_bit_byteenable_FSM the_thirty_two_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(write_in),
.byteenable_in(byteenable_in),
.waitrequest_out(waitrequest_out),
.byteenable_out(byteenable_out),
.waitrequest_in(waitrequest_in)
);
end else if (BYTEENABLE_WIDTH == 8) begin
sixty_four_bit_byteenable_FSM the_sixty_four_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(write_in),
.byteenable_in(byteenable_in),
.waitrequest_out(waitrequest_out),
.byteenable_out(byteenable_out),
.waitrequest_in(waitrequest_in)
);
end else if (BYTEENABLE_WIDTH == 16) begin
one_hundred_twenty_eight_bit_byteenable_FSM the_one_hundred_twenty_eight_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(write_in),
.byteenable_in(byteenable_in),
.waitrequest_out(waitrequest_out),
.byteenable_out(byteenable_out),
.waitrequest_in(waitrequest_in)
);
end else if (BYTEENABLE_WIDTH == 32) begin
two_hundred_fifty_six_bit_byteenable_FSM the_two_hundred_fifty_six_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(write_in),
.byteenable_in(byteenable_in),
.waitrequest_out(waitrequest_out),
.byteenable_out(byteenable_out),
.waitrequest_in(waitrequest_in)
);
end else if (BYTEENABLE_WIDTH == 64) begin
five_hundred_twelve_bit_byteenable_FSM the_five_hundred_twelve_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(write_in),
.byteenable_in(byteenable_in),
.waitrequest_out(waitrequest_out),
.byteenable_out(byteenable_out),
.waitrequest_in(waitrequest_in)
);
end else if (BYTEENABLE_WIDTH == 128) begin
one_thousand_twenty_four_byteenable_FSM the_one_thousand_twenty_four_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(write_in),
.byteenable_in(byteenable_in),
.waitrequest_out(waitrequest_out),
.byteenable_out(byteenable_out),
.waitrequest_in(waitrequest_in)
);
end
endgenerate
endmodule
| 8.933273 |
module five_hundred_twelve_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [63:0] byteenable_in;
output wire waitrequest_out;
output wire [63:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @(posedge clk or posedge reset) begin
if (reset) begin
state_bit <= 0;
end else begin
if (transfer_done == 1) begin
state_bit <= 0;
end else if (advance_to_next_state == 1) begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[31:0] != 0);
assign full_lower_half_transfer = (byteenable_in[31:0] == 32'hFFFFFFFF);
assign partial_upper_half_transfer = (byteenable_in[63:32] != 0);
assign full_upper_half_transfer = (byteenable_in[63:32] == 32'hFFFFFFFF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
two_hundred_fifty_six_bit_byteenable_FSM lower_two_hundred_fifty_six_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(lower_enable),
.byteenable_in(byteenable_in[31:0]),
.waitrequest_out(lower_stall),
.byteenable_out(byteenable_out[31:0]),
.waitrequest_in(waitrequest_in)
);
two_hundred_fifty_six_bit_byteenable_FSM upper_two_hundred_fifty_six_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(upper_enable),
.byteenable_in(byteenable_in[63:32]),
.waitrequest_out(upper_stall),
.byteenable_out(byteenable_out[63:32]),
.waitrequest_in(waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
| 6.522024 |
module sixty_four_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [7:0] byteenable_in;
output wire waitrequest_out;
output wire [7:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @(posedge clk or posedge reset) begin
if (reset) begin
state_bit <= 0;
end else begin
if (transfer_done == 1) begin
state_bit <= 0;
end else if (advance_to_next_state == 1) begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[3:0] != 0);
assign full_lower_half_transfer = (byteenable_in[3:0] == 4'hF);
assign partial_upper_half_transfer = (byteenable_in[7:4] != 0);
assign full_upper_half_transfer = (byteenable_in[7:4] == 4'hF);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
thirty_two_bit_byteenable_FSM lower_thirty_two_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(lower_enable),
.byteenable_in(byteenable_in[3:0]),
.waitrequest_out(lower_stall),
.byteenable_out(byteenable_out[3:0]),
.waitrequest_in(waitrequest_in)
);
thirty_two_bit_byteenable_FSM upper_thirty_two_bit_byteenable_FSM (
.clk(clk),
.reset(reset),
.write_in(upper_enable),
.byteenable_in(byteenable_in[7:4]),
.waitrequest_out(upper_stall),
.byteenable_out(byteenable_out[7:4]),
.waitrequest_in(waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
| 6.848656 |
module thirty_two_bit_byteenable_FSM (
clk,
reset,
write_in,
byteenable_in,
waitrequest_out,
byteenable_out,
waitrequest_in
);
input clk;
input reset;
input write_in;
input [3:0] byteenable_in;
output wire waitrequest_out;
output wire [3:0] byteenable_out;
input waitrequest_in;
// internal statemachine signals
wire partial_lower_half_transfer;
wire full_lower_half_transfer;
wire partial_upper_half_transfer;
wire full_upper_half_transfer;
wire full_word_transfer;
reg state_bit;
wire transfer_done;
wire advance_to_next_state;
wire lower_enable;
wire upper_enable;
wire lower_stall;
wire upper_stall;
wire two_stage_transfer;
always @(posedge clk or posedge reset) begin
if (reset) begin
state_bit <= 0;
end else begin
if (transfer_done == 1) begin
state_bit <= 0;
end else if (advance_to_next_state == 1) begin
state_bit <= 1;
end
end
end
assign partial_lower_half_transfer = (byteenable_in[1:0] != 0);
assign full_lower_half_transfer = (byteenable_in[1:0] == 2'h3);
assign partial_upper_half_transfer = (byteenable_in[3:2] != 0);
assign full_upper_half_transfer = (byteenable_in[3:2] == 2'h3);
assign full_word_transfer = (full_lower_half_transfer == 1) & (full_upper_half_transfer == 1);
assign two_stage_transfer = (full_word_transfer == 0) & (partial_lower_half_transfer == 1) & (partial_upper_half_transfer == 1);
assign advance_to_next_state = (two_stage_transfer == 1) & (lower_stall == 0) & (write_in == 1) & (state_bit == 0) & (waitrequest_in == 0); // partial lower half transfer completed and there are bytes in the upper half that need to go out still
assign transfer_done = ((full_word_transfer == 1) & (waitrequest_in == 0) & (write_in == 1)) | // full word transfer complete
((two_stage_transfer == 0) & (lower_stall == 0) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)) | // partial upper or lower half transfer complete
((two_stage_transfer == 1) & (state_bit == 1) & (upper_stall == 0) & (write_in == 1) & (waitrequest_in == 0)); // partial upper and lower half transfers complete
assign lower_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_lower_half_transfer == 1)) | // only a partial lower half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_lower_half_transfer == 1) & (state_bit == 0)); // partial lower half transfer (to be followed by an upper half transfer)
assign upper_enable = ((write_in == 1) & (full_word_transfer == 1)) | // full word transfer
((write_in == 1) & (two_stage_transfer == 0) & (partial_upper_half_transfer == 1)) | // only a partial upper half transfer
((write_in == 1) & (two_stage_transfer == 1) & (partial_upper_half_transfer == 1) & (state_bit == 1)); // partial upper half transfer (after the lower half transfer)
sixteen_bit_byteenable_FSM lower_sixteen_bit_byteenable_FSM (
.write_in(lower_enable),
.byteenable_in(byteenable_in[1:0]),
.waitrequest_out(lower_stall),
.byteenable_out(byteenable_out[1:0]),
.waitrequest_in(waitrequest_in)
);
sixteen_bit_byteenable_FSM upper_sixteen_bit_byteenable_FSM (
.write_in(upper_enable),
.byteenable_in(byteenable_in[3:2]),
.waitrequest_out(upper_stall),
.byteenable_out(byteenable_out[3:2]),
.waitrequest_in(waitrequest_in)
);
assign waitrequest_out = (waitrequest_in == 1) | ((transfer_done == 0) & (write_in == 1));
endmodule
| 6.672265 |
module byte_endian_converter (
ENABLE,
DATA_IN,
DATA_OUT
);
parameter DATA_WIDTH = 32; //8, 16, 32, 64
input ENABLE;
input [DATA_WIDTH-1:0] DATA_IN;
output [DATA_WIDTH-1:0] DATA_OUT;
generate
if (DATA_WIDTH == 8) begin //no byte endian is required, passthrough
assign DATA_OUT = DATA_IN;
end else if (DATA_WIDTH == 16) begin
assign DATA_OUT = ENABLE ? {DATA_IN[7:0], DATA_IN[15:8]} : DATA_IN;
end else if (DATA_WIDTH == 32) begin
assign DATA_OUT = ENABLE? {DATA_IN[7:0], DATA_IN[15:8], DATA_IN[23:16], DATA_IN[31:24]}: DATA_IN;
end else if (DATA_WIDTH == 64) begin
assign DATA_OUT = ENABLE? {DATA_IN[7:0], DATA_IN[15:8], DATA_IN[23:16], DATA_IN[31:24], DATA_IN[39:32], DATA_IN[47:40], DATA_IN[55:48], DATA_IN[63:56]}: DATA_IN;
end
endgenerate
endmodule
| 8.95288 |
module Byte_Entry_Unit (
input [1:0] A1_0,
input [1:0] BEControl,
output [3:0] BE
);
assign BE = (BEControl == 2'b01 && A1_0 == 2'b00) ? 4'b0001 : // 01: ֽ
(BEControl==2'b01 && A1_0==2'b01) ? 4'b0010 :
(BEControl==2'b01 && A1_0==2'b10) ? 4'b0100 :
(BEControl==2'b01 && A1_0==2'b11) ? 4'b1000 :
(BEControl==2'b10 && A1_0==2'b00) ? 4'b0011 : // 10:
(BEControl == 2'b10 && A1_0 == 2'b10) ? 4'b1100 : 4'b1111;
endmodule
| 7.007263 |
module byte_en_reg (
clk,
rst,
we,
en,
d,
q
);
parameter DATA_W = 32;
parameter INIT_VAL = {DATA_W{1'b0}};
input clk;
input rst;
input we;
input [(DATA_W-1)/8:0] en;
input [DATA_W-1:0] d;
output reg [DATA_W-1:0] q;
integer i;
always @(posedge clk or posedge rst) begin
if (rst == 1) q <= INIT_VAL;
else for (i = 0; i < DATA_W; i = i + 1) if (we && en[i/8]) q[i] <= d[i];
end
endmodule
| 6.530968 |
module byte_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrempty,
wrfull
);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output wrempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [7:0] q = sub_wire0[7:0];
wire wrempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.aclr(aclr),
.data(data),
.rdclk(rdclk),
.rdreq(rdreq),
.wrclk(wrclk),
.wrreq(wrreq),
.q(sub_wire0),
.wrempty(sub_wire1),
.wrfull(sub_wire2),
.eccstatus(),
.rdempty(),
.rdfull(),
.rdusedw(),
.wrusedw()
);
defparam dcfifo_component.intended_device_family = "Cyclone 10 LP",
dcfifo_component.lpm_numwords = 16, dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo", dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 4, dcfifo_component.overflow_checking = "OFF",
dcfifo_component.rdsync_delaypipe = 4, dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "OFF", dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF", dcfifo_component.wrsync_delaypipe = 4;
endmodule
| 6.654152 |
module byte_mixcolum (
a,
b,
c,
d,
outx,
outy
);
input [7:0] a, b, c, d;
output [7:0] outx, outy;
reg [7:0] outx, outy;
function [7:0] xtime;
input [7:0] in;
reg [3:0] xtime_t;
begin
xtime[7:5] = in[6:4];
xtime_t[3] = in[7];
xtime_t[2] = in[7];
xtime_t[1] = 0;
xtime_t[0] = in[7];
xtime[4:1] = xtime_t ^ in[3:0];
xtime[0] = in[7];
end
endfunction
reg [7:0] w1, w2, w3, w4, w5, w6, w7, w8, outx_var;
always @(a, b, c, d) begin
w1 = a ^ b;
w2 = a ^ c;
w3 = c ^ d;
w4 = xtime(w1);
w5 = xtime(w3);
w6 = w2 ^ w4 ^ w5;
w7 = xtime(w6);
w8 = xtime(w7);
outx_var = b ^ w3 ^ w4;
outx = outx_var;
outy = w8 ^ outx_var;
end
endmodule
| 7.01994 |
module byte_RCA (
a,
b,
ci,
s,
co
);
input [7:0] a, b;
input ci;
output [7:0] s;
output co;
wire [7:0] c;
full_adder fa1 (
a[0],
b[0],
ci,
s[0],
c[0]
);
full_adder fa2 (
a[1],
b[1],
c[0],
s[1],
c[1]
);
full_adder fa3 (
a[2],
b[2],
c[1],
s[2],
c[2]
);
full_adder fa4 (
a[3],
b[3],
c[2],
s[3],
c[3]
);
full_adder fa5 (
a[4],
b[4],
c[3],
s[4],
c[4]
);
full_adder fa6 (
a[5],
b[5],
c[4],
s[5],
c[5]
);
full_adder fa7 (
a[6],
b[6],
c[5],
s[6],
c[6]
);
full_adder fa8 (
a[7],
b[7],
c[6],
s[7],
co
);
endmodule
| 7.393572 |
module byte_RCA_last (
a,
b,
ci,
s,
co,
overflow
);
input [7:0] a, b;
input ci;
output [7:0] s;
output co, overflow;
wire [6:0] c;
full_adder fa1 (
a[0],
b[0],
ci,
s[0],
c[0]
);
full_adder fa2 (
a[1],
b[1],
c[0],
s[1],
c[1]
);
full_adder fa3 (
a[2],
b[2],
c[1],
s[2],
c[2]
);
full_adder fa4 (
a[3],
b[3],
c[2],
s[3],
c[3]
);
full_adder fa5 (
a[4],
b[4],
c[3],
s[4],
c[4]
);
full_adder fa6 (
a[5],
b[5],
c[4],
s[5],
c[5]
);
full_adder fa7 (
a[6],
b[6],
c[5],
s[6],
c[6]
);
full_adder fa8 (
a[7],
b[7],
c[6],
s[7],
co
);
// Compute the overflow using last bit carry in and out
xor (overflow, co, c[6]);
endmodule
| 6.913012 |
module byte_reorder_8bit (
input [31:0] data_in,
output [31:0] data_out
);
assign data_out[7:0] = data_in[31:24];
assign data_out[15:8] = data_in[23:16];
assign data_out[23:16] = data_in[15:8];
assign data_out[31:24] = data_in[7:0];
endmodule
| 7.625151 |
module byte_reorder_16 (
input [31:0] data_in,
output [31:0] data_out
);
assign data_out[15:0] = data_in[31:16];
assign data_out[31:16] = data_in[15:0];
endmodule
| 7.625151 |
module byte_sel (
input wire [2:0] addr, //address
input wire [3:0] size, //0001=1Byte;0010=2Byte;0100=4Byte;1000=8Byte
input wire mask,
output wire [7:0] bsel
);
wire [7:0] bsel_source;
wire [7:0] shift1;
wire [7:0] shift2;
assign bsel_source = {7'b0, size[0]} | {6'b0, {2{size[1]}}} | {4'b0, {4{size[2]}}} | {8{size[3]}};
assign shift1 = addr[0] ? {bsel_source[7:1], 1'b0} : bsel_source; //左移1位
assign shift2 = addr[1] ? {shift1[7:2], 2'b0} : shift1;
assign bsel = mask ? 8'b11111111 : addr[2] ? {shift2[7:4], 4'b0} : shift2;
endmodule
| 7.23177 |
module byte_shifter (
input wire unsign,
input wire [2:0] addr, //地址低3位 用于指示移位大小
input wire [3:0] size, //0001:1Byte 0010:2Byte 0100=4Byte 1000=8Byte
input wire [63:0] data_in, //要送往BIU的数据
output wire [63:0] data_lsu_cache,
//对BIU信号
output wire [63:0] data_write,
input wire [63:0] data_read
);
parameter offest0 = 3'b000;
parameter offest1 = 3'b001;
parameter offest2 = 3'b010;
parameter offest3 = 3'b011;
parameter offest4 = 3'b100;
parameter offest5 = 3'b101;
parameter offest6 = 3'b110;
parameter offest7 = 3'b111;
wire [63:0] data_lsu_cache_shift; //BIU送来的数据先进行移位
//向左移位
wire [63:0] left_shift_8bit;
wire [63:0] left_shift_level0;
wire [63:0] left_shift_16bit;
wire [63:0] left_shift_level1;
wire [63:0] left_shift_32bit;
//向右对齐
//可缓存的
wire [63:0] cache_right_shift_8bit;
wire [63:0] cache_right_shift_level0;
wire [63:0] cache_right_shift_16bit;
wire [63:0] cache_right_shift_level1;
wire [63:0] cache_right_shift_32bit;
//第零级移位
assign left_shift_8bit = {data_in[55:0], 8'b0};
assign left_shift_level0 = addr[0] ? left_shift_8bit : data_in;
//第一级移位
assign left_shift_16bit = {left_shift_level0[47:0], 16'b0};
assign left_shift_level1 = addr[1] ? left_shift_16bit : left_shift_level0;
assign left_shift_32bit = {left_shift_level1[31:0], 32'b0};
assign data_write = addr[2] ? left_shift_32bit : left_shift_level1;
//送往内部的数据先移位（向右对齐）
//可缓存的数据
//第零级移位
assign cache_right_shift_8bit = {8'b0, data_read[63:8]};
assign cache_right_shift_level0 = addr[0] ? cache_right_shift_8bit : data_read;
//第一级移位
assign cache_right_shift_16bit = {16'b0, cache_right_shift_level0[63:16]};
assign cache_right_shift_level1 = addr[1] ? cache_right_shift_16bit : cache_right_shift_level0;
//第三级
assign cache_right_shift_32bit = {32'b0, cache_right_shift_level1[63:32]};
assign data_lsu_cache_shift = addr[2] ? cache_right_shift_32bit : cache_right_shift_level1;
assign data_lsu_cache = ((size[0]&!unsign)?{{56{data_lsu_cache_shift[7]}},data_lsu_cache_shift[7:0]}:64'b0)|
((size[1]&!unsign)?{{48{data_lsu_cache_shift[15]}},data_lsu_cache_shift[15:0]}:64'b0)|
((size[2]&!unsign)?{{32{data_lsu_cache_shift[31]}},data_lsu_cache_shift[31:0]}:64'b0)|
(unsign? data_lsu_cache_shift : 64'b0);
endmodule
| 9.118945 |
module byte_striping_c (
input clk_2f_c,
input reset,
input valid_in,
input [31:0] Data_in,
output reg valid_0_c,
output reg [31:0] lane_0_c,
output reg valid_1_c,
output reg [31:0] lane_1_c
);
reg contador;
always @(*) begin
if (reset == 0) begin
valid_0_c <= 0;
lane_0_c <= 0;
valid_1_c <= 0;
lane_1_c <= 0;
contador <= 0;
end
end
always @(posedge clk_2f_c) begin
if (valid_in) begin
case (contador)
1'b0: begin
contador <= 1'b1;
lane_0_c <= Data_in;
valid_0_c <= 1;
end
1'b1: begin
contador <= 1'b0;
lane_1_c <= Data_in;
valid_1_c <= 1;
end
endcase
end else begin
valid_0_c <= 0;
lane_0_c <= 0;
if (valid_0_c == 0) begin
lane_1_c <= 0;
valid_1_c <= 0;
end
end
end
endmodule
| 6.597404 |
module byte_striping_e (
clk_2f_e,
reset,
valid_in,
Data_in,
valid_0_e,
lane_0_e,
valid_1_e,
lane_1_e
);
(* src = "byte_striping_e.v:13" *)
reg _00_;
(* src = "byte_striping_e.v:13" *)
reg [31:0] _01_;
(* src = "byte_striping_e.v:13" *)
reg [31:0] _02_;
(* src = "byte_striping_e.v:13" *)
reg _03_;
(* src = "byte_striping_e.v:13" *)
reg _04_;
(* src = "byte_striping_e.v:23" *)
reg _05_;
(* src = "byte_striping_e.v:23" *)
reg [31:0] _06_;
(* src = "byte_striping_e.v:23" *)
reg [31:0] _07_;
(* src = "byte_striping_e.v:23" *)
reg _08_;
(* src = "byte_striping_e.v:23" *)
reg _09_;
(* src = "byte_striping_e.v:14" *)
wire _10_;
(* src = "byte_striping_e.v:43" *)
wire _11_;
(* src = "byte_striping_e.v:5" *)
input [31:0] Data_in;
(* src = "byte_striping_e.v:2" *)
input clk_2f_e;
(* src = "byte_striping_e.v:11" *)
reg contador;
(* src = "byte_striping_e.v:7" *)
output [31:0] lane_0_e;
reg [31:0] lane_0_e;
(* src = "byte_striping_e.v:9" *)
output [31:0] lane_1_e;
reg [31:0] lane_1_e;
(* src = "byte_striping_e.v:3" *)
input reset;
(* src = "byte_striping_e.v:6" *)
output valid_0_e;
reg valid_0_e;
(* src = "byte_striping_e.v:8" *)
output valid_1_e;
reg valid_1_e;
(* src = "byte_striping_e.v:4" *)
input valid_in;
assign _10_ = ~(* src = "byte_striping_e.v:14" *) reset;
assign _11_ = ~(* src = "byte_striping_e.v:43" *) valid_0_e;
always @* begin
_04_ = valid_1_e;
_02_ = lane_1_e;
_00_ = contador;
_03_ = valid_0_e;
_01_ = lane_0_e;
(* src = "byte_striping_e.v:14" *)
casez (_10_)
/* src = "byte_striping_e.v:14" */
1'h1: begin
_03_ = 1'h0;
_01_ = 32'd0;
_04_ = 1'h0;
_02_ = 32'd0;
_00_ = 1'h0;
end
default:
/* empty */;
endcase
end
always @* begin
valid_1_e <= _04_;
lane_1_e <= _02_;
contador <= _00_;
valid_0_e <= _03_;
lane_0_e <= _01_;
end
always @* begin
_09_ = valid_1_e;
_07_ = lane_1_e;
_05_ = contador;
_08_ = valid_0_e;
_06_ = lane_0_e;
(* src = "byte_striping_e.v:24" *)
casez (valid_in)
/* src = "byte_striping_e.v:24" */
1'h1:
(* src = "byte_striping_e.v:25" *) casez (contador)
/* src = "byte_striping_e.v:26" */
1'h0: begin
_05_ = 1'h1;
_06_ = Data_in;
_08_ = 1'h1;
end
/* src = "byte_striping_e.v:32" */
1'h1: begin
_05_ = 1'h0;
_07_ = Data_in;
_09_ = 1'h1;
end
default:
/* empty */;
endcase
/* src = "byte_striping_e.v:40" */
default: begin
_08_ = 1'h0;
_06_ = 32'd0;
(* src = "byte_striping_e.v:43" *)
casez (_11_)
/* src = "byte_striping_e.v:43" */
1'h1: begin
_07_ = 32'd0;
_09_ = 1'h0;
end
default:
/* empty */;
endcase
end
endcase
end
always @(posedge clk_2f_e) begin
valid_1_e <= _09_;
lane_1_e <= _07_;
contador <= _05_;
valid_0_e <= _08_;
lane_0_e <= _06_;
end
endmodule
| 6.597404 |
module byte_sub (
data,
out
);
input [127:0] data;
output [127:0] out;
assign out = ~data;
endmodule
| 6.617995 |
module receives 32 times 8 bits from input pins and concatenate it to
256 block to do encryption.
when it finishes receiving, transmit a pulse (done) that confirm that the block is ready to encrypt
*/
module byte_to_256(
input rst_p, // active high synchronous reset
input in_en, // High when there are more blocks to send for encryption
input clk, // internal 100MHz clock
input [7:0] part_block1, // 8 bits as part of a block
input load1, // when high- new 8 bits had been loaded to pins
output reg [255:0] block,//concatenated 32 - 8 bits
output reg done // pulse when all 32 bytes of block arrived
);
reg [4:0] adrs;
reg msb_adrs;
reg [255:0] tmp_block;
wire tc;
wire load_en, load_block;
reg r1, r2, r3 ,r4;
wire done_en;
reg [7:0] part_block;
reg load;
/*
Because the Raspberry Pi Zero pulses are not exact with their length and not reliable,
we made logic that detects positive edges and do an internal - clock width - pulse and reliable.
*/
always @(posedge clk) begin // logic that avoids Z state on inputs.
if ( rst_p == 1'b1)
load <= 0;
else if(in_en == 1'b1)
load <= load1;
end
always @(posedge clk) begin // logic that does a copy of load delayed one and 2 cycles
if ( rst_p == 1'b1) begin
r3 <= 1'b0;
r4 <= 1'b0;
end
else if(in_en == 1'b1) begin
r3 <= load;
r4 <= r3;
end
end
assign load_en = load & !r3; // pulse of load
always @(posedge clk) begin // load registers when the pins are loaded with the information.
if ( rst_p == 1'b1)
part_block <= 0;
else if(load_en == 1'b1)
part_block <= part_block1;
end
assign load_block = r3 & !r4; // delayed pulse of load
always @ (posedge clk) begin
if (rst_p == 1'b1) begin // logic that concatenates 32 - 8 bits to a 32 bytes block array
adrs <= 6'h00;
tmp_block <= {255{1'b0}};
end
else if (load_block == 1'b1) begin // load_block
tmp_block[248 - 8*adrs+:8] <= part_block;
adrs <= adrs +1; // each new 8 bits the address proceed in one
end
end
always @(posedge clk) begin // logic that send the new block when the whole block arrived
if (rst_p == 1'b1)
block <= {255{1'b0}};
else if(done_en ==1'b1)
block <= tmp_block;
end
// below there is a logic that sends the done signal a clock delayed after it enters to registers
always @(posedge clk) begin
if (rst_p == 1'b1)
msb_adrs <= 1'b0;
else if(load_en == 1'b1)
msb_adrs <= adrs[4];
end
assign tc = (msb_adrs == 1'b1 && adrs == 5'b00000) ? 1'b1 : 1'b0;
always @(posedge clk) begin //change
if (rst_p == 1'b1) begin
r1 <= 1'b0;
end
else begin
r1 <=tc;
end
end
assign done_en = !r1 && tc; //change
always @ (posedge clk) // sends done signal to other blocks
begin
if(rst_p == 1'b1)
done <= 1'b0;
else begin
done <= done_en;
end
end
endmodule
| 8.579324 |
module byte_to_32bits
( input clock,
input run,
input [15:0]to_port,
input udp_rx_active,
input [7:0] udp_rx_data,
input full,
output reg fifo_wrreq,
output reg [31:0] data_out,
output reg [31:0] sequence_errors
);
parameter [15:0] port;
localparam IDLE = 1'd0, PROCESS = 1'd1;
reg [31:0] sequence_number = 0;
reg [31:0] last_sequence_number = 0;
reg [10:0] byte_number = 0;
reg [10:0] byte_counter = 0;
reg main = 0;
always @(posedge clock)
begin
if (!run)
sequence_errors <= 32'd0;
case (main)
IDLE:
begin
if (udp_rx_active && run && to_port == port) begin
sequence_number[31:24] <= udp_rx_data;
byte_counter <= 0;
byte_number <= 0;
main <= PROCESS;
end
end
PROCESS:
begin
case (byte_number)
0: begin
sequence_number[23:16] <= udp_rx_data;
byte_number <= 1;
end
1: begin
sequence_number[15:8] <= udp_rx_data;
byte_number <= 2;
end
2: begin
sequence_number[7:0] <= udp_rx_data;
byte_number <= 3;
end
3: begin
fifo_wrreq <= 0; // have sequence number so now save the I&Q data
data_out[31:24] <= udp_rx_data;
byte_number <= 4;
end
4: begin
data_out[23:16] <= udp_rx_data;
byte_number <= 5;
end
5: begin
data_out[15:8] <= udp_rx_data;
byte_number <= 6;
end
6: begin
data_out[7:0] <= udp_rx_data;
if(byte_counter == 64) begin // MUST get 1440 bytes = 360 x 32 bit I&Q samples. // ** was 360
if (sequence_number != last_sequence_number + 1'b1)
sequence_errors <= sequence_errors + 1'b1;
last_sequence_number <= sequence_number;
byte_counter <= 0;
byte_number <= 0;
if (!udp_rx_active) // only return to IDLE state when udp_rx_active has dropped
main <= IDLE;
end
else begin
if(!full) fifo_wrreq <= 1'b1; // only write to the fifo if not full.
byte_number <= 3;
byte_counter <= byte_counter + 11'd1;
end
end
default: byte_number <= 0;
endcase // byte_number
end
endcase // main
// if (byte_number == 11'd4) Audio_sequence_number <= sequence_number;
end
endmodule
| 7.98739 |
module byte_to_48bits
( input clock,
input run,
input [15:0]to_port,
input udp_rx_active,
input [7:0] udp_rx_data,
input full,
output reg fifo_wrreq,
output reg [47:0] data_out,
output reg [31:0] sequence_errors
);
parameter [15:0] port;
localparam IDLE = 1'd0, PROCESS = 1'd1;
reg [31:0] sequence_number = 0;
reg [31:0] last_sequence_number = 0;
reg [10:0] byte_number;
reg [10:0] byte_counter;
reg main = 0;
always @(posedge clock) begin
if (!run)
sequence_errors <= 32'd0;
case (main)
IDLE: begin
if (udp_rx_active && run && to_port == port) begin
sequence_number[31:24] <= udp_rx_data;
byte_counter <= 0;
byte_number <= 0;
main <= PROCESS;
end
end
PROCESS: begin
case (byte_number)
0: begin
sequence_number[23:16] <= udp_rx_data;
byte_number <= 1;
end
1: begin
sequence_number[15:8] <= udp_rx_data;
byte_number <= 2;
end
2: begin
sequence_number[7:0] <= udp_rx_data;
byte_number <= 3;
end
3: begin
fifo_wrreq <= 0; // have sequence number so now save the I&Q data
data_out[47:40] <= udp_rx_data;
byte_number <= 4;
end
4: begin
data_out[39:32] <= udp_rx_data;
byte_number <= 5;
end
5: begin
data_out[31:24] <= udp_rx_data;
byte_number <= 6;
end
6: begin
data_out[23:16] <= udp_rx_data;
byte_number <= 7;
end
7: begin
data_out[15:8] <= udp_rx_data;
byte_number <= 8;
end
8: begin
data_out[7:0] <= udp_rx_data;
if(byte_counter == 240) begin // MUST get 1440 bytes = 240 x 48 bit I&Q samples.
if (sequence_number != last_sequence_number + 1'b1)
sequence_errors <= sequence_errors + 1'b1;
last_sequence_number <= sequence_number;
byte_counter <= 0;
byte_number <= 0;
if (!udp_rx_active) // only return to IDLE state when udp_rx_active has dropped
main <= IDLE;
end
else begin
if(!full) fifo_wrreq <= 1'b1; // only write to the fifo if not full.
byte_number <= 3;
byte_counter <= byte_counter + 11'd1;
end
end
default: byte_number <= 0;
endcase // byte_number
end
endcase // main
// if (byte_number == 11'd4) Audio_sequence_number <= sequence_number;
end
endmodule
| 7.217568 |
module byte_to_hex (
input [3:0] b,
output [7:0] h
);
assign h = (b < 10 ? "0" + b : "A" + (b - 10));
endmodule
| 6.661181 |
module byte_un_striping (
input clk_2f,
input clk,
input valid_0,
input [31:0] lane_0,
input valid_1,
input [31:0] lane_1,
output reg [31:0] data_out,
output reg valid_out
);
reg [1:0] counter;
always @(posedge clk_2f) begin
if (valid_0 == 0) begin
counter <= 2'b10;
end else begin
counter <= counter + 1;
end
end
always @(*) begin
if (valid_0 == 0) begin
valid_out = 0;
data_out = 'h00000000;
end else begin
case (counter)
2'b00: begin
data_out = lane_0;
valid_out = valid_0;
end
2'b01: begin
data_out = lane_1;
valid_out = valid_0;
end
2'b10: begin
data_out = lane_0;
valid_out = valid_0;
end
2'b11: begin
data_out = lane_1;
valid_out = valid_0;
end
endcase
end
end
endmodule
| 6.743712 |
module byte_un_striping_c (
input clk_2f_c,
input reset,
input valid_0,
input [31:0] lane_0,
input valid_1,
input [31:0] lane_1,
output reg valid_out_c,
output reg [31:0] Data_out_c
);
reg contador;
always @(*) begin
if (reset == 0) begin
valid_out_c <= 0;
Data_out_c <= 32'b0;
contador <= 1;
end
end
always @(posedge clk_2f_c) begin
case (contador)
1'b0: begin
if (valid_0) begin
contador <= 1;
valid_out_c <= 1;
Data_out_c <= lane_0;
end else begin
contador <= 1;
valid_out_c <= 0;
Data_out_c <= 32'b0;
end
end
1'b1: begin
if (valid_1) begin
contador <= 0;
valid_out_c <= 1;
Data_out_c <= lane_1;
end else begin
contador <= 0;
valid_out_c <= 0;
Data_out_c <= 32'b0;
end
end
endcase
end
endmodule
| 6.743712 |
module byte_un_striping_e (
clk_2f_e,
reset,
valid_0,
lane_0,
valid_1,
lane_1,
valid_out_e,
Data_out_e
);
(* src = "byte_un_striping_e.v:13" *)
reg [31:0] _0_;
(* src = "byte_un_striping_e.v:13" *)
reg _1_;
(* src = "byte_un_striping_e.v:13" *)
reg _2_;
(* src = "byte_un_striping_e.v:21" *)
reg [31:0] _3_;
(* src = "byte_un_striping_e.v:21" *)
reg _4_;
(* src = "byte_un_striping_e.v:21" *)
reg _5_;
(* src = "byte_un_striping_e.v:14" *)
wire _6_;
(* src = "byte_un_striping_e.v:9" *)
output [31:0] Data_out_e;
reg [31:0] Data_out_e;
(* src = "byte_un_striping_e.v:2" *)
input clk_2f_e;
(* src = "byte_un_striping_e.v:11" *)
reg contador;
(* src = "byte_un_striping_e.v:5" *)
input [31:0] lane_0;
(* src = "byte_un_striping_e.v:7" *)
input [31:0] lane_1;
(* src = "byte_un_striping_e.v:3" *)
input reset;
(* src = "byte_un_striping_e.v:4" *)
input valid_0;
(* src = "byte_un_striping_e.v:6" *)
input valid_1;
(* src = "byte_un_striping_e.v:8" *)
output valid_out_e;
reg valid_out_e;
assign _6_ = ~(* src = "byte_un_striping_e.v:14" *) reset;
always @* begin
_2_ = valid_out_e;
_0_ = Data_out_e;
_1_ = contador;
(* src = "byte_un_striping_e.v:14" *)
casez (_6_)
/* src = "byte_un_striping_e.v:14" */
1'h1: begin
_2_ = 1'h0;
_0_ = 32'd0;
_1_ = 1'h1;
end
default:
/* empty */;
endcase
end
always @* begin
valid_out_e <= _2_;
Data_out_e <= _0_;
contador <= _1_;
end
always @* begin
_5_ = valid_out_e;
_3_ = Data_out_e;
_4_ = contador;
(* src = "byte_un_striping_e.v:22" *)
casez (contador)
/* src = "byte_un_striping_e.v:23" */
1'h0:
(* src = "byte_un_striping_e.v:25" *) casez (valid_0)
/* src = "byte_un_striping_e.v:25" */
1'h1: begin
_4_ = 1'h1;
_5_ = 1'h1;
_3_ = lane_0;
end
/* src = "byte_un_striping_e.v:30" */
default: begin
_4_ = 1'h1;
_5_ = 1'h0;
_3_ = 32'd0;
end
endcase
/* src = "byte_un_striping_e.v:36" */
1'h1:
(* src = "byte_un_striping_e.v:38" *) casez (valid_1)
/* src = "byte_un_striping_e.v:38" */
1'h1: begin
_4_ = 1'h0;
_5_ = 1'h1;
_3_ = lane_1;
end
/* src = "byte_un_striping_e.v:43" */
default: begin
_4_ = 1'h0;
_5_ = 1'h0;
_3_ = 32'd0;
end
endcase
default:
/* empty */;
endcase
end
always @(posedge clk_2f_e) begin
valid_out_e <= _5_;
Data_out_e <= _3_;
contador <= _4_;
end
endmodule
| 6.743712 |
module top (
input wire CLK_IN,
input wire RST_N,
output wire [2:0] RGB_LED,
output wire BZ
);
reg [23:0] counter;
reg led;
reg buzz;
always @(posedge CLK_IN) begin
if (RST_N == 1'b0) begin
counter <= 24'd0;
led <= 1'b0;
buzz <= 1'b0;
end else begin
if (counter == 12000000 / 440) begin
led <= ~led;
counter <= 24'd0;
buzz <= ~buzz;
end else begin
counter <= counter + 24'd1;
end
end
end
assign RGB_LED = led ? 3'b111 : 3'b110;
assign BZ = buzz;
endmodule
| 7.233807 |
module B_8xBin2BCD (
input [7:0] numBin,
output [9:0] numBCD
);
/*
8-BIT BINARY TO BCD CONVERTER
-----------------------------
[+] Using Double Dabble
[+] Flow: https://johnloomis.org/ece314/notes/devices/binary_to_BCD/bcd04.png
*/
wire [3:0] add3Out[6:0];
B_add3BCD C1 (
{1'b0, numBin[7:5]},
add3Out[6][3:0]
);
B_add3BCD C2 (
{add3Out[6][2:0], numBin[4]},
add3Out[5][3:0]
);
B_add3BCD C3 (
{add3Out[5][2:0], numBin[3]},
add3Out[4][3:0]
);
B_add3BCD C4 (
{add3Out[4][2:0], numBin[2]},
add3Out[3][3:0]
);
B_add3BCD C5 (
{add3Out[3][2:0], numBin[1]},
add3Out[2][3:0]
);
B_add3BCD C6 (
{1'b0, add3Out[6][3], add3Out[5][3], add3Out[4][3]},
add3Out[1][3:0]
);
B_add3BCD C7 (
{add3Out[1][2:0], add3Out[3][3]},
add3Out[0][3:0]
);
assign numBCD[9] = add3Out[1][3];
assign numBCD[8:5] = add3Out[0][3:0];
assign numBCD[4:1] = add3Out[2][3:0];
assign numBCD[0] = numBin[0];
endmodule
| 6.914008 |
module B_add3BCD (
input [3:0] numIN,
output [3:0] numOT
);
/*
Adds 3 if input > 4.
Y3 | A + BC + BD
Y2 | AD + BC'D'
Y1 | B'C + CD + AD'
Y0 | AD' + A'B'D + BCD'
*/
assign numOT[3] = ((numIN[3]) | (numIN[2] & numIN[1]) | (numIN[2] & numIN[0]));
assign numOT[2] = ((numIN[3] & numIN[0]) | (numIN[2] & ~numIN[1] & ~numIN[0]));
assign numOT[1] = ((~numIN[2] & numIN[1]) | (numIN[1] & numIN[0]) | (numIN[3] & ~numIN[0]));
assign numOT[0] = ((numIN[3] & ~numIN[0]) | (~numIN[3] & ~numIN[2] & numIN[0]) | (numIN[2] & numIN[1] & ~numIN[0]));
endmodule
| 7.301121 |
module B_ADDR (
pc_add_4,
immediate,
B_Addr
);
input [31:0] immediate;
input [31:0] pc_add_4;
output [31:0] B_Addr;
wire Cout;
wire [31:0] immediate_left_2;
SHIFTER_32_L2 shift_addr_left_2 (
immediate,
immediate_left_2
);
CLA_32 cla_32 (
pc_add_4,
immediate_left_2,
1'b0,
B_Addr,
Cout
);
endmodule
| 8.030672 |
module B_is2Digit (
input [3:0] num,
output z
);
/*
Checks if the given 4-bit number is greater than 9.
*/
assign z = (num[3] & (num[2] | num[1] | num[0]));
endmodule
| 7.185124 |
module B_2dBCDAdder (
input CIN,
input [7:0] numA,
input [7:0] numB,
output COUT,
output [7:0] sumBCD
);
wire carry0;
B_1dBCDAdder add0 (
CIN,
numA[3:0],
numB[3:0],
carry0,
sumBCD[3:0]
);
B_1dBCDAdder add1 (
carry0,
numA[7:4],
numB[7:4],
COUT,
sumBCD[7:4]
);
endmodule
| 6.868066 |
module B_8xComp (
input [7:0] numA,
numB,
output LT,
EQ,
GT
);
wire [2:0] resCompL;
B_4xComp compL (
1'b0,
1'b1,
1'b0,
numA[3:0],
numB[3:0],
resCompL[2],
resCompL[1],
resCompL[0]
);
B_4xComp compH (
resCompL[2],
resCompL[1],
resCompL[0],
numA[7:4],
numB[7:4],
LT,
EQ,
GT
);
endmodule
| 6.514752 |
module addnSubX #(
parameter adderWidth = 4
) (
output overflowFlag,
output carryOut,
output [adderWidth-1:0] SUM,
input carryIn,
input [adderWidth-1:0] numA,
numB,
input opSelect
); // parameter adderWidth = 4;
// carry ahead logic
//.. ISSUE: carryIn should be removed from portIN.
wire [adderWidth:0] carryAhead;
assign carryAhead[0] = carryIn | opSelect; //for subtraction
assign carryOut = carryAhead[adderWidth];
// adding subtraction feature, Inverting B
wire [adderWidth-1:0] numBx;
genvar j;
generate
for (j = 0; j < adderWidth; j = j + 1) begin : n
assign numBx[j] = opSelect ^ numB[j];
end
endgenerate
// main block
genvar i;
generate
for (i = 0; i < adderWidth; i = i + 1) begin : m
B_1xFullAdder sumEmAll (
numA[i],
numBx[i],
carryAhead[i],
carryAhead[i+1],
SUM[i]
);
end //for
endgenerate
// overflow detection
assign overflowFlag = carryAhead[adderWidth] ^ carryAhead[adderWidth-1];
endmodule
| 7.624249 |
module b_block (
c_out2,
c_out1,
g3,
p3,
g2,
p2,
g1,
p1,
c_in
);
output c_out1, c_out2, g3, p3;
input g2, p2, g1, p1, c_in;
wire w1, w2;
and (p3, p2, p1);
and (w1, p2, g1);
or (g3, g2, w1);
assign c_out1 = c_in;
and (w2, p1, c_in);
or (c_out2, g1, w2);
endmodule
| 8.633743 |
module B_Bus_Mux (
input clk,
input [3:0] sel,
input [27:0] AC,
input [27:0] MAR,
input [27:0] MDR,
input [7:0] PC,
input [27:0] MBRU,
input [27:0] R1,
input [27:0] R2,
input [27:0] R3,
input [27:0] R4,
input [27:0] R5,
input [27:0] R6,
input [27:0] R7,
input [27:0] R8,
input [27:0] R9,
output reg [27:0] Bus_Out
);
always @(sel or MAR or MDR or PC or MBRU or R1 or R2 or R3 or R4 or R5 or R6 or R7 or R8 or R9)
begin
case (sel)
4'b0000: Bus_Out <= AC;
4'b0001: Bus_Out <= MAR;
4'b0010: Bus_Out <= MDR;
4'b0011: Bus_Out <= MBRU;
4'b0100: Bus_Out <= R1;
4'b0101: Bus_Out <= R2;
4'b0110: Bus_Out <= R3;
4'b0111: Bus_Out <= R4;
4'b1000: Bus_Out <= R5;
4'b1001: Bus_Out <= R6;
4'b1010: Bus_Out <= R7;
4'b1011: Bus_Out <= R8;
4'b1100: Bus_Out <= R9;
4'b1101: Bus_Out <= {20'b0, PC};
default: Bus_Out <= 18'b0;
endcase
end
endmodule
| 7.146675 |
module b_cell_1 (
input in_x,
input in_y,
input in_carry,
output out_sum,
output out_generate,
output out_propogate
);
assign out_generate = in_x & in_y;
assign out_propogate = in_x ^ in_y;
assign out_sum = out_propogate ^ in_carry;
endmodule
| 6.932702 |
module counter4x (
output [3:0] countVal4x,
output ANDr,
input ANDl,
CLK,
RESN
);
/*genvar i;
generate
//for(i=1; i<17; i=i+1) begin: m
for(i=1; i<5; i=i+1) begin: m
lab04part01_TFlipAnd (cBout[i], cBout[i-1], SW[1], SW[2]);
end //for
endgenerate*/
wire [3:0] andOut;
lab04part01_TFlipAnd a1 (
andOut[0],
countVal4x[0],
ANDl,
CLK,
RESN
);
lab04part01_TFlipAnd a2 (
andOut[1],
countVal4x[1],
andOut[0],
CLK,
RESN
);
lab04part01_TFlipAnd a3 (
andOut[2],
countVal4x[2],
andOut[1],
CLK,
RESN
);
lab04part01_TFlipAnd a4 (
andOut[3],
countVal4x[3],
andOut[2],
CLK,
RESN
);
assign ANDr = andOut[3];
endmodule
| 7.585489 |
module counter16x (
output [15:0] countVal,
output ANDr,
input ANDl,
CLK,
RESN
);
wire [3:0] carryOn;
counter4x countA (
countVal[3:0],
carryOn[3],
ANDl,
CLK,
RESN
);
counter4x countB (
countVal[7:4],
carryOn[2],
carryOn[3],
CLK,
RESN
);
counter4x countC (
countVal[11:8],
carryOn[1],
carryOn[2],
CLK,
RESN
);
counter4x countD (
countVal[15:12],
carryOn[0],
carryOn[1],
CLK,
RESN
);
assign ANDr = carryOn[0];
endmodule
| 7.072229 |
module counter32x (
output [31:0] countVal,
output ANDr,
input ANDl,
CLK,
RESN
);
wire carryOn;
counter16x count0 (
countVal[15:0],
carryOn,
ANDl,
CLK,
RESN
);
counter16x count1 (
countVal[31:16],
ANDr,
carryOn,
CLK,
RESN
);
endmodule
| 7.510637 |
module counter16x_add (
output reg [15:0] countVal,
input EN,
CLK,
RESN
);
always @(posedge CLK) begin
if (EN) countVal <= countVal + 1;
if (~RESN) countVal <= 16'h0000;
else if (~EN & RESN) countVal <= countVal;
end //always
endmodule
| 6.594678 |
module counterBCD1x(
// output [3:0]countVal1xBCD,
// output incNext1d,
// input incPrev1d, CLK1d, RESN1d
// );
// reg resetF;
// wire [3:0]andOut;
// //resetF is 0 for RESN=0 OR count=1010;
// always@(negedge CLK1d) begin
// /* I have used negative edge for storing reset of the reset flip flop,
// so that counter is able to reset on next positive edge of counter clock.*/
// if(~RESN1d) begin
// resetF <= 1'b0;
// end //if
// else if(countVal1xBCD > 4'd8 && incPrev1d) begin
// resetF <= ~resetF;
// end //elseif
// else begin
// resetF <= 1'b1;
// end //else
// //resetF <= ~(~RESN1d | (countVal1xBCD[3]&~countVal1xBCD[2]&countVal1xBCD[1]&~countVal1xBCD[0]));
// end //always
// lab04part01_TFlipAnd a1(andOut[0], countVal1xBCD[0], incPrev1d, CLK1d, resetF);
// lab04part01_TFlipAnd a2(andOut[1], countVal1xBCD[1], andOut[0], CLK1d, resetF);
// lab04part01_TFlipAnd a3(andOut[2], countVal1xBCD[2], andOut[1], CLK1d, resetF);
// lab04part01_TFlipAnd a4(andOut[3], countVal1xBCD[3], andOut[2], CLK1d, resetF);
// assign incNext1d = ~resetF;
// endmodule
| 7.034661 |
module counterBCD2x(
// output [7:0]countVal2xBCD,
// output incNext2d,
// input incPrev2d, CLK2d, RESN2d
// );
// wire incMiddle;
// counterBCD1x count0(countVal2xBCD[3:0], incMiddle, incPrev2d, CLK2d, RESN2d);
// counterBCD1x count1(countVal2xBCD[7:4], incNext2d, incMiddle, CLK2d, RESN2d);
// endmodule
| 7.172585 |
module counterBCD4x(
// output [15:0]countVal4xBCD,
// output incNext4d,
// input incPrev4d, CLK4d, RESN4d
// );
// wire incMiddle;
// counterBCD2x count01(countVal4xBCD[7:0], incMiddle, incPrev4d, CLK4d, RESN4d);
// counterBCD2x count23(countVal4xBCD[15:8], incNext4d, incMiddle, CLK4d, RESN4d);
// endmodule
| 6.878981 |
module counterBCD1d (
output reg [3:0] countVal1dBCD,
output reg next1d,
input /*prev1d,*/ CLK1d,
RESN1d
);
initial countVal1dBCD = 4'h0;
always @(posedge CLK1d or negedge RESN1d) begin
if (~RESN1d) begin
countVal1dBCD <= 4'h0;
next1d <= 1'b0;
end //if
else if(countVal1dBCD < 4'd9) begin
countVal1dBCD <= countVal1dBCD + 4'h1;
next1d <= 1'b0;
end //elseif
else if(countVal1dBCD >= 4'h9) begin //reset
countVal1dBCD <= 4'h0;
next1d <= 1'b1;
end //elseif
end //always
endmodule
| 7.006916 |
module counterBCD2d (
output [7:0] countVal2dBCD,
output next2d,
input /*prev2d,*/ CLK2d,
CLR2d
, output [1:0] next
);
wire connect2;
counterBCD1d countA (
countVal2dBCD[3:0],
connect2 /*, prev2d*/,
CLK2d,
CLR2d
);
counterBCD1d countB (
countVal2dBCD[7:4],
next2d /*, connect2*/,
connect2,
CLR2d
);
assign next[0] = connect2;
assign next[1] = next2d;
endmodule
| 7.466323 |
module counterBCD4d (
output [15:0] countVal4dBCD,
output next4d,
input prev4d,
CLK4d,
CLR4d
, output [3:0] next
);
wire connect4;
counterBCD2d countA (
countVal4dBCD[7:0],
connect4, /*prev4d,*/
CLK4d,
CLR4d,
next[1:0]
);
counterBCD2d countB (
countVal4dBCD[15:8],
next4d, /*connect4,*/
connect4,
CLR4d,
next[3:2]
);
endmodule
| 7.689586 |
module hexDisplay4digit (
output [ 6:0] d3,
d2,
d1,
d0,
inout [15:0] displayVal
);
hexDecoder7Seg h3 (
d3,
displayVal[15:12]
);
hexDecoder7Seg h2 (
d2,
displayVal[11:8]
);
hexDecoder7Seg h1 (
d1,
displayVal[7:4]
);
hexDecoder7Seg h0 (
d0,
displayVal[3:0]
);
endmodule
| 6.88103 |
module B_DELAY (
CLK,
Xin,
Xin_DEALY
);
//ģӿ
input CLK, Xin;
output Xin_DEALY;
wire signed [15:0] Xin;
wire signed [15:0] Xin_DEALY;
//ģ
//λĴʱ
shift30 S2 (
CLK,
Xin,
Xin_DEALY
);
endmodule
| 6.908582 |
module b_door_lock (
SW,
KEY,
CLOCK_50,
HEX0,
HEX1,
HEX2,
HEX7,
HEX4,
HEX6,
LEDR,
LEDG
);
input [17:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [6:0] HEX0;
output [6:0] HEX1;
output [6:0] HEX2;
output [6:0] HEX7;
output [6:0] HEX4;
output [6:0] HEX6;
output [17:0] LEDR;
output [7:0] LEDG;
door_lock_top TOP (
.i_digit(SW[3:0]),
.i_confirm_getter(~KEY[0]),
.i_confirm_FSM(~KEY[1]),
.i_hard_reset(~KEY[3]),
.i_switch(~KEY[2]),
.i_enable_display(SW[4]),
.i_clk(CLOCK_50),
.o_LED_correct(LEDG[7]),
.o_LED_incorrect(LEDR[0]),
.o_trials_7seg(HEX6),
.o_pass_7seg_0(HEX0),
.o_pass_7seg_1(HEX1),
.o_pass_7seg_2(HEX2),
.o_input_7seg(HEX4),
.o_state_7seg(HEX7)
);
endmodule
| 8.436148 |
module
Instantiation: FSM_4xSequenceDetectorB name(.fOut(), .W(), .pCLK(), .nREST());
-------------------------------------------------------------------------- */
module FSM_4xSequenceDetectorB(
output reg fOut,
//output [3:0]fQ,
input W/*input*/, pCLK, nREST
);
// STATE ASSIGNMENT LIST as parameters
parameter A = 4'b0000;
parameter B = 4'b0001;
parameter C = 4'b0010;
parameter D = 4'b0011;
parameter E = 4'b0100;
parameter F = 4'b0101;
parameter G = 4'b0110;
parameter H = 4'b0111;
parameter I = 4'b1000;
// ----------------------------------
wire [3:0]fQ;
reg [3:0]fD;
always@(*) begin
case({fQ[3:0],W})
5'b00000: fD = B;
5'b00001: fD = F;
5'b00010: fD = C;
5'b00011: fD = F;
5'b00100: fD = D;
5'b00101: fD = F;
5'b00110: fD = E;
5'b00111: fD = F;
5'b01000: fD = E;
5'b01001: fD = F;
5'b01010: fD = B;
5'b01011: fD = G;
5'b01100: fD = B;
5'b01101: fD = H;
5'b01110: fD = B;
5'b01111: fD = I;
5'b10000: fD = B;
5'b10001: fD = I;
default: fD = A;
endcase
end //always
// set aside 4 positive edge triggered low async reset flip flops
registerNx #(4) ffx4(.Q(fQ[3:0]), .D(fD[3:0]), .regCLK(pCLK), .regRESN(nREST));
// output control
always@(*) begin
case(fQ[3:0])
4'd4: fOut = 1'b1;
4'd8: fOut = 1'b1;
default: fOut = 1'b0;
endcase
end
endmodule
| 8.053527 |
module: b_lut
//
// Implements the core logic for the xc.lut instruction.
//
module b_lut (
input wire [31:0] crs1 , // Source register 1 (LUT input)
input wire [31:0] crs2 , // Source register 2 (LUT bottom half)
input wire [31:0] crs3 , // Source register 3 (LUT top half)
output wire [31:0] result //
);
wire [ 3:0] lut_arr [15:0];
wire [63:0] lut_con = {crs1, crs2};
genvar i;
generate for (i = 0; i < 16; i = i + 1) begin
assign lut_arr[i] = lut_con[4*i+3:4*i];
end endgenerate
genvar j;
generate for (j = 0; j < 8; j = j + 1) begin
assign result[4*j+3:4*j] = lut_arr[crs3[4*j+3:4*j]];
end endgenerate
endmodule
| 7.220178 |
module: b_lut_checker
//
// Implements the core logic for the xc.lut instruction for checking
//
module b_lut_checker (
input wire [31:0] crs1 , // Source register 1 (LUT input)
input wire [31:0] crs2 , // Source register 2 (LUT bottom half)
input wire [31:0] crs3 , // Source register 3 (LUT top half)
output wire [31:0] result //
);
wire [ 3:0] lut_arr [15:0];
wire [63:0] lut_con = {crs1, crs2};
genvar i;
generate for (i = 0; i < 16; i = i + 1) begin
assign lut_arr[i] = lut_con[4*i+3:4*i];
end endgenerate
genvar j;
generate for (j = 0; j < 8; j = j + 1) begin
assign result[4*j+3:4*j] = lut_arr[crs3[4*j+3:4*j]];
end endgenerate
endmodule
| 6.604307 |
module B_latchRSe (
input clock,
R,
S,
output Q
);
wire Qa, Qb;
assign Qa = ~((R & clock) | Qb);
assign Qb = ~((S & clock) | Qa);
assign Q = Qa;
endmodule
| 6.531514 |
module mem_DLatch (
output reg Q,
input D,
clk
);
always @(D, clk) begin
if (clk) Q <= D;
end
endmodule
| 6.943764 |
module mem_Dflippos (
output reg Q,
input D,
clk,
resetN
);
always @(posedge clk or negedge resetN) begin
if (~resetN) begin
Q <= 0;
end //if
else begin
Q <= D;
end
end
endmodule
| 7.92443 |
module mem_Dflipneg (
output reg Q,
input D,
clk
);
always @(negedge clk) begin
Q <= D;
end
endmodule
| 7.737337 |
module mem_Tflippos (
output reg Q,
input T,
clk,
reset
);
wire d;
xor (d, Q, T);
always @(posedge clk) begin
if (~reset) Q <= 1'b0;
//else if(T)
// Q <= ~Q;
else
Q <= d;
end
endmodule
| 6.817717 |
module registerNx #(
parameter regWidth = 8
) (
output [regWidth-1 : 0] Q,
input [regWidth-1 : 0] D,
input regCLK,
regRESN
);
//parameter regWidth=8;
genvar i;
generate
for (i = 0; i < regWidth; i = i + 1) begin : m
mem_Dflippos df (
Q[i],
D[i],
regCLK,
regRESN
);
end //for
endgenerate
endmodule
| 9.819495 |
module shiftRegisterNx #(
parameter regWidth = 4
) (
output [(regWidth-1):0] Q,
input D,
input sregCLK,
sregRESN
);
wire [(regWidth):0] shiftAhead;
assign shiftAhead[0] = D;
assign Q[(regWidth-1):0] = shiftAhead[(regWidth):1];
genvar i;
generate
for (i = 0; i < regWidth; i = i + 1) begin : m
mem_Dflippos df (
shiftAhead[i+1],
shiftAhead[i],
sregCLK,
sregRESN
);
end //for
endgenerate
endmodule
| 8.12979 |
module B_1xMUX2to1 (
input S,
X,
Y,
output M
);
assign M = ((~S & X) | (S & Y));
endmodule
| 7.289178 |
module mux2x1 #(
parameter dataW = 8
) (
output reg [(dataW-1):0] M,
input [(dataW-1):0] X,
input [(dataW-1):0] Y,
input Sel
);
always @(*) begin
if (Sel) begin
M = Y;
end else begin
M = X;
end
end
endmodule
| 7.726622 |
module b_out (
i_clk,
i_reset,
i_hsyn,
iv_b11,
iv_b12,
iv_b21,
iv_b22,
iv_fx,
iv_fy,
o_hsyn,
ov_b,
wv_b1r,
wv_b1g,
wv_b1b,
wv_b2r,
wv_b2g,
wv_b2b
);
input i_clk;
input i_reset;
input i_hsyn;
input [15:0] iv_b11, iv_b12, iv_b21, iv_b22;
input [10:0] iv_fx, iv_fy;
output o_hsyn;
output [15:0] ov_b;
output [7:0] wv_b1r, wv_b1g, wv_b1b, wv_b2r, wv_b2g, wv_b2b;
wire [7:0] wv_b11_r = {iv_b11[15:11], iv_b11[13:11]};
wire [7:0] wv_b11_g = {iv_b11[10:5], iv_b11[6:5]};
wire [7:0] wv_b11_b = {iv_b11[4:0], iv_b11[2:0]};
wire [7:0] wv_b12_r = {iv_b12[15:11], iv_b12[13:11]};
wire [7:0] wv_b12_g = {iv_b12[10:5], iv_b12[6:5]};
wire [7:0] wv_b12_b = {iv_b12[4:0], iv_b12[2:0]};
wire [7:0] wv_b21_r = {iv_b21[15:11], iv_b21[13:11]};
wire [7:0] wv_b21_g = {iv_b21[10:5], iv_b21[6:5]};
wire [7:0] wv_b21_b = {iv_b21[4:0], iv_b21[2:0]};
wire [7:0] wv_b22_r = {iv_b22[15:11], iv_b22[13:11]};
wire [7:0] wv_b22_g = {iv_b22[10:5], iv_b22[6:5]};
wire [7:0] wv_b22_b = {iv_b22[4:0], iv_b22[2:0]};
wire [20:0] wv_fx_b1r, wv_fx_b1g, wv_fx_b1b, wv_fx_b2r, wv_fx_b2g, wv_fx_b2b;
fxy_b_mult fx_b1r (
.a ({1'd0, iv_fx}),
.b ({1'd0, wv_b12_r} - {1'd0, wv_b11_r}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fx_b1r)
);
fxy_b_mult fx_b1g (
.a ({1'd0, iv_fx}),
.b ({1'd0, wv_b12_g} - {1'd0, wv_b11_g}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fx_b1g)
);
fxy_b_mult fx_b1b (
.a ({1'd0, iv_fx}),
.b ({1'd0, wv_b12_b} - {1'd0, wv_b11_b}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fx_b1b)
);
fxy_b_mult fx_b2r (
.a ({1'd0, iv_fx}),
.b ({1'd0, wv_b22_r} - {1'd0, wv_b21_r}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fx_b2r)
);
fxy_b_mult fx_b2g (
.a ({1'd0, iv_fx}),
.b ({1'd0, wv_b22_g} - {1'd0, wv_b21_g}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fx_b2g)
);
fxy_b_mult fx_b2b (
.a ({1'd0, iv_fx}),
.b ({1'd0, wv_b22_b} - {1'd0, wv_b21_b}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fx_b2b)
);
wire [7:0] wv_b1r, wv_b1g, wv_b1b, wv_b2r, wv_b2g, wv_b2b;
assign wv_b1r = wv_fx_b1r[10+:8] + wv_b11_r;
assign wv_b1g = wv_fx_b1g[10+:8] + wv_b11_g;
assign wv_b1b = wv_fx_b1b[10+:8] + wv_b11_b;
assign wv_b2r = wv_fx_b2r[10+:8] + wv_b21_r;
assign wv_b2g = wv_fx_b2g[10+:8] + wv_b21_g;
assign wv_b2b = wv_fx_b2b[10+:8] + wv_b21_b;
wire [20:0] wv_fy_br, wv_fy_bg, wv_fy_bb;
fxy_b_mult fy_br (
.a ({1'd0, iv_fy}),
.b ({1'd0, wv_b2r} - {1'd0, wv_b1r}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fy_br)
);
fxy_b_mult fy_bg (
.a ({1'd0, iv_fy}),
.b ({1'd0, wv_b2g} - {1'd0, wv_b1g}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fy_bg)
);
fxy_b_mult fy_bb (
.a ({1'd0, iv_fy}),
.b ({1'd0, wv_b2b} - {1'd0, wv_b1b}),
.clk(i_clk),
.rst(i_reset),
.ce ('b1),
.p (wv_fy_bb)
);
wire [7:0] wv_br = wv_fy_br[10+:8] + wv_b1r;
wire [7:0] wv_bg = wv_fy_bg[10+:8] + wv_b1g;
wire [7:0] wv_bb = wv_fy_bb[10+:8] + wv_b1b;
assign ov_b = {wv_br[7:3], wv_bg[7:2], wv_bb[7:3]};
assign o_hsyn = i_hsyn;
endmodule
| 6.551414 |
module b_predictor (
input clk,
input rst,
input direct_mispredict,
input direct_resolved,
input branch_commit,
input [31:0] pc_head, // the pc of commit branch
input [31:0] pc_branch, // the pc of branch making predict
input [31:0] pc_resolved,
output logic branch_valid,
output logic [31:0] btb_pc_predict,
output logic direct_predict
);
logic [3:0] local_b [63:0];
logic [3:0] local_b_checkpoint[63:0];
logic [1:0] counters [15:0];
integer i;
logic [5:0] pc_head_index, pc_branch_index;
assign pc_head_index = pc_head[7:2];
assign pc_branch_index = pc_branch[7:2];
assign direct_predict = counters[local_b[pc_branch_index]] > 1;
//speculative local history, used for index counter
always @(posedge clk, negedge rst) begin
if (!rst) begin
for (i = 0; i < 64; i = i + 1) begin
local_b[i] <= 4'h0;
end
end else begin
if (direct_mispredict) begin
//update history if mispredict
local_b[pc_head_index] <= (local_b_checkpoint[pc_head_index] << 1) | direct_resolved;
end
if (branch_valid) begin
//insert predicted direction to local branch history
local_b[pc_branch_index] <= (local_b[pc_branch_index] << 1) | (counters[local_b[pc_branch_index]] > 1 ? 4'h1 : 4'h0);
end
end
end // always @ (posedge clk, negedge rst)
// commited local history, used for counter update
always @(posedge clk, negedge rst) begin
if (!rst) begin
for (i = 0; i < 64; i = i + 1) begin
local_b_checkpoint[i] <= 4'h0;
end
end else begin
if (branch_commit) begin
local_b_checkpoint[pc_head_index] <= (local_b_checkpoint[pc_head_index] << 1) | direct_resolved;
end
end
end // always @ (posedge clk, negedge rst)
//saturated counter 0:deep untaken, 1:untaken, 2:taken, 3:deep taken
always @(posedge clk, negedge rst) begin
if (!rst) begin
for (i = 0; i < 16; i = i + 1) begin
counters[i] <= 2'h1;
end
end else begin
if (branch_commit) begin
if (direct_resolved) begin
if (counters[local_b_checkpoint[pc_head_index]] < 4'h3) begin
counters[local_b_checkpoint[pc_head_index]] <= counters[local_b_checkpoint[pc_head_index]] + 1;
end
end else begin
if (counters[local_b_checkpoint[pc_head_index]] > 4'h0) begin
counters[local_b_checkpoint[pc_head_index]] <= counters[local_b_checkpoint[pc_head_index]] - 1;
end
end
end // if (branch_commit)
end // else: !if(!rst)
end // always @ (posedge clk, negedge rst)
typedef struct packed {
bit [23:0] pc_branch_tag;
bit [31:0] btb_pc_predict;
bit bsy;
} btbStruct;
btbStruct btb_array[63:0];
//for simplicity, use pc indexed btb; should use associative one
//fixme: to implement replace policy
always @(posedge clk, negedge rst) begin
if (!rst) begin
for (i = 0; i < $size(btb_array); i = i + 1) begin
btb_array[i] <= {$size(btbStruct) {1'b0}};
end
end else begin
if (branch_commit) begin
btb_array[pc_head_index].bsy <= 1'b1;
btb_array[pc_head_index].pc_branch_tag <= pc_head[31:8];
//only updated target pc when it is actually taken
if (direct_resolved) begin
btb_array[pc_head_index].btb_pc_predict <= pc_resolved;
end
end
end // else: !if(!rst)
end // always @ (posedge clk, negedge rst)
assign branch_valid = btb_array[pc_branch_index].bsy;
assign btb_pc_predict = (btb_array[pc_branch_index].bsy && btb_array[pc_branch_index].pc_branch_tag == pc_branch[31:8]) ? btb_array[pc_branch_index].btb_pc_predict : 32'h0;
endmodule
| 9.767808 |
module b_reg (
input Rst,
input Clk,
input [5:0] b_sel,
input LE_sel,
input [7:0] Selector,
output [7:0] Rx,
output [7:0] Ry
);
reg [7:0] b_regs[7:0];
always @(posedge Clk, posedge Rst) begin
if (Rst) begin
b_regs[0] <= 0;
b_regs[1] <= 0;
b_regs[2] <= 0;
b_regs[3] <= 0;
b_regs[4] <= 0;
b_regs[5] <= 0;
b_regs[6] <= 0;
b_regs[7] <= 0;
end else if (LE_sel) b_regs[b_sel[2:0]] <= Selector;
end
assign Rx = b_regs[b_sel[2:0]];
assign Ry = b_regs[b_sel[5:3]];
endmodule
| 7.672496 |
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