code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module C8T28SOI_LR_CNNOR2AX9_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
not U1 (INTERNAL1, B);
and U2 (Z, A, INTERNAL1);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (A) (B - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR2X19_P0 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (!A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR2X19_P10 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (!A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR2X19_P16 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (!A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR2X19_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (!A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR2X37_P0 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (!A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR2X37_P10 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (!A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR2X37_P16 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (!A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR2X37_P4 (
Z,
A,
B
);
output Z;
input A;
input B;
or U1 (Z, A, B);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B) (A + => Z) = (tDELAY, tDELAY);
if (!A) (B + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X14_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X14_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X14_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X14_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X19_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X19_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X19_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X19_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X27_P0 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X27_P10 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X27_P16 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR3X27_P4 (
Z,
A,
B,
C
);
output Z;
input A;
input B;
input C;
or U1 (Z, A, B, C);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B) (C + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR4X19_P0 (
Z,
A,
B,
C,
D
);
output Z;
input A;
input B;
input C;
input D;
or U1 (Z, A, B, C, D);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C && !D) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C && !D) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B && !D) (C + => Z) = (tDELAY, tDELAY);
if (!A && !B && !C) (D + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR4X19_P10 (
Z,
A,
B,
C,
D
);
output Z;
input A;
input B;
input C;
input D;
or U1 (Z, A, B, C, D);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C && !D) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C && !D) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B && !D) (C + => Z) = (tDELAY, tDELAY);
if (!A && !B && !C) (D + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR4X19_P16 (
Z,
A,
B,
C,
D
);
output Z;
input A;
input B;
input C;
input D;
or U1 (Z, A, B, C, D);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C && !D) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C && !D) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B && !D) (C + => Z) = (tDELAY, tDELAY);
if (!A && !B && !C) (D + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR4X19_P4 (
Z,
A,
B,
C,
D
);
output Z;
input A;
input B;
input C;
input D;
or U1 (Z, A, B, C, D);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C && !D) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C && !D) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B && !D) (C + => Z) = (tDELAY, tDELAY);
if (!A && !B && !C) (D + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR4X27_P0 (
Z,
A,
B,
C,
D
);
output Z;
input A;
input B;
input C;
input D;
or U1 (Z, A, B, C, D);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C && !D) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C && !D) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B && !D) (C + => Z) = (tDELAY, tDELAY);
if (!A && !B && !C) (D + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR4X27_P10 (
Z,
A,
B,
C,
D
);
output Z;
input A;
input B;
input C;
input D;
or U1 (Z, A, B, C, D);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C && !D) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C && !D) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B && !D) (C + => Z) = (tDELAY, tDELAY);
if (!A && !B && !C) (D + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR4X27_P16 (
Z,
A,
B,
C,
D
);
output Z;
input A;
input B;
input C;
input D;
or U1 (Z, A, B, C, D);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C && !D) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C && !D) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B && !D) (C + => Z) = (tDELAY, tDELAY);
if (!A && !B && !C) (D + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNOR4X27_P4 (
Z,
A,
B,
C,
D
);
output Z;
input A;
input B;
input C;
input D;
or U1 (Z, A, B, C, D);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!B && !C && !D) (A + => Z) = (tDELAY, tDELAY);
if (!A && !C && !D) (B + => Z) = (tDELAY, tDELAY);
if (!A && !B && !D) (C + => Z) = (tDELAY, tDELAY);
if (!A && !B && !C) (D + => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X15_P0 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X15_P10 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X15_P16 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X15_P4 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X27_P0 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X27_P10 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X27_P16 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X27_P4 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X9_P0 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X9_P10 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X9_P16 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
module C8T28SOI_LR_CNXOR2X9_P4 (
Z,
A,
S
);
output Z;
input A;
input S;
xor U1 (Z, A, S);
`ifdef functional
`else
specify
specparam tDELAY = 0.0;
if (!S) (A + => Z) = (tDELAY, tDELAY);
if (S) (A - => Z) = (tDELAY, tDELAY);
if (!A) (S + => Z) = (tDELAY, tDELAY);
if (A) (S - => Z) = (tDELAY, tDELAY);
endspecify
`endif
endmodule
| 6.567758 |
modules.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module c2i_buf (/*AUTOARG*/
// Outputs
ucb_buf_acpt, iob_ucb_vld, iob_ucb_data,
// Inputs
rst_l, clk, c2i_packet_vld, ucb_sel, c2i_packet, ucb_iob_stall
);
// synopsys template
parameter REG_WIDTH = 64;
parameter IOB_UCB_WIDTH = 32;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input rst_l;
input clk;
// slow control interface
input c2i_packet_vld;
input ucb_sel;
output ucb_buf_acpt;
// slow datapath interface
input [REG_WIDTH+63:0] c2i_packet;
// UCB interface
output iob_ucb_vld;
output [IOB_UCB_WIDTH-1:0] iob_ucb_data;
input ucb_iob_stall;
// Internal signals
wire dbl_buf_wr;
wire dbl_buf_rd;
wire dbl_buf_vld;
wire dbl_buf_full;
wire outdata_buf_wr;
wire [REG_WIDTH+63:0] outdata_buf_in;
wire [(REG_WIDTH+64)/IOB_UCB_WIDTH-1:0] outdata_vec_in;
wire outdata_buf_busy;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
assign dbl_buf_wr = c2i_packet_vld & ucb_sel & ~dbl_buf_full;
assign ucb_buf_acpt = dbl_buf_wr;
assign dbl_buf_rd = dbl_buf_vld & ~outdata_buf_busy;
assign outdata_buf_wr = dbl_buf_rd;
assign outdata_vec_in = {(REG_WIDTH+64)/IOB_UCB_WIDTH{1'b1}};
dbl_buf #(REG_WIDTH+64) dbl_buf (.rst_l(rst_l),
.clk(clk),
.wr(dbl_buf_wr),
.din(c2i_packet),
.rd(dbl_buf_rd),
.dout(outdata_buf_in),
.vld(dbl_buf_vld),
.full(dbl_buf_full));
ucb_bus_out #(IOB_UCB_WIDTH,REG_WIDTH) ucb_bus_out (.rst_l(rst_l),
.clk(clk),
.outdata_buf_wr(outdata_buf_wr),
.outdata_buf_in(outdata_buf_in),
.outdata_vec_in(outdata_vec_in),
.outdata_buf_busy(outdata_buf_busy),
.vld(iob_ucb_vld),
.data(iob_ucb_data),
.stall(ucb_iob_stall));
endmodule
| 8.426401 |
module ADD21 (
A,
B,
CO,
S
);
output CO, S;
input A, B;
xor (S, B, A);
and (CO, B, A);
`ifdef functional
`else
specify
(A => CO) = (0, 0);
(B => CO) = (0, 0);
(A => S) = (0, 0);
(B => S) = (0, 0);
endspecify
`endif
endmodule
| 6.734772 |
module ADD22 (
A,
B,
CO,
S
);
output CO, S;
input A, B;
xor (S, B, A);
and (CO, B, A);
`ifdef functional
`else
specify
(A => S) = (0, 0);
(B => S) = (0, 0);
(A => CO) = (0, 0);
(B => CO) = (0, 0);
endspecify
`endif
endmodule
| 6.514778 |
module ADD31 (
A,
B,
CI,
CO,
S
);
output CO, S;
input A, B, CI;
U_ADDR2_S(
S, A, B, CI
); U_ADDR2_C(
CO, A, B, CI
);
`ifdef functional
`else
specify
(A => S) = (0, 0);
(B => S) = (0, 0);
(CI => S) = (0, 0);
(A => CO) = (0, 0);
(B => CO) = (0, 0);
(CI => CO) = (0, 0);
endspecify
`endif
endmodule
| 6.539389 |
module ADD32 (
A,
B,
CI,
CO,
S
);
output CO, S;
input A, B, CI;
U_ADDR2_S(
S, A, B, CI
); U_ADDR2_C(
CO, A, B, CI
);
`ifdef functional
`else
specify
(A => S) = (0, 0);
(B => S) = (0, 0);
(CI => S) = (0, 0);
(A => CO) = (0, 0);
(B => CO) = (0, 0);
(CI => CO) = (0, 0);
endspecify
`endif
endmodule
| 6.961664 |
module BUF12 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.86656 |
module BUF15 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.224652 |
module BUF2 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.391175 |
module BUF4 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.778382 |
module BUF6 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.731751 |
module BUF8 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.073897 |
module BUFE10 (
A,
E,
Q
);
output Q;
input A, E;
bufif1 (Q, A, E);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
(E => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.547296 |
module BUFE15 (
A,
E,
Q
);
output Q;
input A, E;
bufif1 (Q, A, E);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
(E => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.634051 |
module BUFE2 (
A,
E,
Q
);
output Q;
input A, E;
bufif1 (Q, A, E);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
(E => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.992282 |
module BUFE4 (
A,
E,
Q
);
output Q;
input A, E;
bufif1 (Q, A, E);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
(E => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.83148 |
module BUFE8 (
A,
E,
Q
);
output Q;
input A, E;
bufif1 (Q, A, E);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
(E => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.708724 |
module BUFT10 (
A,
EN,
Q
);
output Q;
input A, EN;
bufif0 (Q, A, EN);
`ifdef functional
`else
specify
(EN => Q) = (0, 0);
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.962735 |
module BUFT12 (
A,
EN,
Q
);
output Q;
input A, EN;
bufif0 (Q, A, EN);
`ifdef functional
`else
specify
(EN => Q) = (0, 0);
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.501657 |
module BUFT15 (
A,
EN,
Q
);
output Q;
input A, EN;
bufif0 (Q, A, EN);
`ifdef functional
`else
specify
(EN => Q) = (0, 0);
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.815254 |
module BUFT2 (
A,
EN,
Q
);
output Q;
input A, EN;
bufif0 (Q, A, EN);
`ifdef functional
`else
specify
(EN => Q) = (0, 0);
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.178683 |
module BUFT4 (
A,
EN,
Q
);
output Q;
input A, EN;
bufif0 (Q, A, EN);
`ifdef functional
`else
specify
(EN => Q) = (0, 0);
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.688751 |
module BUFT6 (
A,
EN,
Q
);
output Q;
input A, EN;
bufif0 (Q, A, EN);
`ifdef functional
`else
specify
(EN => Q) = (0, 0);
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.782232 |
module BUFT8 (
A,
EN,
Q
);
output Q;
input A, EN;
bufif0 (Q, A, EN);
`ifdef functional
`else
specify
(EN => Q) = (0, 0);
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.780151 |
module CLKBU15 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.825466 |
module CLKBU8 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.531949 |
module DFP1 (
C,
D,
Q,
QN,
SN
);
output Q, QN;
input C, D, SN;
`ifdef functional
U_FD_P_SB_NO(
buf_Q, D, C, SN, 1'b1
);
`else
reg notifier;
U_FD_P_SB_NO(
buf_Q, D, C, SN, notifier
);
`endif
buf (Q, buf_Q);
not (QN, buf_Q);
`ifdef functional
`else
specify
(C => Q) = (1, 1);
(C => QN) = (1, 1);
(SN => Q) = (0, 0);
(SN => QN) = (0, 0);
$setup(posedge D, posedge C, 0, notifier);
$setup(negedge D, posedge C, 0, notifier);
$recovery(posedge SN, posedge C, 0, notifier);
$hold(posedge C, negedge D, 0, notifier);
$hold(posedge C, posedge D, 0, notifier);
$hold(posedge C, posedge SN, 0, notifier);
$width(posedge C, 1, 0, notifier);
$width(negedge C, 1, 0, notifier);
$width(negedge SN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.646077 |
module DL1 (
D,
GN,
Q,
QN
);
output Q, QN;
input D, GN;
`ifdef functional
U_LD_N_NO(
buf_Q, D, GN, 1'b1
);
`else
reg notifier;
U_LD_N_NO(
buf_Q, D, GN, notifier
);
`endif
buf (Q, buf_Q);
not (QN, buf_Q);
`ifdef functional
`else
specify
(D => Q) = (0, 0);
(D => QN) = (0, 0);
(GN => Q) = (1, 1);
(GN => QN) = (1, 1);
$setup(posedge D, posedge GN, 0, notifier);
$setup(negedge D, posedge GN, 0, notifier);
$hold(posedge GN, negedge D, 0, notifier);
$hold(posedge GN, posedge D, 0, notifier);
$width(negedge GN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.868974 |
module DL3 (
D,
GN,
Q,
QN
);
output Q, QN;
input D, GN;
`ifdef functional
U_LD_N_NO(
buf_Q, D, GN, 1'b1
);
`else
reg notifier;
U_LD_N_NO(
buf_Q, D, GN, notifier
);
`endif
buf (Q, buf_Q);
not (QN, buf_Q);
`ifdef functional
`else
specify
(D => Q) = (0, 0);
(D => QN) = (0, 0);
(GN => Q) = (1, 1);
(GN => QN) = (1, 1);
$setup(posedge D, posedge GN, 0, notifier);
$setup(negedge D, posedge GN, 0, notifier);
$hold(posedge GN, negedge D, 0, notifier);
$hold(posedge GN, posedge D, 0, notifier);
$width(negedge GN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.710486 |
module DLP1 (
D,
GN,
Q,
QN,
SN
);
output Q, QN;
input D, GN, SN;
`ifdef functional
U_LD_N_SB_NO(
buf_Q, D, GN, SN, 1'b1
);
`else
reg notifier;
U_LD_N_SB_NO(
buf_Q, D, GN, SN, notifier
);
`endif
buf (Q, buf_Q);
not (QN, buf_Q);
`ifdef functional
`else
specify
(D => Q) = (0, 0);
(D => QN) = (0, 0);
(GN => Q) = (1, 1);
(GN => QN) = (1, 1);
(SN => Q) = (0, 0);
(SN => QN) = (0, 0);
$setup(posedge D, posedge GN, 0, notifier);
$setup(negedge D, posedge GN, 0, notifier);
$recovery(posedge SN, posedge GN, 0, notifier);
$hold(posedge GN, negedge D, 0, notifier);
$hold(posedge GN, posedge D, 0, notifier);
$hold(posedge GN, posedge SN, 0, notifier);
$width(negedge GN, 1, 0, notifier);
$width(negedge SN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.767958 |
module DLP3 (
D,
GN,
Q,
QN,
SN
);
output Q, QN;
input D, GN, SN;
`ifdef functional
U_LD_N_SB_NO(
buf_Q, D, GN, SN, 1'b1
);
`else
reg notifier;
U_LD_N_SB_NO(
buf_Q, D, GN, SN, notifier
);
`endif
buf (Q, buf_Q);
not (QN, buf_Q);
`ifdef functional
`else
specify
(D => Q) = (0, 0);
(D => QN) = (0, 0);
(GN => Q) = (1, 1);
(GN => QN) = (1, 1);
(SN => Q) = (0, 0);
(SN => QN) = (0, 0);
$setup(posedge D, posedge GN, 0, notifier);
$setup(negedge D, posedge GN, 0, notifier);
$recovery(posedge SN, posedge GN, 0, notifier);
$hold(posedge GN, negedge D, 0, notifier);
$hold(posedge GN, posedge D, 0, notifier);
$hold(posedge GN, posedge SN, 0, notifier);
$width(negedge GN, 1, 0, notifier);
$width(negedge SN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.717927 |
module DLQ1 (
D,
GN,
Q
);
output Q;
input D, GN;
`ifdef functional
U_LD_N_NO(
Q, D, GN, 1'b1
);
`else
reg notifier;
U_LD_N_NO(
Q, D, GN, notifier
);
`endif
`ifdef functional
`else
specify
(D => Q) = (0, 0);
(GN => Q) = (1, 1);
$setup(posedge D, posedge GN, 0, notifier);
$setup(negedge D, posedge GN, 0, notifier);
$hold(posedge GN, negedge D, 0, notifier);
$hold(posedge GN, posedge D, 0, notifier);
$width(negedge GN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.577058 |
module DLY12 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (1, 1);
endspecify
`endif
endmodule
| 7.028535 |
module DLY22 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (1, 1);
endspecify
`endif
endmodule
| 7.525911 |
module DLY32 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (1, 1);
endspecify
`endif
endmodule
| 7.708153 |
module DLY42 (
A,
Q
);
output Q;
input A;
buf (Q, A);
`ifdef functional
`else
specify
(A => Q) = (1, 1);
endspecify
`endif
endmodule
| 7.357104 |
module IMUX20 (
A,
B,
Q,
S
);
output Q;
input A, B, S;
U_MUX_2_1_INV(
Q, A, B, S
);
`ifdef functional
`else
specify
(S => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
endspecify
`endif
endmodule
| 8.151799 |
module IMUX21 (
A,
B,
Q,
S
);
output Q;
input A, B, S;
U_MUX_2_1_INV(
Q, A, B, S
);
`ifdef functional
`else
specify
(S => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
endspecify
`endif
endmodule
| 8.076151 |
module IMUX22 (
A,
B,
Q,
S
);
output Q;
input A, B, S;
U_MUX_2_1_INV(
Q, A, B, S
);
`ifdef functional
`else
specify
(S => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.3113 |
module IMUX23 (
A,
B,
Q,
S
);
output Q;
input A, B, S;
U_MUX_2_1_INV(
Q, A, B, S
);
`ifdef functional
`else
specify
(S => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.004826 |
module IMUX24 (
A,
B,
Q,
S
);
output Q;
input A, B, S;
U_MUX_2_1_INV(
Q, A, B, S
);
`ifdef functional
`else
specify
(S => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.442989 |
module IMUX31 (
A,
B,
C,
Q,
S0,
S1
);
output Q;
input A, B, C, S0, S1;
U_MUX_3_2_INV(
Q, A, B, C, S0, S1
);
`ifdef functional
`else
specify
(S0 => Q) = (0, 0);
(S1 => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
(C => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.502804 |
module IMUX32 (
A,
B,
C,
Q,
S0,
S1
);
output Q;
input A, B, C, S0, S1;
U_MUX_3_2_INV(
Q, A, B, C, S0, S1
);
`ifdef functional
`else
specify
(S0 => Q) = (0, 0);
(S1 => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
(C => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.54486 |
module IMUX40 (
A,
B,
C,
D,
Q,
S0,
S1
);
output Q;
input A, B, C, D, S0, S1;
U_MUX_4_2_INV(
Q, A, B, C, D, S0, S1
);
`ifdef functional
`else
specify
(S0 => Q) = (0, 0);
(S1 => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
(C => Q) = (0, 0);
(D => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.955351 |
module IMUX41 (
A,
B,
C,
D,
Q,
S0,
S1
);
output Q;
input A, B, C, D, S0, S1;
U_MUX_4_2_INV(
Q, A, B, C, D, S0, S1
);
`ifdef functional
`else
specify
(S0 => Q) = (0, 0);
(S1 => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
(C => Q) = (0, 0);
(D => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.751607 |
module IMUX42 (
A,
B,
C,
D,
Q,
S0,
S1
);
output Q;
input A, B, C, D, S0, S1;
U_MUX_4_2_INV(
Q, A, B, C, D, S0, S1
);
`ifdef functional
`else
specify
(S0 => Q) = (0, 0);
(S1 => Q) = (0, 0);
(A => Q) = (0, 0);
(B => Q) = (0, 0);
(C => Q) = (0, 0);
(D => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.745827 |
module INV0 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.913862 |
module INV1 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.038062 |
module INV10 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.350629 |
module INV12 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.145988 |
module INV15 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.591504 |
module INV2 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.462846 |
module INV3 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.582219 |
module INV4 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.119576 |
module INV6 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.906552 |
module INV8 (
A,
Q
);
output Q;
input A;
not (Q, A);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
endspecify
`endif
endmodule
| 7.333446 |
module JKC1 (
C,
J,
K,
Q,
QN,
RN
);
output Q, QN;
input C, J, K, RN;
`ifdef functional
U_FJK_P_RB_NO(
buf_Q, J, K, C, RN, 1'b1
);
`else
reg notifier;
U_FJK_P_RB_NO(
buf_Q, J, K, C, RN, notifier
);
`endif
buf (Q, buf_Q);
not (QN, buf_Q);
`ifdef functional
`else
specify
(C => Q) = (1, 1);
(C => QN) = (1, 1);
(RN => Q) = (0, 0);
(RN => QN) = (0, 0);
$setup(posedge J, posedge C, 0, notifier);
$setup(negedge J, posedge C, 0, notifier);
$setup(posedge K, posedge C, 0, notifier);
$setup(negedge K, posedge C, 0, notifier);
$recovery(posedge RN, posedge C, 0, notifier);
$hold(posedge C, negedge J, 0, notifier);
$hold(posedge C, posedge J, 0, notifier);
$hold(posedge C, negedge K, 0, notifier);
$hold(posedge C, posedge K, 0, notifier);
$hold(posedge C, posedge RN, 0, notifier);
$width(posedge C, 1, 0, notifier);
$width(negedge C, 1, 0, notifier);
$width(negedge RN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.578302 |
module JKP1 (
C,
J,
K,
Q,
QN,
SN
);
output Q, QN;
input C, J, K, SN;
`ifdef functional
U_FJK_P_SB_NO(
buf_Q, J, K, C, SN, 1'b1
);
`else
reg notifier;
U_FJK_P_SB_NO(
buf_Q, J, K, C, SN, notifier
);
`endif
buf (Q, buf_Q);
not (QN, buf_Q);
`ifdef functional
`else
specify
(C => Q) = (1, 1);
(C => QN) = (1, 1);
(SN => Q) = (0, 0);
(SN => QN) = (0, 0);
$setup(posedge J, posedge C, 0, notifier);
$setup(negedge J, posedge C, 0, notifier);
$setup(posedge K, posedge C, 0, notifier);
$setup(negedge K, posedge C, 0, notifier);
$recovery(posedge SN, posedge C, 0, notifier);
$hold(posedge C, negedge J, 0, notifier);
$hold(posedge C, posedge J, 0, notifier);
$hold(posedge C, negedge K, 0, notifier);
$hold(posedge C, posedge K, 0, notifier);
$hold(posedge C, posedge SN, 0, notifier);
$width(posedge C, 1, 0, notifier);
$width(negedge C, 1, 0, notifier);
$width(negedge SN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.598225 |
module JKP3 (
C,
J,
K,
Q,
QN,
SN
);
output Q, QN;
input C, J, K, SN;
`ifdef functional
U_FJK_P_SB_NO(
buf_Q, J, K, C, SN, 1'b1
);
`else
reg notifier;
U_FJK_P_SB_NO(
buf_Q, J, K, C, SN, notifier
);
`endif
buf (Q, buf_Q);
not (QN, buf_Q);
`ifdef functional
`else
specify
(C => Q) = (1, 1);
(C => QN) = (1, 1);
(SN => Q) = (0, 0);
(SN => QN) = (0, 0);
$setup(posedge J, posedge C, 0, notifier);
$setup(negedge J, posedge C, 0, notifier);
$setup(posedge K, posedge C, 0, notifier);
$setup(negedge K, posedge C, 0, notifier);
$recovery(posedge SN, posedge C, 0, notifier);
$hold(posedge C, negedge J, 0, notifier);
$hold(posedge C, posedge J, 0, notifier);
$hold(posedge C, negedge K, 0, notifier);
$hold(posedge C, posedge K, 0, notifier);
$hold(posedge C, posedge SN, 0, notifier);
$width(posedge C, 1, 0, notifier);
$width(negedge C, 1, 0, notifier);
$width(negedge SN, 1, 0, notifier);
endspecify
`endif
endmodule
| 6.503375 |
module MAJ31 (
A,
B,
C,
Q
);
output Q;
input A, B, C;
and (g_1_out, B, A);
and (g_2_out, C, B);
and (g_3_out, C, A);
or (Q, g_1_out, g_2_out, g_3_out);
`ifdef functional
`else
specify
(A => Q) = (0, 0);
(B => Q) = (0, 0);
(C => Q) = (0, 0);
endspecify
`endif
endmodule
| 6.764931 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.