code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tileSelect (
clk,
resetn,
enable,
pause,
location_out
);
input clk, resetn, enable, pause;
output reg [3:0] location_out;
reg [4:0] current_state, next_state;
wire rate_out;
rateDivider r0 (
clk,
resetn,
rate_out
);
localparam TILE_0 = 4'd0,
TILE_1 = 4'd1,
TILE_2 = 4'd2,
TILE_3 = 4'd3,
TILE_4 = 4'd4,
TILE_5 = 4'd5,
TILE_6 = 4'd6,
TILE_7 = 4'd7,
TILE_8 = 4'd8;
always @(*) begin : state_table
case (current_state)
TILE_0: next_state = rate_out ? TILE_1 : TILE_0;
TILE_1: next_state = rate_out ? TILE_2 : TILE_1;
TILE_2: next_state = rate_out ? TILE_3 : TILE_2;
TILE_3: next_state = rate_out ? TILE_4 : TILE_3;
TILE_4: next_state = rate_out ? TILE_5 : TILE_4;
TILE_5: next_state = rate_out ? TILE_6 : TILE_5;
TILE_6: next_state = rate_out ? TILE_7 : TILE_6;
TILE_7: next_state = rate_out ? TILE_8 : TILE_7;
TILE_8: next_state = rate_out ? TILE_0 : TILE_8;
default: next_state = TILE_0;
endcase
end
always @(*) begin : enable_signals
location_out = 4'd0;
case (current_state)
TILE_0: location_out = 4'd0;
TILE_1: location_out = 4'd1;
TILE_2: location_out = 4'd2;
TILE_3: location_out = 4'd3;
TILE_4: location_out = 4'd4;
TILE_5: location_out = 4'd5;
TILE_6: location_out = 4'd6;
TILE_7: location_out = 4'd7;
TILE_8: location_out = 4'd8;
default: location_out = 4'd0;
endcase
end
always @(posedge clk) begin : state_FFs
if (!resetn) current_state <= TILE_0;
else if (pause) current_state <= current_state;
else current_state <= next_state;
end
endmodule
| 7.330474 |
module rateDivider (
clock_in,
resetn,
clock_out
);
input clock_in, resetn;
output clock_out;
reg [6:0] count;
always @(posedge clock_in) begin
if (resetn == 1'b0) count <= 0;
else if (count == 0) count <= 7'd100;
else count <= count - 1'b1;
end
assign clock_out = ~|count[7:0];
endmodule
| 7.564049 |
module test_tilerender_top (
input wire [0 : 0] clk,
input wire [0 : 0] reset,
output wire [0 : 0] hsync,
output wire [0 : 0] vsync,
output wire [2 : 0] rgb
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
wire [ 0 : 0] display_on;
wire [15 : 0] hpos;
wire [15 : 0] vpos;
wire [15 : 0] ram_addr;
wire [15 : 0] ram_read;
wire [15 : 0] ram_write; // not connected ?
wire [ 0 : 0] ram_writeenable; // not connected ?
wire [10 : 0] rom_addr;
wire [ 7 : 0] rom_data;
wire [ 0 : 0] ram_busy;
/*******************************************************
* MODULE INSTANCES *
*******************************************************/
// creating one hvsync_generator
hvsync_generator hvsync_gen (
.clk (clk),
.reset (reset),
.hsync (hsync),
.vsync (vsync),
.display_on(display_on),
.hpos (hpos),
.vpos (vpos)
);
// creating one ram
RAM_sync ram (
.clk (clk),
.dout(ram_read),
.din (ram_write),
.addr(ram_addr),
.we (ram_writeenable)
);
// creating one tile_renderer
tile_renderer tile_gen (
.clk (clk),
.reset (reset),
.hpos (hpos),
.vpos (vpos),
.ram_addr(ram_addr),
.ram_read(ram_read),
.ram_busy(ram_busy),
.rom_addr(rom_addr),
.rom_data(rom_data),
.rgb (rgb)
);
// creating one tile_rom
font_cp437_8x8 tile_rom (
.addr(rom_addr),
.data(rom_data)
);
endmodule
| 7.649092 |
module Crossbar__98fa4340c7cb5a19 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:4],
input CGRAData_32_1 recv_data__msg[0:4],
output logic [0:0] recv_data__rdy[0:4],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_5_6 recv_opt__msg,
output logic [0:0] recv_opt__rdy,
output logic [0:0] send_data__en[0:5],
output CGRAData_32_1 send_data__msg[0:5],
input logic [0:0] send_data__rdy[0:5]
);
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_outports_at_update_signal = 32'd6;
logic [0:0] __tmpvar__update_signal_out_rdy;
logic [2:0] __tmpvar__update_signal_in_dir;
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/noc/Crossbar.py:32
// @update
// def update_signal():
// out_rdy = b1( 0 )
// if s.recv_opt.msg.ctrl != OPT_START:
// for i in range( num_outports ):
// in_dir = s.recv_opt.msg.outport[i]
// out_rdy = out_rdy | s.send_data[i].rdy
// if in_dir > OutType( 0 ):
// in_dir = in_dir - OutType( 1 )
// s.recv_data[in_dir].rdy = s.send_data[i].rdy
// s.send_data[i].en = s.recv_data[in_dir].en
// s.send_data[i].msg = s.recv_data[in_dir].msg
// else:
// for i in range( num_outports ):
// s.send_data[i].en = b1( 0 )
// s.recv_opt.rdy = out_rdy
always_comb begin : update_signal
__tmpvar__update_signal_out_rdy = 1'd0;
if (recv_opt__msg.ctrl != __const__OPT_START) begin
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) begin
__tmpvar__update_signal_in_dir = recv_opt__msg.outport[i];
__tmpvar__update_signal_out_rdy = __tmpvar__update_signal_out_rdy | send_data__rdy[i];
if (__tmpvar__update_signal_in_dir > 3'd0) begin
__tmpvar__update_signal_in_dir = __tmpvar__update_signal_in_dir - 3'd1;
recv_data__rdy[__tmpvar__update_signal_in_dir] = send_data__rdy[i];
send_data__en[i] = recv_data__en[__tmpvar__update_signal_in_dir];
send_data__msg[i] = recv_data__msg[__tmpvar__update_signal_in_dir];
end
end
end else
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) send_data__en[i] = 1'd0;
recv_opt__rdy = __tmpvar__update_signal_out_rdy;
end
endmodule
| 8.331541 |
module CtrlMem__CtrlType_CGRAConfig_5_5_6__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_5_6 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_waddr__rdy,
output logic [0:0] send_ctrl__en,
output CGRAConfig_5_5_6 send_ctrl__msg,
input logic [0:0] send_ctrl__rdy
);
localparam logic [31:0] __const__num_ctrl_at_update_signal = 32'd3;
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_ctrl_at_update_raddr = 32'd3;
localparam logic [1:0] __const__last_item_at_update_raddr = 2'd2;
logic [1:0] times;
//-------------------------------------------------------------
// Component reg_file
//-------------------------------------------------------------
logic [0:0] reg_file__clk;
logic [1:0] reg_file__raddr[0:0];
CGRAConfig_5_5_6 reg_file__rdata[0:0];
logic [0:0] reg_file__reset;
logic [1:0] reg_file__waddr[0:0];
CGRAConfig_5_5_6 reg_file__wdata[0:0];
logic [0:0] reg_file__wen[0:0];
RegisterFile__b7926dbb0b6f094e reg_file (
.clk (reg_file__clk),
.raddr(reg_file__raddr),
.rdata(reg_file__rdata),
.reset(reg_file__reset),
.waddr(reg_file__waddr),
.wdata(reg_file__wdata),
.wen (reg_file__wen)
);
//-------------------------------------------------------------
// End of component reg_file
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:45
// @update
// def update_signal():
// if s.times == TimeType( num_ctrl ) or s.reg_file.rdata[0].ctrl == OPT_START:
// s.send_ctrl.en = b1( 0 )
// else:
// s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
// s.recv_waddr.rdy = b1( 1 )
// s.recv_ctrl.rdy = b1( 1 )
always_comb begin : update_signal
if ((times == 2'd3) || (reg_file__rdata[0].ctrl == __const__OPT_START)) begin
send_ctrl__en = 1'd0;
end else send_ctrl__en = send_ctrl__rdy;
recv_waddr__rdy = 1'd1;
recv_ctrl__rdy = 1'd1;
end
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:54
// @update_ff
// def update_raddr():
// if s.reg_file.rdata[0].ctrl != OPT_START:
// if s.times < TimeType( num_ctrl ):
// s.times <<= s.times + TimeType( 1 )
// if s.reg_file.raddr[0] < last_item:
// s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
// else:
// s.reg_file.raddr[0] <<= AddrType( 0 )
always_ff @(posedge clk) begin : update_raddr
if (reg_file__rdata[0].ctrl != __const__OPT_START) begin
if (times < 2'd3) begin
times <= times + 2'd1;
end
if (reg_file__raddr[0] < __const__last_item_at_update_raddr) begin
reg_file__raddr[0] <= reg_file__raddr[0] + 2'd1;
end else reg_file__raddr[0] <= 2'd0;
end
end
assign reg_file__clk = clk;
assign reg_file__reset = reset;
assign send_ctrl__msg = reg_file__rdata[0];
assign reg_file__waddr[0] = recv_waddr__msg;
assign reg_file__wdata[0] = recv_ctrl__msg;
assign reg_file__wen[0] = recv_waddr__en;
endmodule
| 6.639327 |
module Crossbar__85a8b278d9b91463 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_6 recv_opt__msg,
output logic [0:0] recv_opt__rdy,
output logic [0:0] send_data__en[0:5],
output CGRAData_32_1 send_data__msg[0:5],
input logic [0:0] send_data__rdy[0:5]
);
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_outports_at_update_signal = 32'd6;
logic [0:0] __tmpvar__update_signal_out_rdy;
logic [2:0] __tmpvar__update_signal_in_dir;
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/noc/Crossbar.py:32
// @update
// def update_signal():
// out_rdy = b1( 0 )
// if s.recv_opt.msg.ctrl != OPT_START:
// for i in range( num_outports ):
// in_dir = s.recv_opt.msg.outport[i]
// out_rdy = out_rdy | s.send_data[i].rdy
// if in_dir > OutType( 0 ):
// in_dir = in_dir - OutType( 1 )
// s.recv_data[in_dir].rdy = s.send_data[i].rdy
// s.send_data[i].en = s.recv_data[in_dir].en
// s.send_data[i].msg = s.recv_data[in_dir].msg
// else:
// for i in range( num_outports ):
// s.send_data[i].en = b1( 0 )
// s.recv_opt.rdy = out_rdy
always_comb begin : update_signal
__tmpvar__update_signal_out_rdy = 1'd0;
if (recv_opt__msg.ctrl != __const__OPT_START) begin
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) begin
__tmpvar__update_signal_in_dir = recv_opt__msg.outport[i];
__tmpvar__update_signal_out_rdy = __tmpvar__update_signal_out_rdy | send_data__rdy[i];
if (__tmpvar__update_signal_in_dir > 3'd0) begin
__tmpvar__update_signal_in_dir = __tmpvar__update_signal_in_dir - 3'd1;
recv_data__rdy[__tmpvar__update_signal_in_dir] = send_data__rdy[i];
send_data__en[i] = recv_data__en[__tmpvar__update_signal_in_dir];
send_data__msg[i] = recv_data__msg[__tmpvar__update_signal_in_dir];
end
end
end else
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) send_data__en[i] = 1'd0;
recv_opt__rdy = __tmpvar__update_signal_out_rdy;
end
endmodule
| 8.268085 |
module CtrlMem__CtrlType_CGRAConfig_5_6_6__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_6 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_waddr__rdy,
output logic [0:0] send_ctrl__en,
output CGRAConfig_5_6_6 send_ctrl__msg,
input logic [0:0] send_ctrl__rdy
);
localparam logic [31:0] __const__num_ctrl_at_update_signal = 32'd3;
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_ctrl_at_update_raddr = 32'd3;
localparam logic [1:0] __const__last_item_at_update_raddr = 2'd2;
logic [1:0] times;
//-------------------------------------------------------------
// Component reg_file
//-------------------------------------------------------------
logic [0:0] reg_file__clk;
logic [1:0] reg_file__raddr[0:0];
CGRAConfig_5_6_6 reg_file__rdata[0:0];
logic [0:0] reg_file__reset;
logic [1:0] reg_file__waddr[0:0];
CGRAConfig_5_6_6 reg_file__wdata[0:0];
logic [0:0] reg_file__wen[0:0];
RegisterFile__c03acdb717cf6fb7 reg_file (
.clk (reg_file__clk),
.raddr(reg_file__raddr),
.rdata(reg_file__rdata),
.reset(reg_file__reset),
.waddr(reg_file__waddr),
.wdata(reg_file__wdata),
.wen (reg_file__wen)
);
//-------------------------------------------------------------
// End of component reg_file
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:45
// @update
// def update_signal():
// if s.times == TimeType( num_ctrl ) or s.reg_file.rdata[0].ctrl == OPT_START:
// s.send_ctrl.en = b1( 0 )
// else:
// s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
// s.recv_waddr.rdy = b1( 1 )
// s.recv_ctrl.rdy = b1( 1 )
always_comb begin : update_signal
if ((times == 2'd3) || (reg_file__rdata[0].ctrl == __const__OPT_START)) begin
send_ctrl__en = 1'd0;
end else send_ctrl__en = send_ctrl__rdy;
recv_waddr__rdy = 1'd1;
recv_ctrl__rdy = 1'd1;
end
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:54
// @update_ff
// def update_raddr():
// if s.reg_file.rdata[0].ctrl != OPT_START:
// if s.times < TimeType( num_ctrl ):
// s.times <<= s.times + TimeType( 1 )
// if s.reg_file.raddr[0] < last_item:
// s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
// else:
// s.reg_file.raddr[0] <<= AddrType( 0 )
always_ff @(posedge clk) begin : update_raddr
if (reg_file__rdata[0].ctrl != __const__OPT_START) begin
if (times < 2'd3) begin
times <= times + 2'd1;
end
if (reg_file__raddr[0] < __const__last_item_at_update_raddr) begin
reg_file__raddr[0] <= reg_file__raddr[0] + 2'd1;
end else reg_file__raddr[0] <= 2'd0;
end
end
assign reg_file__clk = clk;
assign reg_file__reset = reset;
assign send_ctrl__msg = reg_file__rdata[0];
assign reg_file__waddr[0] = recv_waddr__msg;
assign reg_file__wdata[0] = recv_ctrl__msg;
assign reg_file__wen[0] = recv_waddr__en;
endmodule
| 6.639327 |
module Crossbar__85a8b278d9b91463 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_6 recv_opt__msg,
output logic [0:0] recv_opt__rdy,
output logic [0:0] send_data__en[0:5],
output CGRAData_32_1 send_data__msg[0:5],
input logic [0:0] send_data__rdy[0:5]
);
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_outports_at_update_signal = 32'd6;
logic [0:0] __tmpvar__update_signal_out_rdy;
logic [2:0] __tmpvar__update_signal_in_dir;
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/noc/Crossbar.py:32
// @update
// def update_signal():
// out_rdy = b1( 0 )
// if s.recv_opt.msg.ctrl != OPT_START:
// for i in range( num_outports ):
// in_dir = s.recv_opt.msg.outport[i]
// out_rdy = out_rdy | s.send_data[i].rdy
// if in_dir > OutType( 0 ):
// in_dir = in_dir - OutType( 1 )
// s.recv_data[in_dir].rdy = s.send_data[i].rdy
// s.send_data[i].en = s.recv_data[in_dir].en
// s.send_data[i].msg = s.recv_data[in_dir].msg
// else:
// for i in range( num_outports ):
// s.send_data[i].en = b1( 0 )
// s.recv_opt.rdy = out_rdy
always_comb begin : update_signal
__tmpvar__update_signal_out_rdy = 1'd0;
if (recv_opt__msg.ctrl != __const__OPT_START) begin
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) begin
__tmpvar__update_signal_in_dir = recv_opt__msg.outport[i];
__tmpvar__update_signal_out_rdy = __tmpvar__update_signal_out_rdy | send_data__rdy[i];
if (__tmpvar__update_signal_in_dir > 3'd0) begin
__tmpvar__update_signal_in_dir = __tmpvar__update_signal_in_dir - 3'd1;
recv_data__rdy[__tmpvar__update_signal_in_dir] = send_data__rdy[i];
send_data__en[i] = recv_data__en[__tmpvar__update_signal_in_dir];
send_data__msg[i] = recv_data__msg[__tmpvar__update_signal_in_dir];
end
end
end else
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) send_data__en[i] = 1'd0;
recv_opt__rdy = __tmpvar__update_signal_out_rdy;
end
endmodule
| 8.268085 |
module CtrlMem__CtrlType_CGRAConfig_5_6_6__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_6 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_waddr__rdy,
output logic [0:0] send_ctrl__en,
output CGRAConfig_5_6_6 send_ctrl__msg,
input logic [0:0] send_ctrl__rdy
);
localparam logic [31:0] __const__num_ctrl_at_update_signal = 32'd3;
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_ctrl_at_update_raddr = 32'd3;
localparam logic [1:0] __const__last_item_at_update_raddr = 2'd2;
logic [1:0] times;
//-------------------------------------------------------------
// Component reg_file
//-------------------------------------------------------------
logic [0:0] reg_file__clk;
logic [1:0] reg_file__raddr[0:0];
CGRAConfig_5_6_6 reg_file__rdata[0:0];
logic [0:0] reg_file__reset;
logic [1:0] reg_file__waddr[0:0];
CGRAConfig_5_6_6 reg_file__wdata[0:0];
logic [0:0] reg_file__wen[0:0];
RegisterFile__c03acdb717cf6fb7 reg_file (
.clk (reg_file__clk),
.raddr(reg_file__raddr),
.rdata(reg_file__rdata),
.reset(reg_file__reset),
.waddr(reg_file__waddr),
.wdata(reg_file__wdata),
.wen (reg_file__wen)
);
//-------------------------------------------------------------
// End of component reg_file
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:45
// @update
// def update_signal():
// if s.times == TimeType( num_ctrl ) or s.reg_file.rdata[0].ctrl == OPT_START:
// s.send_ctrl.en = b1( 0 )
// else:
// s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
// s.recv_waddr.rdy = b1( 1 )
// s.recv_ctrl.rdy = b1( 1 )
always_comb begin : update_signal
if ((times == 2'd3) || (reg_file__rdata[0].ctrl == __const__OPT_START)) begin
send_ctrl__en = 1'd0;
end else send_ctrl__en = send_ctrl__rdy;
recv_waddr__rdy = 1'd1;
recv_ctrl__rdy = 1'd1;
end
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:54
// @update_ff
// def update_raddr():
// if s.reg_file.rdata[0].ctrl != OPT_START:
// if s.times < TimeType( num_ctrl ):
// s.times <<= s.times + TimeType( 1 )
// if s.reg_file.raddr[0] < last_item:
// s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
// else:
// s.reg_file.raddr[0] <<= AddrType( 0 )
always_ff @(posedge clk) begin : update_raddr
if (reg_file__rdata[0].ctrl != __const__OPT_START) begin
if (times < 2'd3) begin
times <= times + 2'd1;
end
if (reg_file__raddr[0] < __const__last_item_at_update_raddr) begin
reg_file__raddr[0] <= reg_file__raddr[0] + 2'd1;
end else reg_file__raddr[0] <= 2'd0;
end
end
assign reg_file__clk = clk;
assign reg_file__reset = reset;
assign send_ctrl__msg = reg_file__rdata[0];
assign reg_file__waddr[0] = recv_waddr__msg;
assign reg_file__wdata[0] = recv_ctrl__msg;
assign reg_file__wen[0] = recv_waddr__en;
endmodule
| 6.639327 |
module Crossbar__9de0b627a60fd452 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_8 recv_opt__msg,
output logic [0:0] recv_opt__rdy,
output logic [0:0] send_data__en[0:7],
output CGRAData_32_1 send_data__msg[0:7],
input logic [0:0] send_data__rdy[0:7]
);
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_outports_at_update_signal = 32'd8;
logic [0:0] __tmpvar__update_signal_out_rdy;
logic [2:0] __tmpvar__update_signal_in_dir;
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/noc/Crossbar.py:32
// @update
// def update_signal():
// out_rdy = b1( 0 )
// if s.recv_opt.msg.ctrl != OPT_START:
// for i in range( num_outports ):
// in_dir = s.recv_opt.msg.outport[i]
// out_rdy = out_rdy | s.send_data[i].rdy
// if in_dir > OutType( 0 ):
// in_dir = in_dir - OutType( 1 )
// s.recv_data[in_dir].rdy = s.send_data[i].rdy
// s.send_data[i].en = s.recv_data[in_dir].en
// s.send_data[i].msg = s.recv_data[in_dir].msg
// else:
// for i in range( num_outports ):
// s.send_data[i].en = b1( 0 )
// s.recv_opt.rdy = out_rdy
always_comb begin : update_signal
__tmpvar__update_signal_out_rdy = 1'd0;
if (recv_opt__msg.ctrl != __const__OPT_START) begin
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) begin
__tmpvar__update_signal_in_dir = recv_opt__msg.outport[i];
__tmpvar__update_signal_out_rdy = __tmpvar__update_signal_out_rdy | send_data__rdy[i];
if (__tmpvar__update_signal_in_dir > 3'd0) begin
__tmpvar__update_signal_in_dir = __tmpvar__update_signal_in_dir - 3'd1;
recv_data__rdy[__tmpvar__update_signal_in_dir] = send_data__rdy[i];
send_data__en[i] = recv_data__en[__tmpvar__update_signal_in_dir];
send_data__msg[i] = recv_data__msg[__tmpvar__update_signal_in_dir];
end
end
end else
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) send_data__en[i] = 1'd0;
recv_opt__rdy = __tmpvar__update_signal_out_rdy;
end
endmodule
| 8.434496 |
module CtrlMem__CtrlType_CGRAConfig_5_6_8__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_waddr__rdy,
output logic [0:0] send_ctrl__en,
output CGRAConfig_5_6_8 send_ctrl__msg,
input logic [0:0] send_ctrl__rdy
);
localparam logic [31:0] __const__num_ctrl_at_update_signal = 32'd3;
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_ctrl_at_update_raddr = 32'd3;
localparam logic [1:0] __const__last_item_at_update_raddr = 2'd2;
logic [1:0] times;
//-------------------------------------------------------------
// Component reg_file
//-------------------------------------------------------------
logic [0:0] reg_file__clk;
logic [1:0] reg_file__raddr[0:0];
CGRAConfig_5_6_8 reg_file__rdata[0:0];
logic [0:0] reg_file__reset;
logic [1:0] reg_file__waddr[0:0];
CGRAConfig_5_6_8 reg_file__wdata[0:0];
logic [0:0] reg_file__wen[0:0];
RegisterFile__d0a98e0d377198ba reg_file (
.clk (reg_file__clk),
.raddr(reg_file__raddr),
.rdata(reg_file__rdata),
.reset(reg_file__reset),
.waddr(reg_file__waddr),
.wdata(reg_file__wdata),
.wen (reg_file__wen)
);
//-------------------------------------------------------------
// End of component reg_file
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:45
// @update
// def update_signal():
// if s.times == TimeType( num_ctrl ) or s.reg_file.rdata[0].ctrl == OPT_START:
// s.send_ctrl.en = b1( 0 )
// else:
// s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
// s.recv_waddr.rdy = b1( 1 )
// s.recv_ctrl.rdy = b1( 1 )
always_comb begin : update_signal
if ((times == 2'd3) || (reg_file__rdata[0].ctrl == __const__OPT_START)) begin
send_ctrl__en = 1'd0;
end else send_ctrl__en = send_ctrl__rdy;
recv_waddr__rdy = 1'd1;
recv_ctrl__rdy = 1'd1;
end
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:54
// @update_ff
// def update_raddr():
// if s.reg_file.rdata[0].ctrl != OPT_START:
// if s.times < TimeType( num_ctrl ):
// s.times <<= s.times + TimeType( 1 )
// if s.reg_file.raddr[0] < last_item:
// s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
// else:
// s.reg_file.raddr[0] <<= AddrType( 0 )
always_ff @(posedge clk) begin : update_raddr
if (reg_file__rdata[0].ctrl != __const__OPT_START) begin
if (times < 2'd3) begin
times <= times + 2'd1;
end
if (reg_file__raddr[0] < __const__last_item_at_update_raddr) begin
reg_file__raddr[0] <= reg_file__raddr[0] + 2'd1;
end else reg_file__raddr[0] <= 2'd0;
end
end
assign reg_file__clk = clk;
assign reg_file__reset = reset;
assign send_ctrl__msg = reg_file__rdata[0];
assign reg_file__waddr[0] = recv_waddr__msg;
assign reg_file__wdata[0] = recv_ctrl__msg;
assign reg_file__wen[0] = recv_waddr__en;
endmodule
| 6.639327 |
module Crossbar__9de0b627a60fd452 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_8 recv_opt__msg,
output logic [0:0] recv_opt__rdy,
output logic [0:0] send_data__en[0:7],
output CGRAData_32_1 send_data__msg[0:7],
input logic [0:0] send_data__rdy[0:7]
);
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_outports_at_update_signal = 32'd8;
logic [0:0] __tmpvar__update_signal_out_rdy;
logic [2:0] __tmpvar__update_signal_in_dir;
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/noc/Crossbar.py:32
// @update
// def update_signal():
// out_rdy = b1( 0 )
// if s.recv_opt.msg.ctrl != OPT_START:
// for i in range( num_outports ):
// in_dir = s.recv_opt.msg.outport[i]
// out_rdy = out_rdy | s.send_data[i].rdy
// if in_dir > OutType( 0 ):
// in_dir = in_dir - OutType( 1 )
// s.recv_data[in_dir].rdy = s.send_data[i].rdy
// s.send_data[i].en = s.recv_data[in_dir].en
// s.send_data[i].msg = s.recv_data[in_dir].msg
// else:
// for i in range( num_outports ):
// s.send_data[i].en = b1( 0 )
// s.recv_opt.rdy = out_rdy
always_comb begin : update_signal
__tmpvar__update_signal_out_rdy = 1'd0;
if (recv_opt__msg.ctrl != __const__OPT_START) begin
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) begin
__tmpvar__update_signal_in_dir = recv_opt__msg.outport[i];
__tmpvar__update_signal_out_rdy = __tmpvar__update_signal_out_rdy | send_data__rdy[i];
if (__tmpvar__update_signal_in_dir > 3'd0) begin
__tmpvar__update_signal_in_dir = __tmpvar__update_signal_in_dir - 3'd1;
recv_data__rdy[__tmpvar__update_signal_in_dir] = send_data__rdy[i];
send_data__en[i] = recv_data__en[__tmpvar__update_signal_in_dir];
send_data__msg[i] = recv_data__msg[__tmpvar__update_signal_in_dir];
end
end
end else
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) send_data__en[i] = 1'd0;
recv_opt__rdy = __tmpvar__update_signal_out_rdy;
end
endmodule
| 8.434496 |
module CtrlMem__CtrlType_CGRAConfig_5_6_8__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_waddr__rdy,
output logic [0:0] send_ctrl__en,
output CGRAConfig_5_6_8 send_ctrl__msg,
input logic [0:0] send_ctrl__rdy
);
localparam logic [31:0] __const__num_ctrl_at_update_signal = 32'd3;
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_ctrl_at_update_raddr = 32'd3;
localparam logic [1:0] __const__last_item_at_update_raddr = 2'd2;
logic [1:0] times;
//-------------------------------------------------------------
// Component reg_file
//-------------------------------------------------------------
logic [0:0] reg_file__clk;
logic [1:0] reg_file__raddr[0:0];
CGRAConfig_5_6_8 reg_file__rdata[0:0];
logic [0:0] reg_file__reset;
logic [1:0] reg_file__waddr[0:0];
CGRAConfig_5_6_8 reg_file__wdata[0:0];
logic [0:0] reg_file__wen[0:0];
RegisterFile__d0a98e0d377198ba reg_file (
.clk (reg_file__clk),
.raddr(reg_file__raddr),
.rdata(reg_file__rdata),
.reset(reg_file__reset),
.waddr(reg_file__waddr),
.wdata(reg_file__wdata),
.wen (reg_file__wen)
);
//-------------------------------------------------------------
// End of component reg_file
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:45
// @update
// def update_signal():
// if s.times == TimeType( num_ctrl ) or s.reg_file.rdata[0].ctrl == OPT_START:
// s.send_ctrl.en = b1( 0 )
// else:
// s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
// s.recv_waddr.rdy = b1( 1 )
// s.recv_ctrl.rdy = b1( 1 )
always_comb begin : update_signal
if ((times == 2'd3) || (reg_file__rdata[0].ctrl == __const__OPT_START)) begin
send_ctrl__en = 1'd0;
end else send_ctrl__en = send_ctrl__rdy;
recv_waddr__rdy = 1'd1;
recv_ctrl__rdy = 1'd1;
end
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:54
// @update_ff
// def update_raddr():
// if s.reg_file.rdata[0].ctrl != OPT_START:
// if s.times < TimeType( num_ctrl ):
// s.times <<= s.times + TimeType( 1 )
// if s.reg_file.raddr[0] < last_item:
// s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
// else:
// s.reg_file.raddr[0] <<= AddrType( 0 )
always_ff @(posedge clk) begin : update_raddr
if (reg_file__rdata[0].ctrl != __const__OPT_START) begin
if (times < 2'd3) begin
times <= times + 2'd1;
end
if (reg_file__raddr[0] < __const__last_item_at_update_raddr) begin
reg_file__raddr[0] <= reg_file__raddr[0] + 2'd1;
end else reg_file__raddr[0] <= 2'd0;
end
end
assign reg_file__clk = clk;
assign reg_file__reset = reset;
assign send_ctrl__msg = reg_file__rdata[0];
assign reg_file__waddr[0] = recv_waddr__msg;
assign reg_file__wdata[0] = recv_ctrl__msg;
assign reg_file__wen[0] = recv_waddr__en;
endmodule
| 6.639327 |
module Crossbar__9de0b627a60fd452 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_8 recv_opt__msg,
output logic [0:0] recv_opt__rdy,
output logic [0:0] send_data__en[0:7],
output CGRAData_32_1 send_data__msg[0:7],
input logic [0:0] send_data__rdy[0:7]
);
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_outports_at_update_signal = 32'd8;
logic [0:0] __tmpvar__update_signal_out_rdy;
logic [2:0] __tmpvar__update_signal_in_dir;
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/noc/Crossbar.py:32
// @update
// def update_signal():
// out_rdy = b1( 0 )
// if s.recv_opt.msg.ctrl != OPT_START:
// for i in range( num_outports ):
// in_dir = s.recv_opt.msg.outport[i]
// out_rdy = out_rdy | s.send_data[i].rdy
// if in_dir > OutType( 0 ):
// in_dir = in_dir - OutType( 1 )
// s.recv_data[in_dir].rdy = s.send_data[i].rdy
// s.send_data[i].en = s.recv_data[in_dir].en
// s.send_data[i].msg = s.recv_data[in_dir].msg
// else:
// for i in range( num_outports ):
// s.send_data[i].en = b1( 0 )
// s.recv_opt.rdy = out_rdy
always_comb begin : update_signal
__tmpvar__update_signal_out_rdy = 1'd0;
if (recv_opt__msg.ctrl != __const__OPT_START) begin
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) begin
__tmpvar__update_signal_in_dir = recv_opt__msg.outport[i];
__tmpvar__update_signal_out_rdy = __tmpvar__update_signal_out_rdy | send_data__rdy[i];
if (__tmpvar__update_signal_in_dir > 3'd0) begin
__tmpvar__update_signal_in_dir = __tmpvar__update_signal_in_dir - 3'd1;
recv_data__rdy[__tmpvar__update_signal_in_dir] = send_data__rdy[i];
send_data__en[i] = recv_data__en[__tmpvar__update_signal_in_dir];
send_data__msg[i] = recv_data__msg[__tmpvar__update_signal_in_dir];
end
end
end else
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) send_data__en[i] = 1'd0;
recv_opt__rdy = __tmpvar__update_signal_out_rdy;
end
endmodule
| 8.434496 |
module CtrlMem__CtrlType_CGRAConfig_5_6_8__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_waddr__rdy,
output logic [0:0] send_ctrl__en,
output CGRAConfig_5_6_8 send_ctrl__msg,
input logic [0:0] send_ctrl__rdy
);
localparam logic [31:0] __const__num_ctrl_at_update_signal = 32'd3;
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_ctrl_at_update_raddr = 32'd3;
localparam logic [1:0] __const__last_item_at_update_raddr = 2'd2;
logic [1:0] times;
//-------------------------------------------------------------
// Component reg_file
//-------------------------------------------------------------
logic [0:0] reg_file__clk;
logic [1:0] reg_file__raddr[0:0];
CGRAConfig_5_6_8 reg_file__rdata[0:0];
logic [0:0] reg_file__reset;
logic [1:0] reg_file__waddr[0:0];
CGRAConfig_5_6_8 reg_file__wdata[0:0];
logic [0:0] reg_file__wen[0:0];
RegisterFile__d0a98e0d377198ba reg_file (
.clk (reg_file__clk),
.raddr(reg_file__raddr),
.rdata(reg_file__rdata),
.reset(reg_file__reset),
.waddr(reg_file__waddr),
.wdata(reg_file__wdata),
.wen (reg_file__wen)
);
//-------------------------------------------------------------
// End of component reg_file
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:45
// @update
// def update_signal():
// if s.times == TimeType( num_ctrl ) or s.reg_file.rdata[0].ctrl == OPT_START:
// s.send_ctrl.en = b1( 0 )
// else:
// s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
// s.recv_waddr.rdy = b1( 1 )
// s.recv_ctrl.rdy = b1( 1 )
always_comb begin : update_signal
if ((times == 2'd3) || (reg_file__rdata[0].ctrl == __const__OPT_START)) begin
send_ctrl__en = 1'd0;
end else send_ctrl__en = send_ctrl__rdy;
recv_waddr__rdy = 1'd1;
recv_ctrl__rdy = 1'd1;
end
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:54
// @update_ff
// def update_raddr():
// if s.reg_file.rdata[0].ctrl != OPT_START:
// if s.times < TimeType( num_ctrl ):
// s.times <<= s.times + TimeType( 1 )
// if s.reg_file.raddr[0] < last_item:
// s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
// else:
// s.reg_file.raddr[0] <<= AddrType( 0 )
always_ff @(posedge clk) begin : update_raddr
if (reg_file__rdata[0].ctrl != __const__OPT_START) begin
if (times < 2'd3) begin
times <= times + 2'd1;
end
if (reg_file__raddr[0] < __const__last_item_at_update_raddr) begin
reg_file__raddr[0] <= reg_file__raddr[0] + 2'd1;
end else reg_file__raddr[0] <= 2'd0;
end
end
assign reg_file__clk = clk;
assign reg_file__reset = reset;
assign send_ctrl__msg = reg_file__rdata[0];
assign reg_file__waddr[0] = recv_waddr__msg;
assign reg_file__wdata[0] = recv_ctrl__msg;
assign reg_file__wen[0] = recv_waddr__en;
endmodule
| 6.639327 |
module Crossbar__9de0b627a60fd452 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_data__en[0:5],
input CGRAData_32_1 recv_data__msg[0:5],
output logic [0:0] recv_data__rdy[0:5],
input logic [0:0] recv_opt__en,
input CGRAConfig_5_6_8 recv_opt__msg,
output logic [0:0] recv_opt__rdy,
output logic [0:0] send_data__en[0:7],
output CGRAData_32_1 send_data__msg[0:7],
input logic [0:0] send_data__rdy[0:7]
);
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_outports_at_update_signal = 32'd8;
logic [0:0] __tmpvar__update_signal_out_rdy;
logic [2:0] __tmpvar__update_signal_in_dir;
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/noc/Crossbar.py:32
// @update
// def update_signal():
// out_rdy = b1( 0 )
// if s.recv_opt.msg.ctrl != OPT_START:
// for i in range( num_outports ):
// in_dir = s.recv_opt.msg.outport[i]
// out_rdy = out_rdy | s.send_data[i].rdy
// if in_dir > OutType( 0 ):
// in_dir = in_dir - OutType( 1 )
// s.recv_data[in_dir].rdy = s.send_data[i].rdy
// s.send_data[i].en = s.recv_data[in_dir].en
// s.send_data[i].msg = s.recv_data[in_dir].msg
// else:
// for i in range( num_outports ):
// s.send_data[i].en = b1( 0 )
// s.recv_opt.rdy = out_rdy
always_comb begin : update_signal
__tmpvar__update_signal_out_rdy = 1'd0;
if (recv_opt__msg.ctrl != __const__OPT_START) begin
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) begin
__tmpvar__update_signal_in_dir = recv_opt__msg.outport[i];
__tmpvar__update_signal_out_rdy = __tmpvar__update_signal_out_rdy | send_data__rdy[i];
if (__tmpvar__update_signal_in_dir > 3'd0) begin
__tmpvar__update_signal_in_dir = __tmpvar__update_signal_in_dir - 3'd1;
recv_data__rdy[__tmpvar__update_signal_in_dir] = send_data__rdy[i];
send_data__en[i] = recv_data__en[__tmpvar__update_signal_in_dir];
send_data__msg[i] = recv_data__msg[__tmpvar__update_signal_in_dir];
end
end
end else
for (int i = 0; i < __const__num_outports_at_update_signal; i += 1) send_data__en[i] = 1'd0;
recv_opt__rdy = __tmpvar__update_signal_out_rdy;
end
endmodule
| 8.434496 |
module CtrlMem__CtrlType_CGRAConfig_5_6_8__ctrl_mem_size_3__num_ctrl_3 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_5_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_waddr__rdy,
output logic [0:0] send_ctrl__en,
output CGRAConfig_5_6_8 send_ctrl__msg,
input logic [0:0] send_ctrl__rdy
);
localparam logic [31:0] __const__num_ctrl_at_update_signal = 32'd3;
localparam logic [4:0] __const__OPT_START = 5'd0;
localparam logic [31:0] __const__num_ctrl_at_update_raddr = 32'd3;
localparam logic [1:0] __const__last_item_at_update_raddr = 2'd2;
logic [1:0] times;
//-------------------------------------------------------------
// Component reg_file
//-------------------------------------------------------------
logic [0:0] reg_file__clk;
logic [1:0] reg_file__raddr[0:0];
CGRAConfig_5_6_8 reg_file__rdata[0:0];
logic [0:0] reg_file__reset;
logic [1:0] reg_file__waddr[0:0];
CGRAConfig_5_6_8 reg_file__wdata[0:0];
logic [0:0] reg_file__wen[0:0];
RegisterFile__d0a98e0d377198ba reg_file (
.clk (reg_file__clk),
.raddr(reg_file__raddr),
.rdata(reg_file__rdata),
.reset(reg_file__reset),
.waddr(reg_file__waddr),
.wdata(reg_file__wdata),
.wen (reg_file__wen)
);
//-------------------------------------------------------------
// End of component reg_file
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:45
// @update
// def update_signal():
// if s.times == TimeType( num_ctrl ) or s.reg_file.rdata[0].ctrl == OPT_START:
// s.send_ctrl.en = b1( 0 )
// else:
// s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
// s.recv_waddr.rdy = b1( 1 )
// s.recv_ctrl.rdy = b1( 1 )
always_comb begin : update_signal
if ((times == 2'd3) || (reg_file__rdata[0].ctrl == __const__OPT_START)) begin
send_ctrl__en = 1'd0;
end else send_ctrl__en = send_ctrl__rdy;
recv_waddr__rdy = 1'd1;
recv_ctrl__rdy = 1'd1;
end
// PyMTL Update Block Source
// At /home/ct535/project/PyCGRA/mem/ctrl/CtrlMem.py:54
// @update_ff
// def update_raddr():
// if s.reg_file.rdata[0].ctrl != OPT_START:
// if s.times < TimeType( num_ctrl ):
// s.times <<= s.times + TimeType( 1 )
// if s.reg_file.raddr[0] < last_item:
// s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
// else:
// s.reg_file.raddr[0] <<= AddrType( 0 )
always_ff @(posedge clk) begin : update_raddr
if (reg_file__rdata[0].ctrl != __const__OPT_START) begin
if (times < 2'd3) begin
times <= times + 2'd1;
end
if (reg_file__raddr[0] < __const__last_item_at_update_raddr) begin
reg_file__raddr[0] <= reg_file__raddr[0] + 2'd1;
end else reg_file__raddr[0] <= 2'd0;
end
end
assign reg_file__clk = clk;
assign reg_file__reset = reset;
assign send_ctrl__msg = reg_file__rdata[0];
assign reg_file__waddr[0] = recv_waddr__msg;
assign reg_file__wdata[0] = recv_ctrl__msg;
assign reg_file__wen[0] = recv_waddr__en;
endmodule
| 6.639327 |
module ChannelRTL__DataType_CGRAData_32_1_1__latency_1 (
input logic [0:0] clk,
output logic [1:0] count,
input logic [0:0] reset,
input logic [0:0] recv__en,
input CGRAData_32_1_1 recv__msg,
output logic [0:0] recv__rdy,
output logic [0:0] send__en,
output CGRAData_32_1_1 send__msg,
input logic [0:0] send__rdy
);
localparam CGRAData_32_1_1 data = {32'd0, 1'd0, 1'd0};
localparam logic [31:0] latency = 32'd1;
//-------------------------------------------------------------
// Component queues[0:0]
//-------------------------------------------------------------
logic [0:0] queues__clk[0:0];
logic [1:0] queues__count[0:0];
logic [0:0] queues__reset[0:0];
logic [0:0] queues__deq__en[0:0];
logic [0:0] queues__deq__rdy[0:0];
CGRAData_32_1_1 queues__deq__ret[0:0];
logic [0:0] queues__enq__en[0:0];
CGRAData_32_1_1 queues__enq__msg[0:0];
logic [0:0] queues__enq__rdy[0:0];
NormalQueueRTL__EntryType_CGRAData_32_1_1__num_entries_2 queues__0 (
.clk(queues__clk[0]),
.count(queues__count[0]),
.reset(queues__reset[0]),
.deq__en(queues__deq__en[0]),
.deq__rdy(queues__deq__rdy[0]),
.deq__ret(queues__deq__ret[0]),
.enq__en(queues__enq__en[0]),
.enq__msg(queues__enq__msg[0]),
.enq__rdy(queues__enq__rdy[0])
);
//-------------------------------------------------------------
// End of component queues[0:0]
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/cheng/workspace/projects/cgra/vrsa/noc/ChannelRTL.py:35
// @update
// def process():
// if s.recv.msg.bypass == b1( 0 ):
// s.recv.rdy = s.queues[0].enq.rdy
// s.queues[0].enq.msg = s.recv.msg
// s.queues[0].enq.en = s.recv.en and s.queues[0].enq.rdy
// for i in range(s.latency - 1):
// s.queues[i+1].enq.msg = s.queues[i].deq.ret
// s.queues[i+1].enq.en = s.queues[i].deq.rdy and s.queues[i+1].enq.rdy
// s.queues[i].deq.en = s.queues[i+1].enq.en
//
// s.send.msg = s.queues[s.latency-1].deq.ret
// s.send.en = s.send.rdy and s.queues[s.latency-1].deq.rdy
// s.queues[s.latency-1].deq.en = s.send.en
// else:
// s.send.msg = s.data
// s.send.msg.payload = s.recv.msg.payload
// s.send.msg.predicate = s.recv.msg.predicate
// s.send.msg.bypass = b1( 0 )
// s.send.en = s.send.rdy and s.recv.en
// s.recv.rdy = s.send.rdy
always_comb begin : process
if (recv__msg.bypass == 1'd0) begin
recv__rdy = queues__enq__rdy[0];
queues__enq__msg[0] = recv__msg;
queues__enq__en[0] = recv__en && queues__enq__rdy[0];
for (int i = 0; i < latency - 1; i += 1) begin
queues__enq__msg[i+1] = queues__deq__ret[i];
queues__enq__en[i+1] = queues__deq__rdy[i] && queues__enq__rdy[i+1];
queues__deq__en[i] = queues__enq__en[i+1];
end
send__msg = queues__deq__ret[latency-1];
send__en = send__rdy && queues__deq__rdy[latency-1];
queues__deq__en[latency-1] = send__en;
end else begin
send__msg = data;
send__msg.payload = recv__msg.payload;
send__msg.predicate = recv__msg.predicate;
send__msg.bypass = 1'd0;
send__en = send__rdy && recv__en;
recv__rdy = send__rdy;
end
end
assign queues__clk[0] = clk;
assign queues__reset[0] = reset;
assign count = queues__count[0];
endmodule
| 6.712902 |
module CtrlMemRTL__8f238acfb01302b1 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv_ctrl__en,
input CGRAConfig_6_4_6_8 recv_ctrl__msg,
output logic [0:0] recv_ctrl__rdy,
input logic [0:0] recv_waddr__en,
input logic [1:0] recv_waddr__msg,
output logic [0:0] recv_waddr__rdy,
output logic [0:0] send_ctrl__en,
output CGRAConfig_6_4_6_8 send_ctrl__msg,
input logic [0:0] send_ctrl__rdy
);
localparam logic [31:0] __const__num_ctrl_at_update_signal = 32'd3;
localparam logic [5:0] __const__OPT_START = 6'd0;
localparam logic [31:0] __const__num_ctrl_at_update_raddr = 32'd3;
localparam logic [1:0] __const__last_item_at_update_raddr = 2'd2;
logic [1:0] times;
//-------------------------------------------------------------
// Component reg_file
//-------------------------------------------------------------
logic [0:0] reg_file__clk;
logic [1:0] reg_file__raddr[0:0];
CGRAConfig_6_4_6_8 reg_file__rdata[0:0];
logic [0:0] reg_file__reset;
logic [1:0] reg_file__waddr[0:0];
CGRAConfig_6_4_6_8 reg_file__wdata[0:0];
logic [0:0] reg_file__wen[0:0];
RegisterFile__63449cda1f03128c reg_file (
.clk (reg_file__clk),
.raddr(reg_file__raddr),
.rdata(reg_file__rdata),
.reset(reg_file__reset),
.waddr(reg_file__waddr),
.wdata(reg_file__wdata),
.wen (reg_file__wen)
);
//-------------------------------------------------------------
// End of component reg_file
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/cheng/workspace/projects/cgra/vrsa/mem/ctrl/CtrlMemRTL.py:42
// @update
// def update_signal():
// if s.times == TimeType( num_ctrl ) or s.reg_file.rdata[0].ctrl == OPT_START:
// s.send_ctrl.en = b1( 0 )
// else:
// s.send_ctrl.en = s.send_ctrl.rdy # s.recv_raddr[i].rdy
// s.recv_waddr.rdy = b1( 1 )
// s.recv_ctrl.rdy = b1( 1 )
always_comb begin : update_signal
if ((times == 2'd3) || (reg_file__rdata[0].ctrl == __const__OPT_START)) begin
send_ctrl__en = 1'd0;
end else send_ctrl__en = send_ctrl__rdy;
recv_waddr__rdy = 1'd1;
recv_ctrl__rdy = 1'd1;
end
// PyMTL Update Block Source
// At /home/cheng/workspace/projects/cgra/vrsa/mem/ctrl/CtrlMemRTL.py:51
// @update_ff
// def update_raddr():
// if s.reg_file.rdata[0].ctrl != OPT_START:
// if s.times < TimeType( num_ctrl ):
// s.times <<= s.times + TimeType( 1 )
// if s.reg_file.raddr[0] < last_item:
// s.reg_file.raddr[0] <<= s.reg_file.raddr[0] + AddrType( 1 )
// else:
// s.reg_file.raddr[0] <<= AddrType( 0 )
always_ff @(posedge clk) begin : update_raddr
if (reg_file__rdata[0].ctrl != __const__OPT_START) begin
if (times < 2'd3) begin
times <= times + 2'd1;
end
if (reg_file__raddr[0] < __const__last_item_at_update_raddr) begin
reg_file__raddr[0] <= reg_file__raddr[0] + 2'd1;
end else reg_file__raddr[0] <= 2'd0;
end
end
assign reg_file__clk = clk;
assign reg_file__reset = reset;
assign send_ctrl__msg = reg_file__rdata[0];
assign reg_file__waddr[0] = recv_waddr__msg;
assign reg_file__wdata[0] = recv_ctrl__msg;
assign reg_file__wen[0] = recv_waddr__en;
endmodule
| 6.696227 |
module RegisterRTL__DataType_CGRAData_1_1__latency_1 (
input logic [0:0] clk,
input logic [0:0] reset,
input logic [0:0] recv__en,
input CGRAData_1_1 recv__msg,
output logic [0:0] recv__rdy,
output logic [0:0] send__en,
output CGRAData_1_1 send__msg,
input logic [0:0] send__rdy
);
localparam logic [31:0] latency = 32'd1;
//-------------------------------------------------------------
// Component queues[0:0]
//-------------------------------------------------------------
logic [0:0] queues__clk[0:0];
logic [1:0] queues__count[0:0];
logic [0:0] queues__reset[0:0];
logic [0:0] queues__deq__en[0:0];
logic [0:0] queues__deq__rdy[0:0];
CGRAData_1_1 queues__deq__ret[0:0];
logic [0:0] queues__enq__en[0:0];
CGRAData_1_1 queues__enq__msg[0:0];
logic [0:0] queues__enq__rdy[0:0];
NormalQueueRTL__EntryType_CGRAData_1_1__num_entries_2 queues__0 (
.clk(queues__clk[0]),
.count(queues__count[0]),
.reset(queues__reset[0]),
.deq__en(queues__deq__en[0]),
.deq__rdy(queues__deq__rdy[0]),
.deq__ret(queues__deq__ret[0]),
.enq__en(queues__enq__en[0]),
.enq__msg(queues__enq__msg[0]),
.enq__rdy(queues__enq__rdy[0])
);
//-------------------------------------------------------------
// End of component queues[0:0]
//-------------------------------------------------------------
// PyMTL Update Block Source
// At /home/cheng/workspace/projects/cgra/vrsa/rf/RegisterRTL.py:30
// @update
// def process():
// s.recv.rdy = s.queues[0].enq.rdy
// s.queues[0].enq.msg = s.recv.msg
// s.queues[0].enq.en = s.recv.en and s.queues[0].enq.rdy
// for i in range(s.latency - 1):
// s.queues[i+1].enq.msg = s.queues[i].deq.ret
// s.queues[i+1].enq.en = s.queues[i].deq.rdy and s.queues[i+1].enq.rdy
// s.queues[i].deq.en = s.queues[i+1].enq.en
//
// s.send.msg = s.queues[s.latency-1].deq.ret
// s.send.en = s.send.rdy and s.queues[s.latency-1].deq.rdy
// s.queues[s.latency-1].deq.en = s.send.en
always_comb begin : process
recv__rdy = queues__enq__rdy[0];
queues__enq__msg[0] = recv__msg;
queues__enq__en[0] = recv__en && queues__enq__rdy[0];
for (int i = 0; i < latency - 1; i += 1) begin
queues__enq__msg[i+1] = queues__deq__ret[i];
queues__enq__en[i+1] = queues__deq__rdy[i] && queues__enq__rdy[i+1];
queues__deq__en[i] = queues__enq__en[i+1];
end
send__msg = queues__deq__ret[latency-1];
send__en = send__rdy && queues__deq__rdy[latency-1];
queues__deq__en[latency-1] = send__en;
end
assign queues__clk[0] = clk;
assign queues__reset[0] = reset;
endmodule
| 6.84815 |
module tile_8x1 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb_in,
right_sb_in,
top_cb_out,
right_cb_out
);
input clk, scan_clk, clb_scan_in, clb_scan_en, conn_scan_in, conn_scan_en, reset;
output clb_scan_out, conn_scan_out;
input [3:0] top_in, bottom_in;
output [3:0] top_out, bottom_out;
input bottom_clb_in;
output top_cb_out;
//scaling singals here
input [31:0] left_in, right_in;
output [31:0] left_out, right_out;
input [7:0] left_clb_in, right_sb_in;
output [7:0] left_clb_out, right_cb_out;
//interconnect
wire [3:0] top_bottom_conn, bottom_top_conn;
wire cb_conn;
wire clb_scan_conn, conn_scan_conn;
/*ALL inputs: (Classifeid for the case of vertical expansion)
//Inferred
clk, scan_clk,
clb_scan_en, conn_scan_en
//One or the other
clb_scan_in, clb_scan_out,
conn_scan_in, conn_scan_out,
bottom_clb_in, top_cb_out,
top_in, bottom_in,
top_out, bottom_out,
//Change index
left_in, right_in, left_out, right_out, left_clb_out, left_clb_in, right_sb_in, right_cb_out, */
tile_4x1 tile_4x1_top (
.left_in(left_in[15:0]),
.left_out(left_out[15:0]),
.left_clb_in(left_clb_in[3:0]),
.left_clb_out(left_clb_out[3:0]),
.right_in(right_in[15:0]),
.right_out(right_out[15:0]),
.right_sb_in(right_sb_in[3:0]),
.right_cb_out(right_cb_out[3:0]),
.bottom_in(bottom_top_conn),
.bottom_out(top_bottom_conn),
.bottom_clb_in(cb_conn),
.clb_scan_out(clb_scan_conn),
.conn_scan_out(conn_scan_conn),
.*
);
tile_4x1 tile_4x1_botoom (
.left_in(left_in[31:16]),
.left_out(left_out[31:16]),
.left_clb_in(left_clb_in[7:4]),
.left_clb_out(left_clb_out[7:4]),
.right_in(right_in[31:16]),
.right_out(right_out[31:16]),
.right_sb_in(right_sb_in[7:4]),
.right_cb_out(right_cb_out[7:4]),
.top_in(top_bottom_conn),
.top_out(bottom_top_conn),
.top_cb_out(cb_conn),
.clb_scan_in(clb_scan_conn),
.conn_scan_in(conn_scan_conn),
.*
);
endmodule
| 6.756362 |
module tile_4x1 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb_in,
right_sb_in,
top_cb_out,
right_cb_out
);
input clk, scan_clk, clb_scan_in, clb_scan_en, conn_scan_in, conn_scan_en, reset;
output clb_scan_out, conn_scan_out;
input [3:0] top_in, bottom_in;
output [3:0] top_out, bottom_out;
input bottom_clb_in;
output top_cb_out;
//scaling singals here
input [15:0] left_in, right_in;
output [15:0] left_out, right_out;
input [3:0] left_clb_in, right_sb_in;
output [3:0] left_clb_out, right_cb_out;
//interconnect
wire [3:0] top_bottom_conn, bottom_top_conn;
wire cb_conn;
wire clb_scan_conn, conn_scan_conn;
/*ALL inputs: (Classifeid for the case of vertical expansion)
//Inferred
clk, scan_clk,
clb_scan_en, conn_scan_en
//One or the other
clb_scan_in, clb_scan_out,
conn_scan_in, conn_scan_out,
bottom_clb_in, top_cb_out,
top_in, bottom_in,
top_out, bottom_out,
//Change index
left_in, right_in, left_out, right_out, left_clb_out, left_clb_in, right_sb_in, right_cb_out, */
tile_2x1 tile_2x1_top (
.left_in(left_in[7:0]),
.left_out(left_out[7:0]),
.left_clb_in(left_clb_in[1:0]),
.left_clb_out(left_clb_out[1:0]),
.right_in(right_in[7:0]),
.right_out(right_out[7:0]),
.right_sb_in(right_sb_in[1:0]),
.right_cb_out(right_cb_out[1:0]),
.bottom_in(bottom_top_conn),
.bottom_out(top_bottom_conn),
.bottom_clb_in(cb_conn),
.clb_scan_out(clb_scan_conn),
.conn_scan_out(conn_scan_conn),
.*
);
tile_2x1 tile_2x1_botoom (
.left_in(left_in[15:8]),
.left_out(left_out[15:8]),
.left_clb_in(left_clb_in[3:2]),
.left_clb_out(left_clb_out[3:2]),
.right_in(right_in[15:8]),
.right_out(right_out[15:8]),
.right_sb_in(right_sb_in[3:2]),
.right_cb_out(right_cb_out[3:2]),
.top_in(top_bottom_conn),
.top_out(bottom_top_conn),
.top_cb_out(cb_conn),
.clb_scan_in(clb_scan_conn),
.conn_scan_in(conn_scan_conn),
.*
);
endmodule
| 6.814472 |
module tile_2x1 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb_in,
right_sb_in,
top_cb_out,
right_cb_out
);
input clk, scan_clk, clb_scan_in, clb_scan_en, conn_scan_in, conn_scan_en, reset;
output clb_scan_out, conn_scan_out;
input [3:0] top_in, bottom_in;
output [3:0] top_out, bottom_out;
input bottom_clb_in;
output top_cb_out;
//scaling singals here
input [7:0] left_in, right_in;
output [7:0] left_out, right_out;
input [1:0] left_clb_in, right_sb_in;
output [1:0] left_clb_out, right_cb_out;
//interconnect
wire [3:0] top_bottom_conn, bottom_top_conn;
wire cb_conn;
wire clb_scan_conn, conn_scan_conn;
/*ALL inputs: (Classifeid for the case of vertical expansion)
//Inferred
clk, scan_clk,
clb_scan_en, conn_scan_en
//One or the other
clb_scan_in, clb_scan_out,
conn_scan_in, conn_scan_out,
bottom_clb_in, top_cb_out,
top_in, bottom_in,
top_out, bottom_out,
//Change index
left_in, right_in, left_out, right_out, left_clb_out, left_clb_in, right_sb_in, right_cb_out, */
tile inst_tile_top (
.left_in(left_in[3:0]),
.left_out(left_out[3:0]),
.left_clb_in(left_clb_in[0]),
.left_clb_out(left_clb_out[0]),
.right_in(right_in[3:0]),
.right_out(right_out[3:0]),
.right_sb_in(right_sb_in[0]),
.right_cb_out(right_cb_out[0]),
.bottom_in(bottom_top_conn),
.bottom_out(top_bottom_conn),
.bottom_clb_in(cb_conn),
.clb_scan_out(clb_scan_conn),
.conn_scan_out(conn_scan_conn),
.test_out_x4(),
.*
);
tile inst_tile_bottom (
.left_in(left_in[7:4]),
.left_out(left_out[7:4]),
.left_clb_in(left_clb_in[1]),
.left_clb_out(left_clb_out[1]),
.right_in(right_in[7:4]),
.right_out(right_out[7:4]),
.right_sb_in(right_sb_in[1]),
.right_cb_out(right_cb_out[1]),
.top_in(top_bottom_conn),
.top_out(bottom_top_conn),
.top_cb_out(cb_conn),
.clb_scan_in(clb_scan_conn),
.conn_scan_in(conn_scan_conn),
.test_out_x4(),
.*
);
endmodule
| 6.680381 |
module tile_8x8 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb_in,
right_sb_in,
top_cb_out,
right_cb_out
);
//clk + scan chain
input clk, scan_clk, clb_scan_in, clb_scan_en, conn_scan_in, conn_scan_en, reset;
output clb_scan_out, conn_scan_out;
//scaling singals for vertical expansion, non-scaling for horizontal
input [31:0] left_in, right_in;
output [31:0] left_out, right_out;
input [7:0] left_clb_in, right_sb_in;
output [7:0] left_clb_out, right_cb_out;
//scaling signals for horizontal expansion
input [31:0] top_in, bottom_in;
output [31:0] top_out, bottom_out;
input [7:0] bottom_clb_in;
output [7:0] top_cb_out;
//interconnect
wire [31:0] left_right_conn, right_left_conn;
wire [7:0] cb_conn, sb_conn;
wire clb_scan_conn, conn_scan_conn;
/*ALL inputs: (Classifeid for the case of horizontal expansion)
//Inferred
clk, scan_clk,
clb_scan_en, conn_scan_en
//One or the other
clb_scan_in, clb_scan_out,
conn_scan_in, conn_scan_out,
left_in, right_in,
left_out, right_out,
left_clb_out, right_sb_in
left_clb_in, right_cb_out,
//Change index
top_in, bottom_in, top_out, bottom_out, bottom_clb_in, top_cb_out, */
tile_8x4 tile_8x4_left (
.top_in(top_in[15:0]),
.top_out(top_out[15:0]),
.bottom_in(bottom_in[15:0]),
.bottom_out(bottom_out[15:0]),
.top_cb_out(top_cb_out[3:0]),
.bottom_clb_in(bottom_clb_in[3:0]),
.right_out(left_right_conn),
.right_in(right_left_conn),
.right_sb_in(sb_conn),
.right_cb_out(cb_conn),
.clb_scan_out(clb_scan_conn),
.conn_scan_out(conn_scan_conn),
.*
);
tile_8x4 tile_8x4_right (
.top_in(top_in[31:16]),
.top_out(top_out[31:16]),
.bottom_in(bottom_in[31:16]),
.bottom_out(bottom_out[31:16]),
.top_cb_out(top_cb_out[7:4]),
.bottom_clb_in(bottom_clb_in[7:4]),
.left_in(left_right_conn),
.left_out(right_left_conn),
.left_clb_out(sb_conn),
.left_clb_in(cb_conn),
.clb_scan_in(clb_scan_conn),
.conn_scan_in(conn_scan_conn),
.*
);
endmodule
| 7.04754 |
module tile_8x4 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb_in,
right_sb_in,
top_cb_out,
right_cb_out
);
//clk + scan chain
input clk, scan_clk, clb_scan_in, clb_scan_en, conn_scan_in, conn_scan_en, reset;
output clb_scan_out, conn_scan_out;
//scaling singals for vertical expansion, non-scaling for horizontal
input [31:0] left_in, right_in;
output [31:0] left_out, right_out;
input [7:0] left_clb_in, right_sb_in;
output [7:0] left_clb_out, right_cb_out;
//scaling signals for horizontal expansion
input [15:0] top_in, bottom_in;
output [15:0] top_out, bottom_out;
input [3:0] bottom_clb_in;
output [3:0] top_cb_out;
//interconnect
wire [31:0] left_right_conn, right_left_conn;
wire [7:0] cb_conn, sb_conn;
wire clb_scan_conn, conn_scan_conn;
/*ALL inputs: (Classifeid for the case of horizontal expansion)
//Inferred
clk, scan_clk,
clb_scan_en, conn_scan_en
//One or the other
clb_scan_in, clb_scan_out,
conn_scan_in, conn_scan_out,
left_in, right_in,
left_out, right_out,
left_clb_out, right_sb_in
left_clb_in, right_cb_out,
//Change index
top_in, bottom_in, top_out, bottom_out, bottom_clb_in, top_cb_out, */
tile_8x2 tile_8x2_left (
.top_in(top_in[7:0]),
.top_out(top_out[7:0]),
.bottom_in(bottom_in[7:0]),
.bottom_out(bottom_out[7:0]),
.top_cb_out(top_cb_out[1:0]),
.bottom_clb_in(bottom_clb_in[1:0]),
.right_out(left_right_conn),
.right_in(right_left_conn),
.right_sb_in(sb_conn),
.right_cb_out(cb_conn),
.clb_scan_out(clb_scan_conn),
.conn_scan_out(conn_scan_conn),
.*
);
tile_8x2 tile_8x2_right (
.top_in(top_in[15:8]),
.top_out(top_out[15:8]),
.bottom_in(bottom_in[15:8]),
.bottom_out(bottom_out[15:8]),
.top_cb_out(top_cb_out[3:2]),
.bottom_clb_in(bottom_clb_in[3:2]),
.left_in(left_right_conn),
.left_out(right_left_conn),
.left_clb_out(sb_conn),
.left_clb_in(cb_conn),
.clb_scan_in(clb_scan_conn),
.conn_scan_in(conn_scan_conn),
.*
);
endmodule
| 7.061012 |
module tile_8x2 (
clk,
scan_clk,
clb_scan_in,
clb_scan_out,
clb_scan_en,
conn_scan_in,
conn_scan_out,
conn_scan_en,
reset,
left_in,
right_in,
top_in,
bottom_in,
left_out,
right_out,
top_out,
bottom_out,
left_clb_out,
left_clb_in,
bottom_clb_in,
right_sb_in,
top_cb_out,
right_cb_out
);
//clk + scan chain
input clk, scan_clk, clb_scan_in, clb_scan_en, conn_scan_in, conn_scan_en, reset;
output clb_scan_out, conn_scan_out;
//scaling singals for vertical expansion, non-scaling for horizontal
input [31:0] left_in, right_in;
output [31:0] left_out, right_out;
input [7:0] left_clb_in, right_sb_in;
output [7:0] left_clb_out, right_cb_out;
//scaling signals for horizontal expansion
input [7:0] top_in, bottom_in;
output [7:0] top_out, bottom_out;
input [1:0] bottom_clb_in;
output [1:0] top_cb_out;
//interconnect
wire [31:0] left_right_conn, right_left_conn;
wire [7:0] cb_conn, sb_conn;
wire clb_scan_conn, conn_scan_conn;
/*ALL inputs: (Classifeid for the case of horizontal expansion)
//Inferred
clk, scan_clk,
clb_scan_en, conn_scan_en
//One or the other
clb_scan_in, clb_scan_out,
conn_scan_in, conn_scan_out,
left_in, right_in,
left_out, right_out,
left_clb_out, right_sb_in
left_clb_in, right_cb_out,
//Change index
top_in, bottom_in, top_out, bottom_out, bottom_clb_in, top_cb_out, */
tile_8x1 tile_8x1_left (
.top_in(top_in[3:0]),
.top_out(top_out[3:0]),
.bottom_in(bottom_in[3:0]),
.bottom_out(bottom_out[3:0]),
.top_cb_out(top_cb_out[0]),
.bottom_clb_in(bottom_clb_in[0]),
.right_out(left_right_conn),
.right_in(right_left_conn),
.right_sb_in(sb_conn),
.right_cb_out(cb_conn),
.clb_scan_out(clb_scan_conn),
.conn_scan_out(conn_scan_conn),
.*
);
tile_8x1 tile_8x1_right (
.top_in(top_in[7:4]),
.top_out(top_out[7:4]),
.bottom_in(bottom_in[7:4]),
.bottom_out(bottom_out[7:4]),
.top_cb_out(top_cb_out[1]),
.bottom_clb_in(bottom_clb_in[1]),
.left_in(left_right_conn),
.left_out(right_left_conn),
.left_clb_out(sb_conn),
.left_clb_in(cb_conn),
.clb_scan_in(clb_scan_conn),
.conn_scan_in(conn_scan_conn),
.*
);
endmodule
| 7.119048 |
module tile_cache (
input reset,
input clk,
input cache_req,
input [19:0] cache_addr,
output reg cache_valid,
output [31:0] cache_data,
input [31:0] rom_data,
input rom_valid,
output reg rom_req,
output reg [19:0] rom_addr
);
reg [19:9] tag [511:0];
reg [511:0] valid ;
reg [1:0] state = 0;
reg [8:0] idx_r;
wire [8:0] idx = cache_addr[8:0];
wire hit;
// if tag value matches the upper bits of the address
// and valid then no need to pass request to sdram
assign hit = (tag[idx] == cache_addr[19:9] && valid[idx] == 1 && state == 1);
assign cache_data = (hit == 1) ? cache_dout : rom_data;
always @(posedge clk) begin
cache_valid <= (cache_req != 0) && (hit == 1 || rom_valid == 1);
if (reset == 1) begin
state <= 0;
// reset bits that indicate tag is valid
valid <= 0;
end else begin
// if no read request then do nothing
if (cache_req == 0) begin
rom_req <= 0;
state <= 1;
end else begin
// if there is a hit then read from cache and say we are done
if (hit == 1) begin
rom_req <= 0;
end else if (state == 1) begin
// read from memory
idx_r <= idx;
// we need to read from sdram
rom_req <= 1;
rom_addr <= cache_addr;
// next state is wait for rom ready
state <= 2;
end else if (state == 2 && rom_valid == 1) begin
// write updated tag
tag[idx_r] <= rom_addr[19:9];
// mark tag valid
valid[idx_r] <= 1'b1;
cache_din <= rom_data;
state <= 3;
end else if (state == 3) begin
state <= 0;
end
end
end
end
reg [31:0] cache_din;
wire [31:0] cache_dout;
dual_port_ram #(
.LEN(512),
.DATA_WIDTH(32)
) cache_ram (
.clock_a(clk),
.address_a(idx_r),
.wren_a(state == 3),
.data_a(cache_din),
.q_a(),
.clock_b(clk),
.address_b(idx),
.wren_b(0),
.q_b(cache_dout)
);
endmodule
| 7.420221 |
module flipflop (
input wire [0:0] clk
, input wire [0:0] D
, output reg [0:0] Q
, input wire [0:0] prog_done // programming finished
, input wire [0:0] prog_data // mode: enabled (not disabled)
);
always @(posedge clk) begin
if (~prog_done || ~prog_data) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 6.626138 |
module scanchain_data_d17 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [17 - 1:0] prog_data
, output wire [ 1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 17;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
module prga_simple_buf (
input wire [0:0] C,
input wire [0:0] D,
output reg [0:0] Q
);
always @(posedge C) begin
Q <= D;
end
endmodule
| 7.13912 |
module prga_simple_bufr (
input wire [0:0] C,
input wire [0:0] R,
input wire [0:0] D,
output reg [0:0] Q
);
always @(posedge C) begin
if (R) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 7.13912 |
module scanchain_delim (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [0:0] prog_we_o
, output reg [1 - 1:0] prog_dout
);
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_we_o <= 1'b0;
prog_dout <= 1'b0;
end else if (~prog_done && prog_we) begin
prog_we_o <= 1'b1;
prog_dout <= prog_din;
end else begin
prog_we_o <= 1'b0;
end
end
endmodule
| 7.198827 |
module scanchain_data_d2 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [2 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 2;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
module scanchain_data_d3 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [3 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 3;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
module flipflop (
input wire [0:0] clk
, input wire [0:0] D
, output reg [0:0] Q
, input wire [0:0] prog_done // programming finished
, input wire [0:0] prog_data // mode: enabled (not disabled)
);
always @(posedge clk) begin
if (~prog_done || ~prog_data) begin
Q <= 1'b0;
end else begin
Q <= D;
end
end
endmodule
| 6.626138 |
module scanchain_data_d17 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [17 - 1:0] prog_data
, output wire [ 1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 17;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
module scanchain_data_d1 (
input wire [0:0] prog_clk
, input wire [0:0] prog_rst
, input wire [0:0] prog_done
, input wire [0:0] prog_we
, input wire [1 - 1:0] prog_din
, output reg [1 - 1:0] prog_data
, output wire [1 - 1:0] prog_dout
);
localparam CHAIN_BITCOUNT = 1;
localparam CHAIN_WIDTH = 1;
wire [CHAIN_BITCOUNT + CHAIN_WIDTH - 1:0] prog_data_next;
assign prog_data_next = {prog_data, prog_din};
always @(posedge prog_clk) begin
if (prog_rst) begin
prog_data <= {CHAIN_BITCOUNT{1'b0}};
end else if (~prog_done && prog_we) begin
prog_data <= prog_data_next[0+:CHAIN_BITCOUNT];
end
end
assign prog_dout = prog_data_next[CHAIN_BITCOUNT+:CHAIN_WIDTH];
endmodule
| 7.770095 |
module tile_memory (
input clk,
wen,
ren,
input [11:0] waddr,
raddr,
input [5:0] wdata,
output reg [5:0] rdata
);
reg [5:0] mem[0:4095]; // enough memory for 80x50 map of tiles // uses ~6 BRAMS of Ice40
always @(posedge clk) begin
if (ren) rdata <= mem[raddr];
if (wen) mem[waddr] <= wdata;
end
endmodule
| 6.881561 |
module tile_ram (
addra,
addrb,
clka,
clkb,
dina,
doutb,
wea
);
input [10 : 0] addra;
input [10 : 0] addrb;
input clka;
input clkb;
input [7 : 0] dina;
output [7 : 0] doutb;
input wea;
// synopsys translate_off
BLKMEMDP_V6_3 #(11, // c_addra_width
11, // c_addrb_width
"0", // c_default_data
1560, // c_depth_a
1560, // c_depth_b
0, // c_enable_rlocs
1, // c_has_default_data
1, // c_has_dina
0, // c_has_dinb
0, // c_has_douta
1, // c_has_doutb
0, // c_has_ena
0, // c_has_enb
0, // c_has_limit_data_pitch
0, // c_has_nda
0, // c_has_ndb
0, // c_has_rdya
0, // c_has_rdyb
0, // c_has_rfda
0, // c_has_rfdb
0, // c_has_sinita
0, // c_has_sinitb
1, // c_has_wea
0, // c_has_web
18, // c_limit_data_pitch
"mif_file_16_1", // c_mem_init_file
0, // c_pipe_stages_a
0, // c_pipe_stages_b
0, // c_reg_inputsa
0, // c_reg_inputsb
"NONE", // c_sim_collision_check
"0", // c_sinita_value
"0", // c_sinitb_value
8, // c_width_a
8, // c_width_b
0, // c_write_modea
0, // c_write_modeb
"0", // c_ybottom_addr
1, // c_yclka_is_rising
1, // c_yclkb_is_rising
1, // c_yena_is_high
1, // c_yenb_is_high
"hierarchy1", // c_yhierarchy
0, // c_ymake_bmm
"16kx1", // c_yprimitive_type
1, // c_ysinita_is_high
1, // c_ysinitb_is_high
"1024", // c_ytop_addr
0, // c_yuse_single_primitive
1, // c_ywea_is_high
1, // c_yweb_is_high
1) // c_yydisable_warnings
inst (
.ADDRA(addra),
.ADDRB(addrb),
.CLKA(clka),
.CLKB(clkb),
.DINA(dina),
.DOUTB(doutb),
.WEA(wea),
.DINB(),
.DOUTA(),
.ENA(),
.ENB(),
.NDA(),
.NDB(),
.RFDA(),
.RFDB(),
.RDYA(),
.RDYB(),
.SINITA(),
.SINITB(),
.WEB()
);
// synopsys translate_on
// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of tile_ram is "true"
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of tile_ram is "black_box"
endmodule
| 7.132429 |
module tile_rom (
clk,
addr,
rdata
);
parameter ADDR_WIDTH = 14;
parameter DATA_WIDTH = 8;
parameter ROM_DATA_FILE = "tiles.mem";
input clk;
input [ADDR_WIDTH-1:0] addr;
output reg [DATA_WIDTH-1:0] rdata;
reg [DATA_WIDTH-1:0] MY_ROM[0:2**ADDR_WIDTH-1];
initial $readmemb(ROM_DATA_FILE, MY_ROM);
always @(posedge clk) rdata <= MY_ROM[addr];
endmodule
| 7.868442 |
module tilting_registers (
clk,
rst,
D0_in,
D1_in,
D2_in,
D3_in,
D4_in,
D5_in,
D6_in,
D7_in,
D0_out,
D1_out,
D2_out,
D3_out,
D4_out,
D5_out,
D6_out,
D7_out
);
parameter wl = 8;
input clk, rst;
input [wl-1:0] D0_in, D1_in, D2_in, D3_in, D4_in, D5_in, D6_in, D7_in;
output [wl-1:0] D0_out, D1_out, D2_out, D3_out, D4_out, D5_out, D6_out, D7_out;
reg [wl-1:0] D1R0;
reg [wl-1:0] D2R0, D2R1;
reg [wl-1:0] D3R0, D3R1, D3R2;
reg [wl-1:0] D4R0, D4R1, D4R2, D4R3;
reg [wl-1:0] D5R0, D5R1, D5R2, D5R3, D5R4;
reg [wl-1:0] D6R0, D6R1, D6R2, D6R3, D6R4, D6R5;
reg [wl-1:0] D7R0, D7R1, D7R2, D7R3, D7R4, D7R5, D7R6;
always @(posedge clk or posedge rst) begin
if (rst) begin
D1R0 <= {wl{1'b0}};
D2R0 <= {wl{1'b0}};
D2R1 <= {wl{1'b0}};
D3R0 <= {wl{1'b0}};
D3R1 <= {wl{1'b0}};
D3R2 <= {wl{1'b0}};
D4R0 <= {wl{1'b0}};
D4R1 <= {wl{1'b0}};
D4R2 <= {wl{1'b0}};
D4R3 <= {wl{1'b0}};
D5R0 <= {wl{1'b0}};
D5R1 <= {wl{1'b0}};
D5R2 <= {wl{1'b0}};
D5R3 <= {wl{1'b0}};
D5R4 <= {wl{1'b0}};
D6R0 <= {wl{1'b0}};
D6R1 <= {wl{1'b0}};
D6R2 <= {wl{1'b0}};
D6R3 <= {wl{1'b0}};
D6R4 <= {wl{1'b0}};
D6R5 <= {wl{1'b0}};
D7R0 <= {wl{1'b0}};
D7R1 <= {wl{1'b0}};
D7R2 <= {wl{1'b0}};
D7R3 <= {wl{1'b0}};
D7R4 <= {wl{1'b0}};
D7R5 <= {wl{1'b0}};
D7R6 <= {wl{1'b0}};
end else begin
D1R0 <= D1_in;
D2R0 <= D2_in;
D2R1 <= D2R0;
D3R0 <= D3_in;
D3R1 <= D3R0;
D3R2 <= D3R1;
D4R0 <= D4_in;
D4R1 <= D4R0;
D4R2 <= D4R1;
D4R3 <= D4R2;
D5R0 <= D5_in;
D5R1 <= D5R0;
D5R2 <= D5R1;
D5R3 <= D5R2;
D5R4 <= D5R3;
D6R0 <= D6_in;
D6R1 <= D6R0;
D6R2 <= D6R1;
D6R3 <= D6R2;
D6R4 <= D6R3;
D6R5 <= D6R4;
D7R0 <= D7_in;
D7R1 <= D7R0;
D7R2 <= D7R1;
D7R3 <= D7R2;
D7R4 <= D7R3;
D7R5 <= D7R4;
D7R6 <= D7R5;
end
end
assign D0_out = D0_in;
assign D1_out = D1R0;
assign D2_out = D2R1;
assign D3_out = D3R2;
assign D4_out = D4R3;
assign D5_out = D5R4;
assign D6_out = D6R5;
assign D7_out = D7R6;
endmodule
| 6.663622 |
module timers_frc #(
parameter TIMER_WIDTH = 8,
parameter TIMER_PULSE_EXTD = 0
) (
input wire timer_clk,
input wire timer_resetn,
input wire timer_en,
input wire timer_mode,
input wire timerhwen,
input wire [TIMER_WIDTH-1:0] load_value,
output reg [ 31:0] current_value,
output reg toggle,
output wire interrupt,
output wire timertrig
);
reg rising_edge;
reg atzero;
reg [TIMER_WIDTH-1:0] timer;
reg extend1;
reg extend2;
reg extend3;
wire load;
wire raw_interrupt;
wire interrupt_extd1;
wire interrupt_extd2;
wire interrupt_extd3;
always @(posedge timer_clk or negedge timer_resetn) begin
if (timer_resetn == 1'b0) rising_edge <= 1'b0;
else rising_edge <= timer_en;
end
assign load = ((timer_en == 1'b1) & (rising_edge == 1'b0));
always @(posedge timer_clk or negedge timer_resetn) begin
if (timer_resetn == 1'b0) timer <= {TIMER_WIDTH{1'b1}};
else begin
if (timer_en == 1'b1) begin
if (load == 1'b1) timer <= load_value;
else begin
if (timer == {TIMER_WIDTH{1'b0}}) begin
if (timer_mode == 1'b0) timer <= {TIMER_WIDTH{1'b1}};
else timer <= load_value;
end else timer <= timer - {{(TIMER_WIDTH - 1) {1'b0}}, {1'b1}};
end
end else timer <= {TIMER_WIDTH{1'b1}};
end
end
always @(posedge timer_clk or negedge timer_resetn) begin
if (timer_resetn == 1'b0) atzero <= 1'b0;
else atzero <= (timer == {TIMER_WIDTH{1'b0}});
end
assign raw_interrupt = atzero;
assign timertrig = atzero & timerhwen;
always @(posedge timer_clk or negedge timer_resetn) begin
if (timer_resetn == 1'b0) toggle <= 1'b0;
else if (timer == {TIMER_WIDTH{1'b0}}) toggle <= ~toggle;
else;
end
always @(posedge timer_clk or negedge timer_resetn) begin
if (timer_resetn == 1'b0) begin
extend1 <= 1'b0;
extend2 <= 1'b0;
extend3 <= 1'b0;
end else begin
extend1 <= raw_interrupt;
extend2 <= extend1;
extend3 <= extend2;
end
end
assign interrupt_extd1 = raw_interrupt | extend1;
assign interrupt_extd2 = interrupt_extd1 | extend2;
assign interrupt_extd3 = interrupt_extd2 | extend3;
always @(*) begin
current_value = 32'b0;
if (timer_en == 1'b1) current_value[TIMER_WIDTH-1:0] = timer;
end
assign interrupt = ((TIMER_PULSE_EXTD == 0) ? raw_interrupt :
((TIMER_PULSE_EXTD == 1) ? interrupt_extd1 :
((TIMER_PULSE_EXTD == 2) ? interrupt_extd2 :
interrupt_extd3)));
endmodule
| 7.766675 |
module test;
/* Make a reset that pulses once. */
reg clk = 0;
reg [7:0] trg_wrd;
reg fifo_empty;
wire re;
wire [6:0] out;
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test);
fifo_empty = 1'b0;
trg_wrd = 8'b00000000;
#1 rst = 1'b1;
#1 rst = 1'b0;
#1 trg_wrd = 8'b10000001;
#1 trg_wrd = 8'b00000011;
#1 fifo_empty = 1'b0;
#100 $finish;
end
/* Make a regular pulsing clock. */
always #1 clk = !clk;
TimingControlUnit mod1 (
clk,
trg_wrd,
fifo_empty,
re,
rst
);
// initial
//$monitor("At time %t, trigger word %h, fifo_empty %h and re %h", $time, trg_wrd, fifo_empty, re);
endmodule
| 7.230422 |
module TimeAverager (
iCLK,
iVGA_BLANK,
iVGA_X,
iVGA_Y,
iRed,
iGreen,
iBlue,
oRed,
oGreen,
oBlue,
oSRAM_WE_N,
oSRAM_ADDR,
SRAM_DQ
);
input iCLK;
input iVGA_BLANK;
input [9:0] iVGA_X, iVGA_Y; //Address requested by VGA Ctrl
input [4:0] iRed, iGreen, iBlue;
output reg [4:0] oRed, oGreen, oBlue;
output oSRAM_WE_N;
output [17:0] oSRAM_ADDR;
inout [15:0] SRAM_DQ;
wire [15:0] avg_in, avg_out;
reg [15:0] temp;
//To make 2x2 blocking, discard LSB and address for 320x240
assign oSRAM_ADDR = {iVGA_Y[9:1], iVGA_X[9:1]};
//Read during first cycle, write during second
assign SRAM_DQ = iVGA_X[0] ? avg_out : 16'hzzzz;
//Time averager module
averager avg0 (
iRed,
iGreen,
iBlue,
avg_in,
avg_out
);
//Take input from SRAM during first cycle
assign avg_in = iVGA_X[0] ? temp : SRAM_DQ;
//Only write during first cycle if not a VGA blank
assign oSRAM_WE_N = (iVGA_X[0] && iVGA_BLANK) ? 1'b0 : 1'b1;
//update
always @(posedge iCLK) begin
oRed <= avg_out[14:10];
oGreen <= avg_out[9:5];
oBlue <= avg_out[4:0];
temp <= avg_out;
end
endmodule
| 7.672321 |
module Time_Cnt (
CLK,
RST,
TIME_SEC
);
input CLK;
input RST;
output reg [15:0] TIME_SEC = 0;
integer time_f = 0;
always @(negedge CLK) begin
if (RST) begin
time_f <= 0;
TIME_SEC <= 0;
end else begin
if (time_f < 999999) begin
time_f <= time_f + 1;
end else begin
time_f <= 0;
TIME_SEC <= TIME_SEC + 1;
end
end
end
endmodule
| 6.832748 |
module timecount2 (
input wire clock, // prescaler
input wire Prescale_EN, // DW 2005.06.21 Prescale Enable
input wire reset, // resetgen
input wire increment, // fsm
input wire setctzero, // fsm
input wire setctotwo, // fsm
output wire [3:0] counto // sum (arithmetik)
);
//tmrg default triplicate
//tmrg tmr_error false
reg [3:0] counto_i; // sum (arithmetik)
//triplication signals
wire [3:0] counto_iVoted = counto_i;
assign counto = counto_iVoted;
always @(posedge clock, negedge reset) // pos. flanke (clock), asynchroner reset
begin
if (reset == 1'b0) counto_i <= 4'b0000;
else
if (Prescale_EN == 1'b1) // DW 2005.06.21 Prescale Enable
begin
if (setctzero == 1'b1) // null setzen
counto_i <= 4'b0000;
else if (increment == 1'b1) // erhoehen
counto_i <= counto_iVoted + 1;
else if (setctotwo == 1'b1) // auf 2 setzen
counto_i <= 4'd2;
else counto_i <= counto_iVoted; // halten
end
end
endmodule
| 7.530242 |
module timeCounter (
input CLK,
input RST,
output reg [15:0] Time
);
integer counter = 0;
always @(posedge CLK) begin
if (!RST) begin
Time <= 0;
counter <= 0;
end else if ((counter + 1) == 100000000) begin
counter <= 0;
Time <= Time + 1;
end else counter <= counter + 1;
end
endmodule
| 6.991736 |
module timeDivider (
input clk,
input pause,
output reg clockOut
);
reg [23:0] buffer;
initial begin
buffer = 0;
clockOut = 0;
end
always @(posedge clk) begin
if (!pause) buffer <= buffer + 1;
clockOut <= &buffer;
end
endmodule
| 6.601571 |
module timed_monoflop (
input wire clock,
input wire enable,
input wire [PulseLengthWidth-1:0] pulselength,
input wire trigger,
output wire q
);
parameter PulseLengthWidth = 4;
reg load = 1'b0;
reg [PulseLengthWidth-1:0] Countdown = 0;
assign q = |Countdown;
always @(posedge trigger or posedge q) begin
if (q) load <= 0;
else if (enable) load <= 1;
end
always @(posedge clock) begin
if (load) Countdown[PulseLengthWidth-1:0] <= pulselength;
else if (q) Countdown[PulseLengthWidth-1:0] <= Countdown[PulseLengthWidth-1:0] - 1'h1;
end
endmodule
| 7.321023 |
module timed_tester #(
parameter WIDTH = 1
) (
input wire clk,
input wire [WIDTH-1:0] expected_value,
input wire [WIDTH-1:0] mask,
input wire tgen,
input wire [WIDTH-1:0] signal,
output reg [WIDTH-1:0] filtered_value,
output reg [ WIDTH:1] fail
);
always @(*)
if (tgen) filtered_value = signal;
else filtered_value = filtered_value;
wire [WIDTH:1] tst_fail;
assign tst_fail = {WIDTH{tgen}} & mask & (signal ^ expected_value);
generate
genvar i;
for (i = 1; i <= WIDTH; i = i + 1) begin : dummy
always @(posedge clk or posedge tst_fail[i])
if (tst_fail[i]) fail[i] <= 1'b1;
else fail[i] <= 1'b0;
end
endgenerate
endmodule
| 7.732413 |
module timegen (
clock,
reset,
reset_count,
fastwatch,
one_second,
one_minute
);
input clock, reset, reset_count, //Resets the timegen when you set a new time
fastwatch;
output one_second, one_minute;
reg [13:0] count;
reg one_second;
reg one_minute_reg;
reg one_minute;
always @(posedge clock or posedge reset) begin
if (reset) begin
count <= 14'b0;
one_minute_reg <= 0;
end else if (reset_count) begin
count <= 14'b0;
one_minute_reg <= 1'b0;
end else if (count[13:0] == 14'd15359) begin
count <= 14'b0;
one_minute_reg <= 1'b1;
end else begin
count <= count + 1'b1;
one_minute_reg <= 1'b0;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
one_second <= 1'b0;
end else if (reset_count) begin
one_second <= 1'b0;
end else if (count[7:0] == 8'd255) begin
one_second <= 1'b1;
end else begin
one_second <= 1'b0;
end
end
always @(*) begin
// If fastwatch asserted, one_second equals one_minute
if (fastwatch) one_minute = one_second;
else one_minute = one_minute_reg;
end
endmodule
| 6.549803 |
module timekeeper #(
parameter SR_TIME_HI = 0,
parameter SR_TIME_LO = 1,
parameter SR_TIME_CTRL = 2
) (
input clk,
input reset,
input pps,
input sync_in,
input strobe,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
output reg [63:0] vita_time,
output reg [63:0] vita_time_lastpps,
output reg sync_out
);
//////////////////////////////////////////////////////////////////////////
// timer settings for this module
//////////////////////////////////////////////////////////////////////////
wire [63:0] time_at_next_event;
wire set_time_pps, set_time_now, set_time_sync;
wire cmd_trigger;
setting_reg #(
.my_addr(SR_TIME_HI),
.width (32)
) sr_time_hi (
.clk(clk),
.rst(reset),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(time_at_next_event[63:32]),
.changed()
);
setting_reg #(
.my_addr(SR_TIME_LO),
.width (32)
) sr_time_lo (
.clk(clk),
.rst(reset),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(time_at_next_event[31:0]),
.changed()
);
setting_reg #(
.my_addr(SR_TIME_CTRL),
.width (3)
) sr_ctrl (
.clk(clk),
.rst(reset),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out({set_time_sync, set_time_pps, set_time_now}),
.changed(cmd_trigger)
);
//////////////////////////////////////////////////////////////////////////
// PPS edge detection logic
//////////////////////////////////////////////////////////////////////////
reg pps_del, pps_del2;
always @(posedge clk) {pps_del2, pps_del} <= {pps_del, pps};
wire pps_edge = !pps_del2 & pps_del;
//////////////////////////////////////////////////////////////////////////
// arm the trigger to latch a new time when the ctrl register is written
//////////////////////////////////////////////////////////////////////////
reg armed;
wire time_event = armed && ((set_time_now) || (set_time_pps && pps_edge) || (set_time_sync && sync_in));
always @(posedge clk) begin
if (reset) armed <= 1'b0;
else if (cmd_trigger) armed <= 1'b1;
else if (time_event) armed <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////
// vita time tracker - update every tick or when we get an "event"
//////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
sync_out <= 1'b0;
if (reset) begin
vita_time <= 64'h0;
end else begin
if (time_event) begin
sync_out <= 1'b1;
vita_time <= time_at_next_event;
end else if (strobe) begin
vita_time <= vita_time + 64'h1;
end
end
end
//////////////////////////////////////////////////////////////////////////
// track the time at last pps so host can detect the pps
//////////////////////////////////////////////////////////////////////////
always @(posedge clk)
if (reset) vita_time_lastpps <= 64'h0;
else if (pps_edge)
if (time_event) vita_time_lastpps <= time_at_next_event;
else vita_time_lastpps <= vita_time + 64'h1;
endmodule
| 6.937626 |
module timekeeper_legacy #(
parameter SR_TIME_HI = 0,
parameter SR_TIME_LO = 1,
parameter SR_TIME_CTRL = 2,
parameter INCREMENT = 64'h1
) (
input clk,
input reset,
input pps,
input sync_in,
input strobe,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
output reg [63:0] vita_time,
output reg [63:0] vita_time_lastpps,
output reg sync_out
);
//////////////////////////////////////////////////////////////////////////
// timer settings for this module
//////////////////////////////////////////////////////////////////////////
wire [63:0] time_at_next_event;
wire set_time_pps, set_time_now, set_time_sync;
wire cmd_trigger;
setting_reg #(
.my_addr(SR_TIME_HI),
.width (32)
) sr_time_hi (
.clk(clk),
.rst(reset),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(time_at_next_event[63:32]),
.changed()
);
setting_reg #(
.my_addr(SR_TIME_LO),
.width (32)
) sr_time_lo (
.clk(clk),
.rst(reset),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out(time_at_next_event[31:0]),
.changed()
);
setting_reg #(
.my_addr(SR_TIME_CTRL),
.width (3)
) sr_ctrl (
.clk(clk),
.rst(reset),
.strobe(set_stb),
.addr(set_addr),
.in(set_data),
.out({set_time_sync, set_time_pps, set_time_now}),
.changed(cmd_trigger)
);
//////////////////////////////////////////////////////////////////////////
// PPS edge detection logic
//////////////////////////////////////////////////////////////////////////
reg pps_del, pps_del2;
always @(posedge clk) {pps_del2, pps_del} <= {pps_del, pps};
wire pps_edge = !pps_del2 & pps_del;
//////////////////////////////////////////////////////////////////////////
// arm the trigger to latch a new time when the ctrl register is written
//////////////////////////////////////////////////////////////////////////
reg armed;
wire time_event = armed && ((set_time_now) || (set_time_pps && pps_edge) || (set_time_sync && sync_in));
always @(posedge clk) begin
if (reset) armed <= 1'b0;
else if (cmd_trigger) armed <= 1'b1;
else if (time_event) armed <= 1'b0;
end
//////////////////////////////////////////////////////////////////////////
// vita time tracker - update every tick or when we get an "event"
//////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
sync_out <= 1'b0;
if (reset) begin
vita_time <= 64'h0;
end else begin
if (time_event) begin
sync_out <= 1'b1;
vita_time <= time_at_next_event;
end else if (strobe) begin
vita_time <= vita_time + INCREMENT;
end
end
end
//////////////////////////////////////////////////////////////////////////
// track the time at last pps so host can detect the pps
//////////////////////////////////////////////////////////////////////////
always @(posedge clk)
if (reset) vita_time_lastpps <= 64'h0;
else if (pps_edge)
if (time_event) vita_time_lastpps <= time_at_next_event;
else vita_time_lastpps <= vita_time + INCREMENT;
endmodule
| 7.097456 |
module timem (
input clk,
input [`HASTI_ADDR_WIDTH-1:0] addr,
input read,
input write,
input [`HASTI_SIZE_WIDTH-1:0] size,
input [ `HASTI_BUS_WIDTH-1:0] wdata,
output [ `HASTI_BUS_WIDTH-1:0] rdata
);
reg [3:0] we;
always @(*) begin
if (write)
casez ({
size[2:0], addr[1:0]
})
5'b000_11: we = 4'b1000;
5'b000_10: we = 4'b0100;
5'b000_01: we = 4'b0010;
5'b000_00: we = 4'b0001;
5'b001_1?: we = 4'b1100;
5'b001_0?: we = 4'b0011;
5'b010_??: we = 4'b1111;
default: we = 4'b1111;
endcase
else we = 4'b0000;
end
v_rams_20c ram0 (
.clk (clk),
.we (we[0]),
.addr(addr[13:2]),
.din (wdata[7:0]),
.dout(rdata[7:0])
);
v_rams_21c ram1 (
.clk (clk),
.we (we[1]),
.addr(addr[13:2]),
.din (wdata[15:8]),
.dout(rdata[15:8])
);
v_rams_22c ram2 (
.clk (clk),
.we (we[2]),
.addr(addr[13:2]),
.din (wdata[23:16]),
.dout(rdata[23:16])
);
v_rams_23c ram3 (
.clk (clk),
.we (we[3]),
.addr(addr[13:2]),
.din (wdata[31:24]),
.dout(rdata[31:24])
);
endmodule
| 7.807872 |
module v_rams_20c (
clk,
we,
addr,
din,
dout
);
input clk;
input we;
input [11:0] addr;
input [7:0] din;
output [7:0] dout;
reg [7:0] ram [0:4095];
reg [7:0] dout;
initial begin
$readmemh("ram.data0", ram);
end
always @(posedge clk) begin
if (we) ram[addr] <= din;
dout <= ram[addr];
end
endmodule
| 6.604807 |
module v_rams_21c (
clk,
we,
addr,
din,
dout
);
input clk;
input we;
input [11:0] addr;
input [7:0] din;
output [7:0] dout;
reg [7:0] ram [0:4095];
reg [7:0] dout;
initial begin
$readmemh("ram.data1", ram);
end
always @(posedge clk) begin
if (we) ram[addr] <= din;
dout <= ram[addr];
end
endmodule
| 6.648021 |
module v_rams_22c (
clk,
we,
addr,
din,
dout
);
input clk;
input we;
input [11:0] addr;
input [7:0] din;
output [7:0] dout;
reg [7:0] ram [0:4095];
reg [7:0] dout;
initial begin
$readmemh("ram.data2", ram);
end
always @(posedge clk) begin
if (we) ram[addr] <= din;
dout <= ram[addr];
end
endmodule
| 6.518002 |
module v_rams_23c (
clk,
we,
addr,
din,
dout
);
input clk;
input we;
input [11:0] addr;
input [7:0] din;
output [7:0] dout;
reg [7:0] ram [0:4095];
reg [7:0] dout;
initial begin
$readmemh("ram.data3", ram);
end
always @(posedge clk) begin
if (we) ram[addr] <= din;
dout <= ram[addr];
end
endmodule
| 6.829322 |
module TimeMod (
input signed [17:0] l_audio_in,
input signed [17:0] r_audio_in,
input ready,
input clock,
input reset,
input [9:0] controls,
output signed [17:0] l_audio_out,
output signed [17:0] r_audio_out
);
//Echo variables
wire e_d;
wire e_u;
reg old_e_d = 0;
reg old_e_u = 0;
//Output of BRAM
wire signed [17:0] l_echo_out;
wire signed [17:0] r_echo_out;
//Echo signal being applied to input
reg signed [22:0] l_echo_effect = 0;
reg signed [22:0] r_echo_effect = 0;
//Contains either echo signal or all zeros, is added to input
wire signed [17:0] l_effect;
wire signed [17:0] r_effect;
//Signal being added to output of BRAM, for 'reverse' echo
wire signed [17:0] l_forward;
wire signed [17:0] r_forward;
//Final signal input into BRAM
reg signed [17:0] l_echo_in = 0;
reg signed [17:0] r_echo_in = 0;
//Echo attenuation factor
reg [4:0] echo_factor = 5'd14;
//Counters to implement delay
reg [13:0] e_count = 0;
reg [13:0] old_e_count = 0;
//Write enable for BRAM
reg wenable = 0;
//Control echo attenuation with L+R buttons
assign e_d = controls[9];
assign e_u = controls[8];
echo echo75ms (
.clka (clock),
.clkb (clock),
.dina ({l_echo_in, r_echo_in}),
.doutb({l_echo_out, r_echo_out}),
.addra(old_e_count),
.wea (wenable),
.addrb(e_count)
);
always @(posedge clock) begin
if (reset) begin
l_echo_in <= 0;
r_echo_in <= 0;
e_count <= 0;
wenable <= 0;
old_e_u <= 0;
old_e_d <= 0;
echo_factor <= 5'd14;
end else if (ready) begin
e_count <= e_count + 1;
old_e_count <= e_count;
l_echo_in <= (l_audio_in >>> 1) + l_effect;
r_echo_in <= (r_audio_in >>> 1) + r_effect;
wenable <= 1;
l_echo_effect <= (l_echo_out * echo_factor);
r_echo_effect <= (r_echo_out * echo_factor);
end else begin
if (e_u & ~old_e_u & echo_factor != 5'd22) echo_factor <= echo_factor + 1;
if (e_d & ~old_e_d & echo_factor != 5'd0) echo_factor <= echo_factor - 1;
old_e_u <= e_u;
old_e_d <= e_d;
wenable <= 0;
end
end
assign l_effect = controls[0] ? (l_echo_effect[22:5]) : (18'b00_0000_0000_0000_0000);
assign r_effect = controls[0] ? (r_echo_effect[22:5]) : (18'b00_0000_0000_0000_0000);
assign l_forward = controls[1] ? (l_echo_in >>> 1) : (18'b00_0000_0000_0000_0000);
assign r_forward = controls[1] ? (r_echo_in >>> 1) : (18'b00_0000_0000_0000_0000);
assign l_audio_out = l_echo_out + l_forward;
assign r_audio_out = r_echo_out + r_forward;
endmodule
| 6.907819 |
module timeofDayReceiver (
input Clock,
input Reset,
input [ 7:0] EventStream,
output reg [ 9:0] tooManyCount = 0,
output reg [ 9:0] tooFewCount = 0,
output reg [ 9:0] outOfSeqCount = 0,
output wire [63:0] TimeStamp
);
localparam SECONDS_WIDTH = 32;
localparam TICKS_WIDTH = 32;
reg [SECONDS_WIDTH-1:0] tsSeconds = 0, expectSeconds = 0;
reg [TICKS_WIDTH-1:0] tsTicks = 0;
reg tsValid = 0;
assign TimeStamp = {tsSeconds, tsTicks};
localparam EVCODE_SHIFT_ZERO = 8'h70;
localparam EVCODE_SHIFT_ONE = 8'h71;
localparam EVCODE_SECONDS_MARKER = 8'h7D;
reg [ SECONDS_WIDTH-1:0] shiftReg;
reg [$clog2(SECONDS_WIDTH)-1:0] bitsLeft = SECONDS_WIDTH - 1;
reg enoughBits = 0, tooManyBits = 0;
always @(posedge Clock) begin
if (Reset) begin
tsSeconds <= 0;
tsTicks <= 0;
tsValid <= 0;
end else if (EventStream == EVCODE_SECONDS_MARKER) begin
if (!enoughBits) tooFewCount <= tooFewCount + 1;
if (tooManyBits) tooManyCount <= tooManyCount + 1;
if (enoughBits && !tooManyBits) begin
expectSeconds <= shiftReg + 1;
if (shiftReg == expectSeconds) begin
tsSeconds <= shiftReg;
tsValid <= 1;
end else begin
outOfSeqCount <= outOfSeqCount + 1;
if (tsValid) begin
tsSeconds <= tsSeconds + 1;
end
end
end else if (tsValid) begin
tsSeconds <= tsSeconds + 1;
end
tsTicks <= 0;
bitsLeft <= SECONDS_WIDTH - 1;
enoughBits <= 0;
tooManyBits <= 0;
end else begin
if ((EventStream == EVCODE_SHIFT_ZERO) || (EventStream == EVCODE_SHIFT_ONE)) begin
// Shift in another bit of upcoming seconds
bitsLeft <= bitsLeft - 1;
if (enoughBits) tooManyBits <= 1;
if (bitsLeft == 0) enoughBits <= 1;
shiftReg <= {shiftReg[SECONDS_WIDTH-2:0], EventStream[0]};
end
if (tsTicks[TICKS_WIDTH-1] == 0) begin
tsTicks <= tsTicks + 1;
end else begin
tsValid <= 0;
end
end
end
endmodule
| 6.724339 |
module timeout (
input wire clk,
input wire [7:0] Enable,
input wire Enable_Init_or_Resp,
input wire reset,
input wire auth_msg_ready,
input wire [31:0] current_timeout,
output wire Error_Busy
);
reg [31:0] Timeout_counter = 0;
reg Error_Busy_temp = 0;
always @(posedge clk) begin
if (auth_msg_ready | reset) begin
Timeout_counter = 0;
end else if (Enable | Enable_Init_or_Resp) begin
Timeout_counter = Timeout_counter + 1;
end else begin
Timeout_counter = 0;
end
if (Timeout_counter >= current_timeout) begin
Error_Busy_temp <= 1'b1;
end else begin
Error_Busy_temp <= 1'b0;
end
end
assign Error_Busy = Error_Busy_temp;
endmodule
| 6.788577 |
module connection_outTime_inspector (
reset,
clk,
idx_agingTb,
data_agingTb,
rdValid_agingTb,
wrValid_agingTb,
ctx_agingTb,
agingInfo_valid,
agingInfo,
cur_timestamp
);
/* width or depth or words info of signals
*/
parameter w_agingInfo = 16, // width of aging info to build-in event generator;
w_agingTb = 17, // width of aging table;
d_agingTb = 3, // depth of aging table;
w_timestamp = 16, // width of timestamp;
/* bit(loaction) of each component in x(table/reg) */
b_valid_agingTb = 16, // last bit of valid in aging table;
b_ts_agingTb = 0, // last bit of timestamp in agingTb;
/* constant/static parameter */
INCREASE_IDX_AGINGTB = 3'd1, // check connetion one by one;
INTERVAL_AGING = 16'd100; // one interval is 100ms, so '100' represends 10 seconds;
input clk;
input reset;
output reg [d_agingTb-1:0] idx_agingTb;
output reg [w_agingTb-1:0] data_agingTb;
output reg rdValid_agingTb;
output reg wrValid_agingTb;
input [w_agingTb-1:0] ctx_agingTb;
output reg agingInfo_valid;
output reg [w_agingInfo-1:0] agingInfo;
input [w_timestamp-1:0] cur_timestamp;
/*************************************************************************************/
/* varialbe declaration */
/* gen agingInfo state machine */
reg [3:0] state_aging;
parameter IDLE_S = 4'd0, WAIT_RAM_1_S = 4'd1, WAIT_RAM_2_S = 4'd2, READ_AGINGTB_S = 4'd3;
/*************************************************************************************/
/* state machine declaration
* this state machine is used to read agingTb;
*
* Learning makes me happy, except reading this stupid code.
*/
always @(posedge clk or negedge reset) begin
if (!reset) begin
idx_agingTb <= {d_agingTb{1'b0}};
rdValid_agingTb <= 1'b0;
wrValid_agingTb <= 1'b0;
data_agingTb <= {w_agingTb{1'b0}};
agingInfo_valid <= 1'b0;
agingInfo <= {w_agingInfo{1'b0}};
state_aging <= IDLE_S;
end else begin
case (state_aging)
IDLE_S: begin
wrValid_agingTb <= 1'b0;
agingInfo_valid <= 1'b0;
/** initialization, start from index of '1', because '0' is empty */
if (idx_agingTb == {d_agingTb{1'b1}}) idx_agingTb <= INCREASE_IDX_AGINGTB;
else idx_agingTb <= idx_agingTb + INCREASE_IDX_AGINGTB;
rdValid_agingTb <= 1'b1;
state_aging <= WAIT_RAM_1_S;
end
WAIT_RAM_1_S: begin
rdValid_agingTb <= 1'b0;
state_aging <= WAIT_RAM_2_S;
end
WAIT_RAM_2_S: begin
state_aging <= READ_AGINGTB_S;
end
READ_AGINGTB_S: begin
if (ctx_agingTb[b_valid_agingTb] == 1'b1) begin
if ((ctx_agingTb[w_timestamp-1:0] + INTERVAL_AGING) == cur_timestamp) begin
/** out time */
wrValid_agingTb <= 1'b1;
data_agingTb <= {w_agingTb{1'b0}};
agingInfo_valid <= 1'b1;
agingInfo <= idx_agingTb;
end else begin
wrValid_agingTb <= 1'b0;
agingInfo_valid <= 1'b0;
end
end
state_aging <= IDLE_S;
end
default: begin
state_aging <= IDLE_S;
end
endcase
end
end
endmodule
| 6.890324 |
module TimePulGenerator (
CLK,
RST,
SW,
CP,
Sublevel
);
input CLK, RST;
input [4:0] SW;
output CP;
output reg [3:0] Sublevel;
reg [15:0] Count;
reg [15:0] CountMAX;
reg div_CLK;
//根据表格来确定计数器和Sublevel
always @(posedge CLK) begin
case (SW)
5'b00000: begin
CountMAX = 16'd7324;
Sublevel = 4'b1011;
end
5'b00001: begin
CountMAX = 16'd3662;
Sublevel = 4'b1011;
end
5'b00010: begin
CountMAX = 16'd1831;
Sublevel = 4'b1011;
end
5'b00011: begin
CountMAX = 16'd1221;
Sublevel = 4'b1011;
end
5'b00100: begin
CountMAX = 16'd916;
Sublevel = 4'b1011;
end
5'b00101: begin
CountMAX = 16'd1465;
Sublevel = 4'b1010;
end
5'b00110: begin
CountMAX = 16'd977;
Sublevel = 4'b1010;
end
5'b00111: begin
CountMAX = 16'd732;
Sublevel = 4'b1010;
end
5'b01000: begin
CountMAX = 16'd586;
Sublevel = 4'b1010;
end
5'b01001: begin
CountMAX = 16'd488;
Sublevel = 4'b1010;
end
5'b01010: begin
CountMAX = 16'd837;
Sublevel = 4'b1001;
end
5'b01011: begin
CountMAX = 16'd732;
Sublevel = 4'b1001;
end
5'b01100: begin
CountMAX = 16'd651;
Sublevel = 4'b1001;
end
5'b01101: begin
CountMAX = 16'd586;
Sublevel = 4'b1001;
end
5'b01110: begin
CountMAX = 16'd533;
Sublevel = 4'b1001;
end
5'b01111: begin
CountMAX = 16'd977;
Sublevel = 4'b1000;
end
5'b10000: begin
CountMAX = 16'd901;
Sublevel = 4'b1000;
end
5'b10001: begin
CountMAX = 16'd837;
Sublevel = 4'b1000;
end
5'b10010: begin
CountMAX = 16'd781;
Sublevel = 4'b1000;
end
5'b10011: begin
CountMAX = 16'd732;
Sublevel = 4'b1000;
end
5'b10100: begin
CountMAX = 16'd1397;
Sublevel = 4'b0111;
end
5'b10101: begin
CountMAX = 16'd1234;
Sublevel = 4'b0111;
end
5'b10110: begin
CountMAX = 16'd1172;
Sublevel = 4'b0111;
end
5'b10111: begin
CountMAX = 16'd1116;
Sublevel = 4'b0111;
end
5'b11000: begin
CountMAX = 16'd1065;
Sublevel = 4'b0111;
end
5'b11001: begin
CountMAX = 16'd1019;
Sublevel = 4'b0111;
end
5'b11010: begin
CountMAX = 16'd977;
Sublevel = 4'b0111;
end
5'b11011: begin
CountMAX = 16'd901;
Sublevel = 4'b0111;
end
5'b11100: begin
CountMAX = 16'd868;
Sublevel = 4'b0111;
end
5'b11101: begin
CountMAX = 16'd837;
Sublevel = 4'b0111;
end
5'b11110: begin
CountMAX = 16'd808;
Sublevel = 4'b0111;
end
5'b11111: begin
CountMAX = 16'd781;
Sublevel = 4'b0111;
end
default: begin
CountMAX = 16'd7324;
Sublevel = 4'b1011;
end
endcase
end
//根据计数器的值进行分频，产生分频信号
always @(posedge CLK or negedge RST) begin
if (!RST) begin
Count <= 0;
div_CLK <= 0;
end else if (Count < CountMAX) Count <= Count + 1;
else begin
Count <= 0;
div_CLK = ~div_CLK;
end
end
assign CP = div_CLK;
endmodule
| 7.221055 |
module timepulse #(
parameter CLK_PER_NS = 40,
parameter PULSE_PER_NS = 5120
) (
/* clock and reset */
input clk_i,
input rst_i,
/* output */
output tp_o
);
`define MAX_COUNT (PULSE_PER_NS/CLK_PER_NS)
`define MAX_COUNT_SIZE ($clog2(`MAX_COUNT))
/* Display parameters in simulation */
initial begin
$display("CLK_PER_NS : %d", CLK_PER_NS);
$display("PULSE_PER_NS : %d", PULSE_PER_NS);
$display("MAX_COUNT : %x", `MAX_COUNT);
$display("MAX_COUNT_SIZE : %x", `MAX_COUNT_SIZE);
end
reg [`MAX_COUNT_SIZE-1:0] counter = 0;
assign tp_o = (counter == 0);
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
counter <= 0;
end else begin
if (counter < `MAX_COUNT) begin
counter <= counter + 1'b1;
end else begin
counter <= 0;
end
end
end
/*********************/
/* Yosys formal part */
/*********************/
`ifdef FORMAL
reg past_valid;
reg [7:0] count_tp_o = 0;
initial begin
past_valid <= 1'b0;
assume (rst_i);
end
always @(posedge clk_i) begin
past_valid <= 1'b1;
if (past_valid) assume (!rst_i);
if (tp_o) count_tp_o <= count_tp_o + 1'b1;
cover (count_tp_o == 2);
/* tp_o must be 1 cycle length */
if (tp_o == 1'b1 && past_valid) assert ($past(tp_o, 1) == !tp_o);
/* counter should increase by 1 */
if ((counter != 0) && (counter != (`MAX_COUNT - 1)) && past_valid && !rst_i)
assert ($past(counter) + 1'b1 == counter);
if (($past(counter) == (`MAX_COUNT - 1)) && past_valid && !rst_i && !$past(rst_i))
assert (tp_o);
if (($past(counter) != (`MAX_COUNT - 1)) && past_valid && !rst_i && !$past(rst_i))
assert (!tp_o);
cover (tp_o);
cover (counter == (`MAX_COUNT - 1));
end
`endif
endmodule
| 7.830303 |
module Timer_tb;
parameter HALF_PERIOD = 0.5;
reg load, clr, clk, en;
reg [3:0] data;
wire [3:0] sec_ones, sec_tens, mins;
wire zero;
always #HALF_PERIOD clk = ~clk;
Timer timer (
load,
clr,
clk,
en,
data,
sec_ones,
sec_tens,
mins,
zero
);
initial begin
// setup
clk = 0;
$dumpfile("Timer.vcd");
$dumpvars(0, Timer_tb);
// reset
clr = 0;
load = 1;
en = 1;
data = 4'd5;
#3;
// mudando tempo para 5:43
clr = 1;
load = 0;
en = 1;
#2; // tempo = 0:05
data = 4'd4;
#2; // tempo = 0:54
data = 4'd3;
#2; // tempo = 5:43
// contagem com transição de dezenas de segundos
clr = 1;
load = 1;
en = 0;
#10;
// pausa
clr = 1;
load = 1;
en = 1;
#3;
// reset
clr = 0;
load = 1;
en = 0;
#2;
// mudando tempo para 1:12
clr = 1;
load = 0;
en = 1;
data = 4'd1;
#2; // tempo = 0:11
data = 4'd3;
#2; // tempo = 1:13
// contagem com transição de minutos
clr = 1;
load = 1;
en = 0;
#30;
$finish();
end
endmodule
| 6.642052 |
module Timer (
input wire reset,
input wire count,
input wire clk,
input wire signed [8:0] adder,
output wire [3:0] seconds0,
output wire [3:0] seconds1,
output wire [3:0] minutes0
);
reg [8:0] seconds;
assign minutes0 = seconds / 60;
assign seconds1 = (seconds % 60) / 10;
assign seconds0 = (seconds % 60) % 10;
initial begin
seconds = 0'b0;
end
/* Contagem do dígito s0, com o clock do input */
/* O adder pode ser settado de forma assíncrona */
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) seconds = 9'b0; // Zera o timer de acordo com a entrada de reset
else if (count == 1'b1) seconds = seconds + adder;
end
/* Passa o timer quando o adder de forma assíncrona muda para algo diferente de 1 */
always @(adder) begin
// So adiciona de forma assíncrona quando é passado um adder customizado
if (adder != 1'b1) seconds = seconds + adder;
end
endmodule
| 6.729771 |
module TIMER32 (
input wire clk,
input wire rst,
output reg [31:0] TMR,
input wire [31:0] PRE,
input wire [31:0] TMRCMP,
output reg TMROV,
input wire TMROVCLR,
input wire TMREN
);
reg [31:0] clkdiv;
wire timer_clk = (clkdiv == PRE);
wire tmrov = (TMR == TMRCMP);
// Prescalar
always @(posedge clk or posedge rst) begin
if (rst) clkdiv <= 32'd0;
else if (timer_clk) clkdiv <= 32'd0;
else if (TMREN) clkdiv <= clkdiv + 32'd1;
end
// Timer
always @(posedge clk or posedge rst) begin
if (rst) TMR <= 32'd0;
else if (tmrov) TMR <= 32'd0;
else if (timer_clk) TMR <= TMR + 32'd1;
end
always @(posedge clk or posedge rst) begin
if (rst) TMROV <= 1'd0;
else if (TMROVCLR) TMROV <= 1'd0;
else if (tmrov) TMROV <= 1'd1;
end
endmodule
| 8.011137 |
module timer_8253 (
input CS,
input WR,
input [1:0] addr,
input [7:0] din,
output wire [7:0] dout,
input CLK_25,
input clk, // cpu CLK
output out0,
output out2
);
reg [8:0] rclk = 0; // rclk[8] oscillates at 1193181.8181... Hz
reg [1:0] cclk = 0;
always @(posedge CLK_25) begin
if (rclk[7:0] < 8'd208) rclk <= rclk + 21;
else rclk <= rclk + 57;
end
always @(posedge clk) begin
cclk <= {cclk[0], rclk[8]};
end
wire a0 = addr == 0;
wire a2 = addr == 2;
wire a3 = addr == 3;
wire cmd0 = a3 && din[7:6] == 0;
wire cmd2 = a3 && din[7:6] == 2;
wire [7:0] dout0;
wire [7:0] dout2;
wire [7:0] mode0;
wire [7:0] mode2;
counter counter0 (
.CS (CS && (a0 || cmd0)),
.WR (WR),
.clk (clk),
.cmd (cmd0),
.din (din),
.dout(dout0),
.mode(mode0),
.CE (cclk)
);
counter counter2 (
.CS (CS && (a2 || cmd2)),
.WR (WR),
.clk (clk),
.cmd (cmd2),
.din (din),
.dout(dout2),
.mode(mode2),
.CE (cclk)
);
assign out0 = mode0[7];
assign out2 = mode2[7];
assign dout = a0 ? dout0 : dout2;
endmodule
| 6.56733 |
module TimerEcclesiaMorain (
input CLOCK_50,
input FPGA_RESET_N,
input [9:0] SW,
input [3:0] KEY,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [9:0] LEDR
);
// ==============================================
// CLOCK
// ==============================================
// wire clk_1Hz;
//clk_divider clk_div(CLOCK_50, clk_1Hz);
// ==============================================
// ==============================================
// Sequence Detector
// ==============================================
wire [3:0] state;
wire [3:0] ones_Secs, tens_Secs, ones_Mins, tens_Mins;
//
seq_detector seqdet (
.clock (CLOCK_50),
.reset (FPGA_RESET_N),
.input_0 (key0_press),
.input_1 (key1_press),
.SW (SW),
.y (LEDR[0]),
.onesSecDisp(ones_Secs),
.tensSecDisp(tens_Secs),
.onesMinDisp(ones_Mins),
.tensMinDisp(tens_Mins),
.state (state)
);
// ==============================================
// ==============================================
// Key Press 0
// ==============================================
wire key0_press;
//
key_press key0p (
.clock (CLOCK_50),
.key (KEY[0]),
.key_press(key0_press)
);
// ==============================================
// ==============================================
// Key Press 1
// ==============================================
wire key1_press;
//
key_press key1p (
.clock (CLOCK_50),
.key (KEY[1]),
.key_press(key1_press)
);
// ==============================================
//seq_detector seqdet(CLOCK_50, ~FPGA_RESET_N, key0_press, key1_press, LEDR[0], state);
// Display the current state
dec2_7seg disp4 (
1'b0,
HEX4
);
dec2_7seg disp (
state,
HEX5
);
//Display Seconds and Minutes
dec2_7seg disp0 (
ones_Secs,
HEX0
);
dec2_7seg disp1 (
tens_Secs,
HEX1
);
dec2_7seg disp2 (
ones_Mins,
HEX2
);
dec2_7seg disp3 (
tens_Mins,
HEX3
);
// Show the status of keys
assign LEDR[1] = ~FPGA_RESET_N;
assign LEDR[2] = KEY[0];
assign LEDR[3] = KEY[1];
// ==============================================
endmodule
| 7.331134 |
module TimerInput_tb;
reg [9:0] kbd;
reg enn, clk;
wire [3:0] D;
wire loadn, pgt_1Hz;
always #5 clk = ~clk;
TimerInput DUT (
kbd,
enn,
clk,
D,
loadn,
pgt_1Hz
);
initial begin
clk = 0;
$dumpfile("TimerInput.vcd");
$dumpvars(0, TimerInput_tb);
enn = 1;
kbd = 10'b0000000000;
#1000;
enn = 1;
kbd = 10'b0000000010;
#1000;
enn = 1;
kbd = 10'b0010000000;
#1000;
enn = 1;
kbd = 10'b0010000010;
#1000;
enn = 0;
kbd = 10'b0000000000;
#1000;
enn = 0;
kbd = 10'b0010000010;
#1000;
enn = 0;
kbd = 10'b0000000000;
#1000;
enn = 0;
kbd = 10'b0010000000;
#1000;
enn = 0;
kbd = 10'b0000000000;
#1000;
enn = 0;
kbd = 10'b0000000010;
#1000;
enn = 0;
kbd = 10'b0000000000;
#1000;
enn = 1;
kbd = 10'b0000000010;
#1000;
enn = 1;
kbd = 10'b0000000000;
#5000;
$finish();
end
endmodule
| 7.167681 |
module TimerInput (
input wire [9:0] kbd,
input wire enn,
clk,
output wire [3:0] D,
output wire loadn,
pgt_1Hz
);
wire clk1hz, delcount;
KeyboardCoder coder (
kbd,
enn,
D,
loadn
);
FrequencyDelayer_1hz freqdel (
clk,
clk1hz
);
Counter0_7 counter (
clk,
loadn,
delcount
);
Mux2x1 MUX (
delcount,
clk1hz,
enn,
pgt_1Hz
);
endmodule
| 7.448537 |
module timer1 (
enable,
clk,
reset,
setbit,
curr_state
);
input enable, clk, reset;
input [1:0] curr_state;
wire d0, d1;
reg [1:0] q;
output reg [3:0] setbit;
assign d0 = ~q[0];
assign d1 = q[0] ^ q[1];
always @(posedge clk or negedge reset) begin
if (~reset) begin
q = 2'b00;
end else begin
if (enable) begin
q[0] = d0;
q[1] = d1;
end else begin
q[0] = 1'b0;
q[1] = 1'b0;
end
end
end
always @(posedge clk) begin
case (curr_state)
2'b00: setbit = 4'h8;
2'b01: setbit = 4'h4;
2'b10: setbit = 4'h2;
2'b11: setbit = 4'h1;
endcase
end
/*
always@(posedge clk) begin
if(q[0] & q[1]) begin
setbit = 4'b1000;
end
else begin
setbit = 4'b0000;
end
end
*/
endmodule
| 6.616152 |
module timer4 (
enable,
clk,
reset,
setbit
);
input enable, clk, reset;
wire d0, d1;
reg [1:0] q;
output reg [3:0] setbit;
assign d0 = ~q[0];
assign d1 = q[0] ^ q[1];
always @(posedge clk or negedge reset) begin
if (~reset) begin
q = 2'b00;
end else begin
if (enable) begin
q[0] = d0;
q[1] = d1;
end else begin
q[0] = 1'b0;
q[1] = 1'b0;
end
end
end
always @(posedge clk) begin
if (q[0] & q[1]) begin
setbit = 4'b0001;
end else begin
setbit = 4'b0000;
end
end
endmodule
| 6.547903 |
module timer_1_32_l (
input clk,
resetn,
enable,
output time_up
);
reg [25:0] count;
wire [ 9:0] dividend;
assign dividend = 10'd32;
wire [25:0] initial_value, check_value;
assign initial_value = 26'd50000000;
assign check_value = initial_value / dividend;
always @(posedge clk) begin
if (!resetn) count <= check_value;
else if (enable) begin
if (count == 26'd0) count <= check_value;
else count <= count - 1'b1;
end
end
assign time_up = ((count >= 26'd0) & (count <= check_value / 2)) ? 1 : 0;
endmodule
| 6.71649 |
module timer_s (
input clk,
resetn,
enable,
input [25:0] dividend,
output time_up
);
reg [25:0] count;
wire [25:0] check_value;
assign check_value = 26'd50000000 / dividend;
always @(posedge clk) begin
if (!resetn) count <= check_value;
else if (enable) begin
if (count == 26'd0) count <= check_value;
else count <= count - 1'b1;
end
end
assign time_up = (count == 26'd0) ? 1 : 0;
endmodule
| 6.799927 |
module timers_tb;
reg enable, clk, reset;
wire [3:0] setbit1, setbit2, setbit3, setbit4;
timer1 t1 (
enable,
clk,
reset,
setbit1
);
timer2 t2 (
enable,
clk,
reset,
setbit2
);
timer3 t3 (
enable,
clk,
reset,
setbit3
);
timer4 t4 (
enable,
clk,
reset,
setbit4
);
always #5 clk = ~clk;
initial begin
clk = 1'b0;
reset = 1'b1;
#2 reset = 1'b0;
#5 reset = 1'b1;
#5 enable = 1'b1;
#50 enable = 1'b0;
#100 $finish;
end
endmodule
| 6.860182 |
module timers_top ( /*AUTOARG*/
// Outputs
ANODE,
CATHODE,
// Inputs
CLK_IN,
RESET_IN
);
input CLK_IN;
input RESET_IN;
output [3:0] ANODE;
output [7:0] CATHODE;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire CLK_OUT; // From syscon of system_controller.v
wire RESET_OUT; // From syscon of system_controller.v
// End of automatics
/*AUTOREG*/
wire [7:0] port_id;
wire [7:0] out_port;
wire [7:0] in_port;
wire [7:0] timer_data_out;
wire [7:0] display_data_out;
wire [3:0] ANODE;
wire [7:0] CATHODE;
//
// System Controller
//
system_controller syscon ( /*AUTOINST*/
// Outputs
.CLK_OUT (CLK_OUT),
.RESET_OUT(RESET_OUT),
// Inputs
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN)
);
//
// Picoblaze CPU
//
cpu Picoblaze (
// Outputs
.port_id (port_id[7:0]),
.out_port (out_port[7:0]),
.write_strobe (write_strobe),
.read_strobe (read_strobe),
.interrupt_ack(interrupt_ack),
// Inputs
.clk (CLK_OUT),
.in_port (in_port[7:0]),
.interrupt (interrupt),
.kcpsm6_sleep (kcpsm6_sleep),
.cpu_reset (RESET_OUT)
);
assign in_port = timer_data_out | display_data_out;
assign interrupt = timer_irq;
assign kcpsm6_sleep = 0;
//
// Display
//
pb_display #(
.BASE_ADDRESS(8'h10)
) seven_segments (
// Outputs
.data_out(display_data_out),
.anode(ANODE),
.cathode(CATHODE),
// Inputs
.clk(CLK_OUT),
.reset(RESET_OUT),
.port_id(port_id),
.data_in(out_port),
.read_strobe(read_strobe),
.write_strobe(write_strobe)
);
pb_timer timer0 (
// Outputs
.data_out(timer_data_out),
.interrupt(timer_irq),
// Inputs
.clk(CLK_OUT),
.reset(RESET_OUT),
.port_id(port_id),
.data_in(out_port),
.read_strobe(read_strobe),
.write_strobe(write_strobe),
.watchdog(1'b0)
);
endmodule
| 6.610104 |
module timer_1sec (
output tick,
input reset,
clk,
en
);
localparam CLOCK_FREQ = 50000000 / 4;
reg [26:0] timer_reg;
wire [26:0] timer_next;
//registors
always @(posedge clk, posedge reset)
if (reset) timer_reg <= 0;
else timer_reg <= timer_next;
//next state logic
assign timer_next = (en) ? ((tick) ? 0 : timer_reg + 1) : timer_reg;
//output logic
assign tick = (timer_reg == CLOCK_FREQ);
endmodule
| 6.552668 |
module timer_1sec_fsm (
output reg timer_up_tick,
input reset,
clk,
start
);
localparam [1:0] paused = 2'b00, running = 2'b01, time_up = 2'b10;
reg en, r_set;
wire tick;
timer_1sec timer_unit (
.tick(tick),
.clk(clk),
.reset(r_set),
.en(en)
);
reg [1:0] state_reg, state_next;
//registers
always @(posedge clk, posedge reset)
if (reset) state_reg <= paused;
else state_reg <= state_next;
//next state and output logic
always @* begin
state_next = state_reg;
en = 1'b0;
r_set = 1'b0;
timer_up_tick = 1'b0;
case (state_reg)
paused: begin
r_set = 1'b1;
if (start) state_next = running;
else state_next = paused;
end
running: begin
en = 1'b1;
if (tick) state_next = time_up;
else state_next = running;
end
time_up: begin
timer_up_tick = 1'b1;
state_next = paused;
end
default: state_next = paused;
endcase
end
endmodule
| 7.906064 |
module Timer_adder_testbench;
/* Inicialização das variáveis de input */
reg count_tb, reset_tb, clk_tb;
reg signed [8:0] adder_tb;
/* Inicialização da variáveis de output */
wire [3:0] seconds0_tb, seconds1_tb, minutes0_tb;
/* Inicialização do módulo a ser testado */
Timer UUT (
.reset(reset_tb),
.count(count_tb),
.clk(clk_tb),
.adder(adder_tb),
.seconds0(seconds0_tb),
.seconds1(seconds1_tb),
.minutes0(minutes0_tb)
);
initial begin
/* Condições inciais */
clk_tb = 1'b0;
reset_tb = 1'b0;
count_tb = 1'b1;
adder_tb = 9'b1;
$monitor("%d : %d %d", minutes0_tb, seconds1_tb, seconds0_tb);
/* Mesmo sem clock, deve mudar o valor */
adder_tb = 9'd30;
#100
if (seconds1_tb == 0) $display("Erro, o valor não mudar");
else $display("Teste encerrado com sucesso");
#100 $stop;
end
endmodule
| 7.185424 |
module timer_apb #(
parameter NUM_TIMER = 2
, FREQUENCY = 1_000_000 // frequency of clk_timer
) (
input wire PRESETn
, input wire PCLK
, input wire PSEL
, input wire PENABLE
, input wire [ 31:0] PADDR
, input wire PWRITE
, output reg [ 31:0] PRDATA
, input wire [ 31:0] PWDATA
, output wire [NUM_TIMER-1:0] interrupt // active-high interrupt
, output wire [NUM_TIMER-1:0] interruptb // active-low interrupt
, input wire clk_timer
);
//------------------------------------
assign interruptb = ~interrupt; // active-low interrupt
//------------------------------------
wire [NUM_TIMER-1:0] T_RE;
wire [NUM_TIMER-1:0] T_WE;
wire [ 31:0] T_ADDR;
wire [ 31:0] T_DW;
wire [ 31:0] T_DR [0:NUM_TIMER-1];
//------------------------------------
wire [ 31:0] T_DR0 = T_DR[0];
wire [ 31:0] T_DR1 = T_DR[1];
//------------------------------------
generate
genvar idx;
for (idx = 0; idx < NUM_TIMER; idx = idx + 1) begin : BLK_IDX
assign T_RE[idx] = (T_ADDR[7:4] == idx[3:0]) ? ~PWRITE & PSEL & PENABLE & PRESETn : 1'b0;
assign T_WE[idx] = (T_ADDR[7:4] == idx[3:0]) ? PWRITE & PSEL & PENABLE & PRESETn : 1'b0;
end
endgenerate
//------------------------------------
integer idy;
always @(*) begin
PRDATA <= 32'h0;
for (idy = 0; idy < NUM_TIMER; idy = idy + 1) begin
if (T_ADDR[7:4] == idy[3:0]) begin
PRDATA <= T_DR[idy];
end
end // for
end // always
//------------------------------------
assign T_ADDR = PADDR;
assign T_DW = PWDATA;
//------------------------------------
generate
genvar idz;
for (idz = 0; idz < NUM_TIMER; idz = idz + 1) begin : BLK_IDZ
timer_tick #(
.FREQUENCY(FREQUENCY)
) u_timer (
.clk_i (PCLK)
, .rstb_i (PRESETn)
, .re_i (T_RE[idz])
, .we_i (T_WE[idz])
, .addr_i (T_ADDR[3:2])
, .data_i (T_DW)
, .data_o (T_DR[idz])
, .intr_o (interrupt[idz])
, .clk_timer_i(clk_timer)
);
end
endgenerate
endmodule
| 6.974668 |
module timer_cntrl (
input wire clk_i,
input wire rstn_i,
input wire cfg_start_i,
input wire cfg_stop_i,
input wire cfg_rst_i,
input wire cfg_update_i,
input wire cfg_arm_i,
output reg ctrl_cnt_upd_o,
output reg ctrl_all_upd_o,
output wire ctrl_active_o,
output reg ctrl_rst_o,
output wire ctrl_arm_o,
input wire cnt_update_i,
output wire [7:0] status_o
);
reg r_active;
reg r_pending;
assign ctrl_arm_o = cfg_arm_i;
assign status_o = {6'h00, r_pending};
assign ctrl_active_o = r_active;
always @(*) begin : proc_sm
if (cfg_start_i && !r_active) begin
ctrl_rst_o = 1'b1;
ctrl_cnt_upd_o = 1'b1;
ctrl_all_upd_o = 1'b1;
end else begin
ctrl_rst_o = cfg_rst_i;
ctrl_cnt_upd_o = cfg_update_i;
ctrl_all_upd_o = cnt_update_i;
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_active
if (~rstn_i) begin
r_active <= 0;
r_pending <= 0;
end else begin
if (cfg_start_i) r_active <= 1;
else if (cfg_stop_i) r_active <= 0;
if (cnt_update_i && !cfg_update_i) r_pending <= 0;
else if (cfg_update_i) r_pending <= 1;
end
end
endmodule
| 6.747358 |
module timer_control_level2 (
keypad,
enable_n,
clock_100Hz,
D,
load_n,
pgt_1Hz
);
input [9:0] keypad;
input enable_n, clock_100Hz;
output wire [3:0] D;
output wire load_n, pgt_1Hz;
wire clock_1Hz, data_valid, delayed_data_valid;
priority_encoder encoder (
.keypad(keypad),
.enable_n(enable_n),
.BCD_out(D),
.data_valid(data_valid)
);
frequency_divide_by_100 divide (
.in_clock (clock_100Hz),
.out_clock(clock_1Hz)
);
debounce_delay delay (
.clock(clock_100Hz),
.clear(data_valid),
.edge_out(delayed_data_valid)
);
mux_2x1 mux (
.i0(delayed_data_valid),
.i1(clock_1Hz),
.select(enable_n),
.F(pgt_1Hz)
);
assign load_n = ~data_valid;
endmodule
| 6.879247 |
module timer_control_level2_tb;
reg [9:0] keypad_tb;
reg enable_n_tb, clock_100Hz_tb;
wire [3:0] D_tb;
wire load_n_tb, pgt_1Hz_tb;
timer_control_level2 uut (
keypad_tb,
enable_n_tb,
clock_100Hz_tb,
D_tb,
load_n_tb,
pgt_1Hz_tb
);
initial begin
$dumpfile("./wave_forms/timer_control_level2.vcd");
$dumpvars(0, timer_control_level2_tb);
clock_100Hz_tb = 0;
enable_n_tb = 1;
keypad_tb = 10'b00_0000_0000;
end
initial begin
repeat (500) #5 clock_100Hz_tb = ~clock_100Hz_tb;
end
initial begin
#10 keypad_tb = 10'b00_0001_0000;
#100 keypad_tb = 10'b00_0000_0000;
#100 keypad_tb = 10'b00_1000_0000;
#300 keypad_tb = 10'b10_0010_0001;
#100 keypad_tb = 10'b00_0000_0000;
#10 enable_n_tb = 0;
#10 keypad_tb = 10'b00_1001_0000;
#100 keypad_tb = 10'b00_0000_0000;
#100 keypad_tb = 10'b00_0010_0000;
#300 keypad_tb = 10'b01_0010_0001;
#100 keypad_tb = 10'b00_0000_0000;
#100 keypad_tb = 10'b00_1100_0000;
#100 keypad_tb = 10'b00_0000_0000;
#10 enable_n_tb = 1;
#100;
end
endmodule
| 6.879247 |
module timer_display (
input [10:0] hcount, // Screen placement
input [10:0] vcount,
input [ 9:0] time_remaining, // Time left
input blank,
input clk,
input rst,
output r_timer, // Colors to display time
output g_timer,
output b_timer
);
reg [32:0] zero [0:31];
reg [32:0] one [0:31]; // Arrays for numbers
reg [32:0] two [0:31];
reg [32:0] three [0:31];
reg [ 5:0] rom_address; // Address to read
reg INTENSITY;
reg in_range;
reg [31:0] rom_data; // Data to display per line
reg [5:0] hc1, vc1; // Variable to display data
initial $readmemb("zero.dat", zero);
initial $readmemb("one.dat", one);
initial $readmemb("two.dat", two); // Read in data files for numbers
initial $readmemb("three.dat", three);
always @(posedge clk or negedge rst) begin
if (!rst) begin
vc1 <= 0;
rom_address <= 6'b100000; // Reset all values
in_range <= 0;
end
else if((hcount == 320) && (vcount == 4) && (blank == 0)) // Check if in range for display
begin
vc1 <= 0;
rom_address <= 9'b0; // Start initial values
in_range <= 1;
end
/* While in range display values */
else if((hcount >= 320) && (hcount < 351) && (vcount > 4) && (vcount <= 36) && (blank == 0))
begin
if ((hcount == 350)) begin
vc1 <= vc1 + 1;
rom_address <= vc1; // Increment vc1 when end of horizontal is reached
in_range <= 1;
end else begin
rom_address <= vc1; // Keep same line
in_range <= 1;
end
end else begin
rom_address <= 6'b100000; // Do nothing
in_range <= 0;
end
end
always @(posedge clk or negedge rst) begin
if (!rst) begin
hc1 <= 6'b0; // Reset horizontal counter
end else if ((hcount >= 320) && (hcount < 351) && (blank == 0)) begin
if ((hcount >= 320) && (hcount < 351) && (vcount > 4) && (vcount <= 36) && (blank == 0))
hc1 <= hc1 + 1; // Increment horizontal counter
end else begin
hc1 <= 6'b0; // Do nothing
end
end
/* Choose which number to display for time remaining */
always @(time_remaining) begin
if (time_remaining > 500) rom_data = three[rom_address]; // 3 seconds
else if (time_remaining > 250) rom_data = two[rom_address]; // 2 seconds
else if (time_remaining > 0) rom_data = one[rom_address]; // 1 second
else if (time_remaining == 0) rom_data = zero[rom_address]; // Game over
else rom_data = three[rom_address];
end
// Procedural block to assign pixel values to RGB
always @(posedge clk or negedge rst) begin
if (!rst) INTENSITY <= 0;
else if ((in_range) && (blank == 0)) // Output time left
INTENSITY <= rom_data[hc1];
else INTENSITY <= 0;
end
assign r_timer = (blank == 0) ? {{INTENSITY}} : 3'b0;
assign g_timer = (blank == 0) ? {{INTENSITY}} : 3'b0; // Values for displaying timer
assign b_timer = (blank == 0) ? {{INTENSITY}} : 2'b0;
endmodule
| 7.310348 |
module TM (
TMCLK,
DSPCLK,
T_RST,
TMODE,
DMD,
selTSR,
selTCR,
selTPR,
TSR_we,
TCR_we,
TPR_we,
MSTAT5,
TMOUT,
MMR_web,
ICE_ST,
`ifdef FD_DFT
/* dft */ SCAN_TEST,
`endif
TINT
);
input [15:0] DMD;
input TMCLK;
input DSPCLK;
input T_RST;
input selTSR;
input selTCR;
input selTPR;
input MSTAT5;
input TSR_we;
input TCR_we;
input TPR_we;
input TMODE;
input MMR_web;
input ICE_ST;
`ifdef FD_DFT
input SCAN_TEST;
`endif
output [15:0] TMOUT;
output TINT;
assign TMOUT = 0;
assign TINT = 0;
endmodule
| 7.473647 |
module TIMER_fjl (
input SYSCLK,
input RST_B,
input [2:0] TIME_MIN,
input [5:0] TIME_SEC,
input START,
output reg [2:0] MINUTE,
output reg [5:0] SECOND,
output reg TIME_UP
);
reg flag;
always @(posedge TIME_UP, posedge START) begin
if (TIME_UP) flag <= 0;
else flag = 1;
end
always @(posedge SYSCLK, negedge RST_B) begin
if (~RST_B) begin
MINUTE <= 3'd0;
SECOND <= 6'd0;
end else if (flag == 1)
if (MINUTE < TIME_MIN) begin
if (SECOND == 6'd59) begin
MINUTE <= MINUTE + 1'b1;
SECOND <= 3'd0;
end else begin
SECOND <= SECOND + 1'b1;
end
end else if (MINUTE == TIME_MIN)
if (SECOND == TIME_SEC) begin
MINUTE <= MINUTE;
SECOND <= SECOND;
end else begin
SECOND <= SECOND + 1'b1;
end
else begin
MINUTE <= MINUTE;
SECOND <= SECOND;
end
else begin
MINUTE <= MINUTE;
SECOND <= SECOND;
end
end
always @(posedge SYSCLK, negedge RST_B) begin
if (~RST_B) TIME_UP <= 1'b0;
else if (MINUTE == TIME_MIN && SECOND == TIME_SEC) TIME_UP <= 1'b1;
else TIME_UP <= 1'b0;
end
endmodule
| 7.211665 |
module TIMER_fjl_tb;
//reg count_flag;
reg clk = 0;
reg rst = 0;
reg [2:0] minute_in = 3'd0;
reg [5:0] second_in = 6'd0;
reg start = 0;
wire [2:0] minute_out;
wire [5:0] second_out;
wire time_up;
always begin
#5 clk = ~clk;
end
initial begin
rst = 0;
start = 0;
//count_flag = 0;
minute_in = 3'd0;
second_in = 3'd0;
#10 rst = 1;
#5 start = 1;
minute_in = 3'd3;
second_in = 6'd48;
#5 start = 1;
#1000000 $finish;
end
TIMER_fjl TIMER_fjl_test (
.SYSCLK(clk),
.RST_B(rst),
.START(start),
.TIME_MIN(minute_in),
.TIME_SEC(second_in),
.MINUTE(minute_out),
.SECOND(second_out),
.TIME_UP(time_up)
);
initial $monitor("At time :%t,%d,%d", $time, minute_out, second_out);
initial begin
$dumpfile("TIMER_fjl_test.vcd");
$dumpvars(0, TIMER_fjl_test);
end
endmodule
| 6.760316 |
module Timer_hull (
Clk,
rst_n,
Enable,
Start,
Clr,
Dir,
Dout1
);
parameter Bit = 32;
input Clk, rst_n, Enable, Clr, Dir, Start;
output [Bit-1:0] Dout1;
reg [Bit-1:0] Dout, Dout1;
always @(posedge Clk or negedge Clr or negedge rst_n) begin
if (rst_n == 1'b0) begin
Dout <= 32'd0;
Dout1 <= 32'd0;
end else begin
if (Clr == 1'b0) Dout <= 0;
else if (Enable & Start) begin
if (Dir == 1'b1) begin
if (Dout == (32'b1 << (Bit - 1)) - 1) Dout <= 32'b1;
else Dout <= Dout + 1'b1;
end else begin
if (Dout == (32'b1 << (Bit - 1))) Dout <= -32'b1;
else Dout <= Dout - 1'b1;
end
end else if (Start == 1'b0) Dout1 <= Dout;
else Dout <= Dout;
end
end
endmodule
| 7.034946 |
module timer_input #(
parameter BITS = 4
) (
input clk,
input reset_n,
input enable,
input [BITS - 1:0] FINAL_VALUE,
// output [BITS - 1:0] Q,
output done
);
reg [BITS - 1:0] Q_reg, Q_next;
always @(posedge clk, negedge reset_n) begin
if (~reset_n) Q_reg <= 'b0;
else if (enable) Q_reg <= Q_next;
else Q_reg <= Q_reg;
end
// Next state logic
assign done = Q_reg == FINAL_VALUE;
always @(*) Q_next = done ? 'b0 : Q_reg + 1;
endmodule
| 6.618852 |
module timer_input_and_control_module (
output wire [3:0] D,
output wire loadn,
output wire pgt_1Hz,
input [9:0] numpad,
input enablen,
input clock_100Hz
);
wire dataValid;
numpad_encoder encoder (
.BCDout(D),
.validData(dataValid),
.enablen(enablen),
.numpad(numpad)
);
assign loadn = dataValid;
wire debounceCounterOut;
counter_0to7_nonRecycling counter (
.out (debounceCounterOut),
.clear(dataValid),
.clk (clock_100Hz)
);
wire clock_1Hz;
counter_divide_by_100 count (
.clk(clock_100Hz),
.newclk(clock_1Hz)
);
MUX_2X1 mux (
.in1(debounceCounterOut),
.in2(clock_1Hz),
.select(enablen),
.out(pgt_1Hz)
);
endmodule
| 8.252794 |
module.v"
module test;
wire [3:0] D;
wire loadn;
wire pgt_1Hz;
reg [9:0] numpad;
reg enablen;
reg clock_100Hz;
timer_input_and_control_module modulo(
.D(D),
.loadn(loadn),
.pgt_1Hz(pgt_1Hz),
.numpad(numpad),
.enablen(enablen),
.clock_100Hz(clock_100Hz)
);
always #5 clock_100Hz <= ~clock_100Hz;
initial begin
clock_100Hz = 1;
$dumpfile("test.vcd");
$dumpvars(0,test);
// teste do enablen
enablen = 1;
numpad = 10'b0000000000;
#10; // validData == 1; BCDout == X
numpad = 10'b0000000001;
#10; // validData == 1; BCDout == X
// teste apertando os botões
enablen = 0;
numpad = 10'b0000000000;
#10; // validData == 1; BCDout == X
// embaixo, validData == 0; BCDout == *conversão*
numpad = 10'b0000000001;
#300;
numpad = 10'b0000000000; // tira o dedo do botão
#100;
numpad = 10'b0000000010;
#300;
// numpad = 10'b0000000100;
// #100;
// numpad = 10'b0000001000;
// #100;
// numpad = 10'b0000010000;
// #100;
// numpad = 10'b0000100000;
// #100;
// numpad = 10'b0001000000;
// #100;
// numpad = 10'b0010000000;
// #100;
// numpad = 10'b0100000000;
// #100;
// numpad = 10'b1000000000;
// #100;
// // agora, não aperta nenhum botão
// numpad = 10'b0000000000;
// #100;
// // aperta um botão aleatório e solta pra testar
// numpad = 10'b0000010000;
// #100;
// numpad = 10'b0000000000;
// #100;
$finish();
end
endmodule
| 6.67459 |
module timer_input_tb ();
localparam BITS = 16;
reg clk, reset_n, enable;
reg [BITS - 1:0] FINAL_VALUE;
wire done;
// Instantiate module under test
timer_input #(
.BITS(BITS)
) uut (
.clk(clk),
.reset_n(reset_n),
.enable(enable),
.FINAL_VALUE(FINAL_VALUE),
.done(done)
);
// Generate stimuli
// Generating a clk signal
localparam T = 10;
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2);
end
initial begin
// issue a quick reset for 2 ns
reset_n = 1'b0;
#2 reset_n = 1'b1;
enable = 1'b1;
FINAL_VALUE = 255;
#(FINAL_VALUE * T * 3);
FINAL_VALUE = 49_999;
#(FINAL_VALUE * T * 2);
$stop;
end
endmodule
| 8.015644 |
module `VARIANT`TIMER_MICRO_REG
#(parameter BASE_ADDR = 4'h0,
parameter BASE_WIDTH = 4,
parameter ADDR_WIDTH = 8
)(
input wire clk,
input wire reset,
input wire cs,
input wire wr,
input wire rd,
input wire [ADDR_WIDTH-1:0] waddr,
input wire [ADDR_WIDTH-1:0] raddr,
input wire [7:0] wdata,
output reg [7:0] rdata,
input wire [7:0] count_0,
input wire [7:0] start_0,
input wire [7:0] count_1,
input wire [7:0] start_1
);
parameter TIMER_0_START = 4'h0;
parameter TIMER_0_COUNT = 4'h2;
parameter TIMER_0_END = 4'h4;
parameter TIMER_1_START = 4'h8;
parameter TIMER_1_COUNT = 4'hA;
parameter TIMER_1_END = 4'hC;
reg was;
reg ras;
always@(*) was = (waddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*) ras = (raddr[ADDR_WIDTH-1:ADDR_WIDTH-BASE_WIDTH] == BASE_ADDR);
always@(*)
if(rd && cs && ras)
begin
case(raddr[3:0])
TIMER_0_START: rdata = start_0;
TIMER_0_COUNT: rdata = count_0;
TIMER_1_START: rdata = start_1;
TIMER_1_COUNT: rdata = count_1;
default: rdata = 8'h00;
endcase
end
else
begin
rdata = 8'hFF;
end
endmodule
| 7.116795 |
module timer_N_bits #(
parameter N = 4
) (
input clk,
load,
enable,
input [N-1:0] data,
output out
);
reg [N-1:0] count;
always @(posedge clk)
if (load) count <= data;
else if (enable) count <= count - 1;
else count <= count;
assign out = (count == 0);
endmodule
| 6.77748 |
module timer_parameter #(
parameter FINAL_VALUE = 255
) (
input clk,
input reset_n,
input enable,
// output [BITS - 1:0] Q, // we don't care about the value of the counter
output done
);
localparam BITS = $clog2(FINAL_VALUE);
reg [BITS - 1:0] Q_reg, Q_next;
always @(posedge clk, negedge reset_n) begin
if (~reset_n) Q_reg <= 'b0;
else if (enable) Q_reg <= Q_next;
else Q_reg <= Q_reg;
end
// Next state logic
assign done = Q_reg == FINAL_VALUE;
always @(*) Q_next = done ? 'b0 : Q_reg + 1;
endmodule
| 7.66581 |
module timer_parameter_tb ();
localparam FINAL_VALUE = 49_999;
localparam BITS = $clog2(FINAL_VALUE);
reg clk, reset_n, enable;
wire done;
// Instantiate module under test
timer_parameter #(
.FINAL_VALUE(FINAL_VALUE)
) uut (
.clk(clk),
.reset_n(reset_n),
.enable(enable),
.done(done)
);
// Generate stimuli
// Generating a clk signal
localparam T = 10;
always begin
clk = 1'b0;
#(T / 2);
clk = 1'b1;
#(T / 2);
end
initial #(FINAL_VALUE * T * 3) $stop;
initial begin
// issue a quick reset for 2 ns
reset_n = 1'b0;
#2 reset_n = 1'b1;
enable = 1'b1;
end
endmodule
| 7.66581 |
module generates a one clock pulse
* at a frequency specified by the input rate_ms.
* Valid range is 1 .. 255 ms.
*
* Status: In development
*
* Author : Brandon Blodget
* Create Date: 10/13/2019
*
*****************************
*/
/*
*****************************
*
* Copyright (C) 2019 by Brandon Blodget <brandon.blodget@gmail.com>
* All rights reserved.
*
* License:
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*****************************
*/
module timer_pulse #
(
parameter integer CLK_FREQUENCY = 50_000_000
)
(
input wire clk,
input wire reset,
input wire [7:0] rate_ms,
output reg pulse
);
// Generate the interrupt enable at specified rate
localparam ONE_MS_COUNT = ( CLK_FREQUENCY / 1000 );
localparam COUNT_BITS = $clog2(ONE_MS_COUNT);
reg [COUNT_BITS-1:0] count_to_1ms;
reg [7:0] count_1ms;
always @ (posedge clk)
begin
if (reset) begin
count_to_1ms <= 0;
count_1ms <= 0;
pulse <= 0;
end else begin
if (rate_ms != 0) begin
pulse <= 0;
count_to_1ms <= count_to_1ms + 1;
if (count_to_1ms == (ONE_MS_COUNT-1)) begin
count_to_1ms <= 0;
count_1ms <= count_1ms + 1;
end
if (count_1ms == rate_ms) begin
count_1ms <= 0;
pulse <= 1;
end
end
end
end
endmodule
| 7.192867 |
module timer_send (
input clk,
input rst_n,
input en,
input tx_busy,
output reg [7:0] tx_dout,
output reg tx_dout_vld
);
//
parameter BYTE_NUM = 19; //һη19ֽ
reg [(BYTE_NUM*8)-1:0] send_data; //Ĵ淢Ϣ
reg en_flag; //ģ鹤
reg send_flag; //ͱ־ź
reg [ 7:0] cnt; //ֽڼ,255ֽ
wire add_cnt;
wire end_cnt;
wire [ 23:0] clock_data;
wire start_send;
//send_flagΪģ鹤
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_flag <= 1'b0;
end else if (en) begin
en_flag <= ~en_flag;
end else begin
en_flag <= en_flag;
end
end
//1152001sԷ115200bit,11520ֽ
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
send_flag <= 1'b0;
end else if (en_flag && end_cnt) begin
send_flag <= 1'b0;
end else if (en_flag && start_send) begin
send_flag <= 1'b1;
end else begin
send_flag <= send_flag;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
send_data <= 0;
end else if (start_send) begin
send_data <= {
`CURTENT_TIME,
":",
"0" + clock_data[23:20],
"0" + clock_data[19:16],
":",
"0" + clock_data[15:12],
"0" + clock_data[11:8],
":",
"0" + clock_data[7:4],
"0" + clock_data[3:0],
"\r",
"\n"
}; //ƴӷϢ
end else begin
send_data <= send_data;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tx_dout <= 8'd0;
end else if (send_flag && !tx_busy) begin
tx_dout <= send_data[((BYTE_NUM*8)-1)-(cnt*8)-:8];
end else begin
tx_dout <= tx_dout;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
tx_dout_vld <= 1'b0;
end else if (send_flag && !tx_busy) begin //send_flag==1ҷģ
tx_dout_vld <= 1'b1;
end else begin
tx_dout_vld <= 1'b0;
end
end
//ֽڼͳƷ͵Ķֽ
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 0;
end else if (add_cnt) begin
if (end_cnt) begin
cnt <= 0;
end else begin
cnt <= cnt + 1;
end
end else begin
cnt <= cnt;
end
end
assign add_cnt = tx_dout_vld;
assign end_cnt = add_cnt && cnt == BYTE_NUM - 1;
clock_data u_clock_data (
/*input */.clk (clk),
/*input */.rst_n (rst_n),
/*output [23:0] */.clock_data(clock_data),
/*output reg */.alarm_en (),//ӱ־ź
/*output */.time_1s (start_send) //1sź
);
endmodule
| 7.023341 |
module timer_setting (
input clk,
input [1:0] switch_state,
input button_left,
input button_right,
input button_increase,
input button_decrease,
input switch_confirm,
output reg [23:0] set_timer_display, //this is the pattern that is going to be displayed
//remember you also want to display it even if the user
//is in the process of setting time. You can still use this
//variable name but it may not mean "intended" timer
output reg [23:0] intended_set_timer,
output reg [5:0] blinking_pattern //Which digit shall blink. 1 for blinking, 0 for stationary.
);
wire clean_button_left;
wire clean_button_right;
wire clean_button_increase;
wire clean_button_decrease;
wire clean_switch_confirm;
debouncer debounce_left3 (
button_left,
clk,
clean_button_left
);
debouncer debounce_right3 (
button_right,
clk,
clean_button_right
);
debouncer debounce_increase3 (
button_increase,
clk,
clean_button_increase
);
debouncer debounce_decrease3 (
button_decrease,
clk,
clean_button_decrease
);
debouncer debounce_confirm3 (
switch_confirm,
clk,
clean_switch_confirm
);
//the two hour digits
reg [3:0] hour_left;
reg [3:0] hour_right;
//the two minute digits
reg [3:0] min_left;
reg [3:0] min_right;
//the two second digits
reg [3:0] sec_left;
reg [3:0] sec_right;
initial blinking_pattern = 6'b100000;
always @(posedge clk) begin
if (switch_state[0] == 0)
{hour_left, hour_right, min_left, min_right, sec_left, sec_right} <= intended_set_timer;
else if (switch_state[1:0] == 2'b11) begin
if (clean_switch_confirm == 1) intended_set_timer <= set_timer_display;
else begin
set_timer_display <= {hour_left, hour_right, min_left, min_right, sec_left, sec_right};
if (clean_button_right == 1)
case (blinking_pattern)
6'b100000: blinking_pattern <= 6'b010000;
6'b010000: blinking_pattern <= 6'b001000;
6'b001000: blinking_pattern <= 6'b000100;
6'b000100: blinking_pattern <= 6'b000010;
6'b000010: blinking_pattern <= 6'b000001;
6'b000001: blinking_pattern <= 6'b100000;
endcase
else if (clean_button_left == 1)
case (blinking_pattern)
6'b100000: blinking_pattern <= 6'b000001;
6'b010000: blinking_pattern <= 6'b100000;
6'b001000: blinking_pattern <= 6'b010000;
6'b000100: blinking_pattern <= 6'b001000;
6'b000010: blinking_pattern <= 6'b000100;
6'b000001: blinking_pattern <= 6'b000010;
endcase
else if (clean_button_increase == 1)
case (blinking_pattern)
6'b100000: begin
if (hour_left < 9) hour_left <= hour_left + 1;
else hour_right <= 0;
end
6'b010000: begin
if (hour_right < 9) hour_right <= hour_right + 1;
else hour_right <= 0;
end
6'b001000: begin
if (min_left < 5) min_left <= min_left + 1;
else min_left <= 0;
end
6'b000100: begin
if (min_right < 9) min_right <= min_right + 1;
else min_right <= 0;
end
6'b000010: begin
if (sec_left < 5) sec_left <= sec_left + 1;
else sec_left <= 0;
end
6'b000001: begin
if (sec_right < 9) sec_right <= sec_right + 1;
else sec_right <= 0;
end
endcase
else if (clean_button_decrease == 1)
case (blinking_pattern)
6'b100000: begin
if (hour_left > 0) hour_left <= hour_left - 1;
else hour_left <= 9;
end
6'b010000: begin
if (hour_right > 0) hour_right <= hour_right - 1;
else hour_right <= 9;
end
6'b001000: begin
if (min_left > 0) min_left <= min_left - 1;
else min_left <= 5;
end
6'b000100: begin
if (min_right > 0) min_right <= min_right - 1;
else min_right <= 9;
end
6'b000010: begin
if (sec_left > 0) sec_left <= sec_left - 1;
else sec_left <= 5;
end
6'b000001: begin
if (sec_right > 0) sec_right <= sec_right - 1;
else sec_right <= 9;
end
endcase
end
end
end
endmodule
| 7.761972 |
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