code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module timing_gen_xy #(
parameter DATA_WIDTH = 16 // Video data one clock data width
) (
input rst_n,
input clk,
input i_hs,
input i_vs,
input i_de,
input [DATA_WIDTH - 1:0] i_data,
output o_hs,
output o_vs,
output o_de,
output [DATA_WIDTH - 1:0] o_data,
output [ 11:0] x, // video position X
output [ 11:0] y // video position y
);
reg de_d0;
reg de_d1;
reg vs_d0;
reg vs_d1;
reg hs_d0;
reg hs_d1;
reg [DATA_WIDTH - 1:0] i_data_d0;
reg [DATA_WIDTH - 1:0] i_data_d1;
reg [11:0] x_cnt = 12'd0;
reg [11:0] y_cnt = 12'd0;
wire vs_edge;
wire de_falling;
assign vs_edge = vs_d0 & ~vs_d1;
assign de_falling = ~de_d0 & de_d1;
assign o_de = de_d1;
assign o_vs = vs_d1;
assign o_hs = hs_d1;
assign o_data = i_data_d1;
always @(posedge clk) begin
de_d0 <= i_de;
de_d1 <= de_d0;
vs_d0 <= i_vs;
vs_d1 <= vs_d0;
hs_d0 <= i_hs;
hs_d1 <= hs_d0;
i_data_d0 <= i_data;
i_data_d1 <= i_data_d0;
end
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) x_cnt <= 12'd0;
else if (de_d1 == 1'b1) x_cnt <= x_cnt + 12'd1;
else x_cnt <= 12'd0;
end
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) y_cnt <= 12'd0;
else if (vs_edge == 1'b1) y_cnt <= 12'd0;
else if (de_falling == 1'b1) y_cnt <= y_cnt + 12'd1;
else y_cnt <= y_cnt;
end
assign x = x_cnt;
assign y = y_cnt;
endmodule
| 8.049548 |
module timing_io (
input wire sysclk,
input wire clk1_pad,
input wire clk2_pad,
input wire poc_pad,
input wire ior,
// Timing and I/O Board Outputs
output wire clk1,
output wire clk2,
output wire a12,
output wire a22,
output wire a32,
output wire m12,
output wire m22,
output wire x12,
output wire x22,
output wire x32,
output wire gate,
output reg poc,
// External I/O Pad conditioning
inout wire [3:0] data,
inout wire [3:0] data_pad,
input wire test_pad,
output reg n0432,
output reg sync_pad,
input wire cmrom,
output wire cmrom_pad,
input wire cmram0,
output wire cmram0_pad,
input wire cmram1,
output wire cmram1_pad,
input wire cmram2,
output wire cmram2_pad,
input wire cmram3,
output wire cmram3_pad
);
// Simple pass-throughs
assign clk1 = clk1_pad;
assign clk2 = clk2_pad;
assign cmrom_pad = cmrom;
assign cmram0_pad = cmram0;
assign cmram1_pad = cmram1;
assign cmram2_pad = cmram2;
assign cmram3_pad = cmram3;
// Generate the 8 execution phase indicators
reg [0:7] master = 8'h00;
reg [0:7] slave = 8'h00;
always @(posedge sysclk) begin
if (clk2) master <= {~|slave[0:6], slave[0:6]};
else sync_pad <= master[7];
if (clk1) slave <= master;
end
assign a12 = slave[0];
assign a22 = slave[1];
assign a32 = slave[2];
assign m12 = slave[3];
assign m22 = slave[4];
assign x12 = slave[5];
assign x22 = slave[6];
assign x32 = slave[7];
// Generate the DRAM Input Gate signal
// Properly called M12+M22+CLK1~(M11&M12)
wire n0279 = ~(a32 | m12);
reg n0278;
always @(posedge sysclk) begin
if (clk2) n0278 <= n0279;
end
wire n0708 = ~((n0278 & clk1) | m12 | m22);
assign gate = ~n0708;
// Generate a clean POC signal
always @(posedge sysclk) begin
if (poc_pad) poc <= 1'b1;
else if (a12) poc <= 1'b0;
else poc <= poc;
end
// Generate a clean ~TEST signal (n0432)
always @(posedge sysclk) begin
n0432 <= ~test_pad;
end
// Manage the Data I/O pads
reg L;
always @(posedge sysclk) begin
if (clk2) L <= a32 | m12 | (x12 & (ior | poc));
end
wire n0702 = ~clk2;
reg n0685;
reg n0699;
reg n0707;
always @(posedge sysclk) begin
if (clk1) begin
n0685 <= ~L;
n0707 <= L;
end
if (n0702) n0699 <= ~L;
end
wire n0700 = n0707 | (L & n0702) | poc;
wire n0659 = (clk2 & n0685) | (clk1 & L);
wire n0676 = clk1 | n0685 | n0699;
// Incoming data from the external pads
reg [3:0] data_in;
always @* begin
if (n0659) data_in = 4'b1111;
else if (n0676) data_in = 4'bzzzz;
else if (poc) data_in = 4'b0000;
else data_in = data_pad;
end
assign data = data_in;
// Outgoing data to the external pads
reg [3:0] data_out;
always @(posedge sysclk) begin
if (n0702) data_out <= data;
end
assign data_pad = poc ? 4'b0000 : (n0700 ? 4'bzzzz : data_out);
endmodule
| 7.629368 |
module timing_management_unit #(
parameter HIGH_COUNT = 1,
parameter LOW_COUNT = 12
) (
input rst,
input clk_in,
output reg clk_out
);
parameter COUNTER_LAST_BIT_INDEX = HIGH_COUNT + LOW_COUNT - 1;
reg [COUNTER_LAST_BIT_INDEX : 0] reg_counter;
wire [COUNTER_LAST_BIT_INDEX : 0] counter_in = reg_counter << 1;
always @(posedge clk_in) begin
if (rst || !counter_in) reg_counter <= 1;
else reg_counter <= counter_in;
end
always @(posedge clk_in) begin
if (rst || !counter_in || counter_in < 1 << LOW_COUNT) clk_out <= 0;
else clk_out <= 1;
end
endmodule
| 7.513826 |
module timing_state (
input en,
input clk,
input [1:0] KEY,
input [9:0] SW,
output reg [9:0] LEDR,
output wire [7:0] HEX0,
output wire [7:0] HEX1,
output wire [7:0] HEX2,
output wire [7:0] HEX3,
output reg [3:0] score_a,
output reg [3:0] score_b,
output reg [3:0] score_c,
output reg [3:0] score_d,
output wire [3:0] out_state
);
wire khz_clk;
wire [3:0] cnt_a;
wire [3:0] cnt_b;
wire [3:0] cnt_c;
wire [3:0] cnt_d;
wire carry_a;
wire carry_b;
wire carry_c;
wire carry_d;
clock_divider clk_div (
clk,
khz_clk
);
bcd_counter ca (
khz_clk,
!en,
cnt_a,
carry_a
);
bcd_counter cb (
carry_a,
!en,
cnt_b,
carry_b
);
bcd_counter cc (
carry_b,
!en,
cnt_c,
carry_c
);
bcd_counter cd (
carry_c,
!en,
cnt_d,
carry_d
);
bcd_decoder da (
cnt_a,
0,
HEX0
);
bcd_decoder db (
cnt_b,
0,
HEX1
);
bcd_decoder dc (
cnt_c,
0,
HEX2
);
bcd_decoder dz (
cnt_d,
1,
HEX3
);
wire [2:0] l_out;
reg [3:0] l_mem;
lfsr_nine lnine (
khz_clk,
l_out
);
wire [7:0] eight_dec;
three_to_eight_decoder ted (
l_mem,
eight_dec
);
always @(negedge en) begin
score_a <= cnt_a;
score_b <= cnt_b;
score_c <= cnt_c;
score_d <= cnt_d;
end
always @(posedge clk) begin
if (en)
// LEDR <= 10'h3ff;
LEDR <= {
2'd0, eight_dec
};
else begin
LEDR <= 0;
l_mem <= l_out;
end
end
assign out_state = (en && (SW == {2'd0, eight_dec})) ? 3 : 2;
//assign out_state = (en && !KEY[0]) ? 3 : 2;
endmodule
| 8.697175 |
module timing_strobe_generator #(
parameter CLOCKS_PER_TICK = 415_667 // 25MHz / 60Hz
) (
input wire i_clk,
output wire o_tick_stb,
output wire o_beat_stb
);
localparam TICK_WIDTH = $clog2(CLOCKS_PER_TICK);
reg [TICK_WIDTH-1:0] r_tick_counter = 0;
always @(posedge i_clk) begin
if (r_tick_counter == CLOCKS_PER_TICK - 1) begin
r_tick_counter <= 0;
end else begin
r_tick_counter <= r_tick_counter + 1;
end
end
assign o_tick_stb = (r_tick_counter == CLOCKS_PER_TICK - 1);
localparam TICKS_PER_BEAT = 5;
localparam BEAT_WIDTH = $clog2(TICKS_PER_BEAT);
reg [BEAT_WIDTH-1:0] r_beat_counter = 0;
always @(posedge i_clk) begin
if (o_tick_stb) begin
if (r_beat_counter == TICKS_PER_BEAT - 1) begin
r_beat_counter <= 0;
end else begin
r_beat_counter <= r_beat_counter + 1;
end
end
end
assign o_beat_stb = o_tick_stb & (r_beat_counter == TICKS_PER_BEAT - 1);
endmodule
| 6.522316 |
module timing_subsystem #(
parameter C_USE_HARDWARE_CLOCKS = 0
) (
input wire rst_n,
input wire CLK_48M,
// generated clocks
output wire CLK_24M,
output wire CLK_12M,
output wire CLK_6M,
output wire CLK_6MD,
// video synchronisation
output wire nVSYNC,
output wire nHSYNC,
output wire nHBLANK,
output wire nVBLANK,
output wire nHRESET,
output wire nVRESET,
output wire BLANKING,
output wire nCOMPSYNC,
// video timing signals
output wire _8V,
output wire _4V,
output wire _1V,
output wire _4H,
output wire _2H,
output wire _1H,
output wire n1H,
output wire S2H,
output wire S1H,
output wire nS1H
);
wire cus27_hblank;
// CUS27 - CLOCK DIVIDER
//cus27
cus27_gng_ref cus27_9p_clock_divider (
.rst_n(rst_n),
.CLK_48M(CLK_48M),
.CLK_6M_IN(CLK_6M),
.CLK_24M(CLK_24M),
.CLK_12M(CLK_12M),
.CLK_6M(CLK_6M),
.nVSYNC(nVSYNC),
.nHSYNC(nHSYNC),
.nHBLANK(nHBLANK),
.nVBLANK(nVBLANK),
.nHRESET(nHRESET),
.nVRESET(nVRESET),
._8V(_8V),
._4V(_4V),
._1V(_1V),
._4H(_4H),
._2H(_2H),
._1H(_1H),
.S2H(S2H),
.S1H(S1H)
);
// == TTL glue logic
ls74 ls74_8u (
.CLK1(CLK_6M),
.nPRE1(1'b1),
.nCLR1(1'b1),
.D1(CLK_1H),
.Q1(CLK_n1H),
//.nQ1(1'b0),
.CLK2(CLK_4H),
.nPRE2(1'b1),
.nCLR2(nVBLANK),
.D2(nHBLANK),
//.Q2(1'b0),
.nQ2(BLANKING)
);
assign CLK_6MD = CLK_6M;
assign nS1H = ~S1H;
assign nCOMPSYNC = nHSYNC && nVSYNC; // via LS08 (3H) and'ing of negated signals
endmodule
| 7.424261 |
module: TILEGEN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// License: https://www.apache.org/licenses/LICENSE-2.0
//
////////////////////////////////////////////////////////////////////////////////
module timing_subsystem_tb;
reg clk_in;
reg rst_n;
// == supply rails ==
supply1 VCC;
supply0 GND;
wire CLK_6M;
wire _1H;
wire _2H;
wire _4H;
wire _1V;
//wire CLK_2V;
wire _4V;
wire n1H;
wire S1H;
wire S2H;
wire nS1H;
wire nHSYNC;
wire nVSYNC;
wire nHBLANK;
wire nVBLANK;
wire nVRESET;
wire nCOMPSYNC;
// Timing subsystem
timing_subsystem timing(
.rst_n(rst_n),
.CLK_48M(clk_in),
.CLK_6M(CLK_6M),
.nHSYNC(nHSYNC),
.nVSYNC(nVSYNC),
.nHBLANK(nHBLANK),
.nVBLANK(nVBLANK),
.nVRESET(nVRESET),
.nCOMPSYNC(nCOMPSYNC),
._1H(_1H),
.n1H(n1H),
._2H(_2H),
._4H(_4H),
._1V(_1V),
//.CLK_2V(_2V),
._4V(_4V),
._8V(_8V),
.S1H(S1H),
.nS1H(nS1H),
.S2H(S2H)
);
initial begin
rst_n = 0;
clk_in = 0;
// Wait 100 ns for global reset to finish
#100;
rst_n = 1;
end
always @(negedge nHSYNC) begin
if (_1V && _4V && _8V)
$stop;
end
always begin
#10.1725 clk_in = ~clk_in;
end
endmodule
| 7.238032 |
module timing_top (
// 12MHz clock input
input clk,
input [8:0] a,
input [8:0] b,
output [35:0] c
);
wire rst = 1'b0;
timing pipeline (
.clk(clk),
.rst(rst),
.a (a),
.b (b),
.c (c)
);
endmodule
| 7.744135 |
module tiny (
clk,
reset,
sel,
addr,
w,
data,
out,
done
);
input clk, reset;
input sel;
input [5:0] addr;
input w;
input [`WIDTH_D0:0] data;
output [`WIDTH_D0:0] out;
output done;
/* for FSM */
wire [5:0] fsm_addr;
/* for RAM */
wire [5:0] ram_a_addr, ram_b_addr;
wire [`WIDTH_D0:0] ram_b_data_in;
wire ram_a_w, ram_b_w;
wire [`WIDTH_D0:0] ram_a_data_out, ram_b_data_out;
/* for const */
wire [`WIDTH_D0:0] const0_out, const1_out;
wire const0_effective, const1_effective;
/* for muxer */
wire [`WIDTH_D0:0] muxer0_out, muxer1_out;
/* for ROM */
wire [ 8:0] rom_addr;
wire [28:0] rom_q;
/* for PE */
wire [10:0] pe_ctrl;
assign out = ram_a_data_out;
select select0 (
sel,
addr,
fsm_addr,
w,
ram_a_addr,
ram_a_w
);
rom rom0 (
clk,
rom_addr,
rom_q
);
FSM fsm0 (
clk,
reset,
rom_addr,
rom_q,
fsm_addr,
ram_b_addr,
ram_b_w,
pe_ctrl,
done
);
const_
const0 (
clk,
ram_a_addr,
const0_out,
const0_effective
),
const1 (
clk,
ram_b_addr,
const1_out,
const1_effective
);
ram ram0 (
clk,
ram_a_w,
ram_a_addr,
data,
ram_a_data_out,
ram_b_w,
ram_b_addr[5:0],
ram_b_data_in,
ram_b_data_out
);
muxer
muxer0 (
ram_a_data_out,
const0_out,
const0_effective,
muxer0_out
),
muxer1 (
ram_b_data_out,
const1_out,
const1_effective,
muxer1_out
);
PE pe0 (
clk,
reset,
pe_ctrl,
muxer1_out,
muxer0_out[`WIDTH:0],
muxer0_out[`WIDTH:0],
ram_b_data_in[`WIDTH:0]
);
assign ram_b_data_in[`WIDTH_D0:`WIDTH+1] = 0;
endmodule
| 6.906849 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module PPG (
d,
A,
C
);
input [1:0] d;
input [`WIDTH:0] A;
output [`WIDTH:0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : ppg0
f3_mult f3_mult_0 (
d,
A[2*i+1:2*i],
C[2*i+1:2*i]
);
end
endgenerate
endmodule
| 7.164526 |
module muxer (
from_ram,
from_const,
const_effective,
out
);
input [`WIDTH_D0:0] from_ram, from_const;
input const_effective;
output [`WIDTH_D0:0] out;
assign out = const_effective ? from_const : from_ram;
endmodule
| 6.618212 |
module ram #(
parameter DATA = 1188,
parameter ADDR = 6
) (
input clk,
// Port A
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
// Shared memory
reg [DATA-1:0] mem[(2**ADDR)-1:0];
initial begin : init
integer i;
for (i = 0; i < (2 ** ADDR); i = i + 1) mem[i] = 0;
end
// Port A
always @(posedge clk) begin
a_dout <= mem[a_addr];
if (a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge clk) begin
b_dout <= mem[b_addr];
if (b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
| 7.30525 |
module const_ (
clk,
addr,
out,
effective
);
input clk;
input [5:0] addr;
output reg [`WIDTH_D0:0] out;
output reg effective; // active high if out is effective
always @(posedge clk) begin
effective <= 1;
case (addr)
1: out <= 0;
2: out <= 1;
4: out <= {6'b000101, 1182'd0};
8: out <= {6'b001001, 1182'd0};
16: out <= {6'b010101, 1182'd0};
default: begin
out <= 0;
effective <= 0;
end
endcase
end
endmodule
| 7.25663 |
module FSM (
clk,
reset,
rom_addr,
rom_q,
ram_a_addr,
ram_b_addr,
ram_b_w,
pe,
done
);
input clk;
input reset;
output reg [8:0] rom_addr; /* command id. extra bits? */
input [28:0] rom_q; /* command value */
output reg [5:0] ram_a_addr;
output reg [5:0] ram_b_addr;
output ram_b_w;
output reg [10:0] pe;
output reg done;
reg [5:0] state;
parameter START = 0, READ_SRC1 = 1, READ_SRC2 = 2, CALC = 4, WAIT = 8, WRITE = 16, DON = 32;
wire [5:0] dest, src1, src2;
wire [8:0] times;
wire [1:0] op;
assign {dest, src1, op, times, src2} = rom_q;
reg [8:0] count;
always @(posedge clk)
if (reset) state <= START;
else
case (state)
START: state <= READ_SRC1;
READ_SRC1: state <= READ_SRC2;
READ_SRC2:
if (times == 0) state <= DON;
else state <= CALC;
CALC: if (count == 1) state <= WAIT;
WAIT: state <= WRITE;
WRITE: state <= READ_SRC1;
endcase
/* we support two loops */
parameter LOOP1_START = 9'd21, LOOP1_END = 9'd116, LOOP2_START = 9'd288, LOOP2_END = 9'd301;
reg [294:0] loop1, loop2;
always @(posedge clk)
if (reset) rom_addr <= 0;
else if (state == WAIT) begin
if (rom_addr == LOOP1_END && loop1[0]) rom_addr <= LOOP1_START;
else if (rom_addr == LOOP2_END && loop2[0]) rom_addr <= LOOP2_START;
else rom_addr <= rom_addr + 1'd1;
end
always @(posedge clk)
if (reset) loop1 <= ~0;
else if (state == WAIT && rom_addr == LOOP1_END) loop1 <= loop1 >> 1;
always @(posedge clk)
if (reset) loop2 <= ~0;
else if (state == WAIT && rom_addr == LOOP2_END) loop2 <= loop2 >> 1;
always @(posedge clk)
if (reset) count <= 0;
else if (state == READ_SRC1) count <= times;
else if (state == CALC) count <= count - 1'd1;
always @(posedge clk)
if (reset) done <= 0;
else if (state == DON) done <= 1;
else done <= 0;
always @(state, src1, src2)
case (state)
READ_SRC1: ram_a_addr = src1;
READ_SRC2: ram_a_addr = src2;
default: ram_a_addr = 0;
endcase
parameter CMD_ADD=6'd4, CMD_SUB=6'd8, CMD_CUBIC=6'd16,
ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
always @(posedge clk)
case (state)
READ_SRC1:
case (op)
ADD: pe <= 11'b11001000000;
SUB: pe <= 11'b11001000000;
CUBIC: pe <= 11'b11111000000;
MULT: pe <= 11'b11110000000;
default: pe <= 0;
endcase
READ_SRC2:
case (op)
ADD: pe <= 11'b00110000000;
SUB: pe <= 11'b00110000000;
CUBIC: pe <= 0;
MULT: pe <= 11'b00001000000;
default: pe <= 0;
endcase
CALC:
case (op)
ADD: pe <= 11'b00000010001;
SUB: pe <= 11'b00000010001;
CUBIC: pe <= 11'b01010000001;
MULT: pe <= 11'b00000111111;
default: pe <= 0;
endcase
default: pe <= 0;
endcase
always @(state, op, src2, dest)
case (state)
READ_SRC1:
case (op)
ADD: ram_b_addr = CMD_ADD;
SUB: ram_b_addr = CMD_SUB;
CUBIC: ram_b_addr = CMD_CUBIC;
default: ram_b_addr = 0;
endcase
READ_SRC2: ram_b_addr = src2;
WRITE: ram_b_addr = dest;
default: ram_b_addr = 0;
endcase
assign ram_b_w = (state == WRITE) ? 1'b1 : 1'b0;
endmodule
| 6.752458 |
module select (
sel,
addr_in,
addr_fsm_in,
w_in,
addr_out,
w_out
);
input sel;
input [5:0] addr_in;
input [5:0] addr_fsm_in;
input w_in;
output [5:0] addr_out;
output w_out;
assign addr_out = sel ? addr_in : addr_fsm_in;
assign w_out = sel & w_in;
endmodule
| 7.910302 |
module TinyAESTopTestbench;
localparam RESET_PERIOD = 200000; //in pSec
parameter CLKIN_PERIOD = 5000;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wire sys_rst;
reg sys_clk_i;
wire sys_clk_p;
wire sys_clk_n;
//**************************************************************************//
// Reset Generation
//**************************************************************************//
initial begin
sys_rst_n = 1'b0;
#RESET_PERIOD sys_rst_n = 1'b1;
end
assign sys_rst = ~sys_rst_n;
//**************************************************************************//
// Clock Generation
//**************************************************************************//
initial sys_clk_i = 1'b0;
always sys_clk_i = #(CLKIN_PERIOD / 2.0) ~sys_clk_i;
assign sys_clk_p = sys_clk_i;
assign sys_clk_n = ~sys_clk_i;
wire uart_txd;
reg uart_rxd = 0;
always @(posedge sys_clk_p) uart_rxd <= ~uart_rxd;
//--------------------------------------------------------------------------
// CUT
//--------------------------------------------------------------------------
tiny_aes_vc707 CUT (
.sys_clk_p(sys_clk_p),
.sys_clk_n(sys_clk_n),
.sys_rst(sys_rst),
.uart_txd(uart_txd),
.uart_rxd(uart_rxd)
);
//--------------------------------------------------------------------------
endmodule
| 6.753723 |
module top (
input clk,
output D1,
output D2,
output D3,
output D4,
output D5,
output D6,
output D7,
output D8,
output uart_txd,
input uart_rxd,
output i2c_scl,
inout i2c_sda,
output spi_sclk,
output spi_mosi,
input spi_miso,
output spi_cs,
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
wire [7:0] P1_out;
wire [7:0] P2_out;
wire i2c_scl;
wire i2c_sda_out;
wire i2c_sda_in;
wire i2c_sda_oen;
assign D1 = P1_out[0];
assign D2 = P1_out[1];
assign D3 = P1_out[2];
assign D4 = P1_out[3];
assign D5 = P1_out[4];
assign D6 = P1_out[5];
assign D7 = P1_out[6];
assign D8 = P1_out[7];
SB_IO #(
.PIN_TYPE(6'b1010_01),
.PULLUP (1'b0)
) i2c_sda_pin (
.PACKAGE_PIN(i2c_sda),
.OUTPUT_ENABLE(i2c_sda_oen),
.D_OUT_0(i2c_sda_out),
.D_IN_0(i2c_sda_in)
);
iceZ0mb1e core (
.clk(clk),
.uart_txd(uart_txd),
.uart_rxd(uart_rxd),
.i2c_scl(i2c_scl),
.i2c_sda_in(i2c_sda_in),
.i2c_sda_out(i2c_sda_out),
.i2c_sda_oen(i2c_sda_oen),
.spi_sclk(spi_sclk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_cs(spi_cs),
.P1_out(P1_out),
.P1_in(8'h55),
.P1_oen(),
.P2_out(P2_out),
.P2_in(8'hAA),
.P2_oen(),
.debug()
);
// ================================================================
// ================================================================
// ================================================================
wire CLK = clk;
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
// look in pins.pcf for all the pin names on the TinyFPGA BX board
////////
// make a simple blink circuit
////////
// keep track of time and location in blink_pattern
reg [25:0] blink_counter;
// pattern that will be flashed over the LED over time
wire [31:0] blink_pattern = 32'b101010001110111011100010101;
// increment the blink_counter every clock
always @(posedge CLK) begin
blink_counter <= blink_counter + 1;
end
// light up the LED according to the pattern
// assign LED = blink_pattern[blink_counter[25:21]];
assign LED = P1_out[0]; // blink_pattern[blink_counter[25:21]];
endmodule
| 7.233807 |
module tinycpu(clk,reset,run,in,cs,pcout,irout,qtop,abus,dbus,out);
input [0:0] clk,reset,run;
input [15:0] in;
output [2:0] cs;
output [15:0] irout,qtop,dbus,out;
output [11:0] pcout,abus;
wire [15] qnext,ramout,aluout;
reg [11:0] abus;
reg halt,cont,pcinc,push,pop,abus2pc,dbus2ir,dbus2qtop,dbus2ram,dbus2obuf,pc2abus,
ir2abus,ir2dbus,qtop2dbus,alu2dbus,ram2dbus,in2dbus;
counter #(12) pc0(.clk(clk),.reset(reset),.load(abus2pc),.inc(pcinc),.d(abus),.q(pcout));
counter #(16) ir0(.clk(clk),.reset(reset),.load(dbus2ir),.inc(0),.d(dbus),.q(irout));
state state0(.clk(clk),.reset(reset),.run(run),.cont(cont),.halt(halt),.cs(cs));
stack satck0(.clk(clk),.reset(reset),.load(dbus2qtop),.push(push),.pop(pop),
.d(dbus),.qtop(qtop),.qnext(qnext));
alu alu0(.a(qtop),.b(qnext),.f(irout[4:0]),.s(aluout));
ram #(16,12,4096) ram0(.clk(clk),.load(dbus2ram),.addr(abus),.d(dbus),.q(ramout));
counter #(16) obuf0(.clk(clk),.reset(reset),.load(dbus2obuf),.inc(0),.d(dbus),.q(out));
always @(pc2abus or ir2abus or pcout or irout)
if(pc2abus)
abus = pcout;
else if(ir2abus)
abus = irout[11:0];
else
abus = 12'hxxx;
assign dbus = ir2dbus ? {{4{irout[11]}},irout[11:0]} : 16'hzzzz;
assign dbus = qtop2dbus ? qtop : 16'hzzzz;
assign dbus = ram2dbus ? ramout : 16'hzzzz;
assign dbus = in2dbus ? in : 16'hzzzz;
always @(cs or irout or qtop)
begin
halt = 0;
cont = 0;
pcinc = 0;
push = 0;
pop = 0;
abus2pc = 0;
dbus2ir = 0;
dbus2qtop = 0;
dbus2ram = 0;
dbus2obuf = 0;
pc2abus = 0;
ir2abus = 0;
ir2dbus = 0;
qtop2dbus = 0;
alu2dbus = 0;
ram2dbus = 0;
in2dbus = 0;
if(cs == `FETCHA)
begin
pcinc = 1;
pc2abus = 1;
end
else if(cs == `FETCHB)
begin
ram2dbus = 1;
dbus2ir = 1;
end
else if(cs == `EXCHA)
case(irout[15:12])
`PUSHI:
begin
ir2dbus = 1;
dbus2qtop = 1;
push = 1;
end
`PUSH:
begin
ir2abus = 1;
cont = 1;
end
`POP:
begin
ir2abus = 1;
qtop2dbus = 1;
dbus2ram = 1;
pop = 1;
end;
`JMP:
begin
ir2abus = 1;
abus2pc = 1;
end
`JZ:
begin
if(qtop == 0)
begin
ir2abus = 1;
abus2pc = 1;
end
pop = 1;
end
`JNZ:
begin
if(qtop != 0)
begin
ir2abus = 1;
abus2pc = 1;
end
pop = 1;
end
`IN:
begin
in2dbus = 1;
dbus2obuf = 1;
push = 1;
end
`OUT:
begin
qtop2dbus = 1;
dbus2obuf = 1;
pop = 1;
end
`OP:
begin
alu2dbus = 1;
dbus2qtop = 1;
if(irout[4] == )
pop = 1;
end
default:
halt = 1;
endcase
else if(cs == `EXCHB)
if(irout[15:12] == `PUSH)
begin
ram2dbus = 1;
dbus2qtop = 1;
push = 1;
end
end
endmodule
| 6.540244 |
module tinyEVR #(
parameter EVSTROBE_COUNT = 126,
parameter DEBUG = "false",
parameter TIMESTAMP_WIDTH = 64
) (
input wire evrRxClk,
(*mark_debug=DEBUG*) input [15:0] evrRxWord,
(*mark_debug=DEBUG*) input [ 1:0] evrCharIsK,
(*mark_debug=DEBUG*) output wire ppsMarker,
(*mark_debug=DEBUG*) output wire timestampValid,
(*mark_debug=DEBUG*) output wire [TIMESTAMP_WIDTH-1:0] timestamp,
(*mark_debug=DEBUG*) output wire [ 7:0] distributedDataBus,
output wire [ EVSTROBE_COUNT:1] evStrobe
);
tinyEVRcommon #(
.ACTION_RAM_WIDTH(0),
.EVSTROBE_COUNT(EVSTROBE_COUNT),
.DEBUG(DEBUG),
.TIMESTAMP_WIDTH(TIMESTAMP_WIDTH)
) tinyEVRcommon (
.evrRxClk(evrRxClk),
.evrRxWord(evrRxWord),
.evrCharIsK(evrCharIsK),
.ppsMarker(ppsMarker),
.timestampValid(timestampValid),
.timestamp(timestamp),
.distributedDataBus(distributedDataBus),
.action(evStrobe),
.sysClk(1'b0),
.sysActionWriteEnable(1'b0),
.sysActionAddress(8'h00),
.sysActionData(1'b0)
);
endmodule
| 7.146152 |
module smallEVR #(
parameter ACTION_WIDTH = 1,
parameter DEBUG = "false",
parameter TIMESTAMP_WIDTH = 64
) (
input wire evrRxClk,
(*mark_debug=DEBUG*) input [15:0] evrRxWord,
(*mark_debug=DEBUG*) input [ 1:0] evrCharIsK,
(*mark_debug=DEBUG*) output wire ppsMarker,
(*mark_debug=DEBUG*) output wire timestampValid,
(*mark_debug=DEBUG*) output wire [TIMESTAMP_WIDTH-1:0] timestamp,
(*mark_debug=DEBUG*) output wire [ 7:0] distributedDataBus,
(*mark_debug=DEBUG*) output wire [ ACTION_WIDTH-1:0] action,
input sysClk,
input sysActionWriteEnable,
input [ 7:0] sysActionAddress,
input [ACTION_WIDTH-1:0] sysActionData
);
tinyEVRcommon #(
.ACTION_RAM_WIDTH(ACTION_WIDTH),
.EVSTROBE_COUNT(0),
.DEBUG(DEBUG),
.TIMESTAMP_WIDTH(TIMESTAMP_WIDTH)
) tinyEVRcommon (
.evrRxClk(evrRxClk),
.evrRxWord(evrRxWord),
.evrCharIsK(evrCharIsK),
.ppsMarker(ppsMarker),
.timestampValid(timestampValid),
.timestamp(timestamp),
.distributedDataBus(distributedDataBus),
.action(action),
.sysClk(sysClk),
.sysActionWriteEnable(sysActionWriteEnable),
.sysActionAddress(sysActionAddress),
.sysActionData(sysActionData)
);
endmodule
| 7.50974 |
module tinyEVRcommon #(
parameter ACTION_RAM_WIDTH = 0,
parameter EVSTROBE_COUNT = 126,
parameter DEBUG = "false",
parameter TIMESTAMP_WIDTH = 64,
parameter ACT_MSB = ACTION_RAM_WIDTH ? ACTION_RAM_WIDTH - 1 : EVSTROBE_COUNT,
parameter ACT_LSB = ACTION_RAM_WIDTH ? 0 : 1
) (
input wire evrRxClk,
(*mark_debug=DEBUG*) input [15:0] evrRxWord,
(*mark_debug=DEBUG*) input [ 1:0] evrCharIsK,
(*mark_debug=DEBUG*) output wire ppsMarker,
(*mark_debug=DEBUG*) output reg timestampValid = 0,
(*mark_debug=DEBUG*) output wire [TIMESTAMP_WIDTH-1:0] timestamp,
(*mark_debug=DEBUG*) output wire [ 7:0] distributedDataBus,
output wire [ ACT_MSB:ACT_LSB] action,
input sysClk,
input sysActionWriteEnable,
input [ 7:0] sysActionAddress,
input [(ACTION_RAM_WIDTH?ACTION_RAM_WIDTH-1 : 0):0] sysActionData
);
localparam SECONDS_WIDTH = TIMESTAMP_WIDTH / 2;
localparam TICKS_WIDTH = TIMESTAMP_WIDTH / 2;
reg [SECONDS_WIDTH-1:0] tsSeconds = 0;
reg [ TICKS_WIDTH-1:0] tsTicks = 0;
assign timestamp = {tsSeconds, tsTicks};
localparam EVCODE_SHIFT_ZERO = 8'h70;
localparam EVCODE_SHIFT_ONE = 8'h71;
localparam EVCODE_SECONDS_MARKER = 8'h7D;
(*mark_debug=DEBUG*)reg [ SECONDS_WIDTH-1:0] shiftReg;
(*mark_debug=DEBUG*)reg [$clog2(SECONDS_WIDTH)-1:0] bitsLeft = SECONDS_WIDTH - 1;
(*mark_debug=DEBUG*) reg enoughBits = 0, tooManyBits = 0;
wire [7:0] evCode = evrRxWord[7:0];
assign distributedDataBus = evrRxWord[15:8];
wire evCodeValid = !evrCharIsK[0];
always @(posedge evrRxClk) begin
// Update time stamp seconds and clear time stamp ticks
// on arrival of 'pulse per second' marker event code.
if (evCodeValid && (evCode == EVCODE_SECONDS_MARKER)) begin
if (enoughBits && !tooManyBits) begin
tsSeconds <= shiftReg;
timestampValid <= 1;
end else if (timestampValid) begin
tsSeconds <= tsSeconds + 1;
end
tsTicks <= 0;
bitsLeft <= SECONDS_WIDTH - 1;
enoughBits <= 0;
tooManyBits <= 0;
end else if (tsTicks[TICKS_WIDTH-1] == 0) begin
tsTicks <= tsTicks + 1;
end else begin
timestampValid <= 0;
end
// Shift in another bit of upcoming seconds
if (evCodeValid && ((evCode == EVCODE_SHIFT_ZERO) || (evCode == EVCODE_SHIFT_ONE))) begin
bitsLeft <= bitsLeft - 1;
if (enoughBits) tooManyBits <= 1;
if (bitsLeft == 0) enoughBits <= 1;
shiftReg <= {shiftReg[SECONDS_WIDTH-2:0], evCode[0]};
end
end
// Rely on the optimizer to clean out all unused event strobes
genvar e;
wire [254:1] evStrobe;
assign ppsMarker = evStrobe[EVCODE_SECONDS_MARKER];
for (e = 1; e <= 254; e = e + 1) begin : evstr
reg evs;
always @(posedge evrRxClk) begin
evs <= (evCodeValid && (evCode == e));
end
assign evStrobe[e] = evs;
end
generate
if (ACTION_RAM_WIDTH > 0) begin
//
// Traditional lookup-table based actions
//
reg [ACTION_RAM_WIDTH-1:0] actionRAM[0:255], actionRAMQ, actionBus;
reg ramQisValid = 0;
always @(posedge sysClk) begin
if (sysActionWriteEnable) begin
actionRAM[sysActionAddress] <= sysActionData;
end
end
always @(posedge evrRxClk) begin
ramQisValid <= evCodeValid;
actionRAMQ <= actionRAM[evCode];
actionBus <= ramQisValid ? actionRAMQ : 0;
end
assign action = actionBus;
end else begin
//
// Individual strobes per event
//
for (e = 1; e <= EVSTROBE_COUNT; e = e + 1) begin : evact
assign action[e] = evStrobe[e];
end
end
endgenerate
endmodule
| 7.47872 |
module tinyEVR_tb;
parameter TIMESTAMP_WIDTH = 64;
parameter ACTION_WIDTH = 4;
parameter EVSTROBE_COUNT = 126;
parameter EVCODE_SHIFT_ZERO = 8'h70;
parameter EVCODE_SHIFT_ONE = 8'h71;
parameter EVCODE_SECONDS_MARKER = 8'h7D;
reg sysClk = 1;
reg sysActionWriteEnable = 1'b0;
reg [ 7:0] sysActionAddress = {8{1'bx}};
reg [ACTION_WIDTH-1:0] sysActionData = {ACTION_WIDTH{1'bx}};
reg evrClk = 1;
reg [ 15:0] evrRxWord = 16'hx;
reg [ 1:0] evrCharIsK = 2'hx;
wire ppsMarker, timestampValid;
wire ppsMarker_s, timestampValid_s;
wire [TIMESTAMP_WIDTH-1:0] timestamp, timestamp_s;
wire [EVSTROBE_COUNT:1] evStrobe;
wire [ACTION_WIDTH-1:0] action;
tinyEVR #(
.EVSTROBE_COUNT(EVSTROBE_COUNT)
) tinyEVR (
.evrRxClk(evrClk),
.evrRxWord(evrRxWord),
.evrCharIsK(evrCharIsK),
.ppsMarker(ppsMarker),
.timestampValid(timestampValid),
.timestamp(timestamp),
.evStrobe(evStrobe)
);
smallEVR #(
.ACTION_WIDTH(ACTION_WIDTH)
) smallEVR (
.evrRxClk(evrClk),
.evrRxWord(evrRxWord),
.evrCharIsK(evrCharIsK),
.ppsMarker(ppsMarker_s),
.timestampValid(timestampValid_s),
.timestamp(timestamp_s),
.action(action),
.sysClk(sysClk),
.sysActionWriteEnable(sysActionWriteEnable),
.sysActionAddress(sysActionAddress),
.sysActionData(sysActionData)
);
always begin
#5 sysClk <= !sysClk;
end
always begin
#4 evrClk <= !evrClk;
end
integer i;
reg fail = 0;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("tinyEVR.vcd");
$dumpvars(0, tinyEVR_tb);
end
#40;
for (i = 0; i < 256; i += 1) begin
setAction(i, 4'b0000);
end
setAction(EVCODE_SECONDS_MARKER, 4'b0010);
setAction(8'hBC, 4'b1111);
#40;
sendEvent(EVCODE_SECONDS_MARKER);
check(32'h00000000);
#100;
sendSeconds(32'h12345678);
#100;
sendEvent(EVCODE_SECONDS_MARKER);
check(32'h12345678);
#200;
sendEvent(EVCODE_SECONDS_MARKER);
check(32'h12345679);
#200;
sendSeconds(32'h12345678);
#100;
sendSeconds(32'h12345678);
#100;
sendEvent(EVCODE_SECONDS_MARKER);
check(32'h1234567A);
#1000;
if (fail) begin
$display("FAIL");
$stop(0);
end else begin
$display("PASS");
$finish(0);
end
end
task setAction;
input [7:0] evCode;
input [ACTION_WIDTH-1:0] evAction;
begin
@(posedge sysClk) begin
sysActionWriteEnable <= 1'b1;
sysActionAddress <= evCode;
sysActionData <= evAction;
end
@(posedge sysClk) begin
sysActionWriteEnable <= 1'b0;
sysActionAddress <= {8{1'bx}};
sysActionData <= {ACTION_WIDTH{1'bx}};
end
end
endtask
task sendSeconds;
input [31:0] arg;
begin : sendSec
integer i;
for (i = 0; i < 32; i += 1) begin
sendEvent(arg[31-i] ? EVCODE_SHIFT_ONE : EVCODE_SHIFT_ZERO);
end
end
endtask
task sendEvent;
input [7:0] arg;
begin
@(posedge evrClk) begin
evrRxWord[7:0] = arg;
evrCharIsK = 2'bx0;
end
@(posedge evrClk) begin
evrRxWord[7:0] = 8'h00;
evrCharIsK = 2'bx0;
end
@(posedge evrClk) begin
evrRxWord[7:0] = 8'hBC;
evrCharIsK = 2'bx1;
end
@(posedge evrClk) begin
evrRxWord[7:0] = 8'h00;
evrCharIsK = 2'bx0;
end
@(posedge evrClk);
end
endtask
task check;
input [31:0] arg;
reg [31:0] seconds;
begin
seconds = timestamp[32+:32];
$display("%x %x %s", arg, seconds, (arg == seconds) ? " OK" : "BAD");
if (arg != seconds) fail = 1;
end
endtask
endmodule
| 6.738797 |
module TinyFPGA_B (
//output pin1_usb_dp,
//inout pin2_usb_dn,
input pin3_clk_16mhz, // 16MHz clock
//output pin4,
//output pin5,
output pin6, // Seven unused LEDs: 6 to 12
output pin7,
output pin8,
output pin9,
output pin10,
output pin11,
output pin12,
output pin13, // Debounced output
//inout pin14_sdo,
//inout pin15_sdi,
//inout pin16_sck,
//inout pin17_ss,
//inout pin18,
//inout pin19,
//inout pin20,
//inout pin21,
//inout pin22,
//inout pin23,
inout pin24 // Raw button
);
// Set the other seven LEDs off
assign pin6 = 0;
assign pin7 = 0;
assign pin8 = 0;
assign pin9 = 0;
assign pin10 = 0;
assign pin11 = 0;
assign pin12 = 0;
debounce #(16_000_000, 100) // 1/100th of a second delay
dut(
pin3_clk_16mhz,
pin24,
pin13
);
endmodule
| 6.592493 |
module TinyFPGA_B (
input CLK, // 16MHz clock
output LED, // User/boot LED next to power LED
output USBPU // USB pull-up resistor
);
reg [23:0] counter;
always @(posedge CLK) counter <= counter + 1;
// drive USB pull-up resistor to '0' to disable USB
assign USBPU = 0;
assign LED = counter[23];
endmodule
| 6.592493 |
module TinyMIPS_tb ();
// Regfile Data
reg clk;
reg regwrite;
reg [2:0] ra1;
reg [2:0] ra2;
reg [2:0] wa;
reg [7:0] wd;
wire [7:0] rd1, rd2;
// ALU Control Data
reg [5:0] funct;
reg [1:0] aluop;
wire [2:0] alucont;
// ALU Data
wire [7:0] result;
regfile reg1 (
.rd1(rd1),
.rd2(rd2),
.clk(clk),
.regwrite(regwrite),
.ra1(ra1),
.ra2(ra2),
.wa(wa),
.wd(wd)
);
alu alu (
.result(result),
.a(rd1),
.b(rd2),
.alucont(alucont)
);
alucontrol alucontroller (
.alucont(alucont),
.aluop (aluop),
.funct (funct)
);
initial begin
// Initialize inputs
clk = 0;
ra1 = 3'b001; // Read from register s1
ra2 = 3'b010; // Read from register s2
wa = 3'b001; // Address to write to (currently s1)
aluop = 2'b11; // Set to default
funct = 6'b100000; // Set to add
#2 regwrite = 1'b1;
wd <= 8'b00000001;
#2 regwrite = 1'b0;
wa = 3'b010;
#2 regwrite = 1'b1;
wd <= 8'b00000010;
// Add
#2 wa = 3'b011;
#2 funct = 6'b100000;
#2 wd = result;
#2 regwrite = 1'b1;
#2 regwrite = 1'b0;
#2 $display("Contents of s3: %d +%d =%d", rd1, rd2, wd);
// Sub
#2 wa = 3'b100;
#2 funct = 6'b100010;
#2 wd = result;
#2 regwrite = 1'b1;
#2 regwrite = 1'b0;
#2 $display("Contents of s3: %d -%d =%d", rd1, rd2, wd);
// AND
#2 wa = 3'b101;
#2 funct = 6'b100100;
#2 wd = result;
#2 regwrite = 1'b1;
#2 regwrite = 1'b0;
#2 $display("Contents of s3: %d &%d=%d", rd1, rd2, wd);
// OR
#2 wa = 3'b110;
#2 funct = 6'b100101;
#2 wd = result;
#2 regwrite = 1'b1;
#2 regwrite = 1'b0;
#2 $display("Contents of s3: %d |%d=%d", rd1, rd2, wd);
// slt
#2 wa = 3'b111;
#2 funct = 6'b101010;
#2 wd = result;
#2 regwrite = 1'b1;
#2 regwrite = 1'b0;
#2 $display("Contents of s3: slt(%d,%d) = %d", rd1, rd2, wd);
#10 $finish;
end
always begin
#1 clk = ~clk;
end
initial begin
//$display("\t\ttime, \ta,\tb,\tsel,\t\tresult");
//$monitor("%d,\t%b,\t%b,\t%b,\t\t%d",$time,a,b,sel,result);
// Open a db file for saving simulation data
$shm_open("TinyMIPS_tb.db");
// Collect al signals (hierarchically) from the module
$shm_probe(TinyMIPS_tb, "AS");
end
endmodule
| 6.629121 |
module rv2isa_InstUnpack (
// Packed message
input [`RV2ISA_INST_NBITS-1:0] inst,
// Packed fields
output [`RV2ISA_INST_OPCODE_NBITS-1:0] opcode,
output [ `RV2ISA_INST_RD_NBITS-1:0] rd,
output [ `RV2ISA_INST_RS1_NBITS-1:0] rs1,
output [ `RV2ISA_INST_RS2_NBITS-1:0] rs2,
output [`RV2ISA_INST_FUNCT3_NBITS-1:0] funct3,
output [`RV2ISA_INST_FUNCT7_NBITS-1:0] funct7,
output [ `RV2ISA_INST_CSR_NBITS-1:0] csr
);
assign opcode = inst[`RV2ISA_INST_OPCODE];
assign rd = inst[`RV2ISA_INST_RD];
assign rs1 = inst[`RV2ISA_INST_RS1];
assign rs2 = inst[`RV2ISA_INST_RS2];
assign funct3 = inst[`RV2ISA_INST_FUNCT3];
assign csr = inst[`RV2ISA_INST_CSR];
endmodule
| 8.211707 |
module tinytot (
input clk,
input reset
);
wire xpc10;
always @(posedge clk) begin
//Start HPR tinytot.exe
if ((xpc10 == 0 /*0:US*/)) $finish(0);
//End HPR tinytot.exe
end
//Total area 0
// Total state bits in module = 0 bits.
// Total number of leaf cells = 0
endmodule
| 7.306575 |
module aes_128 (
clk,
state,
key,
out
);
input clk;
input [127:0] state, key;
output [127:0] out;
reg [127:0] s0, k0;
wire [127:0] s1, s2, s3, s4, s5, s6, s7, s8, s9,
k1, k2, k3, k4, k5, k6, k7, k8, k9,
k0b, k1b, k2b, k3b, k4b, k5b, k6b, k7b, k8b, k9b;
always @(posedge clk) begin
s0 <= state ^ key;
k0 <= key;
end
expand_key_128
a1 (
clk,
k0,
k1,
k0b,
8'h1
),
a2 (
clk,
k1,
k2,
k1b,
8'h2
),
a3 (
clk,
k2,
k3,
k2b,
8'h4
),
a4 (
clk,
k3,
k4,
k3b,
8'h8
),
a5 (
clk,
k4,
k5,
k4b,
8'h10
),
a6 (
clk,
k5,
k6,
k5b,
8'h20
),
a7 (
clk,
k6,
k7,
k6b,
8'h40
),
a8 (
clk,
k7,
k8,
k7b,
8'h80
),
a9 (
clk,
k8,
k9,
k8b,
8'h1b
),
a10 (
clk,
k9
,,
k9b,
8'h36
);
one_round
r1 (
clk,
s0,
k0b,
s1
),
r2 (
clk,
s1,
k1b,
s2
),
r3 (
clk,
s2,
k2b,
s3
),
r4 (
clk,
s3,
k3b,
s4
),
r5 (
clk,
s4,
k4b,
s5
),
r6 (
clk,
s5,
k5b,
s6
),
r7 (
clk,
s6,
k6b,
s7
),
r8 (
clk,
s7,
k7b,
s8
),
r9 (
clk,
s8,
k8b,
s9
);
final_round rf (
clk,
s9,
k9b,
out
);
endmodule
| 6.624619 |
module one_round (
clk,
state_in,
key,
state_out
);
input clk;
input [127:0] state_in, key;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3,
z0, z1, z2, z3,
p00, p01, p02, p03,
p10, p11, p12, p13,
p20, p21, p22, p23,
p30, p31, p32, p33,
k0, k1, k2, k3;
assign {k0, k1, k2, k3} = key;
assign {s0, s1, s2, s3} = state_in;
table_lookup
t0 (
clk,
s0,
p00,
p01,
p02,
p03
),
t1 (
clk,
s1,
p10,
p11,
p12,
p13
),
t2 (
clk,
s2,
p20,
p21,
p22,
p23
),
t3 (
clk,
s3,
p30,
p31,
p32,
p33
);
assign z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0;
assign z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1;
assign z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2;
assign z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3;
always @(posedge clk) state_out <= {z0, z1, z2, z3};
endmodule
| 7.018166 |
module final_round (
clk,
state_in,
key_in,
state_out
);
input clk;
input [127:0] state_in;
input [127:0] key_in;
output reg [127:0] state_out;
wire [31:0] s0, s1, s2, s3, z0, z1, z2, z3, k0, k1, k2, k3;
wire [7:0] p00, p01, p02, p03, p10, p11, p12, p13, p20, p21, p22, p23, p30, p31, p32, p33;
assign {k0, k1, k2, k3} = key_in;
assign {s0, s1, s2, s3} = state_in;
S4
S4_1 (
clk,
s0,
{p00, p01, p02, p03}
),
S4_2 (
clk,
s1,
{p10, p11, p12, p13}
),
S4_3 (
clk,
s2,
{p20, p21, p22, p23}
),
S4_4 (
clk,
s3,
{p30, p31, p32, p33}
);
assign z0 = {p00, p11, p22, p33} ^ k0;
assign z1 = {p10, p21, p32, p03} ^ k1;
assign z2 = {p20, p31, p02, p13} ^ k2;
assign z3 = {p30, p01, p12, p23} ^ k3;
always @(posedge clk) state_out <= {z0, z1, z2, z3};
endmodule
| 7.609225 |
module S4 (
clk,
in,
out
);
input clk;
input [31:0] in;
output [31:0] out;
S
S_0 (
clk,
in[31:24],
out[31:24]
),
S_1 (
clk,
in[23:16],
out[23:16]
),
S_2 (
clk,
in[15:8],
out[15:8]
),
S_3 (
clk,
in[7:0],
out[7:0]
);
endmodule
| 6.592394 |
module T (
clk,
in,
out
);
input clk;
input [7:0] in;
output [31:0] out;
S s0 (
clk,
in,
out[31:24]
);
assign out[23:16] = out[31:24];
xS s4 (
clk,
in,
out[7:0]
);
assign out[15:8] = out[23:16] ^ out[7:0];
endmodule
| 6.667023 |
module up_counter #(
parameter END_VALUE = 30,
NB_BITS = 5
) (
input clk,
input reset,
input trigger,
output done
);
// on the falling edge of the trigger signal we start counting
// until a reset or a new falling edge trigger occurs
reg [NB_BITS:0] counter;
reg triggered;
assign done = (counter == END_VALUE) ? 1'b1 : 1'b0;
always @(posedge clk) begin : COUNTER
if (reset == 1'b1) begin
counter = {NB_BITS{1'b0}};
triggered = 1'b0;
end else if (trigger == 1'b1) begin
counter = {NB_BITS{1'b0}};
triggered = 1'b1;
end else if (triggered == 1'b1) begin
counter <= #1 counter + 1;
end
end
endmodule
| 6.602909 |
module for the Ascend chip.
//==============================================================================
module tiny_aes_vc707(
input sys_clk_p,
input sys_clk_n,
input sys_rst, // SW8
output uart_txd,
input uart_rxd
);
//------------------------------------------------------------------------------
// Constants
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Wires & Regs
//------------------------------------------------------------------------------
wire [127:0] CoreDataIn;
wire [127:0] CoreKey;
wire [127:0] CoreDataOut;
//------------------------------------------------------------------------------
// Clock
//------------------------------------------------------------------------------
wire Clock_Bufg, Clock, FastClock;
wire Locked, FastReset;
IBUFGDS ibufgds( .I( sys_clk_p),
.IB( sys_clk_n),
.O( Clock_Bufg));
BUFG bufg( .I( Clock_Bufg),
.O( Clock));
aes_clock ultra( .clk_in1( Clock),
.clk_out1( FastClock),
.reset( sys_rst),
.locked( Locked));
assign FastReset = ~Locked;
//------------------------------------------------------------------------------
// UART
//------------------------------------------------------------------------------
UART#( .ClockFreq( 300000000),
.Baud( 9600),
.Width( 256),
.Parity( 0),
.StopBits( 1))
uart( .Clock( FastClock),
.Reset( FastReset),
.DataIn( {128'b1, CoreDataOut}),
.DataInValid( 1'b1),
.DataInReady( ),
.DataOut( {CoreKey, CoreDataIn}),
.DataOutValid( ),
.DataOutReady( 1'b1),
.SIn( uart_rxd),
.SOut( uart_txd));
//------------------------------------------------------------------------------
// AES
//------------------------------------------------------------------------------
aes_128 tiny_aes( .clk( FastClock),
.state( CoreDataIn),
.key( CoreKey),
.out( CoreDataOut));
//------------------------------------------------------------------------------
endmodule
| 6.949754 |
module td_fused_top_ap_hmul_3_max_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
wire res;
reg [15:0] a_reg, b_reg, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
multiply_fp u_mult_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPMult_16 u_FPMult (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module td_fused_top_ap_hadd_6_full_dsp_16 (
input wire aclk,
input wire aclken,
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
output wire m_axis_result_tvalid,
output wire [15:0] m_axis_result_tdata
);
wire res;
reg [15:0] a_reg, b_reg, res_reg;
always @(posedge aclk) begin
if (aclken) begin
a_reg <= s_axis_a_tdata;
b_reg <= s_axis_b_tdata;
res_reg <= res;
end
end
`ifdef complex_dsp
adder_fp u_add_fp (
.a (a_reg),
.b (b_reg),
.out(res)
);
`else
FPAddSub u_FPAddSub (
.clk(),
.rst(1'b0),
.a(a_reg),
.b(b_reg),
.operation(1'b0),
.result(res),
.flags()
);
`endif
assign m_axis_result_tdata = res_reg;
endmodule
| 6.827284 |
module td_fused_top_ap_hcmp_0_no_dsp_16 (
input wire s_axis_a_tvalid,
input wire [15:0] s_axis_a_tdata,
input wire s_axis_b_tvalid,
input wire [15:0] s_axis_b_tdata,
input wire s_axis_operation_tvalid,
input wire [ 7:0] s_axis_operation_tdata,
output wire m_axis_result_tvalid,
output wire [ 7:0] m_axis_result_tdata
);
// TEMP - compare module not yet ready
// In the meantime, negate operand B, add them
// together, and return the sign bit of the result.
wire [15:0] b_negative;
wire [15:0] result;
assign b_negative = {~s_axis_b_tdata[15], s_axis_b_tdata[14:0]};
`ifdef complex_dsp
adder_fp u_add_fp (
.a (s_axis_a_tdata),
.b (b_negative),
.out(result)
);
`else
FPAddSub u_FPAddSub_2 (
.clk(),
.rst(1'b0),
.a(s_axis_a_tdata),
.b(b_negative),
.operation(1'b0),
.result(result),
.flags()
);
`endif
assign m_axis_result_tdata = {7'b0, result[15]};
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc491 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_434,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_434;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_434;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_434;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc492 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_435,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_435;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_435;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_435;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc493 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_436,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_436;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_436;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_436;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc498 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc499 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_251,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_251;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_251;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_251;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc500 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_252,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_252;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_252;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_252;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc501 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_253,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_253;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_253;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_253;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc506 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc512 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc513 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_218,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_218;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_218;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_218;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc514 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_219,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_219;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_219;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_219;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc515 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_220,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_220;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_220;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_220;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc520 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc521 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_141,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_141;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_141;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_141;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc522 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_142,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_142;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_142;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_142;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc523 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_143,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_143;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_143;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_143;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc528 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc534 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc535 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_108,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_108;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_108;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_108;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc536 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_109,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_109;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_109;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_109;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc537 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_110,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_110;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_110;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_110;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc542 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc543 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_31,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_31;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_31;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_31;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc544 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_32,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_32;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_32;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_32;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc545 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_33,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_33;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_33;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_33;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc550 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc556 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc557 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_431,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_431;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_431;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_431;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc558 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_432,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_432;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_432;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_432;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc559 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_433,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_433;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_433;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_433;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc565 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc566 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_354,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_354;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_354;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_354;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc567 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_355,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_355;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_355;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_355;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc568 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_356,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_356;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_356;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_356;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc573 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc574 (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp_272,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp_272;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp_272;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp_272;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 14;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd14;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP16_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP16_accum1_out_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_accum2_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 7;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_accum2_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd7;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP16_accum2_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP16_accum2_out_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 6;
parameter MEM_SIZE = 54;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd54;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 5,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input wire i_ce,
input wire i_write,
output wire i_full_n,
input wire i_ce0,
input wire i_we0,
input wire [AddressWidth-1:0] i_address0,
input wire [ DataWidth-1:0] i_d0,
output wire [ DataWidth-1:0] i_q0,
// target
input wire t_ce,
input wire t_read,
output wire t_empty_n,
input wire t_ce0,
input wire t_we0,
input wire [AddressWidth-1:0] t_address0,
input wire [ DataWidth-1:0] t_d0,
output wire [ DataWidth-1:0] t_q0
);
//------------------------Local signal-------------------
// control/status
reg [ IndexWidth-1:0] iptr = 1'b0; // initiator index
reg [ IndexWidth-1:0] tptr = 1'b0; // target index
reg [ IndexWidth:0] count = 1'b0; // count of written buffers
reg full_n = 1'b1; // whether all buffers are written
reg empty_n = 1'b0; // whether none of the buffers is written
wire push_buf; // finish writing a buffer
wire write_buf; // write a buffer
wire pop_buf; // finish reading a buffer
wire [AddressWidth+IndexWidth-1:0] memcore_iaddr;
wire [AddressWidth+IndexWidth-1:0] memcore_taddr;
//------------------------Instantiation------------------
assign memcore_iaddr = {i_address0, iptr};
assign memcore_taddr = {t_address0, tptr};
td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP16_ifmap_vec_memcore_U (
.reset (reset),
.clk (clk),
.address0(memcore_iaddr),
.ce0 (i_ce0),
.we0 (i_we0),
.d0 (i_d0),
.q0 (i_q0),
.address1(memcore_taddr),
.ce1 (t_ce0),
.we1 (t_we0),
.d1 (t_d0),
.q1 (t_q0)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++output+++++++++++++++++++++++++
assign i_full_n = full_n;
assign t_empty_n = empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++control/status+++++++++++++++++
assign push_buf = i_ce & i_write & full_n;
assign write_buf = i_ce & i_write;
assign pop_buf = t_ce & t_read & empty_n;
// iptr
always @(posedge clk) begin
if (reset == 1'b1) iptr <= 1'b0;
else if (push_buf) begin
if (iptr == BufferCount - 1'b1) iptr <= 1'b0;
else iptr <= iptr + 1'b1;
end
end
// tptr
always @(posedge clk) begin
if (reset == 1'b1) tptr <= 1'b0;
else if (pop_buf) begin
if (tptr == BufferCount - 1'b1) tptr <= 1'b0;
else tptr <= tptr + 1'b1;
end
end
// count
always @(posedge clk) begin
if (reset == 1'b1) count <= 1'b0;
else if (push_buf && !pop_buf) count <= count + 1'b1;
else if (!push_buf && pop_buf) count <= count - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1) full_n <= 1'b1;
else if (push_buf && !pop_buf && count == BufferCount - 2'd2) full_n <= 1'b0;
else if (!push_buf && pop_buf) full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1) empty_n <= 1'b0;
else if ((!write_buf && pop_buf && count == 1'b1) || (pop_buf && count == 1'b0))
empty_n <= 1'b0;
else if (write_buf && !pop_buf) empty_n <= 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 27;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP16_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd27;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP16_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP16_products_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum1_out_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 16;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd16;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0 #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 3,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input wire i_ce,
input wire i_write,
output wire i_full_n,
input wire i_ce0,
input wire i_we0,
input wire [AddressWidth-1:0] i_address0,
input wire [ DataWidth-1:0] i_d0,
output wire [ DataWidth-1:0] i_q0,
// target
input wire t_ce,
input wire t_read,
output wire t_empty_n,
input wire t_ce0,
input wire t_we0,
input wire [AddressWidth-1:0] t_address0,
input wire [ DataWidth-1:0] t_d0,
output wire [ DataWidth-1:0] t_q0
);
//------------------------Local signal-------------------
// control/status
reg [ IndexWidth-1:0] iptr = 1'b0; // initiator index
reg [ IndexWidth-1:0] tptr = 1'b0; // target index
reg [ IndexWidth:0] count = 1'b0; // count of written buffers
reg full_n = 1'b1; // whether all buffers are written
reg empty_n = 1'b0; // whether none of the buffers is written
wire push_buf; // finish writing a buffer
wire write_buf; // write a buffer
wire pop_buf; // finish reading a buffer
wire [AddressWidth+IndexWidth-1:0] memcore_iaddr;
wire [AddressWidth+IndexWidth-1:0] memcore_taddr;
//------------------------Instantiation------------------
assign memcore_iaddr = {i_address0, iptr};
assign memcore_taddr = {t_address0, tptr};
td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP47680_accum2_out_0_memcore_U (
.reset (reset),
.clk (clk),
.address0(memcore_iaddr),
.ce0 (i_ce0),
.we0 (i_we0),
.d0 (i_d0),
.q0 (i_q0),
.address1(memcore_taddr),
.ce1 (t_ce0),
.we1 (t_we0),
.d1 (t_d0),
.q1 (t_q0)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++output+++++++++++++++++++++++++
assign i_full_n = full_n;
assign t_empty_n = empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++control/status+++++++++++++++++
assign push_buf = i_ce & i_write & full_n;
assign write_buf = i_ce & i_write;
assign pop_buf = t_ce & t_read & empty_n;
// iptr
always @(posedge clk) begin
if (reset == 1'b1) iptr <= 1'b0;
else if (push_buf) begin
if (iptr == BufferCount - 1'b1) iptr <= 1'b0;
else iptr <= iptr + 1'b1;
end
end
// tptr
always @(posedge clk) begin
if (reset == 1'b1) tptr <= 1'b0;
else if (pop_buf) begin
if (tptr == BufferCount - 1'b1) tptr <= 1'b0;
else tptr <= tptr + 1'b1;
end
end
// count
always @(posedge clk) begin
if (reset == 1'b1) count <= 1'b0;
else if (push_buf && !pop_buf) count <= count + 1'b1;
else if (!push_buf && pop_buf) count <= count - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1) full_n <= 1'b1;
else if (push_buf && !pop_buf && count == BufferCount - 2'd2) full_n <= 1'b0;
else if (!push_buf && pop_buf) full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1) empty_n <= 1'b0;
else if ((!write_buf && pop_buf && count == 1'b1) || (pop_buf && count == 1'b0))
empty_n <= 1'b0;
else if (write_buf && !pop_buf) empty_n <= 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_ifmap_vec_0_0_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 7;
parameter MEM_SIZE = 128;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_ifmap_vec_0_0_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd128;
parameter AddressWidth = 32'd7;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP47680_ifmap_vec_0_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP47680_ifmap_vec_0_0_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_products_0_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 6;
parameter MEM_SIZE = 64;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47680_products_0_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd64;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP47680_products_0_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP47680_products_0_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 32;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd32;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum1_out_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum2_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 3;
parameter MEM_SIZE = 8;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum2_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd8;
parameter AddressWidth = 32'd3;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum2_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP47773_accum2_out_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 9;
parameter MEM_SIZE = 288;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd288;
parameter AddressWidth = 32'd9;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0 #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 8,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input wire i_ce,
input wire i_write,
output wire i_full_n,
input wire i_ce0,
input wire i_we0,
input wire [AddressWidth-1:0] i_address0,
input wire [ DataWidth-1:0] i_d0,
output wire [ DataWidth-1:0] i_q0,
// target
input wire t_ce,
input wire t_read,
output wire t_empty_n,
input wire t_ce0,
input wire t_we0,
input wire [AddressWidth-1:0] t_address0,
input wire [ DataWidth-1:0] t_d0,
output wire [ DataWidth-1:0] t_q0
);
//------------------------Local signal-------------------
// control/status
reg [ IndexWidth-1:0] iptr = 1'b0; // initiator index
reg [ IndexWidth-1:0] tptr = 1'b0; // target index
reg [ IndexWidth:0] count = 1'b0; // count of written buffers
reg full_n = 1'b1; // whether all buffers are written
reg empty_n = 1'b0; // whether none of the buffers is written
wire push_buf; // finish writing a buffer
wire write_buf; // write a buffer
wire pop_buf; // finish reading a buffer
wire [AddressWidth+IndexWidth-1:0] memcore_iaddr;
wire [AddressWidth+IndexWidth-1:0] memcore_taddr;
//------------------------Instantiation------------------
assign memcore_iaddr = {i_address0, iptr};
assign memcore_taddr = {t_address0, tptr};
td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP47773_ifmap_vec_0_memcore_U (
.reset (reset),
.clk (clk),
.address0(memcore_iaddr),
.ce0 (i_ce0),
.we0 (i_we0),
.d0 (i_d0),
.q0 (i_q0),
.address1(memcore_taddr),
.ce1 (t_ce0),
.we1 (t_we0),
.d1 (t_d0),
.q1 (t_q0)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++output+++++++++++++++++++++++++
assign i_full_n = full_n;
assign t_empty_n = empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++control/status+++++++++++++++++
assign push_buf = i_ce & i_write & full_n;
assign write_buf = i_ce & i_write;
assign pop_buf = t_ce & t_read & empty_n;
// iptr
always @(posedge clk) begin
if (reset == 1'b1) iptr <= 1'b0;
else if (push_buf) begin
if (iptr == BufferCount - 1'b1) iptr <= 1'b0;
else iptr <= iptr + 1'b1;
end
end
// tptr
always @(posedge clk) begin
if (reset == 1'b1) tptr <= 1'b0;
else if (pop_buf) begin
if (tptr == BufferCount - 1'b1) tptr <= 1'b0;
else tptr <= tptr + 1'b1;
end
end
// count
always @(posedge clk) begin
if (reset == 1'b1) count <= 1'b0;
else if (push_buf && !pop_buf) count <= count + 1'b1;
else if (!push_buf && pop_buf) count <= count - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1) full_n <= 1'b1;
else if (push_buf && !pop_buf && count == BufferCount - 2'd2) full_n <= 1'b0;
else if (!push_buf && pop_buf) full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1) empty_n <= 1'b0;
else if ((!write_buf && pop_buf && count == 1'b1) || (pop_buf && count == 1'b0))
empty_n <= 1'b0;
else if (write_buf && !pop_buf) empty_n <= 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 6.827284 |
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