code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module timer_ssp (
input clock,
input rst_n,
input [31:0] apb_addr,
input apb_sel,
input apb_write,
input apb_ena,
input [31:0] apb_wdata,
output reg [31:0] apb_rdata,
input [ 3:0] apb_pstb,
output apb_rready
);
localparam TIME0_LADDR = 8'h00;
localparam TIME0_HADDR = 8'h04;
localparam TIME0_CMPLADDR = 8'h08;
localparam TIME0_CMPHADDR = 8'h0C;
localparam TIME1_LADDR = 8'h10;
localparam TIME1_HADDR = 8'h14;
localparam TIME1_CMPLADDR = 8'h18;
localparam TIME1_CMPHADDR = 8'h1C;
localparam TIMEENA_ADDR = 8'h20;
reg [63:0] time0;
reg [63:0] time1;
reg [63:0] time0_cmp;
reg [63:0] time1_cmp;
wire [ 1:0] count_eq;
assign count_eq[0] = (time0 >= time0_cmp);
assign count_eq[1] = (time1 >= time1_cmp);
reg [1:0] tmr_ena;
assign apb_rready = 1'b1;
always @(posedge clock) begin
if (!rst_n) begin
time0 <= 64'h0000_0000_0000_0000;
time1 <= 64'h0000_0000_0000_0000;
time0_cmp <= 64'h0000_0000_0000_0000;
time1_cmp <= 64'h0000_0000_0000_0000;
time1_cmp <= 64'h0000_0000_0000_0000;
tmr_ena <= 2'b00;
apb_rdata <= 32'h0000_0000;
end else begin
if (apb_sel && apb_write && !apb_ena) begin
case (apb_addr[7:0])
TIME0_LADDR: begin
time0[31:0] <= apb_wdata;
end
TIME0_HADDR: begin
time0[63:32] <= apb_wdata;
end
TIME0_CMPLADDR: begin
time0_cmp[31:0] <= apb_wdata;
end
TIME0_CMPHADDR: begin
time0_cmp[63:32] <= apb_wdata;
end
TIME1_LADDR: begin
time1[31:0] <= apb_wdata;
end
TIME1_HADDR: begin
time1[63:32] <= apb_wdata;
end
TIME1_CMPLADDR: begin
time1_cmp[31:0] <= apb_wdata;
end
TIME1_CMPHADDR: begin
time1_cmp[63:32] <= apb_wdata;
end
TIMEENA_ADDR: begin
tmr_ena <= apb_wdata[1:0];
end
endcase
end else begin
// no autoreload
time0 <= tmr_ena[0] ? (time0 == time0_cmp) ? time0 : time0 + 64'h0000_0000_0000_0001 : 64'h0000_0000_0000_0000;
// auto reload
time1 <= tmr_ena[1] ? (time1 == time1_cmp) ? time1_cmp : time1 + 64'h0000_0000_0000_0001 : 64'h0000_0000_0000_0000;
end
if (apb_sel && !apb_write && !apb_ena) begin
case (apb_addr[7:0])
TIME0_LADDR: begin
apb_rdata <= time0[31:0];
end
TIME0_HADDR: begin
apb_rdata <= time0[63:32];
end
TIME0_CMPLADDR: begin
apb_rdata <= time0_cmp[31:0];
end
TIME0_CMPHADDR: begin
apb_rdata <= time0_cmp[63:32];
end
TIME1_LADDR: begin
apb_rdata <= time1[31:0];
end
TIME1_HADDR: begin
apb_rdata <= time1[63:32];
end
TIME1_CMPLADDR: begin
apb_rdata <= time1_cmp[31:0];
end
TIME1_CMPHADDR: begin
apb_rdata <= time1_cmp[63:32];
end
TIMEENA_ADDR: begin
apb_rdata <= {28'h0000000, 2'b00, count_eq};
end
default: begin
apb_rdata <= 32'h0000_0000;
end
endcase
end
end
end
endmodule
| 7.371588 |
module timer_stepper_test;
reg clk = 0;
reg [31:0] prescaler = 5;
reg run = 0;
wire [23:0] data;
time_stepper #(
.TIME_LENGTH(24)
) test (
clk,
prescaler,
run,
data
);
initial begin
$dumpfile("timer_stepper_test.v");
$dumpvars(0, timer_stepper_test);
#10 run <= 1;
#100 run <= 0;
#10 $finish;
end
always begin
#1 clk <= 1;
#2 clk <= 0;
#1 clk <= 0;
end
endmodule
| 7.661777 |
module timer_stream_adapter (
asyncTime_V,
synchTime_1_V_V_din,
synchTime_1_V_V_full_n,
synchTime_1_V_V_write,
synchTime_2_V_V_din,
synchTime_2_V_V_full_n,
synchTime_2_V_V_write,
ap_clk,
ap_rst
);
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
input [63:0] asyncTime_V;
output [63:0] synchTime_1_V_V_din;
input synchTime_1_V_V_full_n;
output synchTime_1_V_V_write;
output [63:0] synchTime_2_V_V_din;
input synchTime_2_V_V_full_n;
output synchTime_2_V_V_write;
input ap_clk;
input ap_rst;
wire Block_proc_U0_ap_start;
wire Block_proc_U0_ap_done;
wire Block_proc_U0_ap_continue;
wire Block_proc_U0_ap_idle;
wire Block_proc_U0_ap_ready;
wire [63:0] Block_proc_U0_synchTime_1_V_V_din;
wire Block_proc_U0_synchTime_1_V_V_write;
wire [63:0] Block_proc_U0_synchTime_2_V_V_din;
wire Block_proc_U0_synchTime_2_V_V_write;
wire ap_hs_continue;
Block_proc Block_proc_U0 (
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(Block_proc_U0_ap_start),
.ap_done(Block_proc_U0_ap_done),
.ap_continue(Block_proc_U0_ap_continue),
.ap_idle(Block_proc_U0_ap_idle),
.ap_ready(Block_proc_U0_ap_ready),
.synchTime_1_V_V_din(Block_proc_U0_synchTime_1_V_V_din),
.synchTime_1_V_V_full_n(synchTime_1_V_V_full_n),
.synchTime_1_V_V_write(Block_proc_U0_synchTime_1_V_V_write),
.synchTime_2_V_V_din(Block_proc_U0_synchTime_2_V_V_din),
.synchTime_2_V_V_full_n(synchTime_2_V_V_full_n),
.synchTime_2_V_V_write(Block_proc_U0_synchTime_2_V_V_write),
.asyncTime_V(asyncTime_V)
);
assign Block_proc_U0_ap_continue = 1'b1;
assign Block_proc_U0_ap_start = 1'b1;
assign ap_hs_continue = 1'b0;
assign synchTime_1_V_V_din = Block_proc_U0_synchTime_1_V_V_din;
assign synchTime_1_V_V_write = Block_proc_U0_synchTime_1_V_V_write;
assign synchTime_2_V_V_din = Block_proc_U0_synchTime_2_V_V_din;
assign synchTime_2_V_V_write = Block_proc_U0_synchTime_2_V_V_write;
endmodule
| 7.147767 |
module timer_stream_adapter_ap_rst_if #(
parameter RESET_ACTIVE_LOW = 0
) (
input wire din,
output wire dout
);
assign dout = (RESET_ACTIVE_LOW == 1) ? ~din : din;
endmodule
| 7.147767 |
module timer_stream_adapter_synchTime_1_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
// User signals
input wire [63:0] synchTime_1_V_V_din,
output wire synchTime_1_V_V_full_n,
input wire synchTime_1_V_V_write
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_read;
wire [ 0:0] fifo_empty_n;
wire [63:0] synchTime_1_V_V_dout;
wire [ 0:0] synchTime_1_V_V_empty_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [63:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [63:0] m_data;
//------------------------Instantiation------------------
// rs
timer_stream_adapter_synchTime_1_reg_slice #(
.N(64)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// synchTime_1_V_V_fifo
timer_stream_adapter_synchTime_1_fifo #(
.DATA_BITS (64),
.DEPTH_BITS(4)
) synchTime_1_V_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(synchTime_1_V_V_empty_n),
.full_n (synchTime_1_V_V_full_n),
.read (fifo_read),
.write (synchTime_1_V_V_write),
.dout (synchTime_1_V_V_dout),
.din (synchTime_1_V_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TVALID = m_valid;
assign TDATA = m_data[63:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = fifo_empty_n;
assign m_ready = TREADY;
assign s_data = {synchTime_1_V_V_dout};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_read = fifo_empty_n & s_ready;
assign fifo_empty_n = synchTime_1_V_V_empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.147767 |
module timer_stream_adapter_synchTime_1_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.147767 |
module timer_stream_adapter_synchTime_1_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.147767 |
module timer_stream_adapter_synchTime_2_if (
// AXI4-Stream singals
input wire ACLK,
input wire ARESETN,
output wire TVALID,
input wire TREADY,
output wire [63:0] TDATA,
// User signals
input wire [63:0] synchTime_2_V_V_din,
output wire synchTime_2_V_V_full_n,
input wire synchTime_2_V_V_write
);
//------------------------Local signal-------------------
// FIFO
wire [ 0:0] fifo_read;
wire [ 0:0] fifo_empty_n;
wire [63:0] synchTime_2_V_V_dout;
wire [ 0:0] synchTime_2_V_V_empty_n;
// register slice
wire [ 0:0] s_valid;
wire [ 0:0] s_ready;
wire [63:0] s_data;
wire [ 0:0] m_valid;
wire [ 0:0] m_ready;
wire [63:0] m_data;
//------------------------Instantiation------------------
// rs
timer_stream_adapter_synchTime_2_reg_slice #(
.N(64)
) rs (
.clk (ACLK),
.reset (ARESETN),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready)
);
// synchTime_2_V_V_fifo
timer_stream_adapter_synchTime_2_fifo #(
.DATA_BITS (64),
.DEPTH_BITS(4)
) synchTime_2_V_V_fifo (
.clk (ACLK),
.aclr (~ARESETN),
.empty_n(synchTime_2_V_V_empty_n),
.full_n (synchTime_2_V_V_full_n),
.read (fifo_read),
.write (synchTime_2_V_V_write),
.dout (synchTime_2_V_V_dout),
.din (synchTime_2_V_V_din)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++AXI4-Stream++++++++++++++++++++
assign TVALID = m_valid;
assign TDATA = m_data[63:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++Reigister Slice++++++++++++++++
assign s_valid = fifo_empty_n;
assign m_ready = TREADY;
assign s_data = {synchTime_2_V_V_dout};
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++FIFO+++++++++++++++++++++++++++
assign fifo_read = fifo_empty_n & s_ready;
assign fifo_empty_n = synchTime_2_V_V_empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 7.147767 |
module timer_stream_adapter_synchTime_2_fifo #(
parameter DATA_BITS = 8,
DEPTH_BITS = 4
) (
input wire clk,
input wire aclr,
output wire empty_n,
output wire full_n,
input wire read,
input wire write,
output wire [DATA_BITS-1:0] dout,
input wire [DATA_BITS-1:0] din
);
//------------------------Parameter----------------------
localparam DEPTH = 1 << DEPTH_BITS;
//------------------------Local signal-------------------
reg empty;
reg full;
reg [DEPTH_BITS-1:0] index;
reg [ DATA_BITS-1:0] mem [0:DEPTH-1];
//------------------------Body---------------------------
assign empty_n = ~empty;
assign full_n = ~full;
assign dout = mem[index];
// empty
always @(posedge clk or posedge aclr) begin
if (aclr) empty <= 1'b1;
else if (empty & write & ~read) empty <= 1'b0;
else if (~empty & ~write & read & (index == 1'b0)) empty <= 1'b1;
end
// full
always @(posedge clk or posedge aclr) begin
if (aclr) full <= 1'b0;
else if (full & read & ~write) full <= 1'b0;
else if (~full & ~read & write & (index == DEPTH - 2'd2)) full <= 1'b1;
end
// index
always @(posedge clk or posedge aclr) begin
if (aclr) index <= {DEPTH_BITS{1'b1}};
else if (~empty & ~write & read) index <= index - 1'b1;
else if (~full & ~read & write) index <= index + 1'b1;
end
// mem
always @(posedge clk) begin
if (~full & write) mem[0] <= din;
end
genvar i;
generate
for (i = 1; i < DEPTH; i = i + 1) begin : gen_sr
always @(posedge clk) begin
if (~full & write) mem[i] <= mem[i-1];
end
end
endgenerate
endmodule
| 7.147767 |
module timer_stream_adapter_synchTime_2_reg_slice #(
parameter N = 8 // data width
) (
// system signals
input wire clk,
input wire reset,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0] ZERO = 2'b10, ONE = 2'b11, TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [ 1:0] state;
reg [ 1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge clk) begin
if (load_p1) begin
if (load_p1_from_p2) data_p1 <= data_p2;
else data_p1 <= s_data;
end
end
// data_p2
always @(posedge clk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge clk) begin
if (~reset) s_ready_t <= 1'b0;
else if (state == ZERO) s_ready_t <= 1'b1;
else if (state == ONE && next == TWO) s_ready_t <= 1'b0;
else if (state == TWO && next == ONE) s_ready_t <= 1'b1;
end
// state
always @(posedge clk) begin
if (~reset) state <= ZERO;
else state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready) next = ONE;
else next = ZERO;
ONE:
if (~s_valid & m_ready) next = ZERO;
else if (s_valid & ~m_ready) next = TWO;
else next = ONE;
TWO:
if (m_ready) next = ONE;
else next = TWO;
default: next = ZERO;
endcase
end
endmodule
| 7.147767 |
module timer_stream_adapter_top (
synchTime_1_TVALID,
synchTime_1_TREADY,
synchTime_1_TDATA,
synchTime_2_TVALID,
synchTime_2_TREADY,
synchTime_2_TDATA,
aresetn,
aclk,
asyncTime_V
);
parameter RESET_ACTIVE_LOW = 1;
output synchTime_1_TVALID;
input synchTime_1_TREADY;
output [64 - 1:0] synchTime_1_TDATA;
output synchTime_2_TVALID;
input synchTime_2_TREADY;
output [64 - 1:0] synchTime_2_TDATA;
input aresetn;
input aclk;
input [64 - 1:0] asyncTime_V;
wire synchTime_1_TVALID;
wire synchTime_1_TREADY;
wire [64 - 1:0] synchTime_1_TDATA;
wire synchTime_2_TVALID;
wire synchTime_2_TREADY;
wire [64 - 1:0] synchTime_2_TDATA;
wire aresetn;
wire [64 - 1:0] sig_timer_stream_adapter_synchTime_1_V_V_din;
wire sig_timer_stream_adapter_synchTime_1_V_V_full_n;
wire sig_timer_stream_adapter_synchTime_1_V_V_write;
wire [64 - 1:0] sig_timer_stream_adapter_synchTime_2_V_V_din;
wire sig_timer_stream_adapter_synchTime_2_V_V_full_n;
wire sig_timer_stream_adapter_synchTime_2_V_V_write;
wire sig_timer_stream_adapter_ap_rst;
timer_stream_adapter timer_stream_adapter_U (
.synchTime_1_V_V_din(sig_timer_stream_adapter_synchTime_1_V_V_din),
.synchTime_1_V_V_full_n(sig_timer_stream_adapter_synchTime_1_V_V_full_n),
.synchTime_1_V_V_write(sig_timer_stream_adapter_synchTime_1_V_V_write),
.synchTime_2_V_V_din(sig_timer_stream_adapter_synchTime_2_V_V_din),
.synchTime_2_V_V_full_n(sig_timer_stream_adapter_synchTime_2_V_V_full_n),
.synchTime_2_V_V_write(sig_timer_stream_adapter_synchTime_2_V_V_write),
.ap_rst(sig_timer_stream_adapter_ap_rst),
.ap_clk(aclk),
.asyncTime_V(asyncTime_V)
);
timer_stream_adapter_synchTime_1_if timer_stream_adapter_synchTime_1_if_U (
.ACLK(aclk),
.ARESETN(aresetn),
.synchTime_1_V_V_din(sig_timer_stream_adapter_synchTime_1_V_V_din),
.synchTime_1_V_V_full_n(sig_timer_stream_adapter_synchTime_1_V_V_full_n),
.synchTime_1_V_V_write(sig_timer_stream_adapter_synchTime_1_V_V_write),
.TVALID(synchTime_1_TVALID),
.TREADY(synchTime_1_TREADY),
.TDATA(synchTime_1_TDATA)
);
timer_stream_adapter_synchTime_2_if timer_stream_adapter_synchTime_2_if_U (
.ACLK(aclk),
.ARESETN(aresetn),
.synchTime_2_V_V_din(sig_timer_stream_adapter_synchTime_2_V_V_din),
.synchTime_2_V_V_full_n(sig_timer_stream_adapter_synchTime_2_V_V_full_n),
.synchTime_2_V_V_write(sig_timer_stream_adapter_synchTime_2_V_V_write),
.TVALID(synchTime_2_TVALID),
.TREADY(synchTime_2_TREADY),
.TDATA(synchTime_2_TDATA)
);
timer_stream_adapter_ap_rst_if #(
.RESET_ACTIVE_LOW(RESET_ACTIVE_LOW)
) ap_rst_if_U (
.dout(sig_timer_stream_adapter_ap_rst),
.din (aresetn)
);
endmodule
| 7.147767 |
module timer_sync (
input wire sys_rst,
input wire sys_clk,
input wire t, // external input clock
output wire t_rise,
output wire t_fall
);
// Latch
`ifdef TIME_SYNC_LATCH
reg t_latch;
always @(sys_clk, t) begin
if (sys_clk) t_latch <= t;
end
`endif
reg t_reg;
always @(posedge sys_clk) begin
if (sys_rst) t_reg <= 1'b0;
else
`ifdef TIME_SYNC_LATCH
t_reg <= t_latch;
`else
t_reg <= t;
`endif
end
// edge detect
reg t_reg2;
always @(posedge sys_clk) begin
if (sys_rst) t_reg2 <= 1'b0;
else t_reg2 <= t_reg;
end
assign t_rise = ~t_reg2 & t_reg;
assign t_fall = t_reg2 & ~t_reg;
endmodule
| 7.224187 |
module: timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module timer_t;
// Inputs
reg clk;
reg rst;
reg [23:0] tmr_period;
reg [23:0] tmr_compare;
// Outputs
wire [23:0] tmr_count;
wire flag;
// Instantiate the Unit Under Test (UUT)
timer uut (
.tmr_count(tmr_count),
.flag(flag),
.clk(clk),
.rst(rst),
.tmr_period(tmr_period),
.tmr_compare(tmr_compare)
);
always #50 clk = ~clk;
always #100 begin
$display("tmr_count");
$display(flag);
$stop;
end
initial begin
// Initialize Inputs
clk = 1;
rst = 0;
tmr_period = 24'h7;
tmr_compare = 24'h4;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst = 1; #1000;
tmr_compare = 24'h1; #1000;
tmr_compare = 24'h0; #1000;
tmr_compare = 24'h8; #1000;
tmr_compare = 24'h7; #1000;
end
endmodule
| 7.287821 |
module timer_tb;
reg RSTB;
reg clock;
reg power1, power2;
always #10 clock <= (clock === 1'b0);
initial begin
clock <= 0;
end
initial begin
$dumpfile("timer.vcd");
$dumpvars(0, timer_tb);
// Repeat cycles of 1000 clock edges as needed to complete testbench
repeat (50) begin
repeat (1000) @(posedge clock);
$display("+1000 cycles");
end
$display("%c[1;31m", 27);
`ifdef GL
$display("Monitor: Timeout, Test GPIO (GL) Failed");
`else
$display("Monitor: Timeout, Test GPIO (RTL) Failed");
`endif
$display("%c[0m", 27);
$finish;
end
wire [37:0] mprj_io; // Most of these are no-connects
wire [ 5:0] checkbits;
wire [31:0] countbits;
assign checkbits = mprj_io[37:32];
assign countbits = mprj_io[31:0];
assign mprj_io[3] = 1'b1; // Force CSB high.
wire flash_csb;
wire flash_clk;
wire flash_io0;
wire flash_io1;
wire gpio;
// Monitor
initial begin
wait (checkbits == 6'h0a);
`ifdef GL
$display("Monitor: Test Timer (GL) Started");
`else
$display("Monitor: Test Timer (RTL) Started");
`endif
/* Add checks here */
wait (checkbits == 6'h01);
$display(" countbits = 0x%x (should be 0xdcba7cfb)", countbits);
if (countbits !== 32'hdcba7cfb) begin
$display("Monitor: Test Timer Failed");
$finish;
end
wait (checkbits == 6'h02);
$display(" countbits = 0x%x (should be 0x19)", countbits);
if (countbits !== 32'h19) begin
$display("Monitor: Test Timer Failed");
$finish;
end
wait (checkbits == 6'h03);
$display(" countbits = %x (should be 0x0f)", countbits);
if (countbits !== ((32'h0f) | (3'b100))) begin
$display("Monitor: Test Timer Failed");
$finish;
end
wait (checkbits == 6'h04);
$display(" countbits = %x (should be 0x0f)", countbits);
if (countbits !== ((32'h0f) | (3'b100))) begin
$display("Monitor: Test Timer Failed");
$finish;
end
wait (checkbits == 6'h05);
$display(" countbits = %x (should be 0x12bc)", countbits);
if (countbits !== 32'h12bc) begin
$display("Monitor: Test Timer Failed");
$finish;
end
`ifdef GL
$display("Monitor: Test Timer (GL) Passed");
`else
$display("Monitor: Test Timer (RTL) Passed");
`endif
$finish;
end
initial begin
RSTB <= 1'b0;
#1000;
RSTB <= 1'b1; // Release reset
end
initial begin // Power-up sequence
power1 <= 1'b0;
power2 <= 1'b0;
#200;
power1 <= 1'b1;
#200;
power2 <= 1'b1;
end
always @(checkbits) begin
#1 $display("Timer state = %b (%d)", countbits, countbits);
end
wire VDD3V3;
wire VDD1V8;
wire VSS;
assign VDD3V3 = power1;
assign VDD1V8 = power2;
assign VSS = 1'b0;
// These are the mappings of mprj_io GPIO pads that are set to
// specific functions on startup:
//
// JTAG = mgmt_gpio_io[0] (inout)
// SDO = mgmt_gpio_io[1] (output)
// SDI = mgmt_gpio_io[2] (input)
// CSB = mgmt_gpio_io[3] (input)
// SCK = mgmt_gpio_io[4] (input)
// ser_rx = mgmt_gpio_io[5] (input)
// ser_tx = mgmt_gpio_io[6] (output)
// irq = mgmt_gpio_io[7] (input)
caravel uut (
.vddio (VDD3V3),
.vssio (VSS),
.vdda (VDD3V3),
.vssa (VSS),
.vccd (VDD1V8),
.vssd (VSS),
.vdda1 (VDD3V3),
.vdda2 (VDD3V3),
.vssa1 (VSS),
.vssa2 (VSS),
.vccd1 (VDD1V8),
.vccd2 (VDD1V8),
.vssd1 (VSS),
.vssd2 (VSS),
.clock (clock),
.gpio (gpio),
.mprj_io (mprj_io),
.flash_csb(flash_csb),
.flash_clk(flash_clk),
.flash_io0(flash_io0),
.flash_io1(flash_io1),
.resetb (RSTB)
);
spiflash #(
.FILENAME("timer.hex")
) spiflash (
.csb(flash_csb),
.clk(flash_clk),
.io0(flash_io0),
.io1(flash_io1),
.io2(), // not used
.io3() // not used
);
endmodule
| 6.888373 |
module: timer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module timer_test;
// Inputs
reg clk;
reg rst;
reg start;
reg endn;
// Outputs
wire [9:0] sec;
wire [2:0] remainder;
wire [1:0] digit;
wire [3:0] a;
// Instantiate the Unit Under Test (UUT)
timer uut (
.clk(clk),
.rst(rst),
.start(start),
.endn(endn),
// output
.sec(sec),
.remainder(remainder),
.digit(digit),
.a0(a[0]),
.a1(a[1]),
.a2(a[2]),
.a3(a[3])
);
integer i;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
#5;
rst = 1;
start = 1;
endn = 0;
// Wait 100 ns for global reset to finish
#100;
forever begin
clk = ~clk;
#5;
end
// Add stimulus here
end
always @(*)begin
if(sec==9'd1001)begin
endn = 1'b1;
end
end
endmodule
| 7.287821 |
module Timer_testbench;
/* Inicialização das variáveis de input */
reg count_tb, reset_tb, clk_tb;
reg signed [8:0] adder_tb;
/* Inicialização da variáveis de output */
wire [3:0] seconds0_tb, seconds1_tb, minutes0_tb;
wire [6:0] s0_7seg, s1_7seg, m0_7seg;
/* Inicialização do módulo a ser testado */
Timer UUT (
.reset(reset_tb),
.count(count_tb),
.clk(clk_tb),
.adder(adder_tb),
.seconds0(seconds0_tb),
.seconds1(seconds1_tb),
.minutes0(minutes0_tb)
);
/* Teste para o driver do display_timer */
display_timer Display (
.seconds0(seconds0_tb),
.seconds1(seconds1_tb),
.minutes0(minutes0_tb),
.seconds_lsd(s0_7seg),
.seconds_msd(s1_7seg),
.minutes(m0_7seg)
);
initial begin
/* Condições inciais */
clk_tb = 1'b0;
reset_tb = 0'b0;
count_tb = 1'b1;
adder_tb = 9'b1;
$monitor("%d : %d %d -> %b %b %b", minutes0_tb, seconds1_tb, seconds0_tb, m0_7seg, s1_7seg,
s0_7seg);
/* Depois de um tempo, seta o count para 0, o timer deve parar de passar */
#1000 $display("Setting count = 0");
count_tb = 1'b0;
/* Depois de mais um tempo, o count deve voltar a funcionar */
#1000 $display("Setting count = 1");
count_tb = 1'b1;
/* Resetando a contagem */
#300 $display("Setting reset = 1");
reset_tb = 1'b1;
#5 reset_tb = 1'b0;
/* Timer rodando de 8 em 8 segundos */
#1000 $display("Setting adder = 8");
adder_tb = 9'b1000;
#500 $display("Setting adder = 15");
adder_tb = 9'b1111;
#500 $display("Setting adder = 1");
adder_tb = 9'b1;
#500 $display("Setting adder = -1");
adder_tb = -9'b1;
#500 $display("Setting adder = -10");
adder_tb = -9'd10;
#500 $display("Setting adder = -30");
adder_tb = -9'd30;
/* O timer continua por mais um tempo até parar */
#500 $stop;
end
/* Geração de um clock */
always #10 clk_tb = ~clk_tb;
endmodule
| 6.631631 |
module Timer_v #(
parameter DATA_WIDTH = 4
) (
i_clk,
rst_n,
data_in,
cnt_out,
enable,
cnt_one
);
input i_clk;
input rst_n;
input [DATA_WIDTH-1:0] data_in;
input enable;
output [DATA_WIDTH-1:0] cnt_out;
output cnt_one;
wire [DATA_WIDTH-1:0] count_next;
reg [DATA_WIDTH-1:0] counter_out;
always @(posedge i_clk) begin
if (rst_n == 1'b0) begin
counter_out <= data_in;
end else begin
if (enable == 1'b1) counter_out <= count_next;
end
end
assign count_next = (counter_out == 1'b0) ? data_in : counter_out - 1'b1;
assign cnt_one = (counter_out == 1'b0) ? 1'b1 : 1'b0;
assign cnt_out = counter_out;
endmodule
| 7.103779 |
module timer_ver (
clk,
rst_n,
en_out
);
input clk, rst_n;
output en_out;
reg en_out;
reg [31:0] counter;
reg [31:0] trig_time;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_out <= 1'b0;
counter <= 32'd0;
trig_time <= 32'd100000; //2ms
end else begin
counter <= counter + 32'd1;
if (counter == trig_time) begin
counter <= 32'd0;
en_out <= 1'b1;
end else begin
en_out <= 1'b0;
end
end
end //awlays
endmodule
| 6.676996 |
module timer_ver_db (
clk,
rst_n,
en_out
);
input clk, rst_n;
output en_out;
reg en_out;
reg [31:0] counter;
reg [31:0] trig_time;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_out <= 1'b0;
counter <= 32'd0;
trig_time <= 32'd1000000; //20ms
end else begin
counter <= counter + 32'd1;
if (counter == trig_time) begin
counter <= 32'd0;
en_out <= 1'b1;
end else begin
en_out <= 1'b0;
end
end
end //awlays
endmodule
| 6.794421 |
module//////////
module Timer_v_tb ();
parameter WIDTH = 4 ;
reg i_clk ;
reg rst_n ;
reg enable ;
reg [WIDTH-1:0] data_in ;
wire [WIDTH-1:0] cnt_out ;
wire cnt_one ;
///instantiation ///
Timer_v DUT (i_clk , rst_n , data_in , cnt_out , enable , cnt_one) ;
initial
begin
i_clk = 1'b0 ;
rst_n = 1'b0 ;
end
always
begin
#5 i_clk = ~i_clk ;
end
initial
begin
#2 rst_n = 1'b0 ;
#26 rst_n = 1'b1 ;
end
initial
begin
#3 enable = 1'b1 ;
#1 data_in = 4'b1000 ;
#180 data_in = 4'b0100;
#26 data_in = 4'b1001;
#1000 $stop ;
end
endmodule
| 7.045634 |
module timer_wb (
// RCC
input wire i_clk,
input wire i_reset,
// Trigger out signal
output wire o_timer_trigger,
// Wishbone
input wire [31:0] i_wb_adr,
input wire [31:0] i_wb_dat,
input wire [ 3:0] i_wb_sel,
input wire i_wb_we,
input wire i_wb_cyc,
input wire i_wb_stb,
output reg [31:0] o_wb_dat,
output reg o_wb_ack
);
// Default prescaler value. Reloaded on reset.
parameter DEFAULT_PRESCALER = 32'hFFFF_FFFF;
// Prescaler value. Reloaded onto the downcounter on update.
reg [31:0] prescaler = DEFAULT_PRESCALER;
// Downcounter. Trigger output is latched high when this hits zero.
reg [31:0] downcounter = DEFAULT_PRESCALER;
// Register the output trigger signal
reg timer_trigger = 0;
assign o_timer_trigger = timer_trigger;
// Bit indices for the flags register
localparam wb_r_FLAGS__TRIGGER = 0;
// Flags register is just a collection of bits, in this case just the trigger
wire [31:0] flags;
assign flags[wb_r_FLAGS__TRIGGER] = timer_trigger;
assign flags[31:1] = 0;
// Wishbone register addresses
// Each register is actually 32 bits wide
localparam wb_r_PRESCALER = 1'b0, wb_r_FLAGS = 1'b1, wb_r_MAX = 1'b1;
// Since the incoming wishbone address from the CPU increments by 4 bytes, we
// need to right shift it by 2 to get our actual register index
localparam reg_sel_bits = $clog2(wb_r_MAX + 1);
wire [reg_sel_bits-1:0] register_index = i_wb_adr[reg_sel_bits+1:2];
always @(posedge i_clk) begin
if (i_reset) begin
o_wb_ack <= 0;
prescaler <= DEFAULT_PRESCALER;
downcounter <= DEFAULT_PRESCALER;
timer_trigger <= 1'b0;
end else begin
// Handle the downcounter
if (downcounter > 0) begin
downcounter <= downcounter - 1;
end else begin
downcounter <= prescaler;
timer_trigger <= 1'b1;
end
// Wishbone interface logic
o_wb_ack <= 1'b0;
if (i_wb_cyc && i_wb_stb && !o_wb_ack) begin
o_wb_ack <= 1'b1;
// Register read
case (register_index)
wb_r_PRESCALER: o_wb_dat <= prescaler;
wb_r_FLAGS: o_wb_dat <= flags;
endcase
// Register write
if (i_wb_we) begin
case (register_index)
wb_r_PRESCALER: begin
// Load the new prescaler, also reset the downcounter
prescaler <= i_wb_dat;
downcounter <= i_wb_dat;
end
wb_r_FLAGS: begin
// If the trigger bit is written, clear the trig state
if (i_wb_dat[wb_r_FLAGS__TRIGGER]) timer_trigger <= 1'b0;
end
endcase
end
end
end
end
endmodule
| 8.7028 |
module timer_wrapper ( /*AUTOARG*/
// Outputs
timer_apb_prdata,
timer_apb_pready,
timer_apb_pslverr,
timer_hires_irq,
timer_systick_irq,
// Inputs
apb_timer_psel,
apb_timer_paddr,
apb_timer_penable,
apb_timer_pwrite,
apb_timer_pwdata,
clk,
rst_n
);
input apb_timer_psel; // Peripheral select
input [11:0] apb_timer_paddr; // Address
input apb_timer_penable; // Transfer control
input apb_timer_pwrite; // Write control
input [31:0] apb_timer_pwdata; // Write data
output [31:0] timer_apb_prdata; // Read data
output timer_apb_pready; // Device ready
output timer_apb_pslverr; // Device error response
output timer_hires_irq; // From U_TIMER of timer_periph.v
output timer_systick_irq; // From U_TIMER of timer_periph.v
input clk; // To U_TIMER of timer_periph.v
input rst_n; // To U_TIMER of timer_periph.v
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
wire read_enable;
wire write_enable;
wire strobe;
assign read_enable = apb_timer_psel & (~apb_timer_pwrite); // assert for whole APB read transfer
assign write_enable = apb_timer_psel & (~apb_timer_penable) & apb_timer_pwrite; // assert for 1st cycle of write transfer
assign strobe = read_enable | write_enable; // yes, this could be simplify
/* timer_periph AUTO_TEMPLATE(
.intr_o (timer_irq),
.data_o (timer_apb_prdata),
// Inputs
.clk_i (clk),
.rst_i (!rst_n),
.addr_i (apb_timer_paddr[7:0] ),
.data_i (apb_timer_pwdata),
.we_i (write_enable),
.stb_i (strobe),
.intr_systick_o (timer_systick_irq),
.intr_hires_o (timer_hires_irq),
); */
timer_periph U_TIMER (
/*AUTOINST*/
// Outputs
.intr_systick_o(timer_systick_irq), // Templated
.intr_hires_o (timer_hires_irq), // Templated
.data_o (timer_apb_prdata), // Templated
// Inputs
.clk_i (clk), // Templated
.rst_i (!rst_n), // Templated
.addr_i (apb_timer_paddr[7:0]), // Templated
.data_i (apb_timer_pwdata), // Templated
.we_i (write_enable), // Templated
.stb_i (strobe)
); // Templated
// Output read data to APB
assign timer_apb_pready = 1'b1; // always ready
assign timer_apb_pslverr = 1'b0; // always okay
endmodule
| 7.23652 |
module xyz (
input clk,
output reg p
);
always @(clk) begin
p <= clk;
end
endmodule
| 7.433964 |
module tb ();
reg clk;
wire p;
xyz x (
clk,
p
);
initial clk = 1'b0;
always @(*) #5 clk = ~clk;
initial begin
$dumpfile("tb.vcd");
$dumpvars(0, tb);
// clk = 1'b0;
#1000 $finish;
end
endmodule
| 7.002324 |
module example (
input logic a,
b,
c,
output y
);
logic ab, bb, cb, n1, n2, n3;
assign #1{ab, bb, cb} = -{a, b, c};
assign #2 n1 = ab & bb & cb;
assign #2 n2 = a & bb & cb;
assign #2 n3 = a & bb & c;
assign #4 y = n1 | n2 | n3;
endmodule
| 6.978445 |
module top;
logic a, b, c, y;
example U0 (
a,
b,
c,
y
);
initial begin
$dumpfile("outputs/simple.vcd");
$dumpvars(0, top);
$display("\t\ttime\ta\tb\tc\t\y");
$monitor("%d\t%b\t%b\t%b\t%b", $time, a, b, c, y);
#1 a = 1;
b = 0;
c = 0;
#1 a = 1;
b = 0;
c = 0;
#1 a = 1;
b = 0;
c = 0;
#1 a = 1;
b = 0;
c = 0;
end
endmodule
| 7.3094 |
module timescale_syntax (
a,
b,
c
);
input a;
input b;
output c;
assign c = a ^ b;
endmodule
| 6.834049 |
module TimeSelector (
input [2:0] c_type,
input [2:0] ing_type,
output reg [1:0] t_value
);
always @(*) begin
if (c_type == 3'b001)
case (ing_type)
3'b001: t_value = 2;
3'b010: t_value = 3;
3'b011: t_value = 0;
3'b100: t_value = 0;
3'b101: t_value = 1;
default: t_value = 0;
endcase
else if (c_type == 3'b010)
case (ing_type)
3'b001: t_value = 2;
3'b010: t_value = 2;
3'b011: t_value = 1;
3'b100: t_value = 0;
3'b101: t_value = 1;
default: t_value = 0;
endcase
else if (c_type == 3'b011)
case (ing_type)
3'b001: t_value = 2;
3'b010: t_value = 1;
3'b011: t_value = 2;
3'b100: t_value = 0;
3'b101: t_value = 1;
default: t_value = 0;
endcase
else if (c_type == 3'b100)
case (ing_type)
3'b001: t_value = 1;
3'b010: t_value = 1;
3'b011: t_value = 1;
3'b100: t_value = 2;
3'b101: t_value = 1;
default: t_value = 0;
endcase
else t_value = 0;
end
endmodule
| 6.525033 |
module ubbDemodulator #(
parameter S_AXIS_CONFIG_TDATA_WIDTH = 32,
parameter S_AXIS_RCVR_TDATA_WIDTH = 16,
parameter S_AXIS_RCVR_TUSER_WIDTH = 2,
parameter S_AXIS_NCO_TDATA_WIDTH = 32,
parameter S_AXIS_NCO_TUSER_WIDTH = 2,
parameter M_AXIS_TIME_TDATA_WIDTH = 64,
parameter M_AXIS_TIME_TUSER_WIDTH = 2
) (
input aclk, // Core clock
input aresetn, // Synchronous Reset, Active-Low
input [S_AXIS_CONFIG_TDATA_WIDTH-1:0] s_axis_config_tdata, // Configuration Input Channel...
input s_axis_config_tvalid,
output s_axis_config_tready,
input s_axis_config_tlast,
input [S_AXIS_RCVR_TDATA_WIDTH-1:0] s_axis_rcvr_tdata, // Receiver Input Channel...
input [S_AXIS_RCVR_TUSER_WIDTH-1:0] s_axis_rcvr_tuser,
input s_axis_rcvr_tvalid,
output s_axis_rcvr_tready,
input s_axis_rcvr_tlast,
input [S_AXIS_NCO_TDATA_WIDTH-1:0] s_axis_nco_tdata, // NCO Input Channel...
input [S_AXIS_NCO_TUSER_WIDTH-1:0] s_axis_nco_tuser,
input s_axis_nco_tvalid,
output s_axis_nco_tready,
input s_axis_nco_tlast,
output [M_AXIS_DEMOD_TDATA_WIDTH-1:0] m_axis_time_tdata, // Time Output channel...
output [M_AXIS_DEMOD_TUSER_WIDTH-1:0] m_axis_time_tuser,
output m_axis_time_tvalid,
input m_axis_time_tready,
output m_axis_time_tlast
);
endmodule
| 7.335111 |
module TimeShow (
input [5:0] hour__,
input [5:0] minute__,
input [5:0] second__,
input [5:0] hour_,
input [5:0] minute_,
input [5:0] second_,
input set_en,
input alarm_en,
output [41:0] all_hex
);
reg [5:0] second;
reg [5:0] minute;
reg [5:0] hour;
initial begin
second = 8'b0;
minute = 8'b0;
hour = 8'b0;
end
always @(*) begin
if (set_en == 1'b1 || alarm_en == 1'b1) begin
second = second_;
minute = minute_;
hour = hour_;
end else begin
second = second__;
minute = minute__;
hour = hour__;
end
end
HEXShow second_show (
.data(second),
.hex_one(all_hex[6:0]),
.hex_ten(all_hex[13:7])
);
HEXShow minute_show (
.data(minute),
.hex_one(all_hex[20:14]),
.hex_ten(all_hex[27:21])
);
HEXShow hour_show (
.data(hour),
.hex_one(all_hex[34:28]),
.hex_ten(all_hex[41:35])
);
endmodule
| 7.003601 |
module timeslot (
clk_6M,
rstz,
p_1us,
p_05us,
regi_time_base_offset,
corre_sync_p,
pssyncCLK_p,
//
BTCLK,
tslot_p,
half_tslot_p,
offcounter_1us,
regi_slot_offset
);
input clk_6M, rstz, p_1us, p_05us;
input [27:0] regi_time_base_offset;
input corre_sync_p, pssyncCLK_p;
//
output [27:0] BTCLK;
output tslot_p, half_tslot_p;
output [9:0] offcounter_1us;
output [9:0] regi_slot_offset;
reg [9:0] regi_slot_offset;
wire [9:0] nxtcounter_1us_off, offcounter_1us;
wire tslot_p;
reg [9:0] counter_1us;
always @(posedge clk_6M or negedge rstz) begin
if (!rstz) counter_1us <= 0;
else if ((counter_1us == 10'd624) & p_1us) counter_1us <= 0;
// else if (corre_sync_p)
// counter_1us <= 10'd68; // 4(preamble length) + 64 (syncword-length)
else if (p_1us) counter_1us <= counter_1us + 1'b1;
end
//
wire [9:0] off;
always @(posedge clk_6M or negedge rstz) begin
if (!rstz) regi_slot_offset <= 0;
else if (corre_sync_p) regi_slot_offset <= off;
end
assign off = counter_1us <= 10'd68 ? 10'd68 - counter_1us : 10'd68 + 10'd624 - counter_1us;
assign nxtcounter_1us_off = counter_1us + regi_slot_offset;
assign offcounter_1us = nxtcounter_1us_off <= 10'd624 ? nxtcounter_1us_off : nxtcounter_1us_off - 10'd625;
assign tslot_p = (offcounter_1us == 10'd624) & p_1us;
assign half_tslot_p = (offcounter_1us == 10'd312) & p_1us; //p_05us;
reg [27:0] BTCLK;
always @(posedge clk_6M or negedge rstz) begin
if (!rstz) BTCLK <= 0;
else if (pssyncCLK_p) BTCLK <= {BTCLK[27:2], 2'b11}; //1'b0, 1'b0};
else if (corre_sync_p) BTCLK <= {BTCLK[27:2], 1'b0, 1'b0};
else if (half_tslot_p || tslot_p) BTCLK <= BTCLK + 1'b1;
end
endmodule
| 6.520066 |
module TimesN_comb1 (
output [7:0] Times_x,
input [7:0] X
);
wire [7:0] Times_x1, Times_x2;
assign Times_x1 = X;
assign Times_x2 = Times_x1 + X;
assign Times_x = Times_x2 + X;
endmodule
| 6.666919 |
module TimesN_pipe (
output reg [7:0] Times_x,
input clk,
input [7:0] X
);
reg [7:0] Times_x1, Times_x2;
reg [7:0] X1, X2;
always @(posedge clk) begin
// Pipeline stage 1
X1 <= X;
Times_x1 <= X;
// Pipeline stage 2
X2 <= X1;
Times_x2 <= Times_x1 + X1;
// Pipeline stage 3
Times_x <= Times_x2 + X2;
end
endmodule
| 6.534716 |
module Timestamp_Counter (
input i_sys_clk,
input i_enable,
input i_incr,
input i_event,
output o_rollover,
output reg [7:0] o_time
);
assign o_rollover = (&o_time) & i_incr;
always @(posedge i_sys_clk) begin
if (!i_enable) begin
o_time <= 1;
end else if (i_event) begin
o_time <= 1;
end else if (i_incr) begin
o_time <= o_time + 1;
end
end // End always
endmodule
| 7.552579 |
module Timestamp_Counter_tb;
reg clk, incr, _event, enable;
wire w_rollover;
wire [7:0] w_time;
Timestamp_Counter tsc (
.i_sys_clk(clk),
.i_enable(enable),
.i_event(_event),
.i_incr(incr),
.o_rollover(w_rollover),
.o_time(w_time)
);
always #2 clk = ~clk;
initial begin
clk = 0;
enable = 0;
incr = 0;
_event = 0;
#11 enable = 1;
end
always @(posedge clk) begin
incr <= ~incr;
end
initial #2100 $finish;
endmodule
| 7.552579 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module timestamp_fifo(
// input rst,
input sclk,
input srst, // @ posedge smclk - sync reset
input pre_stb, // marks pre-first input byte (s0,s1,s2,s3,u0,u1,u2,u3)
input [7:0] din, // data in - valid for 8 cycles after pre_stb
input aclk, // clock to synchronize "advance" commands
input arst, // @ posedge aclk - sync reset
input advance, // @aclk advance registers
input rclk, // output clock
input rrst, // @ posedge rclk - sync reset
input rstb, // @rclk, read start (data available next 8 cycles)
output reg [ 7:0] dout
);
reg [7:0] fifo_ram[0:15]; // 16x8 fifo
reg [3:0] wpntr; // input fifo pointer
reg rcv; // receive data
reg [3:0] rpntr; // fifo read pointer
reg [1:0] advance_r;
reg snd; // send data
reg snd_d;
always @ (posedge sclk) begin
if (srst) rcv <= 0;
else if (pre_stb) rcv <= 1;
else if (&wpntr[2:0]) rcv <= 0;
if (srst) wpntr <= 0;
else if (!rcv) wpntr <= {wpntr[3],3'b0};
else wpntr <= wpntr + 1;
end
always @ (posedge sclk) begin
if (rcv) fifo_ram[wpntr] <= din;
end
always @(posedge aclk) begin
if (arst) advance_r <= 0;
else advance_r <= {advance_r[0], advance};
end
always @(posedge aclk) begin
if (advance_r[0] && !advance_r[1]) rpntr[3] <= ~wpntr[3]; // previous value (now wpntr[3] is already inverted
end
always @(posedge rclk) begin
if (rrst) snd <= 0;
else if (rstb) snd <= 1;
else if (&rpntr[2:1]) snd <= 0; // at count 6
snd_d <= snd;
if (rrst) rpntr[2:0] <= 0;
else if (!snd && !rstb) rpntr[2:0] <= 0;
else rpntr[2:0] <= rpntr[2:0] + 1;
end
always @(posedge rclk) begin
if (rstb || snd || snd_d) dout <= fifo_ram[rpntr];
end
endmodule
| 8.081644 |
module timestamp_forward (
clk_in,
timestamp_in,
clk_out,
timestamp_out
);
parameter TIMESTAMP_WIDTH = 64;
input clk_in;
input [TIMESTAMP_WIDTH-1:0] timestamp_in;
input clk_out;
output [TIMESTAMP_WIDTH-1:0] timestamp_out;
// clk_in domain
reg req_in = 0;
reg ack_in = 0;
reg [TIMESTAMP_WIDTH-1:0] timestamp_in_latched;
// clk_out domain
reg req_out = 0;
reg req_d_out = 0;
reg [TIMESTAMP_WIDTH-1:0] timestamp_out;
always @(posedge clk_in) begin
if (req_in == ack_in) begin
req_in <= !req_in;
timestamp_in_latched <= timestamp_in;
end
ack_in <= req_d_out;
end
always @(posedge clk_out) begin
req_out <= req_in;
req_d_out <= req_out;
if (req_d_out != req_out) timestamp_out <= timestamp_in_latched;
end
endmodule
| 7.231397 |
module timestamp_gen #(
parameter TIMESTAMP_WIDTH = 5,
parameter TIMESTAMP_UNIT_WIDTH = 32,
parameter TIMESTAMP_UNIT = 1 << TIMESTAMP_UNIT_WIDTH
) (
input clk,
input reset,
output reg [TIMESTAMP_WIDTH-1:0] timestamp
);
reg [TIMESTAMP_UNIT_WIDTH-1:0] counter;
always @(posedge clk) begin
if (reset) begin
timestamp <= 0;
counter <= 0;
end else begin
if (counter == TIMESTAMP_UNIT - 1) begin
timestamp <= timestamp + 1;
counter <= 0;
end else begin
counter <= counter + 1;
end
end
end
endmodule
| 7.279181 |
module timestamp_insertion #(
parameter TIMESTAMP_WIDTH = 64,
parameter C_M_AXIS_DATA_WIDTH = 256,
parameter C_M_AXIS_TUSER_WIDTH = 128
) (
output reg [ C_M_AXIS_DATA_WIDTH-1:0] m_axis_tdata,
output reg [ C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
output reg [C_M_AXIS_DATA_WIDTH/8-1:0] m_axis_tstrb,
output reg m_axis_tvalid,
output reg m_axis_tlast,
input m_axis_tready,
input [TIMESTAMP_WIDTH-1:0] stamp_counter,
input pkt_start,
input [ C_M_AXIS_DATA_WIDTH-1:0] s_axis_tdata,
input [ C_M_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
input [C_M_AXIS_DATA_WIDTH/8-1:0] s_axis_tstrb,
input s_axis_tvalid,
input s_axis_tlast,
output s_axis_tready,
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2 = 0;
while (2 ** log2 < number) begin
log2 = log2 + 1;
end
end
endfunction // log2
localparam TIMESTAMP = 32;
localparam WAIT = 1;
localparam SEND_PACKET = 2;
localparam MAX_PKT_RX_QUEUE = 66;
localparam IN_TIME_DEPTH_BIT = log2(MAX_PKT_RX_QUEUE);
wire timestamp_fifo_nearly_full;
wire timestamp_fifo_empty;
reg timestamp_fifo_rd_en;
reg in_fifo_rd_en;
wire in_fifo_empty;
wire in_fifo_nearly_full;
wire [ TIMESTAMP_WIDTH-1:0] fifo_timestamp;
wire [ C_M_AXIS_TUSER_WIDTH-1:0] tuser_fifo;
wire [((C_M_AXIS_DATA_WIDTH / 8))-1:0] tstrb_fifo;
wire tlast_fifo;
wire [ C_M_AXIS_DATA_WIDTH-1:0] tdata_fifo;
reg [1:0] state, state_next;
assign s_axis_tready = !in_fifo_nearly_full;
fallthrough_small_fifo #(
.WIDTH(C_M_AXIS_DATA_WIDTH + C_M_AXIS_TUSER_WIDTH + C_M_AXIS_DATA_WIDTH / 8 + 1),
.MAX_DEPTH_BITS(2)
) input_fifo (
.din ({s_axis_tlast, s_axis_tuser, s_axis_tstrb, s_axis_tdata}), // Data in
.wr_en (s_axis_tvalid & ~in_fifo_nearly_full), // Write enable
.rd_en (in_fifo_rd_en), // Read the next word
.dout ({tlast_fifo, tuser_fifo, tstrb_fifo, tdata_fifo}),
.full (),
.prog_full (),
.nearly_full(in_fifo_nearly_full),
.empty (in_fifo_empty),
.reset (reset),
.clk (clk)
);
fallthrough_small_fifo #(
.WIDTH(TIMESTAMP_WIDTH),
.MAX_DEPTH_BITS(IN_TIME_DEPTH_BIT)
) timestamp_fifo (
// Outputs
.dout(fifo_timestamp),
.full(),
.nearly_full(timestamp_fifo_nearly_full),
.prog_full(),
.empty(timestamp_fifo_empty),
// Inputs
.din(stamp_counter),
.wr_en(pkt_start),
.rd_en(timestamp_fifo_rd_en),
.reset(reset),
.clk(clk)
);
always @(*) begin
m_axis_tuser = tuser_fifo;
m_axis_tstrb = tstrb_fifo;
m_axis_tlast = tlast_fifo;
m_axis_tdata = tdata_fifo;
m_axis_tvalid = 0;
in_fifo_rd_en = 0;
timestamp_fifo_rd_en = 0;
state_next = state;
case (state)
WAIT: begin
if (!timestamp_fifo_empty && !in_fifo_empty) begin
m_axis_tvalid = 1;
m_axis_tuser[TIMESTAMP+TIMESTAMP_WIDTH-1:TIMESTAMP] = fifo_timestamp;
if (m_axis_tready) begin
in_fifo_rd_en = 1;
timestamp_fifo_rd_en = 1;
state_next = SEND_PACKET;
end
end
end
SEND_PACKET: begin
if (!in_fifo_empty) begin
m_axis_tvalid = 1;
if (m_axis_tready) begin
in_fifo_rd_en = 1;
if (tlast_fifo) state_next = WAIT;
end
end
end
endcase
end
always @(posedge clk) begin
if (reset) begin
state <= WAIT;
end else begin
state <= state_next;
end
end
endmodule
| 7.796676 |
module timestamp_pad_proc #(
parameter TS_POSITION_WIDTH = 8,
parameter C_M_AXIS_TDATA_WIDTH = 256,
parameter C_S_AXIS_TDATA_WIDTH = 256
) (
input axi_aclk,
input axi_resetn,
input [ 63:0] ref_counter,
input ts_valid,
input [ TS_POSITION_WIDTH-1:0] slave_ts_position,
input [ TS_POSITION_WIDTH-1:0] master_ts_position,
//Slave Stream Ports (interface to data path)
input [C_S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input s_axis_tvalid,
input s_axis_tready,
input s_axis_tlast,
//To rx fifo
output [C_S_AXIS_TDATA_WIDTH-1:0] s_axis_tdata_ts_pad,
//Master Stream Ports (interface to TX queues)
input [C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
input m_axis_tvalid,
input m_axis_tready,
input m_axis_tlast,
//From tx fifo
output [C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata_ts_pad
);
//Add packet data in passive way at axis slave
reg [7:0] slave_pkt_word_cnt, master_pkt_word_cnt;
always @(posedge axi_aclk)
if (~axi_resetn) slave_pkt_word_cnt <= 0;
else if (s_axis_tlast & s_axis_tvalid & s_axis_tready) slave_pkt_word_cnt <= 0;
else if (s_axis_tvalid & s_axis_tready) slave_pkt_word_cnt <= slave_pkt_word_cnt + 1;
assign s_axis_tdata_ts_pad = (ts_valid && (slave_ts_position[7:0] == slave_pkt_word_cnt)) ? ref_counter : s_axis_tdata;
//Add packet data in passive way at axis master
always @(posedge axi_aclk)
if (~axi_resetn) master_pkt_word_cnt <= 0;
else if (m_axis_tlast & m_axis_tvalid & m_axis_tready) master_pkt_word_cnt <= 0;
else if (m_axis_tvalid & m_axis_tready) master_pkt_word_cnt <= master_pkt_word_cnt + 1;
assign m_axis_tdata_ts_pad = (ts_valid && (master_ts_position[7:0] == master_pkt_word_cnt)) ? ref_counter : m_axis_tdata;
endmodule
| 8.520097 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module timestamp_snapshot(
// input rst,
input tclk, // clock that drives time counters
input [31:0] sec, // @tclk: current time seconds
input [19:0] usec, // @tclk: current time microseconds
// snapshot destination clock domain
input sclk,
input srst, // @ posedge sclk - sync reset
input snap,
output reg pre_stb, // one clock pulse before sending TS data
output reg [7:0] ts_data // timestamp data (s0,s1,s2,s3,u0,u1,u2,u3==0)
);
wire snap_tclk;
reg [51:0] sec_usec_snap;
wire pulse_busy;
reg pulse_busy_r;
reg [2:0] cntr;
reg snd;
wire pre_stb_w;
assign pre_stb_w = !pulse_busy && pulse_busy_r;
always @ (posedge tclk) begin
if (snap_tclk) sec_usec_snap <= {usec,sec};
end
always @(posedge sclk) begin
if (srst) snd <= 0;
else if (!pulse_busy && pulse_busy_r) snd <= 1;
else if ((&cntr) || snap) snd <= 0;
pre_stb <= pre_stb_w;
end
always @(posedge sclk) begin
pulse_busy_r <= pulse_busy;
if (!snd) cntr <= 0;
else cntr <= cntr + 1;
if (snd) case (cntr)
3'h0: ts_data <= sec_usec_snap[ 7: 0];
3'h1: ts_data <= sec_usec_snap[15: 8];
3'h2: ts_data <= sec_usec_snap[23:16];
3'h3: ts_data <= sec_usec_snap[31:24];
3'h4: ts_data <= sec_usec_snap[39:32];
3'h5: ts_data <= sec_usec_snap[47:40];
3'h6: ts_data <= {4'b0,sec_usec_snap[51:48]};
3'h7: ts_data <= 8'b0;
endcase
end
pulse_cross_clock #(
.EXTRA_DLY (1)
) snap_tclk_i (
.rst (srst), // input
.src_clk (sclk), // input
.dst_clk (tclk), // input
.in_pulse (snap), // input
.out_pulse (snap_tclk), // output
.busy (pulse_busy) // output
);
endmodule
| 8.081644 |
module TimeStamp_stimulus;
reg clk, reset;
initial begin
clk = 1'b1;
reset = 1'b1;
#20 reset = 1'b0;
end
always #2 clk = ~clk;
wire [3:0] oldest;
reg en;
reg [3:0] access;
TimeStamp time_stamp (
.clk(clk),
.reset(reset),
.en(en),
.access(access),
.oldest_stamp(oldest)
);
integer i, j, seed;
integer count[0:15];
integer max_value;
integer max_index;
initial begin
en = 1'b0;
access = 4'h0;
seed = 0;
for (j = 0; j < 16; j = j + 1) begin
count[j] = 0;
end
#21
for (i = 0; i < 10000; i = i + 1) begin
#4
// Simulate expected output
max_value = count[0];
max_index = 0;
for (j = 1; j < 16; j = j + 1) begin
if (count[j] > max_value) begin
max_value = count[j];
max_index = j;
end
end
if (max_index != oldest) begin
$display("Error: mismatch");
$stop;
end
// Set random input
access = ($random(seed) - 1) % 16;
en = $random(seed) % 2;
// Update simulated states
if (en == 1) begin
for (j = 0; j < 16; j = j + 1) count[j] = count[j] + 1;
count[access] = 0;
#8 begin
end
end
end
$display("PASS");
end
endmodule
| 6.883594 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module timestamp_to_parallel(
input clk, // clock that drives time counters
input pre_stb, // just before receiving sequence of 7 bytes
input [7:0] tdata, // byte-parallel timestamp data
output reg [31:0] sec, // time seconds
output reg [19:0] usec, // time microseconds
output done // got serial timetamp message, output is valid (1-cycle pulse)
);
reg [6:0] seq;
assign done = seq[6];
always @ (posedge clk) begin
seq <= {seq[5:0],pre_stb};
if (seq[0]) sec[ 7: 0] <= tdata;
if (seq[1]) sec[15: 8] <= tdata;
if (seq[2]) sec[23:16] <= tdata;
if (seq[3]) sec[31:24] <= tdata;
if (seq[4]) usec[ 7: 0] <= tdata;
if (seq[5]) usec[15: 8] <= tdata;
if (seq[6]) usec[19:16] <= tdata[3:0];
end
endmodule
| 8.081644 |
modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module timestamp_to_serial(
input clk, // clock that drives time counters
input stb, // serialize and send timestamp message
input [31:0] sec, // time seconds
input [19:0] usec, // time microseconds
output reg [7:0] tdata // byte-parallel timestamp data sent right after stb input
);
reg [2:0] cntr;
reg busy = 0;
wire [2:0] cntr_w;
assign cntr_w= stb? 3'b0 : cntr;
always @ (posedge clk) begin
if (stb) busy <= 1;
else if (&cntr_w[2:1]) busy <= 0;
if (stb) cntr <= 1;
else if (busy) cntr <= cntr + 1;
case (cntr_w)
3'h0:tdata <= sec[ 7: 0];
3'h1:tdata <= sec[15: 8];
3'h2:tdata <= sec[23:16];
3'h3:tdata <= sec[31:24];
3'h4:tdata <= usec[ 7: 0];
3'h5:tdata <= usec[15: 8];
3'h6:tdata <= {4'h0,usec[19:16]};
3'h7:tdata <= 8'h0;
endcase
end
endmodule
| 8.081644 |
module Times_to_Seg (
input clk,
input reset,
input [3:0] Second_First,
input [3:0] Second_Second,
input [3:0] Minute_First,
input [3:0] Minute_Second,
input [3:0] Hour_First,
input [3:0] Hour_Second,
output reg [7:0] seg_out,
output reg [7:0] seg_en
);
reg [2:0] count;
wire [7:0] S_F_out;
wire [7:0] S_S_out;
wire [7:0] M_F_out;
wire [7:0] M_S_out;
wire [7:0] H_F_out;
wire [7:0] H_S_out;
enCoder_Four_to_Eight S_F (
//.clk(clk),
.decimalNumber(Second_First),
.segNumber(S_F_out)
);
enCoder_Four_to_Eight S_S (
//.clk(clk),
.decimalNumber(Second_Second),
.segNumber(S_S_out)
);
enCoder_Four_to_Eight M_F (
//.clk(clk),
.decimalNumber(Minute_First),
.segNumber(M_F_out)
);
enCoder_Four_to_Eight M_S (
//.clk(clk),
.decimalNumber(Minute_Second),
.segNumber(M_S_out)
);
enCoder_Four_to_Eight H_F (
//.clk(clk),
.decimalNumber(Hour_First),
.segNumber(H_F_out)
);
enCoder_Four_to_Eight H_S (
//.clk(clk),
.decimalNumber(Hour_Second),
.segNumber(H_S_out)
);
always @(posedge clk, posedge reset) begin
if (reset) begin
count <= 0;
end else begin
if (count == 5) begin
count <= 0;
end else begin
count <= count + 1;
end
end
end
always @(count) begin
case (count)
3'b000: begin
seg_out <= S_S_out;
seg_en <= 8'b11111110;
end
3'b001: begin
seg_out <= S_F_out;
seg_en <= 8'b11111101;
end
3'b010: begin
seg_out <= M_S_out;
seg_en <= 8'b11110111;
end
3'b011: begin
seg_out <= M_F_out;
seg_en <= 8'b11101111;
end
3'b100: begin
seg_out <= H_S_out;
seg_en <= 8'b10111111;
end
3'b101: begin
seg_out <= H_F_out;
seg_en <= 8'b01111111;
end
default begin
seg_out <= 8'b11111111;
seg_en <= 8'b11111111;
end
endcase
end
endmodule
| 6.715929 |
module timetag_bench ();
reg clk;
reg fx2_clk;
reg cmd_wr;
reg [7:0] cmd_in;
wire [15:0] length;
reg request_length;
wire [7:0] data;
wire data_rdy;
reg data_ack;
reg [3:0] detectors;
wire [3:0] laser_en;
wire running;
// Bidirs
// Instantiate the UUT
timetag uut (
.fx2_clk(fx2_clk),
.cmd_wr (cmd_wr),
.cmd_in (cmd_in),
.clk(clk),
.strobe_in(detectors),
// TODO: Implement delta channel test
.data_rdy(data_rdy),
.data(data),
.data_ack(data_ack)
);
// This just prints the results in the ModelSim text window
// You can leave this out if you want
initial
$monitor(
$time,
" cmd(%b %x) data(%b %x) cmd_rdy=%b cmd_ack=%b cmd_data=%x state=",
cmd_wr,
cmd_in,
data_rdy,
data,
uut.reg_addr,
uut.reg_data
);
// Clocks
initial clk = 0;
always #2 clk = ~clk;
initial fx2_clk = 0;
always #6 fx2_clk = ~fx2_clk;
// Simulate photons
initial detectors = 4'b0000;
//`define RANDOM_PHOTONS
`ifdef RANDOM_PHOTONS
initial begin
if ((4'b1111 & $random) == 4'b0) begin
detectors[0] = 1'b1;
#10 detectors[0] = 1'b0;
end
end
`else
always begin
#100 detectors[0] = 1'b1;
#5 detectors[0] = 1'b0;
end
`endif
// These statements conduct the actual circuit test
initial begin
$display($time, " Starting...");
$display($time, " Starting detectors");
#100;
#12 cmd_in = 8'hAA;
cmd_wr = 1;
#12 cmd_in = 8'h01;
#12 cmd_in = 8'h01;
#12 cmd_in = 8'h01;
#12 cmd_wr = 0;
data_ack = 1;
end
endmodule
| 6.650135 |
module TimeTrans (
output flicker,
output reg [7:0] oSeg,
output [3:0] oAn,
input [4:0] lightTime,
input Cm,
Cc,
input clk
);
wire [7:0] oSeg1, oSeg2, oSeg3, oSeg4;
wire [7:0] sec;
reg [3:0] CmBuf = 4'd15;
reg [3:0] CcBuf = 4'd15;
DigitTrans dt (
flicker,
sec,
lightTime
);
SEG7 seg1 (
oSeg1,
sec[3:0]
);
SEG7 seg2 (
oSeg2,
sec[7:4]
);
SEG7 seg3 (
oSeg3,
CcBuf
);
SEG7 seg4 (
oSeg4,
CmBuf
);
Enabler enb (
oAn,
clk
);
always @(clk) begin
if (Cm) CmBuf <= 4'd10;
else CmBuf <= 4'd15;
if (Cc) CcBuf <= 4'd10;
else CcBuf <= 4'd15;
end
always @(oAn) begin
case (oAn)
4'b0111: oSeg <= oSeg1;
4'b1011: oSeg <= oSeg2;
4'b1101: oSeg <= oSeg3;
4'b1110: oSeg <= oSeg4;
default: oSeg <= 7'b1111111;
endcase
end
endmodule
| 6.531705 |
module TimeUnitEnable (
input clk,
input reset,
output pulse
);
function integer Size(input integer in);
for (Size = 0; in > 0; Size = Size + 1) in = in >> 1;
endfunction
parameter FREQ_CLK = 50000000;
parameter FREQ_WANTED = 20000;
localparam NB_TIC = FREQ_CLK / FREQ_WANTED; // Division entiere
localparam SIZE_CPT = Size(NB_TIC);
reg [SIZE_CPT-1:0] cpt;
always @(posedge clk) begin
if (reset) cpt <= 0;
else if (cpt == NB_TIC - 1) cpt <= 0;
else cpt <= cpt + 1;
end
assign pulse = cpt == NB_TIC - 1;
endmodule
| 6.700418 |
module TimeZoneHours (
TZHours,
clk,
KeyPlus,
KeyMinus,
reset,
EditPos,
EditMode,
screen,
TZPlusMinus
);
output reg [6:0] TZHours;
input [2:0] EditPos;
input EditMode, clk, KeyPlus, KeyMinus, reset, TZPlusMinus;
input [1:0] screen;
reg [2:0] mode;
always @(posedge clk, negedge reset) begin
if (~reset) begin
TZHours <= 7;
mode <= 0;
end else if (~KeyPlus && EditMode == 1 && screen == 2 && EditPos == 2) begin
if (TZPlusMinus == 1) mode <= 1;
else mode <= 3;
end else if (~KeyMinus && EditMode == 1 && screen == 2 && EditPos == 2) begin
if (TZPlusMinus == 1) mode <= 2;
else mode <= 4;
end else begin
mode <= 0;
TZHours <= mode == 1? (TZHours == 12? 7'd0: TZHours + 7'd1):
mode == 2? (TZHours == 0? 7'd12: TZHours - 7'd1):
mode == 3? (TZHours == 12? 7'd1: TZHours + 7'd1):
mode == 4? (TZHours == 1? 7'd12: TZHours - 7'd1):
(TZHours > 12 && EditMode == 0)? 7'd12: TZHours;
end
end
endmodule
| 6.749354 |
module TimeZoneMinutes (
TZMinutes,
clk,
KeyPlus,
KeyMinus,
reset,
EditPos,
EditMode,
screen
);
output reg [6:0] TZMinutes;
input [2:0] EditPos;
input EditMode, clk, KeyPlus, KeyMinus, reset;
input [1:0] screen;
reg [2:0] mode;
always @(posedge clk, negedge reset) begin
if (~reset) begin
TZMinutes <= 0;
mode <= 0;
end else if (~KeyPlus && EditMode == 1 && screen == 2 && (EditPos == 4 || EditPos == 5)) begin
if (EditPos == 5) mode <= 1;
else if (EditPos == 4) mode <= 3;
else mode <= 0;
end else if (~KeyMinus && EditMode == 1 && screen == 2 && (EditPos == 4 || EditPos == 5)) begin
if (EditPos == 5) mode <= 2;
else if (EditPos == 4) mode <= 4;
else mode <= 0;
end else begin
mode <= 0;
TZMinutes <= mode == 1? (TZMinutes % 10 == 9? TZMinutes - 7'd9: TZMinutes + 7'd1):
mode == 2? (TZMinutes % 10 == 0? TZMinutes + 7'd9: TZMinutes - 7'd1):
mode == 3? (TZMinutes >= 50? TZMinutes - 7'd50: TZMinutes + 7'd10):
mode == 4? (TZMinutes < 10? TZMinutes + 7'd50: TZMinutes - 7'd10):
TZMinutes;
end
end
endmodule
| 8.196704 |
module TimeZonePlusMinus (
TZPlusMinus,
clk,
KeyPlus,
KeyMinus,
reset,
EditPos,
EditMode,
screen,
TZHours
);
output reg TZPlusMinus;
input [2:0] EditPos;
input EditMode, clk, KeyPlus, KeyMinus, reset;
input [6:0] TZHours;
input [1:0] screen;
reg mode;
always @(posedge clk, negedge reset) begin
if (~reset) begin
TZPlusMinus <= 1;
mode <= 0;
end else if (~KeyPlus && EditMode == 1 && screen == 2 && EditPos == 0) begin
mode <= 1;
end else if (~KeyMinus && EditMode == 1 && screen == 2 && EditPos == 0) begin
mode <= 1;
end else begin
mode <= 0;
TZPlusMinus <= (mode == 1 && TZHours != 0) ? TZPlusMinus + 1'b1 : TZPlusMinus;
end
end
endmodule
| 7.827526 |
module implements the product between an input Galois
Finite {2^8} element and a fixed element {03} of the same field.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
------------------------------------------------------------------------------*/
module time_03
#(
// PARAMETERS.
parameter NB_BYTE = 8
)
(
// OUTPUTS.
output wire [NB_BYTE - 1 : 0] o_byte ,
// INPUTS.
input wire [NB_BYTE - 1 : 0] i_byte
) ;
// LOCAL PARAMETERS.
localparam BAD_CONF = ( NB_BYTE != 8 ) ;
localparam [NB_BYTE - 1 : 0] M_X = 8'h1b ;
// INTERNAL SIGNALS.
// None so far.
// ALGORITHM BEGIN.
assign o_byte
= ( ( i_byte[NB_BYTE-1]==1'b0 )? {i_byte[NB_BYTE-1-1:0],1'b0} : ({i_byte[NB_BYTE-1-1:0],1'b0} ^ M_X) ) ^ i_byte ;
endmodule
| 7.842559 |
module implements the product between an input Galois
Finite {2^8} element and a fixed element {02} of the same field.
-------------------------------------------------------------------------------
-- Copyright (C) 2016 ClariPhy Argentina S.A. All rights reserved
------------------------------------------------------------------------------*/
module time_03_new
#(
// PARAMETERS.
parameter NB_BYTE = 8
)
(
// OUTPUTS.
output wire [NB_BYTE - 1 : 0] o_byte ,
// INPUTS.
input wire [NB_BYTE - 1 : 0] i_byte
) ;
// LOCAL PARAMETERS.
localparam BAD_CONF = ( NB_BYTE != 8 ) ;
// INTERNAL SIGNALS.
// None so far.
// ALGORITHM BEGIN.
assign o_byte[7] = i_byte[5];
assign o_byte[6] = i_byte[4];
assign o_byte[5] = i_byte[3] ^ i_byte[7];
assign o_byte[4] = i_byte[2] ^ i_byte[6] ^ i_byte[7];
assign o_byte[3] = i_byte[1] ^ i_byte[6];
assign o_byte[2] = i_byte[0] ^ i_byte[7];
assign o_byte[1] = i_byte[6] ^ i_byte[7];
assign o_byte[0] = i_byte[6];
endmodule
| 7.842559 |
module timer_ns (
input wire clk,
output reg clk_1ms,
input [1:0] spe
);
reg [31:0] cnt;
reg [31:0] rep;
initial begin
cnt[31:0] <= 0;
clk_1ms <= 0;
end
always @(posedge clk) begin
case (spe) //ٶȿص״̬ȷʱӵƵ
2'b00: begin
rep <= 25000000; //1HZ
end
2'b01: begin
rep <= 12500000; //2HZ
end
2'b10: begin
rep <= 6250000; //4HZ
end
2'b11: begin
rep <= 3125000; //8HZ
end
endcase
if (cnt >= rep) begin
cnt <= 0;
clk_1ms <= ~clk_1ms;
end else begin
cnt <= cnt + 1;
end
end
endmodule
| 6.698628 |
module time_alignment (
input clk,
input rst_n,
//ǰ
input pre_src_frame_vsync,
input pre_src_frame_href,
input pre_src_frame_clken,
input [23 : 0] pre_img,
input pre_tx_frame_vsync,
input pre_tx_frame_href,
input pre_tx_frame_clken,
input [7 : 0] pre_tx_img,
input [ 7 : 0] pre_A,
//
output post_src_frame_vsync,
output post_src_frame_href,
output post_src_frame_clken,
output [23 : 0] post_img,
output post_tx_frame_vsync,
output post_tx_frame_href,
output post_tx_frame_clken,
output [7 : 0] post_tx_img,
output [7 : 0] post_A
);
integer i;
parameter src_delay = 6;
reg pre_src_frame_vsync_d[src_delay - 1 : 0];
reg pre_src_frame_href_d [src_delay - 1 : 0];
reg pre_src_frame_clken_d[src_delay - 1 : 0];
reg [23 : 0] pre_img_d [src_delay - 1 : 0];
//src_delay
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
for (i = 0; i < src_delay; i = i + 1) begin
pre_src_frame_vsync_d[i] <= 0;
pre_src_frame_href_d[i] <= 0;
pre_src_frame_clken_d[i] <= 0;
pre_img_d[i] <= 0;
end
end else begin
pre_src_frame_vsync_d[0] <= pre_src_frame_vsync;
pre_src_frame_href_d[0] <= pre_src_frame_href;
pre_src_frame_clken_d[0] <= pre_src_frame_clken;
pre_img_d[0] <= pre_img;
for (i = 1; i < src_delay; i = i + 1) begin
pre_src_frame_vsync_d[i] <= pre_src_frame_vsync_d[i-1];
pre_src_frame_href_d[i] <= pre_src_frame_href_d[i-1];
pre_src_frame_clken_d[i] <= pre_src_frame_clken_d[i-1];
pre_img_d[i] <= pre_img_d[i-1];
end
end
end
assign post_src_frame_vsync = pre_src_frame_vsync_d[src_delay-1];
assign post_src_frame_href = pre_src_frame_href_d[src_delay-1];
assign post_src_frame_clken = pre_src_frame_clken_d[src_delay-1];
assign post_img = pre_img_d[src_delay-1];
assign post_tx_frame_vsync = pre_tx_frame_vsync;
assign post_tx_frame_href = pre_tx_frame_href;
assign post_tx_frame_clken = pre_tx_frame_clken;
assign post_tx_img = pre_tx_img;
assign post_A = pre_A;
endmodule
| 6.913041 |
module TIME_CAL (
RESETN,
CLK,
IN_TIME,
IN_DATE,
IN_ALARM_TIME,
MODE,
MODE_STATE,
SETTING,
ALARM_SETTING,
SETTING_OK,
OUT_TIME,
OUT_DATE,
OUT_ALARM_TIME
);
input RESETN, CLK;
input [16:0] IN_ALARM_TIME;
input [16:0] IN_TIME;
input [15:0] IN_DATE;
input MODE, MODE_STATE, SETTING, ALARM_SETTING;
output reg [16:0] OUT_ALARM_TIME;
output reg [16:0] OUT_TIME;
output reg [15:0] OUT_DATE;
output reg SETTING_OK;
reg [16:0] SETTING_TIME;
reg [15:0] SETTING_DATE;
// TEMP TIME
reg [ 4:0] HOUR;
reg [5:0] MIN, SEC;
// TEMP DATE
reg [6:0] YEAR;
reg [3:0] MONTH;
reg [4:0] DAY;
integer CNT;
always @(posedge CLK) begin
if (!RESETN) begin
CNT = 0;
SETTING_OK = 0;
end else if ((SETTING == 1'b1) || (ALARM_SETTING == 1'b1)) begin
CNT = 0;
SETTING_OK = 1;
end else begin
if (CNT >= 99999) CNT = 0;
else CNT = CNT + 1;
SETTING_OK = 0;
end
end
always @(posedge CLK) begin
if (!RESETN) begin
SETTING_TIME = 16'b0000000000000001; // 16'b0000/000000/000001;
SETTING_DATE = 16'b0010000000100001; // 16'b0010000/0001/00001;
end else begin
if ((SETTING == 0) && (ALARM_SETTING == 0)) begin
SETTING_TIME = IN_TIME;
SETTING_DATE = IN_DATE;
end
end
end
// Count part
always @(posedge CLK) begin
if(!MODE)
// MODE 0 -> continue stream(time is going)
begin
if(!MODE_STATE)
// MODE_STATE 0 -> current time
begin
OUT_TIME = {HOUR, MIN, SEC};
OUT_DATE = {YEAR, MONTH, DAY};
end else begin
// MODE_STATE 1 -> alarm time & alarm control time
OUT_TIME = {HOUR, MIN, SEC};
OUT_DATE = {YEAR, MONTH, DAY};
OUT_ALARM_TIME = {IN_ALARM_TIME[16:12], IN_ALARM_TIME[11:6], IN_ALARM_TIME[5:0]};
end
end else
// MODE 1 -> stop stream(time is not going)
begin
if(!MODE_STATE)
// MODE_STATE 0 -> current control time
begin
OUT_TIME = {SETTING_TIME[16:12], SETTING_TIME[11:6], SETTING_TIME[5:0]};
OUT_DATE = {SETTING_DATE[15:9], SETTING_DATE[8:5], SETTING_DATE[4:0]};
end
end
end
// Second part
always @(posedge CLK) begin
if (!RESETN) SEC = 0;
else if (SETTING == 1) SEC = SETTING_TIME[5:0];
else if (CNT == 99999) begin
if (SEC >= 59) SEC = 0;
else SEC = SEC + 1;
end
end
// Minute part
always @(posedge CLK) begin
if (!RESETN) MIN = 0;
else if (SETTING == 1) MIN = SETTING_TIME[11:6];
else if ((CNT == 99999) && (SEC == 59)) begin
if (MIN >= 59) MIN = 0;
else MIN = MIN + 1;
end
end
// Hour part
always @(posedge CLK) begin
if (!RESETN) HOUR = 0;
else if (SETTING == 1) HOUR = SETTING_TIME[16:12];
else if ((CNT == 99999) && (SEC == 59) && (MIN == 59)) begin
if (HOUR >= 23) HOUR = 0;
else begin
HOUR = HOUR + 1;
end
end
end
// Day part
always @(posedge CLK) begin
if (!RESETN) DAY = 1;
else if (SETTING == 1'b1) DAY = SETTING_DATE[4:0];
else if ((CNT == 99999) && (HOUR == 23) && (SEC == 59) && (MIN == 59)) begin
if (DAY >= 31) DAY = 1;
else DAY = DAY + 1;
end
end
// Month part
always @(posedge CLK) begin
if (!RESETN) MONTH = 1;
else if (SETTING == 1'b1) MONTH = SETTING_DATE[8:5];
else if ((CNT == 99999) && (DAY == 31) && (HOUR == 23) && (SEC == 59) && (MIN == 59)) begin
if (MONTH >= 31) MONTH = 1;
else MONTH = MONTH + 1;
end
end
// Year part
always @(posedge CLK) begin
if (!RESETN) YEAR = 16;
else if (SETTING == 1'b1) YEAR = SETTING_DATE[15:9];
else
if((CNT == 99999) && (MONTH == 12) && (DAY == 31) && (HOUR == 23) && (SEC == 59) && (MIN == 59))
begin
if (YEAR >= 99) YEAR = 0;
else YEAR = YEAR + 1;
end
end
endmodule
| 6.923508 |
module time_change (
clk_1hz,
count,
mode,
led1,
hour_change,
minute_change,
alarm_en,
count_alarm
);
input clk_1hz, mode, hour_change, minute_change, alarm_en;
output led1;
output [20:0] count;
output [20:0] count_alarm;
reg led1;
reg [20:0] count;
reg [20:0] count_alarm;
reg [20:0] count_12;
initial begin
count = 0;
led1 = 0;
count_alarm = 0;
end
always @(posedge clk_1hz) begin
count_12 <= count%43200;//12进制时用，这个好像没用了，但是不影响跑就没改
case (alarm_en)
1'b0: //不调闹钟
begin
case ({
hour_change, minute_change
})
2'b00: //无校时
if (count < 20'd86400) count <= count + 1;
else count <= 0;
2'b01: //分钟校时
if (count < 20'd86400) count <= count + 6'd60;
else count <= count - 20'd86340;
2'b10: //小时校时
if (count < 20'd82800) count <= count + 12'd3600;
else count <= count - 20'd82800;
2'b11: //锁存
count <= count;
endcase
end
1'b1: //调闹钟
begin
case ({
hour_change, minute_change
})
2'b00: //无校时
if (count_alarm < 20'd86400) count_alarm <= count_alarm + 1;
else count_alarm <= 0;
2'b01: //分钟校时
if (count_alarm < 20'd86400) count_alarm <= count_alarm + 6'd60;
else count_alarm <= count_alarm - 20'd86340;
2'b10: //小时校时
if (count_alarm < 20'd82800) count_alarm <= count_alarm + 12'd3600;
else count_alarm <= count_alarm - 20'd82800;
2'b11: //锁存
count_alarm <= count_alarm;
endcase
end
endcase
end
//如果是12进制并且count>12小时，说明是下午，led1亮
always @(posedge clk_1hz) begin
if (mode == 1 && count >= 20'd43200) led1 <= 1;
else led1 <= 0;
end
endmodule
| 6.894827 |
module time_cnt (
input wire aclk,
input wire ap_start,
output wire time_out
);
localparam [32-1:0] LP_TIME_VALUE = 32'h7735_9400; // around 8s for 250MHz
reg [32-1:0] time_cnt = 32'd0;
assign time_out = (time_cnt == 32'd1);
always @(posedge aclk) begin
if (ap_start) begin
time_cnt <= LP_TIME_VALUE;
end else if (time_cnt != 32'd0) begin
time_cnt <= time_cnt - 1;
end
end
endmodule
| 6.837235 |
module time_comparator #(
parameter BITS = 32
) (
input [BITS-1:0] clock,
input [BITS-1:0] timestamp,
output reg match,
output reg valid
);
reg [BITS-1:0] half_range;
reg [BITS-1:0] delta;
always @* begin
//FIXME: this should be based on BITS
half_range = 32'h7fffffff;
delta = timestamp - clock; //this may wrap around here, which is ok.
if (delta > half_range) begin //out of range
valid <= 0;
match <= 0;
end else if (delta == 0) begin
valid <= 1;
match <= 1;
end else begin
valid <= 1;
match <= 0;
end
end
endmodule
| 6.694844 |
module time_comparator_tb;
reg [31:0] clock;
reg [31:0] timestamp;
wire match;
wire valid;
`define JITTER 4
time_comparator time_check (
.clock(clock),
.timestamp(timestamp),
.match(match),
.valid(valid)
);
integer i;
initial begin
$display("timestamp,clock,match,valid");
$monitor("%h %h %b %b", timestamp, clock, match, valid);
$display("Normal sequence");
timestamp = 32'h0000003;
clock = 32'h0000000;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 $display("Wrap around sequence");
clock = 32'hfffffffe;
timestamp = 32'h00000001;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 $display("Into range");
clock = 32'h00000000;
timestamp = 32'h80000002;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 clock = clock + 31'h1;
#1 $finish;
end
endmodule
| 6.694844 |
module time_compare (
input [63:0] time_now,
input [63:0] trigger_time,
output now,
output early,
output late,
output too_early
);
wire sec_match = (time_now[63:32] == trigger_time[63:32]);
wire sec_late = (time_now[63:32] > trigger_time[63:32]);
wire tick_match = (time_now[31:0] == trigger_time[31:0]);
wire tick_late = (time_now[31:0] > trigger_time[31:0]);
/*
assign now = sec_match & tick_match;
assign late = sec_late | (sec_match & tick_late);
assign early = ~now & ~late;
*/
/*
assign now = (time_now == trigger_time);
assign late = (time_now > trigger_time);
assign early = (time_now < trigger_time);
*/
// Compare fewer bits instead of 64 to speed up logic
// Unused bits are not significant
// Top bit of seconds would put us in year 2038, long after
// the warranty has run out :)
// Top 5 bits of ticks are always zero for clocks less than 134MHz
// "late" can drop bottom few bits of ticks, and just delay signaling
// of late.
// "now" cannot drop those bits, it needs to be exact.
wire [57:0] short_now = {time_now[62:32],time_now[26:0]};
wire [57:0] short_trig = {trigger_time[62:32],trigger_time[26:0]};
assign now = (short_now == short_trig);
assign late = (short_now[57:5] > short_trig[57:5]);
assign early = (short_now < short_trig);
assign too_early = (trigger_time[63:32] > (time_now[63:32] + 4)); // Don't wait too long
endmodule
| 7.402805 |
module TIME_CONT (
RESETN,
CLK,
IN_TIME,
IN_DATE,
FLAG,
UP,
DOWN,
OUT_TIME,
OUT_DATE
);
input RESETN, CLK;
input [16:0] IN_TIME, IN_DATE;
input [2:0] FLAG;
input [2:0] UP, DOWN;
output wire [16:0] OUT_TIME, OUT_DATE;
/* FLAG BUFF */
parameter FLAG_CONTROL_STATE = 3'b010;
/* CONTROL SELECTER LIST */
parameter CONT_NO = 3'b000,
CONT_HOUR = 3'b001,
CONT_MIN = 3'b010,
CONT_SEC = 3'b011,
CONT_MERIDIAN = 3'b100,
CONT_YEAR = 3'b101,
CONT_MONTH = 3'b110,
CONT_DAY = 3'b111;
/* MERIDIAN LIST */
parameter AM = 0, PM = 1;
reg MERIDIAN;
reg [3:0] HOUR;
reg [5:0] MIN, SEC;
reg [6:0] YEAR;
reg [4:0] MONTH, DAY;
always @(posedge CLK or negedge RESETN) begin
if (~RESETN) begin
HOUR = IN_TIME[15:12];
MIN = IN_TIME[11:6];
SEC = IN_TIME[5:0];
MERIDIAN = AM;
YEAR = IN_DATE[16:10];
MONTH = IN_DATE[9:5];
DAY = IN_DATE[4:0];
end else begin
if (FLAG == FLAG_CONTROL_STATE)
// Up part
case (UP)
CONT_HOUR: begin
if (HOUR >= 23) HOUR = 0;
else HOUR = HOUR + 1;
end
CONT_MIN: begin
if (MIN >= 59) MIN = 0;
else MIN = MIN + 1;
end
CONT_SEC: begin
if (SEC >= 59) SEC = 0;
else SEC = SEC + 1;
end
CONT_MERIDIAN: begin
if (MERIDIAN == AM) MERIDIAN = PM;
else MERIDIAN = AM;
end
CONT_YEAR: begin
if (YEAR >= 99) YEAR = 0;
else YEAR = YEAR + 1;
end
CONT_MONTH: begin
if (MONTH >= 12) MONTH = 1;
else MONTH = MONTH + 1;
end
CONT_DAY: begin
if (DAY >= 31) DAY = 1;
else DAY = DAY + 1;
end
default: begin
HOUR = IN_TIME[15:12];
MIN = IN_TIME[11:6];
SEC = IN_TIME[5:0];
MERIDIAN = AM;
YEAR = IN_DATE[16:10];
MONTH = IN_DATE[9:5];
DAY = IN_DATE[4:0];
end
endcase
// DOWN part
case (DOWN)
CONT_HOUR: begin
if (HOUR <= 0) HOUR = 23;
else HOUR = HOUR - 1;
end
CONT_MIN: begin
if (MIN <= 0) MIN = 59;
else MIN = MIN - 1;
end
CONT_SEC: begin
if (SEC <= 0) SEC = 59;
else SEC = SEC - 1;
end
CONT_MERIDIAN: begin
if (MERIDIAN == AM) MERIDIAN = PM;
else MERIDIAN = AM;
end
CONT_YEAR: begin
if (YEAR <= 0) YEAR = 99;
else YEAR = YEAR - 1;
end
CONT_MONTH: begin
if (MONTH <= 1) MONTH = 12;
else MONTH = MONTH - 1;
end
CONT_DAY: begin
if (DAY <= 1) DAY = 31;
else DAY = DAY - 1;
end
default: begin
HOUR = IN_TIME[15:12];
MIN = IN_TIME[11:6];
SEC = IN_TIME[5:0];
MERIDIAN = AM;
YEAR = IN_DATE[16:10];
MONTH = IN_DATE[9:5];
DAY = IN_DATE[4:0];
end
endcase
end
end
assign OUT_TIME = {MERIDIAN, HOUR, MIN, SEC};
assign OUT_DATE = {YEAR, MONTH, DAY};
endmodule
| 6.7723 |
module divider1 (
input clk,
output reg clk_1
);
parameter NUM_DIV = 100000000;
reg [31:0] cnt;
always @(posedge clk) begin
if (cnt < NUM_DIV / 2 - 1) begin
cnt <= cnt + 1'b1;
clk_1 <= clk_1;
end else begin
cnt <= 32'b0;
clk_1 <= ~clk_1;
end
end
endmodule
| 7.259919 |
module TimeDeal (
input clk, //1s
input rst_n,
output [3:0] min_l,
output [3:0] min_h,
output [3:0] sec_l,
output [3:0] sec_h
);
reg [3:0] dout1;
reg [3:0] dout2;
reg [3:0] dout3;
reg [3:0] dout4;
//秒的高、低位，分钟的高、低位
reg carry1, carry2, carry3;
//进位
//先处理秒的低位
always @(posedge clk or negedge rst_n) begin
if (!rst_n) dout1 <= 0;
else begin
if (dout1 < 9) begin
dout1 <= dout1 + 1'b1;
carry1 <= 0;
end else begin
dout1 <= 0;
carry1 <= 1'b1;
end
end
end
//再处理秒的高位
always @(posedge carry1 or negedge rst_n) begin
if (!rst_n) dout2 <= 0;
else begin
if (dout2 < 5) begin
dout2 <= dout2 + 1'b1;
carry2 <= 0;
end else begin
dout2 <= 0;
carry2 <= 1'b1;
end
end
end
//再处理分钟的低位
always @(posedge carry2 or negedge rst_n) begin
if (!rst_n) dout3 <= 0;
else begin
if (dout3 < 9) begin
dout3 <= dout3 + 1'b1;
carry3 <= 0;
end else begin
dout3 <= 0;
carry3 <= 1'b1;
end
end
end
//再处理分钟的低位
always @(posedge carry3 or negedge rst_n) begin
if (!rst_n) dout4 <= 0;
else begin
if (dout4 < 6) begin
dout4 <= dout4 + 1'b1;
end else begin
dout4 <= 0;
end
end
end
assign sec_l = dout1;
assign sec_h = dout2;
assign min_l = dout3;
assign min_h = dout4;
endmodule
| 7.760355 |
module time_design (
input clk,
input rst,
input [15:0] data,
output reg [7:0] seg_data,
output reg [3:0] seg_cs
);
reg clk_500HZ;
integer clk_cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
clk_500HZ <= 0;
clk_cnt <= 0;
end else begin
if (clk_cnt >= 100_000) begin
clk_cnt <= 0;
clk_500HZ <= ~clk_500HZ;
end else begin
clk_cnt <= clk_cnt + 1;
end
end
end
always @(posedge clk_500HZ or posedge rst)
if (rst) seg_cs <= 4'b0001;
else seg_cs <= {seg_cs[2:0], seg_cs[3]};
reg [3:0] dis_data;
always @(seg_cs)
case (seg_cs)
4'b0001: dis_data = data[3:0];
4'b0010: dis_data = data[7:4];
4'b0100: dis_data = data[11:8];
4'b1000: dis_data = data[15:12];
default: dis_data = 4'hf;
endcase
always @(dis_data)
case (dis_data)
04'h0: seg_data = 8'h3F;
04'h1: seg_data = 8'h06;
04'h2: seg_data = 8'h5B;
04'h3: seg_data = 8'h4F;
04'h4: seg_data = 8'h66;
04'h5: seg_data = 8'h6D;
04'h6: seg_data = 8'h7D;
04'h7: seg_data = 8'h07;
04'h8: seg_data = 8'h7F;
04'h9: seg_data = 8'h6F;
04'ha: seg_data = 8'h77;
04'hb: seg_data = 8'h7C;
04'hc: seg_data = 8'h39;
04'hd: seg_data = 8'h5E;
04'he: seg_data = 8'h79;
04'hf: seg_data = 8'h40;
default: seg_data = 8'hFF;
endcase
endmodule
| 8.093298 |
module time_display (
// input
CLK,
RSTN,
SEG_A_VAL,
SEG_B_VAL,
SEG_C_VAL,
SEG_D_VAL,
// output
SEG_A,
SEG_B,
SEG_C,
SEG_D
);
// ------ input --------------------------------------------
input CLK, RSTN;
input [3:0] SEG_A_VAL, SEG_B_VAL, SEG_C_VAL, SEG_D_VAL;
// ------ output -------------------------------------------
output [7:0] SEG_A, SEG_B, SEG_C, SEG_D;
// ------ wire ----------------------------------------------
wire [7:0] SEG_A, SEG_B, SEG_C, SEG_D;
display_module dm1 (
.CLK(CLK),
.RSTN(RSTN),
.SEG_VAL(SEG_A_VAL),
.SEG(SEG_A)
);
display_module dm2 (
.CLK(CLK),
.RSTN(RSTN),
.SEG_VAL(SEG_B_VAL),
.SEG(SEG_B)
);
display_module dm3 (
.CLK(CLK),
.RSTN(RSTN),
.SEG_VAL(SEG_C_VAL),
.SEG(SEG_C)
);
display_module dm4 (
.CLK(CLK),
.RSTN(RSTN),
.SEG_VAL(SEG_D_VAL),
.SEG(SEG_D)
);
endmodule
| 6.981525 |
module time_divider #( //分频器
parameter N = 2,
WIDTH = 8
) (
input clk,
input rst,
output reg clk_out
); //N是分频比，WIDTH计数器位宽
reg [WIDTH-1:0] cnt;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt <= 0;
clk_out <= 0;
end
else if(cnt==(N>>1)-1) //偶分频，计数器计到N/2-1取反
begin
clk_out <= ~clk_out;
cnt <= 0;
end else cnt <= cnt + 1;
end
endmodule
| 6.589183 |
module time_exceed (
input wire clk,
input wire rst,
input wire [7:0] ms,
input wire [7:0] sec,
input wire [7:0] min,
output reg legal
);
always @(posedge clk or posedge rst) begin
if (rst) legal <= 'b1;
else begin
if (min == 8'b0000_0001 || min == 8'b0000_0000) legal <= 'b1;
else legal <= 'b0;
end
end
endmodule
| 8.210795 |
module time_fifo #(
parameter NAME = "SETME"
) (
input clk,
input rst,
input [1:0] state,
input print
);
real idle, calc, done, sum;
always @(posedge clk) begin
if (rst) begin
idle = 0;
calc = 0;
done = 0;
end else begin
case (state)
0: idle = idle + 1;
1: calc = calc + 1;
2: done = done + 1;
endcase
if (print) begin
sum = idle + calc + done;
$display("%s fifo breakdown: idle: %f, calc: %f, done: %f", NAME, idle / sum, calc / sum,
done / sum);
end
end
end
endmodule
| 6.872364 |
module time_fsm (
input wire enable,
input wire reset,
input wire CLK, //10kHz
input wire [15:0] secondsToCount,
output reg finished
);
reg [15:0] count;
reg [15:0] seconds;
reg [ 7:0] countSeconds;
parameter MAX = 10000;
/*Contador de tiempo: habilita y deshabilita el paso al siguiente estado una vez que termina o inicia la cuenta*/
always @(posedge CLK) begin
if(reset == 1 && enable == 1) //Reset devuelve parametros a condicion inicial
begin
$display("RESET");
seconds <= 0;
count <= 0;
finished <= 1;
end else if (enable == 1) begin
finished <= 0; //flag de habilitacion/deshabilitacion de cambio al proximo estado
count <= count + 1;
if (count == MAX) begin
seconds <= seconds + 1; //contador de segundos
count <= 0;
$display("Segundo %d", seconds); //display para control de simulacion
end
else if (seconds == secondsToCount) //una vez que cumplio el tiempo, habilita paso a siguiente estado
begin
count <= 0; //parametros a condicion inicial
seconds <= 0;
finished <= 1;
$display("Finalizo estado %d", finished); //display para control de simulacion
end
end
end
endmodule
| 7.742458 |
module time_manager (
//input
CLK,
RSTN,
//output
SEC_SIG
);
//--- input --------------------------------------------------------------
input CLK;
input RSTN;
//--- output -------------------------------------------------------------
output SEC_SIG;
//--- reg ----------------------------------------------------------------
reg [27:0] SEC_COUNT;
reg SEC_SIG;
always @(posedge CLK or negedge RSTN) begin
if (!RSTN) begin
SEC_COUNT <= 28'd0;
end else if (SEC_COUNT >= 28'd20000000 - 28'd1) begin
SEC_COUNT <= 28'd0;
end else begin
SEC_COUNT <= SEC_COUNT + 28'd1;
end
end
always @(posedge CLK or negedge RSTN) begin
if (!RSTN) begin
SEC_SIG <= 1'b0;
end else if (SEC_COUNT >= 28'd20000000 - 28'd1) begin
SEC_SIG <= 1'b1;
end else begin
SEC_SIG <= 1'b0;
end
end
endmodule
| 6.602098 |
module time_parameters (
input reset,
input clock,
input [1:0] parameter_selector, //from switch
input [3:0] time_value, //from switch
input reprogram,
input [1:0] interval,
output [3:0] value
);
parameter T_ARM_DELAY = 2'b00;
parameter T_DRIVER_DELAY = 2'b01;
parameter T_PASSENGER_DELAY = 2'b10;
parameter T_ALARM_ON = 2'b11;
reg [3:0] next_arm_delay, next_driver_delay, next_passenger_delay, next_alarm_on;
reg [3:0] arm_delay, driver_delay, passenger_delay, alarm_on;
reg [3:0] next_value;
always @* begin
if (reset) begin
next_arm_delay = 4'b0110; //6
next_driver_delay = 4'b1000; //8
next_passenger_delay = 4'b1111; //15
next_alarm_on = 4'b1010; //10
next_value = arm_delay;
end else if (reprogram) begin
case (parameter_selector)
T_ARM_DELAY: next_arm_delay = time_value;
T_DRIVER_DELAY: next_driver_delay = time_value;
T_PASSENGER_DELAY: next_passenger_delay = time_value;
T_ALARM_ON: next_alarm_on = time_value;
//default: next_arm_delay = arm_delay;//improper parameter selected, do nothing
endcase
end else begin
case (interval)
T_ARM_DELAY: next_value = arm_delay;
T_DRIVER_DELAY: next_value = driver_delay;
T_PASSENGER_DELAY: next_value = passenger_delay;
T_ALARM_ON: next_value = alarm_on;
default: next_value = arm_delay;
endcase
end
end
always @(posedge clock) begin
arm_delay <= next_arm_delay;
driver_delay <= next_driver_delay;
passenger_delay <= next_passenger_delay;
alarm_on <= next_alarm_on;
end
assign value = next_value;
endmodule
| 7.050443 |
module time_posedge #(
parameter NAME = "SETME"
) (
input signal
);
integer old_time;
always @(posedge signal) begin
$display("%s: %d ns", NAME, $stime - old_time);
old_time <= $stime;
end
endmodule
| 6.533868 |
module time_sel_sync (
input wire areset,
input wire clk,
input wire sel,
input wire [63:0] ntp_time_a,
input wire ntp_time_upd_a,
input wire [63:0] ntp_time_b,
input wire ntp_time_upd_b,
output wire [63:0] ntp_time
);
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)reg [2:0] time_a_sync_reg = 3'b0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *)reg [2:0] time_b_sync_reg = 3'b0;
always @(posedge clk) time_a_sync_reg[0] <= ntp_time_upd_a;
always @(negedge clk) time_a_sync_reg[1] <= time_a_sync_reg[0];
always @(posedge clk) time_a_sync_reg[2] <= time_a_sync_reg[1];
reg [63:0] ntp_time_a_sync;
wire load_a_sync;
assign load_a_sync = time_a_sync_reg[1] != time_a_sync_reg[2];
always @(posedge clk) begin
if (load_a_sync) begin
ntp_time_a_sync <= ntp_time_a;
end
end
always @(posedge clk) time_b_sync_reg[0] <= ntp_time_upd_b;
always @(negedge clk) time_b_sync_reg[1] <= time_b_sync_reg[0];
always @(posedge clk) time_b_sync_reg[2] <= time_b_sync_reg[1];
reg [63:0] ntp_time_b_sync;
wire load_b_sync;
assign load_b_sync = time_b_sync_reg[1] != time_b_sync_reg[2];
always @(posedge clk) begin
if (load_b_sync) begin
ntp_time_b_sync <= ntp_time_b;
end
end
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] sel_sync_reg = 2'b0;
always @(posedge clk) begin
sel_sync_reg[0] <= sel;
sel_sync_reg[1] <= sel_sync_reg[0];
end
assign ntp_time = sel_sync_reg[1] == 1'b0 ? ntp_time_a_sync : ntp_time_b_sync;
specify
$setup(ntp_time_a, negedge load_a_sync, 5000);
$setup(ntp_time_b, negedge load_b_sync, 5000);
$hold(negedge load_a_sync, ntp_time_a, 2500);
$hold(negedge load_a_sync, ntp_time_b, 2500);
endspecify
endmodule
| 7.451523 |
module time_signature_clock (
input clk,
input [31:0] beat_cycles,
output [1:0] pulse
);
parameter BEATS_PER_MEASURE = 4;
parameter NOTE_BEAT = 4;
parameter PULSE_LENGTH = 10000000;
reg [31:0] period_count = 0;
reg [ 7:0] beat_count = 0;
reg [ 1:0] tick = 2'b10;
always @(posedge clk)
if ((period_count < beat_cycles && NOTE_BEAT == 4) || (period_count < beat_cycles >> 1 && NOTE_BEAT == 8))
begin
period_count <= period_count + 1;
if ((tick[0] | tick[1]) & period_count == PULSE_LENGTH - 1) begin
tick <= 2'b00;
end
end else begin
period_count <= 0;
beat_count <= beat_count + 1;
if (beat_count == BEATS_PER_MEASURE - 1) beat_count <= 0;
if (beat_count == 0) tick <= 2'b10;
else tick <= 2'b01;
end
assign pulse = tick;
endmodule
| 7.642278 |
module time_simulation ();
reg clk;
initial begin
clk = 1'b0;
repeat (10) begin
#50 clk = ~clk;
end
#50 $finish;
end
Top test (.clkin(clk));
endmodule
| 6.544532 |
module time_slice_gen #(
) ( // generate time slice for tx_control.v
input wire clk,
input wire rstn,
input wire tsf_pulse_1M,
input wire slv_reg_wren_signal,
input wire [1:0] count_total_slice_idx,
input wire [19:0] count_total,
input wire [1:0] count_start_slice_idx,
input wire [19:0] count_start,
input wire [1:0] count_end_slice_idx,
input wire [19:0] count_end,
output wire cycle_start0,
output reg slice_en0,
output reg slice_en1,
output reg slice_en2,
output reg slice_en3
);
reg [19:0] count_total0;
reg [19:0] count_total1;
reg [19:0] count_total2;
reg [19:0] count_total3;
reg [19:0] count_start0;
reg [19:0] count_start1;
reg [19:0] count_start2;
reg [19:0] count_start3;
reg [19:0] count_end0;
reg [19:0] count_end1;
reg [19:0] count_end2;
reg [19:0] count_end3;
reg [19:0] counter0;
reg [19:0] counter1;
reg [19:0] counter2;
reg [19:0] counter3;
assign cycle_start0 = (counter0 == count_total0);
always @(posedge clk) begin
if (rstn == 0) begin
count_total0 <= count_total0;
count_total1 <= count_total1;
count_total2 <= count_total2;
count_total3 <= count_total3;
count_start0 <= count_start0;
count_start1 <= count_start1;
count_start2 <= count_start2;
count_start3 <= count_start3;
count_end0 <= count_end0;
count_end1 <= count_end1;
count_end2 <= count_end2;
count_end3 <= count_end3;
counter0 <= 0;
counter1 <= 0;
counter2 <= 0;
counter3 <= 0;
slice_en0 <= 1;
slice_en1 <= 1;
slice_en2 <= 1;
slice_en3 <= 1;
end else begin
// capture input value to correct slice register
count_total0 <= ( (slv_reg_wren_signal==1 && count_total_slice_idx==0)?count_total:count_total0 );
count_total1 <= ( (slv_reg_wren_signal==1 && count_total_slice_idx==1)?count_total:count_total1 );
count_total2 <= ( (slv_reg_wren_signal==1 && count_total_slice_idx==2)?count_total:count_total2 );
count_total3 <= ( (slv_reg_wren_signal==1 && count_total_slice_idx==3)?count_total:count_total3 );
count_start0 <= ( (slv_reg_wren_signal==1 && count_start_slice_idx==0)?count_start:count_start0 );
count_start1 <= ( (slv_reg_wren_signal==1 && count_start_slice_idx==1)?count_start:count_start1 );
count_start2 <= ( (slv_reg_wren_signal==1 && count_start_slice_idx==2)?count_start:count_start2 );
count_start3 <= ( (slv_reg_wren_signal==1 && count_start_slice_idx==3)?count_start:count_start3 );
count_end0 <= ( (slv_reg_wren_signal==1 && count_end_slice_idx==0)?count_end:count_end0 );
count_end1 <= ( (slv_reg_wren_signal==1 && count_end_slice_idx==1)?count_end:count_end1 );
count_end2 <= ( (slv_reg_wren_signal==1 && count_end_slice_idx==2)?count_end:count_end2 );
count_end3 <= ( (slv_reg_wren_signal==1 && count_end_slice_idx==3)?count_end:count_end3 );
// generate slice enable signal
counter0 <= (tsf_pulse_1M ? (counter0 == count_total0 ? 0 : (counter0 + 1)) : counter0);
counter1 <= (tsf_pulse_1M ? (counter1 == count_total1 ? 0 : (counter1 + 1)) : counter1);
counter2 <= (tsf_pulse_1M ? (counter2 == count_total2 ? 0 : (counter2 + 1)) : counter2);
counter3 <= (tsf_pulse_1M ? (counter3 == count_total3 ? 0 : (counter3 + 1)) : counter3);
slice_en0 <= ((counter0 <= count_end0) && (counter0 >= count_start0));
slice_en1 <= ((counter1 <= count_end1) && (counter1 >= count_start1));
slice_en2 <= ((counter2 <= count_end2) && (counter2 >= count_start2));
slice_en3 <= ((counter3 <= count_end3) && (counter3 >= count_start3));
end
end
endmodule
| 7.715108 |
module TIME_STATE_MACHINE (
input wire reset_n,
clk,
set_time,
// alarm,
//Toggle_switch,
hours_set,
mins_set,
//output reg [4 : 0] hour,
// reg [5 : 0] mins,
output reg hours,
mins,
secs
);
parameter first = 2'b00, second = 2'b01, third = 2'b10, four = 2'b11;
reg [1 : 0] state;
always @(posedge clk, negedge reset_n) begin
if (!reset_n) begin
hours = 0;
mins = 0;
state = 0;
secs = 0;
end else if (set_time) begin
secs = 0;
case (state)
first: begin
case ({
hours_set, mins_set
})
first: begin
state = first;
hours = 0;
mins = 0;
end
second: begin
state = second;
hours = 0;
mins = 0;
end
third: begin
state = third;
hours = 0;
mins = 0;
end
four: begin
state = first;
hours = 0;
mins = 0;
end
endcase
end
second: begin
case ({
hours_set, mins_set
})
first: begin
state = first;
hours = 0;
mins = 1;
end
second: begin
state = second;
hours = 0;
mins = 0;
end
third: begin
state = third;
hours = 0;
mins = 1;
end
four: begin
state = first;
hours = 0;
mins = 0;
end
endcase
end
third: begin
case ({
hours_set, mins_set
})
first: begin
state = first;
hours = 1;
mins = 0;
end
second: begin
state = second;
hours = 1;
mins = 0;
end
third: begin
state = third;
hours = 0;
mins = 0;
end
four: begin
state = first;
hours = 0;
mins = 0;
end
endcase
end
endcase
end else begin
secs = 1;
hours = 0;
mins = 0;
state = 0;
end
end
endmodule
| 6.747396 |
module time_stepper #(
parameter TIME_LENGTH = 24
) (
input i_clk,
input [31:0] prescaler,
input i_run,
output reg [TIME_LENGTH - 1 : 0] o_time
);
reg [31:0] counter = 0;
always @(posedge i_clk) begin
if (i_run) begin
counter <= counter + 1;
if (counter >= prescaler) begin
o_time <= o_time + 1;
counter <= 0;
end
end else begin
o_time <= 0;
counter <= 0;
end
end
endmodule
| 7.849752 |
module time_suit (
clk,
rst_n,
clk_suit
);
input clk;
input rst_n;
output clk_suit;
reg [27:0] count;
reg clk_suit;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count <= 0;
clk_suit <= 0;
end else if (count < 20000) count <= count + 1;
else begin
count <= 0;
clk_suit <= ~clk_suit;
end
end
endmodule
| 6.856237 |
module time_sync (
input wb_clk_i,
input rst_i,
input cyc_i,
input stb_i,
input [2:0] adr_i,
input we_i,
input [31:0] dat_i,
output [31:0] dat_o,
output ack_o,
input sys_clk_i,
output [31:0] master_time_o,
input pps_posedge,
input pps_negedge,
input exp_pps_in,
output exp_pps_out,
output reg int_o,
output reg epoch_o,
output reg pps_o
);
wire [31:0] master_time_rcvd;
reg [31:0] master_time;
reg [31:0] delta_time;
reg internal_tick;
wire sync_rcvd, pps_ext;
reg [31:0] tick_time, tick_time_wb;
wire tick_free_run;
reg tick_int_enable, tick_source, external_sync;
reg [31:0] tick_interval;
reg sync_on_next_pps;
reg sync_every_pps;
reg pps_edge;
// Generate master time
always @(posedge sys_clk_i)
if (rst_i) master_time <= 0;
else if (external_sync & sync_rcvd) master_time <= master_time_rcvd + delta_time;
else if (pps_ext & (sync_on_next_pps | sync_every_pps)) master_time <= 0;
else master_time <= master_time + 1;
assign master_time_o = master_time;
time_sender time_sender (
.clk(sys_clk_i),
.rst(rst_i),
.master_time(master_time),
.send_sync(internal_tick),
.exp_pps_out(exp_pps_out)
);
time_receiver time_receiver (
.clk(sys_clk_i),
.rst(rst_i),
.master_time(master_time_rcvd),
.sync_rcvd(sync_rcvd),
.exp_pps_in(exp_pps_in)
);
assign ack_o = stb_i;
wire wb_write = cyc_i & stb_i & we_i;
wire wb_read = cyc_i & stb_i & ~we_i;
wire wb_acc = cyc_i & stb_i;
always @(posedge wb_clk_i)
if (rst_i) begin
tick_source <= 0;
tick_int_enable <= 0;
external_sync <= 0;
tick_interval <= 100000 - 1; // default to 1K times per second
delta_time <= 0;
pps_edge <= 0;
sync_every_pps <= 0;
end else if (wb_write)
case (adr_i[2:0])
3'd0: begin
tick_source <= dat_i[0];
tick_int_enable <= dat_i[1];
external_sync <= dat_i[2];
pps_edge <= dat_i[3];
sync_every_pps <= dat_i[4];
end
3'd1: tick_interval <= dat_i;
3'd2: delta_time <= dat_i;
3'd3: ;
// Do nothing here, this is to arm the sync_on_next
endcase // case(adr_i[2:0])
always @(posedge sys_clk_i)
if (rst_i) sync_on_next_pps <= 0;
else if (pps_ext) sync_on_next_pps <= 0;
else if (wb_write & (adr_i[2:0] == 3)) sync_on_next_pps <= 1;
always @(posedge sys_clk_i) if (internal_tick) tick_time <= master_time;
always @(posedge wb_clk_i) tick_time_wb <= tick_time;
assign dat_o = tick_time_wb;
always @(posedge sys_clk_i) internal_tick <= (tick_source == 0) ? tick_free_run : pps_ext;
reg [31:0] counter;
always @(posedge sys_clk_i)
if (rst_i) counter <= 0;
else if (tick_free_run) counter <= 0;
else counter <= counter + 1;
assign tick_free_run = (counter >= tick_interval);
// Properly Latch and edge detect External PPS input
reg pps_in_d1, pps_in_d2;
always @(posedge sys_clk_i) begin
pps_in_d1 <= pps_edge ? pps_posedge : pps_negedge;
pps_in_d2 <= pps_in_d1;
end
assign pps_ext = pps_in_d1 & ~pps_in_d2;
always @(posedge sys_clk_i) pps_o <= pps_ext;
// Need to register this?
reg internal_tick_d1;
always @(posedge sys_clk_i) internal_tick_d1 <= internal_tick;
always @(posedge wb_clk_i)
if (rst_i) int_o <= 0;
else if (tick_int_enable & (internal_tick | internal_tick_d1)) int_o <= 1;
else int_o <= 0;
always @(posedge sys_clk_i)
if (rst_i) epoch_o <= 0;
else epoch_o <= (master_time_o[27:0] == 0);
endmodule
| 7.746656 |
module Time_Synch (
input clk,
rst,
syn_run,
input metric_val,
input [21:0] P_Metric_Re,
P_Metric_Im,
input [21:0] R_Metric,
input [3:0] SNR,
output syn_done,
output reg [31:0] FRE_O
);
parameter SYN_VAL = 6'd56;
reg [16:0] Synch_thres_coeff[15:0]; // threshold in format 2.15
initial $readmemh("./MY_SOURCES/RTL_Synch_thres_coeff_q05.txt", Synch_thres_coeff);
wire ena = metric_val & syn_run;
wire [16:0] thres_coeff = Synch_thres_coeff[SNR];
wire [33:0] mult_thres_out; // output of multiplying to threshold in format 9.25
mult thres_mult_ins (
.clk (clk), // input clk
.sclr(rst), // input sclr
.ce (ena), // input ce
.a (R_Metric[21:5]), // input [16 : 0] a in format 7.10
.b (thres_coeff), // input [16 : 0] b
.p (mult_thres_out) // output [33 : 0] p
);
wire [22:0] R_Metric_thr = mult_thres_out[32:10]; // R metric multipies threshold in format 8.15
wire [22:0] P_Metric_mag;
wire appr_mag_val;
Appr_Mag P_Metic_mag_ins (
.clk(clk),
.rst(rst),
.ena(ena),
.real_in(P_Metric_Re),
.imag_in(P_Metric_Im),
.mag(P_Metric_mag), // magnitute of P metric in format 8.15
.val(appr_mag_val)
);
wire [7:0] R_Metric_d64; //reduced bit R_metric delay 64 in format 7.1
Delay2n #(
.WIDTH(8),
.D(64),
.B(6)
) RX_delay64 (
.clk(clk),
.rst(rst),
.ena(ena),
.dat_in(R_Metric[21:14]),
.dat_out(R_Metric_d64)
);
reg cmp_metric;
always @(posedge clk) begin
if (rst) cmp_metric = 1'b0;
else if (appr_mag_val & (P_Metric_mag > R_Metric_thr)) cmp_metric = 1'b1;
else if (~syn_run) cmp_metric = 1'b0;
end
reg [6:0] find_peak_cnt;
wire find_peak_ena = (~find_peak_cnt[6]) & cmp_metric & syn_run;
always @(posedge clk) begin
if (rst) find_peak_cnt = 7'b1;
else if (~syn_run) find_peak_cnt = 7'b1;
else if (find_peak_ena) find_peak_cnt = find_peak_cnt + 1'b1;
end
wire [22:0] add_metric = R_Metric[21:0] + {R_Metric_d64,14'd0};
reg peak_dec;
reg [22:0] peak_add_metric;
always @(posedge clk) begin
if (rst) begin
FRE_O <= 32'd0;
peak_dec <= 1'b0;
peak_add_metric <= 23'd0;
end else if (find_peak_ena) begin
if (peak_add_metric < add_metric) begin
FRE_O = {P_Metric_Im[21:6], P_Metric_Re[21:6]};
peak_add_metric <= add_metric;
peak_dec <= 1'b1;
end else peak_dec <= 1'b0;
end else begin
peak_dec <= 1'b0;
peak_add_metric <= 23'd0;
end
end
reg [5:0] syn_cnt;
wire syn_cnt_run = ~(syn_cnt == 6'd0);
always @(posedge clk) begin
if (rst) syn_cnt <= 6'd0;
if (~syn_run) syn_cnt <= 6'd0;
else if (find_peak_ena & (~syn_cnt_run)) syn_cnt <= 6'b1;
else if (syn_cnt == SYN_VAL) syn_cnt <= 6'b0;
else if (syn_cnt_run & peak_dec) syn_cnt <= 6'b1;
else if (syn_cnt_run) syn_cnt <= syn_cnt + 1'b1;
end
assign syn_done = (syn_cnt == SYN_VAL) & (~find_peak_ena);
endmodule
| 8.369612 |
module time_text (
input wire clk,
reset,
pause,
input wire refresh_tick,
input wire [20:0] pix_x,
pix_y,
output wire time_on,
output wire [2:0] bit_addr,
output wire [10:0] rom_addr
);
//variables
wire [ 3:0] row_addr;
reg [12:0] char_addr;
reg [23:0] time_tick;
reg [30:0] raceTime;
reg [3:0] dig_10th, dig_1s, dig_10s, dig_100s, dig_1000s, dig_10000s;
assign time_on = (pix_y[9:5] == 0) && (pix_x[9:4] < 9);
assign row_addr = pix_y[4:1];
assign bit_addr = pix_x[3:1];
assign rom_addr = {char_addr, row_addr};
//measure time in miliseonds
always @(posedge clk) begin
time_tick <= time_tick + 1;
if (reset) raceTime <= 0;
else if (pause) raceTime <= raceTime;
else if(time_tick==10000000) //0.1 second
begin
time_tick <= 0;
raceTime <= raceTime + 1;
end
//calculate decimal digits
if (refresh_tick) begin
dig_10th <= raceTime % 10;
dig_1s <= (raceTime % 100) / 10;
dig_10s <= (raceTime % 1000) / 100;
dig_100s <= (raceTime % 10000) / 1000;
dig_1000s <= (raceTime % 100000) / 10000;
dig_10000s <= (raceTime % 100000) / 10000;
end
end
always @*
case (pix_x[7:4])
4'h0: char_addr = 7'h53; // S
4'h1: char_addr = 7'h43; // c
//4'h2: char_addr = 7'h4F; // o
//4'h3: char_addr = 7'h52; // r
//4'h4: char_addr = 7'h45; // e
4'h2: char_addr = 7'h3A; // :
4'h3: char_addr = {3'b011, dig_10000s}; // d i g i t 10000
4'h4: char_addr = {3'b011, dig_1000s}; // d i g i t 1000
4'h5: char_addr = {3'b011, dig_100s}; // d i g i t 100
4'h6: char_addr = {3'b011, dig_10s}; // d i g i t 10
4'h7: char_addr = {3'b011, dig_1s}; // d i g i t 1
//4'hA: char_addr = 7'h2e; // .
4'h8: char_addr = {3'b011, dig_10th}; // d i g i t 10th
default: char_addr = 7'h00; //
endcase
endmodule
| 6.997507 |
module time_transfer_tb ();
reg clk = 0, rst = 1;
always #5 clk = ~clk;
initial begin
@(negedge clk);
@(negedge clk);
rst <= 0;
end
initial $dumpfile("time_transfer_tb.vcd");
initial $dumpvars(0, time_transfer_tb);
initial #100000000 $finish;
wire exp_time, pps, pps_rcv;
wire [63:0] vita_time_rcv;
reg [63:0] vita_time = 0;
reg [63:0] counter = 0;
localparam PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9
always @(posedge clk)
if (counter == PPS_PERIOD) counter <= 0;
else counter <= counter + 1;
assign pps = (counter == (PPS_PERIOD - 1));
always @(posedge clk) vita_time <= vita_time + 1;
time_sender time_sender (
.clk(clk),
.rst(rst),
.vita_time(vita_time),
.send_sync(pps),
.exp_time_out(exp_time)
);
time_receiver time_receiver (
.clk(clk),
.rst(rst),
.vita_time(vita_time_rcv),
.sync_rcvd(pps_rcv),
.exp_time_in(exp_time)
);
wire [31:0] delta = vita_time - vita_time_rcv;
endmodule
| 7.489384 |
module time_updater (
input wire clk,
output wire timer
);
reg [11:0] cnt;
assign timer = cnt[11];
always @(posedge clk) begin
cnt <= (cnt === {12{1'b1}}) ? 12'h0 : cnt + 12'h1;
end
endmodule
| 6.912329 |
module time_val_rdy #(
parameter NAME = "SETME"
) (
input clk,
input rst,
input val,
input rdy
input print
);
real idle, calc, done, sum;
always @ (posedge clk) begin
if (rst) begin
idle = 0;
calc = 0;
done = 0;
end
else begin
case (state)
0: idle = idle + 1;
1: calc = calc + 1;
2: done = done + 1;
endcase
if (print) begin
sum = idle + calc + done;
$display("%s fifo breakdown: idle: %f, calc: %f, done: %f", NAME, idle/sum, calc/sum, done/sum);
end
end
end
endmodule
| 6.908664 |
module top;
reg ck;
specify
$width(posedge ck, 30);
$width(negedge ck, 25);
endspecify
initial $monitor("%4d: ck=%b", $time, ck);
initial begin
ck = 1'b1;
#50;
ck = 1'b0;
$display("No violation expected at %d", $time);
#50;
ck = 1'b1;
$display("No violation expected at %d", $time);
#50;
ck = 1'b0;
$display("No violation expected at %d", $time);
#50;
ck = 1'b1;
$display("No violation expected at %d", $time);
#20;
ck = 1'b0;
$display("$width violation expected at %d on posedge", $time);
#80;
ck = 1'b1;
$display("No violation expected at %d", $time);
#90;
ck = 1'b0;
$display("No violation expected at %d", $time);
#10;
ck = 1'b1;
$display("$width violation expected at %d on negedge", $time);
#50;
ck = 1'b0;
$display("No violation expected at %d", $time);
#50;
end
endmodule
| 6.559821 |
module TimingControl #(
parameter SYM_WIDTH = 1,
parameter INT_WIDTH = 1,
parameter DEC_WIDTH = 14,
parameter signed [`DATA_WIDTH-1 : 0] ONE_DIV_FS_DIV_BAND = 'sh03E3,
parameter signed [`DATA_WIDTH-1 : 0] ONE = 'sh4000
) (
input wire clk,
input wire rstn,
input wire signed [`DATA_WIDTH-1 : 0] TimingControlInputData,
input wire data_ready,
output wire mk,
output wire signed [`DATA_WIDTH-1 : 0] uk
);
wire signed [`DATA_WIDTH-1 : 0] TimingControlModData;
wire signed [INT_WIDTH-1:0] Buffer2int;
wire signed [`DATA_WIDTH-1 : 0] TimingControlBuffer1;
wire mkDelay1, mkDelay2, syncPulseStart, ukSatart;
wire signed [`DATA_WIDTH-1 : 0] TimingControlBuffer2;
assign ukSatart = data_ready & mkDelay2;
assign syncPulseStart = (TimingControlBuffer2 < TimingControlModData) & data_ready;
assign Buffer2int = TimingControlBuffer2[`DATA_WIDTH-1 : DEC_WIDTH];
assign TimingControlBuffer1 = TimingControlModData - TimingControlInputData - ONE_DIV_FS_DIV_BAND;
assign TimingControlModData = (Buffer2int >= 0) ? TimingControlBuffer2 : (TimingControlBuffer2 + ONE);
dfflr #(1) dfflr_mk (
clk,
rstn,
data_ready,
mkDelay1,
mk
);
dfflr #(1) dfflr_Delay1 (
clk,
rstn,
data_ready,
mkDelay2,
mkDelay1
);
dfflr #(`DATA_WIDTH) dfflr_Buffer2 (
clk,
rstn,
data_ready,
TimingControlBuffer1,
TimingControlBuffer2
);
dfflrc #(1) dfflrc_Delay2 (
clk,
rstn,
syncPulseStart,
1'b1,
mkDelay2
);
dfflrc #(`DATA_WIDTH) dfflrc_uk (
clk,
rstn,
ukSatart,
TimingControlModData,
uk
);
endmodule
| 7.634528 |
module timingsgen (
input clock,
input VideoMode videoMode,
output reg [11:0] counterX,
output reg [11:0] counterY,
output reg [11:0] visible_counterX,
output reg [11:0] visible_counterY,
output reg hsync,
output reg vsync,
output reg de,
output reg state
);
/*
H_SYNC H_BACK_PORCH H_ACTIVE H_FRONT_PORCH
V_SYNC V_BACK_PORCH V_ACTIVE V_FRONT_PORCH
*/
/* generate counter */
always @(posedge clock) begin
if (counterX < videoMode.h_total - 1) begin
counterX <= counterX + 1'b1;
end else begin
counterX <= 0;
if (counterY < (state ? videoMode.v_total_2 : videoMode.v_total_1) - 1) begin
counterY <= counterY + 1'b1;
end else begin
counterY <= 0;
state <= ~state;
end
end
end
/* generate visible area timings */
always @(posedge clock) begin
visible_counterX <= counterX + 1'b1 /* add one */ - (videoMode.h_sync + videoMode.h_back_porch);
visible_counterY <= counterY - (videoMode.v_sync + (state ? videoMode.v_back_porch_2 : videoMode.v_back_porch_1));
end
/* generate hsync */
always @(posedge clock) begin
if (counterX < videoMode.h_sync) begin
hsync <= videoMode.h_sync_pol;
end else begin
hsync <= ~videoMode.h_sync_pol;
end
end
`define VerticalSyncPixelOffset (state ? videoMode.v_pxl_offset_2 : videoMode.v_pxl_offset_1)
/* generate vsync */
always @(posedge clock) begin
if (counterY <= videoMode.v_sync) begin
if (counterY == 0 && counterX <
`VerticalSyncPixelOffset
|| counterY == videoMode.v_sync && counterX >= `VerticalSyncPixelOffset) begin
vsync <= ~videoMode.v_sync_pol;
end else begin
vsync <= videoMode.v_sync_pol;
end
end else begin
vsync <= ~videoMode.v_sync_pol;
end
end
/* generate DE */
always @(posedge clock) begin
if (counterX >= videoMode.h_sync + videoMode.h_back_porch
&& counterY >= videoMode.v_sync + (state ? videoMode.v_back_porch_2 : videoMode.v_back_porch_1)
&& counterX < videoMode.h_sync + videoMode.h_back_porch + videoMode.h_active
&& counterY < videoMode.v_sync + (state ? videoMode.v_back_porch_2 : videoMode.v_back_porch_1) + videoMode.v_active)
begin
de <= 1'b1;
end else begin
de <= 0;
end
end
endmodule
| 7.07401 |
module timing_adapter_0001 (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input [7:0] in_data,
// Interface: out
output reg out_valid,
output reg [7:0] out_data,
input out_ready
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [7:0] in_payload;
reg [7:0] out_payload;
reg [0:0] ready;
reg in_ready;
// synthesis translate_off
always @(negedge in_ready) begin
$display(
"%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
end
// synthesis translate_on
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data};
{out_data} = out_payload;
end
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
ready[0] = out_ready;
out_valid = in_valid;
out_payload = in_payload;
in_ready = ready[0];
end
endmodule
| 7.827601 |
module timing_adapter_32 (
// Interface: clk
input clk,
input reset,
// Interface: in
output reg in_ready,
input in_valid,
input [31:0] in_data,
input in_startofpacket,
input in_endofpacket,
input [ 1:0] in_empty,
input in_error,
// Interface: out
input out_ready,
output reg out_valid,
output reg [31:0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 1:0] out_empty,
output reg out_error
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [36:0] in_payload;
wire [36:0] out_payload;
wire in_ready_wire;
wire out_valid_wire;
wire [ 2:0] fifo_fill;
reg ready;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @ (in_data or in_startofpacket or in_endofpacket or in_empty or in_error or out_payload)
begin
in_payload = {in_data, in_startofpacket, in_endofpacket, in_empty, in_error};
{out_data, out_startofpacket, out_endofpacket, out_empty, out_error} = out_payload;
end
// ---------------------------------------------------------------------
//| FIFO
// ---------------------------------------------------------------------
timing_adapter_fifo_32 timing_adapter_fifo (
.clk (clk),
.reset (reset),
.in_ready (),
.in_valid (in_valid),
.in_data (in_payload),
.out_ready (ready),
.out_valid (out_valid_wire),
.out_data (out_payload),
.fill_level(fifo_fill)
);
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @(fifo_fill or out_valid_wire or out_ready) begin
in_ready <= (fifo_fill < 3);
out_valid <= out_valid_wire;
ready = out_ready;
end
endmodule
| 7.827601 |
module timing_adapter_8 (
// Interface: clk
input clk, //INPUT : CLK
input reset, //INPUT : Asynchronous ACTIVE LOW Reset
// Interface: in
output reg in_ready, //OUTPUT : 'TIMING ADAPTER' READYNESS TO ACCEPT DATA FROM 'MAC'
input in_valid, //INPUT : 'MAC TO TIMING ADAPTER' DATA VALID
input [7:0] in_data, //INPUT : 'MAC TO TIMING ADAPTER' DATA
input in_startofpacket, //INPUT : 'MAC TO TIMING ADAPTER' START OF PACKET
input in_endofpacket, //INPUT : 'MAC TO TIMING ADAPTER' END OF PACKET
input in_error, //INPUT : 'MAC TO TIMING ADAPTER' PACKET DATA ERROR
// Interface: out
input out_ready, //INPUT : 'APPLICATION' READYNESS TO ACCEPT DATA FROM 'TIMING ADAPTER'
output reg out_valid, //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA VALID
output reg [7:0] out_data, //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA
output reg out_startofpacket, //OUTPUT : 'TIMING ADAPTER TO APPLICATION' START OF PACKET
output reg out_endofpacket, //OUTPUT : 'TIMING ADAPTER TO APPLICATION' END OF PACKET
output reg out_error //OUTPUT : 'TIMING ADAPTER TO APPLICATION' PACKET DATA ERROR
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [10:0] in_payload;
wire [10:0] out_payload;
wire in_ready_wire;
wire out_valid_wire;
wire [ 6:0] fifo_fill;
reg ready;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @(in_data or in_startofpacket or in_endofpacket or in_error or out_payload) begin
in_payload = {in_data, in_startofpacket, in_endofpacket, in_error};
{out_data, out_startofpacket, out_endofpacket, out_error} = out_payload;
end
// ---------------------------------------------------------------------
//| FIFO
// ---------------------------------------------------------------------
timing_adapter_fifo_8 u_timing_adapter_fifo (
.clk(clk), //INPUT : CLK
.reset(reset), //INPUT : Asynchronous ACTIVE LOW Reset
.in_ready(), //OUTPUT : 'TIMING ADAPTER' READYNESS TO ACCEPT DATA FROM 'MAC'
.in_valid(in_valid), //INPUT : 'MAC TO TIMING ADAPTER' DATA VALID
.in_data(in_payload), //INPUT : 'MAC TO TIMING ADAPTER' DATA
.out_ready(ready), //INPUT : 'APPLICATION' READYNESS TO ACCEPT DATA FROM 'TIMING ADAPTER'
.out_valid(out_valid_wire), //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA VALID
.out_data(out_payload), //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA
.fill_level(fifo_fill) //OUTPUT : 'TIMING ADAPTER' FIFO FILL LEVEL
);
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @(fifo_fill or out_valid_wire or out_ready) begin
in_ready <= (fifo_fill < 40);
out_valid <= out_valid_wire;
ready = out_ready;
end
endmodule
| 7.827601 |
module timing_adapter_fifo_32 (
output reg [3:0] fill_level,
// Interface: clock
input clk,
input reset,
// Interface: data_in
output reg in_ready,
input in_valid,
input [36:0] in_data,
// Interface: data_out
input out_ready,
output reg out_valid,
output reg [36:0] out_data
);
// ---------------------------------------------------------------------
//| Internal Parameters
// ---------------------------------------------------------------------
parameter DEPTH = 8;
parameter DATA_WIDTH = 37;
parameter ADDR_WIDTH = 3;
// ---------------------------------------------------------------------
//| Signals
// ---------------------------------------------------------------------
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] next_wr_addr;
reg [ADDR_WIDTH-1:0] next_rd_addr;
reg [ADDR_WIDTH-1:0] mem_rd_addr;
reg [DATA_WIDTH-1:0] mem[DEPTH-1:0];
reg empty;
reg full;
reg out_ready_vector;
// ---------------------------------------------------------------------
//| FIFO Status
// ---------------------------------------------------------------------
always @(out_ready or wr_addr or rd_addr or full) begin
// out_valid = !empty;
out_ready_vector = out_ready;
in_ready = !full;
next_wr_addr = wr_addr + 1;
next_rd_addr = rd_addr + 1;
fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
fill_level[ADDR_WIDTH] = 0;
if (full) fill_level = DEPTH;
end
// ---------------------------------------------------------------------
//| Manage Pointers
// ---------------------------------------------------------------------
always @(posedge reset or posedge clk) begin
if (reset) begin
wr_addr <= 0;
rd_addr <= 0;
empty <= 1;
rd_addr <= 0;
full <= 0;
out_valid <= 0;
end else begin
out_valid <= !empty;
if (in_ready && in_valid) begin
wr_addr <= next_wr_addr;
empty <= 0;
if (next_wr_addr == rd_addr) full <= 1;
end
if (out_ready_vector && out_valid) begin
rd_addr <= next_rd_addr;
full <= 0;
if (next_rd_addr == wr_addr) begin
empty <= 1;
out_valid <= 0;
end
end
if (out_ready_vector && out_valid && in_ready && in_valid) begin
full <= full;
empty <= empty;
end
end
end // always @ (posedge reset, posedge clk)
always @(rd_addr or out_ready or out_valid or next_rd_addr) begin
mem_rd_addr = rd_addr;
if (out_ready && out_valid) begin
mem_rd_addr = next_rd_addr;
end
end
// ---------------------------------------------------------------------
//| Infer Memory
// ---------------------------------------------------------------------
always @(posedge reset or posedge clk) begin
if (reset) mem[0] <= 38'h0;
else begin
if (in_ready && in_valid) mem[wr_addr] <= in_data;
end
out_data = mem[mem_rd_addr];
end
endmodule
| 7.827601 |
module timing_adapter_fifo_8 (
output reg [6:0] fill_level, //OUTPUT : 'TIMING ADAPTER' FIFO FILL LEVEL
// Interface: clock
input clk, //INPUT : CLK
input reset, //INPUT : Asynchronous ACTIVE LOW Reset
// Interface: data_in
output reg in_ready, //OUTPUT : 'TIMING ADAPTER' READYNESS TO ACCEPT DATA FROM 'MAC'
input in_valid, //INPUT : 'MAC TO TIMING ADAPTER' DATA VALID
input [10:0] in_data, //INPUT : 'MAC TO TIMING ADAPTER' DATA
// Interface: data_out
input out_ready, //INPUT : 'APPLICATION' READYNESS TO ACCEPT DATA FROM 'TIMING ADAPTER'
output reg out_valid, //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA VALID
output reg [10:0] out_data //OUTPUT : 'TIMING ADAPTER TO APPLICATION' DATA
);
// ---------------------------------------------------------------------
//| Internal Parameters
// ---------------------------------------------------------------------
parameter DEPTH = 64;
parameter DATA_WIDTH = 11;
parameter ADDR_WIDTH = 6;
// ---------------------------------------------------------------------
//| Signals
// ---------------------------------------------------------------------
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] next_wr_addr;
reg [ADDR_WIDTH-1:0] next_rd_addr;
reg [ADDR_WIDTH-1:0] mem_rd_addr;
reg [DATA_WIDTH-1:0] mem [DEPTH-1:0];
reg empty;
reg full;
reg out_ready_vector;
integer j;
// ---------------------------------------------------------------------
//| FIFO Status
// ---------------------------------------------------------------------
always @(out_ready or wr_addr or rd_addr or full) begin
// out_valid = !empty;
out_ready_vector = out_ready;
in_ready = !full;
next_wr_addr = wr_addr + 1;
next_rd_addr = rd_addr + 1;
fill_level[ADDR_WIDTH-1:0] = wr_addr - rd_addr;
fill_level[ADDR_WIDTH] = 0;
if (full) fill_level = DEPTH;
end
// ---------------------------------------------------------------------
//| Manage Pointers
// ---------------------------------------------------------------------
always @(posedge reset or posedge clk) begin
if (reset) begin
wr_addr <= 0;
rd_addr <= 0;
empty <= 1;
rd_addr <= 0;
full <= 0;
out_valid<= 0;
end else begin
out_valid <= !empty;
if (in_ready && in_valid) begin
wr_addr <= next_wr_addr;
empty <= 0;
if (next_wr_addr == rd_addr) full <= 1;
end
if (out_ready_vector && out_valid) begin
rd_addr <= next_rd_addr;
full <= 0;
if (next_rd_addr == wr_addr) begin
empty <= 1;
out_valid <= 0;
end
end
if (out_ready_vector && out_valid && in_ready && in_valid) begin
full <= full;
empty <= empty;
end
end
end // always @ (posedge reset, posedge clk)
always @(rd_addr or out_ready or out_valid or next_rd_addr) begin
mem_rd_addr = rd_addr;
if (out_ready && out_valid) begin
mem_rd_addr = next_rd_addr;
end
end
// ---------------------------------------------------------------------
//| Infer Memory
// ---------------------------------------------------------------------
always @(posedge reset or posedge clk) begin
if (reset) begin
for (j = 0; j < DEPTH; j = j + 1) begin
mem[j] <= 11'h0;
end
end else begin
if (in_ready && in_valid) mem[wr_addr] <= in_data;
end
out_data = mem[mem_rd_addr];
end
endmodule
| 7.827601 |
module timingcontrol (
wrflag,
MEMWR,
cs,
clk,
HLDA,
AEN,
reset,
IReady,
TReady,
IOR,
IOW,
IOflag,
mem2mem,
Data_flag,
flag_data_ready,
address_ready,
processor_write_done,
myBus,
command_writed,
request_writed,
address_bus,
TC
); //IOflag for data is out from IO device
input cs,clk,HLDA,reset,wrflag,mem2mem,flag_data_ready,address_ready,myBus,processor_write_done,command_writed,request_writed; //wrflag is a flag indicates wether the IO device will read or write
input [15:0] address_bus;
reg write;
output reg AEN, Data_flag = 1;
inout TReady, IReady,MEMWR; //IOW and IOR always input to the DMA but they are defined as inout because the are on the control bus
input IOR, IOW, IOflag, TC;
reg iready, tready, memwr;
wire myBus;
assign myBus = (address_bus >= 0 && address_bus <= 15);
assign IReady = (HLDA === 1 && mem2mem === 0) ? iready : 1'bz; //when the DMA is a master
assign TReady = ((IOR===0) || (IOW===0))? tready :1'bz ; //When the DMA is a target and called by address from the processor
assign MEMWR = (HLDA) ? wrflag : 1'bz;
initial begin
AEN <= 0;
end
always @(posedge TC) begin
AEN = 0;
end
always @(posedge IReady or posedge reset or posedge wrflag) begin
if (!cs) begin
if (!IOW && IOR) begin
@(posedge processor_write_done, posedge command_writed, posedge request_writed);
tready = 1;
@(negedge IReady);
tready = 0;
end
if (!reset) begin
if (HLDA) begin
AEN <= 1;
end else if (!HLDA) begin
AEN <= 0;
end
if (wrflag === 1 && HLDA === 1) begin
if (IOflag) begin
memwr = 1;
iready = 1;
@(posedge TReady); //waiting for ack from memo
iready = 0;
end else if (mem2mem && Data_flag && MEMWR) begin
Data_flag = 1;
@(posedge flag_data_ready);
memwr = 1;
iready = 1;
@(posedge TReady); //waiting for ack from memo
iready = 0;
Data_flag = 0;
end
end else if (wrflag === 0 && HLDA === 1) begin
@(posedge address_ready);
memwr = 0;
iready = 1;
@(posedge TReady); //waiting for memo to finish
iready = 0;
end
end else if (reset) begin
memwr <= 1'bz;
AEN <= 0;
end
end
end
endmodule
| 7.163447 |
module timing_counter #(
parameter nCK_PER_CLK = 4,
parameter DDR_PRD = 2.5,
parameter TP = 35
) (
input clk,
input rst,
input start,
input [(`CLOG2(nCK_PER_CLK))-1:0] slot,
output [(`CLOG2(nCK_PER_CLK))-1:0] offset,
output done
);
localparam integer CTR_VAL = $ceil((TP - (nCK_PER_CLK * DDR_PRD)) / DDR_PRD);
reg [(`CLOG2(TP)):0] counter_r;
assign done = counter_r < nCK_PER_CLK;
assign offset = counter_r[nCK_PER_CLK-1:0];
always @(posedge clk) begin
if (rst) begin
counter_r <= CTR_VAL;
end else begin
if (start) begin
counter_r <= CTR_VAL + slot;
end else begin
if (counter_r < nCK_PER_CLK) counter_r = 0;
else counter_r = counter_r - nCK_PER_CLK;
end
end
end
endmodule
| 7.572248 |
module timing (
input clk,
input rst,
input valid,
input [3:0] strb,
input [2:0] addr,
input [31:0] data_i,
output reg ready,
output reg irq
);
reg timer_en;
reg [31:0] TIMER_CNT_MAX;
reg [31:0] timer_cnt;
always @(posedge clk)
if (rst) ready <= 1'b0;
else if (valid & !ready & (addr <= 3'h4)) ready <= 1'b1;
else ready <= 1'b0;
always @(posedge clk)
if (rst) timer_en <= 1'b0;
else if (valid & strb[0] & (addr == 3'h0)) timer_en <= data_i[0];
always @(posedge clk)
if (rst) TIMER_CNT_MAX <= 32'd50;
else if (valid & (strb == 4'hF) & (addr == 3'h4)) TIMER_CNT_MAX <= data_i;
always @(posedge clk)
if (rst) timer_cnt <= 32'd0;
else if (timer_en & (timer_cnt < TIMER_CNT_MAX)) timer_cnt <= timer_cnt + 1'b1;
else timer_cnt <= 32'h0;
always @(posedge clk)
if (rst) irq <= 1'b0;
else if (timer_cnt == TIMER_CNT_MAX) irq <= 1'b1;
else irq <= 1'b0;
endmodule
| 6.81778 |
module timing_ctrl_shift (
output wire seventy_d35,
output wire da, // Sign test pulse for Multiplicand (via CCU 2).
output wire dx, // Digit test pulse for Multiplier.
output wire dy, // Resetting pulse after addition of partial product.
output wire g2_pos, // Multiplicand and shifting gate.
output wire g2_neg, // Inverse Multiplicand and shifting gate.
input wire clk,
input wire c5, // V, N orders - multiply and add/subtract (V/N).
input wire c6, // R, L order - right and left shift respectively.
input wire zero_d0,
input wire d35
);
wire g2_pos_del;
wire g2_neg_del;
wire timing_store_in;
wire timing_store_out;
wire ff_set;
assign ff_set = (timing_store_out & (c5 | c6) & g2_neg_del) | zero_d0;
assign da = g2_pos_del & timing_store_out;
flipflop ff_g2 (
.out (g2_pos),
.out_bar(g2_neg),
.set (ff_set),
.reset (dy)
);
assign timing_store_in = dy | ff_set;
// 1 M/C (36 p.i.) 72 us delay tank.
delay #(
.INTERVAL(36)
) timing_store (
.out(timing_store_out),
.clk(clk),
.in (timing_store_in)
);
// 1 p.i. delay that generates successive dy pulses.
delay #(
.INTERVAL(1)
) dl_dy (
.out(dy),
.clk(clk),
.in (da)
);
delay #(
.INTERVAL(1)
) dl_pos (
.out(g2_pos_del),
.clk(clk),
.in (g2_pos)
);
delay #(
.INTERVAL(1)
) dl_neg (
.out(g2_neg_del),
.clk(clk),
.in (g2_neg)
);
assign dx = ff_set & c5;
assign seventy_d35 = d35 & ff_set;
endmodule
| 7.166194 |
module timing_gen #(
parameter DELAY = 10,
parameter WIDTH = 20
) (
input wire clk,
input wire reset,
output reg tgen
);
initial begin
tgen = 1'b0;
end
always @(posedge clk) tgen = #DELAY 1'b1;
always @(posedge tgen) tgen = #WIDTH 1'b0;
endmodule
| 6.905555 |
module timing_generator_VGA (
input wire clk,
reset,
output wire hsync,
vsync,
video_on,
p_tick,
output wire [9:0] pixel_x,
pixel_y
);
//Declaracin de constantes
//Parmetros para VGA 640x480
localparam HD = 640; //rea de despliegue horizontal
localparam HF = 48; // borde izquierdo horizontal
localparam HB = 16; //borde derecho horizontal(16)
localparam HR = 96; //retraso horizontal
localparam VD = 480; //rea de despliegue vertical
localparam VF = 10; //borde superior vertical
localparam VB = 33; //borde inferior vertical
localparam VR = 2; //retraso vertical
//Contadores
//Contador para la divisin de frecuencia (100 MHz a 25 MHz)
//reg mod2_reg;
//wire mod2_next;
reg cuenta, CV;
//Contadores de "timing" vertical y horizontal
reg [9:0] h_count_reg, h_count_next;
reg [9:0] v_count_reg, v_count_next;
reg h_sync_reg, v_sync_reg;
wire h_sync_next, v_sync_next;
//Seales de status
wire h_end, v_end;
wire pixel_tick;
//Definicin de comportamiento
//Registros
always @(posedge clk, posedge reset) begin
if (reset) begin
//mod2_reg <= 1'b0;
h_count_reg <= 0;
v_count_reg <= 0;
h_sync_reg <= 1'b0;
v_sync_reg <= 1'b0;
end else begin
//mod2_reg <= mod2_next;
h_count_reg <= h_count_next;
v_count_reg <= v_count_next;
h_sync_reg <= h_sync_next;
v_sync_reg <= v_sync_next;
end
end
//Para generar 25 MHz
always @(posedge clk, posedge reset) begin
if (reset) begin
cuenta <= 0;
CV <= 0;
end else begin
if (cuenta == 1'b1) begin
cuenta <= 0;
CV <= ~CV;
end else cuenta <= cuenta + 1'b1;
end
end
//assign mod2_next = ~mod2_reg;
assign pixel_tick = CV;
//Definicin seales de status
//Final del contador horizontal (799)
assign h_end = (h_count_reg == (HD + HF + HB + HR - 1));
//Final contador vertical (524)
assign v_end = (v_count_reg == (VD + VF + VB + VR - 1));
//Lgicas de estado siguiente de los contadores
//Contador horizontal
always @(negedge pixel_tick) begin
//if(pixel_tick) //pulso de 25 MHz
if (h_end) h_count_next = 0;
else h_count_next = h_count_reg + 1'b1;
/* else
h_count_next = h_count_reg; //Mantiene la cuenta*/
end
//Contador vertical
always @(negedge pixel_tick) begin
//if(pixel_tick & h_end) //pulso de 25 MHz y final de fila
if (h_end) //pulso de 25 MHz y final de fila
if (v_end) v_count_next = 0;
else v_count_next = v_count_reg + 1'b1;
else v_count_next = v_count_reg; //Mantiene la cuenta
end
/*h_sync_next puesto en bajo para generar retraso
entre la cuentas 656 y 751*/
assign h_sync_next = (h_count_reg >= (HD + HB) && h_count_reg <= (HD + HB + HR - 1));
/*v_sync_next puesto en bajo para generar retraso
entre la cuentas 490 y 491*/
assign v_sync_next = (v_count_reg >= (VD + VB) && v_count_reg <= (VD + VB + VR - 1));
//Asignacin de salidas
//Para generar seal video on/off
assign video_on = (h_count_reg < HD) && (v_count_reg < VD); //Para mantener una forma de saber si el pixel est en la regin visible
assign hsync = ~h_sync_reg;
assign vsync = ~v_sync_reg;
assign pixel_x = h_count_reg; //Coordenada x
assign pixel_y = v_count_reg; //Coordenada y
assign p_tick = pixel_tick; //Ayuda a coordinar la creacin de imgenes (mdulo de generacin de pxeles)
endmodule
| 7.784965 |
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