code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module three_input_or_gate_a (
input a,
input b,
input c,
output d
);
assign d = a | b | c;
endmodule
| 6.687992 |
module three_input_or_gate_a_tb;
reg aa, bb, cc;
wire d;
three_input_or_gate_a u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(d)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 6.687992 |
module three_input_or_gate_tb;
reg aa, bb, cc;
wire x, y;
three_input_or_gate u_three_input_or_gate (
.a(aa),
.b(bb),
.c(cc),
.x(x),
.y(y)
);
initial aa = 0'b0;
initial bb = 0'b0;
initial cc = 0'b0;
always aa = #50 ~aa;
always bb = #100 ~bb;
always cc = #200 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 6.687992 |
module three_ip_tb;
wire t_p, t_q, t_r;
reg [2:0] inTest;
gate dut (
.a(inTest[2]),
.b(inTest[1]),
.c(inTest[0]),
.p(t_p),
.q(t_q),
.r(t_r)
);
initial begin
$monitor(inTest[0], inTest[1], inTest[2], t_p, t_q, t_r);
inTest = 3'b000;
#60 inTest = 3'b001;
#60 inTest = 3'b010;
#60 inTest = 3'b011;
#60 inTest = 3'b100;
#60 inTest = 3'b101;
#60 inTest = 3'b110;
#60 inTest = 3'b111;
#60 $finish;
end
endmodule
| 7.120881 |
module: Three_parallel_CRC_retimed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Verilog testbench code for generator polynomial 1+y+y8+y9 with 3 level unfolding and retimed
module Three_parallel_CRC_retimed_test;
// Inputs
reg clk;
reg reset;
reg [8:0] data_in;
// Outputs
wire [8:0] data_out;
// Instantiate the Unit Under Test (UUT)
Three_parallel_CRC_retimed uut (
.clk(clk),
.reset(reset),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clk = 0;
reset = 1;
//data_in = 10'b1100000011;
data_in = 9'b101011010;
//data_in = 10'b1011001011;
#1
reset = 0;
end
always #1 clk = ~clk;
endmodule
| 8.224695 |
module: Three_parallel_CRC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Verilog testbench code for generator polynomial 1+y+y8+y9 with 3 level unfolding
module Three_parallel_CRC_test;
// Inputs
reg clk;
reg reset;
reg [8:0] data_in;
// Outputs
wire [8:0] data_out;
// Instantiate the Unit Under Test (UUT)
Three_parallel_CRC uut (
.clk(clk),
.reset(reset),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clk = 0;
reset = 1;
//data_in = 10'b1100000011;
data_in = 9'b101011010;
//data_in = 10'b1011001011;
#1
reset = 0;
end
always #1 clk = ~clk;
endmodule
| 8.224695 |
module Three_phase_sin (
clk,
out_p1,
out_p1_inv,
out_p2,
out_p2_inv,
out_p3,
out_p3_inv,
freq_adj
);
input clk;
input [3:0] freq_adj;
output out_p1, out_p1_inv, out_p2, out_p2_inv, out_p3, out_p3_inv;
wire [7:0] duty_cycle_1;
wire [7:0] duty_cycle_2;
wire [7:0] duty_cycle_3;
wire [7:0] address_p1;
wire [7:0] address_p2;
wire [7:0] address_p3;
wire en;
wire clock;
pwm u1 (
.duty_cycle(duty_cycle_1),
.clk(clk),
.out(out_p1),
.en(en)
);
pwm u2 (
.duty_cycle(duty_cycle_2),
.clk(clk),
.out(out_p2),
.en(en)
);
pwm u3 (
.duty_cycle(duty_cycle_3),
.clk(clk),
.out(out_p3),
.en(en)
);
sin_look_up u4 (
.address(address_p1),
.duty_cycle(duty_cycle_1)
);
sin_look_up u5 (
.address(address_p2),
.duty_cycle(duty_cycle_2)
);
sin_look_up u6 (
.address(address_p3),
.duty_cycle(duty_cycle_3)
);
clk_div u7 (
.clk(clk),
.clk_sel(freq_adj),
.clk_out(clock)
);
modulation_con u8 (
.clk(clock),
.address_p1(address_p1),
.address_p2(address_p2),
.address_p3(address_p3)
);
assign en = 1;
assign out_p1_inv = ~out_p1;
assign out_p2_inv = ~out_p2;
assign out_p3_inv = ~out_p3;
endmodule
| 7.248268 |
module clk_div (
clk,
clk_sel,
clk_out
);
input clk;
input [3:0] clk_sel;
output reg clk_out;
reg [15:0] counter;
reg [15:0] next_counter;
always @(posedge clk) begin
counter = next_counter;
end
always @* begin
next_counter = counter + 1;
case (clk_sel[3:0])
0: clk_out = counter[0];
1: clk_out = counter[1];
2: clk_out = counter[2];
3: clk_out = counter[3];
4: clk_out = counter[4];
5: clk_out = counter[5];
6: clk_out = counter[6];
7: clk_out = counter[7];
8: clk_out = counter[8];
9: clk_out = counter[9];
10: clk_out = counter[10];
11: clk_out = counter[11];
12: clk_out = counter[12];
13: clk_out = counter[13];
14: clk_out = counter[14];
15: clk_out = counter[15];
endcase
end
endmodule
| 7.520262 |
module three_port_reg_file (
data,
load,
clk,
clr,
addrD,
addrA,
addrB,
a,
b
);
input [3:0] data;
input load, clk, clr;
input [2:0] addrD, addrA, addrB;
output [3:0] a, b;
reg [3:0] reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8;
wire[7:0] decoder; // reg로 선언하면 "error: cannot be driven by primitives or continuous assignment"
wire [7:0] enable; // 1 bit enable 8개
decoder_3to8 uut (
addrD,
decoder
);
assign enable = decoder & {load, load, load, load, load, load, load, load};
always @(posedge clr) begin
reg1 = 0;
reg2 = 0;
reg3 = 0;
reg4 = 0;
reg5 = 0;
reg6 = 0;
reg7 = 0;
reg8 = 0;
end
always @(posedge clk) begin
case (enable)
8'b00000001: reg1 = data;
8'b00000010: reg2 = data;
8'b00000100: reg3 = data;
8'b00001000: reg4 = data;
8'b00010000: reg5 = data;
8'b00100000: reg6 = data;
8'b01000000: reg7 = data;
8'b10000000: reg8 = data;
endcase
end
mux_8to1 A (
reg1,
reg2,
reg3,
reg4,
reg5,
reg6,
reg7,
reg8,
addrA,
a
);
mux_8to1 B (
reg1,
reg2,
reg3,
reg4,
reg5,
reg6,
reg7,
reg8,
addrB,
b
);
endmodule
| 6.786619 |
module main (
clk
);
input clk;
wire all_shared, is_sharedA, is_sharedB, is_sharedC;
wire ND_inA, ND_inB, ND_inC, ndA, ndB, ndC;
wire master_outA, master_outB, master_outC;
wire master_inA, master_inB, master_inC;
wire inv_outA, inv_outB, inv_outC, invalidate;
wire mem_served;
wire info_availA, info_availB, info_availC;
wire bus_reqA, bus_reqB, bus_reqC;
wire bus_ackA, bus_ackB, bus_ackC;
wire [2:0] snoop_typeA, snoop_typeB, snoop_typeC;
wire [2:0] shared_snoop;
pcache pcacheA (
clk,
shared_snoop,
is_snoop,
master_inA,
ND_inA,
bus_ackA,
all_shared,
mem_served,
invalidate,
inv_outA,
snoop_typeA,
bus_reqA,
master_outA,
is_sharedA,
info_availA
);
pcache pcacheB (
clk,
shared_snoop,
is_snoop,
master_inB,
ND_inB,
bus_ackB,
all_shared,
mem_served,
invalidate,
inv_outB,
snoop_typeB,
bus_reqB,
master_outB,
is_sharedB,
info_availB
);
pcache pcacheC (
clk,
shared_snoop,
is_snoop,
master_inC,
ND_inC,
bus_ackC,
all_shared,
mem_served,
invalidate,
inv_outC,
snoop_typeC,
bus_reqC,
master_outC,
is_sharedC,
info_availC
);
assign all_shared = (is_sharedA && is_sharedB && is_sharedC);
// All the proceesors are in Shared state
assign ND_inA = ndA && !bus_ackA;
assign ND_inB = (master_outA) ? ND_inA : (ndB && !bus_ackB);
// Non deter. B if proc. A is not Master
assign ND_inC = (master_outA) ? ND_inB : (master_outB) ? ND_inB : (ndC && !bus_ackC);
// Non deter. C if proc. A & B not Master
assign master_inA = 0;
assign master_inB = master_outA;
assign master_inC = (master_outA || master_outB);
// initial
// begin
// random_regA = 4831;
// random_regB = 5237;
// random_regC = 12098;
// end
// always @(posedge clk)
// begin
// random_regA = $random($time);
// random_regB = $random($time+20);
// random_regC = $random($time-10);
// end
// assign ndA = random_regA[4];
// assign ndB = random_regB[6];
// assign ndC = random_regC[15];
assign ndA = {0, 1};
assign ndB = {0, 1};
assign ndC = {0, 1};
assign mem_served = !(info_availA || info_availB || info_availC);
// if no proc. has info, Mem supplies
arbiter bus_arbiter (
clk,
bus_reqA,
bus_reqB,
bus_reqC,
snoop_typeA,
snoop_typeB,
snoop_typeC,
inv_outA,
inv_outB,
inv_outC,
bus_ackA,
bus_ackB,
bus_ackC,
is_snoop,
shared_snoop,
invalidate
);
endmodule
| 7.779865 |
module main (
clk
);
input clk;
wire all_shared, is_sharedA, is_sharedB, is_sharedC;
wire ND_inA, ND_inB, ND_inC, ndA, ndB, ndC;
wire master_outA, master_outB, master_outC;
wire master_inA, master_inB, master_inC;
wire inv_outA, inv_outB, inv_outC, invalidate;
wire mem_served;
wire info_availA, info_availB, info_availC;
wire bus_reqA, bus_reqB, bus_reqC;
wire bus_ackA, bus_ackB, bus_ackC;
wire [2:0] snoop_typeA, snoop_typeB, snoop_typeC;
wire [2:0] shared_snoop;
wire is_snoop;
pcache pcacheA (
clk,
shared_snoop,
is_snoop,
master_inA,
ND_inA,
bus_ackA,
all_shared,
mem_served,
invalidate,
inv_outA,
snoop_typeA,
bus_reqA,
master_outA,
is_sharedA,
info_availA
);
pcache pcacheB (
clk,
shared_snoop,
is_snoop,
master_inB,
ND_inB,
bus_ackB,
all_shared,
mem_served,
invalidate,
inv_outB,
snoop_typeB,
bus_reqB,
master_outB,
is_sharedB,
info_availB
);
pcache pcacheC (
clk,
shared_snoop,
is_snoop,
master_inC,
ND_inC,
bus_ackC,
all_shared,
mem_served,
invalidate,
inv_outC,
snoop_typeC,
bus_reqC,
master_outC,
is_sharedC,
info_availC
);
assign all_shared = (is_sharedA && is_sharedB && is_sharedC);
// All the proceesors are in Shared state
assign ND_inA = ndA && !bus_ackA;
assign ND_inB = (master_outA == 1'b1) ? ND_inA : (ndB & !bus_ackB);
// Non deter. B if proc. A is not Master
assign ND_inC = (master_outA == 1'b1) ? ND_inB : (master_outB == 1'b1) ? ND_inB : (ndC & !bus_ackC);
// Non deter. C if proc. A & B not Master
assign master_inA = 0;
assign master_inB = master_outA;
assign master_inC = (master_outA || master_outB);
// initial
// begin
// random_regA = 4831;
// random_regB = 5237;
// random_regC = 12098;
// end
// always @(posedge clk)
// begin
// random_regA = $random($time);
// random_regB = $random($time+20);
// random_regC = $random($time-10);
// end
// assign ndA = random_regA[4];
// assign ndB = random_regB[6];
// assign ndC = random_regC[15];
assign ndA = {0, 1};
assign ndB = {0, 1};
assign ndC = {0, 1};
assign mem_served = !(info_availA || info_availB || info_availC);
// if no proc. has info, Mem supplies
arbiter bus_arbiter (
clk,
bus_reqA,
bus_reqB,
bus_reqC,
snoop_typeA,
snoop_typeB,
snoop_typeC,
inv_outA,
inv_outB,
inv_outC,
bus_ackA,
bus_ackB,
bus_ackC,
is_snoop,
shared_snoop,
invalidate
);
endmodule
| 7.779865 |
module three_stage_mult (
input [15:0] a,
input [15:0] b,
output [31:0] out,
input clk
);
logic [31:0] register;
logic [31:0] register2;
logic [31:0] register3;
always @(posedge clk) begin
register <= a * b;
register2 <= register;
register3 <= register2;
end
assign out = register3;
endmodule
| 7.099054 |
module three_state_gates (
input iA,
input iEna,
output oTri
);
assign oTri = (iEna == 1) ? iA : 'bz;
endmodule
| 8.00834 |
module three_state_gates_tb;
reg iA;
reg iEna;
wire oTristate;
three_state_gates uut (
.iA (iA),
.iEna(iEna),
.oTri(oTriState)
);
initial begin
iA = 0;
#40 iA = 1;
#40 iA = 0;
#40 iA = 1;
end
initial begin
iEna = 1;
#20 iEna = 0;
#40 iEna = 1;
#40 iEna = 0;
end
endmodule
| 8.00834 |
module three_to_eight_decoder (
input [2:0] in,
output reg [7:0] out
);
always @(in) begin
case (in)
0: out <= 8'd0;
1: out <= 8'd1;
2: out <= 8'd2;
3: out <= 8'd4;
4: out <= 8'd8;
5: out <= 8'd16;
6: out <= 8'd32;
7: out <= 8'd64;
endcase
end
endmodule
| 6.539167 |
module three_to_vote (
sw3,
agreement
);
input [2:0] sw3;
output reg agreement;
wire result;
wire w1, w2, w3;
always @(sw3) begin
agreement = ~result;
end
gate_1 u1 (
.a (sw3[0]),
.b (sw3[1]),
.out(w1)
);
gate_1 u2 (
.a (sw3[0]),
.b (sw3[2]),
.out(w2)
);
gate_1 u3 (
.a (sw3[1]),
.b (sw3[2]),
.out(w3)
);
gate_2 u4 (
.a (w1),
.b (w2),
.c (w3),
.out(result)
);
endmodule
| 6.920259 |
module gate_1 (
out,
a,
b
);
input a, b;
output out;
assign out = ~(a & b);
endmodule
| 8.208518 |
module gate_2 (
out,
a,
b,
c
);
input a, b, c;
output out;
assign out = ~(a & b & c);
endmodule
| 8.775338 |
module three_two_comp (
data,
sum
);
input [2:0] data;
output [1:0] sum;
reg [1:0] sum;
always @(data) begin
case (data)
0: sum = 0;
1: sum = 1;
2: sum = 1;
3: sum = 2;
4: sum = 1;
5: sum = 2;
6: sum = 2;
7: sum = 3;
default: sum = 0;
endcase
end
endmodule
| 6.900058 |
module three_wire_controller ( // Host Side
iCLK,
iRST,
iDATA,
iSTR,
oACK,
oRDY,
oCLK,
// Serial Side
oSCEN,
SDA,
oSCLK
);
// Host Side
input iCLK;
input iRST;
input iSTR;
input [15:0] iDATA;
output oACK;
output oRDY;
output oCLK;
// Serial Side
output oSCEN;
inout SDA;
output oSCLK;
// Internal Register and Wire
reg mSPI_CLK;
reg [15:0] mSPI_CLK_DIV;
reg mSEN;
reg mSDATA;
reg mSCLK;
reg mACK;
reg [4:0] mST;
parameter CLK_Freq = 50000000; // 50 MHz
parameter SPI_Freq = 20000; // 20 KHz
// Serial Clock Generator
always @(posedge iCLK or negedge iRST) begin
if (!iRST) begin
mSPI_CLK <= 0;
mSPI_CLK_DIV <= 0;
end else begin
if (mSPI_CLK_DIV < (CLK_Freq / SPI_Freq)) mSPI_CLK_DIV <= mSPI_CLK_DIV + 1;
else begin
mSPI_CLK_DIV <= 0;
mSPI_CLK <= ~mSPI_CLK;
end
end
end
// Parallel to Serial
always @(negedge mSPI_CLK or negedge iRST) begin
if (!iRST) begin
mSEN <= 1'b1;
mSCLK <= 1'b0;
mSDATA <= 1'bz;
mACK <= 1'b0;
mST <= 4'h00;
end else begin
if (iSTR) begin
if (mST < 17) mST <= mST + 1'b1;
if (mST == 0) begin
mSEN <= 1'b0;
mSCLK <= 1'b1;
end else if (mST == 8) mACK <= SDA;
else if (mST == 16 && mSCLK) begin
mSEN <= 1'b1;
mSCLK <= 1'b0;
end
if (mST < 16) mSDATA <= iDATA[15-mST];
end else begin
mSEN <= 1'b1;
mSCLK <= 1'b0;
mSDATA <= 1'bz;
mACK <= 1'b0;
mST <= 4'h00;
end
end
end
assign oACK = mACK;
assign oRDY = (mST == 17) ? 1'b1 : 1'b0;
assign oSCEN = mSEN;
assign oSCLK = mSCLK & mSPI_CLK;
assign SDA = (mST == 8) ? 1'bz : (mST == 17) ? 1'bz : mSDATA;
assign oCLK = mSPI_CLK;
endmodule
| 9.574951 |
module threshold #(
parameter THRESHOLD = 35
) (
input signed [15:0] data_x,
output is_over_threshold
);
wire is_over_threshold = (data_x > THRESHOLD) | (data_x < -THRESHOLD);
endmodule
| 6.69762 |
module threshold2_mul_mulbW_DSP48_0 (
a,
b,
p
);
input [8 - 1 : 0] a;
input [14 - 1 : 0] b;
output [21 - 1 : 0] p;
assign p = $unsigned(a) * $unsigned(b);
endmodule
| 6.669315 |
module threshold2_mul_mulbW (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
threshold2_mul_mulbW_DSP48_0 threshold2_mul_mulbW_DSP48_0_U (
.a(din0),
.b(din1),
.p(dout)
);
endmodule
| 6.669315 |
module threshold2_mul_murcU_DSP48_5 (
a,
b,
p
);
input [20 - 1 : 0] a;
input [8 - 1 : 0] b;
output [28 - 1 : 0] p;
assign p = $unsigned(a) * $unsigned(b);
endmodule
| 6.669315 |
module threshold2_mul_murcU (
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
threshold2_mul_murcU_DSP48_5 threshold2_mul_murcU_DSP48_5_U (
.a(din0),
.b(din1),
.p(dout)
);
endmodule
| 6.669315 |
module threshold2_mux_32kbM #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
dout_WIDTH = 32
) (
input [7 : 0] din0,
input [7 : 0] din1,
input [7 : 0] din2,
input [1 : 0] din3,
output [7 : 0] dout
);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [7 : 0] mux_1_0;
wire [7 : 0] mux_1_1;
// level 2 signals
wire [7 : 0] mux_2_0;
assign sel = din3;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = din2;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
| 6.669315 |
module threshold2_udiv_2pcA_div_u #(
parameter in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
) (
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output wire [out_WIDTH-1:0] quot,
output wire [out_WIDTH-1:0] remd
);
localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH) ? in0_WIDTH : in1_WIDTH;
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend_tmp[0:in0_WIDTH];
reg [in1_WIDTH-1:0] divisor_tmp[0:in0_WIDTH];
reg [in0_WIDTH-1:0] remd_tmp[0:in0_WIDTH];
wire [in0_WIDTH-1:0] comb_tmp[0:in0_WIDTH-1];
wire [cal_WIDTH:0] cal_tmp[0:in0_WIDTH-1];
//------------------------Body---------------------------
assign quot = dividend_tmp[in0_WIDTH];
assign remd = remd_tmp[in0_WIDTH];
// dividend_tmp[0], divisor_tmp[0], remd_tmp[0]
always @(posedge clk) begin
if (ce) begin
dividend_tmp[0] <= dividend;
divisor_tmp[0] <= divisor;
remd_tmp[0] <= 1'b0;
end
end
genvar i;
generate
for (i = 0; i < in0_WIDTH; i = i + 1) begin : loop
if (in0_WIDTH == 1) assign comb_tmp[i] = dividend_tmp[i][0];
else assign comb_tmp[i] = {remd_tmp[i][in0_WIDTH-2:0], dividend_tmp[i][in0_WIDTH-1]};
assign cal_tmp[i] = {1'b0, comb_tmp[i]} - {1'b0, divisor_tmp[i]};
always @(posedge clk) begin
if (ce) begin
if (in0_WIDTH == 1) dividend_tmp[i+1] <= ~cal_tmp[i][cal_WIDTH];
else dividend_tmp[i+1] <= {dividend_tmp[i][in0_WIDTH-2:0], ~cal_tmp[i][cal_WIDTH]};
divisor_tmp[i+1] <= divisor_tmp[i];
remd_tmp[i+1] <= cal_tmp[i][cal_WIDTH] ? comb_tmp[i] : cal_tmp[i][in0_WIDTH-1:0];
end
end
end
endgenerate
endmodule
| 6.687156 |
module threshold2_udiv_2pcA_div #(
parameter in0_WIDTH = 32,
in1_WIDTH = 32,
out_WIDTH = 32
) (
input clk,
input reset,
input ce,
input [in0_WIDTH-1:0] dividend,
input [in1_WIDTH-1:0] divisor,
output reg [out_WIDTH-1:0] quot,
output reg [out_WIDTH-1:0] remd
);
//------------------------Local signal-------------------
reg [in0_WIDTH-1:0] dividend0;
reg [in1_WIDTH-1:0] divisor0;
wire [in0_WIDTH-1:0] dividend_u;
wire [in1_WIDTH-1:0] divisor_u;
wire [out_WIDTH-1:0] quot_u;
wire [out_WIDTH-1:0] remd_u;
//------------------------Instantiation------------------
threshold2_udiv_2pcA_div_u #(
.in0_WIDTH(in0_WIDTH),
.in1_WIDTH(in1_WIDTH),
.out_WIDTH(out_WIDTH)
) threshold2_udiv_2pcA_div_u_0 (
.clk (clk),
.reset (reset),
.ce (ce),
.dividend(dividend_u),
.divisor (divisor_u),
.quot (quot_u),
.remd (remd_u)
);
//------------------------Body---------------------------
assign dividend_u = dividend0;
assign divisor_u = divisor0;
always @(posedge clk) begin
if (ce) begin
dividend0 <= dividend;
divisor0 <= divisor;
end
end
always @(posedge clk) begin
if (ce) begin
quot <= quot_u;
remd <= remd_u;
end
end
endmodule
| 6.687156 |
module threshold2_udiv_2pcA (
clk,
reset,
ce,
din0,
din1,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
output [dout_WIDTH - 1:0] dout;
wire [dout_WIDTH - 1:0] sig_remd;
threshold2_udiv_2pcA_div #(
.in0_WIDTH(din0_WIDTH),
.in1_WIDTH(din1_WIDTH),
.out_WIDTH(dout_WIDTH)
) threshold2_udiv_2pcA_div_U (
.dividend(din0),
.divisor(din1),
.quot(dout),
.remd(sig_remd),
.clk(clk),
.ce(ce),
.reset(reset)
);
endmodule
| 6.687156 |
module Testbench_4 ();
reg Go_s;
wire [(`A_WIDTH-1):0] P_Addr_s, B_Addr_s;
wire [(`D_WIDTH-1):0] P_Data_s, P_Di_s, B_Data_s;
wire [(`V_WIDTH-1):0] T_Out_s;
wire I_RW_s, I_En_s, O_RW_s, O_En_s, Done_s;
reg Clk_s, Rst_t, Rst_p, Rst_b;
parameter ClkPeriod = 20;
Tresholding_4 CompToTest (
Go_s,
P_Addr_s,
P_Data_s,
B_Addr_s,
I_RW_s,
I_En_s,
O_RW_s,
O_En_s,
Done_s,
T_Out_s,
Clk_s,
Rst_t
);
Sram_Operand MemP (
P_Di_s,
P_Data_s,
P_Addr_s,
I_RW_s,
I_En_s,
Clk_s,
Rst_p
);
Sram_Operand MemB (
T_Out_s,
B_Data_s,
B_Addr_s,
O_RW_s,
O_En_s,
Clk_s,
Rst_b
);
// Clock Procedure
always begin
Clk_s <= 1'b0;
#(ClkPeriod / 2);
Clk_s <= 1'b1;
#(ClkPeriod / 2);
end
reg [(`D_WIDTH-1):0] Ref[0:(76800-1)];
reg [17:0] Count;
reg [16:0] correct, incorrect;
//Initialize Arrays
initial $readmemh("MemP.txt", MemP.Memory);
initial $readmemh("sw_result.txt", Ref);
//Vector Procedure
initial begin
Rst_t <= 1'b1;
Rst_b <= 1'b1;
Rst_p <= 1'b0;
@(posedge Clk_s);
Rst_t <= 1'b0;
Rst_b <= 1'b0;
Go_s <= 1'b1;
@(posedge Clk_s);
Go_s <= 1'b0;
@(posedge Clk_s);
while (Done_s != 1'b1) @(posedge Clk_s);
correct <= 0;
incorrect <= 0;
@(posedge Clk_s);
for (Count = 0; Count < 76800; Count = Count + 1) begin
if (MemB.Memory[Count] == Ref[Count]) begin
$display("%d. memB : %d and is equal to sw_result: %d", Count, MemB.Memory[Count],
Ref[Count]);
correct <= correct + 1;
end else begin
$display("%d. FAIL!! memB : %d and is not equal to sw_result: %d", Count,
MemB.Memory[Count], Ref[Count]);
incorrect <= incorrect + 1;
end
@(posedge Clk_s);
end
$display("correct : %d, incorrect : %d", correct, incorrect);
$stop;
end
endmodule
| 6.709933 |
module Testbench ();
reg Go_s;
wire [(`A_WIDTH-1):0] P_Addr_s, B_Addr_s;
wire [(`D_WIDTH-1):0] P_Data_s, P_Di_s, B_Data_s;
wire [(`V_WIDTH-1):0] T_Out_s;
wire I_RW_s, I_En_s, O_RW_s, O_En_s, Done_s;
reg Clk_s, Rst_t, Rst_p, Rst_b;
parameter ClkPeriod = 20;
Tresholding CompToTest (
Go_s,
P_Addr_s,
P_Data_s,
B_Addr_s,
I_RW_s,
I_En_s,
O_RW_s,
O_En_s,
Done_s,
T_Out_s,
Clk_s,
Rst_t
);
Sram_Operand MemP (
P_Di_s,
P_Data_s,
P_Addr_s,
I_RW_s,
I_En_s,
Clk_s,
Rst_p
);
Sram_Operand MemB (
T_Out_s,
B_Data_s,
B_Addr_s,
O_RW_s,
O_En_s,
Clk_s,
Rst_b
);
// Clock Procedure
always begin
Clk_s <= 1'b0;
#(ClkPeriod / 2);
Clk_s <= 1'b1;
#(ClkPeriod / 2);
end
reg [(`D_WIDTH-1):0] Ref[0:(76800-1)];
reg [17:0] Count;
reg [16:0] correct, incorrect;
//Initialize Arrays
initial $readmemh("MemP.txt", MemP.Memory);
initial $readmemh("sw_result.txt", Ref);
//Vector Procedure
initial begin
Rst_t <= 1'b1;
Rst_b <= 1'b1;
Rst_p <= 1'b0;
@(posedge Clk_s);
Rst_t <= 1'b0;
Rst_b <= 1'b0;
Go_s <= 1'b1;
@(posedge Clk_s);
Go_s <= 1'b0;
@(posedge Clk_s);
while (Done_s != 1'b1) @(posedge Clk_s);
correct <= 0;
incorrect <= 0;
@(posedge Clk_s);
for (Count = 0; Count < 76800; Count = Count + 1) begin
if (MemB.Memory[Count] == Ref[Count]) begin
$display("%d. memB : %d and is equal to sw_result: %d", Count, MemB.Memory[Count],
Ref[Count]);
correct <= correct + 1;
end else begin
$display("%d. FAIL!! memB : %d and is not equal to sw_result: %d", Count,
MemB.Memory[Count], Ref[Count]);
incorrect <= incorrect + 1;
end
@(posedge Clk_s);
end
$display("correct : %d, incorrect : %d", correct, incorrect);
$stop;
end
endmodule
| 6.722871 |
module including Tresholding and Dual-Port SRAM
// ***********************************************************************
`timescale 1 ns/1 ns
`define A_WIDTH 17
`define D_WIDTH 8
module Thresholding_Top(Go_t, Done_t, Rst_Core,
MP_di31, MP_di8, MP_do31, MP_Addr15, MP_enb, MP_web, Rst_P,
MB_di8_2, MB_do8, MB_do8_2, MB_Addr17_2, MB_ena, MB_wea, Rst_B,
Clk);
//Thresholding_Core interface
input Go_t;
output Done_t;
input Rst_Core;
//Dual-port SRAM_P Interface
input [31:0] MP_di31;
input [7:0] MP_di8; //not used!
output [31:0] MP_do31; //not used!
input [14:0] MP_Addr15;
input MP_enb, MP_web;
input Rst_P;
//Dual-port SRAM_B Interface
input [7:0] MB_di8_2; //not used!
output [7:0] MB_do8, MB_do8_2; //do8: not used!
input [16:0] MB_Addr17_2;
input MB_ena, MB_wea;
input Rst_B;
//Interface between Thresholdingn_Core and Dual_port SRAM_P
wire [(`D_WIDTH-1):0] MP_do8;
wire [(`A_WIDTH-1):0] MP_Addr17;
wire MP_ena, MP_wea;
//Interface between Thresholdingn_Core and Dual_port SRAM_B
wire [(`D_WIDTH-1):0] MB_di8;
wire [(`A_WIDTH-1):0] MB_Addr17;
wire MB_enb, MB_web;
//Common Interface
input Clk;
Tresholding T_Core(Go_t, MP_Addr17, MP_do8, MB_Addr17, MP_wea, MP_ena, MB_web, MB_enb,
Done_t, MB_di8, Clk, Rst_Core);
dp_sram_coregen_p MemP(
MP_Addr17,//addra,
MP_Addr15,//addrb,
Clk,//clka,
Clk,//clkb,
MP_di8,//dina,
MP_di31,//dinb,
MP_do8,//douta,
MP_do31,//doutb,
MP_ena,//ena,
MP_enb,//enb,
Rst_P,//sinita,
Rst_P,//sinitb,
MP_wea,//wea,
MP_web);//web);
dp_sram_coregen_b MemB(
MB_Addr17_2,//addra,
MB_Addr17,//addrb,
Clk,//clka,
Clk,//clkb,
MB_di8_2,//dina,
MB_di8,//dinb,
MB_do8_2,//douta,
MB_do8,//doutb,
MB_ena,//ena,
MB_enb,//enb,
Rst_B,//sinita,
Rst_B,//sinitb,
MB_wea,//wea,
MB_web);//web);
endmodule
| 6.855655 |
module ThresholdUnit #(
parameter INTEGER_WIDTH = 16,
parameter DATA_WIDTH_FRAC = 32,
parameter DATA_WIDTH = INTEGER_WIDTH + DATA_WIDTH_FRAC
) (
input wire signed [(DATA_WIDTH-1):0] Vth,
input wire signed [(DATA_WIDTH-1):0] Vmem,
input wire signed [(INTEGER_WIDTH-1):0] Vreset,
output wire signed [(DATA_WIDTH-1):0] VmemOut,
output wire SpikeOut
);
//Intermediate Values:
wire signed [(DATA_WIDTH-1):0] Vreset_Extended;
//Wire Select and/or padding for Fixed-point Arithmetic
assign Vreset_Extended = {Vreset, {DATA_WIDTH_FRAC{1'b0}}}; //pad fractional bits
//Combinational Computation
assign SpikeOut = (Vmem >= Vth) ? 1'b1 : 1'b0;
assign VmemOut = (Vmem >= Vth) ? Vreset_Extended : Vmem;
endmodule
| 6.557893 |
module threshold_17x17 (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [12:0] iPosition,
input [31:0] iMax_val,
input iFinish,
input [31:0] iData_from_OM,
//Output
output reg [12:0] oAddr_OM,
output reg [12:0] oPosition,
output reg oOutput_ready,
output reg oEnd
);
//=========================REGISTERS================================
reg [1:0] state;
reg [12:0] position;
//===========================WIRES==================================
wire threshold;
wire [12:0] face_center;
wire cond;
//==================================================================
assign threshold = iMax_val > 32'h4E66666;
assign face_center = iPosition + 13'd162;
assign cond = iData_from_OM > 32'h11EB85;
//==================================================================
always @(posedge iClk)
if (~iReset_n || iFinish) begin
state <= 2'b0;
position <= 13'b0;
oAddr_OM <= 13'b0;
oPosition <= 13'b0;
oOutput_ready <= 1'b0;
oEnd <= 1'b0;
end else begin
case (state)
0:
if (iInput_ready) begin
if (threshold) begin
state <= 2'd1;
oAddr_OM <= face_center;
position <= iPosition;
oEnd <= 1'b0;
end else begin
oPosition <= 13'b0;
oOutput_ready <= 1'b0;
oEnd <= 1'b1;
end
end else oOutput_ready <= 1'b0;
1: begin
oAddr_OM <= oAddr_OM + 1'b1;
state <= 2'd2;
end
2:
if (cond) begin
oPosition <= position;
oOutput_ready <= 1'b1;
state <= 3'd0;
end else state <= 2'd3;
3: begin
if (cond) oPosition <= position + 1'b1;
else oPosition <= position + 13'd81;
oOutput_ready <= 1'b1;
state <= 2'd0;
end
endcase
end
endmodule
| 7.365664 |
module threshold_19x19 (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [12:0] iPosition,
input [31:0] iMax_val,
input iFinish,
input [31:0] iData_from_OM,
//Output
output reg [12:0] oAddr_OM,
output reg [12:0] oPosition,
output reg oOutput_ready,
output reg oEnd
);
//=========================REGISTERS================================
reg [1:0] state;
reg [12:0] position;
//===========================WIRES==================================
wire threshold;
wire [12:0] face_center;
wire cond;
//==================================================================
assign threshold = iMax_val > 32'h4199999;
assign face_center = iPosition + 13'd162;
assign cond = iData_from_OM > 32'h11EB85;
//==================================================================
always @(posedge iClk)
if (~iReset_n || iFinish) begin
state <= 2'b0;
position <= 13'b0;
oAddr_OM <= 13'b0;
oPosition <= 13'b0;
oOutput_ready <= 1'b0;
oEnd <= 1'b0;
end else begin
case (state)
0:
if (iInput_ready) begin
if (threshold) begin
state <= 2'd1;
oAddr_OM <= face_center;
position <= iPosition;
oEnd <= 1'b0;
end else begin
oPosition <= 13'b0;
oOutput_ready <= 1'b0;
oEnd <= 1'b1;
end
end else oOutput_ready <= 1'b0;
1: begin
oAddr_OM <= oAddr_OM + 1'b1;
state <= 2'd2;
end
2:
if (cond) begin
oPosition <= position;
oOutput_ready <= 1'b1;
state <= 3'd0;
end else state <= 2'd3;
3: begin
if (cond) oPosition <= position + 1'b1;
else oPosition <= position + 13'd81;
oOutput_ready <= 1'b1;
state <= 2'd0;
end
endcase
end
endmodule
| 7.23229 |
module threshold_23x23 (
//Input
input iClk,
input iReset_n,
input iInput_ready,
input [12:0] iPosition,
input [31:0] iMax_val,
input iFinish,
input [31:0] iData_from_OM,
//Output
output reg [12:0] oAddr_OM,
output reg [12:0] oPosition,
output reg oOutput_ready,
output reg oEnd
);
//=========================REGISTERS================================
reg [1:0] state;
reg [12:0] position;
//===========================WIRES==================================
wire threshold;
wire [12:0] face_center;
wire cond;
//==================================================================
assign threshold = iMax_val > 32'h4199999;
assign face_center = iPosition + 13'd162;
assign cond = iData_from_OM > 32'h11EB85;
//==================================================================
always @(posedge iClk)
if (~iReset_n || iFinish) begin
state <= 2'b0;
position <= 13'b0;
oAddr_OM <= 13'b0;
oPosition <= 13'b0;
oOutput_ready <= 1'b0;
oEnd <= 1'b0;
end else begin
case (state)
0:
if (iInput_ready) begin
if (threshold) begin
state <= 2'd1;
oAddr_OM <= face_center;
position <= iPosition;
oEnd <= 1'b0;
end else begin
oPosition <= 13'b0;
oOutput_ready <= 1'b0;
oEnd <= 1'b1;
end
end else oOutput_ready <= 1'b0;
1: begin
oAddr_OM <= oAddr_OM + 1'b1;
state <= 2'd2;
end
2:
if (cond) begin
oPosition <= position;
oOutput_ready <= 1'b1;
state <= 3'd0;
end else state <= 2'd3;
3: begin
if (cond) oPosition <= position + 1'b1;
else oPosition <= position + 13'd81;
oOutput_ready <= 1'b1;
state <= 2'd0;
end
endcase
end
endmodule
| 7.302283 |
module Threshold_Adj (
//global clock
input clk, //100MHz
input rst_n, //global reset
//user interface
input key_flag, //key down flag
input [1:0] key_value, //key control data
output reg [7:0] Threshold //Threshold Grade output
);
reg [3:0] Threshold_Grade;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Threshold_Grade <= 8'h9;
else if (key_flag) begin
case (key_value)
2'b01: Threshold_Grade <= (Threshold_Grade == 0) ? 8'b0 : Threshold_Grade - 1'b1;
2'b10: Threshold_Grade <= (Threshold_Grade == 15) ? 8'hf : Threshold_Grade + 1'b1;
default: ;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) Threshold <= 8'd100;
else begin
case (Threshold_Grade)
4'h0: Threshold <= 8'd10;
4'h1: Threshold <= 8'd20;
4'h2: Threshold <= 8'd30;
4'h3: Threshold <= 8'd40;
4'h4: Threshold <= 8'd50;
4'h5: Threshold <= 8'd60;
4'h6: Threshold <= 8'd70;
4'h7: Threshold <= 8'd80;
4'h8: Threshold <= 8'd90;
4'h9: Threshold <= 8'd100;
4'ha: Threshold <= 8'd110;
4'hb: Threshold <= 8'd120;
4'hc: Threshold <= 8'd130;
4'hd: Threshold <= 8'd140;
4'he: Threshold <= 8'd150;
4'hf: Threshold <= 8'd160;
default: ;
endcase
end
end
endmodule
| 6.532472 |
module Threshold_Binarization (
input CLK100MHZ, //input clock
input [7:0] next_px, //input px
input btn_reset, //reset line
input ena, //reset line
output [7:0] output_px //output px (255 represents 1 and 0 represents 0)
);
parameter [7:0] THRESHOLD = 8'd78; //threshold value
assign output_px = ((next_px > THRESHOLD) && ena ? 255 : 0);
endmodule
| 6.809804 |
module threshold_binary_0 #(
parameter DW = 24,
parameter Y_TH = 225,
parameter Y_TL = 60,
parameter CB_TH = 141,
parameter CB_TL = 111,
parameter CR_TH = 139,
parameter CR_TL = 98
) (
input pixelclk,
input reset_n,
input [DW-1:0] i_ycbcr,
input [DW-1:0] i_rgb,
input i_hsync,
input i_vsync,
input i_de,
// output [DW-1:0] o_binary ,
output [DW-1:0] o_rgb,
output o_hsync,
output o_vsync,
output x0,
output reg en,
output o_de
);
reg [DW-1:0] binary_r;
reg [DW-1:0] i_rgb_r;
reg h_sync_r;
reg v_sync_r;
reg de_r;
wire en0;
wire en1;
wire en2;
//assign o_binary = binary_r;
assign o_rgb = i_rgb_r;
assign o_hsync = h_sync_r;
assign o_vsync = v_sync_r;
assign o_de = de_r;
////////////////////// threshold//////////////////////////////////////
assign en0 = i_ycbcr[23:16] >= Y_TL && i_ycbcr[23:16] <= Y_TH;
assign en1 = i_ycbcr[15:8] >= CB_TL && i_ycbcr[15:8] <= CB_TH;
assign en2 = i_ycbcr[7:0] >= CR_TL && i_ycbcr[7:0] <= CR_TH;
/********************************************************************************************/
/***************************************timing***********************************************/
always @(posedge pixelclk) begin
h_sync_r<= i_hsync;
v_sync_r<= i_vsync;
de_r <= i_de;
i_rgb_r <= i_rgb;
end
/********************************************************************************************/
/***************************************Binarization threshold*******************************/
always @(posedge pixelclk or negedge reset_n) begin
if (!reset_n) begin
binary_r <= 24'd15;
en <= 1'b0;
end else begin
if (en0 == 1'b1 && en1 == 1'b1 && en2 == 1'b1) begin
binary_r <= 24'h0;
en <= 1'b1;
end else begin
binary_r <= 24'h15;
en <= 1'b1;
end
end
end
assign x0 = (binary_r == 24'h0) ? 1'b0 : 1'b1;
endmodule
| 6.665487 |
module threshold_dac #(
parameter signalwidth = 16
) (
input clk,
input reset_n,
input [signalwidth-1:0] d,
output q
);
reg q_reg;
assign q = q_reg;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
q_reg <= 1'b0;
end else begin
q_reg <= d[signalwidth-1];
end
end
endmodule
| 6.772579 |
module threshold_detect (
input clk,
input rst,
input [12:0] length,
output reg [11:0] result
);
parameter threshold = 140;
always @(posedge clk) begin
if (rst) result <= 0;
else result <= (length >= threshold ? {12{1'b1}} : 0);
end
endmodule
| 6.576015 |
module threshold_scaled #(
parameter WIDTH = 32,
SCALAR = 131072
) (
input clk,
input reset,
input clear,
input [WIDTH-1:0] i0_tdata,
input i0_tlast,
input i0_tvalid,
output i0_tready,
input [WIDTH-1:0] i1_tdata,
input i1_tlast,
input i1_tvalid,
output i1_tready,
output o_tdata,
output o_tlast,
output o_tvalid,
input o_tready
);
wire signed [WIDTH-1:0] scaled_input;
wire signed [WIDTH-1:0] difference;
wire signed thresh_met;
assign scaled_input = (i1_tdata - 1) * SCALAR;
assign difference = scaled_input - i0_tdata;
assign thresh_met = difference > 0;
assign o_tdata = thresh_met;
assign o_tlast = i0_tlast;
wire do_op = o_tready & i0_tvalid & i1_tvalid;
assign o_tvalid = do_op;
assign i0_tready = do_op;
assign i1_tready = do_op;
endmodule
| 8.051676 |
module thunder_ams_analog (
hf_osc_out,
iledir_out,
lf_osc_out,
vgnda,
vsupa,
hf_on,
hf_trim,
iledir_on,
iledir_trim,
lf_on,
lf_trim,
ref_on,
hf_therm_trim,
lf_therm_trim,
hf_trim_msb,
lf_trim_msb
);
output hf_osc_out;
input ref_on;
input [3:0] lf_trim;
input [14:0] lf_therm_trim;
input lf_trim_msb;
input iledir_on;
input [3:0] hf_trim;
input [14:0] hf_therm_trim;
input hf_trim_msb;
output lf_osc_out;
output iledir_out;
inout vsupa;
input lf_on;
input hf_on;
inout vgnda;
input [7:0] iledir_trim;
parameter real lf_base = 3125; //6.25us (div16) for 160khz tt
parameter real hf_base = 10; //20ns
reg lf_osc_out = 1'b0;
reg hf_osc_out = 1'b0;
real fast_delay = 10; //20ns
real slow_delay = 3125; //6.25us (div16) for 160khz tt
real iled_val = 40; //40u default
real lf_lsb = 12.5; //0.2%
real hf_lsb = 0.04; //0.2%
real max_fast_delay = 26;
real max_slow_delay = 7812;
wire [8:0] effective_lf_trim;
wire [8:0] effective_hf_trim;
reg [3:0] lf_therm_bin;
reg [3:0] hf_therm_bin;
wire [8:0] combined_lf_trim;
wire [8:0] combined_hf_trim;
assign combined_lf_trim = {lf_trim_msb, lf_therm_bin, lf_trim[3:0]};
assign combined_hf_trim = {hf_trim_msb, hf_therm_bin, hf_trim[3:0]};
assign effective_lf_trim = combined_lf_trim;
assign effective_hf_trim = combined_hf_trim;
initial begin
lf_osc_out = 0;
hf_osc_out = 0;
end
//Therm2bin for therm_trims
//lf
always @(*) begin
case (lf_therm_trim)
15'h0000: lf_therm_bin = 4'h0;
15'h0001: lf_therm_bin = 4'h1;
15'h0003: lf_therm_bin = 4'h2;
15'h0007: lf_therm_bin = 4'h3;
15'h000f: lf_therm_bin = 4'h4;
15'h001f: lf_therm_bin = 4'h5;
15'h003f: lf_therm_bin = 4'h6;
15'h007f: lf_therm_bin = 4'h7;
15'h00ff: lf_therm_bin = 4'h8;
15'h01ff: lf_therm_bin = 4'h9;
15'h03ff: lf_therm_bin = 4'ha;
15'h07ff: lf_therm_bin = 4'hb;
15'h0fff: lf_therm_bin = 4'hc;
15'h1fff: lf_therm_bin = 4'hd;
15'h3fff: lf_therm_bin = 4'he;
15'h7fff: lf_therm_bin = 4'hf;
default: lf_therm_bin = 4'h0;
endcase
end
//hf
always @(*) begin
case (hf_therm_trim)
15'h0000: hf_therm_bin = 4'h0;
15'h0001: hf_therm_bin = 4'h1;
15'h0003: hf_therm_bin = 4'h2;
15'h0007: hf_therm_bin = 4'h3;
15'h000f: hf_therm_bin = 4'h4;
15'h001f: hf_therm_bin = 4'h5;
15'h003f: hf_therm_bin = 4'h6;
15'h007f: hf_therm_bin = 4'h7;
15'h00ff: hf_therm_bin = 4'h8;
15'h01ff: hf_therm_bin = 4'h9;
15'h03ff: hf_therm_bin = 4'ha;
15'h07ff: hf_therm_bin = 4'hb;
15'h0fff: hf_therm_bin = 4'hc;
15'h1fff: hf_therm_bin = 4'hd;
15'h3fff: hf_therm_bin = 4'he;
15'h7fff: hf_therm_bin = 4'hf;
default: hf_therm_bin = 'h0;
endcase
end
always @(*) begin
//osc delay based on trim
slow_delay = max_slow_delay - effective_lf_trim * lf_lsb;
fast_delay = max_fast_delay - effective_hf_trim * hf_lsb;
end
//LF osc
always #slow_delay lf_osc_out = !lf_osc_out && lf_on && ref_on;
//LF osc
always #fast_delay hf_osc_out = !hf_osc_out && hf_on && ref_on;
//Iledir No rnm, so no trim checks
assign iledir_out = (iledir_on && ref_on) ? 1'b0 : 1'bz;
endmodule
| 7.492537 |
module thymesisflow_llc_ingress_driver (
input clock // Clock - samples & launches data on rising edge
, input reset_n // Active Low
// 32B incoming data Interface
, input [255:0] driver_in_tdata
, input driver_in_tvalid
, output driver_in_tready
// 32B AXI-STREAM
, output [255:0] driver_out_tdata
, output driver_out_tvalid
, input driver_out_tready
);
reg [255:0] outdata_q;
reg outdata_vld;
assign driver_out_tdata = outdata_q;
assign driver_out_tvalid = outdata_vld;
//Encoding of the various flit cases based on OpenCAPI TL/TLx protocol
reg [1:0] ocapi_sm;
parameter CMDFLIT = 2'b01;
parameter DATAFLIT = 2'b10;
wire is_cmd;
assign is_cmd = ocapi_sm[0];
wire is_data;
assign is_data = ocapi_sm[1];
wire [1:0] cmd_dl;
assign cmd_dl = driver_in_tdata[167:166]; //according to the mapping
wire [1:0] resp_dl;
assign resp_dl = driver_in_tdata[227:226];
//Check command types
wire is_writecmd;
assign is_writecmd = driver_in_tdata[253];
wire is_readcmd;
assign is_readcmd = driver_in_tdata[252];
wire is_nopcmd;
assign is_nopcmd = ((driver_in_tdata[254] == 1'b1) && (driver_in_tdata[249] == 1'b0));
wire is_respRok;
assign is_respRok = ((driver_in_tdata[250] == 1'b1) && (driver_in_tdata[248] == 1'b0));
wire is_respWok;
assign is_respWok = ((driver_in_tdata[251] == 1'b1) && (driver_in_tdata[248] == 1'b0));
//we eat up nop cmds here so the other side does not have to be ready to process those. -- this is interfaced to aurora parser so it needs to be always ready
assign driver_in_tready = (driver_out_tready == 1'b1) || ((is_nopcmd == 1'b1) && (is_cmd == 1'b1) && (driver_in_tvalid == 1'b1));
reg [2:0] dflit_size;
always @(posedge (clock)) begin
if (reset_n == 1'b0) begin
dflit_size <= 3'b0;
ocapi_sm <= CMDFLIT;
end else
case (ocapi_sm)
CMDFLIT: begin
if ((driver_out_tready == 1'b1) && (driver_in_tvalid == 1'b1) &&
((is_writecmd == 1'b1) || (is_respRok == 1'b1))) //Commands with dataflits
begin
ocapi_sm <= DATAFLIT;
dflit_size <= 3'b100;
end
end
DATAFLIT: begin
if ((driver_out_tready == 1'b1) && (driver_in_tvalid == 1'b1) && (dflit_size != 3'b001)) //Commands with dataflits
dflit_size <= dflit_size - 3'b001;
else if ((driver_out_tready == 1'b1) && (driver_in_tvalid == 1'b1)) ocapi_sm <= CMDFLIT;
end
endcase
end
//Data and command
always @(posedge(clock))
begin //this is the first network Rx moduls so make sure only allowed commands get through.
if (reset_n == 1'b0) begin
outdata_q <= 256'b0;
outdata_vld <= 1'b0;
end
else if ((is_cmd == 1'b1) && (driver_in_tvalid == 1'b1) && (driver_out_tready == 1'b1) && (is_nopcmd == 1'b0)) //Cmd flit out
begin
outdata_q <= driver_in_tdata;
outdata_vld <= 1'b1;
end
else if ((is_data == 1'b1) && (driver_in_tvalid == 1'b1) && (driver_out_tready == 1'b1)) //Data flit out
begin
outdata_q <= driver_in_tdata;
outdata_vld <= 1'b1;
end else if (driver_out_tready == 1'b1) begin
outdata_q <= 256'b0;
outdata_vld <= 1'b0;
end
end
endmodule
| 7.072743 |
module thymesisflow_rr_arbiter #(
parameter SIZE = 2
) (
input clock // Clock - samples & launches data on rising edge
, input reset_n // Active Low
// fifo_in AXI-STREAM
, input [SIZE-1:0] request_vector
, input request_nxt
, output [SIZE-1:0] selected
);
reg [SIZE-1:0] masked_req_vector; //snapshot of the request input.
//masked req vector
always @(posedge (clock)) begin
if (reset_n == 1'b0) //Reset active
begin
masked_req_vector <= 2'b0;
end
else if ((request_nxt == 1'b1) && (masked_req_vector == 2'b0)) //active
begin
masked_req_vector <= (request_vector ^ selected) & request_vector; //empty mask means no history or rollover - so we just remove previous selection.
end else if ((request_nxt == 1'b1)) begin
masked_req_vector <= (masked_req_vector ^ selected) & request_vector; //
end
end
//Combinational to return selection immediately
assign selected = (masked_req_vector == 2'b0) ? request_vector & (~request_vector + 1) : masked_req_vector & (~masked_req_vector + 1);
endmodule
| 7.072743 |
module: dflop
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_dflop;
// Inputs
reg rst;
reg clk;
reg din;
// Outputs
wire qout;
wire qbout;
// Instantiate the Unit Under Test (UUT)
dflop uut (
.rst(rst),
.clk(clk),
.din(din),
.qout(qout),
.qbout(qbout)
);
initial begin
// Initialize Inputs
rst = 1'b0;
clk = 1'b0;
#40;
din = 1'b0;
#40;
clk = ~clk;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#5;
clk = ~clk;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#5;
clk = ~clk;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b0;
rst = 1'b1;
#5;
clk = ~clk;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#15;
din = 1'b0;
#15;
din = 1'b1;
#5;
$finish;
// Add stimulus here
end
endmodule
| 7.473416 |
module
// Checks the pixel number against a stretched and possibly duplicated version of the
// object.
module objPixelOn(pixelNum, objPos, objSize, objMask, pixelOn);
input [7:0] pixelNum, objPos, objMask;
input [2:0] objSize;
output pixelOn;
wire [7:0] objIndex;
wire [8:0] objByteIndex;
wire objMaskOn, objPosOn;
reg objSizeOn;
reg [2:0] objMaskSel;
assign objIndex = pixelNum - objPos - 8'd1;
assign objByteIndex = 9'b1 << (objIndex[7:3]);
always @(objSize, objByteIndex)
begin
case (objSize)
3'd0: objSizeOn <= (objByteIndex & 9'b00000001) != 0;
3'd1: objSizeOn <= (objByteIndex & 9'b00000101) != 0; // NS 2 copies - close (8)
3'd2: objSizeOn <= (objByteIndex & 9'b00010001) != 0;
3'd3: objSizeOn <= (objByteIndex & 9'b00010101) != 0;
3'd4: objSizeOn <= (objByteIndex & 9'b10000001) != 0;
3'd5: objSizeOn <= (objByteIndex & 9'b00000011) != 0;
3'd6: objSizeOn <= (objByteIndex & /*9'b10010001*/9'b100010001) != 0; // NS 02-02-17
3'd7: objSizeOn <= (objByteIndex & 9'b00001111) != 0;
endcase
end // end always
always @(objSize, objIndex)
begin
case (objSize)
3'd5: objMaskSel <= objIndex[3:1];
3'd7: objMaskSel <= objIndex[4:2];
default: objMaskSel <= objIndex[2:0];
endcase
end // end always
assign objMaskOn = objMask[objMaskSel];
assign objPosOn = (pixelNum > objPos) && ({1'b0, pixelNum} <= {1'b0, objPos} + 9'd72);
assign pixelOn = objSizeOn && objMaskOn && objPosOn;
endmodule
| 6.774774 |
module
// Checks the pixel number against a stretched and possibly duplicated version of the
// object. See below for detailed functionality...
module objPlayersPixelOn(pixelNum, objPos, objSize, objMask, plReset, pixelOn);
input [7:0] pixelNum, objPos, objMask;
input [2:0] objSize;
input plReset;
output pixelOn;
wire [7:0] objIndex;
wire [8:0] objByteIndex;
wire objMaskOn, objPosOn;
reg objSizeOn;
reg [2:0] objMaskSel;
assign objIndex = pixelNum - objPos - 8'd1;
assign objByteIndex = 9'b1 << (objIndex[7:3]);
always @(objSize, objByteIndex)
begin
case (objSize)
3'd0: objSizeOn <= (objByteIndex & 9'b00000001 & ~plReset) != 0;
// NS 2 copies - close (8)
3'd1: objSizeOn <= (plReset) ? ((objByteIndex & 9'b00000100) != 0) : ((objByteIndex & 9'b0000101) != 0);
3'd2: objSizeOn <= (plReset) ? ((objByteIndex & 9'b00010000) != 0) : ((objByteIndex & 9'b00010001) != 0);
3'd3: objSizeOn <= (plReset) ? ((objByteIndex & 9'b00010100) != 0) : ((objByteIndex & 9'b00010101) != 0);
3'd4: objSizeOn <= (objByteIndex & 9'b10000001 & ~plReset) != 0;
3'd5: objSizeOn <= (objByteIndex & 9'b00000011 & ~plReset) != 0;
3'd6: objSizeOn <= (plReset) ? ((objByteIndex & /*9'b10010001*/9'b100010000) != 0) : ((objByteIndex & /*9'b10010001*/9'b100010001) != 0);
3'd7: objSizeOn <= (objByteIndex & 9'b00001111 & ~plReset) != 0;
endcase
end // end always
always @(objSize, objIndex)
begin
case (objSize)
3'd5: objMaskSel <= objIndex[3:1];
3'd7: objMaskSel <= objIndex[4:2];
default: objMaskSel <= objIndex[2:0];
endcase
end // end always
assign objMaskOn = objMask[objMaskSel];
assign objPosOn = (pixelNum > objPos) && ({1'b0, pixelNum} <= {1'b0, objPos} + 9'd72);
assign pixelOn = objSizeOn && objMaskOn && objPosOn;
endmodule
| 6.774774 |
module TickCounter #(
parameter CW = 24
) // internal counter width
(
// External time interface(also associated with the external input/output port)
output TICK_OUT,
input TICK_IN,
output [CW-1:0] COUNT,
output [ 5:1] time_o,
output [ 1:0] ctrl_flg_o,
input [ 5:1] time_i,
input [ 1:0] ctrl_flg_i,
// interconnect
output [ ] TimeReg_o,
input [PORTNUM-1:0] IFtick_i, // Interface ports tick_out internal
// global signal input
input reset,
input gclk
);
reg [] TimeReg; // "time register"
reg [CW-1:0] tcnt; // "internal time counter"
assign TimeReg_o = TimeReg;
///////////////////////
// tcnt(timer counter)
//
wire run_tcnt = |(IFtick_i[i]) || tick_in;
always @(posedge gclk) begin
if (reset == `reset) tcnt <= 0;
else if (run_tcnt) tcnt <= tcnt + 1;
end
endmodule
| 6.870199 |
module ticker (
input wire clk_bus,
input wire rst_n,
input wire clk_tick, //10MHz clock in
input wire rst_tick_n,
//bus
output wire [31:0] bus_data_o,
input wire [ 7:0] bus_address,
input wire [31:0] bus_data_i,
input wire bus_read,
input wire bus_write
);
reg [31:0] ticker;
reg [31:0] ticker_d1;
reg [31:0] ticker_d2;
reg [13:0] prescaler;
assign bus_data_o = bus_read ? ticker_d2 : 32'd0;
always @(posedge clk_bus or negedge rst_n) begin
if (!rst_n) begin
ticker_d1 <= 32'd0;
end else begin
ticker_d1 <= ticker;
end
end
always @(posedge clk_bus or negedge rst_n) begin
if (!rst_n) begin
ticker_d2 <= 32'd0;
end else begin
ticker_d2 <= ticker_d1;
end
end
always @(posedge clk_tick or negedge rst_tick_n) begin
if (!rst_tick_n) begin
ticker <= 32'd0;
prescaler <= 14'd0;
end else begin
prescaler <= (prescaler < 14'd9999) ? prescaler + 1'b1 : 14'd0;
ticker <= ticker + (prescaler == 14'd9999); //ticker frequency is 1KHz
end
end
endmodule
| 7.411879 |
module TestBench;
reg Clock, Clear, Ten, Twenty;
wire Ready, Dispense, Return, Bill;
parameter TRUE = 1'b1;
parameter FALSE = 1'b0;
parameter CLOCK_CYCLE = 10;
parameter CLOCK_WIDTH = CLOCK_CYCLE / 2;
parameter IDLE_CLOCKS = 2;
// instantiate an object of type TicketMachine to test
TicketMachine TFSM (
Clock,
Clear,
Ten,
Twenty,
Ready,
Dispense,
Return,
Bill
);
//
// set up monitor
//
initial begin
forever
@(posedge Clock) begin
#1
$display(
$time,
" %b %b %b %b %b %b",
Ten,
Twenty,
Ready,
Dispense,
Return,
Bill
);
end
end
//
// Create free running clock
//
initial begin
Clock = FALSE;
forever #CLOCK_WIDTH Clock = ~Clock;
end
//
// Generate stimulus after waiting for reset
//
initial begin
Clear = 1;
repeat (2) @(negedge Clock);
Clear = 0;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // case #1
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // exact change with 10+10+10+10
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01; // case #2
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01; // exact change with 20+20
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // case #3
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // exact change with 10+10+20
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // case #4
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01; // exact change with 10+20+10
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01; // case #5
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // exact change with 20+10+10
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // case #6
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01; // overshoot with 10+20+20
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // case #7
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01; // overshoot with 10+20+20
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01; // case #8
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // overshoot with 20+10+20
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // case #9
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10; // overshoot with 10+10+10+20
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b10;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b01;
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b00; // case #10 - explicit no bills
repeat (1) @(negedge Clock);
{Ten, Twenty} = 2'b11; // case #11 - LUDICROUS CASE
// failure in laws of physics
$stop;
end
endmodule
| 6.639035 |
module BaudTickGen (
input clk,
enable,
output tick
);
parameter ClkFrequency = 50000000; // 50 MHz
parameter Baud = 9600;
parameter Oversampling = 1;
function integer log2(input integer v);
begin
log2 = 0;
while (v >> log2) log2 = log2 + 1;
end
endfunction
localparam AccWidth = log2(ClkFrequency / Baud) + 8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(
Baud * Oversampling >> (31 - AccWidth)
); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk)
if (enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
| 7.463142 |
module tick_gen (
input clk,
input reset_n,
input [2:0] state,
input [2:0] grid_state,
input input_buffer_empty,
input forward_north_local_buffer_empty_all,
input complete,
output tick
);
localparam [1:0] IDLE = 2'b00, TICK1 = 2'b01, TICK2 = 2'b10;
reg [2:0] cnt_reg, cnt_next;
reg [31:0] cnt2_reg, cnt2_next;
reg tick_reg, tick_next;
reg [1:0] state_tick_reg, state_tick_next;
always @(posedge clk) begin
if (!reset_n) begin
tick_reg <= 0;
cnt_reg <= 0;
cnt2_reg <= 0;
state_tick_reg <= IDLE;
end else begin
tick_reg <= tick_next;
cnt_reg <= cnt_next;
cnt2_reg <= cnt2_next;
state_tick_reg <= state_tick_next;
end
end
always @(*) begin
tick_next = 1'b0;
cnt_next = cnt_reg;
cnt2_next = cnt2_reg;
case (state_tick_reg)
IDLE: begin
if (!input_buffer_empty) state_tick_next = TICK1;
else state_tick_next = IDLE;
end
TICK1: begin
if (input_buffer_empty && grid_state == 0) begin
if (cnt_reg == 7) begin
tick_next = 1;
cnt_next = 0;
end else if (forward_north_local_buffer_empty_all) begin
cnt_next <= cnt_reg + 1'b1;
end else if (!forward_north_local_buffer_empty_all) begin
cnt_next <= cnt_reg - 1'b1;
end
end
if (state == 3'b100) begin
state_tick_next = TICK2;
end else state_tick_next = TICK1;
end
TICK2: begin
if (complete) state_tick_next = IDLE;
else begin
state_tick_next = TICK2;
if (cnt2_reg == 32'h3ec) begin
tick_next = 1'b1;
cnt2_next = 0;
end else cnt2_next = cnt2_reg + 1'b1;
end
end
endcase
end
assign tick = tick_reg;
endmodule
| 7.877713 |
module stimulus();
// reg CLK,RESET;
// wire TICK;
// tick_generator #(.tick_time(32'd5),.frequency(32'd1))
// t1(
// .clk(CLK),
// .tick(TICK),
// .reset(RESET)
// );
// initial begin
// $dumpfile("simulation.vcd");
// $dumpvars(0,
// CLK,
// TICK,
// RESET
// );
// end
// initial begin
// CLK = 1'b0;
// RESET = 1'b0;
// end
// always
// #1 CLK = ~ CLK;
// initial begin
// #20 RESET = 1'b1;
// #10 RESET = 1'b0;
// end
// initial
// #100 $finish;
// endmodule
| 6.85176 |
module: TicTacToe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tictactoe_test;
// Inputs
reg clk;
reg upButton;
reg downButton;
reg leftButton;
reg rightButton;
reg centerButton;
reg resetButton;
reg vgaReset;
// Outputs
wire [2:0] R;
wire [2:0] G;
wire [1:0] B;
wire HS;
wire VS;
wire [6:0] hex;
wire [3:0] AN;
// Instantiate the Unit Under Test (UUT)
TicTacToe uut (
.clk(clk),
.upButton(upButton),
.downButton(downButton),
.leftButton(leftButton),
.rightButton(rightButton),
.centerButton(centerButton),
.resetButton(resetButton),
.vgaReset(vgaReset),
.R(R),
.G(G),
.B(B),
.HS(HS),
.VS(VS),
.hex(hex),
.AN(AN)
);
initial begin
// Initialize Inputs
clk = 0;
upButton = 0;
downButton = 0;
leftButton = 0;
rightButton = 0;
centerButton = 0;
resetButton = 0;
vgaReset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10 resetButton = 1;
#10 resetButton = 0;
#100
#10 centerButton = 1;
#50 centerButton = 0;
#50 centerButton = 1;
#50 centerButton = 0;
end
always
#10 clk = ~clk;
endmodule
| 7.700046 |
module TicTacToe_to_VGA (
input [8:0] x_positions,
o_positions,
next_position,
input [7:0] win_line,
input reset,
CLOCK_50,
output VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK,
VGA_SYNC,
output [7:0] VGA_R,
VGA_G,
VGA_B
);
wire raster_valid, shader_ready, shader_valid, fb_ready;
wire [9:0] coor_x, coor_y;
wire [31:0] shader_pixel_rgba, shader_pixel_addr;
rasterizer RASTER (
.clk(CLOCK_50),
.reset(reset),
.shader_ready(shader_ready),
.raster_valid(raster_valid),
.x(coor_x),
.y(coor_y)
);
tictactoe_shader SHADER (
.clk(CLOCK_50),
.reset(reset),
.coor_x(coor_x),
.coor_y(coor_y),
.x_pos(x_positions),
.o_pos(o_positions),
.next_position(next_position),
.win(win_line),
.fb_ready(fb_ready),
.shader_pixel_rgba(shader_pixel_rgba),
.shader_pixel_addr(shader_pixel_addr),
.shader_ready(shader_ready),
.raster_valid(raster_valid),
.shader_valid(shader_valid)
);
framebuffer FB (
.shader_valid(shader_valid),
.fb_ready(fb_ready),
.shader_pixel_rgba(shader_pixel_rgba),
.shader_pixel_addr(shader_pixel_addr),
.reset(reset),
.CLOCK_50(CLOCK_50),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK),
.VGA_SYNC(VGA_SYNC),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
endmodule
| 6.536328 |
module
module tictactoe(
input clock, // clock of the game
input reset, // reset button to reset the game
input play, // play button to enable player to play
input pc, // pc button to enable computer to play
input [3:0] computer_position,player_position,
// positions to play
output wire [1:0] pos1,pos2,pos3,
pos4,pos5,pos6,pos7,pos8,pos9,
// LED display for positions
// 01: Player
// 10: Computer
output wire[1:0]who
// who the winner is
);
wire [15:0] PC_en;// Computer enable signals
wire [15:0] PL_en; // Player enable signals
wire illegal_move; // disable writing when an illegal move is detected
//wire [1:0] pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9;// positions stored
wire win; // win signal
wire computer_play; // computer enabling signal
wire player_play; // player enabling signal
wire no_space; // no space signal
// position registers
position_registers position_reg_unit(
clock, // clock of the game
reset, // reset the game
illegal_move, // disable writing when an illegal move is detected
PC_en[8:0], // Computer enable signals
PL_en[8:0], // Player enable signals
pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9// positions stored
);
// winner detector
winner_detector win_detect_unit(pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,win,who);
// position decoder for computer
position_decoder pd1(computer_position,computer_play,PC_en);
// position decoder for player
position_decoder pd2(player_position,player_play,PL_en);
// illegal move detector
illegal_move_detector imd_unit(
pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,
PC_en[8:0], PL_en[8:0],
illegal_move
);
// no space detector
nospace_detector nsd_unit(
pos1,pos2,pos3,pos4,pos5,pos6,pos7,pos8,pos9,
no_space
);
fsm_controller tic_tac_toe_controller(
clock,// clock of the circuit
reset,// reset
play, // player plays
pc,// computer plays
illegal_move,// illegal move detected
no_space, // no_space detected
win, // winner detected
computer_play, // enable computer to play
player_play // enable player to play
);
endmodule
| 7.38656 |
module position_registers (
input clock, // clock of the game
input reset, // reset the game
input illegal_move, // disable writing when an illegal move is detected
input [8:0] PC_en, // Computer enable signals
input [8:0] PL_en, // Player enable signals
output reg [1:0] pos1,
pos2,
pos3,
pos4,
pos5,
pos6,
pos7,
pos8,
pos9 // positions stored
);
// Position 1
always @(posedge clock or posedge reset) begin
if (reset) pos1 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos1 <= pos1; // keep previous position
else if (PC_en[0] == 1'b1) pos1 <= 2'b10; // store computer data
else if (PL_en[0] == 1'b1) pos1 <= 2'b01; // store player data
else pos1 <= pos1; // keep previous position
end
end
// Position 2
always @(posedge clock or posedge reset) begin
if (reset) pos2 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos2 <= pos2; // keep previous position
else if (PC_en[1] == 1'b1) pos2 <= 2'b10; // store computer data
else if (PL_en[1] == 1'b1) pos2 <= 2'b01; // store player data
else pos2 <= pos2; // keep previous position
end
end
// Position 3
always @(posedge clock or posedge reset) begin
if (reset) pos3 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos3 <= pos3; // keep previous position
else if (PC_en[2] == 1'b1) pos3 <= 2'b10; // store computer data
else if (PL_en[2] == 1'b1) pos3 <= 2'b01; // store player data
else pos3 <= pos3; // keep previous position
end
end
// Position 4
always @(posedge clock or posedge reset) begin
if (reset) pos4 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos4 <= pos4; // keep previous position
else if (PC_en[3] == 1'b1) pos4 <= 2'b10; // store computer data
else if (PL_en[3] == 1'b1) pos4 <= 2'b01; // store player data
else pos4 <= pos4; // keep previous position
end
end
// Position 5
always @(posedge clock or posedge reset) begin
if (reset) pos5 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos5 <= pos5; // keep previous position
else if (PC_en[4] == 1'b1) pos5 <= 2'b10; // store computer data
else if (PL_en[4] == 1'b1) pos5 <= 2'b01; // store player data
else pos5 <= pos5; // keep previous position
end
end
// Position 6
always @(posedge clock or posedge reset) begin
if (reset) pos6 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos6 <= pos6; // keep previous position
else if (PC_en[5] == 1'b1) pos6 <= 2'b10; // store computer data
else if (PL_en[5] == 1'b1) pos6 <= 2'b01; // store player data
else pos6 <= pos6; // keep previous position
end
end
// Position 7
always @(posedge clock or posedge reset) begin
if (reset) pos7 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos7 <= pos7; // keep previous position
else if (PC_en[6] == 1'b1) pos7 <= 2'b10; // store computer data
else if (PL_en[6] == 1'b1) pos7 <= 2'b01; // store player data
else pos7 <= pos7; // keep previous position
end
end
// Position 8
always @(posedge clock or posedge reset) begin
if (reset) pos8 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos8 <= pos8; // keep previous position
else if (PC_en[7] == 1'b1) pos8 <= 2'b10; // store computer data
else if (PL_en[7] == 1'b1) pos8 <= 2'b01; // store player data
else pos8 <= pos8; // keep previous position
end
end
// Position 9
always @(posedge clock or posedge reset) begin
if (reset) pos9 <= 2'b00;
else begin
if (illegal_move == 1'b1) pos9 <= pos9; // keep previous position
else if (PC_en[8] == 1'b1) pos9 <= 2'b10; // store computer data
else if (PL_en[8] == 1'b1) pos9 <= 2'b01; // store player data
else pos9 <= pos9; // keep previous position
end
end
endmodule
| 6.859691 |
module fsm_controller (
input clock, // clock of the circuit
input reset, // reset
play, // player plays
pc, // computer plays
illegal_move, // illegal move detected
no_space, // no_space detected
win, // winner detected
output reg computer_play, // enable computer to play
player_play // enable player to play
);
// FSM States
parameter IDLE = 2'b00;
parameter PLAYER = 2'b01;
parameter COMPUTER = 2'b10;
parameter GAME_DONE = 2'b11;
reg [1:0] current_state, next_state;
// current state registers
always @(posedge clock or posedge reset) begin
if (reset) current_state <= IDLE;
else current_state <= next_state;
end
// next state
always @(*) begin
case (current_state)
IDLE: begin
if (reset == 1'b0 && play == 1'b1) next_state <= PLAYER; // player to play
else next_state <= IDLE;
player_play <= 1'b0;
computer_play <= 1'b0;
end
PLAYER: begin
player_play <= 1'b1;
computer_play <= 1'b0;
if (illegal_move == 1'b0) next_state <= COMPUTER; // computer to play
else next_state <= IDLE;
end
COMPUTER: begin
player_play <= 1'b0;
if (pc == 1'b0) begin
next_state <= COMPUTER;
computer_play <= 1'b0;
end else if (win == 1'b0 && no_space == 1'b0) begin
next_state <= IDLE;
computer_play <= 1'b1; // computer to play when PC=1
end else if (no_space == 1 || win == 1'b1) begin
next_state <= GAME_DONE; // game done
computer_play <= 1'b1; // computer to play when PC=1
end
end
GAME_DONE: begin // game done
player_play <= 1'b0;
computer_play <= 1'b0;
if (reset == 1'b1) next_state <= IDLE; // reset the game to IDLE
else next_state <= GAME_DONE;
end
default: next_state <= IDLE;
endcase
end
endmodule
| 7.681256 |
module position_decoder (
input [3:0] in,
input enable,
output wire [15:0] out_en
);
reg [15:0] temp1;
assign out_en = (enable == 1'b1) ? temp1 : 16'd0;
always @(*) begin
case (in)
4'd0: temp1 <= 16'b0000000000000001;
4'd1: temp1 <= 16'b0000000000000010;
4'd2: temp1 <= 16'b0000000000000100;
4'd3: temp1 <= 16'b0000000000001000;
4'd4: temp1 <= 16'b0000000000010000;
4'd5: temp1 <= 16'b0000000000100000;
4'd6: temp1 <= 16'b0000000001000000;
4'd7: temp1 <= 16'b0000000010000000;
4'd8: temp1 <= 16'b0000000100000000;
4'd9: temp1 <= 16'b0000001000000000;
4'd10: temp1 <= 16'b0000010000000000;
4'd11: temp1 <= 16'b0000100000000000;
4'd12: temp1 <= 16'b0001000000000000;
4'd13: temp1 <= 16'b0010000000000000;
4'd14: temp1 <= 16'b0100000000000000;
4'd15: temp1 <= 16'b1000000000000000;
default: temp1 <= 16'b0000000000000001;
endcase
end
endmodule
| 7.76015 |
module tictactoe_tb;
// Inputs
reg clock;
reg reset;
reg play;
reg pc;
reg [3:0] computer_position;
reg [3:0] player_position;
// Outputs
wire [1:0] pos_led1;
wire [1:0] pos_led2;
wire [1:0] pos_led3;
wire [1:0] pos_led4;
wire [1:0] pos_led5;
wire [1:0] pos_led6;
wire [1:0] pos_led7;
wire [1:0] pos_led8;
wire [1:0] pos_led9;
wire [1:0] who;
// Instantiate the Unit Under Test (UUT)
tictactoe uut (
.clock(clock),
.reset(reset),
.play(play),
.pc(pc),
.computer_position(computer_position),
.player_position(player_position),
.pos1(pos_led1),
.pos2(pos_led2),
.pos3(pos_led3),
.pos4(pos_led4),
.pos5(pos_led5),
.pos6(pos_led6),
.pos7(pos_led7),
.pos8(pos_led8),
.pos9(pos_led9),
.who(who)
);
// clock
initial begin
clock = 0;
forever #5 clock = ~clock;
end
initial begin
// Initialize Inputs
play = 0;
reset = 1;
computer_position = 0;
player_position = 0;
pc = 0;
#100;
reset = 0;
#100;
play = 1;
pc = 0;
computer_position = 4;
player_position = 0;
#50;
pc = 1;
play = 0;
#100;
reset = 0;
play = 1;
pc = 0;
computer_position = 8;
player_position = 1;
#50;
pc = 1;
play = 0;
#100;
reset = 0;
play = 1;
pc = 0;
computer_position = 6;
player_position = 2;
#50;
pc = 1;
play = 0;
#50 pc = 0;
play = 0;
end
endmodule
| 7.223526 |
module tb_tic_tac_toe;
// Inputs
reg clock;
reg reset;
reg play;
reg pc;
reg [3:0] computer_position;
reg [3:0] player_position;
// Outputs
wire [1:0] pos_led1;
wire [1:0] pos_led2;
wire [1:0] pos_led3;
wire [1:0] pos_led4;
wire [1:0] pos_led5;
wire [1:0] pos_led6;
wire [1:0] pos_led7;
wire [1:0] pos_led8;
wire [1:0] pos_led9;
wire [1:0] who;
// Instantiate the Unit Under Test (UUT)
tic_tac_toe_game uut (
.clock(clock),
.reset(reset),
.play(play),
.pc(pc),
.computer_position(computer_position),
.player_position(player_position),
.pos1(pos_led1),
.pos2(pos_led2),
.pos3(pos_led3),
.pos4(pos_led4),
.pos5(pos_led5),
.pos6(pos_led6),
.pos7(pos_led7),
.pos8(pos_led8),
.pos9(pos_led9),
.who(who)
);
// clock
initial begin
clock = 0;
forever #5 clock = ~clock;
end
initial begin
// Initialize Inputs
play = 0;
reset = 1;
computer_position = 0;
player_position = 0;
pc = 0;
#100;
reset = 0;
#100;
play = 1;
pc = 0;
computer_position = 4;
player_position = 0;
#50;
pc = 1;
play = 0;
#100;
reset = 0;
play = 1;
pc = 0;
computer_position = 8;
player_position = 1;
#50;
pc = 1;
play = 0;
#100;
reset = 0;
play = 1;
pc = 0;
computer_position = 6;
player_position = 2;
#50;
pc = 1;
play = 0;
#50 pc = 0;
play = 0;
end
endmodule
| 6.721339 |
module tic_tac_toe_top (
input reset,
input clk,
output [3:0] DISP_EN,
output [7:0] SEGMENTS,
output [4:1] COL,
input [4:1] ROW
);
wire [3:0] zz;
wire reset2;
wire pp;
wire last_player;
submission submit_move (
.last_player(last_player),
.reset(reset),
.x(COL),
.y(ROW),
.clk(clk),
.player_out(pp),
.z(zz),
.reset2(reset2)
);
wire [1:0] pos1, pos2, pos3, pos4, pos5, pos6, pos7, pos8, pos9;
wire [1:0] win;
game game_controller (
.clk(clk),
.move({pp, zz}),
.pos1(pos1),
.pos2(pos2),
.pos3(pos3),
.pos4(pos4),
.pos5(pos5),
.pos6(pos6),
.pos7(pos7),
.pos8(pos8),
.pos9(pos9),
.last_player(last_player)
);
win_detector win_detector (
.clk (clk),
.pos1 (pos1),
.pos2 (pos2),
.pos3 (pos3),
.pos4 (pos4),
.pos5 (pos5),
.pos6 (pos6),
.pos7 (pos7),
.pos8 (pos8),
.pos9 (pos9),
.win (win),
.reset(reset2)
);
BC_DEC seven_segment_display (
.player({!last_player}),
.pos1(pos1),
.pos2(pos2),
.pos3(pos3),
.pos4(pos4),
.pos5(pos5),
.pos6(pos6),
.pos7(pos7),
.pos8(pos8),
.pos9(pos9),
.win(win),
.CLK(clk),
.DISP_EN(DISP_EN),
.SEGMENTS(SEGMENTS)
);
endmodule
| 7.482532 |
module tid_m3_for_arty_a7_axis_subset_converter_0_1 #(
parameter C_S_AXIS_TID_WIDTH = 1,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TDATA_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TID_WIDTH = 32
) (
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ (C_M_AXIS_TID_WIDTH == 0 ? 1 : C_M_AXIS_TID_WIDTH)-1:0] tid_out
);
assign tid_out = {tid[0:0]};
endmodule
| 6.966715 |
module tid_m3_for_arty_a7_axis_subset_converter_0_2 #(
parameter C_S_AXIS_TID_WIDTH = 1,
parameter C_S_AXIS_TUSER_WIDTH = 0,
parameter C_S_AXIS_TDATA_WIDTH = 0,
parameter C_S_AXIS_TDEST_WIDTH = 0,
parameter C_M_AXIS_TID_WIDTH = 32
) (
input [ (C_S_AXIS_TID_WIDTH == 0 ? 1 : C_S_AXIS_TID_WIDTH)-1:0] tid,
input [(C_S_AXIS_TDATA_WIDTH == 0 ? 1 : C_S_AXIS_TDATA_WIDTH)-1:0] tdata,
input [(C_S_AXIS_TUSER_WIDTH == 0 ? 1 : C_S_AXIS_TUSER_WIDTH)-1:0] tuser,
input [(C_S_AXIS_TDEST_WIDTH == 0 ? 1 : C_S_AXIS_TDEST_WIDTH)-1:0] tdest,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tkeep,
input [ (C_S_AXIS_TDATA_WIDTH/8)-1:0] tstrb,
input tlast,
output [ (C_M_AXIS_TID_WIDTH == 0 ? 1 : C_M_AXIS_TID_WIDTH)-1:0] tid_out
);
assign tid_out = {tid[0:0]};
endmodule
| 6.966715 |
module tiempodemuestreo
//Declaracion de senales de entrada y salida
(
input wire Clck_in,
enable,
input wire reset_Clock,
output reg Clock_out
);
//Declaracion de senales utilizadas dentro del modulo
reg [18:0] contador;
always @(posedge Clck_in,posedge reset_Clock) //Lista sensitiva, responde ante un flanco positivo del Clck_in o reset_Clock
begin
if (reset_Clock) //Si el reset esta encendido el contador permanece en cero y la salida de reloj que se quiere generar tambien
begin
Clock_out <= 0;
contador <= 0;
end
else if (enable)
begin // Cuando el contador llega a la cuenta de 499999 cambia la polaridad del reloj de salida y reinicia la cuenta, generando un reloj
// de 100Hz. El valor de 499999 necesario para obtener esta senal de reloj se obtuvo redondeando al entero mas cercano el resultado
// de la siguiente formula: [(100MHz/100Hz)/2]-1. Donde 100MHz es el reloj interno de la FPGA y 100Hz el reloj deseado.
if (contador == 19'd499999) begin
contador <= 19'd0;
Clock_out <= ~Clock_out;
end else contador <= contador + 1'b1;
end else begin
contador <= 0;
Clock_out <= 0;
end
end
endmodule
| 6.92659 |
module tier2_control (
clk,
rst,
buffer_all_over,
codestream_generate_start,
cal_truncation_point_start,
cal_truncation_point_over,
codestream_generate_over,
rst_syn
);
input clk;
input rst;
input rst_syn;
input buffer_all_over;
input cal_truncation_point_over;
input codestream_generate_over;
output codestream_generate_start;
output cal_truncation_point_start;
parameter IDLE = 0, BUFFERING_PASSES = 1, CAL_TRUNCATION_POINT = 2, GENERATING_CODESTREAM = 3;
/*********** reg ***********/
reg [2:0] state;
reg [2:0] nextstate;
/********** wire ***********/
wire codestream_generate_start;
wire cal_truncation_point_start;
//////////////////// reg internal
//////////////////// wire internal
assign codestream_generate_start=((state==CAL_TRUNCATION_POINT)&&(nextstate==GENERATING_CODESTREAM));
assign cal_truncation_point_start = (state == CAL_TRUNCATION_POINT);
//////////////////// FSM
always @(posedge clk or negedge rst) begin
if (!rst) state <= IDLE;
else state <= nextstate;
end
always @(*) begin
case (state)
IDLE: begin
if (codestream_generate_over) nextstate = IDLE;
else nextstate = BUFFERING_PASSES;
end
BUFFERING_PASSES: begin
if (buffer_all_over) nextstate = CAL_TRUNCATION_POINT;
else nextstate = BUFFERING_PASSES;
end
CAL_TRUNCATION_POINT: begin
if (cal_truncation_point_over) nextstate = GENERATING_CODESTREAM;
else nextstate = CAL_TRUNCATION_POINT;
end
GENERATING_CODESTREAM: begin
if (rst_syn) nextstate = IDLE;
else nextstate = GENERATING_CODESTREAM;
end
default: nextstate = IDLE;
endcase
end
endmodule
| 7.306225 |
module tier2_ram (
rd_clk,
laddr_rd,
laddr_wr,
output_to_ram,
lram_write_en,
lram_read_en,
ldata_ram,
rst_syn
);
parameter ADDR_WIDTH = 14, WORD_WIDTH = 18;
input rd_clk;
input [ADDR_WIDTH-1:0] laddr_rd;
input [ADDR_WIDTH-1:0] laddr_wr;
input [WORD_WIDTH-1:0] output_to_ram;
input lram_write_en;
input lram_read_en;
input rst_syn;
output [WORD_WIDTH-1:0] ldata_ram;
/***** wire *****/
wire [ADDR_WIDTH-1:0] lram_address;
/***** wire internal *****/
assign lram_address = lram_write_en ? laddr_wr : (lram_read_en ? laddr_rd : 0);
/***** wire output *****/
//assign lrw_=~lram_write_en;
ram_12k ram_12k (
.clka (rd_clk),
.wea (lram_write_en),
.addra(lram_address),
.dina (output_to_ram),
.douta(ldata_ram),
.rsta (rst_syn)
);
endmodule
| 7.230298 |
module tb ();
parameter FRAME_WIDTH = 112;
parameter FRAME_HEIGHT = 48;
parameter SIM_FRAMES = 2;
reg rstn;
reg clk;
reg ee_clk;
wire rstn_ee = rstn;
initial begin
rstn = `RESET_ACTIVE;
#(`RESET_DELAY);
$display("T%d rstn done#############################", $time);
rstn = `RESET_IDLE;
end
initial begin
clk = 1;
forever begin
clk = ~clk;
#(`CLK_PERIOD_DIV2);
end
end
initial begin
ee_clk = 1;
forever begin
ee_clk = ~ee_clk;
#(`EE_CLOCK_PERIOD_DIV2);
end
end
reg gt_ref_clk;
initial begin
gt_ref_clk = 1;
forever begin
gt_ref_clk = ~gt_ref_clk;
#(`GT_REF_CLOCK_PERIOD_DIV2);
end
end
reg [15:0] frame_width_0;
reg [15:0] frame_height_0;
reg [31:0] pic_to_sim;
reg [`MAX_PATH*8-1:0] sequence_name_0;
itf itf (clk);
initial begin
itf.init("mq.log");
#(`RESET_DELAY) #(`RESET_DELAY) itf.start();
// itf.drive();
#(`RESET_DELAY)
//itf.drive_a_frame();
#(500 * `TIME_COEFF)
$finish();
end
wire bytes_out_f;
wire bytes_out_len;
wire [15:0] bytes_out;
packet_header packet_header (
.clk (clk),
.rstn(rstn),
.go (itf.go),
.zero_bitplanes(1),
.pass_num (22),
.codeword_len (4323),
// .zero_bitplanes (2),
// .pass_num (19),
// .codeword_len (3365),
.pp()
);
`ifdef DUMP_FSDB
initial begin
$fsdbDumpfile("fsdb/xx.fsdb");
//$fsdbDumpvars();
$fsdbDumpvars(3, tb);
end
`endif
endmodule
| 7.147559 |
module tiger_reset_clk_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
);
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_in_d1 <= 0;
else data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else data_out <= data_in_d1;
end
endmodule
| 7.277505 |
module tiger_alu (
input signed [31:0] srca,
srcb, // 2 operands
input [ 4:0] alucontrol, // What function to perform
output [31:0] aluout // Result of the function
);
wire unsigned [31:0] srcau = srca;
wire unsigned [31:0] srcbu = srcb;
assign aluout = alucontrol == `ALU_ADD || alucontrol == (`ALU_ADD | `ALU_UNSIGNED) ? srca + srcb
: alucontrol == `ALU_SUB || alucontrol == (`ALU_SUB | `ALU_UNSIGNED) ? srca - srcb
: alucontrol == `ALU_AND ? srca & srcb
: alucontrol == `ALU_OR ? srca | srcb
: alucontrol == `ALU_XOR ? srca ^ srcb
: alucontrol == `ALU_NOR ? ~(srca | srcb)
: alucontrol == `ALU_SLT ? srca < srcb
: alucontrol == (`ALU_SLT | `ALU_UNSIGNED) ? srcau < srcbu
: alucontrol == `ALU_LUI ? {srcb[15:0], 16'b0}
: 32'hxxxx_xxxx;
endmodule
| 6.881237 |
module contains the state machine to control processor for accessing components over Avalon (non-memory related)
module tiger_avalon (
input clk,
input reset,
input [31:0] memaddress,
input memread,
input memwrite,
input [31:0] memwritedata,
input mem8,
input mem16,
output avalon_stall,
output reg [31:0]avm_procMaster_address,
output reg avm_procMaster_read,
output reg avm_procMaster_write,
output reg [31:0] avm_procMaster_writedata,
output reg [3:0] avm_procMaster_byteenable,
input [31:0]avm_procMaster_readdata,
input avm_procMaster_waitrequest,
input avm_procMaster_readdatavalid
);
localparam stateIDLE = 0;
localparam stateAVALON_READ = 1;
localparam stateAVALON_WRITE = 2;
wire [1:0] bytes;
reg [1:0] state;
reg [31:0] procMaster_writedata_32;
reg [3:0] procMaster_byteenable_32;
assign bytes = memaddress[1 : 0];
assign avalon_stall = (state == stateAVALON_READ && !avm_procMaster_readdatavalid) || (memwrite && state != stateIDLE) || (state != stateIDLE && memread);
//state machine for cache controller
always @(posedge clk, posedge reset) begin
if(reset) begin
state <= stateIDLE;
//avm_procMaster_address <= 0;
avm_procMaster_read <= 0;
avm_procMaster_write <= 0;
//avm_procMaster_writedata <= 0;
end else begin
case(state)
stateIDLE: begin
avm_procMaster_address <= {memaddress[31:2], 2'b0};
//if((memread && bypassCache) || memWrite) begin
avm_procMaster_byteenable <= procMaster_byteenable_32;
//end
if(memread) begin //If we want a read
avm_procMaster_read <= 1; //start a read
state <= stateAVALON_READ;
end else if(memwrite) begin //If we want a write
avm_procMaster_write <= 1; //start a read
state <= stateAVALON_WRITE;
avm_procMaster_writedata <= procMaster_writedata_32;
end
end
stateAVALON_READ: begin
//No more wait request so address has been captured
if(!avm_procMaster_waitrequest) begin
avm_procMaster_read <= 0; //So stop asserting read
end
if(avm_procMaster_readdatavalid) begin //We have our data
state <= stateIDLE; //so go back to the idle state
end
end
stateAVALON_WRITE: begin
if(!avm_procMaster_waitrequest) begin //if the write has finished
state <= stateIDLE; //then go back to the idle state
avm_procMaster_write <= 0;
end
end
endcase
end
end
always @(*)
begin
if (mem8)
begin
case (bytes)
2'b00: begin
procMaster_writedata_32 <= {24'd0, memwritedata[7 : 0]};
procMaster_byteenable_32 <= 4'b0001;
end
2'b01: begin
procMaster_writedata_32 <= {16'd0, memwritedata[7 : 0], 8'd0};
procMaster_byteenable_32 <= 4'b0010;
end
2'b10: begin
procMaster_writedata_32 <= {8'd0, memwritedata[7 : 0], 16'd0};
procMaster_byteenable_32 <= 4'b0100;
end
2'b11: begin
procMaster_writedata_32 <= {memwritedata[7 : 0], 24'b0};
procMaster_byteenable_32 <= 4'b1000;
end
default : begin
procMaster_writedata_32 <= 32'dx;
procMaster_byteenable_32 <= 4'bxxxx;
end
endcase
end
else if (mem16)
begin
case (bytes[1])
1'b0: begin
procMaster_writedata_32 <= {16'd0, memwritedata[15 : 0]};
procMaster_byteenable_32 <= 4'b0011;
end
1'b1: begin
procMaster_writedata_32 <= {memwritedata[15 : 0], 16'd0};
procMaster_byteenable_32 <= 4'b1100;
end
default : begin
procMaster_writedata_32 <= 32'dx;
procMaster_byteenable_32 <= 4'bxxxx;
end
endcase
end
else
begin
procMaster_writedata_32 <= memwritedata;
procMaster_byteenable_32 <= 4'b1111;
end
end
endmodule
| 7.358377 |
module contains the state machine to control processor for accessing components over Avalon (non-memory related)
module tiger_avalon_im (
input clk,
input reset,
input [31:0] memaddress,
input memread,
input memwrite,
input [31:0] memwritedata,
input mem8,
input mem16,
output avalon_stall,
output [31:0]avm_procMaster_address,
output avm_procMaster_read,
output avm_procMaster_write,
output [31:0] avm_procMaster_writedata,
output [3:0] avm_procMaster_byteenable,
input [31:0]avm_procMaster_readdata,
input avm_procMaster_waitrequest,
input avm_procMaster_readdatavalid
);
reg outstanding_read;
assign avalon_stall = ~avm_procMaster_readdatavalid;
// assign avalon_stall = avm_procMaster_waitrequest | (outstanding_read & ~avm_procMaster_readdatavalid);
assign avm_procMaster_address = {memaddress[31:2], 2'h0};
// assign avm_procMaster_address = (outstanding_read) ? outstanding_address : memaddress;
assign avm_procMaster_read = memread & (~outstanding_read | avm_procMaster_readdatavalid);
assign avm_procMaster_write = memwrite;
assign avm_procMaster_writedata = memwritedata;
assign avm_procMaster_byteenable = 4'hF;
always @(posedge clk)
begin
if (reset)
outstanding_read <= 1'b0;
else if (avm_procMaster_readdatavalid & (~memread | avm_procMaster_waitrequest))
outstanding_read <= 1'b0;
else if (memread & ~avm_procMaster_waitrequest)
outstanding_read <= 1'b1;
end
endmodule
| 7.358377 |
module tiger_branch (
input clk, // clock signal
input reset, // reset signal
input stall, // stall signal
input exception, // interrupt request signal
input [31:0] instr, // current instruction
input [`CONTROL_WIDTH] control, // control signals
input [31:0] rs, // first operand
input [31:0] rt, // second operand
output reg [31:0] branchout, // return address if we are doing a branch with link operation
output [31:0] epc,
output reg branchDelay,
//modified for checkpoint and rollback
input poweron,
input checkpoint,
output [31:0] nextpc // address of the next instruction to load
);
parameter EXCEPTION_HANDLER_ADDR = 32'h0000_0A00;
parameter BOOT_ADDR = 32'h0000_0000;
reg [31:0] currentpc;
wire [2:0] branchtype = control[`CONTROL_BRANCHTYPE];
wire takebranch = control[`CONTROL_BRANCH] // take the branch if:
&&
( (branchtype == `BR_LTZ && rs[31]) // we have a branch if < 0 instruction and the MSB of the first operand is set
|| (branchtype == `BR_GEZ && !rs[31]) // we have a branch if >= 0 instruction and the MSB of the first operand is not set
|| (branchtype == `BR_EQ && rs == rt) // we have a branch if equal isntruction and both operands are equal to each other
|| (branchtype == `BR_NE && rs != rt) // we have a branch if not equal instruction and both operands are not equal
|| (branchtype == `BR_LEZ && rs[31]) // we have a branch if <= 0 instruction and either the MSB is set
|| (branchtype == `BR_LEZ && rs == 0) // or the register equals 0
|| (branchtype == `BR_GTZ && !rs[31] && rs != 0) // we have a branch if > 0 instruction, and the MSB is not set, and the register does not equal 0
);
// sign extend the immediate constant (used for a relative jump here) and shift 2 places to the left
wire [31:0] signimmsh = {{14{instr[15]}}, instr[15:0], 2'b00};
wire [31:0] pcplus4 = currentpc + 4;
//modified for checkpoint and rollback
wire [31:0] chkptpc = checkpoint ? currentpc - 4 : chkptpc;
assign nextpc = reset ? BOOT_ADDR // reset the start address
//modified for checkpoint and rollback
: poweron ? chkptpc
: stall ? currentpc // we are stalled so do not change the current address
: exception ? EXCEPTION_HANDLER_ADDR
: takebranch ? currentpc + signimmsh // perform a relative branch
: control[`CONTROL_JUMP] ? {currentpc[31:28], instr[25:0], 2'b00} // perform an immediate jump
: control[`CONTROL_REGJUMP] ? rs // perform a jump to the address contained in operand 1
: pcplus4; // if a jump is not being performed, advance the pc by 4
//if we're in a branch delay slot the exception program counter needs to
//point to the branch rather than the instruction in the delay slot
//otherwise we need to point to the instruction where the exception occurred
assign epc = branchDelay ? branchout - 8 : currentpc - 4;
always @(posedge clk) begin
currentpc <= nextpc;
if ((takebranch || control[`CONTROL_JUMP] || control[`CONTROL_REGJUMP]) && !stall)
branchDelay <= 1;
else if (!stall) branchDelay <= 0;
if (reset) begin
branchDelay <= 0;
end else if (!stall) begin
// set the return branch address
branchout <= pcplus4;
end
end
endmodule
| 7.773101 |
module tiger_ff (
input [4:0] regnum, // register number that we are writing to
writereg1, // register number the execute unit wishes to write to
writereg2, // register number the MWB unit wishes to write to
input writeregen1, // enable WB for the execute unit
writeregen2, // enable WB for the MWB unit
input [31:0] regdata, // current contents of the register
writeregdata1, // data the execute unit wishes to write to the register
writeregdata2, // data the MWB unit wishes to write to the register
output [31:0] out
);
//////////////////////////////////////////////////////////////////////////
// The following code performs the same operation as the line commented
// below but synthesises to a better circuit
//////////////////////////////////////////////////////////////////////////
/* assign out = (regnum == 5'b0) ? 32'b0 :
(regnum == writereg1) && writeregen1 ? writeregdata1 :
(regnum == writereg2) && writeregen2 ? writeregdata2 : regdata;
*/
// check to see if regnum == writereg2 and writeregen2 is enabled
wire en2;
tiger_ff_compare c2 (
regnum,
writereg2,
writeregen2,
en2
);
// if it is enabled, then write the data to the register, otherwise write the current contents of the register
// back to it (i.e. do not change the contents of the register
wire [31:0] muxedin2 = en2 ? writeregdata2 : regdata;
// check to see if regnum == writereg1 and writeregen1 is enabled
wire en1;
tiger_ff_compare c1 (
regnum,
writereg1,
writeregen1,
en1
);
// if it is enabled, then write the data to the register, otherwise use the result of the MWB checker above
wire [31:0] muxedin1 = en1 ? writeregdata1 : muxedin2;
// check to see if the register number is zero
// we do not have a 5-input or gate, so use a 4 input and feed
// the result into a 2-input gate
wire notzero1;
or nz1 (notzero1, regnum[0], regnum[1], regnum[2], regnum[3]);
wire notzero;
or nz (notzero, notzero1, regnum[4]);
// if the register number is zero, the 'and' ensures we return the constant zero, as per the MIPS specification
// otherwise we return the data determined by the multiplexor
and a[31:0] (out, muxedin1, notzero);
endmodule
| 8.218401 |
module tiger_ff_compare (
input [4:0] regnum, // the register number we are writing to
input [4:0] writereg, // the register number we wish to write to
input writeregen, // write-enable signal
output en // output indicating if the write is enabled, and the register that is being
// written to is the same as the one we would like to write to
);
///////////////////////////////////////////////////////////////
// The following code performs the operation below
// but synthesises to a better circuit on the FPGA
///////////////////////////////////////////////////////////////
// assign en = (regnum == writereg) && writeregen ? 1'b1 : 1'b0;
// wires indidicating equality
wire eq[5:0];
wire anded[2:0];
// check to see if bits [1:0] of the register numbers are equal
xnor e0 (eq[0], regnum[0], writereg[0]);
and a0 (anded[0], eq[0], eq[1]);
xnor e1 (eq[1], regnum[1], writereg[1]);
// check to see if bits [3:2] of the register numbers are equal
xnor e2 (eq[2], regnum[2], writereg[2]);
and a1 (anded[1], eq[2], eq[3]);
xnor e3 (eq[3], regnum[3], writereg[3]);
// check to see if bit [4] of the register numbers is equal
xnor e4 (eq[4], regnum[4], writereg[4]);
and a2 (anded[2], eq[4], eq[5]);
// we assign the 6th bit of eq the write-enable signal
assign eq[5] = writeregen;
// the write is allowed only if all bits of the register numbers are equal and
// the write has been enabled
and (en, anded[0], anded[1], anded[2]);
endmodule
| 7.008329 |
module tiger_icache_av_1port (
input clk,
input reset_n,
input [29:0] avs_icache_slave_address,
input avs_icache_slave_read,
output [31:0] avs_icache_slave_readdata,
output avs_icache_slave_readdatavalid,
output avs_icache_slave_waitrequest,
input [ `SDRAM_WIDTH-1:0] avm_icache_master_readdata,
input avm_icache_master_readdatavalid,
input avm_icache_master_waitrequest,
output [ 31:0] avm_icache_master_address,
output avm_icache_master_beginbursttransfer,
output [`IBURSTCOUNTWIDTH-1:0] avm_icache_master_burstcount,
output avm_icache_master_read
);
reg outstandingRead;
wire readDataValid;
wire stall;
assign avs_icache_slave_readdatavalid = readDataValid & outstandingRead;
assign avs_icache_slave_waitrequest = stall | (outstandingRead & ~avs_icache_slave_readdatavalid) | ~reset_n;
always @(posedge clk) begin
if (~reset_n) outstandingRead <= 1'b0;
else if (avs_icache_slave_read) outstandingRead <= 1'b1;
else if (avs_icache_slave_readdatavalid) outstandingRead <= 1'b0;
end
tiger_icache tiger_icache_inst (
.clk (clk),
.reset_n(reset_n),
//CPU side memory control signals
.PROC0_memRead (avs_icache_slave_read | outstandingRead),
.PROC0_memAddress ({avs_icache_slave_address, 2'h0}),
.PROC0_memReadData(avs_icache_slave_readdata),
.PROC0_flush(1'b0),
.PROC0_canFlush(),
//True if the data on memReadData is valid (i.e. data we've just read from the cache)
.PROC0_readDataValid(readDataValid),
//CPU pipeline stall
.PROC0_stall(stall),
//Avalon Bus side signals
.avm_dataMaster0_read (avm_icache_master_read),
.avm_dataMaster0_address (avm_icache_master_address),
.avm_dataMaster0_beginbursttransfer(avm_icache_master_beginbursttransfer),
.avm_dataMaster0_burstcount (avm_icache_master_burstcount),
.avm_dataMaster0_readdata (avm_icache_master_readdata),
.avm_dataMaster0_waitrequest (avm_icache_master_waitrequest & avm_icache_master_read),
.avm_dataMaster0_readdatavalid (avm_icache_master_readdatavalid)
);
endmodule
| 6.945937 |
module tiger_icache_memory (
address,
clken,
clock,
data,
wren,
q
);
input [8:0] address;
input clken;
input clock;
input [147:0] data;
input wren;
output [147:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [147:0] sub_wire0;
wire [147:0] q = sub_wire0[147:0];
altsyncram altsyncram_component (
.address_a(address),
.clock0(clock),
.data_a(data),
.wren_a(wren),
.clocken0(clken),
.q_a(sub_wire0),
.aclr0(1'b0),
.aclr1(1'b0),
.address_b(1'b1),
.addressstall_a(1'b0),
.addressstall_b(1'b0),
.byteena_a(1'b1),
.byteena_b(1'b1),
.clock1(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
.data_b(1'b1),
.eccstatus(),
.q_b(),
.rden_a(1'b1),
.rden_b(1'b1),
.wren_b(1'b0)
);
defparam altsyncram_component.clock_enable_input_a = "NORMAL",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram", altsyncram_component.maximum_depth = 512,
altsyncram_component.numwords_a = 512, altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.widthad_a = 9,
altsyncram_component.width_a = 148, altsyncram_component.width_byteena_a = 1;
endmodule
| 6.945937 |
module tiger_icache_mux_param (
Z,
SEL,
D
);
parameter N = 8; //number of bits wide
parameter M = 4; //number of inputs
parameter S = 2; //number of select lines
parameter W = M * N;
`define DTOTAL W-1:0
`define DWIDTH N-1:0
`define SELW S-1:0
`define WORDS M-1:0
input [`DTOTAL] D;
input [`SELW] SEL;
output [`DWIDTH] Z;
integer i;
reg [`DWIDTH] tmp, Z; //tmp will be used to minimize events
always @(SEL or D) begin
for (i = 0; i < N; i = i + 1) //for bits in the width
tmp[i] = D[N*SEL+i];
Z = tmp;
end
endmodule
| 6.945937 |
module tiger_memoryaccess (
input clk, // clock signal
input reset,
input clear,
input stall,
input [31:0] instr, // current instruction
input [`CONTROL_WIDTH] control, // control signals
input [31:0] executeout, // output of the execute stage
input [31:0] branchout,
output reg [`CONTROL_WIDTH] controlWB,
output reg [31:0] MAOutWB,
output reg [31:0] branchoutWB,
output reg [31:0] instrWB,
//input [1:0] bottomaddress, // bottom bits of the address
input [31:0] memreaddata, // data read from memory
//true if we wish to write to the register given in writeRegNum
//the write will actually be done in the following WB stage
output writeRegEn,
//the number of the register we're going write to (in the WB stage)
output [`REGNUM_WIDTH] writeRegNum,
//true if we wish to write to the coprocessor register given in writeRegNum
//the write will actually be done in the following WB stage
output writeRegEnCop,
//if we are going to write to a register, what data we would write
//note that this is the output from the execute stage
//if we are reading from memory, the memory read data will
//be put into the next pipeline register at the next clock
output [31:0] writeRegData
);
assign writeRegEn = control[`CONTROL_REGWRITE];
assign writeRegEnCop = control[`CONTROL_COPWRITE];
assign writeRegNum = control[`CONTROL_WRITEREGNUM];
assign writeRegData = executeout;
wire [31:0] memData;
assign memData = memreaddata;
/*assign memregdata = control[`CONTROL_MEML] ? // left hand side of the bus
bottomaddress==2'd0 ? memreaddata
:bottomaddress==2'd1 ? {memreaddata[23:0],executeout[7:0]}
:bottomaddress==2'd2 ? {memreaddata[15:0],executeout[15:0]}
:bottomaddress==2'd3 ? {memreaddata[7:0],executeout[23:0]}
: 32'hXXXX_XXXX
:control[`CONTROL_MEMR] ? // right hand side of the bus
bottomaddress==2'd0 ? {executeout[31:8],memreaddata[31:24]}
:bottomaddress==2'd1 ? {executeout[31:16],memreaddata[31:16]}
:bottomaddress==2'd2 ? {executeout[31:24],memreaddata[31:8]}
:bottomaddress==2'd3 ? memreaddata
: 32'hXXXX_XXXX
:memreaddata;*/
//Pipeline, on the positive clock edge move everything to the next pipeline stage
always @(posedge clk) begin
if (reset || clear) begin
controlWB <= 0;
MAOutWB <= 0;
branchoutWB <= 0;
instrWB <= 0;
end else if (stall) begin
//stall controlWB
//stall MAOutWB
//stall branchoutWB
//stall instrWB
end else begin
controlWB <= control;
MAOutWB <= control[`CONTROL_MEMREAD] ?
(!control[`CONTROL_ZEROFILL] && control[`CONTROL_MEM8] ? {{24{memData[7]}}, memData[7 : 0]}
: !control[`CONTROL_ZEROFILL] && control[`CONTROL_MEM16] ? {{16{memData[15]}}, memData[15 : 0]}
: memData)
: executeout;
branchoutWB <= branchout;
instrWB <= instr;
end
end
endmodule
| 7.597911 |
module tiger_round (
input i_clk,
input [63:0] i_ain,
input [63:0] i_bin,
input [63:0] i_cin,
input [63:0] i_xin,
input [3:0] i_mul,
output [63:0] o_aout,
output [63:0] o_bout,
output [63:0] o_cout
);
localparam DLY = 1;
wire [63:0] s_a, s_b, s_c;
reg [63:0] r_c;
reg [63:0] r_ain, r_bin;
reg [ 3:0] r_mul;
wire [ 7:0] s_sin [7:0];
wire [63:0] s_sout[7:0];
always @(posedge i_clk) begin
r_ain <= #DLY i_ain;
r_bin <= #DLY i_bin;
r_mul <= #DLY i_mul;
end
always @(posedge i_clk) begin
r_c <= #DLY s_c;
end
assign s_c = i_cin ^ i_xin;
assign s_sin[0] = s_c[7:0];
assign s_sin[1] = s_c[15:8];
assign s_sin[2] = s_c[23:16];
assign s_sin[3] = s_c[31:24];
assign s_sin[4] = s_c[39:32];
assign s_sin[5] = s_c[47:40];
assign s_sin[6] = s_c[55:48];
assign s_sin[7] = s_c[63:56];
assign s_a = r_ain - (s_sout[0] ^ s_sout[2] ^ s_sout[4] ^ s_sout[6]);
assign s_b = r_bin + (s_sout[1] ^ s_sout[3] ^ s_sout[5] ^ s_sout[7]);
assign o_aout = s_a;
assign o_bout = (r_mul==4'd5) ? ({s_b[61:0],2'b0} + s_b):
((r_mul==4'd7) ? ({s_b[60:0],3'b0} - s_b):
((r_mul==4'd9) ? ({s_b[60:0],3'b0} + s_b): 64'b0));
assign o_cout = r_c;
//t1
tiger_sbox_a u_sbox_0 (
.i_clk (i_clk),
.i_addr(s_sin[0]),
.o_data(s_sout[0])
);
//t2
tiger_sbox_b u_sbox_1 (
.i_clk (i_clk),
.i_addr(s_sin[2]),
.o_data(s_sout[2])
);
//t3
tiger_sbox_c u_sbox_2 (
.i_clk (i_clk),
.i_addr(s_sin[4]),
.o_data(s_sout[4])
);
//t4
tiger_sbox_d u_sbox_3 (
.i_clk (i_clk),
.i_addr(s_sin[6]),
.o_data(s_sout[6])
);
//t4
tiger_sbox_d u_sbox_4 (
.i_clk (i_clk),
.i_addr(s_sin[1]),
.o_data(s_sout[1])
);
//t3
tiger_sbox_c u_sbox_5 (
.i_clk (i_clk),
.i_addr(s_sin[3]),
.o_data(s_sout[3])
);
//t2
tiger_sbox_b u_sbox_6 (
.i_clk (i_clk),
.i_addr(s_sin[5]),
.o_data(s_sout[5])
);
//t1
tiger_sbox_a u_sbox_7 (
.i_clk (i_clk),
.i_addr(s_sin[7]),
.o_data(s_sout[7])
);
endmodule
| 6.723734 |
module tiger_shifter (
input [31:0] src, // source data
input [4:0] amt, // number of bits to shift by
input dir, // direction to shift (0 = left; 1 = right)
input alusigned, // signed shift? 0 = unsigned; 1 = signed
output [31:0] shifted // output
);
// fill bit for right shifts
wire fillbit = alusigned & src[31];
// do a right shift by shifting 0-5 times
wire [31:0] right16;
wire [31:0] right8;
wire [31:0] right4;
wire [31:0] right2;
wire [31:0] right1;
wire [31:0] right;
assign right16 = amt[4] ? {{16{fillbit}}, src[31:16]} : src;
assign right8 = amt[3] ? {{8{fillbit}}, right16[31:8]} : right16;
assign right4 = amt[2] ? {{4{fillbit}}, right8[31:4]} : right8;
assign right2 = amt[1] ? {{2{fillbit}}, right4[31:2]} : right4;
assign right1 = amt[0] ? {{1{fillbit}}, right2[31:1]} : right2;
assign right = right1;
// do a left shift by shifting 0-5 times
wire [31:0] left16;
wire [31:0] left8;
wire [31:0] left4;
wire [31:0] left2;
wire [31:0] left1;
wire [31:0] left;
assign left16 = amt[4] ? {src[15:0], 16'b0} : src;
assign left8 = amt[3] ? {left16[23:0], 8'b0} : left16;
assign left4 = amt[2] ? {left8[27:0], 4'b0} : left8;
assign left2 = amt[1] ? {left4[29:0], 2'b0} : left4;
assign left1 = amt[0] ? {left2[30:0], 1'b0} : left2;
assign left = left1;
// select the correct shift output
assign shifted = dir ? right : left;
endmodule
| 7.133542 |
module tiger_wrapper (
input CLOCK_27,
/*
output [17:0] LEDR,
output [8:0] LEDG,
*/
/*
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
*/
output [11:0] DRAM_ADDR,
output DRAM_BA_0,
output DRAM_BA_1,
output DRAM_LDQM,
output DRAM_UDQM,
output DRAM_RAS_N,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_WE_N,
output DRAM_CS_N,
output DRAM_CLK,
inout [15:0] DRAM_DQ
/*,
input UART_RXD,
output UART_TXD
*/
);
// SDRAM clock must lead CPU clock by 3ns
pll25MHz pll25 (
.inclk0(CLOCK_27),
.c0(CLOCK_25),
.c1(DRAM_CLK)
);
tiger tiger_sopc (
// general
.clk(CLOCK_25),
.reset_n(1'b1),
// LEDs
/*
.out_port_from_the_GreenLED(LEDG[8:0]),
.out_port_from_the_RedLED(LEDR[17:0]),
*/
/*
// Hex LEDs
.HEX0_from_the_HexLED_0(HEX0),
.HEX1_from_the_HexLED_0(HEX1),
.HEX2_from_the_HexLED_0(HEX2),
.HEX3_from_the_HexLED_0(HEX3),
.HEX4_from_the_HexLED_0(HEX4),
.HEX5_from_the_HexLED_0(HEX5),
.HEX6_from_the_HexLED_0(HEX6),
.HEX7_from_the_HexLED_0(HEX7),
*/
// SDRAM
.zs_addr_from_the_sdram(DRAM_ADDR),
.zs_ba_from_the_sdram({DRAM_BA_1, DRAM_BA_0}),
.zs_cas_n_from_the_sdram(DRAM_CAS_N),
.zs_cke_from_the_sdram(DRAM_CKE),
.zs_cs_n_from_the_sdram(DRAM_CS_N),
.zs_dq_to_and_from_the_sdram(DRAM_DQ),
.zs_dqm_from_the_sdram({DRAM_UDQM, DRAM_LDQM}),
.zs_ras_n_from_the_sdram(DRAM_RAS_N),
.zs_we_n_from_the_sdram(DRAM_WE_N)
// UART
/*
.rxd_to_the_uart_0(UART_RXD),
.txd_from_the_uart_0(UART_TXD)
*/
);
endmodule
| 6.686357 |
module tiger_writeback (
input clk, // clock signal
input [31:0] instr, // current instruction
input [`CONTROL_WIDTH] control, // control signals
input [31:0] branchout, // the branch address to save if we are doing a link operation
input [31:0] MAOut, // result from the memory access stage
output writeRegEn, // output indicating if we wish to write to a register
output writeRegEnCop, // output indicating if we wish to write to a coprocessor register
output [`REGNUM_WIDTH] writeRegNum, // what register number to write to
output [31:0] writeRegData // data to store in the register
);
assign writeRegEn = control[`CONTROL_REGWRITE];
assign writeRegEnCop = control[`CONTROL_COPWRITE];
assign writeRegNum = control[`CONTROL_WRITEREGNUM];
assign writeRegData = MAOut;
endmodule
| 7.303956 |
module tiktaktoe (
CLOCK_50, // On Board 50 MHz
// Your inputs and outputs here
KEY,
HEX0,
HEX1,
// The ports below are for the VGA output. Do not change.
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
input CLOCK_50; // 50 MHz
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
output [6:0] HEX0;
output [6:0] HEX1;
wire resetn;
wire left;
wire right;
wire select;
assign resetn = KEY[0];
assign select = ~KEY[2];
// Create the colour, cursor_x, cursor_y and writeEn wires that are inputs to the controller.
wire [2:0] colour;
wire [6:0] cursor_x;
wire [6:0] cursor_y;
wire [1:0] player;
wire [6:0] draw_x;
wire [6:0] draw_y;
wire writeEn;
wire enable;
wire [1:0] winner;
wire [3:0] grid_x;
wire [3:0] grid_y;
wire [3:0] hex_digit;
wire [3:0] hex_p;
wire [97:0] full_grid;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA (
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(draw_x),
.y(draw_y),
.plot(enable),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK)
);
defparam VGA.RESOLUTION = "160x120"; defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1; defparam VGA.BACKGROUND_IMAGE = "grid.mif";
// Put your code here. Your code should produce signals x,y,colour and writeEn/plot
// for the VGA controller, in addition to any other functionality your design may require.
pulse pulse_left (
left,
~KEY[3],
CLOCK_50
);
pulse pulse_right (
right,
~KEY[1],
CLOCK_50
);
// Instansiate datapath
datapath d0 (
left,
right,
cursor_x,
cursor_y,
grid_x,
grid_y,
winner,
colour,
select,
CLOCK_50,
resetn,
enable,
draw_x,
draw_y,
player,
hex_p,
hex_digit
);
hex_decoder hex_0 (
hex_digit,
HEX0
);
hex_decoder hex_1 (
hex_p,
HEX1
);
// Instansiate FSM control
control c0 (
select,
resetn,
CLOCK_50,
enable,
player
);
endmodule
| 7.692648 |
module rate_counter (
clock,
reset_n,
enable,
q
);
input clock;
input reset_n;
input enable;
output reg [1:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) q <= 2'b11;
else if (enable == 1'b1) begin
if (q == 2'b00) q <= 2'b11;
else q <= q - 1'b1;
end
end
endmodule
| 6.605756 |
module rate_counter1 (
clock,
reset_n,
enable,
q
);
input clock;
input reset_n;
input enable;
output reg [4:0] q;
always @(posedge clock) begin
if (reset_n == 1'b0) q <= 5'b10000;
else if (enable == 1'b1) begin
if (q == 5'b00000) q <= 5'b10000;
else q <= q - 1'b1;
end
end
endmodule
| 7.198693 |
module control (
select_btn,
reset_n,
clock,
enable,
player
);
input select_btn, reset_n, clock;
output reg enable;
output reg [1:0] player;
reg [2:0] current_state, next_state;
wire clock_1;
rate_counter1 m1 (
clock,
reset_n,
1'b1,
q
);
assign clock_1 = (q == 5'b00000) ? 1 : 0;
localparam SELECT_1 = 3'd0, P_ONE = 3'd1, SELECT_2 = 3'd2, P_TWO = 3'd3, SELECT_3 = 3'd4;
always @(*) begin : state_table
case (current_state)
SELECT_1: next_state = select_btn ? P_ONE : SELECT_1;
P_ONE: next_state = ~select_btn ? SELECT_2 : P_ONE;
SELECT_2: next_state = select_btn ? P_TWO : SELECT_2;
P_TWO: next_state = ~select_btn ? SELECT_3 : P_TWO;
SELECT_3: next_state = SELECT_1;
default: next_state = SELECT_1;
endcase
end
always @(*) begin : enable_signals
enable = 1'b0;
player = 2'b00;
case (current_state)
P_ONE: begin
enable = 1'b1;
player = 2'b01;
end
P_TWO: begin
enable = 1'b1;
player = 2'b10;
end
endcase
end
always @(posedge clock_1) begin : state_FFs
if (!reset_n) current_state <= SELECT_1;
else current_state <= next_state;
end
endmodule
| 7.715617 |
module hex_decoder (
hex_digit,
segments
);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b111_1111; // displays nothing
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b000_1100; // display 'P'
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
4'hA: segments = 7'b000_1000;
4'hB: segments = 7'b000_0011;
4'hC: segments = 7'b100_0110;
4'hD: segments = 7'b010_0001;
4'hE: segments = 7'b000_0110;
4'hF: segments = 7'b000_1110;
default: segments = 7'h7f;
endcase
endmodule
| 7.584821 |
module tilde (
input [31:0] irq,
mask,
output reg [31:0] wrdata,
output reg zero,
lognot
);
reg [1023:0] arg;
assign wrdata = irq & ~mask;
assign zero = !mask;
assign lognot = !$value$plusargs("lognot=%d", arg);
endmodule
| 6.57178 |
module CrossBarCell (
input [63:0] io_fw_left,
input [63:0] io_fw_top,
output [63:0] io_fw_bottom,
output [63:0] io_fw_right,
input io_sel
);
assign io_fw_bottom = io_sel ? io_fw_left : io_fw_top; // @[CrossBarSwitchNew.scala 15:17 CrossBarSwitchNew.scala 16:18 CrossBarSwitchNew.scala 18:18]
assign io_fw_right = io_fw_left; // @[CrossBarSwitchNew.scala 14:15]
endmodule
| 7.603405 |
module RegMux (
input clock,
input [63:0] io_in,
output [63:0] io_out,
input io_sel
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
`endif // RANDOMIZE_REG_INIT
reg [63:0] reg_; // @[RegMux.scala 11:16]
wire [63:0] _GEN_0 = io_sel ? reg_ : io_in; // @[RegMux.scala 15:32 RegMux.scala 16:12 RegMux.scala 18:12]
assign io_out = ~io_sel ? io_in : _GEN_0; // @[RegMux.scala 13:27 RegMux.scala 14:12]
always @(posedge clock) begin
reg_ <= io_in; // @[RegMux.scala 12:7]
end
// Register and memory initialization
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin
end
`else
#0.002 begin
end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
reg_ = _RAND_0[63:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
endmodule
| 6.643954 |
module iob_2p_assim_mem_tiled #(
parameter DATA_W_A = 32, // port A data width
parameter DATA_W_B = 16, // port B data width
parameter N_WORDS = 8192, // number of words (each word has 'DATA_W/8' bytes)
parameter ADDR_W_A = $clog2(N_WORDS * DATA_W_A / 8), // port A address width
parameter ADDR_W_B = $clog2(N_WORDS * DATA_W_B / 8), // port B address width
parameter TILE_ADDR_W = 11, // log2 of block size
parameter USE_RAM = 0
) (
// Inputs
input clk,
input w_en,
input r_en,
input [DATA_W_A-1:0] data_in, // input data to write port
input [ADDR_W_A-1:0] w_addr, // address for write port
input [ADDR_W_B-1:0] r_addr, // address for read port
// Outputs
output reg [DATA_W_B-1:0] data_out //output port
);
// Number of BRAMs to generate, each containing 2**TILE_ADDR_W bytes
localparam K = $ceil(2 ** (ADDR_W_A - TILE_ADDR_W));
// Address decoder: enables write on selected BRAM
wire [K-1:0] addr_en; // address decoder output
decN #(
.N_OUTPUTS(K)
) addr_dec (
.dec_in(w_addr[ADDR_W_A-1:ADDR_W_A-$clog2(
K
)]), // only the first clog2(K) MSBs select the BRAM
.dec_out(addr_en)
);
// Generate K BRAMs
genvar i;
generate
// Vector containing all BRAM outputs
wire [DATA_W_B-1:0] data_out_vec[K-1:0];
for (i = 0; i < K; i = i + 1) begin
iob_2p_assim_mem #(
.W_DATA_W(DATA_W_A),
.W_ADDR_W(ADDR_W_A - $clog2(K)),
.R_DATA_W(DATA_W_B),
.R_ADDR_W(ADDR_W_B - $clog2(K)),
.USE_RAM (USE_RAM)
) bram (
.clk(clk),
.w_en(w_en & addr_en[i]),
.r_en(r_en & addr_en[i]),
.data_in(data_in),
.w_addr(w_addr[ADDR_W_A-$clog2(K)-1:0]),
.r_addr(r_addr[ADDR_W_B-$clog2(K)-1:0]),
.data_out(data_out_vec[i])
);
end
endgenerate
// bram mux: outputs selected BRAM
muxN #(
.N_INPUTS(K),
.INPUT_W (DATA_W_B)
) bram_out_sel (
.data_in(data_out_vec),
.sel(r_addr[ADDR_W_B-1:ADDR_W_B-$clog2(K)]),
.data_out(data_out)
);
endmodule
| 6.69528 |
module decN #(
parameter N_OUTPUTS = 16
) (
input [$clog2(N_OUTPUTS)-1:0] dec_in,
output reg [N_OUTPUTS-1:0] dec_out
);
always @* begin
dec_out = 0;
dec_out[dec_in] = 1'b1;
end
endmodule
| 6.877415 |
module muxN #(
parameter N_INPUTS = 4, // number of inputs
parameter INPUT_W = 8, // input bit width
parameter S = $clog2(N_INPUTS), // number of select lines
parameter W = N_INPUTS * INPUT_W // total data width
) (
// Inputs
input [INPUT_W-1:0] data_in[N_INPUTS-1:0], // input port
input [ S-1:0] sel, // selection port
// Outputs
output reg [INPUT_W-1:0] data_out // output port
);
always @* begin
data_out = data_in[sel];
end
endmodule
| 8.176797 |
module tiledBcdCounter (
output [DIGITS*4-1:0] num,
output cout,
output bout,
input [DIGITS-1:0] ups,
input [DIGITS-1:0] downs,
input set9,
input set0,
input clock
);
parameter DIGITS = 4;
wire [DIGITS:0] cin, bin;
assign cin[0] = 0;
assign bin[0] = 0;
assign cout = cin[DIGITS];
assign bout = bin[DIGITS];
genvar c;
generate
for (c = 0; c < DIGITS; c = c + 1) begin
wire up, down;
assign up = cin[c] | ups[c];
assign down = bin[c] | downs[c];
bcdCounter counter (
num[c*4+3:c*4],
cin[c+1],
bin[c+1],
up,
down,
set9,
set0,
clock
);
end
endgenerate
endmodule
| 6.893296 |
module iob_2p_assim_mem_tiled_tb;
// Inputs
reg clk;
reg w_en;
reg r_en;
reg [`W_DATA-1:0] data_in;
reg [`W_ADDR-1:0] w_addr;
reg [`R_ADDR-1:0] r_addr;
// Outputs
wire [`R_DATA-1:0] data_out;
integer i, seq_ini;
integer test, base_block;
parameter clk_per = 10; // clk period = 10 timeticks
// Instantiate the Unit Under Test (UUT)
iob_2p_assim_mem_tiled #(
.DATA_W_A(`W_DATA),
.DATA_W_B(`R_DATA),
.N_WORDS(`WORDS),
.TILE_ADDR_W(`TILE_ADDR_W),
.USE_RAM(`USE_RAM)
) uut (
.clk(clk),
.w_en(w_en),
.r_en(r_en),
.data_in(data_in),
.w_addr(w_addr),
.r_addr(r_addr),
.data_out(data_out)
);
// system clock
always #(clk_per / 2) clk = ~clk;
initial begin
// Initialize Inputs
clk = 1;
w_addr = 0;
w_en = 0;
r_en = 0;
data_in = 0;
r_addr = 0;
// Number from which to start the incremental sequence to write into the RAM
seq_ini = 32;
// Write data > read data
if (`R_BIG == 0) begin
// optional VCD
`ifdef VCD
$dumpfile("2p_assim_mem_tiled_w.vcd");
$dumpvars();
`endif
//Write all the locations of RAM
w_en = 1;
for (i = 0; i < 4; i = i + 1) begin
data_in[7:0] = i * 4 + seq_ini;
data_in[15:8] = i * 4 + 1 + seq_ini;
data_in[23:16] = i * 4 + 2 + seq_ini;
data_in[31:24] = i * 4 + 3 + seq_ini;
w_addr = i;
#(clk_per);
@(posedge clk) #1;
end
w_en = 0;
@(posedge clk) #1;
if (`USE_RAM == 1) begin
for (i = 0; i < 16; i = i + 1) begin
r_addr = i;
@(posedge clk) #1;
if (data_out != 0) begin
$display(
"Test 1 failed: with r_en = 0, at position %0d, data_out should be 0 but is %d", i,
data_out);
$finish;
end
end
end
//Read all the locations of RAM
r_en = 1;
for (i = 0; i < 16; i = i + 1) begin
r_addr = i;
@(posedge clk) #1;
if (data_out != i + seq_ini) begin
$display(
"Test 2 failed: read error in data_out. \n \t i=%0d; data = %h when it should have been %0h",
i, data_out, i + 32);
end
end
end
// Read data > write data
if (`R_BIG == 1) begin
// optional VCD
`ifdef VCD
$dumpfile("2p_assim_mem_tiled_r.vcd");
$dumpvars();
`endif
@(posedge clk) #1;
//Write all the locations of RAM
w_en = 1;
for (i = 0; i < 16; i = i + 1) begin
w_addr = i;
data_in = i + seq_ini;
@(posedge clk) #1;
end
w_en = 0;
@(posedge clk) #1;
//Read all the locations of RAM
r_en = 1;
for (i = 0; i < 4; i = i + 1) begin
r_addr = i;
@(posedge clk) #1;
if(data_out[7:0]!=i*4+seq_ini || data_out[15:8]!=i*4+1+seq_ini ||
data_out[23:16]!=i*4+2+seq_ini || data_out[31:24]!=i*4+3+seq_ini) begin
$display("Test 3 failed: read error in data_out.\n\t");
$finish;
end
@(posedge clk) #1;
end
end
@(posedge clk) #1;
r_en = 0;
#clk_per $display("%c[1;34m", 27);
$display("Test completed successfully.");
$display("%c[0m", 27);
#(5 * clk_per) $finish;
end
endmodule
| 6.69528 |
module: TILEGEN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// License: https://www.apache.org/licenses/LICENSE-2.0
//
////////////////////////////////////////////////////////////////////////////////
`include "../roms/rthunder.vh"
module tilegen_dual_tb
(
// Inputs
input reg clk_in,
input reg rst,
output wire [7:0] R,
output wire [7:0] G,
output wire [7:0] B,
output wire HSYNC,
output wire VSYNC
);
// == supply rails ==
supply1 VCC;
supply0 GND;
wire CLK_6M;
wire CLK_2H;
// Timing subsystem
TIMING timing(
.CLK_48M(clk_in),
.CLK_6M(CLK_6M),
.VSYNC(VSYNC),
.HSYNC(HSYNC),
.HBLANK(HBLANK),
.VBLANK(VBLANK),
.VRESET(VRESET),
.COMPSYNC(COMPSYNC),
.CLK_2H(CLK_2H)
);
// Inputs
reg SCROLL0;
reg SCROLL1;
reg LATCH0;
reg LATCH1;
reg FLIP;
reg SRCWIN;
reg BACKCOLOR;
reg [12:0] A;
reg WE;
reg [7:0] MD;
// Outputs
wire [2:0] SPR;
wire [7:0] DOT;
// Bidirs
wire [7:0] D;
wire [20:1] J5;
reg [2:0] counter = 0;
integer rgb_fd;
// Instantiate the Unit Under Test (UUT)
TILEGEN
#(
`ROM_4R, `ROM_4S, `ROM_4V, `ROM_6U, `ROM_7R, `ROM_7S
)
uut
(
.CLK_6M(CLK_6M),
.CLK_2H(CLK_2H),
.SCROLL0(SCROLL0),
.SCROLL1(SCROLL1),
.LATCH0(LATCH0),
.LATCH1(LATCH1),
.HSYNC(HSYNC),
.VSYNC(VSYNC),
.FLIP(FLIP),
.SRCWIN(SRCWIN),
.BACKCOLOR(BACKCOLOR),
.A(A),
.WE(WE),
.MD(MD),
.D(D),
.J5(J5),
.SPR(SPR),
.DOT(DOT)
);
initial begin
// Initialize Inputs
clk_in = 0;
FLIP = 0;
SRCWIN = 0;
BACKCOLOR = 0;
A = 0;
WE = 0;
MD = 0;
rgb_fd = $fopen("rgb.log", "w");
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always begin
#10.1725 clk_in = ~clk_in;
if (!rst) begin
if (counter[2])
$fwrite(rgb_fd, "%0d ns: %b %b %b %b %b\n", $time, HSYNC, VSYNC, R, G, B);
if (clk_in)
counter = counter + 1;
end
end
endmodule
| 7.238032 |
module TileMap (
input wire clk,
input wire reset_n,
input wire [5:0] i_tilemap_x_idx,
input wire [5:0] i_tilemap_y_idx,
output reg [7:0] o_tilemap_texture_idx,
input wire [31:0] i_wdata,
input wire i_wea,
input wire [3:0] i_wselect,
input wire [26:0] i_waddr
);
wire [3:0] select_with_we = {4{i_wea}} & i_wselect;
wire [11:0] read_byte_address = {i_tilemap_y_idx, 5'h0} + {i_tilemap_y_idx, 3'h0} + i_tilemap_x_idx;
wire [31:0] raw_read_data;
tilemap_block_mem tilemap_block_mem_inst (
.clka (clk), // input wire clka
.wea (select_with_we), // input wire [3 : 0] wea
.addra(i_waddr[11:2]), // input wire [9 : 0] addra
.dina (i_wdata), // input wire [31 : 0] dina
.clkb (clk), // input wire clkb
.addrb(read_byte_address[11:2]), // input wire [9 : 0] addrb
.doutb(raw_read_data) // output wire [31 : 0] doutb
);
reg [1:0] last_two_bit;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
last_two_bit <= 0;
end else begin
last_two_bit <= read_byte_address[1:0];
end
end
always @(*) begin
case (last_two_bit[1:0])
2'b00: begin
o_tilemap_texture_idx = raw_read_data[31:24];
end
2'b01: begin
o_tilemap_texture_idx = raw_read_data[23:16];
end
2'b10: begin
o_tilemap_texture_idx = raw_read_data[15:8];
end
default: begin
o_tilemap_texture_idx = raw_read_data[7:0];
end
endcase
end
endmodule
| 7.238453 |
module tilemem #(
parameter ZOOM = 0
) (
input wire clk,
input wire [ 25:0] RGBStr_i,
output reg [`FONT_WIDTH-1:0] char_code
);
localparam cols = 80 / 2 ** ZOOM;
localparam rows = 60 / 2 ** ZOOM;
wire [9:0] px_x, px_y;
assign px_x = RGBStr_i[`XC];
assign px_y = RGBStr_i[`YC];
wire [(13-2*ZOOM)-1:0] raddr;
assign raddr = px_y[8:(3+ZOOM)] * 80 + px_x[9:(3+ZOOM)]; // y (480) is 1 bit shorter than x (640)
wire [`FONT_WIDTH-1:0] rdata;
ram #(
.ram_size (cols * rows),
.data_width(`FONT_WIDTH)
) ram0 (
.rclk(clk),
.raddr(raddr),
.dout(rdata),
.wclk(clk),
.write_en(1'b0) // disable write port for now
);
defparam ram0.ROMFILE = "ram65.list";
// Registred output
always @(posedge clk) begin
char_code <= rdata;
end
endmodule
| 7.592803 |
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