code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_xgmii_baser_dec_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] encoded_rx_data = 0;
reg [HDR_WIDTH-1:0] encoded_rx_hdr = 0;
// Outputs
wire [DATA_WIDTH-1:0] xgmii_rxd;
wire [CTRL_WIDTH-1:0] xgmii_rxc;
wire rx_bad_block;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, encoded_rx_data, encoded_rx_hdr);
$to_myhdl(xgmii_rxd, xgmii_rxc, rx_bad_block);
// dump file
$dumpfile("test_xgmii_baser_dec_64.lxt");
$dumpvars(0, test_xgmii_baser_dec_64);
end
xgmii_baser_dec_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH (HDR_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.rx_bad_block(rx_bad_block)
);
endmodule
| 7.176683 |
module test_xgmii_baser_enc_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] xgmii_txd = 0;
reg [CTRL_WIDTH-1:0] xgmii_txc = 0;
// Outputs
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, xgmii_txd, xgmii_txc);
$to_myhdl(encoded_tx_data, encoded_tx_hdr);
// dump file
$dumpfile("test_xgmii_baser_enc_64.lxt");
$dumpvars(0, test_xgmii_baser_enc_64);
end
xgmii_baser_enc_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH (HDR_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr)
);
endmodule
| 7.176683 |
module test_xor ();
reg a, b;
wire out;
xor_gate dut (
out,
a,
b
);
initial begin
$dumpfile("test.vcd");
$dumpvars(0, test_xor);
a = 0;
b = 0;
#10;
a = 1;
b = 0;
#10;
a = 0;
b = 1;
#10;
a = 1;
b = 1;
#10;
end
endmodule
| 6.507287 |
module test_yxt_2497_7 ();
reg clk_in;
reg rst;
reg auto;
reg [13:0] Key;
wire clk_out;
wire beep;
wire [ 7:0] codeout;
wire [ 6:0] low;
wire [ 6:0] middle;
yxt_2497_3 play (
.clk_in(clk_in),
.rst(rst),
.auto(auto),
.Key(Key),
.clk_out(clk_out),
.beep(beep),
.codeout(codeout),
.low(low),
.middle(middle)
);
initial clk_in = 1;
always #500 clk_in = ~clk_in; //时钟频率1MHZ
initial begin
rst = 0;
auto = 0;
Key = 14'b0;
#(1000) rst = 1;
#(10000 * 1000);
repeat(3) //每次按下按键10ms
begin
Key = 14'b000_0000_000_0001;
#(10000 * 1000) Key = 14'b000_0000_000_0010;
#(10000 * 1000) Key = 14'b000_0000_000_0100;
#(10000 * 1000) Key = 14'b000_0000_000_1000;
#(10000 * 1000) Key = 14'b000_0000_001_0000;
#(10000 * 1000) Key = 14'b000_0000_010_0000;
#(10000 * 1000) Key = 14'b000_0000_100_0000;
#(10000 * 1000) Key = 14'b000_0001_000_0000;
#(10000 * 1000) Key = 14'b000_0010_000_0000;
#(10000 * 1000) Key = 14'b000_0100_000_0000;
#(10000 * 1000) Key = 14'b000_1000_000_0000;
#(10000 * 1000) Key = 14'b001_0000_000_0000;
#(10000 * 1000) Key = 14'b010_0000_000_0000;
#(10000 * 1000) Key = 14'b100_0000_000_0000;
end
end
endmodule
| 7.188798 |
module LFSR (
out,
clk,
rst
);
output reg [4:0] out;
input clk, rst;
wire feedback;
assign feedback = ~(out[2] ^ out[4]);
always @(posedge clk, posedge rst) begin
if (rst) out = 5'b0;
else out = {out[3:0], feedback};
end
endmodule
| 7.001839 |
module test_zet;
// Net declarations
wire [15:0] dat_o;
wire [15:0] mem_dat_i, io_dat_i, dat_i;
wire [19:1] adr;
wire we;
wire tga;
wire [ 1:0] sel;
wire stb;
wire cyc;
wire ack, mem_ack, io_ack;
wire inta;
wire [19:0] pc;
reg clk;
reg rst;
reg [15:0] io_reg;
reg intr;
// Wishbone master interface - fetch
wire [15:0] wbf_dat_i;
wire [19:1] wbf_adr_o;
wire [ 1:0] wbf_sel_o;
wire wbf_cyc_o;
wire wbf_stb_o;
wire wbf_ack_i;
// Module instantiations
memory2prt mem0 (
.wb1_clk_i(clk),
.wb1_dat_o(wbf_dat_i),
.wb1_adr_i(wbf_adr_o),
.wb1_sel_i(wbf_sel_o),
.wb1_cyc_i(wbf_cyc_o),
.wb1_stb_i(wbf_stb_o),
.wb1_ack_o(wbf_ack_i),
.wb2_clk_i(clk),
.wb2_rst_i(rst),
.wb2_dat_i(dat_o),
.wb2_dat_o(mem_dat_i),
.wb2_adr_i(adr),
.wb2_we_i (we),
.wb2_sel_i(sel),
.wb2_stb_i(stb & !tga),
.wb2_cyc_i(cyc & !tga),
.wb2_ack_o(mem_ack)
);
zet zet (
.clk_i(clk),
.rst_i(rst),
// Wishbone master interface - fetch
.wbf_dat_i(wbf_dat_i),
.wbf_adr_o(wbf_adr_o),
.wbf_sel_o(wbf_sel_o),
.wbf_cyc_o(wbf_cyc_o),
.wbf_stb_o(wbf_stb_o),
.wbf_ack_i(wbf_ack_i),
.wb_dat_i(dat_i),
.wb_dat_o(dat_o),
.wb_adr_o(adr),
.wb_we_o (we),
.wb_tga_o(tga),
.wb_sel_o(sel),
.wb_stb_o(stb),
.wb_cyc_o(cyc),
.wb_ack_i(ack),
.intr(1'b0),
.inta(inta),
.iid (4'h0),
.pc(pc)
);
// Assignments
assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }
: ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);
assign dat_i = inta ? 16'd3 : (tga ? io_dat_i : mem_dat_i);
assign ack = tga ? io_ack : mem_ack;
assign io_ack = stb;
// Behaviour
// IO Stub
always @(posedge clk)
if (adr[15:1] == 15'h5b && sel[1] && cyc && stb) io_reg[7:0] <= dat_o[15:8];
else if (adr[15:1] == 15'h5c & sel[0] && cyc && stb) io_reg[15:8] <= dat_o[7:0];
always #1.5 clk = ~clk;
initial begin
intr <= 1'b0;
clk <= 1'b1;
rst <= 1'b0;
#5 rst <= 1'b1;
#2 rst <= 1'b0;
#1000 intr <= 1'b1;
//@(posedge inta)
@(posedge clk) intr <= 1'b0;
end
initial begin
$readmemh("data.rtlrom", mem0.ram1, 19'h78000);
$readmemh("data.rtlrom", mem0.ram2, 19'h78000);
// $readmemb("../rtl/micro_rom.dat",
// zet.core.micro_data.micro_rom.rom);
end
endmodule
| 7.145266 |
module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Tes_add;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UUT)
qadd #(19,32) uut (
.a(a),
.b(b),
.c(c)
);
// These are to monitor the values...
wire [30:0] c_out;
wire [30:0] a_in;
wire [30:0] b_in;
wire a_sign;
wire b_sign;
wire c_sign;
assign a_in = a[30:0];
assign b_in = b[30:0];
assign c_out = c[30:0];
assign a_sign = a[31];
assign b_sign = b[31];
assign c_sign = c[31];
initial begin
// Initialize Inputs
a[30:0] = 0;
a[31] = 0;
b[31] = 1;
b[30:0] = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 a = a+5179347; // why not?
a[31] = 0; // a is negative...
b[31] = 1;
if (a[30:0] > 2.1E9) // input will always be "positive"
begin
a = 0;
b[31] = 1; // b is negative...
b[30:0] = b[30:0] + 3779351;
end
end
end
endmodule
| 7.550078 |
module divfreq (
input CLK,
output reg CLK_div,
output reg CLK_Hz10
); //時脈
reg [30:0] Hz10_Count;
reg [19:0] CLK_Count;
always @(posedge CLK) begin
if (CLK_Count > 10000) begin
CLK_Count <= 0;
CLK_div <= ~CLK_div;
end else CLK_Count <= CLK_Count + 1'b1;
if (Hz10_Count > 2499999) begin
CLK_Hz10 <= ~CLK_Hz10;
Hz10_Count <= 0;
end else Hz10_Count <= Hz10_Count + 1'b1;
end
endmodule
| 6.846501 |
module JIZLOTS_sel(input[2:0] type, input[1:0] rot, output reg[0:15] block);
wire[0:15] block_t, block_z, block_s, block_j, block_l, block_o, block_i;
T_sel t(rot, block_t);
Z_sel z(rot, block_z);
S_sel s(rot, block_s);
J_sel j(rot, block_j);
L_sel l(rot, block_l);
O_sel o(rot, block_o);
I_sel i(rot, block_i);
always @*
begin
case(type)
0: block = block_t;
1: block = block_z;
2: block = block_s;
3: block = block_j;
4: block = block_l;
5: block = block_o;
6: block = block_i;
default: block = 0; //shouldn't happen
endcase
end
endmodule
| 6.673376 |
module T_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] t0 = 16'b1110010000000000;
wire [0:15] t1 = 16'b0010011000100000;
wire [0:15] t2 = 16'b0000010011100000;
wire [0:15] t3 = 16'b1000110010000000;
always @* begin
case (rot)
0: block = t0;
1: block = t1;
2: block = t2;
3: block = t3;
default: block = t0;
endcase
end
endmodule
| 7.316494 |
module Z_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] z0 = 16'b1100011000000000;
wire [0:15] z1 = 16'b0010011001000000;
wire [0:15] z2 = 16'b0000110001100000;
wire [0:15] z3 = 16'b0100110010000000;
always @* begin
case (rot)
0: block = z0;
1: block = z1;
2: block = z2;
3: block = z3;
default: block = z0;
endcase
end
endmodule
| 7.190765 |
module S_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] s0 = 16'b0110110000000000;
wire [0:15] s1 = 16'b0100011000100000;
wire [0:15] s2 = 16'b0000011011000000;
wire [0:15] s3 = 16'b1000110001000000;
always @* begin
case (rot)
0: block = s0;
1: block = s1;
2: block = s2;
3: block = s3;
default: block = s0;
endcase
end
endmodule
| 6.90364 |
module J_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] j0 = 16'b0100010011000000;
wire [0:15] j1 = 16'b1000111000000000;
wire [0:15] j2 = 16'b0110010001000000;
wire [0:15] j3 = 16'b0000111000100000;
always @* begin
case (rot)
0: block = j0;
1: block = j1;
2: block = j2;
3: block = j3;
default: block = j0;
endcase
end
endmodule
| 7.501091 |
module L_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] l0 = 16'b0100010011000000;
wire [0:15] l1 = 16'b0000111010000000;
wire [0:15] l2 = 16'b1100010001000000;
wire [0:15] l3 = 16'b0010111000000000;
always @* begin
case (rot)
0: block = l0;
1: block = l1;
2: block = l2;
3: block = l3;
default: block = l0;
endcase
end
endmodule
| 7.330394 |
module O_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] o0 = 16'b1100110000000000;
always @* begin
case (rot)
default: block = o0;
endcase
end
endmodule
| 7.929439 |
module I_sel (
input [1:0] rot,
output reg [0:15] block
);
wire [0:15] i0 = 16'b1000100010001000;
wire [0:15] i1 = 16'b0000000011110000;
always @* begin
case (rot)
0: block = i0;
1: block = i1;
2: block = i0;
3: block = i1;
default: block = i0;
endcase
end
endmodule
| 6.906223 |
module Tetris_tb ();
reg clk, rstn, ps2clk, ps2data;
wire pwm;
Tetris Tetris (
.clk(clk),
.rstn(rstn),
.pwm(pwm),
.PS2_CLK(ps2clk),
.PS2_DATA(ps2data)
);
initial begin
clk = 0;
rstn = 1;
ps2clk <= 1;
ps2data <= 1;
#0.1 rstn = 0;
#0.1 rstn = 1;
#1 #0.1 ps2data <= 0;
#0.1 ps2clk <= ~ps2clk;
// #0.1 ps2data<=0;ps2clk <= ~ps2clk;
// #0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 0;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 0;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 0;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 1;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 1;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 1;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 0;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 1;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 1;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 1;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#0.1 ps2data <= 0;
ps2clk <= ~ps2clk;
#0.1 ps2clk <= ~ps2clk;
#1 $finish;
end
always #0.01 clk <= ~clk;
// always #0.1 ps2clk <= ~ps2clk;
endmodule
| 7.263495 |
module tetris_tester (
input CLK,
input [4:0] BTN, // CENTER, DOWN, RIGHT, LEFT, UP
input [15:0] SW, // LEFT : RIGHT
input UART_RX, // See Ref. Page 7
output UART_TX, // See Ref. Page 7
output [7:0] SSEG_CA, // See Ref. Page 15
output [3:0] SSEG_AN, // See Ref. Page 15
output [15:0] LED, // LEFT : RIGHT
//output [3:0]VGA_RED, // See Ref. Page 10
//output [3:0]VGA_GREEN, // See Ref. Page 10
//output [3:0]VGA_BLUE, // See Ref. Page 10
//output VGA_HS, // See Ref. Page 10
//output VGA_VS, // See Ref. Page 10
input [7:0] JA, // See Ref. Page 17
output [7:0] JB, // See Ref. Page 17
inout [7:0] JC // See Ref. Page 17
//inout [7:0]JXADC // // See Ref. Page 17/18
);
parameter PANEL_WIDTH = 32;
parameter PANEL_HEIGHT = 32;
parameter PIXEL_COLOR_BITS = 8;
parameter PIXEL_COLOR_CHANNELS = 3;
parameter PIXEL_COUNT = PANEL_WIDTH * PANEL_HEIGHT;
parameter PIXEL_NUM_BITS = PIXEL_COLOR_BITS * PIXEL_COLOR_CHANNELS;
parameter BUFFER_ADDR_BITS = $clog2(PIXEL_COUNT);
parameter DATA_BITS = 8;
wire RESET;
assign RESET = BTN[4];
wire [BUFFER_ADDR_BITS-1:0] buf_read_addr_0;
wire [PIXEL_NUM_BITS-1:0] buf_read_data_0;
wire [BUFFER_ADDR_BITS-1:0] buf_read_addr_1;
wire [PIXEL_NUM_BITS-1:0] buf_read_data_1;
wire [BUFFER_ADDR_BITS-1:0] buf_write_addr;
wire [PIXEL_NUM_BITS-1:0] buf_write_data;
wire buf_write_signal;
wire serial_data_rx_ready_signal;
wire [DATA_BITS-1:0] serial_data_rx;
wire [1:0] buffer_select;
wire gpu_working_status_w;
wire gpu_command_start_signal_w;
wire [3:0] gpu_command_w;
wire [7:0] gpu_spr_select_w;
wire [63:0] gpu_data_w;
assign LED[7:0] = serial_data_rx;
assign LED[8] = gpu_command_start_signal_w;
assign LED[12:9] = gpu_command_w;
assign LED[15] = ~serial_data_rx_ready_signal;
assign LED[14] = gpu_working_status_w;
//wire clk_buffer_manager;
//clk_divider #(.CLK_OUT_FREQ(25_000_000)) clk_div0(CLK, clk_buffer_manager);
//wire clk_gpu;
//clk_divider #(.CLK_OUT_FREQ(25_000_000)) clk_div1(CLK, clk_gpu);
serial_rx s_rx0 (
CLK,
RESET,
JC[1],
serial_data_rx,
serial_data_rx_ready_signal
); //input from Arduino
buffer_manager #(
.DATA_SIZE (PIXEL_NUM_BITS),
.BUFFER_SIZE(PIXEL_COUNT)
) bm0 (
CLK,
buffer_select,
buf_write_addr,
buf_write_data,
buf_write_signal,
buf_read_addr_0,
buf_read_data_0,
buf_read_addr_1,
buf_read_data_1
);
panel p0 (
CLK,
buf_read_data_0,
buf_read_addr_0,
buf_read_data_1,
buf_read_addr_1,
JB[0],
JB[1]
);
serial_protocol_decoder dec0 (
serial_data_rx,
serial_data_rx_ready_signal,
gpu_working_status_w,
buffer_select,
gpu_command_start_signal_w,
gpu_command_w,
gpu_spr_select_w,
gpu_data_w
);
gpu gpu0 (
CLK,
gpu_command_start_signal_w,
gpu_command_w,
gpu_spr_select_w,
gpu_data_w,
buf_write_signal,
buf_write_addr,
buf_write_data,
gpu_working_status_w
);
wire [4:0] buttons_debounced_w;
genvar i;
generate
for (i = 0; i < 5; i = i + 1) begin : buttons_debounce_gen
button_debounce db (
CLK,
BTN[i],
buttons_debounced_w[i]
);
end
endgenerate
wire clk_input_handler_internal;
clk_divider #(
.CLK_OUT_FREQ(10_000)
) clk_div_input (
CLK,
clk_input_handler_internal
);
wire [DATA_BITS-1:0] input_handler_data_out_w;
wire input_handler_ready_signal_out_w;
input_handler ih0 (
clk_input_handler_internal,
buttons_debounced_w,
SW[15:0],
JA[7:0],
input_handler_data_out_w,
input_handler_ready_signal_out_w
);
serial_tx s_tx0 (
CLK,
RESET,
JC[0],
input_handler_data_out_w,
input_handler_ready_signal_out_w
); //input_handler output to Arduino
endmodule
| 8.213129 |
module sync_gen (
input clk,
output h_sync,
output v_sync,
output blank,
input gfx_clk,
output [9:0] x,
output [9:0] y,
input rst
);
reg [9:0] hcount, vcount;
assign h_sync = hcount < 96 ? 1'b0 : 1'b1;
assign v_sync = vcount < 2 ? 1'b0 : 1'b1;
assign blank = h_sync & v_sync;
assign x = hcount - 10'd144; //Pulse length + back porch
assign y = vcount - 10'd34;
always @(posedge gfx_clk) begin
if (hcount < 800) hcount <= hcount + 10'd1;
else begin
hcount <= 0;
vcount <= vcount + 10'd1;
end
if (vcount == 525) vcount <= 0;
if (rst) begin
hcount <= 0;
vcount <= 0;
end
end
endmodule
| 7.042061 |
module textbox (
input wire pclk,
input wire rst,
input wire hblnk_in,
input wire [10:0] hcount_in,
input wire hsync_in,
input wire [3:0] level,
input wire [10:0] vcount_in,
input wire vsync_in,
input wire vblnk_in,
input wire [3:0] dead_count_1,
input wire [3:0] dead_count_2,
input wire [11:0] rgb_in,
output wire vsync_out,
output wire hsync_out,
output wire [11:0] rgb_out
);
wire [10:0] vcount_ch, hcount_ch;
wire [11:0] rgb_ch;
wire vsync_ch, hsync_ch;
wire vblnk_ch, hblnk_ch;
wire [7:0] char_pixels;
wire [7:0] char_xy;
wire [3:0] char_line;
wire [10:0] vcount_2, hcount_2;
wire [11:0] rgb_2;
wire vsync_2, hsync_2;
wire vblnk_2, hblnk_2;
wire [7:0] char_pixels_2;
wire [7:0] char_xy_2;
wire [3:0] char_line_2;
draw_rect_char my_draw_rect_char (
.rst(rst),
.pclk(pclk),
.rgb_in(rgb_in),
.char_pixels(char_pixels),
.hcount_in(hcount_in),
.vcount_in(vcount_in),
.hblnk_in (hblnk_in),
.vblnk_in (vblnk_in),
.hsync_in (hsync_in),
.vsync_in (vsync_in),
.hcount_out(hcount_2),
.vcount_out(vcount_2),
.hblnk_out(hblnk_2),
.vblnk_out(vblnk_2),
.hsync_out(hsync_2),
.vsync_out(vsync_2),
.rgb_out(rgb_2),
.char_xy (char_xy),
.char_line(char_line)
);
wire [6:0] char_code;
char_rom_16x16 my_char_rom_16x16 (
.level(level),
.char_xy(char_xy),
.char_code(char_code)
);
font_rom my_font_rom (
.clk(pclk),
.rst(rst),
.addr({char_code, char_line}),
.char_line_pixels(char_pixels)
);
draw_rect_game_over my_draw_rect_game_over (
.rst(rst),
.pclk(pclk),
.rgb_in(rgb_2),
.char_pixels(char_pixels_2),
.hcount_in(hcount_2),
.vcount_in(vcount_2),
.hblnk_in(hblnk_2),
.vblnk_in(vblnk_2),
.hsync_in(hsync_2),
.vsync_in(vsync_2),
.dead_count_1(dead_count_1),
.dead_count_2(dead_count_2),
.hcount_out(hcount_ch),
.vcount_out(vcount_ch),
.hblnk_out (hblnk_ch),
.vblnk_out (vblnk_ch),
.hsync_out (hsync_ch),
.vsync_out (vsync_ch),
.rgb_out (rgb_ch),
.char_xy (char_xy_2),
.char_line(char_line_2)
);
wire [6:0] char_code_2;
char_rom_game_over my_char_rom_game_over (
.char_xy (char_xy_2),
.char_code(char_code_2)
);
font_rom my_font_rom_game_over (
.clk(pclk),
.rst(rst),
.addr({char_code_2, char_line_2}),
.char_line_pixels(char_pixels_2)
);
assign vsync_out = vsync_ch;
assign hsync_out = hsync_ch;
assign rgb_out = rgb_ch;
endmodule
| 8.168478 |
module textdrv (
input clk_i,
input rst_i,
input vga_clock,
input [31:0] cursorpos,
input [3:0] cursormode,
input [15:0] x,
input [15:0] y,
output [7:0] r,
output [7:0] g,
output [7:0] b,
output cyc_o,
output [31:0] adr_o,
input [31:0] dat_i,
input ack_i
);
wire [95:0] fontval;
wire [31:0] char;
wire [95:0] font0_out, font1_out;
wire [31:0] buf_out;
wire [15:0] scanaddr;
wire [15:0] textrow, textcol;
wire [7:0] color0, color1;
wire oncursor;
logic [1:0] state, state_next;
logic [9:0] idx, idx_next;
logic [31:0] rowval, rowval_next;
logic [15:0] x_sync[2:0];
logic [15:0] y_sync[2:0];
logic [31:0] font_idx, font_idx_next;
logic [25:0] blink;
localparam [1:0] STATE_IDLE = 2'h0, STATE_BUS = 2'h1, STATE_FONT = 2'h2, STATE_STORE = 2'h3;
assign cyc_o = (state == STATE_BUS);
assign scanaddr = x + 1'b1;
assign textrow = {3'h0, y[15:3]};
assign textcol = {3'h0, x[15:3]};
assign oncursor = ({textrow,textcol} == cursorpos) && ((blink[25] & cursormode[3:0] == 4'h1) || (cursormode[3:0] == 4'h2));
// break out the rows of the font elements
always_comb begin
case (y[2:0])
'h7: char = {color0, color1, font0_out[39:32], font1_out[39:32]};
'h6: char = {color0, color1, font0_out[47:40], font1_out[47:40]};
'h5: char = {color0, color1, font0_out[55:48], font1_out[55:48]};
'h4: char = {color0, color1, font0_out[63:56], font1_out[63:56]};
'h3: char = {color0, color1, font0_out[71:64], font1_out[71:64]};
'h2: char = {color0, color1, font0_out[79:72], font1_out[79:72]};
'h1: char = {color0, color1, font0_out[87:80], font1_out[87:80]};
'h0: char = {color0, color1, font0_out[95:88], font1_out[95:88]};
default: char = 16'h0;
endcase
end
wire [7:0] red, green, blue;
assign red = (x[3] ? {buf_out[23:22], 6'h0} : {buf_out[31:30], 6'h0});
assign green = (x[3] ? {buf_out[21:19], 5'h0} : {buf_out[29:27], 5'h0});
assign blue = (x[3] ? {buf_out[18:16], 5'h0} : {buf_out[26:24], 5'h0});
assign {r, g, b} = (buf_out[4'hf-x[3:0]] || oncursor ? {red, green, blue} : 24'h000000);
always @(posedge clk_i) begin
x_sync[2] <= x_sync[1];
x_sync[1] <= x_sync[0];
x_sync[0] <= x;
y_sync[2] <= y_sync[1];
y_sync[1] <= y_sync[0];
y_sync[0] <= y;
end
// Master state machine
always @(posedge clk_i or posedge rst_i) begin
if (rst_i) begin
state <= STATE_IDLE;
idx <= 10'h0;
rowval <= 32'h0;
font_idx <= 32'h0;
blink <= 25'h0;
end else begin
idx <= idx_next;
state <= state_next;
rowval <= rowval_next;
font_idx <= font_idx_next;
blink <= blink + 1'h1;
end
end
always_comb begin
state_next = state;
idx_next = idx;
rowval_next = rowval;
font_idx_next = font_idx;
adr_o = 32'h0;
case (state)
STATE_IDLE: begin
if (y_sync[2] != y_sync[1]) begin
state_next = STATE_BUS;
end
end
STATE_BUS: begin
adr_o = rowval + idx;
if (ack_i) begin
state_next = STATE_FONT;
font_idx_next = dat_i;
end
end
STATE_FONT: state_next = STATE_STORE;
STATE_STORE: begin
if (idx < 11'd160) begin
state_next = STATE_BUS;
idx_next = idx + 10'd4;
end else begin
idx_next = 10'd0;
if (y_sync[1] == 16'd479) rowval_next = 32'h0;
else if (y_sync[1][2:0] == 16'h7) rowval_next = rowval + 10'd160;
state_next = STATE_IDLE;
end
end
endcase
end
assign color0 = font_idx[31:24];
fontmem font0 (
.clock(clk_i),
.address(font_idx[22:16]),
.q(font0_out)
);
assign color1 = font_idx[15:8];
fontmem font1 (
.clock(clk_i),
.address(font_idx[6:0]),
.q(font1_out)
);
textlinebuf linebuf0 (
.wrclock(clk_i),
.wraddress(idx[9:2]),
.wren(state == STATE_STORE),
.data(char),
.rdclock(vga_clock),
.rdaddress(scanaddr[11:4]),
.q(buf_out)
);
endmodule
| 8.098516 |
module: SingleCycleCPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TextFile;
// Instantiate the Unit Under Test (UUT)
SingleCycleCPU uut (clk, Extsel, PCWre, InsMemRW, RegOut,
RegWre, ALUSrcB, ALUM2Reg, PCSrc, DataMemRW, ALUOp, _instruction,
_PcOut, _PcIn, _zero, _extendOut, _thirdRg, _RgData1, _RgData2,
_WriteData, _ALUResult, _DataOut, _PcIndect);
reg clk;
wire Extsel, PCWre, InsMemRW, RegOut,
RegWre, ALUSrcB, ALUM2Reg, PCSrc, DataMemRW;
wire [2:0] ALUOp;
// 中间数据
wire [31:0]_instruction;
wire [31:0]_PcOut;
wire [31:0]_PcIn;
wire _zero;
wire [31:0]_extendOut;
wire [4:0]_thirdRg;
wire [31:0]_RgData1;
wire [31:0]_RgData2;
wire [31:0]_WriteData;
wire [31:0]_ALUResult;
wire [31:0]_DataOut;
wire [31:0]_PcIndect;
initial begin
clk = 1;
// Initialize Inputs
#20
clk = 1'b1;
forever #20 clk = !clk;
// Wait 100 ns for global reset to finish
#600 $stop;
// Add stimulus here
end
endmodule
| 6.674631 |
module textgen_8x8 (
input clk_i,
input [7:0] chr_ord_i, // character number (8bit, 0~256)
input [2:0] cell_col_i, // cell column (0~7)
input [2:0] cell_lin_i, // cell line (0~7)
output px_o // pixel is on or off
);
wire vcc = 1'b1;
wire gnd = 1'b0;
reg [7:0] chrline = 0;
wire [7:0] rom_output;
wire [10:0] chrrom_addr; // 7bit + 3bit
assign chrrom_addr = {chr_ord_i, cell_lin_i};
// 8x8 fixed font character generator
chr_rom chr_rom (
.oce (vcc), //
.ce (vcc), //
.reset(gnd), // reset
.dout (rom_output), // data output [7:0]
.clk (clk_i), // clock
.ad (chrrom_addr) // address line [9:0]
);
// Cycle:
// 0: text position updated
// text position -> vram address
// 1: vram address -> vram output
// vram output -> character
// character + cell line -> rom address
// 2: rom address -> rom output
// 3: rom output -> character line
always @(posedge clk_i) begin
if (cell_col_i == 3'd3) chrline <= rom_output;
else chrline <= {chrline[6:0], gnd};
end
// left pixel is most significant bit but columns start by 0
// Cannot use a shift register because one clock is not one cell pixel
assign px_o = chrline[7];
endmodule
| 7.49105 |
module textlcd_tb;
//input
reg RESETN, CLK;
//output
wire LCD_RW, LCD_RS, LCD_E;
wire [7:0] LCD_DATA;
textlcdforSLOT U1 (
RESETN,
CLK,
LCD_E,
LCD_RS,
LCD_RW,
LCD_DATA
);
initial begin
RESETN = 1;
CLK = 0;
#5 RESETN = 0;
end
endmodule
| 6.589122 |
module textlinebuf (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [31:0] data;
input [7:0] rdaddress;
input rdclock;
input [7:0] wraddress;
input wrclock;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (wrclock),
.clock1 (rdclock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV GX",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
| 6.573833 |
module TextMemory #( //width of data bus
parameter TEXT_ADDR_WIDTH = 'h800,
parameter ADDR_WIDTH = 12 //width of addresses buses
) (
//input CLK,
input [(ADDR_WIDTH-1):0] R_ADDR, //address for write/read operation
output reg [ (32-1):0] DOUT //read data
);
//! Internal memory instantation
reg [(32-1):0] rom[2**ADDR_WIDTH-1:0];
initial begin
//$display(ramN);
$readmemh("../../firmware/build/output/text.txt", rom, TEXT_ADDR_WIDTH[ADDR_WIDTH:2]);
$dumpfile("PPCSoC_tb.vcd");
//for (idx = 0; idx < 10; idx = idx + 1) $dumpvars(0, mem[idx]);
end
//The Lattice FPGA i am using can't generate 32-bits wide BRAM
//assign DOUT = rom[R_ADDR];
always @(*) begin
DOUT = rom[R_ADDR];
end
endmodule
| 8.477673 |
module textmode(clk, ce, vsync, hsync, pixel, background, address, data, wren, q,
// debug stuff
linebegin, textaddr, loadchar, tileaddr, tile_y, tileline, pixelreg);
input clk;
input ce;
input vsync;
input hsync;
output pixel = background & pixxel;
output background;
input [`LOG2TXT-1:0] address;
input [7:0] data;
input wren;
output[7:0] q;
// stuff for debug
output linebegin;
output[7:0] textaddr;
output loadchar;
output[9:0] tileaddr;
output[2:0] tile_y;
output[`TILE_W-1:0] tileline;
output [`TILE_W-1:0] pixelreg;
wire [2:0] tile_y;
wire loadchar;
wire [`LOG2TXT-1:0] textaddr;
reg [`TILE_W-1:0] pixelreg;
reg pixxel;
textmode_counter tcu(
.clk(clk),
.ce(ce),
.linebegin(~hsync),
.framebegin(~vsync),
.tile_y(tile_y),
.loadchar(loadchar),
.textaddr(textaddr),
.video_enable(background)
);
wire [7:0] charcode;
screenbuffer ram0(
.clock(clk),
.data_b(data),
.address_a(textaddr),
.address_b(address),
.wren_b(wren),
.q_a(charcode),
.q_b(q));
wire invert = charcode[7];
wire [9:0] tileaddr = tile_y != (`TILE_H-1) ? {charcode[6:0], 3'b000} - charcode[6:0] + tile_y : 10'b0;
wire [`TILE_W-2:0] tileline;
// character rom is 512x5, 8 quintets per tile, 64 tiles total
chargen chrom0(
.address(tileaddr),
.clock(clk),
.q(tileline));
wire [`TILE_W-1:0] poxels = loadchar ? {invert,(invert ? ~tileline : tileline)} : {pixelreg[`TILE_W-2:0],1'b0};
always @(posedge clk) begin
if (ce) begin
pixelreg <= poxels;
pixxel <= pixelreg[`TILE_W-1];
end
end
endmodule
| 6.532894 |
module texto (
index,
ascii_code
);
input [3:0] index;
output reg [7:0] ascii_code;
always @(*) begin
ascii_code = 8'h00;
case (index)
4'h0: ascii_code = 8'h41; // A
4'h1: ascii_code = 8'h6c; // l
4'h2: ascii_code = 8'h65; // e
4'h3: ascii_code = 8'h78; // x
4'h4: ascii_code = 8'h21; // !
default: ascii_code = 8'h00;
endcase
end
endmodule
| 7.107614 |
module Texto_tb(
);
<<<<<<< HEAD
reg [9:0] Qh_tb;
reg [9:0] Qv_tb;
wire BIT_FUENTEtb;
=======
reg [9:0] Qh_tb;// = 10'b0000000000;
reg [9:0] Qv_tb;// = 9'b000000000;
wire BIT_FUENTEtb,ANDD1,ANDD2,ORD,ANDJ,ANDV;
>>>>>>> 577cc9a1689b628be444f2603bb3fba1a29a7b4d
reg reloj_tb;
reg resetH =1'b0;
integer i=0,j=0;
parameter PERIOD = 10;
Posicion_Mosaicos inst_Mosaico(
<<<<<<< HEAD
.Qv(Qv_tb),.Qh(Qh_tb),.resetM(resetH),.reloj(reloj_tb),
=======
.Qv(Qv_tb),.Qh(Qh_tb),.reloj(reloj_tb),
>>>>>>> 577cc9a1689b628be444f2603bb3fba1a29a7b4d
.wire_BIT_FUENTE(BIT_FUENTEtb)
);
initial
begin
reloj_tb=0;
Qh_tb= 10'b0000000000;
Qv_tb=10'b0000000000;
forever begin
for (i=0;i<525;i=i+1)
begin
for (j=0;j<800;j=j+1)
begin
#40 Qh_tb = Qh_tb + 10'd1;
end
if (Qh_tb == 10'd800)
begin
Qh_tb= 10'd0;
Qv_tb=Qv_tb+10'd1;
end
if (Qv_tb == 10'd525)
Qv_tb = 10'd0;
end
end
end
always
begin
#5 reloj_tb = ~reloj_tb;
end
endmodule
| 7.302459 |
module TextPC4 (
clk,
clrn,
wpcir,
pc,
pc4
);
input clk, clrn, wpcir;
output [31:0] pc;
output [31:0] pc4;
//reg [31:0] pc4;
pipepc pcreg (
pc4,
wpcir,
clk,
clrn,
pc
);
cla32 pc_plus4 (
pc,
32'h4,
1'b0,
pc4
);
endmodule
| 7.117047 |
module TextRam (
aclr_a,
aclr_b,
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input aclr_a;
input aclr_b;
input [5:0] address_a;
input [5:0] address_b;
input clock_a;
input clock_b;
input [2559:0] data_a;
input [2559:0] data_b;
input wren_a;
input wren_b;
output [2559:0] q_a;
output [2559:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr_a;
tri0 aclr_b;
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2559:0] sub_wire0;
wire [2559:0] sub_wire1;
wire [2559:0] q_a = sub_wire0[2559:0];
wire [2559:0] q_b = sub_wire1[2559:0];
altsyncram altsyncram_component (
.aclr0 (aclr_a),
.aclr1 (aclr_b),
.address_a (address_a),
.address_b (address_b),
.clock0 (clock_a),
.clock1 (clock_b),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.init_file = "./src/storage/TextRamMiSTer.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 40,
altsyncram_component.numwords_b = 40,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "CLEAR0",
altsyncram_component.outdata_aclr_b = "CLEAR1",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 2560,
altsyncram_component.width_b = 2560,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
| 6.749353 |
module textRenderer (
output [11:0] rgb,
input [31:0] x,
input [31:0] y,
input clk
);
wire member1, member2, member3, member4, member5, anykey;
Pixel_On_Text2 #(
.displayText("6031033521 Nisaruj Rattanaaram")
) t1 (
clk,
200,
100,
x,
y,
member1
);
Pixel_On_Text2 #(
.displayText("6031057621 Sorawit Sunthawatrodom")
) t2 (
clk,
200,
150,
x,
y,
member2
);
Pixel_On_Text2 #(
.displayText("6031044421 Pawat Amornpitakpun")
) t3 (
clk,
200,
200,
x,
y,
member3
);
Pixel_On_Text2 #(
.displayText("6030559121 Siwat Pongpanit")
) t4 (
clk,
200,
250,
x,
y,
member4
);
Pixel_On_Text2 #(
.displayText("6030064821 Khanisorn Khemthong")
) t5 (
clk,
200,
300,
x,
y,
member5
);
Pixel_On_Text2 #(
.displayText("Press any key to continue...")
) t6 (
clk,
200,
350,
x,
y,
anykey
);
assign rgb = (member1 || member2 || member3 || member4 || member5 || anykey) ? 12'hFFF : 12'h000;
endmodule
| 6.732481 |
module texture_memory (
input clk,
wen,
ren,
input [11:0] waddr,
raddr,
input [2:0] wdata,
output reg [2:0] rdata
);
reg [2:0] mem [0:4095]; // enough memory for 64 8x8 texture tiles @ 3bpp // uses 4/32 BRAMS of Ice40
always @(posedge clk) begin
if (ren) rdata <= mem[raddr];
if (wen) mem[waddr] <= wdata;
end
endmodule
| 6.850403 |
module texture_rom (
input clk,
input [5:0] texture_idx,
input [2:0] y_idx,
input [2:0] x_idx,
output reg [2:0] val
);
reg [2:0] TEXTURE_ROM[0:4095]; /* 16 x (32 x 32 x 4bpp) textures */
initial $readmemh("textures.mem", TEXTURE_ROM);
// the indexing below is a little bit complicated, but is because our
// texture image is 64x64 pixels, split into 8x8 textures. I'm fairly
// confident the math works out. :D
always @(posedge clk) begin
val <= TEXTURE_ROM[{texture_idx[5:3], y_idx, texture_idx[2:0], x_idx}];
end
endmodule
| 8.165941 |
module text_display
#(parameter COLOR=24'hFF_FF_FF, WIDTH=31, HEIGHT=31, READ_WIDTH=31)
(input wire [10:0] x, hcount,input wire [9:0] y, vcount,
input wire [5:0] alphabet_num,input wire clk, output reg [23:0] pixel);
// alphabet_num is a number in [1,26] representing A-Z, [27,52] a-z, [53,62] 0-9
wire [10:0] address;
wire [10:0] x_index;
wire in_x_range, in_y_range;
wire [READ_WIDTH-1:0] dout; // dout2,dout3,dout4;
letters let(.clka(clk), .addra(address), .douta(dout));
assign in_y_range = (vcount >= y) && (vcount < y+HEIGHT);
assign in_x_range = (hcount >= x) && (hcount < x+WIDTH);
assign address = (vcount-y+1) + ((alphabet_num-1)*HEIGHT);
assign x_index = (x-hcount+1);
always @ (posedge clk) begin
if (in_x_range && in_y_range) begin
// read from rom to fill the color
pixel <= dout[x_index] ? COLOR : 0;
end
else pixel <= 0;
end
endmodule
| 6.604801 |
module text_editor_keyboard_controller (
input sys_Clk,
input PS2_Clk,
input Reset,
inout PS2KeyboardData,
inout PS2KeyboardClk,
output reg [7:0] KeyData,
output reg KeyReleased
);
/************************************************************************
* LOCAL SIGNALS *
************************************************************************/
reg [1:0] state;
localparam I = 2'b00, BAT = 2'b01, DATA = 2'b10, UNK = 2'bXX;
wire [7:0] received_data;
wire received_data_en;
reg [7:0] previous_word;
reg send_command;
reg [7:0] the_command;
wire command_sent;
/************************************************************************
* PS2 KEYBOARD *
************************************************************************/
PS2_Controller PS2_Keyboard_Controller (
// Inputs
.CLOCK_50(PS2_Clk),
.reset(Reset),
.the_command(the_command),
.send_command(send_command),
// Bidirectionals
.PS2_CLK(PS2KeyboardClk), // PS2 Clock
.PS2_DAT(PS2KeyboardData), // PS2 Data
// Outputs
.command_was_sent(command_sent),
.error_communication_timed_out(),
.received_data(received_data),
.received_data_en(received_data_en) // If 1 - new data has been received
);
/************************************************************************
* STATE MACHINE *
************************************************************************/
always @(posedge sys_Clk, posedge Reset) begin : STATE_MACHINE
if (Reset) begin
state <= I;
previous_word <= 8'hXX;
send_command <= 1'bX;
the_command <= 8'hXX;
KeyData <= 8'hXX;
end else
case (state)
I: begin
state <= BAT;
KeyData <= 8'h00;
previous_word <= 8'h00;
KeyReleased <= 1'b0;
send_command <= 1'b1;
the_command <= 8'hFF; // RESET KEYBOARD
end
BAT: begin
if (command_sent) begin
send_command <= 1'b0;
end
case (received_data)
8'hAA: begin // SUCCESSFUL POST
state <= DATA;
end
8'hFC: begin
send_command <= 1'b1; // TRY TO POST AGAIN
end
default: begin
end
endcase
end
DATA: begin
if (command_sent) begin
send_command <= 1'b0;
end
if (KeyReleased) begin
KeyReleased <= 1'b0;
end
if (received_data_en) begin
previous_word <= received_data;
case (received_data)
8'hF0: begin
// Key Released
end
8'hFA: begin
// Acknowledge
end
8'hAA: begin
// Self Test Passed
end
8'hEE: begin
// Echo Response
end
8'hFE: begin
// Resend Request
end
8'h00: begin
// Error
end
8'hFF: begin
// Error
end
8'h12: begin
// Shift
end
8'h59: begin
// Shift
end
8'h58: begin
// Caps
end
8'h0D: begin
// Tab
end
8'h14: begin
// Ctrl
end
8'h11: begin
// Alt
end
8'hE0: begin
// Extra
end
8'h5A: begin
// Enter
end
default: begin
if (previous_word == 8'hF0) begin // IF PREV WORD WAS KEY RELEASED SCAN CODE
KeyData <= received_data;
KeyReleased <= 1'b1;
end
end
endcase
end
end
default: state <= UNK;
endcase
end
endmodule
| 8.826465 |
module text_editor_RAM (
input clk,
input Reset,
input write,
input [ADDR_WIDTH-1:0] write_address,
input [DATA_WIDTH-1:0] write_data,
input [ADDR_WIDTH-1:0] read_address,
output [DATA_WIDTH-1:0] read_data
);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 9;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
reg [DATA_WIDTH-1:0] data[0:RAM_DEPTH-1]; // Array to store 512 8-bit words (characters)
always @(posedge clk, posedge Reset) begin : RAM_logic
if (Reset) begin : Reset
integer i;
for (i = 0; i < RAM_DEPTH; i = i + 1) begin
data[i] <= 8'h29; // a "Space"
end
end else if (write) begin
data[write_address] <= write_data;
end
end
assign read_data = data[read_address];
endmodule
| 6.821493 |
module text_font (
input wire clk,
input wire [2:0] sw,
input wire [9:0] pix_x,
pix_y,
output wire text_on,
output reg [7:0] text_rgb
);
// declaracion de seales
reg [ 7:0] color_word;
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_l;
reg [3:0] row_addr;
wire [3:0] row_addr_l;
reg [2:0] bit_addr;
wire [2:0] bit_addr_l;
wire [7:0] font_word;
wire font_bit;
// instancia de font ROM
font_rom font_unit (
.clk (clk),
.addr(rom_addr),
.data(font_word)
);
// region letras:
// - desplega palabra "RCMV" centrada
//-------------------------------------------
assign text_on = (pix_y[9:7] == 2) && (3 <= pix_x[9:6]) && (pix_x[9:6] <= 6);
assign row_addr_l = pix_y[6:3]; //tamao del cuadro
assign bit_addr_l = pix_x[5:3];
always @*
case (pix_x[8:6])
3'o3: char_addr_l = 7'h52; // R
3'o4: char_addr_l = 7'h43; // C
3'o5: char_addr_l = 7'h4d; // M
default: char_addr_l = 7'h56; // V
endcase
//-------------------------------------------
// mux para accesar a ROM y rgb
//-------------------------------------------
always @* begin
text_rgb = 8'b11111111; // fondo blanco
case (sw)
3'b000: color_word = 8'b11011101; //Morado
3'b001: color_word = 8'b10010000; //azul oscuro
3'b010: color_word = 8'b11000000; //azul
3'b011: color_word = 8'b10000001; //morado oscuro
3'b100: color_word = 8'b00010001; //verde oscuro
3'b101: color_word = 8'b00011000; //verde claro
3'b110: color_word = 8'b00000100; //rojo
3'b111: color_word = 8'b11000111; //rosado
default: color_word = 8'b11111111; //nregro
endcase
if (text_on) begin
char_addr = char_addr_l;
row_addr = row_addr_l;
bit_addr = bit_addr_l;
if (font_bit) text_rgb = color_word;
end
//
end
//-------------------------------------------
//interface memoria fuente ROM
//-------------------------------------------
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
| 8.957293 |
module text_graph (
input wire clk,
input wire [3:0] left_high,
left_low,
input wire [3:0] right_high,
right_low,
input wire [9:0] pix_x,
pix_y,
output wire text_on,
output reg [2:0] text_rgb
);
wire [10:0] rom_add;
wire [3:0] row_add;
wire [2:0] bit_add;
wire [7:0] temp_data;
reg [7:0] char_add;
wire bit_color;
font_rom rom (
.clk (clk),
.addr(rom_add),
.data(temp_data)
);
assign text_on = (pix_y[9:5] == 0) && (pix_x[9:4] >= 9) && (pix_x[9:4] < 24);
assign row_add = pix_y[4:1];
assign bit_add = pix_x[3:1];
always @*
case (pix_x[9:4])
6'b001001: char_add = 7'h53;
6'b001010: char_add = 7'h63;
6'b001011: char_add = 7'h6f;
6'b001100: char_add = 7'h72;
6'b001101: char_add = 7'h65;
6'b001110: char_add = 7'h3a;
6'b001111: char_add = 7'h00;
6'b010000: char_add = {3'b011, left_high};
6'b010001: char_add = {3'b011, left_low};
6'b010010: char_add = 7'h00;
6'b010011: char_add = 7'h2d;
6'b010100: char_add = 7'h2d;
6'b010101: char_add = 7'h00;
6'b010110: char_add = {3'b011, right_high};
6'b010111: char_add = {3'b011, right_low};
6'b011000: char_add = 7'h00;
endcase
always @* begin
text_rgb = 3'b110;
if (text_on && bit_color) text_rgb = 3'b000;
end
assign rom_add = {char_add, row_add};
assign bit_color = temp_data[~bit_add];
endmodule
| 7.513612 |
module text_manager (
input CLK,
input advanced_sw,
input [3:0] MENU_R,
input [3:0] MENU_G,
input [3:0] MENU_B,
input [11:0] VGA_HORZ_COORD,
input [11:0] VGA_VERT_COORD,
input [3:0] MENU_OPTIONS,
output reg [3:0] TEXTR,
output reg [3:0] TEXTG,
output reg [3:0] TEXTB
);
wire CLK_VGA;
// VGA Clock Generator (108MHz)
CLK_108M VGA_CLK_108M (
CLK, // 100 MHz
CLK_VGA // 108 MHz
);
//max volume indicator + accompanying text coordinates
parameter maxvol_x = 1100;
parameter maxvol_y = 950;
// Text Generation
wire basic1;
wire advanced1;
//Overall
Pixel_On_Text2 #(
.displayText("VOICE SCOPE")
) t1 (
CLK_VGA,
25, // text position.x (top left)
25, // text position.y (top left)
VGA_HORZ_COORD, // current position.x
VGA_VERT_COORD, // current position.y
basic1 // result, 1 if current pixel is on text, 0 otherwise
);
Pixel_On_Text2 #(
.displayText("++")
) t2 (
CLK_VGA,
150, // text position.x (top left)
25, // text position.y (top left)
VGA_HORZ_COORD, // current position.x
VGA_VERT_COORD, // current position.y
advanced1 // result, 1 if current pixel is on text, 0 otherwise
);
wire res;
Pixel_On_Text2 #(
.displayText("VOLUME")
) t3 (
CLK_VGA,
maxvol_x - 25, // text position.x (top left)
maxvol_y, // text position.y (top left)
VGA_HORZ_COORD, // current position.x
VGA_VERT_COORD, // current position.y
res // result, 1 if current pixel is on text, 0 otherwise
);
wire [3:0] TEXT0;
wire [3:0] TEXT1;
assign TEXT0 = ((advanced_sw == 1 && advanced1 == 1) || basic1 == 1) ? 4'hF : 4'h0;
assign TEXT1 = (res == 1) ? 4'hF : 4'h0;
always @(*) begin
TEXTR <= (advanced_sw == 1) ? (TEXT0 | TEXT1 | MENU_OPTIONS | MENU_R) : TEXT0;
TEXTG <= (advanced_sw == 1) ? (TEXT0 | TEXT1 | MENU_OPTIONS | MENU_G) : TEXT0;
TEXTB <= (advanced_sw == 1) ? (TEXT0 | TEXT1 | MENU_OPTIONS | MENU_B) : TEXT0;
end
endmodule
| 6.762367 |
module text_screen_top (
input wire clk,
rst,
input wire [7:0] vga_cmd_word,
input wire [6:0] vga_char_code,
input wire [6:0] vga_cursor_x_pos,
input wire [4:0] vga_cursor_y_pos,
output wire vga_ctrl_idle,
output wire hsync,
vsync,
output wire [11:0] rgb
);
endmodule
| 6.793237 |
module: text
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module text_tb;
// Inputs
// Outputs
wire [3:0] c;
// Instantiate the Unit Under Test (UUT)
text uut (
.c(c)
);
initial begin
// Initialize Inputs
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.951458 |
module ata (
input CLK,
input AS,
input RW,
input [23:0] A,
input WAIT,
output [1:0] IDECS,
output IOR,
output IOW,
output DTACK,
output ACCESS
);
assign ACCESS = 1'b1;
assign DTACK = 1'b1;
assign IOR = 1'b1;
assign IOW = 1'b1;
assign IDECS = 2'b11;
endmodule
| 6.974379 |
module tf530_ram (
input CLKCPU,
input RESET,
input A0,
input A1,
input [8:2] AB,
input [23:12] A,
inout [7:0] D,
input [1:0] SIZ,
input IDEINT,
input IDEWAIT,
output INT2,
input AS20,
input RW20,
input DS20,
// cache and burst control
input CBREQ,
output CBACK,
output CIIN,
output STERM,
// 32 bit internal cycle.
// i.e. assert OVR
output INTCYCLE,
// spare / debug
output SPARE,
// ram chip control
output [3:0] RAMCS,
output RAMOE
);
reg AS20_D = 1'b1;
reg DS20_D = 1'b1;
reg STERM_D = 1'b1;
wire BUS_CYCLE = (~DS20_D | DS20);
reg configured = 'b0;
reg shutup = 'b0;
reg [7:0] data_out = 'h00;
reg [7:0] base = 'h40;
wire GAYLE_INT2;
wire [7:0] GAYLE_DOUT;
//
wire IDE_ACCESS = (A[23:15] != {8'hDA, 1'b0}) | DS20 | AS20;
// $DE0000 or $DA8000 (Ignores A18)
wire GAYLE_REGS = (A[23:15] != {8'hDA, 1'b1});
wire GAYLE_ID = (A[23:15] != {8'hDE, 1'b0});
wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS) | DS20 | AS20;
wire GAYLE_READ = (GAYLE_ACCESS | ~RW20);
gayle GAYLE (
.CLKCPU (CLKCPU),
.RESET (RESET),
.CS (GAYLE_ACCESS),
.DS (DS20),
.RW (RW20),
.A18 (A[18]),
.A ({1, b0, A[13:12]}),
.IDE_INT(IDEINT),
.INT2 (GAYLE_INT2),
.DIN (D),
.DOUT (GAYLE_DOUT)
);
// 0xE80000
wire Z2_ACCESS = ({A[23:16]} != {8'hE8}) | AS20 | DS20 | shutup | configured;
wire Z2_READ = (Z2_ACCESS | ~RW20);
wire Z2_WRITE = (Z2_ACCESS | RW20);
wire RAM_ACCESS = ({A[23:21]} != {base[7:5]}) | AS20 | DS20 | ~configured;
wire [6:0] zaddr = {AB[7:2], A1};
always @(posedge CLKCPU) begin
AS20_D <= AS20;
DS20_D <= DS20;
STERM_D <= INTCYCLE | ~STERM_D;
if (RESET == 1'b0) begin
configured <= 1'b0;
shutup <= 1'b0;
STERM_D <= 1'b1;
end else begin
if (Z2_WRITE === 1'b0) begin
case (zaddr)
'h24: begin
base[7:4] <= D[7:4];
configured <= 1'b1;
end
'h25: base[3:0] <= D[7:4];
'h26: shutup <= 1'b1;
endcase
end
data_out <= 8'hff;
// the Gayle/Gary ID shift register.
if (Z2_READ == 1'b0) begin
// zorro config ROM
case (zaddr)
'h00: data_out[7:4] <= 4'he;
'h01: data_out[7:4] <= 4'h6;
'h02: data_out[7:4] <= 4'h7;
'h03: data_out[7:4] <= 4'h7;
'h04: data_out[7:4] <= 4'h7;
'h08: data_out[7:4] <= 4'he;
'h09: data_out[7:4] <= 4'hc;
'h0a: data_out[7:4] <= 4'h2;
'h0b: data_out[7:4] <= 4'h7;
'h10: data_out[7:4] <= 4'hc;
'h12: data_out[7:4] <= 4'hc;
'h13: data_out[7:4] <= 4'h6;
endcase
end else if (GAYLE_READ == 1'b0) begin
data_out <= GAYLE_DOUT;
end
end
end
wire RAMCS3n = A1 | A0; //
wire RAMCS2n = (~SIZ[1] & SIZ[0] & ~A0) | A1;
wire RAMCS1n = (SIZ[1] & ~SIZ[0] & ~A1 & ~A0) | (~SIZ[1] & SIZ[0] & ~A1) | (A1 & A0);
wire RAMCS0n = (~SIZ[1] & SIZ[0] & ~A1 ) | (~SIZ[1] & SIZ[0] & ~A0 ) | (SIZ[1] & ~A1 & ~A0 ) | (SIZ[1] & ~SIZ[0] & ~A1 );
// disable all the RAM.
assign RAMOE = RAM_ACCESS;
assign RAMCS = {
RAMCS3n | RAM_ACCESS, RAMCS2n | RAM_ACCESS, RAMCS1n | RAM_ACCESS, RAMCS0n | RAM_ACCESS
};
assign INTCYCLE = RAM_ACCESS & GAYLE_ACCESS;
// disable all burst control.
assign STERM = STERM_D;
assign CBACK = 1'b1; //STERM_D | CBREQ;
// cache the sram.
assign CIIN = 1'b0; //~RAM_ACCESS;
assign INT2 = GAYLE_INT2 ? 1'b0 : 1'bz;
assign D = Z2_READ & GAYLE_READ ? 8'bzzzzzzzz : data_out;
endmodule
| 6.876238 |
module tflip (
input t,
qp,
clk,
reset,
output reg qn
);
always @(posedge clk) begin
if (reset == 1'b1) qn = 1'b0;
else qn = t ^ qp;
end
endmodule
| 6.815993 |
module TFF_AsyncClear (
output reg Q,
input T,
input clr,
input clk
);
initial begin
Q = 0;
end
always @(posedge clk, posedge clr) begin
if (clr) Q <= 0;
else Q <= Q ^ T;
end
endmodule
| 6.931557 |
module tff_async_reset (
data, // Data Input
clk, // Clock Input
reset, // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, clk, reset;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @(posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else if (data) begin
q <= !q;
end
endmodule
| 6.8872 |
module tff_async_rst_tb ();
// Signal Decleration
reg clk_i;
reg rst_i;
reg t_i;
wire q_o;
wire q_n_o;
// Instantiation
tff_async_rst dut (
.clk_i(clk_i),
.rst_i(rst_i),
.t_i (t_i),
.q_o (q_o),
.q_n_o(q_n_o)
);
// Clock generation
initial begin
clk_i = 1'b0;
forever #5 clk_i = ~clk_i;
end
// Task for applying input
task apply_input(input in);
begin
@(negedge clk_i);
t_i = in;
end
endtask
// Logic to drive inputs
initial begin
rst_i = 0;
t_i = 0; // Initialize to known values
// Apply Reset
@(posedge clk_i);
rst_i = 1'b1;
@(posedge clk_i);
rst_i = 1'b0;
apply_input(1);
@(negedge clk_i);
@(negedge clk_i);
@(negedge clk_i);
#2 rst_i = 1'b1;
#10 rst_i = 1'b0;
apply_input(1);
@(negedge clk_i);
apply_input(0);
@(negedge clk_i);
@(negedge clk_i);
@(negedge clk_i);
#20 $finish;
end
endmodule
| 7.313492 |
module to connect to the FPGA
module tff_final(SW, KEY, HEX0, HEX1);
input [1:0] SW;
input [0:0] KEY;
output [6:0] HEX0;
output [6:0] HEX1;
wire clk = ~KEY[0];
wire enable = SW[1];
wire clear_b = SW[0];
wire [7:0] Q;
t_flipflop t0(.clk(clk), .enable(enable), .clear_b(clear_b), .Q(Q));
seven_seg h0(.in(Q[3:0]), .hex(HEX0));
seven_seg h1(.in(Q[7:4]), .hex(HEX1));
endmodule
| 6.782222 |
module flipflop (
clk,
enable,
clear_b,
Q
);
input clk;
input enable;
input clear_b;
output reg Q;
always @(posedge clk, negedge clear_b) begin
if (clear_b == 1'b0) Q <= 1'b0;
else Q <= Q ^ enable;
end
endmodule
| 6.626138 |
module tff_p (
output reg q,
qbar,
input clk,
rst_n,
t
);
always @(posedge clk) begin
if (~rst_n) {q, qbar} <= 2'b01;
else if (t) {q, qbar} <= {qbar, q};
end
endmodule
| 8.046041 |
module TFF_SyncClear (
output reg Q,
input T,
input clr,
input clk
);
initial begin
Q = 0;
end
always @(posedge clk) begin
if (clr) Q <= 0;
else Q <= Q ^ T;
end
endmodule
| 6.528098 |
module t_ff_tb ();
// Step 1. Define a parameter with name "cycle" which is equal to 10
parameter cycle = 10;
reg clk, reset, t;
wire q, qb;
// Step 2. Instantiate the dff design
t_ff DUT (
.clk(clk),
.reset(reset),
.t(t),
.q(q),
.qb(qb)
);
// Step 3. Understand the clock generation logic
initial begin
clk = 1'b0;
end
always begin
#(cycle / 2);
clk = ~clk;
end
//Step4. Understand the various tasks used and also how to use tasks in testbench.
task rst_dut();
begin
reset = 1'b1;
#10;
reset = 1'b0;
end
endtask
task tin(input i);
begin
@(negedge clk);
t = i;
end
endtask
initial begin
rst_dut;
tin(0);
tin(1);
tin(0);
tin(1);
tin(1);
rst_dut;
tin(0);
tin(1);
#10;
$finish;
end
// Step 5. Use $monitor task in a parallel initial block to display inputs and outputs
initial $monitor("t=%d--q=%d--qb=%d", t, q, qb);
endmodule
| 6.501445 |
module tflipflop (
q,
qbar,
clk,
rst,
t
);
output reg q;
output qbar;
input clk, rst;
input t;
assign qbar = ~q;
always @(posedge clk) begin
if (rst) q <= 0;
else
case (t)
1'b0: q <= q;
1'b1: q <= ~q;
endcase
end
endmodule
| 6.576555 |
module Tflip_flop (
T,
clk,
reset,
Q
);
input T, clk, reset;
output Q;
reg Q;
wire D;
xor XOR (D, T, Q);
always @(negedge reset or posedge clk) begin
if (~reset) Q <= 1'b0;
else Q <= D;
end
endmodule
| 6.927708 |
module tfp401a (
input wire rst,
input wire odck_in,
input wire vsync_in,
input wire hsync_in,
input wire de_in,
input wire [7:0] pixel_r_in,
input wire [7:0] pixel_g_in,
input wire [7:0] pixel_b_in,
output reg scdt_o,
output wire odck_o,
output wire vsync_o,
output wire hsync_o,
output wire de_o,
output wire [7:0] pixel_r_o,
output wire [7:0] pixel_g_o,
output wire [7:0] pixel_b_o
);
assign odck_o = odck_in;
assign vsync_o = vsync_in;
assign hsync_o = hsync_in;
assign de_o = de_in;
assign pixel_b_o = pixel_b_in;
assign pixel_r_o = pixel_r_in;
assign pixel_g_o = pixel_g_in;
reg [1:0] de_det, de_cnt;
reg [19:0] counter;
wire de_transition;
always @(posedge odck_in) begin
de_det <= {de_det[0], de_in};
end
assign de_transition = de_det[1] != de_det[0];
always @(posedge odck_in or negedge rst) begin
if (!rst) begin
scdt_o <= 0;
counter <= 0;
de_cnt <= 0;
end else begin
if (scdt_o && counter == 20'd1000000) begin //is active now
counter <= 0;
de_cnt <= 0;
scdt_o <= (de_cnt == 2'd0 ? 1'b0 : 1'b1);
end else if (!scdt_o && counter == 20'd1600) begin
counter <= 0;
de_cnt <= 0;
scdt_o <= (de_cnt == 2'd2 ? 1'b1 : 1'b0);
end else begin
counter <= counter + 1'b1;
if (de_transition && de_cnt != 2'd2) de_cnt <= de_cnt + 1'b1;
end
end
end
endmodule
| 6.562374 |
module tfp410 (
input wire rst,
input wire odck_in,
input wire vsync_in,
input wire hsync_in,
input wire de_in,
input wire [7:0] pixel_r_in,
input wire [7:0] pixel_g_in,
input wire [7:0] pixel_b_in,
output wire pixel_clk_o,
output wire vsync_o,
output wire hsync_o,
output wire de_o,
output wire [4:0] pixel_r_o,
output wire [5:0] pixel_g_o,
output wire [4:0] pixel_b_o
);
assign pixel_clk_o = odck_in;
assign vsync_o = vsync_in;
assign hsync_o = hsync_in;
assign de_o = de_in;
assign pixel_r_o = pixel_r_in[7:3];
assign pixel_g_o = pixel_g_in[7:2];
assign pixel_b_o = pixel_b_in[7:3];
endmodule
| 7.272075 |
module tfpam ();
reg clk, rst;
reg pushin;
reg [63:0] ab, bb, cb, db, eb, fb;
wire pushout;
wire [63:0] z;
real a, b, c, d, e, f, res, rz;
reg [63:0] rfifo[0:128];
reg [6:0] rpt, wpt;
real r0 = 0.0;
real r1 = 1.0;
real mr1 = -1.0;
real r2 = 2.0;
real r2_5 = 2.5;
reg [63:0] mask = 64'hffffffff_fffffffC;
reg [63:0] delta;
integer waitclean = 0;
reg debug = 0;
fpam fp (
clk,
rst,
pushin,
ab,
bb,
cb,
db,
eb,
fb,
pushout,
z
);
initial begin
clk = 1;
forever #4.125 clk = ~clk;
end
initial begin
if (debug) begin
$dumpfile("fpam.vcd");
$dumpvars(9, tfpam);
end
rst = 0;
pushin = 0;
wpt = 0;
rpt = 0;
#1;
rst = 1;
repeat (5) @(posedge (clk));
#1;
rst = 0;
end
function [31:0] random_range;
input reg [31:0] low, high;
reg [31:0] wk, delta;
begin
wk = $random;
delta = high - low + 1;
wk = wk % delta;
random_range = wk + low;
end
endfunction
function real randreal;
input reg unused;
reg [63:0] wv;
reg [31:0] rd;
begin
rd = $random;
wv[63] = rd[13];
wv[62:52] = random_range(11'h2f0, 11'h420);
wv[51:0] = {$random, $random};
randreal = $bitstoreal(wv);
end
endfunction
task fail;
begin
$display("\n\n\n Simulation failed \n\n\n");
$finish;
end
endtask
always @(posedge (clk)) begin
if (waitclean > 5) begin
if (pushout === 1'bx) begin
$display("pushout is x");
fail;
end
if (pushout === 1) begin
delta = (z - rfifo[rpt]);
if (delta[63]) delta = -delta;
if (delta < 8) begin
rpt = rpt + 1;
end else begin
$display("\n\n\nOops ??? Expected %19.15e(%h)\n Got %19.15e(%h)\n",
rfifo[rpt], rfifo[rpt], z, z);
fail;
end
end
end else begin
waitclean = waitclean + 1;
end
end
task sendone;
input real ta, tb, tc, td, te, tf;
input integer nrc;
real exp;
reg [63:0] expbits;
begin
pushin = 1;
a = ta;
b = tb;
c = tc;
d = td;
e = te;
f = tf;
ab = $realtobits(ta);
bb = $realtobits(tb);
cb = $realtobits(tc);
db = $realtobits(td);
eb = $realtobits(te);
fb = $realtobits(tf);
exp = (ta + tb) * (tc + td) * (te + tf);
expbits = $realtobits(exp);
rfifo[wpt] = expbits;
wpt = wpt + 1;
if (rpt == wpt) begin
$display("\n\n\nYou overran the fifo Morris");
$display("\n\n\n it failed \n\n\n");
$finish;
end
@(posedge (clk));
#1;
pushin = 0;
ab = {$random, $random};
bb = {$random, $random};
cb = {$random, $random};
db = {$random, $random};
eb = {$random, $random};
fb = {$random, $random};
repeat (nrc) @(posedge (clk)) #1;
end
endtask
initial begin
repeat (8) @(posedge (clk)) #1;
sendone(r0, r1, r0, r1, r0, r1, 0);
sendone(r1, mr1, r0, r1, r0, r1, 0);
sendone(mr1, mr1, mr1, mr1, mr1, mr1, 0);
sendone(r0, r1, r0, r1, r0, r1, 5);
sendone(r1, mr1, r0, r1, r0, r1, 5);
sendone(mr1, mr1, mr1, mr1, mr1, mr1, 5);
repeat (1000) begin
sendone(randreal(1), randreal(1), randreal(1), randreal(1), randreal(1), randreal(1),
random_range(0, 1));
end
repeat (800) begin
sendone(randreal(1), randreal(1), randreal(1), randreal(1), randreal(1), randreal(1),
random_range(0, 15));
end
repeat (25) @(posedge (clk));
if (rpt != wpt) begin
$display("\n\n\nNot all data pushed out");
fail;
end
$display("\n\n\nAll done with a smile\n\n");
$finish;
end
endmodule
| 6.621664 |
module TftDriver (
input clk,
output reg tft_h,
output reg tft_v,
output reg [ 3:0] tft_r,
output reg [ 3:0] tft_g,
output reg [ 3:0] tft_b,
input [14:0] pixel, // Pixel for current cycle.
input de,
input border,
output tft_clk
);
endmodule
| 7.589874 |
module TFTLCDCtrl (
input clk,
input rst_n,
input [ 2:0] convert_type,
output [15:0] RGB, // TFT-LCD Red signal
output write_en,
output stop,
input [15:0] BRAMDATA, // BRAM Data 16bits
output reg [15:0] BRAMADDR // BRAM Address
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) BRAMADDR <= 0;
else if (!stop) BRAMADDR <= BRAMADDR + 1;
end
//assign RGB = BRAMDATA;
DSUS DSUS_i (
.clk (clk),
.rst_n (rst_n),
.convert_type(convert_type),
.BRAMDATA (BRAMDATA),
.RGB_out (RGB),
.write_en_out(write_en),
.stop_out (stop)
);
endmodule
| 7.256011 |
module tftlcd_pong_v1_0 #(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S01_AXI
parameter integer C_S01_AXI_DATA_WIDTH = 32,
parameter integer C_S01_AXI_ADDR_WIDTH = 4
) (
// Users to add ports here
input wire CLK, // = 25MHz
input wire nRESET, // ?
output wire TCLK, // TFT needs <12.5MHz>
output wire Hsync, // TFT-LCD HSYNC
output wire Vsync, // TFT-LCD VSYNC
output wire DE_out, // TFT-LCD Data enable ( Alaways "1" )
output wire [7:3] R,
output wire [7:2] G,
output wire [7:3] B,
output Tpower,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S01_AXI
input wire s01_axi_aclk,
input wire s01_axi_aresetn,
input wire [C_S01_AXI_ADDR_WIDTH-1 : 0] s01_axi_awaddr,
input wire [2 : 0] s01_axi_awprot,
input wire s01_axi_awvalid,
output wire s01_axi_awready,
input wire [C_S01_AXI_DATA_WIDTH-1 : 0] s01_axi_wdata,
input wire [(C_S01_AXI_DATA_WIDTH/8)-1 : 0] s01_axi_wstrb,
input wire s01_axi_wvalid,
output wire s01_axi_wready,
output wire [1 : 0] s01_axi_bresp,
output wire s01_axi_bvalid,
input wire s01_axi_bready,
input wire [C_S01_AXI_ADDR_WIDTH-1 : 0] s01_axi_araddr,
input wire [2 : 0] s01_axi_arprot,
input wire s01_axi_arvalid,
output wire s01_axi_arready,
output wire [C_S01_AXI_DATA_WIDTH-1 : 0] s01_axi_rdata,
output wire [1 : 0] s01_axi_rresp,
output wire s01_axi_rvalid,
input wire s01_axi_rready
);
// Instantiation of Axi Bus Interface S01_AXI
tftlcd_pong_v1_0_S01_AXI #(
.C_S_AXI_DATA_WIDTH(C_S01_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S01_AXI_ADDR_WIDTH)
) tftlcd_pong_v1_0_S01_AXI_inst (
// User Port
.CLK(CLK),
.nRESET(nRESET),
.TCLK(TCLK),
.Hsync(Hsync),
.Vsync(Vsync),
.DE_out(DE_out),
.R(R),
.G(G),
.B(B),
.Tpower(Tpower),
// User Port End
.S_AXI_ACLK(s01_axi_aclk),
.S_AXI_ARESETN(s01_axi_aresetn),
.S_AXI_AWADDR(s01_axi_awaddr),
.S_AXI_AWPROT(s01_axi_awprot),
.S_AXI_AWVALID(s01_axi_awvalid),
.S_AXI_AWREADY(s01_axi_awready),
.S_AXI_WDATA(s01_axi_wdata),
.S_AXI_WSTRB(s01_axi_wstrb),
.S_AXI_WVALID(s01_axi_wvalid),
.S_AXI_WREADY(s01_axi_wready),
.S_AXI_BRESP(s01_axi_bresp),
.S_AXI_BVALID(s01_axi_bvalid),
.S_AXI_BREADY(s01_axi_bready),
.S_AXI_ARADDR(s01_axi_araddr),
.S_AXI_ARPROT(s01_axi_arprot),
.S_AXI_ARVALID(s01_axi_arvalid),
.S_AXI_ARREADY(s01_axi_arready),
.S_AXI_RDATA(s01_axi_rdata),
.S_AXI_RRESP(s01_axi_rresp),
.S_AXI_RVALID(s01_axi_rvalid),
.S_AXI_RREADY(s01_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
| 7.266773 |
module tfto_decade_counter (
input clk,
reset,
output wire [3:0] q
);
wire [3:0] tmpq;
wire check;
wire tmpwire;
reg [3:0] B;
four_bit_decade_counter fourbit (
clk,
reset,
tmpq
);
assign check = (tmpq[3] & ~tmpq[2]) | (tmpq[2] & tmpq[0]) | (tmpq[2] & tmpq[1] & ~tmpq[0]);
always @(check)
if (check == 1'b1) begin
B = 4'b0110;
end else begin
B = 4'b0000;
end
adder4bit add0 (
tmpq,
B,
0,
q,
tmpwire
);
endmodule
| 7.236144 |
module four_bit_decade_counter (
input clk,
reset,
output wire [3:0] q
);
wire [3:0] qc;
wire [3:0] tmpq;
wire [6:0] tmpwire;
jk_ff b1 (
1'b1,
1'b1,
clk,
tmpq[0],
qc[0]
);
and (tmpwire[0], tmpq[0], qc[3]);
jk_ff b2 (
tmpwire[0],
tmpwire[0],
clk,
tmpq[1],
qc[1]
);
and (tmpwire[1], tmpq[0], tmpq[1]);
jk_ff b3 (
tmpwire[1],
tmpwire[1],
clk,
tmpq[2],
qc[2]
);
and (tmpwire[2], tmpwire[1], tmpq[2]);
and (tmpwire[3], tmpq[0], tmpq[3]);
or (tmpwire[4], tmpwire[2], tmpwire[3]);
jk_ff b4 (
tmpwire[4],
tmpwire[4],
clk,
tmpq[3],
qc[3]
);
and (q[0], ~reset, tmpq[0]);
and (q[1], ~reset, tmpq[1]);
and (q[2], ~reset, tmpq[2]);
and (q[3], ~reset, tmpq[3]);
endmodule
| 7.235784 |
module adder4bit (
A,
B,
Ci,
S,
Co
);
input [3:0] A, B;
input Ci;
output [3:0] S;
output Co;
wire [3:0] A, B, S;
wire Ci, Co;
wire [2:0] C;
adder1bit add1 (
A[0],
B[0],
Ci,
S[0],
C[0]
);
adder1bit add2 (
A[1],
B[1],
C[0],
S[1],
C[1]
);
adder1bit add3 (
A[2],
B[2],
C[1],
S[2],
C[2]
);
adder1bit add4 (
A[3],
B[3],
C[2],
S[3],
Co
);
endmodule
| 6.983906 |
module tft_char (
input wire sys_clk, //输入工作时钟,频率50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
output wire [15:0] rgb_tft, //输出像素信息
output wire hsync, //输出行同步信号
output wire vsync, //输出场同步信号
output wire tft_clk, //输出TFT时钟信号
output wire tft_de, //输出TFT使能信号
output wire tft_bl //输出背光信号
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire tft_clk_33m; //TFT工作时钟,频率33MHz
wire locked; //PLL locked信号
wire rst_n; //TFT模块复位信号
wire [10:0] pix_x; //TFT有效显示区域X轴坐标
wire [10:0] pix_y; //TFT有效显示区域Y轴坐标
wire [15:0] pix_data; //TFT像素点色彩信息
//rst_n:VGA模块复位信号
assign rst_n = (sys_rst_n & locked);
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- clk_gen_inst -------------
clk_gen clk_gen_inst (
.areset(~sys_rst_n), //输入复位信号,高电平有效,1bit
.inclk0(sys_clk), //输入50MHz晶振时钟,1bit
.c0 (tft_clk_33m), //输出TFT工作时钟,频率33Mhz,1bit
.locked(locked) //输出pll locked信号,1bit
);
//------------- tft_ctrl_inst -------------
tft_ctrl tft_ctrl_inst (
.tft_clk_33m(tft_clk_33m), //输入时钟,频率33MHz,1bit
.sys_rst_n (rst_n), //系统复位,低电平有效,1bit
.pix_data (pix_data), //待显示数据,16bit
.pix_x (pix_x), //输出TFT有效显示区域像素点X轴坐标,11bit
.pix_y (pix_y), //输出TFT有效显示区域像素点Y轴坐标,11bit
.rgb_tft(rgb_tft), //输出TFT显示数据,16bit
.hsync (hsync), //输出TFT行同步信号,1bit
.vsync (vsync), //输出TFT场同步信号,1bit
.tft_clk(tft_clk), //输出TFT像素时钟,1bit
.tft_de (tft_de), //输出TFT数据使能,1bit
.tft_bl (tft_bl) //输出TFT背光信号,1bit
);
//------------- tft_pic_inst -------------
tft_pic tft_pic_inst (
.tft_clk_33m(tft_clk_33m), //输入工作时钟,频率33MHz,1bit
.sys_rst_n (rst_n), //输入复位信号,低电平有效,1bit
.pix_x (pix_x), //输入TFT有效显示区域像素点X轴坐标,11bit
.pix_y (pix_y), //输入TFT有效显示区域像素点Y轴坐标,11bit
.pix_data(pix_data) //输出像素点色彩信息,16bit
);
endmodule
| 9.158181 |
module tft_color (
sclk,
srst,
hsync,
vsync,
rgb,
tft_bl,
tft_clk,
tft_de
);
input sclk;
input srst; // effective on Low Level
output hsync;
output vsync;
output [15:0] rgb;
output tft_bl;
output tft_clk;
output tft_de;
wire tft_sclk_33m;
wire tft_clk_50m;
wire locked;
wire rst_n;
wire [15:0] pix_data;
wire [10:0] pix_x;
wire [10:0] pix_y;
wire temp_pll_clk;
assign rst_n = locked & srst;
pll_ip pll_ip_inst (
.RESET (~srst),
// Clock in ports
.CLK_IN1 (sclk), // IN
// Clock out ports
.CLK_OUT1(tft_sclk_33m), // OUT
.CLK_OUT2(tft_clk_50m),
// Status and control signals
.LOCKED (locked) // OUT
);
//!!!! we need oddr2 because we can not connect to pll of FPGA directly!!!!!
ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) ODDR2_inst (
.Q(tft_clk), // 1-bit DDR output data
.C0(temp_pll_clk), // 1-bit clock input
.C1(~temp_pll_clk), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);
wire rd_en;
wire image_start;
wire [31:0] address;
wire decode_finished;
wire [15:0] etc_rgb;
tft_pix tft_pix_inst (
.tft_sclk_33m(tft_sclk_33m),
.srst(rst_n),
.pix_x(pix_x),
.pix_y(pix_y),
.decode_finished(decode_finished),
.etc_rgb(etc_rgb),
// output
//.rd_en(rd_en),
.image_start(image_start),
.address(address),
.pix_data(pix_data)
);
tft_ctrl tft_ctrl_inst (
.tft_sclk_33m(tft_sclk_33m),
.srst(rst_n),
.pix_data(pix_data),
.decode_finished(decode_finished),
//output
.pix_x(pix_x),
.pix_y(pix_y),
.vsync(vsync),
.hsync(hsync),
.rgb_data(rgb),
.tft_screen_de(tft_de),
.tft_back_light(tft_bl),
.tft_screen_clk(temp_pll_clk)
);
etc_decoder etc_decoder_inst (
.vga_clk(tft_sclk_33m),
.sclk(tft_clk_50m),
.rst(~rst_n),
.rd_en(image_start),
.read_addr(address),
.rgb(etc_rgb),
//.address_tb(tb_write_address),
.decode_finished(decode_finished)
);
endmodule
| 7.634653 |
module tft_colorbar (
input wire sys_clk, //输入工作时钟,频率50MHz
input wire sys_rst_n, //输入复位信号,低电平有效
output wire [15:0] rgb_tft, //输出像素信息
output wire hsync, //输出行同步信号
output wire vsync, //输出场同步信号
output wire tft_clk, //输出TFT时钟信号
output wire tft_de, //输出TFT使能信号
output wire tft_bl //输出背光信号
);
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire tft_clk_33m; //TFT工作时钟,频率33MHz
wire locked; //PLL locked信号
wire rst_n; //TFT模块复位信号
wire [10:0] pix_x; //TFT有效显示区域X轴坐标
wire [10:0] pix_y; //TFT有效显示区域Y轴坐标
wire [15:0] pix_data; //TFT像素点色彩信息
//rst_n:TFT模块复位信号
assign rst_n = (sys_rst_n & locked);
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- clk_gen_inst -------------
clk_gen clk_gen_inst (
.areset(~sys_rst_n), //输入复位信号,高电平有效,1bit
.inclk0(sys_clk), //输入50MHz晶振时钟,1bit
.c0 (tft_clk_33m), //输出TFT工作时钟,频率33Mhz,1bit
.locked(locked) //输出pll locked信号,1bit
);
//------------- tft_ctrl_inst -------------
tft_ctrl tft_ctrl_inst (
.tft_clk_33m(tft_clk_33m), //输入时钟,频率33MHz
.sys_rst_n (rst_n), //系统复位,低电平有效
.pix_data (pix_data), //待显示数据
.pix_x (pix_x), //输出TFT有效显示区域像素点X轴坐标
.pix_y (pix_y), //输出TFT有效显示区域像素点Y轴坐标
.rgb_tft(rgb_tft), //TFT显示数据
.hsync (hsync), //TFT行同步信号
.vsync (vsync), //TFT场同步信号
.tft_clk(tft_clk), //TFT像素时钟
.tft_de (tft_de), //TFT数据使能
.tft_bl (tft_bl) //TFT背光信号
);
//------------- tft_pic_inst -------------
tft_pic tft_pic_inst (
.tft_clk_33m(tft_clk_33m), //输入工作时钟,频率33MHz
.sys_rst_n (rst_n), //输入复位信号,低电平有效
.pix_x (pix_x), //输入TFT有效显示区域像素点X轴坐标
.pix_y (pix_y), //输入TFT有效显示区域像素点Y轴坐标
.pix_data(pix_data) //输出像素点色彩信息
);
endmodule
| 9.255621 |
module tft_pclk_gen (
clk,
rst,
pclk,
clock_divide,
lock
);
input clk;
input rst;
input [15:0] clock_divide;
//I need this statement because of simulation only in the real design, the pclk will transition when rst is low
output lock;
`ifdef VENDOR_XILINX
output pclk;
wire clk_fb;
wire clk_div;
BUFG CLKO_BUFG_INST (
.I(clk_out),
.O(clk_fb)
);
BUFG CLKO_BUFG_OUT (
.I(clk_div),
.O(pclk)
);
DCM_SP #(
.CLKDV_DIVIDE(5.0),
.CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(0.0),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DLL_FREQUENCY_MODE("LOW"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
) DCM_SP_INST (
.CLK0(clk_out),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLKDV(clk_div),
.CLKFX(),
.CLKFX180(),
.LOCKED(lock),
.PSDONE(),
.STATUS(),
.CLKFB(clk_fb),
.CLKIN(clk),
.PSCLK(0),
.PSEN(0),
.PSINCDEC(0),
.RST(rst)
);
// End of DCM_SP_inst instantiation
`else
//For debug simply connect clk to pclk
output reg pclk = 0;
assign lock = 1;
reg [15:0] delay;
always @(posedge clk) begin
if (rst) begin
delay <= 0;
pclk <= 1;
end else begin
if (delay == 0) begin
pclk <= ~pclk;
delay <= clock_divide;
end else begin
delay <= delay - 1;
end
end
end
`endif
endmodule
| 7.75834 |
module tft_pix (
tft_sclk_33m,
srst,
pix_x,
pix_y,
decode_finished,
etc_rgb,
//output
//rd_en,
image_start,
address,
pix_data
);
parameter H_VALID = 10'd800, V_VALID = 10'd480;
parameter RED = 16'hF800,
ORANGE = 16'hFC00,
YELLOW = 16'hFFE0,
GREEN = 16'h07E0,
CYAN = 16'h07FF,
BLUE = 16'h001F,
PURPPLE = 16'hF81F,
BLACK = 16'h0000,
WHITE = 16'hFFFF,
GRAY = 16'hD69A;
parameter HEIGHT = 10'd128, WIDTH = 10'd128, PIC_SIZE = 16'd16384;
input tft_sclk_33m;
input srst;
input [10:0] pix_x;
input [10:0] pix_y;
input [15:0] etc_rgb;
input decode_finished;
output [15:0] pix_data;
output [31:0] address;
output image_start;
reg rd_en;
reg [31:0] read_addr;
reg [15:0] rgb;
assign image_start = decode_finished &&(((pix_x >= (((H_VALID - HEIGHT)/2) - 1'b1))
&& (pix_x < (((H_VALID - HEIGHT)/2) + HEIGHT - 1'b1)))
&&((pix_y >= ((V_VALID - WIDTH)/2))
&& ((pix_y < (((V_VALID - WIDTH)/2) + WIDTH)))));
assign pix_data = (rd_en == 1'b1) ? etc_rgb : rgb;
assign address = read_addr;
always @(posedge tft_sclk_33m) begin
if (!srst) begin
read_addr <= 31'd0;
rd_en <= 1'b0;
end else begin
if (read_addr == (PIC_SIZE - 1'd1)) begin
read_addr <= 31'd0;
rd_en <= 1'b0;
end else if (image_start) begin
read_addr <= read_addr + 2'd1;
rd_en <= 1'b1;
end else begin
read_addr <= read_addr;
rd_en <= 1'b0;
end
end
end
always @(posedge tft_sclk_33m) begin
if (!srst) rgb <= 16'd0;
if (decode_finished) begin
if ((pix_x >= 0) && (pix_x < H_VALID / 10 * 1)) rgb <= RED;
else if ((pix_x >= (H_VALID / 10 * 1)) && (pix_x < (H_VALID / 10 * 2))) rgb <= ORANGE;
else if ((pix_x >= (H_VALID / 10 * 2)) && (pix_x < (H_VALID / 10 * 3))) rgb <= YELLOW;
else if ((pix_x >= (H_VALID / 10 * 3)) && (pix_x < (H_VALID / 10 * 4))) rgb <= GREEN;
else if ((pix_x >= (H_VALID / 10 * 4)) && (pix_x < (H_VALID / 10 * 5))) rgb <= CYAN;
else if ((pix_x >= (H_VALID / 10 * 5)) && (pix_x < (H_VALID / 10 * 6))) rgb <= BLUE;
else if ((pix_x >= (H_VALID / 10 * 6)) && (pix_x < (H_VALID / 10 * 7))) rgb <= PURPPLE;
else if ((pix_x >= (H_VALID / 10 * 7)) && (pix_x < (H_VALID / 10 * 8))) rgb <= BLACK;
else if ((pix_x >= (H_VALID / 10 * 8)) && (pix_x < (H_VALID / 10 * 9))) rgb <= WHITE;
else if ((pix_x >= (H_VALID / 10 * 9)) && (pix_x < (H_VALID))) rgb <= GRAY;
else rgb <= BLACK;
end
end
endmodule
| 7.014257 |
module: ACCM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_ACCM;
// Inputs
reg [6:0] X;
reg clk;
// Outputs
wire [15:0] ACC;
wire CO;
wire Mx;
// Instantiate the Unit Under Test (UUT)
ACCM uut (
.X(X),
.ACC(ACC),
.CO(CO),
.clk(clk),
.Mx(Mx)
);
parameter Tclk=20; // 20
always begin clk=0; #(Tclk/2); clk=1; #(Tclk/2); end
initial begin
// Initialize Inputs
X = 100;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.816828 |
module: AFE_ADS_TOP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_AFE_ADS;
// Inputs
reg sys_rst_n;
reg sys_clk;
reg AFE_STO;
reg AFE_EOC;
reg ADS_BUSY;
reg ADS_SDOA;
reg ADS_SDOB;
// Outputs
wire AFE_CLK;
wire AFE_INTG;
wire AFE_IRST;
wire AFE_SHS;
wire AFE_SHR;
wire AFE_PDZ;
wire AFE_NAPZ;
wire AFE_ENTRI;
wire AFE_SMT_MD;
wire AFE_INPUTZ;
wire AFE_DF_SM;
wire [2:0] AFE_PGA;
wire ADS_CLK;
wire ADS_CS_N;
wire ADS_RD;
wire ADS_SDI;
wire [1:0] ADS_M;
wire ADS_CONVST;
// Instantiate the Unit Under Test (UUT)
AFE_ADS_TOP uut (
.sys_rst_n(sys_rst_n),
.sys_clk(sys_clk),
.AFE_CLK(AFE_CLK),
.AFE_INTG(AFE_INTG),
.AFE_IRST(AFE_IRST),
.AFE_SHS(AFE_SHS),
.AFE_SHR(AFE_SHR),
.AFE_PDZ(AFE_PDZ),
.AFE_NAPZ(AFE_NAPZ),
.AFE_ENTRI(AFE_ENTRI),
.AFE_STO(AFE_STO),
.AFE_EOC(AFE_EOC),
.AFE_SMT_MD(AFE_SMT_MD),
.AFE_INPUTZ(AFE_INPUTZ),
.AFE_DF_SM(AFE_DF_SM),
.AFE_PGA(AFE_PGA),
.ADS_CLK(ADS_CLK),
.ADS_CS_N(ADS_CS_N),
.ADS_BUSY(ADS_BUSY),
.ADS_RD(ADS_RD),
.ADS_SDI(ADS_SDI),
.ADS_SDOA(ADS_SDOA),
.ADS_SDOB(ADS_SDOB),
.ADS_M(ADS_M),
.ADS_CONVST(ADS_CONVST)
);
initial begin
// Initialize Inputs
sys_rst_n = 0;
sys_clk = 0;
AFE_STO = 0;
AFE_EOC = 0;
ADS_BUSY = 0;
ADS_SDOA = 0;
ADS_SDOB = 0;
// Wait 100 ns for global reset to finish
#100;
sys_rst_n = 1;
// Add stimulus here
end
always # 10 sys_clk = ~sys_clk;
reg ADS_RD_D = 0,
ADS_CS_D = 0,
ADS_CLK_D = 0,
data_valid = 0;
reg [1:0] sdo_cnt = 0;
reg [17:0] sdo_data = 0;
reg [15:0] data = 1;
always @(posedge sys_clk) begin
ADS_RD_D <= ADS_RD;
ADS_CS_D <= ADS_CS_N;
ADS_CLK_D<= ADS_CLK;
if (!ADS_RD_D && ADS_RD) begin
data_valid <= 1;
sdo_cnt <= sdo_cnt + 1;
data <= data + 1;
sdo_data <= {sdo_cnt,data};
end
else if (!ADS_CS_D && ADS_CS_N) begin
data_valid <= 0;
sdo_cnt <= sdo_cnt;
end
else begin
data_valid <= data_valid;
sdo_cnt <= sdo_cnt;
end
if (data_valid) begin
if (!ADS_CLK_D && ADS_CLK) begin
ADS_SDOA <= sdo_data[17];
ADS_SDOB <= sdo_data[17];
sdo_data <= sdo_data << 1;
end
else begin
ADS_SDOA <= ADS_SDOA;
ADS_SDOB <= ADS_SDOB;
sdo_data <= sdo_data;
end
end
else begin
ADS_SDOA <= ADS_SDOA;
ADS_SDOB <= ADS_SDOB;
end
end
endmodule
| 6.87026 |
module tf_AR_TXD;
// Inputs
reg clk;
reg [1:0] Nvel;
reg [7:0] ADR;
reg [22:0] DAT;
reg st;
// Outputs
wire ce_tact;
wire TXD1;
wire TXD0;
wire SLP;
wire en_tx;
wire T_cp;
wire FT_cp;
wire SDAT;
wire QM;
wire [5:0] cb_bit;
wire en_tx_word;
// Instantiate the Unit Under Test (UUT)
AR_TXD uut (
.clk(clk),
.ce_tact(ce_tact),
.Nvel(Nvel),
.TXD1(TXD1),
.ADR(ADR),
.TXD0(TXD0),
.DAT(DAT),
.SLP(SLP),
.st(st),
.en_tx(en_tx),
.T_cp(T_cp),
.FT_cp(FT_cp),
.SDAT(SDAT),
.QM(QM),
.cb_bit(cb_bit),
.en_tx_word(en_tx_word)
);
parameter Tclk = 20; //Tclk=20ns
always begin
clk = 1'b0;
#(Tclk / 2) clk = 1'b1;
#(Tclk / 2);
end
initial begin
st = 0;
Nvel = 1;
ADR = 8'b10001000;
DAT = 23'h4C6600;
#1005;
st = 1;
#20;
st = 0;
#25000;
st = 1;
#20;
st = 0;
#614965;
st = 1;
#20;
st = 0;
#80000;
st = 1;
#20;
st = 0;
//#640000 us it takes to finish
end
endmodule
| 6.525415 |
module tf_DISPL;
// Inputs
reg clk;
reg [7:0] HB;
reg [7:0] LB;
// Outputs
wire [3:0] AN;
wire [6:0] seg;
wire seg_P;
wire ce1ms;
// Instantiate the Unit Under Test (UUT)
DISPL uut (
.clk(clk),
.AN(AN),
.HB(HB),
.seg(seg),
.LB(LB),
.seg_P(seg_P),
.ce1ms(ce1ms)
);
always begin
clk = 1'b0;
#10 clk = 1'b1;
#10;
end // PERIOD = 20
initial begin
// Initialize Inputs
HB = 8'b10000001;
LB = 8'b01111110;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.223089 |
module tf_FB16_to_FD27;
// Inputs
reg [15:0] FBI;
reg clk;
reg st;
// Outputs
wire [26:0] FDO;
wire [4:0] cb_tact;
wire EN_conv;
wire ok_conv;
// Instantiate the Unit Under Test (UUT)
FB16_to_FD27 uut (
.FDO(FDO),
.FBI(FBI),
.cb_tact(cb_tact),
.clk(clk),
.EN_conv(EN_conv),
.st(st),
.ok_conv(ok_conv)
);
parameter Tclk = 20; //Tclk=1/Fclk=1/50 mHz = 20 ns
always begin
clk = 0;
#(Tclk / 2) clk = 1;
#(Tclk / 2);
end
initial begin
// Initialize Inputs
FBI = 0;
clk = 0;
st = 0;
// Wait 100 ns for global reset to finish
#100;
FBI = 16'b0100110100111010;
st = 1;
#20;
st = 0;
// Add stimulus here
end
endmodule
| 7.610092 |
module: Gen_M
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_Gen_M;
// Inputs
reg clk;
reg ce5ms;
reg [10:0] x;
// Outputs
wire s;
// Instantiate the Unit Under Test (UUT)
Gen_M uut (
.clk(clk),
.ce5ms(ce5ms),
.x(x),
.s(s)
);
parameter T5ms = 5000000;
always begin #(T5ms - 20); ce5ms = 1; #20; ce5ms = 0; end;
parameter Tclk = 20;
always begin #(Tclk/2); clk = 1; #(Tclk/2); clk = 0; end;
initial begin
// Initialize Inputs
clk = 0;
ce5ms = 0;
x = 4;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.786262 |
module: Gen_SIN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_Gen_SIN;
// Inputs
reg clk;
reg ce;
// Outputs
wire S;
wire [3:0] X;
wire [7:0] Y;
wire [8:0] SIN;
// Instantiate the Unit Under Test (UUT)
Gen_SIN uut (
.S(S),
.clk(clk),
.X(X),
.ce(ce),
.Y(Y),
.SIN(SIN)
);
parameter Tclk = 20; //Tclk=1/Fclk=1/50 mHz = 20 ns
parameter Tce = 1000; //Tce=1/Fce=1/1Mhz = 1us = 1000ns
parameter NTce = Tce/Tclk ; //NTce=50
always begin clk=0 ; #(Tclk/2) clk=1; #(Tclk/2) ; end
always begin ce=0 ; #(Tclk*(NTce-1)) ce=1; #(Tclk) ; end
initial begin
// Initialize Inputs
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.383916 |
module tf_Gen_st;
// Inputs
reg clk;
// Outputs
wire st;
// Instantiate the Unit Under Test (UUT)
Gen_st uut (
.clk(clk),
.st (st)
);
parameter Tclk = 20;
always begin
clk = 0;
#(Tclk / 2) clk = 1;
#(Tclk / 2);
end
initial begin
// Initialize Inputs
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.0985 |
module: Gen_TM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_Gen_TM;
// Inputs
reg clk;
reg st;
reg ce;
// Outputs
wire Tm;
// Instantiate the Unit Under Test (UUT)
Gen_TM uut (
.clk(clk),
.st(st),
.ce(ce),
.Tm(Tm)
);
parameter Tclk = 20; //Tclk=1/Fclk=1/50 mHz = 20 ns
parameter Tce = 10000; //Tce=1/Fce
parameter NTce = Tce/Tclk ; //NTce=5000
always begin clk=0 ; #(Tclk/2) clk=1; #(Tclk/2) ; end
always begin ce=0 ; #(Tclk*(NTce-1)) ce=1; #(Tclk) ; end
initial begin
// Initialize Inputs
clk = 0;
st = 0;
ce = 0;
// Wait 100 ns for global reset to finish
#100;
ce = 1;
#1000; st = 1;
#20; st = 0;
#100 ce = 0;
#100 ce = 1;
end
endmodule
| 7.068677 |
module: Gen_Ux
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_Gen_Ux;
// Inputs
reg clk;
reg up;
reg BTN;
// Outputs
wire ceo;
wire ce1ms;
wire Ux;
wire [15:0] Xf;
// Instantiate the Unit Under Test (UUT)
Gen_Ux uut (
.clk(clk),
.ceo(ceo),
.up(up),
.ce1ms(ce1ms),
.BTN(BTN),
.Ux(Ux),
.Xf(Xf)
);
parameter Tclk = 20; //Tclk=1/Fclk=1/50 mHz = 20 ns
always begin clk=0 ; #(Tclk/2) clk=1; #(Tclk/2) ; end
initial begin
// Initialize Inputs
up = 0;
BTN = 0;
// Wait 100 ns for global reset to finish
#100;
BTN = 1;
#1000000
BTN = 0;
// Add stimulus here
end
endmodule
| 7.421621 |
module tf_Gen_XY;
// Inputs
reg st;
reg clk;
reg [7:0] SW;
// Outputs
wire [11:0] Q;
wire UP;
wire [11:0] X;
wire [11:0] Y;
// Instantiate the Unit Under Test (UUT)
Gen_XY uut (
.Q (Q),
.st (st),
.UP (UP),
.clk(clk),
.X (X),
.SW (SW),
.Y (Y)
);
parameter Tclk = 20;
always begin
clk = 0;
#(Tclk / 2) clk = 1;
#(Tclk / 2);
end
parameter Tst = 2900;
//Tst >= 2.89us = 2890ns
always begin
st = 0;
#(Tst - 20);
st = 1;
#20;
end
initial begin
// Initialize Inputs
st = 0;
clk = 0;
SW = 0;
// Wait 100 ns for global reset to finish
#100;
//#5222790;
SW = 8'b11000000;
#100;
SW = 8'b11000001;
#100;
SW = 8'b11000010;
#100;
SW = 8'b11000011;
#100;
SW = 8'b11000100;
#100;
// Add stimulus here
end
endmodule
| 6.815201 |
module tf_Hex;
// Inputs
reg [7:0] bin;
// Outputs
wire [9:0] bcd;
// Instantiate the Unit Under Test (UUT)
Hex2Dec uut (
.bin(bin),
.bcd(bcd)
);
initial begin
// Initialize Inputs
bin = 8'hA;
end
endmodule
| 6.944989 |
module tf_HEX27_to_DEC8;
// Inputs
reg [26:0] Dbin;
reg clk;
reg st;
// Outputs
wire [31:0] Ddec;
wire [3:0] ptr_dig;
// Instantiate the Unit Under Test (UUT)
HEX27_to_DEC8 uut (
.Dbin(Dbin),
.Ddec(Ddec),
.clk(clk),
.ptr_dig(ptr_dig),
.st(st)
);
parameter Tclk = 20; //Tclk=1/Fclk=1/50 mHz = 20 ns
always begin
clk = 0;
#(Tclk / 2) clk = 1;
#(Tclk / 2);
end
initial begin
// Initialize Inputs
Dbin = 27'b001011010101001110101010101;
st = 0;
// Wait 100 ns for global reset to finish
#100;
st = 1;
#20;
st = 0;
// Add stimulus here
end
endmodule
| 7.190962 |
module tf_quantization (
clk,
layer_reset,
stage_finish_i,
quan_weight_zero_i,
tf_quantization_en_i,
neuron_activation_i,
quan_scale_o
);
parameter NEURON_ACTIV_BIT_WIDTH = 8;
parameter SUM_QUAN_OFFSET_BIT_WIDTH = 16;
parameter INIT_SUM_QUAN_OFFSET = 16'd0;
parameter QUAN_SCALE_BIT_WIDTH = 24;
parameter INI_QUAN_SCALE = 24'h0;
parameter QUAN_WEIGHT_ZERO_BIT_WIDTH = 8;
input clk;
input layer_reset;
input stage_finish_i;
input [QUAN_WEIGHT_ZERO_BIT_WIDTH-1:0] quan_weight_zero_i;
input tf_quantization_en_i;
input [NEURON_ACTIV_BIT_WIDTH-1:0] neuron_activation_i;
output reg [QUAN_SCALE_BIT_WIDTH-1:0] quan_scale_o;
// sum of neuron activation
reg [SUM_QUAN_OFFSET_BIT_WIDTH-1:0] sum_quan_offset;
always @(posedge clk or posedge layer_reset) begin
if (layer_reset) begin
sum_quan_offset <= INIT_SUM_QUAN_OFFSET;
end else if (tf_quantization_en_i) begin
if (stage_finish_i) begin
sum_quan_offset <= neuron_activation_i;
end else begin
sum_quan_offset <= sum_quan_offset + neuron_activation_i;
end
end
// if (stage_finish_i) begin
// sum_quan_offset <= neuron_activation_i;
// end
// else if (tf_quantization_en_i) begin
// sum_quan_offset <= sum_quan_offset + neuron_activation_i;
// end
end
always @(posedge clk) begin
if (tf_quantization_en_i) begin
if (stage_finish_i) begin
quan_scale_o <= sum_quan_offset * quan_weight_zero_i;
end
end
// else begin
// quan_scale_o <= INI_QUAN_SCALE;
// end
end
endmodule
| 6.947266 |
module tf_Sch_test_SLAVE;
// Inputs
reg st;
reg clk;
reg [14:0] MTX_DAT;
reg RESET;
reg [14:0] STX_DAT;
// Outputs
wire LOAD;
wire SCLK;
wire MOSI;
wire [14:0] MRX_DAT;
wire [14:0] sr_MTX;
wire [14:0] sr_MRX;
wire [7:0] cb_bit;
wire ce_tact;
wire MISO;
wire [14:0] sr_STX;
wire [14:0] sr_SRX;
wire [14:0] SRX_DAT;
// Instantiate the Unit Under Test (UUT)
Sch_test_SLAVE uut (
.st(st),
.LOAD(LOAD),
.clk(clk),
.SCLK(SCLK),
.MTX_DAT(MTX_DAT),
.MOSI(MOSI),
.RESET(RESET),
.MRX_DAT(MRX_DAT),
.sr_MTX(sr_MTX),
.sr_MRX(sr_MRX),
.cb_bit(cb_bit),
.ce_tact(ce_tact),
.STX_DAT(STX_DAT),
.MISO(MISO),
.sr_STX(sr_STX),
.sr_SRX(sr_SRX),
.SRX_DAT(SRX_DAT)
);
always begin
#10;
clk = 1;
#10;
clk = 0;
end
initial begin
// Initialize Inputs
st = 0;
MTX_DAT = 15'b111110000110011;
RESET = 0;
STX_DAT = 15'b101011010101010;
// Wait 100 ns for global reset to finish
#100;
st = 1;
#20;
st = 0;
// Add stimulus here
end
endmodule
| 6.58972 |
module tf_Sch_test_URXD1B;
// Inputs
reg tx_clk;
reg st;
reg [7:0] tx_dat;
reg rx_clk;
// Outputs
wire TXD;
wire [3:0] cb_bit_tx;
wire en_rx_byte;
wire [7:0] sr_dat;
wire [3:0] cb_bit_rx;
wire ok_rx_byte;
wire start_rx;
wire T_start;
wire T_dat;
wire T_stop;
wire ce_tact;
wire ce_bit;
wire RXD;
// Instantiate the Unit Under Test (UUT)
Sch_test_URXD1B uut (
.tx_clk(tx_clk),
.TXD(TXD),
.st(st),
.cb_bit_tx(cb_bit_tx),
.tx_dat(tx_dat),
.en_rx_byte(en_rx_byte),
.rx_clk(rx_clk),
.sr_dat(sr_dat),
.cb_bit_rx(cb_bit_rx),
.ok_rx_byte(ok_rx_byte),
.start_rx(start_rx),
.T_start(T_start),
.T_dat(T_dat),
.T_stop(T_stop),
.ce_tact(ce_tact),
.ce_bit(ce_bit),
.RXD(RXD)
);
always begin
tx_clk = 1'b0;
#10 tx_clk = 1'b1;
#10;
end // PERIOD = 20
always begin
rx_clk = 1'b0;
#10 rx_clk = 1'b1;
#10;
end // PERIOD = 20
//always begin rx_clk = 1'b0; #10.5 rx_clk = 1'b1; #10.5; end // PERIOD = 21
//always begin rx_clk = 1'b0; #9.4 rx_clk = 1'b1; #9.4; end // PERIOD = 18.8
initial begin
st = 0;
tx_dat = 0;
#1000;
st = 1;
tx_dat = 8'b10000001; // my tx_dat ( 1)
#20;
st = 0;
tx_dat = 8'b10000001; // my tx_dat ( 1)
//#1270;
//#160;
//#160;
//#20;
//st = 1;
//#20;
//st = 0;
end
endmodule
| 6.708776 |
module tf_SOURCES_DAT;
// Outputs
wire [14:0] MASTER_dat;
wire [15:0] MASTER_dat_disp;
wire [15:0] SLAVE_dat_disp;
wire [14:0] SLAVE_dat;
// Instantiate the Unit Under Test (UUT)
SOURCES_DAT uut (
.MASTER_dat(MASTER_dat),
.MASTER_dat_disp(MASTER_dat_disp),
.SLAVE_dat_disp(SLAVE_dat_disp),
.SLAVE_dat(SLAVE_dat)
);
initial begin
// Initialize Inputs
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.848456 |
module tf_SPI_DAC8043;
// Inputs
reg st;
reg clk;
reg [11:0] DI;
// Outputs
wire SDAT;
wire SCLK;
wire NLD;
wire ce;
wire [3:0] cb_bit;
// Instantiate the Unit Under Test (UUT)
SPI_DAC8043 uut (
.SDAT(SDAT),
.st(st),
.SCLK(SCLK),
.clk(clk),
.DI(DI),
.NLD(NLD),
.ce(ce),
.cb_bit(cb_bit)
);
parameter Tclk = 20;
always begin
clk = 0;
#(Tclk / 2) clk = 1;
#(Tclk / 2);
end
initial begin
// Initialize Inputs
st = 0;
clk = 0;
DI = 0;
// Wait 100 ns for global reset to finish
#100;
DI = 12'b100011000111;
#20;
st = 1;
#20;
st = 0;
#2870;
//st = 1;
#20;
st = 0;
// Add stimulus here
end
endmodule
| 6.506143 |
module tf_SPI_MASTER;
// Inputs
reg st;
reg clk;
reg MISO;
reg clr;
reg [14:0] DI;
// Outputs
wire LOAD;
wire SCLK;
wire MOSI;
wire ce;
wire ce_tact;
wire [7:0] cb_bit;
wire [14:0] sr_MTX;
wire [14:0] sr_MRX;
wire [14:0] DO;
// Instantiate the Unit Under Test (UUT)
SPI_MASTER uut (
.st(st),
.LOAD(LOAD),
.clk(clk),
.SCLK(SCLK),
.MISO(MISO),
.MOSI(MOSI),
.clr(clr),
.ce(ce),
.DI(DI),
.ce_tact(ce_tact),
.cb_bit(cb_bit),
.sr_MTX(sr_MTX),
.sr_MRX(sr_MRX),
.DO(DO)
);
always begin
#10;
clk = 1;
#10;
clk = 0;
end
initial begin
// Initialize Inputs
st = 0;
MISO = 1;
clr = 0;
DI = 15'b111110000110011;
// Wait 100 ns for global reset to finish
#100;
st = 1;
#20;
st = 0;
#60000;
MISO = 0;
st = 1;
#20;
st = 0;
// Add stimulus here
end
endmodule
| 6.99594 |
module testbench;
parameter cyc = 10; //use "cyc" to represent the period
///// declare input(reg) and output(wire) /////
reg clk;
reg rst_n;
reg enable;
wire [1:0] out_state;
///// declare module /////
trafficlight #(
.RED_TIME(3),
.GREEN_TIME(2),
.YELLOW_TIME(1)
) u1 (
.clk(clk),
.enable(enable),
.rst_n(rst_n),
.out_state(out_state)
);
initial begin
$fsdbDumpfile("tfliht.fsdb");
$fsdbDumpvars;
end
integer i, pat;
////// clock //////
always #(cyc / 2) clk = ~clk;
////// test patterns /////
initial begin
clk = 0;
rst_n = 1;
#(cyc) enable = 0;
rst_n = 0;
#(cyc) rst_n = 1;
#(cyc) enable = 1;
#(cyc * 15) enable = 0;
#(cyc * 1000) $display("Simulaiton end by time out");
$finish;
end
integer f_out, error_cnt;
reg [3:0] golden[0:19];
initial begin
error_cnt = 0;
$readmemh("golden_state.pat", golden);
wait (enable == 0);
wait (enable == 1);
for (i = 0; i < 20; i = i + 1) begin
@(negedge clk)
if (out_state !== golden[i]) begin
$display("time %t : current state should be %d, but your is %d | !!!Incorrect!!!", $time,
golden[i], out_state);
error_cnt = error_cnt + 1;
end else $display("time %t : Current State is %d", $time, out_state);
#(cyc);
end
$fclose(f_out);
if (error_cnt === 0) $display("Good! Your traffic light is correct");
$finish;
end
endmodule
| 7.015571 |
module: transform
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_test;
// Inputs
reg clk;
reg [10:0] t_height;
reg [10:0] t_width;
reg [10:0] x;
reg [9:0] y;
// Outputs
wire [12:0] cv_x;
wire [12:0] cv_y;
wire [21:0] x_prod;
wire [21:0] y_prod;
// Instantiate the Unit Under Test (UUT)
transform uut (
.clk(clk),
.t_height(t_height),
.t_width(t_width),
.x(x),
.y(y),
.cv_x(cv_x),
.cv_y(cv_y),
.x_prod(x_prod),
.y_prod(y_prod)
);
always #5 clk = ~clk;
//always #200
initial begin
// Initialize Inputs
clk = 0;
t_height = 0;
t_width = 0;
x = 0;
y = 0;
// Wait 100 ns for global reset to finish
#100;
t_height= 120;
t_width =120;
x = 234;
y = 34;
// Add stimulus here
end
endmodule
| 6.675281 |
module: transform
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_testb;
// Inputs
reg clk;
reg [10:0] t_height;
reg [10:0] t_width;
reg [10:0] x;
reg [9:0] y;
// Outputs
wire [21:0] x_prod;
wire [21:0] y_prod;
// Instantiate the Unit Under Test (UUT)
transform uut (
.clk(clk),
.t_height(t_height),
.t_width(t_width),
.x(x),
.y(y),
.x_prod(x_prod),
.y_prod(y_prod)
);
always #5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
t_height = 0;
t_width = 0;
x = 0;
y = 0;
// Wait 100 ns for global reset to finish
#100;
t_height=120;
t_width = 120;
x = 124;
y = 300;
// Add stimulus here
end
endmodule
| 6.675281 |
module tf_Test_DET_FSK;
// Inputs
reg clk;
reg st;
reg [7:0] dat;
reg [7:0] Mamp;
// Outputs
wire [11:0] FSK_SH;
wire S;
wire ce_SIN;
wire en_tx;
wire TX_bit;
wire ce_tx_bit;
wire [11:0] DFSK_SH;
wire OCD;
wire [11:0] AMP;
wire [12:0] bf_SH;
wire FSK_tact;
wire [6:0] cb_tact;
wire FSK_start;
wire FSK_en_rx;
wire [3:0] cb_rx_bit;
wire FSK_res;
wire [10:0] F1_AMP;
wire [10:0] F2_AMP;
wire RX_bit;
wire ok_rx_bit;
wire [6:0] cb_FSK_res;
// Instantiate the Unit Under Test (UUT)
Test_DET_FSK uut (
.clk(clk),
.FSK_SH(FSK_SH),
.st(st),
.S(S),
.dat(dat),
.ce_SIN(ce_SIN),
.Mamp(Mamp),
.en_tx(en_tx),
.TX_bit(TX_bit),
.ce_tx_bit(ce_tx_bit),
.DFSK_SH(DFSK_SH),
.OCD(OCD),
.AMP(AMP),
.bf_SH(bf_SH),
.FSK_tact(FSK_tact),
.cb_tact(cb_tact),
.FSK_start(FSK_start),
.FSK_en_rx(FSK_en_rx),
.cb_rx_bit(cb_rx_bit),
.FSK_res(FSK_res),
.F1_AMP(F1_AMP),
.F2_AMP(F2_AMP),
.RX_bit(RX_bit),
.ok_rx_bit(ok_rx_bit),
.cb_FSK_res(cb_FSK_res)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
st = 0;
dat = 0;
Mamp = 0; //
#1000000;
st = 1;
dat = 8'h0F;
Mamp = 16; //Mamp=1,2,128
#20;
st = 0;
end
endmodule
| 6.757608 |
module: Test_MES_AMP_SIN
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`include "CONST.v"
module tf_Test_MES_AMP_SIN;
// Inputs
reg clk;
reg ce;
reg [7:0] NT;
reg [8:0] NS;
reg we;
// Outputs
wire S;
wire ce_tact;
wire [8:0] SIN;
wire ce_S1;
wire ce_S2;
wire [8:0] S1;
wire [8:0] S2;
wire [7:0] mod_S1;
wire [7:0] mod_S2;
wire ok_SQ;
wire [15:0] AMP_QV;
wire [7:0] AMP_SIN;
// Instantiate the Unit Under Test (UUT)
Test_MES_AMP_SIN uut (
.S(S),
.clk(clk),
.ce_tact(ce_tact),
.ce(ce),
.SIN(SIN),
.NT(NT),
.ce_S1(ce_S1),
.NS(NS),
.ce_S2(ce_S2),
.we(we),
.S1(S1),
.S2(S2),
.mod_S1(mod_S1),
.mod_S2(mod_S2),
.ok_SQ(ok_SQ),
.AMP_QV(AMP_QV),
.AMP_SIN(AMP_SIN)
);
parameter Tclk = 20; //Tclk=1/Fclk=1/50 mHz = 20 ns
parameter Tce = 1000; //Tce=1/Fce=1/1Mhz = 1us = 1000ns
parameter NTce = Tce/Tclk ; //NTce=50
always begin clk=0 ; #(Tclk/2) clk=1; #(Tclk/2) ; end
always begin ce=0 ; #(Tclk*(NTce-1)) ce=1; #(Tclk) ; end
initial begin
// Initialize Inputs
//NT = `NP; // NA ~= 99
NT = `NP - 4; // NA ~= 103/104
//NT = `NP + 4; // NA ~= 105/101/97/94
NS = 0;
we = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.572703 |
module tf_Test_RX_ATRP_AR_TXA;
// Inputs
reg clk;
reg [5:0] M;
// Outputs
wire [11:0] TXA;
wire [11:0] D_RXA;
wire [11:0] Xns;
wire RXP;
wire RXN;
wire [10:0] AMP;
wire res;
wire [7:0] N_RXPN;
wire en_TX;
wire err;
// Instantiate the Unit Under Test (UUT)
Test_RX_ATRP_AR_TXA uut (
.clk(clk),
.TXA(TXA),
.M(M),
.D_RXA(D_RXA),
.Xns(Xns),
.RXP(RXP),
.RXN(RXN),
.AMP(AMP),
.res(res),
.N_RXPN(N_RXPN),
.en_TX(en_TX),
.err(err)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
M = 0;
#10000;
M = 5; //2016
#3400000;
M = 6; //1024
#2880000;
M = 16; //512
#2880000;
M = 6; //256
#2880000;
M = 5; //128
#2880000;
M = 4; //96
end
endmodule
| 6.638156 |
module tf_Test_RX_MTR;
// Inputs
reg clk;
reg st;
reg [5:0] M;
reg S;
reg res;
// Outputs
wire [11:0] MTRP;
wire [11:0] MEM_dat;
wire [11:0] Xmax;
wire [11:0] Xns;
wire [11:0] Xmin;
wire [11:0] REF_P;
wire [11:0] REF_N;
wire RXP;
wire RXN;
wire [10:0] AMP;
// Instantiate the Unit Under Test (UUT)
Test_RX_MTRP uut (
.clk(clk),
.MTRP(MTRP),
.st(st),
.MEM_dat(MEM_dat),
.M(M),
.Xmax(Xmax),
.S(S),
.Xns(Xns),
.res(res),
.Xmin(Xmin),
.REF_P(REF_P),
.REF_N(REF_N),
.RXP(RXP),
.RXN(RXN),
.AMP(AMP)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
st = 0;
M = 0;
S = 0;
res = 0;
#3000;
st = 1;
M = 6;
S = 1;
res = 0;
#20;
st = 0;
res = 0;
#80000;
st = 1;
M = 6;
S = 0;
res = 0;
#20;
st = 0;
res = 0;
#100000;
st = 1;
M = 5;
S = 1;
res = 1;
#20;
st = 0;
res = 0;
#80000;
st = 1;
M = 5;
S = 0;
res = 0;
#20;
st = 0;
res = 0;
#80000;
st = 0;
M = 8;
S = 1;
res = 1;
#20;
st = 0;
res = 0;
end
endmodule
| 7.203734 |
module tf_Test_Sch;
// Inputs
reg clk;
reg [1:0] Nvel;
reg [7:0] ADR;
reg [22:0] DAT;
reg st;
// Outputs
wire ce_tx;
wire TXD1;
wire TXD0;
wire SLP;
wire en_tx_dat;
wire T_cp_tx;
wire FT_tx;
wire SDAT;
wire QM;
wire [5:0] cb_bit;
wire en_tx_word;
wire [22:0] sr_dat_rx;
wire [7:0] sr_adr_rx;
wire ok_rx;
// Instantiate the Unit Under Test (UUT)
Test_Sch uut (
.clk(clk),
.ce_tx(ce_tx),
.Nvel(Nvel),
.TXD1(TXD1),
.ADR(ADR),
.TXD0(TXD0),
.DAT(DAT),
.SLP(SLP),
.st(st),
.en_tx_dat(en_tx_dat),
.T_cp_tx(T_cp_tx),
.FT_tx(FT_tx),
.SDAT(SDAT),
.QM(QM),
.cb_bit(cb_bit),
.en_tx_word(en_tx_word),
.sr_dat_rx(sr_dat_rx),
.sr_adr_rx(sr_adr_rx),
.ok_rx(ok_rx)
);
parameter Tclk = 20; //Tclk=20ns
always begin
clk = 1'b0;
#(Tclk / 2) clk = 1'b1;
#(Tclk / 2);
end
initial begin
st = 0;
Nvel = 1;
ADR = 8'b10001000;
DAT = 23'h4C6600;
#1005;
st = 1;
#20;
st = 0;
#25000;
st = 1;
#20;
st = 0;
#614965;
st = 1;
#20;
st = 0;
#80000;
st = 1;
#20;
st = 0;
//#640000 us it takes to finish
end
endmodule
| 6.555105 |
module tf_UTXD1B;
// Inputs
reg clk;
reg [7:0] dat;
reg st;
// Outputs
wire TXD;
wire ce_tact;
wire [3:0] cb_bit;
wire T_start;
wire T_dat;
wire T_stop;
wire ce_stop;
wire en_tx_byte;
wire [7:0] sr_dat;
// Instantiate the Unit Under Test (UUT)
UTXD1B uut (
.clk(clk),
.TXD(TXD),
.dat(dat),
.ce_tact(ce_tact),
.st(st),
.cb_bit(cb_bit),
.T_start(T_start),
.T_dat(T_dat),
.T_stop(T_stop),
.ce_stop(ce_stop),
.en_tx_byte(en_tx_byte),
.sr_dat(sr_dat)
);
always begin
clk = 1'b0;
#10 clk = 1'b1;
#10;
end // PERIOD = 20
initial begin
// Initialize Inputs
dat = 8'b10000001;
st = 0;
// Wait 100 ns for global reset to finish
#100;
st = 1;
#20;
st = 0;
// Add stimulus here
end
endmodule
| 7.159277 |
module: VCB4SED
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tf_VCB4SED;
// Inputs
reg ce;
reg clk;
reg s;
// Outputs
wire [3:0] Q;
wire TC;
wire CEO;
// Instantiate the Unit Under Test (UUT)
VCB4SED uut (
.ce(ce),
.clk(clk),
.s(s),
.Q(Q),
.TC(TC),
.CEO(CEO)
);
// clk
parameter Tclk=20; // 20
always begin clk=0; #(Tclk/2); clk=1; #(Tclk/2); end
initial begin
// Initialize Inputs
ce = 0;
clk = 0;
s = 0;
// Wait 100 ns for global reset to finish
#100;
ce = 0;
s = 0;
clk = 0;
#5; ce = 1;
#75; ce = 0;
#20; ce = 1;
#35; s = 1;
#25; s = 0;
end
endmodule
| 6.971183 |
module.
// The dual-port ram holding the program is part of the local bus
// address space, defined by an external address decoder that supplies
// the dests_write port signal. The size of that memory is defined
// by the pcw parameter.
// After filling the table, toggle bank_next to make it take effect.
// In theory, you should then wait for that new bank_next value to
// propagate to bank_stat before writing anything else to the table.
// That's only of real concern if trig inputs are rare.
// Features:
// Each set of four addresses means:
// time delay
// address to write
// lower half-word of data
// upper half-word of data
// time delay is in units of (clock cycles * 2^tgen_gran), applied _after_ the
// register write.
// Each operation takes four cycles by itself; the delay cycle count adds to
// this pedestal.
// An address of zero ends the program and resets the state to pc=0,
// which restarts when an external trig is supplied.
// runs at 150 MHz in Spartan-6 using 93 slice LUTs and one BRAM.
// Larry Doolittle, LBNL, 2014
module tgen #(
parameter aw = 17,
parameter tgen_gran = 0 // tick extension
) (
input clk, // timespec 6.66 ns
input trig,
output collision,
// Controlling bus
input [31:0] lb_data,
input lb_write,
input [aw-1:0] lb_addr,
input dests_write,
input [aw-17:0] addr_padding,
(* external *)
input bank_next, // external
// optional monitoring
output [3:0] status,
// These two are not actually used, but they trigger magic from newad
(* external *)
input [31:0] delay_pc_XXX, // external
(* external *)
output [9:0] delay_pc_XXX_addr, // external
// Controlled bus
output [31:0] lbo_data,
output lbo_write,
output [aw-1:0] lbo_addr
);
localparam pcw=10; // Set delay_pc_XXX_addr width above to pcw
assign delay_pc_XXX_addr = 0;
// Counters
reg [pcw-1:0] pc=0;
wire [1:0] subcycle = pc[1:0];
reg [15+tgen_gran:0] timer=0;
wire [15:0] new_timer; // comes from RAM
reg mem_zero=0; // comes from RAM
wire zero_addr = (subcycle==3) & mem_zero;
wire trig1 = trig & pc==0;
reg trig1d=0;
reg did_work=0;
wire increment = (pc==0) ? trig1d : (subcycle!=0) | (timer==0);
always @(posedge clk) begin
trig1d <= trig1;
pc <= pc + increment;
if (zero_addr) pc <= 0;
timer <= (subcycle==1) ? (new_timer<<tgen_gran) : timer-(subcycle==0);
if (trig1) did_work <= 0;
if (pc[2]) did_work <= 1;
end
// Atomic flip between banks
// OK for bank_next to be in some other clock domain
reg bank=0, bank_prev=0, work_prev=0;
always @(posedge clk) if (trig1) begin
bank <= bank_next;
bank_prev <= bank;
work_prev <= did_work;
end
// DPRAM
wire [15:0] mem_out;
wire [pcw:0] addra = { bank, lb_addr[pcw-1:0]};
wire [pcw:0] addrb = {~bank, pc};
dpram #(.dw(16), .aw(pcw+1)) dests(.clka(clk), .clkb(clk),
.addra(addra), .dina(lb_data[15:0]), .wena(dests_write),
.addrb(addrb), .doutb(mem_out));
// Data path for DPRAM read results
reg [15:0] mem_out1=0, mem_out2=0;
always @(posedge clk) begin
mem_out1 <= mem_out;
mem_out2 <= mem_out1;
mem_zero <= mem_out==0;
end
assign new_timer=mem_out;
reg write_cycle=0;
wire [31:0] our_data = write_cycle ? {mem_out1,mem_out} : 32'd0;
wire [15:0] our_addr = write_cycle ? mem_out2 : 16'd0;
always @(posedge clk) write_cycle <= subcycle==3 & ~mem_zero;
// Now merge the two streams
reg [31:0] lbo_data_r=0;
reg [aw-1:0] lbo_addr_r=0;
reg lbo_write_r=0, collision_r=0;
wire write_thru = lb_write & ~dests_write;
always @(posedge clk) begin
lbo_data_r <= write_thru ? lb_data : our_data;
lbo_addr_r <= write_thru ? lb_addr : {addr_padding, our_addr};
lbo_write_r <= write_thru | write_cycle;
collision_r <= write_thru & write_cycle;
end
// Output ports
assign lbo_addr = lbo_addr_r;
assign lbo_data = lbo_data_r;
assign lbo_write = lbo_write_r;
assign collision = collision_r;
assign status = {work_prev, bank_prev, bank, bank_next};
endmodule
| 8.331668 |
module tgen_tb;
reg clk;
integer cc, errors;
`ifdef SIMULATE
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("tgen.vcd");
$dumpvars(5, tgen_tb);
end
errors = 0;
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 240; cc = cc + 1) begin
clk = 0;
#5;
clk = 1;
#5;
end
//$display("%s",errors==0?"PASS":"FAIL");
$display("PASS");
$finish(0);
end
`endif // `ifdef SIMULATE
integer file1;
reg [255:0] file1_name;
`ifdef SIMULATE
initial begin
if (!$value$plusargs("tgen_seq=%s", file1_name)) file1_name = "tgen_seq.dat";
file1 = $fopen(file1_name, "r");
end
`endif // `ifdef SIMULATE
integer rc = 2;
reg [31:0] control_data, cd;
reg [16:0] control_addr, ca;
reg control_strobe = 0;
integer control_cnt = 0;
integer wait_horizon = 5;
`ifdef SIMULATE
always @(posedge clk) begin
control_cnt <= control_cnt + 1;
if (control_cnt > wait_horizon && control_cnt % 3 == 1 && rc == 2) begin
rc = $fscanf(file1, "%d %d\n", ca, cd);
if (rc == 2) begin
if (ca == 555) begin
$display("stall %d cycles", cd);
wait_horizon = control_cnt + cd;
end else begin
$display("local bus[%d] = 0x%x (%d)", ca, cd, cd);
control_data <= cd;
control_addr <= ca;
control_strobe <= 1;
end
end
end else begin
control_data <= 32'hx;
control_addr <= 7'hx;
control_strobe <= 0;
end
end // always @ (posedge clk)
`endif // `ifdef SIMULATE
wire dests_write = control_addr[16:12] == 1; // matches addresses 4096-8191; see tgen_seq.dat
reg trig = 0;
// cc==90 trig will be ignored
always @(posedge clk) trig <= cc == 70 || cc == 90 || cc == 130 || cc == 170 || cc == 210;
reg bank_next = 0;
always @(posedge clk) if (cc == 60 || cc == 150) bank_next <= ~bank_next;
wire collision;
wire [31:0] lbo_data;
wire lbo_write;
wire [16:0] lbo_addr;
wire [3:0] status;
wire [31:0] delay_pc_XXX = 0; // dummy
tgen dut (
.clk(clk),
.trig(trig),
.collision(collision),
.lb_data(control_data),
.lb_write(control_strobe),
.lb_addr(control_addr),
.bank_next(bank_next),
.status(status),
.addr_padding(1'b0),
.dests_write(dests_write),
.delay_pc_XXX(delay_pc_XXX),
.lbo_data(lbo_data),
.lbo_write(lbo_write),
.lbo_addr(lbo_addr)
);
`ifdef SIMULATE
always @(negedge clk) begin
if (lbo_write) $display("slave bus[%d] = 0x%x (%d)", lbo_addr, lbo_data, lbo_data);
end
`endif // `ifdef SIMULATE
endmodule
| 6.817933 |
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