code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module f2_test (
input [2:0] in,
output out
);
assign out = (in[0] ^ in[1] ^ in[2]);
endmodule
| 6.539927 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
| 7.868877 |
module Register (
input CLK,
input I_0_X,
input [4:0] I_0_Y,
input I_1_X,
input [4:0] I_1_Y,
output O_0_X,
output [4:0] O_0_Y,
output O_1_X,
output [4:0] O_1_Y
);
wire [11:0] reg_P12_inst0_out;
wire [11:0] reg_P12_inst0_in;
assign reg_P12_inst0_in = {I_1_Y, I_1_X, I_0_Y, I_0_X};
coreir_reg #(
.clk_posedge(1'b1),
.init(12'h000),
.width(12)
) reg_P12_inst0 (
.clk(CLK),
.in (reg_P12_inst0_in),
.out(reg_P12_inst0_out)
);
assign O_0_X = reg_P12_inst0_out[0];
assign O_0_Y = {
reg_P12_inst0_out[5],
reg_P12_inst0_out[4],
reg_P12_inst0_out[3],
reg_P12_inst0_out[2],
reg_P12_inst0_out[1]
};
assign O_1_X = reg_P12_inst0_out[6];
assign O_1_Y = {
reg_P12_inst0_out[11],
reg_P12_inst0_out[10],
reg_P12_inst0_out[9],
reg_P12_inst0_out[8],
reg_P12_inst0_out[7]
};
endmodule
| 7.117303 |
module SIPO5 (
input CLK,
input I_0_X,
input [4:0] I_0_Y,
input I_1_X,
input [4:0] I_1_Y,
output O_0_0_X,
output [4:0] O_0_0_Y,
output O_0_1_X,
output [4:0] O_0_1_Y,
output O_1_0_X,
output [4:0] O_1_0_Y,
output O_1_1_X,
output [4:0] O_1_1_Y,
output O_2_0_X,
output [4:0] O_2_0_Y,
output O_2_1_X,
output [4:0] O_2_1_Y,
output O_3_0_X,
output [4:0] O_3_0_Y,
output O_3_1_X,
output [4:0] O_3_1_Y,
output O_4_0_X,
output [4:0] O_4_0_Y,
output O_4_1_X,
output [4:0] O_4_1_Y
);
wire Register_inst0_O_0_X;
wire [4:0] Register_inst0_O_0_Y;
wire Register_inst0_O_1_X;
wire [4:0] Register_inst0_O_1_Y;
wire Register_inst1_O_0_X;
wire [4:0] Register_inst1_O_0_Y;
wire Register_inst1_O_1_X;
wire [4:0] Register_inst1_O_1_Y;
wire Register_inst2_O_0_X;
wire [4:0] Register_inst2_O_0_Y;
wire Register_inst2_O_1_X;
wire [4:0] Register_inst2_O_1_Y;
wire Register_inst3_O_0_X;
wire [4:0] Register_inst3_O_0_Y;
wire Register_inst3_O_1_X;
wire [4:0] Register_inst3_O_1_Y;
wire Register_inst4_O_0_X;
wire [4:0] Register_inst4_O_0_Y;
wire Register_inst4_O_1_X;
wire [4:0] Register_inst4_O_1_Y;
Register Register_inst0 (
.CLK (CLK),
.I_0_X(I_0_X),
.I_0_Y(I_0_Y),
.I_1_X(I_1_X),
.I_1_Y(I_1_Y),
.O_0_X(Register_inst0_O_0_X),
.O_0_Y(Register_inst0_O_0_Y),
.O_1_X(Register_inst0_O_1_X),
.O_1_Y(Register_inst0_O_1_Y)
);
Register Register_inst1 (
.CLK (CLK),
.I_0_X(Register_inst0_O_0_X),
.I_0_Y(Register_inst0_O_0_Y),
.I_1_X(Register_inst0_O_1_X),
.I_1_Y(Register_inst0_O_1_Y),
.O_0_X(Register_inst1_O_0_X),
.O_0_Y(Register_inst1_O_0_Y),
.O_1_X(Register_inst1_O_1_X),
.O_1_Y(Register_inst1_O_1_Y)
);
Register Register_inst2 (
.CLK (CLK),
.I_0_X(Register_inst1_O_0_X),
.I_0_Y(Register_inst1_O_0_Y),
.I_1_X(Register_inst1_O_1_X),
.I_1_Y(Register_inst1_O_1_Y),
.O_0_X(Register_inst2_O_0_X),
.O_0_Y(Register_inst2_O_0_Y),
.O_1_X(Register_inst2_O_1_X),
.O_1_Y(Register_inst2_O_1_Y)
);
Register Register_inst3 (
.CLK (CLK),
.I_0_X(Register_inst2_O_0_X),
.I_0_Y(Register_inst2_O_0_Y),
.I_1_X(Register_inst2_O_1_X),
.I_1_Y(Register_inst2_O_1_Y),
.O_0_X(Register_inst3_O_0_X),
.O_0_Y(Register_inst3_O_0_Y),
.O_1_X(Register_inst3_O_1_X),
.O_1_Y(Register_inst3_O_1_Y)
);
Register Register_inst4 (
.CLK (CLK),
.I_0_X(Register_inst3_O_0_X),
.I_0_Y(Register_inst3_O_0_Y),
.I_1_X(Register_inst3_O_1_X),
.I_1_Y(Register_inst3_O_1_Y),
.O_0_X(Register_inst4_O_0_X),
.O_0_Y(Register_inst4_O_0_Y),
.O_1_X(Register_inst4_O_1_X),
.O_1_Y(Register_inst4_O_1_Y)
);
assign O_0_0_X = Register_inst0_O_0_X;
assign O_0_0_Y = Register_inst0_O_0_Y;
assign O_0_1_X = Register_inst0_O_1_X;
assign O_0_1_Y = Register_inst0_O_1_Y;
assign O_1_0_X = Register_inst1_O_0_X;
assign O_1_0_Y = Register_inst1_O_0_Y;
assign O_1_1_X = Register_inst1_O_1_X;
assign O_1_1_Y = Register_inst1_O_1_Y;
assign O_2_0_X = Register_inst2_O_0_X;
assign O_2_0_Y = Register_inst2_O_0_Y;
assign O_2_1_X = Register_inst2_O_1_X;
assign O_2_1_Y = Register_inst2_O_1_Y;
assign O_3_0_X = Register_inst3_O_0_X;
assign O_3_0_Y = Register_inst3_O_0_Y;
assign O_3_1_X = Register_inst3_O_1_X;
assign O_3_1_Y = Register_inst3_O_1_Y;
assign O_4_0_X = Register_inst4_O_0_X;
assign O_4_0_Y = Register_inst4_O_0_Y;
assign O_4_1_X = Register_inst4_O_1_X;
assign O_4_1_Y = Register_inst4_O_1_Y;
endmodule
| 7.167706 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
| 7.868877 |
module Register (
input I,
output O,
input CLK
);
wire [0:0] reg_P1_inst0_out;
coreir_reg #(
.clk_posedge(1'b1),
.init(1'h0),
.width(1)
) reg_P1_inst0 (
.clk(CLK),
.in (I),
.out(reg_P1_inst0_out)
);
assign O = reg_P1_inst0_out[0];
endmodule
| 7.117303 |
module SIPO5 (
input I,
output [4:0] O,
input CLK
);
wire Register_inst0_O;
wire Register_inst1_O;
wire Register_inst2_O;
wire Register_inst3_O;
wire Register_inst4_O;
Register Register_inst0 (
.I (I),
.O (Register_inst0_O),
.CLK(CLK)
);
Register Register_inst1 (
.I (Register_inst0_O),
.O (Register_inst1_O),
.CLK(CLK)
);
Register Register_inst2 (
.I (Register_inst1_O),
.O (Register_inst2_O),
.CLK(CLK)
);
Register Register_inst3 (
.I (Register_inst2_O),
.O (Register_inst3_O),
.CLK(CLK)
);
Register Register_inst4 (
.I (Register_inst3_O),
.O (Register_inst4_O),
.CLK(CLK)
);
assign O = {
Register_inst4_O, Register_inst3_O, Register_inst2_O, Register_inst1_O, Register_inst0_O
};
endmodule
| 7.167706 |
module test_sipo_basic (
input I,
output [4:0] O,
input CLK
);
wire [4:0] SIPO5_inst0_O;
SIPO5 SIPO5_inst0 (
.I (I),
.O (SIPO5_inst0_O),
.CLK(CLK)
);
assign O = SIPO5_inst0_O;
endmodule
| 7.550389 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
| 7.868877 |
module Register (
input CLK,
input I_X,
input [4:0] I_Y,
output O_X,
output [4:0] O_Y
);
wire [5:0] reg_P6_inst0_out;
wire [5:0] reg_P6_inst0_in;
assign reg_P6_inst0_in = {I_Y, I_X};
coreir_reg #(
.clk_posedge(1'b1),
.init(6'h00),
.width(6)
) reg_P6_inst0 (
.clk(CLK),
.in (reg_P6_inst0_in),
.out(reg_P6_inst0_out)
);
assign O_X = reg_P6_inst0_out[0];
assign O_Y = {
reg_P6_inst0_out[5],
reg_P6_inst0_out[4],
reg_P6_inst0_out[3],
reg_P6_inst0_out[2],
reg_P6_inst0_out[1]
};
endmodule
| 7.117303 |
module SIPO5 (
input CLK,
input I_X,
input [4:0] I_Y,
output O_0_X,
output [4:0] O_0_Y,
output O_1_X,
output [4:0] O_1_Y,
output O_2_X,
output [4:0] O_2_Y,
output O_3_X,
output [4:0] O_3_Y,
output O_4_X,
output [4:0] O_4_Y
);
wire Register_inst0_O_X;
wire [4:0] Register_inst0_O_Y;
wire Register_inst1_O_X;
wire [4:0] Register_inst1_O_Y;
wire Register_inst2_O_X;
wire [4:0] Register_inst2_O_Y;
wire Register_inst3_O_X;
wire [4:0] Register_inst3_O_Y;
wire Register_inst4_O_X;
wire [4:0] Register_inst4_O_Y;
Register Register_inst0 (
.CLK(CLK),
.I_X(I_X),
.I_Y(I_Y),
.O_X(Register_inst0_O_X),
.O_Y(Register_inst0_O_Y)
);
Register Register_inst1 (
.CLK(CLK),
.I_X(Register_inst0_O_X),
.I_Y(Register_inst0_O_Y),
.O_X(Register_inst1_O_X),
.O_Y(Register_inst1_O_Y)
);
Register Register_inst2 (
.CLK(CLK),
.I_X(Register_inst1_O_X),
.I_Y(Register_inst1_O_Y),
.O_X(Register_inst2_O_X),
.O_Y(Register_inst2_O_Y)
);
Register Register_inst3 (
.CLK(CLK),
.I_X(Register_inst2_O_X),
.I_Y(Register_inst2_O_Y),
.O_X(Register_inst3_O_X),
.O_Y(Register_inst3_O_Y)
);
Register Register_inst4 (
.CLK(CLK),
.I_X(Register_inst3_O_X),
.I_Y(Register_inst3_O_Y),
.O_X(Register_inst4_O_X),
.O_Y(Register_inst4_O_Y)
);
assign O_0_X = Register_inst0_O_X;
assign O_0_Y = Register_inst0_O_Y;
assign O_1_X = Register_inst1_O_X;
assign O_1_Y = Register_inst1_O_Y;
assign O_2_X = Register_inst2_O_X;
assign O_2_Y = Register_inst2_O_Y;
assign O_3_X = Register_inst3_O_X;
assign O_3_Y = Register_inst3_O_Y;
assign O_4_X = Register_inst4_O_X;
assign O_4_Y = Register_inst4_O_Y;
endmodule
| 7.167706 |
module: slt_operator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_slt;
// Inputs
reg signed [31:0] X;
reg signed [31:0] Y;
// Outputs
wire signed [31:0] Z;
// Instantiate the Unit Under Test (UUT)
slt_operator uut (
.X(X),
.Y(Y),
.Z(Z)
);
integer error = 0;
initial begin
// Initialize Inputs
X = 0;
Y = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
X = 32'd354; //expect 1
Y = 32'd450;
#10;
Y = 32'd204; // expect 0
#10;
X = ~X + 1; //expect 1
#10;
Y = ~Y + 1; //expect 1
#10;
Y = 32'd450; //expect 0
Y = ~Y + 1;
#10;
end
always @(X, Y) begin
#3;
if((Y > X) && (Z != 1)) begin
$display("ERROR: X = %d, Y = %d, out = %d", X, Y, Z);
error = error +1;
end
if((Y < X) && (Z == 1)) begin
$display("ERROR: X = %d, Y = %d, out = %d", X, Y, Z);
error = error +1;
end
end
endmodule
| 7.050528 |
module datamemory (
write,
addr,
datain,
dataout,
clk,
reset
);
input [31:0] datain;
input [15:0] addr;
input write, clk, reset;
output [31:0] dataout;
reg [31:0] mem[63:0];
assign dataout = mem[addr];
always @(posedge clk) begin
if (reset) begin
mem[0] <= 32'b0000000000000000_0000000000000101;
mem[1] <= 32'b0000000000000000_0000000000011000;
mem[2] <= 32'b0000000000000000_0000000000001010;
mem[3] <= 32'b0000000000000000_0000000000000001;
mem[4] <= 32'b0000000000000000_0000000000001100;
mem[5] <= 32'b0000000000000000_0000000000000000;
mem[6] <= 32'b0000000000000000_0000000000000000;
mem[7] <= 32'b0000000000000000_0000000000000000;
mem[8] <= 32'b0000000000000000_0000000000000000;
mem[9] <= 32'b0000000000000000_0000000000000000;
mem[10] <= 32'b0000000000000000_0000000000000000;
mem[11] <= 32'b0000000000000000_0000000000000000;
mem[12] <= 32'b0000000000000000_0000000000000000;
mem[13] <= 32'b0000000000000000_0000000000000000;
mem[14] <= 32'b0000000000000000_0000000000000000;
mem[15] <= 32'b0000000000000000_0000000000000000;
mem[16] <= 32'b0000000000000000_0000000000000000;
mem[17] <= 32'b0000000000000000_0000000000000000;
mem[18] <= 32'b0000000000000000_0000000000000000;
mem[19] <= 32'b0000000000000000_0000000000000000;
mem[20] <= 32'b0000000000000000_0000000000000000;
mem[21] <= 32'b0000000000000000_0000000000000000;
mem[22] <= 32'b0000000000000000_0000000000000000;
mem[23] <= 32'b0000000000000000_0000000000000000;
mem[24] <= 32'b0000000000000000_0000000000000000;
mem[25] <= 32'b0000000000000000_0000000000000000;
mem[26] <= 32'b0000000000000000_0000000000000000;
mem[27] <= 32'b0000000000000000_0000000000000000;
mem[28] <= 32'b0000000000000000_0000000000000000;
mem[29] <= 32'b0000000000000000_0000000000000000;
mem[30] <= 32'b0000000000000000_0000000000000000;
mem[31] <= 32'b0000000000000000_0000000000000000;
mem[32] <= 32'b0000000000000000_0000000000000000;
end else begin
if (write == 1) mem[addr] <= datain;
end
end
endmodule
| 7.533611 |
module test_spaced_2lvl_penc #(
parameter INPUT_WIDTH = 8192,
parameter PENC1_SIZE = 32,
parameter PENC2_SIZE = 32,
parameter BIN_COUNT = 8,
parameter LARGE_BLOCK = BIN_COUNT*PENC1_SIZE*PENC2_SIZE,
parameter OUTPUT_WIDTH = $clog2(LARGE_BLOCK)
) (
input wire clk,
input wire rst,
input wire [INPUT_WIDTH-1:0] one_hot,
output wire [OUTPUT_WIDTH-1:0] index [BIN_COUNT],
output wire [ BIN_COUNT-1:0] valid,
output wire [ BIN_COUNT-1:0] error,
output wire error_merged
);
wire [BIN_COUNT*OUTPUT_WIDTH-1:0] index_n;
spaced_2lvl_penc #(
.INPUT_WIDTH (INPUT_WIDTH ),
.PENC1_SIZE (PENC1_SIZE ),
.PENC2_SIZE (PENC2_SIZE ),
.BIN_COUNT (BIN_COUNT ),
.LARGE_BLOCK (LARGE_BLOCK ),
.OUTPUT_WIDTH(OUTPUT_WIDTH)
) dut (
.clk(clk),
.rst(rst),
.one_hot(one_hot),
.index(index_n),
.valid(valid),
.error(error)
);
assign error_merged = |error;
genvar i;
generate
for (i = 0; i < BIN_COUNT; i = i + 1) assign index[i] = index_n[i*OUTPUT_WIDTH+:OUTPUT_WIDTH];
endgenerate
integer j; //,k;
initial begin
$dumpfile("sim_results.fst");
for (j = 0; j < BIN_COUNT; j = j + 1) $dumpvars(0, index[j]);
// for (k=0; k<BIN_COUNT*PENC2_SIZE; k=k+1)
// $dumpvars (0,dut.lvl1_index[k]);
#1;
end
endmodule
| 7.880448 |
module test_spcm_nexys3 (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// SPCM interfaces
output wire spcm_cs_n,
output wire spcm_sck,
output wire spcm_mosi,
input wire spcm_miso
);
parameter CLK_FREQ = 100, ADDR_BITS = 24;
wire busy, ack;
wire [31:0] dout;
reg [31:0] data_buf;
reg cs_prev;
always @(posedge clk) begin
if (rst) cs_prev <= 0;
else cs_prev <= cs;
end
reg cs_buf;
always @(posedge clk) begin
if (rst) cs_buf <= 0;
else if (cs & ~cs_prev) cs_buf <= 1;
else if (ack) cs_buf <= 0;
end
spcm_core_nexys3 #(
.ADDR_BITS(ADDR_BITS)
) SPCM_CORE (
.clk(clk),
.rst(rst),
.cs(~cs_prev & cs),
.addr(addr),
.burst(1'b0),
.dout(dout),
.busy(busy),
.ack(ack),
.spcm_cs_n(spcm_cs_n),
.spcm_sck(spcm_sck),
.spcm_mosi(spcm_mosi),
.spcm_miso(spcm_miso)
);
always @(posedge clk) begin
if (rst) data_buf <= 0;
else if (ack) data_buf <= dout;
end
assign data = data_buf;
assign state = {busy, 5'b0, spcm_cs_n, ack};
endmodule
| 8.44029 |
module test_jbimu;
// Inputs
reg clks;
85
reg clock;
reg reset;
reg start;
wire miso;
// Outputs
wire [15:0] roll;
wire [15:0] pitch;
wire [15:0] yaw;
wire [15:0] roll_rate;
wire [15:0] pitch_rate;
wire [15:0] yaw_rate;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire done;
wire mosi;
wire sck;
wire ss;
// Instantiate the Unit Under Test (UUT)
jb_imu uut (
.clock(clock),
.reset(reset),
.start(start),
.roll(roll),
.pitch(pitch),
.yaw(yaw),
.roll_rate(roll_rate),
.pitch_rate(pitch_rate),
.yaw_rate(yaw_rate),
.accel_x(accel_x),
.accel_y(accel_y),
.accel_z(accel_z),
.done(done),
.miso(miso),
.mosi(mosi),
.sck(sck),
.ss(ss)
);
wire slave_done;
reg [7:0] din;
wire [7:0] slave_dout;
spi_slave slave(
.clk(clks),
.rst(reset),
.ss(ss),
86
.mosi(mosi),
.miso(miso),
.sck(sck),
.done(slave_done),
.din(din),
.dout(slave_dout)
);
always #10 clock = ~clock; //50Mhz = 20 ns period
always #20 clks = ~clks; //25 Mhz slave clock
always @(slave_done) begin
if(slave_done) begin
din = din + 1'b1;
end
end
initial begin
// Initialize Inputs
clock = 0;
clks=0;
reset = 0;
start = 0;
din = 0;
// Wait 100 ns for global reset to finish
reset = 1;
#100;
reset = 0;
// Add stimulus here
din = 8'h00;
#20;
start = 1;
#20;
start = 0;
#10000;
end
endmodule
| 6.632599 |
module test_spils;
// Inputs
reg iocs;
reg [2:0] ioaddr;
reg [15:0] din;
reg iowr;
reg sdi;
reg clk;
reg rst;
// Outputs
wire [15:0] dout;
wire sdo;
wire sck;
wire ss0n, ss1n;
// Instantiate the Unit Under Test (UUT)
spils uut (
.iocs(iocs),
.ioaddr(ioaddr),
.din(din),
.iowr(iowr),
.dout(dout),
.sdi(sdi),
.sdo(sdo),
.sck(sck),
.ss0n(ss0n),
.ss1n(ss1n),
.clk(clk),
.rst(rst)
);
initial begin
// Initialize Inputs
iocs = 0;
ioaddr = 0;
din = 0;
iowr = 0;
sdi = 0;
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// Reset
#5 clk = 0;
rst = 1;
#5 clk = 1;
#5 clk = 0;
rst = 0;
#5 clk = 1;
// SS on
#5 clk = 0;
iocs = 1;
ioaddr = 3;
iowr = 1;
din = 0;
#5 clk = 1;
// output byte 1
#5 clk = 0;
iocs = 1;
ioaddr = 0;
iowr = 1;
din = 8'hFF;
#5 clk = 1;
// SDI = 0
repeat (256) begin
#5 clk = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
din = 0;
sdi = 0; // 00
#5 clk = 1;
end
// input byte
#5 clk = 0;
iocs = 1;
ioaddr = 0;
sdi = 0;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
ioaddr = 0;
iowr = 0;
#5 clk = 1;
// output byte 2
#5 clk = 0;
iocs = 1;
ioaddr = 0;
iowr = 1;
din = 8'hAA;
#5 clk = 1;
// generate data on SDI
repeat (4) begin
repeat (32) begin
#5 clk = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
din = 0;
sdi = 0; // 55
#5 clk = 1;
end
repeat (32) begin
#5 clk = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
din = 0;
sdi = 1;
#5 clk = 1;
end
end
// input byte
#5 clk = 0;
iocs = 1;
ioaddr = 0;
sdi = 0;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
ioaddr = 0;
iowr = 0;
#5 clk = 1;
// SS off
#5 clk = 0;
iocs = 1;
ioaddr = 2;
iowr = 1;
din = 0;
#5 clk = 1;
// change address
#5 clk = 0;
iocs = 1;
ioaddr = 1;
iowr = 1;
din = 1;
#5 clk = 1;
// SS on
#5 clk = 0;
iocs = 1;
ioaddr = 3;
iowr = 1;
din = 0;
#5 clk = 1;
// output byte 3
#5 clk = 0;
iocs = 1;
ioaddr = 0;
iowr = 1;
din = 8'h55;
#5 clk = 1;
// generate data on SDI
repeat (4) begin
repeat (32) begin
#5 clk = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
din = 0;
sdi = 1; // AA
#5 clk = 1;
end
repeat (32) begin
#5 clk = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
din = 0;
sdi = 0;
#5 clk = 1;
end
end
// input byte
#5 clk = 0;
iocs = 1;
ioaddr = 0;
sdi = 0;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
ioaddr = 0;
iowr = 0;
#5 clk = 1;
// output byte 4
#5 clk = 0;
iocs = 1;
ioaddr = 0;
iowr = 1;
din = 8'h00;
#5 clk = 1;
// SDI = FF
repeat (256) begin
#5 clk = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
din = 0;
sdi = 1; // FF
#5 clk = 1;
end
// SS off
#5 clk = 0;
iocs = 1;
ioaddr = 2;
iowr = 1;
din = 0;
#5 clk = 1;
// input byte
#5 clk = 0;
iocs = 1;
ioaddr = 0;
sdi = 0;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
ioaddr = 0;
iowr = 0;
#5 clk = 1;
#5 clk = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
end
endmodule
| 6.866726 |
module test_spi_master (
input nrst, //Асинхронный сброс
input clk, //Тактовый генератор
//input start, //Старт цикла передачи
//output [(1<<3)-1:0]data_out,
//output cyc_num,
//output data_rdy,
//output busy,
output spi_cs, // выбор кристалла
output spi_clk,
output spi_mosi,
input spi_miso,
output RsTx // передатчик UART
);
wire rst;
assign rst = ~nrst;
wire [7:0] data_out;
wire [1:0] cyc_num;
wire data_rdy;
wire busy;
wire tickTimer;
// таймер
timer #(
.period(5_000_000)
) timertickTimer (
.clk(clk),
.rst(rst),
.out(tickTimer)
);
reg [7:0] dataToSPI; //данные для отправки
spi_master #(
.Nd(3), //Размерность шины данных 2^Nd
.Nc(3), //Разрядность количества циклов приемо/передачи за одно соединение
.THalfSpiClk(50), //Полупериод SPI Clock в тактах clk
.TCS(100) //Время между сменой уровня CS и первым импульсом spi_clk
) spi_tx (
.rst(rst), //Асинхронный сброс
.clk(clk), //Тактовый генератор
.start(tickTimer), //Старт цикла передачи
.cyc_count(3), //Количество циклов, передачи данных
.data_in(dataToSPI), //Даные, которые надо послать в ближайший возможный момент
.data_out(data_out), //Принятые данные
.cyc_num(cyc_num), //Текущий номер цикла приемо/передачи за одно соединение
.data_rdy(data_rdy), //Данные в data_out обновлены, а данные из data_in должны быть обновлены на следующем такте после получения data_rdy
.busy(busy), //Индикатор активного цикла приема/передачи данных
//Интерфейс SPI
.spi_cs(spi_cs), //Сhip Select
.spi_clk(spi_clk), //Clock
.spi_mosi(spi_mosi), //MOSI (Master output, Slave input)
.spi_miso(spi_miso) //MISO (Master input, Slave output)
);
// сигнал начала передачи данных по UART
reg uartStartSend;
// автомат формаирования последовательноси байт для передачи по SPI
always @(posedge clk, posedge rst)
if (rst) begin
dataToSPI <= 8'h0B; //значение 0-го байта
end else begin
// если принят 3-й байт - передать его по UART
if (data_rdy & (cyc_num == 2)) uartStartSend <= 1; // старт передачи
else uartStartSend <= 0;
if (data_rdy) begin
if (cyc_num == 0) // значение 1-го байта
dataToSPI <= 8'h07;
else if (cyc_num == 1) // значение 2-го байта
dataToSPI <= 8'h0E;
else dataToSPI <= 8'h0B; // значение 0-го и последующих байт
end
end
// передатчик UART
uart_tx #(
.T(921600)
) uarttx (
.clk(clk),
.rst(rst),
.data(data_out),
.start(uartStartSend),
.dataOut(RsTx) /*, .ready(wTxReadyOut)*/
);
endmodule
| 7.286245 |
module: spi_sniffer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_spi_sniffer2;
// Inputs
reg spi_cs;
reg spi_clk;
reg spi_si;
reg spi_so;
reg clk;
reg reset;
reg enable;
// Outputs
wire [31:0] data;
wire data_stb;
wire [21:0] addr_hi;
wire [1:0] addr_lo;
wire addr_changed;
wire load;
wire shift;
// Instantiate the Unit Under Test (UUT)
spi_sniffer uut (
.spi_cs(spi_cs),
.spi_clk(spi_clk),
.spi_si(spi_si),
.spi_so(spi_so),
.clk(clk),
.reset(reset),
.data(data),
.data_stb(data_stb),
.enable(enable),
.addr_hi(addr_hi),
.addr_lo(addr_lo),
.addr_changed(addr_changed),
.load(load),
.shift(shift)
);
parameter PERIOD = 12;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 100;
initial // Clock process for clk
begin
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
reg [7:0] shift_reg;
always @(posedge clk)
begin
if (load)
begin
shift_reg <= 0;
case (addr_hi <<2 | addr_lo)
0: shift_reg <= 8'hCC;
1: shift_reg <= 8'hBB;
2: shift_reg <= 8'h00;
3: shift_reg <= 8'h20;
24'h2002: shift_reg <= 8'h23;
24'h2003: shift_reg <= 8'h89;
24'h13246: shift_reg <= 8'h02;
24'h13247: shift_reg <= 8'h00;
24'h2004: shift_reg <= 8'h77;
24'h2005: shift_reg <= 8'h64;
24'h2006: shift_reg <= 8'h0c;
24'h2007: shift_reg <= 8'h00;
24'h2008: shift_reg <= 8'hcb;
24'h2009: shift_reg <= 8'h63;
24'h200A: shift_reg <= 8'hAA;
24'h200B: shift_reg <= 8'h01;
24'he8ec: shift_reg <= 8'hA1;
24'he8ed: shift_reg <= 8'h01;
24'he796: shift_reg <= 8'h95;
24'he797: shift_reg <= 8'hc0;
endcase
end
if (shift)
shift_reg <= shift_reg << 1;
end
wire so;
assign so = shift_reg[7];
initial begin
// Initialize Inputs
spi_cs = 0;
spi_clk = 0;
spi_si = 0;
spi_so = 0;
reset = 0;
enable = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1;
#124;
reset = 0;
#120;
enable = 1;
`include "tb.v"
end
endmodule
| 6.527639 |
module test_float_sqrt;
reg l_r_clk;
reg l_r_rst;
wire [15:0] result;
reg [15:0] l_r_radicand;
// sqrt #(.WIDTH(11)) l_m_sqrt(
// .o_w_root(l_w_root),
// .o_w_rdy(l_w_rdy),
// .i_w_clk(l_r_clk),
// .i_w_rst(l_r_rst),
// .i_w_radicand(l_r_rad)
// );
float_sqrt l_m_float_sqrt (
.o_w_result(result),
.i_w_clk(l_r_clk),
.i_w_rst(l_r_rst),
.i_w_radicand(l_r_radicand)
);
always #2 l_r_clk = ~l_r_clk;
//Simulation tests
initial begin
//wave files
$dumpfile("test.vcd");
// dumpp all variables
$dumpvars;
l_r_clk = 0;
// input: 81
// result: 9
l_r_radicand = 16'b0101010100010000;
l_r_rst = 1;
#4 l_r_rst = 0;
#100
// input: 0.03077
// result: 0.1756
l_r_radicand = 16'b0010011111100000;
l_r_rst = 1;
#4 l_r_rst = 0;
#100
// input: 1.4991
// result: 1.224
l_r_radicand = 16'b0011110111111111;
l_r_rst = 1;
#4 l_r_rst = 0;
#100
// input: 512
// result:
l_r_radicand = 16'b0110000000000000;
l_r_rst = 1;
#4 l_r_rst = 0;
#100
//finish the simulation
$finish;
end
endmodule
| 6.602395 |
module test_SRAM;
parameter CYCLE = 10; // use "CYCLE" to represent the period
parameter END_CYCLE = 20000;
parameter DRAM_DATA_WIDTH = 32;
parameter DRAM_ADDR_WIDTH = 13;
parameter SRAM_DATA_WIDTH = 4;
parameter SRAM_ADDR_WIDTH = 7;
parameter DATA_WIDTH = 8;
///// declare input(reg) and output(wire) /////
reg clk;
reg rst_n;
wire DRAM_data_valid;
wire [DRAM_DATA_WIDTH-1:0] DRAM_data_out;
// dram write
reg en_a;
reg [DRAM_ADDR_WIDTH-1:0] addr_a;
reg [DRAM_DATA_WIDTH-1:0] data;
// dram read
wire en_b;
wire [DRAM_ADDR_WIDTH-1:0] addr_b;
wire [DRAM_DATA_WIDTH-1:0] q;
// steganography
reg top_enable;
reg [DATA_WIDTH-1:0] width;
reg [DATA_WIDTH-1:0] height;
wire DRAM_enable;
wire ascii_valid, done;
wire [DATA_WIDTH-1:0] ascii_out;
///// declare module /////
two_port_ram_sclk #(
.DATA_WIDTH(DRAM_DATA_WIDTH),
.ADDR_WIDTH(DRAM_ADDR_WIDTH)
) u_dram (
.clk(clk),
.en_a(en_a),
.addr_a(addr_a),
.data(data),
.en_b(en_b),
.addr_b(addr_b),
.q(q)
);
dram_read_controller #(
.DATA_WIDTH(DRAM_DATA_WIDTH),
.ADDR_WIDTH(DRAM_ADDR_WIDTH)
) u_dram_controller (
.clk(clk),
.rst_n(rst_n),
.enable(DRAM_enable),
.valid(DRAM_data_valid),
.out(DRAM_data_out),
// connect dram
.dram_out(q),
.dram_read_en(en_b),
.dram_addr(addr_b)
);
steganography u_steganography (
.clk(clk),
.rst_n(rst_n),
.enable(top_enable),
.width(width),
.height(height),
.DRAM_enable(DRAM_enable),
.DRAM_data_valid(DRAM_data_valid),
.DRAM_data(DRAM_data_out),
.valid(ascii_valid),
.out(ascii_out),
.done(done)
);
///// fsdb /////
initial begin
$fsdbDumpfile("sram.fsdb");
$fsdbDumpvars(0, test_SRAM, "+mda");
end
///// clock /////
always #(CYCLE / 2) clk = ~clk;
initial begin
// initialize the input signals
clk = 0;
top_enable = 0;
rst_n = 0;
width = 0;
height = 0;
#(CYCLE) rst_n = 1;
// initialize dram
init_dram();
$display("%d ns: Initialize DRAM finish", $time);
#(CYCLE);
// read data from image and write to dram
read_image_to_dram("./image/chess_48x48_en.yuv");
$display("%d ns: Read image finish", $time);
#(CYCLE);
// test SRAM
en_a = 0;
data = 0;
addr_a = 0;
#(CYCLE) width = 48;
height = 48;
#(CYCLE) top_enable = 1;
end
// check first 3 rows data in SRAM
integer i, j, t, r, filetxt, lsb, lsb_golden, char, error;
initial begin
filetxt = $fopen("./chess.txt", "r");
error = 0;
@(negedge clk);
// you can modify the condition for checking the data in SRAM
wait (top_enable === 1); // wait steganography starting
wait (u_dram_controller.address === width); // wait dram read three rows
#(CYCLE);
@(negedge clk);
$display("%d ns: Begin to compare sram and golden", $time);
for (t = 0; t < 3; t = t + 1) begin // 3 rows
for (i = 0; i < width / 3; i = i + 1) begin // all blocks
lsb_golden = 0;
for (j = 0; j < 3; j = j + 1) begin // read 3 char from golden lsb data
r = $fscanf(filetxt, "%c", char);
while (!(char == "0" | char == "1"))
r = $fscanf(filetxt, "%c", char); // deal with new line
char = char - "0";
lsb_golden = lsb_golden | (char << j);
end
lsb = u_steganography.u_SRAM.memory[t*40+i];
if (lsb_golden !== lsb) begin
$display(" Error at addr %4d, sram %b golden %b", t * 40 + i, lsb[3:0],
lsb_golden[3:0]);
error = error + 1;
end
end
end
if (error == 0) begin
$display("%d ns: First 3 rows data in SRAM are the same!", $time);
$finish;
end else begin
$display("%d ns: There are %d errors in SRAM", $time, error);
$finish;
end
end
initial begin
#(CYCLE * END_CYCLE);
$display("%d ns: END CYCLE! Try to enable 'DRAM_enable' in 'steganography'", $time);
$finish;
end
`include "simple_task.v"
endmodule
| 7.71558 |
module test_sram_if (
input clk,
input rst,
input [`WIDTH-1:0] RAM_D_pi,
output [`WIDTH-1:0] RAM_D_po,
output RAM_D_poe,
output [`DEPTH-1:0] RAM_A,
output RAM_WEn,
output RAM_CENn,
output RAM_LDn,
output RAM_OEn,
output RAM_CE1n,
output reg correct
);
reg [`DEPTH-1:0] write_count;
reg [`DEPTH-1:0] read_count;
reg enable;
reg write;
reg write_cycle;
reg read_cycle;
reg enable_reads;
reg [ 18:0] address;
reg [ 17:0] data_out;
wire [ 17:0] data_in;
wire data_in_valid;
reg [ 17:0] check_data;
reg [ 17:0] check_data_old;
reg [ 17:0] check_data_old2;
//
// Create counter that generates both external modulo 2^19 address and modulo 2^18 data to test RAM.
//
always @(posedge clk)
if (rst) begin
write_count <= 19'h0;
read_count <= 19'h0;
end else if (write_cycle) // Write cycle
if (write_count == 19'h7FFFF) begin
write_count <= 19'h0;
end else begin
write_count <= write_count + 1'b1;
end
else if (read_cycle) // Read cycle
if (read_count == 19'h7FFFF) begin
read_count <= 19'h0;
end else begin
read_count <= read_count + 1'b1;
end
always @(posedge clk)
if (rst) begin
enable_reads <= 0;
read_cycle <= 0;
write_cycle <= 0;
end else begin
write_cycle <= ~write_cycle;
if (enable_reads) read_cycle <= write_cycle;
if (write_count == 15) // Enable reads 15 writes after reset terminates.
enable_reads <= 1;
end // else: !if(rst)
always @(posedge clk)
if (rst) begin
enable <= 0;
end else if (write_cycle) begin
address <= write_count;
data_out <= write_count[17:0];
enable <= 1;
write <= 1;
end else if (read_cycle) begin
address <= read_count;
check_data <= read_count[17:0];
check_data_old <= check_data;
check_data_old2 <= check_data_old;
enable <= 1;
write <= 0;
end else enable <= 0;
always @(posedge clk)
if (data_in_valid) begin
correct <= (data_in == check_data_old2);
end
nobl_if nobl_if_i1 (
.clk(clk),
.rst(rst),
.RAM_D_pi(RAM_D_pi),
.RAM_D_po(RAM_D_po),
.RAM_D_poe(RAM_D_poe),
.RAM_A(RAM_A),
.RAM_WEn(RAM_WEn),
.RAM_CENn(RAM_CENn),
.RAM_LDn(RAM_LDn),
.RAM_OEn(RAM_OEn),
.RAM_CE1n(RAM_CE1n),
.address(address),
.data_out(data_out),
.data_in(data_in),
.data_in_valid(data_in_valid),
.write(write),
.enable(enable)
);
wire [35:0] CONTROL0;
reg [7:0] data_in_reg, data_out_reg, address_reg;
reg data_in_valid_reg, write_reg, enable_reg, correct_reg;
always @(posedge clk) begin
data_in_reg <= data_in[7:0];
data_out_reg <= data_out[7:0];
data_in_valid_reg <= data_in_valid;
write_reg <= write;
enable_reg <= enable;
correct_reg <= correct;
address_reg <= address;
end
icon icon_i1 (.CONTROL0(CONTROL0));
ila ila_i1 (
.CLK(clk),
.CONTROL(CONTROL0),
// .TRIG0(address_reg),
.TRIG0(data_in_reg[7:0]),
.TRIG1(data_out_reg[7:0]),
.TRIG2(address_reg[7:0]),
.TRIG3({data_in_valid_reg, write_reg, enable_reg, correct_reg})
);
endmodule
| 7.093279 |
module test_sram_sword (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// SRAM interfaces
output wire sram_ce_n,
output wire sram_oe_n,
output wire sram_we_n,
output wire [ADDR_BITS-1:2] sram_addr,
input wire [47:0] sram_din,
output wire [47:0] sram_dout
);
parameter CLK_FREQ = 100, ADDR_BITS = 22;
wire busy, ack;
wire [31:0] dout;
reg [31:0] data_buf;
reg cs_prev;
always @(posedge clk_bus) begin
if (rst) cs_prev <= 0;
else cs_prev <= cs;
end
reg cs_buf;
always @(posedge clk_bus) begin
if (rst) cs_buf <= 0;
else if (cs & ~cs_prev) cs_buf <= 1;
else if (ack) cs_buf <= 0;
end
wb_sram_sword #(
.ADDR_BITS(ADDR_BITS),
.HIGH_ADDR(0)
) WB_SRAM (
.clk(clk),
.rst(rst),
.sram_ce_n(sram_ce_n),
.sram_oe_n(sram_oe_n),
.sram_we_n(sram_we_n),
.sram_addr(sram_addr),
.sram_din(sram_din),
.sram_dout(sram_dout),
.wbs_clk_i(clk_bus),
.wbs_cyc_i(cs_buf),
.wbs_stb_i(cs_buf),
.wbs_addr_i({22'h0, addr}),
.wbs_cti_i(3'b0),
.wbs_bte_i(2'b0),
.wbs_sel_i(4'b1001),
.wbs_we_i(we),
.wbs_data_i(32'h12345678),
.wbs_data_o(dout),
.wbs_ack_o(ack)
);
always @(posedge clk_bus) begin
if (rst) data_buf <= 0;
else if (ack) data_buf <= dout;
end
assign data = data_buf;
assign state = {busy, sram_ce_n, sram_oe_n, sram_we_n, 3'b0, ack};
endmodule
| 7.142417 |
module test_sreg8;
wire [7:0] q;
reg si, en, ck, nr;
// Instancia el shift register de 8 bits
sreg8 dut (
.Q(q),
.ShiftIn(si),
.Enable(en),
.Clock(ck),
.nReset(nr)
);
// Reset del shift register
initial begin
#10 nr = 0;
#10 nr = 1;
end
initial begin
wait (nr == 1); // Espera que termine el Reset
#10 si = 1;
en = 1;
nr = 1;
ck = 0;
repeat (8) begin // ingresa 8 1s
#5 ck = 1;
#5 ck = 0;
end
#10 si = 0;
en = 1;
nr = 1;
ck = 0;
repeat (8) begin // ingresa 8 0s
#5 ck = 1;
#5 ck = 0;
end
#10 si = 1;
en = 1;
nr = 1;
ck = 0;
repeat (4) begin // ingresa 4 1s
#5 ck = 1;
#5 ck = 0;
end
en = 0; // deshabilikta Enable
repeat (4) begin // por 4 ciclos de clock
#5 ck = 1;
#5 ck = 0;
end
en = 1; // rehabilita enable
repeat (4) begin
#5 ck = 1;
#5 ck = 0;
end
end
endmodule
| 7.060803 |
module test_srff ();
reg S, R, clk;
wire Q, QPrima;
srff_clk srff_1 (
S,
R,
clk,
Q,
QPrima
);
initial begin
$dumpfile("out.vcd");
$dumpvars(1, test_srff);
clk = 1;
S = 0;
R = 0;
#20 S = 1;
R = 0;
#20 S = 0;
R = 0;
#20 S = 0;
R = 1;
#20 S = 0;
R = 0;
#20 S = 1;
R = 1;
#20 #20 $finish;
end
endmodule
| 6.569613 |
module test_srff ();
reg S, R;
wire Q, QPrima;
srff srff_1 (
S,
R,
Q,
QPrima
);
initial begin
$dumpfile("out.vcd");
$dumpvars(1, test_srff);
S = 0;
R = 0;
#20 S = 1;
R = 0;
#20 S = 0;
R = 0;
#20 S = 0;
R = 1;
#20 S = 0;
R = 0;
#20 S = 1;
R = 1;
#20 #20 $finish;
end
endmodule
| 6.569613 |
module top (
input clk,
input rst,
input [15:0] switch,
output reg [ 3:0] in, // IN4, IN3, IN2, IN1
output [ 1:0] pwm, // {left, right}
output [ 3:0] led,
output led15
);
assign led15 = switch[15];
assign led = in;
assign SPIN_TIME = 50_000;
reg [31:0] cnt;
reg [ 1:0] state;
assign pwm = 2'b11;
always @(posedge clk) begin
if (cnt >= SPIN_TIME) begin
cnt <= 32'd0;
state <= state + 2'd1;
end else begin
cnt <= cnt + 32'd1;
state <= state;
end
end
always @(*) begin
if (switch[15] == 1'b0) begin
case (state)
2'd0: in = 4'b0101;
2'd1: in = 4'b1001;
2'd2: in = 4'b1010;
2'd3: in = 4'b0110;
endcase
end else begin
case (state)
2'd0: in = 4'b0101;
2'd1: in = 4'b0110;
2'd2: in = 4'b1010;
2'd3: in = 4'b1001;
endcase
end
end
endmodule
| 7.233807 |
module: step_gen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_step_gen;
// Inputs
reg clk;
reg reset;
reg signed [31:0] velocity;
wire step;
wire dir;
wire signed [31:0] position;
// Instantiate the Unit Under Test (UUT)
step_gen uut (
.clk(clk),
.reset(reset),
.velocity(velocity),
.step(step),
.dir(dir),
.position(position)
);
initial begin
// Initialize Inputs
reset = 0;
velocity = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 1;
#37;
reset = 0;
velocity = 824633;
#100000000;
velocity = -824633;
// Add stimulus here
end
initial begin
#100;
forever
begin
clk = 1;
#10;
clk = 0;
#10;
end;
end
endmodule
| 7.24573 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = d;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction happens, increment data
d <= d + 8'd1;
end
end
endmodule
| 6.890266 |
module test_stream_buf;
reg clk = 0;
reg rst = 0;
reg en = 0;
wire [7:0] data_in;
wire [7:0] data_out;
wire valid_in;
wire valid_out;
reg ready_in = 0;
wire ready_out;
always #5 clk = ~clk;
always @(posedge clk) begin
if (ready_in && valid_out) begin
$display("slave received %d", data_out);
end
if (valid_in && ready_out) begin
$display("master sent %d", data_in);
end
end
initial begin
$dumpfile("test_stream_buf.vcd");
$dumpvars(0);
$monitor(, $time, " en=%b,valid_in=%b,ready_out=%b,valid_out=%b,ready_in=%b", en, valid_in,
ready_out, valid_out, ready_in);
repeat (5) @(posedge clk);
#3 rst <= 1;
repeat (1) @(posedge clk);
#3 rst <= 0;
repeat (5) @(posedge clk);
#3 en <= 1;
repeat (5) @(posedge clk);
#3 ready_in <= 1;
repeat (5) @(posedge clk);
#3 ready_in <= 0;
repeat (5) @(posedge clk);
#3 ready_in <= 1;
repeat (5) @(posedge clk);
#3 ready_in <= 0;
repeat (5) @(posedge clk);
#3 ready_in <= 1;
repeat (5) @(posedge clk);
#3 en <= 0;
repeat (5) @(posedge clk);
#3 ready_in <= 0;
repeat (5) @(posedge clk);
#3 en <= 1;
repeat (5) @(posedge clk);
#3 ready_in <= 1;
repeat (5) @(posedge clk);
#3 ready_in <= 0;
repeat (5) @(posedge clk);
#3 en <= 0;
ready_in <= 1;
repeat (5) @(posedge clk);
$finish;
end
stream_gen gen (
.i_clk(clk),
.i_enable(en),
.i_ready(ready_out),
.o_data(data_in),
.o_valid(valid_in)
);
wire [7:0] t12_data;
wire t12_valid;
wire t12_ready;
stream_buf dut1 (
.i_clk (clk),
.i_rst (rst),
//
.i_data (data_in),
.i_valid(valid_in),
.o_ready(ready_out),
//
.o_data (t12_data),
.o_valid(t12_valid),
.i_ready(t12_ready)
);
stream_buf dut2 (
.i_clk (clk),
.i_rst (rst),
//
.i_data (t12_data),
.i_valid(t12_valid),
.o_ready(t12_ready),
//
.o_data (data_out),
.o_valid(valid_out),
.i_ready(ready_in)
);
endmodule
| 6.592789 |
module test_stub_scan ( /*AUTOARG*/
// Outputs
mux_drive_disable,
mem_write_disable,
sehold,
se,
testmode_l,
mem_bypass,
so_0,
so_1,
so_2,
// Inputs
ctu_tst_pre_grst_l,
arst_l,
global_shift_enable,
ctu_tst_scan_disable,
ctu_tst_scanmode,
ctu_tst_macrotest,
ctu_tst_short_chain,
long_chain_so_0,
short_chain_so_0,
long_chain_so_1,
short_chain_so_1,
long_chain_so_2,
short_chain_so_2
);
input ctu_tst_pre_grst_l;
input arst_l; // no longer used
input global_shift_enable;
input ctu_tst_scan_disable; // redefined as pin_based_scan
input ctu_tst_scanmode;
input ctu_tst_macrotest;
input ctu_tst_short_chain;
input long_chain_so_0;
input short_chain_so_0;
input long_chain_so_1;
input short_chain_so_1;
input long_chain_so_2;
input short_chain_so_2;
output mux_drive_disable;
output mem_write_disable;
output sehold;
output se;
output testmode_l;
output mem_bypass;
output so_0;
output so_1;
output so_2;
wire pin_based_scan;
wire short_chain_en;
wire short_chain_select;
// INTERNAL CLUSTER CONNECTIONS
//
// Scan Chain Hookup
// =================
//
// Scan chains have two configurations: long and short.
// The short chain is typically the first tenth of the
// long chain. The short chain should contain memory
// collar flops for deep arrays. The CTU determines
// which configuration is selected. Up to three chains
// are supported.
//
// The scanout connections from the long and short
// chains connect to the following inputs:
//
// long_chain_so_0, short_chain_so_0 (mandatory)
// long_chain_so_1, short_chain_so_1 (optional)
// long_chain_so_2, short_chain_so_2 (optional)
//
// The test stub outputs should connect directly to the
// scanout port(s) of the cluster:
//
// so_0 (mandatory), so_1 (optional), so_2 (optional)
//
//
// Static Output Signals
// =====================
//
// testmode_l
//
// Local testmode control for overriding gated
// clocks, asynchronous resets, etc. Asserted
// for all shift-based test modes.
//
// mem_bypass
//
// Memory bypass control for arrays without output
// flops. Allows testing of shadow logic. Asserted
// for scan test; de-asserted for macrotest.
//
//
// Dynamic Output Signals
// ======================
//
// sehold
//
// The sehold signal needs to be set for macrotest
// to allow holding flops in the array collars
// to retain their shifted data during capture.
// Inverted version of scan enable during macrotest.
//
// mux_drive_disable (for mux/long chain protection)
//
// Activate one-hot mux protection circuitry during
// scan shift and reset. Formerly known as rst_tri_en.
// Also used by long chain memories with embedded
// control.
//
// mem_write_disable (for short chain protection)
//
// Protects contents of short chain memories during
// shift and POR.
//
// se
assign mux_drive_disable = ~ctu_tst_pre_grst_l | short_chain_select | se;
assign mem_write_disable = ~ctu_tst_pre_grst_l | se;
assign sehold = ctu_tst_macrotest & ~se;
assign se = global_shift_enable;
assign testmode_l = ~ctu_tst_scanmode;
assign mem_bypass = ~ctu_tst_macrotest & ~testmode_l;
assign pin_based_scan = ctu_tst_scan_disable;
assign short_chain_en = ~(pin_based_scan & se);
assign short_chain_select = ctu_tst_short_chain & ~testmode_l & short_chain_en;
assign so_0 = short_chain_select ? short_chain_so_0 : long_chain_so_0;
assign so_1 = short_chain_select ? short_chain_so_1 : long_chain_so_1;
assign so_2 = short_chain_select ? short_chain_so_2 : long_chain_so_2;
endmodule
| 7.575823 |
module test_sub16 (
input [15:0] a,
input [15:0] b,
output [15:0] out
);
assign out = a - b;
endmodule
| 6.564557 |
module test_subtracter;
// Inputs
reg [31:0] a;
reg [31:0] b;
reg c_in;
// Outputs
wire [31:0] sum;
wire c_out;
// Instantiate the Unit Under Test (UUT)
Sub_32 uut (
.sum(sum),
.c_out(c_out),
.a(a),
.b(b),
.c_in(c_in)
);
initial begin
// Initialize Inputs
a = 12;
b = 2;
c_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.55589 |
module TOP;
//ALU inputs
reg a, b, c;
wire sum1;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 0;
b = 0;
c = 0;
#`cycle //1
if(sum1 != a^b^c)
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 1;
b = 0;
c = 0;
#`cycle //3
if(sum1 != a^b^c)
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 0;
b = 1;
c = 0;
#`cycle //5
if(sum1 != a^b^c)
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 0;
b = 0;
c = 1;
#`cycle //7
if(sum1 != a^b^c)
begin
error_free = 0;
error = 1;
end
#`error_time //8
error = 0;
a = 1;
b = 1;
c = 0;
#`cycle //9
if(sum1 != a^b^c)
begin
error_free = 0;
error = 1;
end
#`error_time //10
error = 0;
a = 1;
b = 0;
c = 1;
#`cycle //11
if(sum1 != a^b^c)
begin
error_free = 0;
error = 1;
end
#`error_time //12
error = 0;
a = 0;
b = 1;
c = 1;
#`cycle //13
if(sum1 != a^b^c)
begin
error_free = 0;
error = 1;
end
#`error_time //14
error = 0;
a = 1;
b = 1;
c = 1;
#`cycle //15
if(sum1 != a^b^c)
begin
error_free = 0;
error = 1;
end
#`error_time //16
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("sum1.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(error)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, c = %x, sum = %x",
$time a, b, c, sum1);
sum1 sum1_test(sum1, a, b, c);
endmodule
| 7.259416 |
module: super
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_super;
// Inputs
reg clk;
reg btnd;
reg [1:0] sw;
// Outputs
wire hsync;
wire vsync;
wire [7:0]rgb;
// Instantiate the Unit Under Test (UUT)
super uut (
.clk(clk),
.btnd(btnd),
.sw(sw),
.hsync(hsync),
.vsync(vsync),
.rgb(rgb)
);
initial begin
// Initialize Inputs
clk = 0;
btnd = 1;
sw = 0;
forever
begin
#1; clk = ~clk;
end
// Add stimulus here
end
endmodule
| 7.281223 |
module test_syncfifo;
localparam ADDR_WIDTH = 3;
localparam DATA_WIDTH = 8;
syncfifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DATA_WIDTH(DATA_WIDTH)
) dut (
.i_clk(clk),
.i_rst(rst),
.i_data(wr_data),
.o_data(rd_data),
.i_wr(wr),
.i_rd(rd),
.o_count(count),
.o_empty(empty),
.o_full(full),
.o_half_full(half_full),
.o_overflow(overflow),
.o_underflow(underflow)
);
reg clk = 0;
reg rst = 0;
reg [DATA_WIDTH-1:0] wr_data = {DATA_WIDTH - 1{1'b0}};
wire [DATA_WIDTH-1:0] rd_data;
reg rd = 0;
reg wr = 0;
wire [ADDR_WIDTH-1:0] count;
wire empty, full, half_full, overflow, underflow;
always @(posedge clk) begin
if (rst) begin
$display("RESET");
end else begin
$display(" count: %d", count);
if (wr) begin
if (!overflow) begin
$display("WR: data 0x%x", wr_data);
end else begin
$display("WR: overflow (lost 0x%x)", wr_data);
end
end
if (rd) begin
if (!underflow) begin
$display("RD: data 0x%x", rd_data);
end else begin
$display("RD: underflow (read garbage)");
end
end
end
end
always @(posedge empty) begin
$display("FIFO becomes empty");
end
always @(posedge full) begin
$display("FIFO becomes full");
end
always @(posedge half_full) begin
$display("FIFO becomes half-full");
end
always #5 clk = ~clk;
// Data generator
always @(posedge clk) begin
wr_data <= wr_data + {{DATA_WIDTH - 1{1'b0}}, 1'b1};
end
initial begin
$dumpfile("test_syncfifo.vcd");
$dumpvars;
repeat (5) @(posedge clk);
rst <= 1;
repeat (5) @(posedge clk);
rst <= 0;
// Write some data
wr <= 1;
repeat (5) @(posedge clk);
wr <= 0;
// Read data
rd <= 1;
repeat (5) @(posedge clk);
rd <= 0;
// Make fifo full and overflow
wr <= 1;
repeat (10) @(posedge clk);
wr <= 0;
// Read all the elements and underflow
rd <= 1;
repeat (10) @(posedge clk);
wr <= 0;
// Read and write simultaneously
wr <= 1;
rd <= 1;
repeat (10) @(posedge clk);
// Make it full
rd <= 0;
repeat (6) @(posedge clk);
// Read & write simultaneously
rd <= 1;
repeat (10) @(posedge clk);
// Drain
wr <= 0;
repeat (7) @(posedge clk);
rd <= 0;
repeat (20) @(posedge clk);
$finish;
end
endmodule
| 7.212939 |
module test_SyncGen;
reg clk, rst;
wire [9:0] hcount, vcount;
wire hsync, vsync, hblank, vblank;
SyncGen sync (
.clk(clk),
.rst(rst)
);
initial begin
clk = 0;
rst = 1;
#33_444_000 $stop;
end
always begin
#20 clk = ~clk;
end
endmodule
| 6.770419 |
module test_synchronous_fifo ();
reg i_clk;
reg i_rst_n;
reg i_wr_en;
reg i_rd_en;
reg [47:0] i_data;
wire o_fifo_empty;
wire o_fifo_full;
wire o_fifo_almst_full;
wire [47:0] o_fifo_data;
//instantiate the design module
Synchronous_FIFO DUT (
i_clk, // single clock domain
i_rst_n, // active low reset
i_wr_en, // write enable signal
i_rd_en, // read enable signal
i_data, // data input //
o_fifo_empty, // fifo empty flag
o_fifo_full, // fifo full flag
o_fifo_almst_full, // fifo almost full flag , for controlling the write enable //
o_fifo_data
);
initial begin
i_clk = 1'b0;
i_rst_n = 1'b0;
i_wr_en = 1'b0;
i_rd_en = 1'b0;
i_data = 48'h0;
end
always #5 i_clk = ~i_clk;
integer i;
initial begin
@(posedge i_clk);
#4 i_rst_n = 1'b1;
end
initial begin
for (i = 0; i < 48; i = i + 1) begin
#10 i_data = i_data + 48'h04;
end
end
initial begin
for (i = 0; i < 47; i = i + 1) begin
#12 i_wr_en = 1'b1;
end
i_wr_en = 1'b0;
end
integer j;
initial begin
for (j = 0; j < 47; j = j + 1) begin
#50 i_rd_en = 1'b1;
end
i_rd_en = 1'b0;
end
endmodule
| 6.562984 |
module test_syndet;
// Inputs
reg [5:0] din;
reg iv;
reg [5:0] length;
reg clk;
reg rst;
// Outputs
wire [13:0] dout;
wire ov;
// Instantiate the Unit Under Test (UUT)
syndet uut (
.din(din),
.iv(iv),
.dout(dout),
.ov(ov),
.length(length),
.clk(clk),
.rst(rst)
);
initial begin
// Initialize Inputs
din = 0;
iv = 0;
length = 63;
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// zero data
repeat (320) begin
#5 clk = 0;
rst = 1;
#5 clk = 1;
end
#5 clk = 0;
rst = 0;
#5 clk = 1;
// uncorrelated data
repeat (320) begin
#5 clk = 0;
iv = 1;
din = 0;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
#5 clk = 0;
iv = 1;
din = 21;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
#5 clk = 0;
iv = 1;
din = 42;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
end
// correlated data
repeat (80) begin
#5 clk = 0;
iv = 1;
din = 0;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
#5 clk = 0;
iv = 1;
din = 16;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
#5 clk = 0;
iv = 1;
din = 32;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
#5 clk = 0;
iv = 1;
din = 48;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
end
// uncorrelated data
repeat (320) begin
#5 clk = 0;
iv = 1;
din = 0;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
#5 clk = 0;
iv = 1;
din = 21;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
#5 clk = 0;
iv = 1;
din = 42;
#5 clk = 1;
#5 clk = 0;
iv = 0;
#5 clk = 1;
end
#5 clk = 0;
iv = 0;
#5 clk = 1;
end
endmodule
| 6.719478 |
module: systol_new1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_systol_new;
// Inputs
reg start;
reg [7:0] read_data;
reg clk;
reg rst;
// Outputs
wire [13:0] read_select,ws;
wire [7:0] result;
wire finish;
wire we;
// Instantiate the Unit Under Test (UUT)
systol_new1 uut (
.read_select(read_select),
.result(result),
.finish(finish),
.start(start),
.read_data(read_data),
.clk(clk),
.rst(rst),
.we(we),
.ws(ws)
);
always #5 clk=~clk;
initial begin
// Initialize Inputs
start = 0;
read_data = 1;
clk = 0;
rst = 1;
#5 rst =0;
#20
start = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.510316 |
module test_s_core;
reg clk;
reg rst_n;
//reg[31:0] i_pc_instr_start_addr;
//reg[31:0] inst_mem_addr;
//reg[31:0] inst_mem_data;
//reg[4:0] load_reg_addr;
//reg[31:0] load_reg_data;
//reg setup;
wire [31:0] o_pc;
wire [31:0] o_inst_data;
wire [31:0] o_rs1_data;
wire [31:0] o_rs2_data;
wire [31:0] o_imm_out;
wire [31:0] o_ALU_out;
wire [31:0] o_adder_out;
wire o_ALU_br_cond;
wire [31:0] o_br_jump_addr;
wire [31:0] o_RAM_data_out;
wire [1:0] o_writeback_sel;
wire [31:0] o_rd_writeback;
s_core uut (
clk,
rst_n,
//i_pc_instr_start_addr,
//inst_mem_addr,
//inst_mem_data,
//load_reg_addr,
//load_reg_data,
//setup,
o_pc,
o_inst_data,
o_rs1_data,
o_rs2_data,
o_imm_out,
o_ALU_out,
o_adder_out,
o_ALU_br_cond,
o_br_jump_addr,
o_RAM_data_out,
o_writeback_sel,
o_rd_writeback
);
always #10 clk = ~clk;
initial begin
rst_n = 0;
clk = 1;
#10 rst_n = 1;
//setup=1;
//inst_mem_addr=32'h00000004;
//inst_mem_data=32'b00000000000100100111010000010011; //and immediate
//load_reg_addr=5'b00100; //rs1
//load_reg_data=32'h00000001;
//#10
//inst_mem_addr=32'h00000008;
//inst_mem_data=32'b00000000011000100000000000110011;//addition
//load_reg_addr=5'b00110; //rs2
//load_reg_data=32'h00000004;
//#10
//inst_mem_addr=32'h0000000c;
//inst_mem_data=32'b10000000000010101010100100110111;//lui
//#10
//inst_mem_addr=32'h00000010;
//inst_mem_data=32'b00000000001000100010100110010111;//auipc
//#10
//inst_mem_addr=32'h00000014;
//inst_mem_data=32'b00000010000000000000101111101111;//jal
//#10
//inst_mem_addr=32'h00000034;
//inst_mem_data=32'b00000001001000110000101010110011;//add
//load_reg_addr=5'b10001; //rs2
//load_reg_data=32'h00001101;
//#10
//inst_mem_addr=32'h00000038;
//inst_mem_data=32'b00000001000100110010000000100011; //str
// //rs2=10001 rs1=00110
//#10
//inst_mem_addr=32'h0000003c;
//inst_mem_data=32'b00000000000000110010011000000011; //load //src=00110 dst=01100
//#10
//inst_mem_addr=32'h00000040;
//inst_mem_data=32'b00000000010000000000000110010011; //loading data to 00011 reg
////#10
////inst_mem_addr=32'h00000042;
////inst_mem_data=32'b00000000010000011000110001100111; // jalr to pc 8
//#10
//inst_mem_addr=32'h00000044;
//inst_mem_data=32'b00000000110000000000001000010011; //loading data 4 to 00100 reg
//#10
//inst_mem_addr=32'h00000048; ///
//inst_mem_data=32'b00000000001100100101100001100011;
////inst_mem_data=32'b11111110001100100101111111100011;
//#5
//i_pc_instr_start_addr=32'h00000004;
//#5
//setup=0;
#120 $finish;
end
endmodule
| 6.729422 |
module test_table_lookup;
// Inputs
reg clk;
reg [31:0] state;
// Outputs
wire [31:0] p0;
wire [31:0] p1;
wire [31:0] p2;
wire [31:0] p3;
// Instantiate the Unit Under Test (UUT)
table_lookup uut (
.clk(clk),
.state(state),
.p0(p0),
.p1(p1),
.p2(p2),
.p3(p3)
);
initial begin
clk = 0;
state = 0;
#100;
state = 31'h193de3be;
#10;
if (p0 !== 32'hb3_d4_d4_67) begin
$display("E");
$finish;
end
if (p1 !== 32'h69_4e_27_27) begin
$display("E");
$finish;
end
if (p2 !== 32'h11_33_22_11) begin
$display("E");
$finish;
end
if (p3 !== 32'hae_ae_e9_47) begin
$display("E");
$finish;
end
$display("Good.");
$finish;
end
always #5 clk = ~clk;
endmodule
| 6.599303 |
module test_target ();
reg [35:0] keys_code = 0;
wire [35:0] target_key;
target TGT (
keys_code,
target_key
);
initial begin
#5 keys_code = 36'b000000000000000000000000000000000001;
#5 keys_code = 36'b000000000000000000000000000000000000;
#5 keys_code = 36'b100000000000000000000000000000000000;
#5 keys_code = 36'b000000000000000000000000000000000000;
end
endmodule
| 6.755529 |
module test_tb ();
initial begin
$dumpfile("test_tb.vcd");
$dumpvars(0, my_cpu, d_ram_and_io_inst);
#1000 $finish;
end
reg clk = 0;
always begin
#1 clk <= ~clk;
end
//***************************************************************
// Instantiate CPU
//***************************************************************
// Instantiate Instruction Memory
wire iMemReadEnable;
wire [15:0] iMemAddress;
wire [15:0] iMemOut;
//***************************************************************
// Instantiate Interface to Data Memory and IO
wire top_flag;
wire match0_flag;
wire match1_flag;
wire top_flag_clr;
wire match0_flag_clr;
wire match1_flag_clr;
wire blanking_start_interrupt_flag;
wire blanking_start_interrupt_flag_clr;
wire [15:0] dMemIOAddress;
wire [7:0] dMemIOOut;
wire [7:0] dMemIOIn;
wire dMemIOWriteEn;
wire dMemIOReadEn;
wire [7:0] gpio_pins;
i_ram instructionMemory (
.din(16'd0),
.w_addr(12'd0),
.w_en(1'd0),
.r_addr(iMemAddress[11:0]),
.r_en(iMemReadEnable),
.clk(clk),
.dout(iMemOut)
);
cpu my_cpu (
.clk(clk),
.iMemAddress(iMemAddress),
.iMemOut(iMemOut),
.iMemReadEnable(iMemReadEnable),
.dMemIOAddress(dMemIOAddress),
.dMemIOIn(dMemIOIn),
.dMemIOOut(dMemIOOut),
.dMemIOWriteEn(dMemIOWriteEn),
.dMemIOReadEn(dMemIOReadEn),
.interrupt_0(blanking_start_interrupt_flag),
.interrupt_1(top_flag),
.interrupt_2(match0_flag),
.interrupt_3(match1_flag),
.interrupt_0_clr(blanking_start_interrupt_flag_clr),
.interrupt_1_clr(top_flag_clr),
.interrupt_2_clr(match0_flag_clr),
.interrupt_3_clr(match1_flag_clr)
);
d_ram_and_io d_ram_and_io_inst (
.clk(clk),
.din(dMemIOIn),
.address(dMemIOAddress),
.w_en(dMemIOWriteEn),
.r_en(dMemIOReadEn),
.dout(dMemIOOut),
.gpio_pins(gpio_pins),
.top_flag(top_flag),
.match0_flag(match0_flag),
.match1_flag(match1_flag),
.top_flag_clr(top_flag_clr),
.match0_flag_clr(match0_flag_clr),
.match1_flag_clr(match1_flag_clr),
.rx(rx),
.tx(tx),
.h_sync(),
.v_sync(),
.R(),
.G(),
.B(),
.blanking_start_interrupt_flag(),
.blanking_start_interrupt_flag_clr()
);
//***************************************************************
endmodule
| 7.972333 |
module test_tdma_scheduler;
// Parameters
parameter INDEX_WIDTH = 8;
parameter SCHEDULE_START_S = 48'h0;
parameter SCHEDULE_START_NS = 30'h0;
parameter SCHEDULE_PERIOD_S = 48'd0;
parameter SCHEDULE_PERIOD_NS = 30'd1000000;
parameter TIMESLOT_PERIOD_S = 48'd0;
parameter TIMESLOT_PERIOD_NS = 30'd100000;
parameter ACTIVE_PERIOD_S = 48'd0;
parameter ACTIVE_PERIOD_NS = 30'd100000;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [95:0] input_ts_96 = 0;
reg input_ts_step = 0;
reg enable = 0;
reg [79:0] input_schedule_start = 0;
reg input_schedule_start_valid = 0;
reg [79:0] input_schedule_period = 0;
reg input_schedule_period_valid = 0;
reg [79:0] input_timeslot_period = 0;
reg input_timeslot_period_valid = 0;
reg [79:0] input_active_period = 0;
reg input_active_period_valid = 0;
// Outputs
wire locked;
wire error;
wire schedule_start;
wire [INDEX_WIDTH-1:0] timeslot_index;
wire timeslot_start;
wire timeslot_end;
wire timeslot_active;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, input_ts_96, input_ts_step, enable, input_schedule_start,
input_schedule_start_valid, input_schedule_period, input_schedule_period_valid,
input_timeslot_period, input_timeslot_period_valid, input_active_period,
input_active_period_valid);
$to_myhdl(locked, error, schedule_start, timeslot_index, timeslot_start, timeslot_end,
timeslot_active);
// dump file
$dumpfile("test_tdma_scheduler.lxt");
$dumpvars(0, test_tdma_scheduler);
end
tdma_scheduler #(
.INDEX_WIDTH(INDEX_WIDTH),
.SCHEDULE_START_S(SCHEDULE_START_S),
.SCHEDULE_START_NS(SCHEDULE_START_NS),
.SCHEDULE_PERIOD_S(SCHEDULE_PERIOD_S),
.SCHEDULE_PERIOD_NS(SCHEDULE_PERIOD_NS),
.TIMESLOT_PERIOD_S(TIMESLOT_PERIOD_S),
.TIMESLOT_PERIOD_NS(TIMESLOT_PERIOD_NS),
.ACTIVE_PERIOD_S(ACTIVE_PERIOD_S),
.ACTIVE_PERIOD_NS(ACTIVE_PERIOD_NS)
) UUT (
.clk(clk),
.rst(rst),
.input_ts_96(input_ts_96),
.input_ts_step(input_ts_step),
.enable(enable),
.input_schedule_start(input_schedule_start),
.input_schedule_start_valid(input_schedule_start_valid),
.input_schedule_period(input_schedule_period),
.input_schedule_period_valid(input_schedule_period_valid),
.input_timeslot_period(input_timeslot_period),
.input_timeslot_period_valid(input_timeslot_period_valid),
.input_active_period(input_active_period),
.input_active_period_valid(input_active_period_valid),
.locked(locked),
.error(error),
.schedule_start(schedule_start),
.timeslot_index(timeslot_index),
.timeslot_start(timeslot_start),
.timeslot_end(timeslot_end),
.timeslot_active(timeslot_active)
);
endmodule
| 6.556205 |
module: tft_address_generator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_tft_addr_gen;
// Inputs
reg [8:0] x;
reg [8:0] y;
wire [17:0] addr;
// Instantiate the Unit Under Test (UUT)
tft_address_generator uut (
.x(x),
.y(y),
.addr(addr)
);
initial begin
// Initialize Inputs
x = 0;
y = 0;
for(x = 0; x < 480; x = x + 1) begin
for (y = 0; y < 272; y = y + 1) begin
#10;
if(addr !== (x*272 + y)) begin
$display("error! addr = %d,22 x = %d, y = %d", addr, x, y);
end
end
end
$display("final address = %d", addr);
// Add stimulus here
$finish;
end
endmodule
| 6.954032 |
module test_tiledBcdCounter ();
reg clock, up, down, set9, set0;
wire [3:0] ups, down;
wire [15:0] num;
assign ups = {0, 0, 0, up};
assign downs = {0, 0, 0, down};
tiledBcdCounter #(
.DIGITS(4)
) counter (
num,
cout,
bout,
up,
down,
set9,
set0,
clock
);
wire [3:0] num3, num2, num1, num0;
assign num3 = num[15:12];
assign num2 = num[11:8];
assign num1 = num[7:4];
assign num0 = num[3:0];
always #10 clock = ~clock;
initial begin
clock = 0;
up = 0;
down = 0;
set9 = 0;
set0 = 0;
#15 #10 up = 1;
#250 up = 0;
#10 set9 = 1;
#10 set9 = 0;
#10 set0 = 1;
#10 set0 = 0;
#10 down = 1;
#250 down = 0;
#100 $finish;
end
endmodule
| 6.833341 |
module: token_production
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_token_production;
// Inputs
reg [2:0] park_number;
reg [2:0] pattern;
// Outputs
wire [2:0] token;
// Instantiate the Unit Under Test (UUT)
token_production uut (
.park_number(park_number),
.pattern(pattern),
.token(token)
);
initial begin
park_number = 7; pattern = 2; #250; // token = 101
park_number = 5; pattern = 5; #250; // token = 000
park_number = 7; pattern = 0; #250; // token = 111
park_number = 3; pattern = 5; #250; // token = 110
end
endmodule
| 6.63451 |
module: TOP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module text_TOP_bh;
// Inputs
reg clk;
reg reset;
// Instantiate the Unit Under Test (UUT)
TOP uut (
.clk(clk),.reset(reset)
);
always#(10) clk=~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
| 7.274763 |
module: top_level
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_top_koli_jani;
// Inputs
reg clk;
reg rst;
// Outputs
wire [15:0] mixed_signal;
wire [15:0] sampled_sine_test;
wire [15:0] sampled_cosine_test;
wire [1:0] parallel;
wire parallel1;
wire parallel0;
integer sin_out;
integer cos_out;
integer parallel_1;
integer parallel_0;
assign parallel1=parallel[1];
assign parallel0=parallel[0];
// Instantiate the Unit Under Test (UUT)
top_level uut (
.clk(clk),
.rst(rst),
.mixed_signal(mixed_signal),
.parallel(parallel),
.sampled_sine_test(sampled_sine_test),
.sampled_cosine_test(sampled_cosine_test)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
sin_out = $fopen("sin_output.txt");
cos_out = $fopen("cos_output.txt");
parallel_1 = $fopen("parallel_1.txt");
parallel_0 = $fopen("parallel_0.txt");
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
end
always #5
clk <= ~clk;
always @(posedge clk)
if(~rst)
begin
$fwrite(sin_out,"%b \n", sampled_sine_test);
$fwrite(cos_out,"%b \n", sampled_cosine_test);
$fwrite(parallel_1,"%b \n", parallel1);
$fwrite(parallel_0,"%b \n", parallel0);
end
initial begin
#200000
$fclose(sin_out);
$fclose(cos_out);
$fclose(parallel_1);
$fclose(parallel_0);
end
endmodule
| 7.56918 |
module test_touch;
// Inputs
reg cclk;
reg rstb;
wire touch_busy;
wire data_in;
// Outputs
wire touch_clk;
wire touch_csb;
wire data_out;
wire [11:0] x, y, z;
// Instantiate the Unit Under Test (UUT)
touchpad_controller uut (
.cclk(cclk),
.rstb(rstb),
.touch_busy(touch_busy),
.data_in(data_in),
.touch_clk(touch_clk),
.touch_csb(touch_csb),
.data_out(data_out),
.x(x),
.y(y),
.z(z)
);
//instantiate a model of the ad7873
// change the NOISE parameter to 1 to simulate some noise on the conversion
ad7873 #(
.NOISE(1)
) AD7873 (
.dclk(touch_clk),
.din (data_out),
.csb (touch_csb),
.dout(data_in),
.busy(touch_busy)
);
//run our main clock
always #5 cclk = ~cclk;
initial begin
$dumpfile("test_touch.vcd");
$dumpvars(0, test_touch);
$display("hello world");
// Initialize Inputs
cclk = 0;
rstb = 0;
//assert reset for long enough
repeat (2) @(posedge cclk);
rstb = 1;
//let the simulation run
repeat (10_000)
@(posedge touch_clk); //you need to wait a looong time to properly test your averager
$finish;
end
endmodule
| 6.645161 |
module: transmitter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_transmiiterandreceiver;
// Inputs
reg [7:0] data;
reg start;
reg clk;
// Outputs
wire Tx;
wire Rx;
wire oTx,ob;
wire [3:0] cnt;
wire [3:0] cnt1;
wire data_valid;
wire [7:0] data_out;
// Instantiate the Unit Under Test (UUT)
transmitter uut (
.Tx(Tx),
.cnt(cnt),
.data(data),
.start(start),
.clk(clk)
);
receiver uuut (
.data_valid(data_valid),
.cnt(cnt1),
.data_out(data_out),
.clk(clk),
.Rx(Rx)
);
initial begin
// Initialize Inputs
data = 0;
start = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#50;
@(negedge clk) data=67;
start=1;
@(negedge clk) start=0;
// Add stimulus here
end
OBUFDS o1(
.I(Tx),
.O(oTx),
.OB(ob)
);
IBUFDS o2(
.I(oTx),
.IB(ob),
.O(Rx)
);
always @(posedge clk) begin
if ( cnt==11 ) begin
start<=1;
data<=76;
end
else start<=0;
end
always #20.83 clk<=~clk;
endmodule
| 6.812619 |
module test_transrf_b4r5g3;
parameter period = 5;
reg clk_w, clk_r, rst_n, w_en, r_en;
reg [ 3:0] w_data;
wire [19:0] r_data;
wire rf_full, rf_empty;
transrf_b4r5g3 DUT (
.clk_w(clk_w),
.clk_r(clk_r),
.rst_n(rst_n),
.w_en(w_en),
.w_data(w_data),
.r_en(r_en),
.r_data(r_data),
.rf_full(rf_full),
.rf_empty(rf_empty)
);
always #period clk_w = ~clk_w;
always #40 clk_r = ~clk_r;
//always #30 clk_r = ~clk_r;
//always #20 clk_r = ~clk_r;
//reset
initial begin
clk_r = 0;
clk_w = 0;
rst_n = 0;
w_en = 0;
r_en = 0;
w_data = 4'd0;
#6;
rst_n = 0;
#6;
rst_n = 1;
w_en = 1;
r_en = 1;
#10000;
$finish();
end
// stimulus
always @(posedge clk_w or negedge clk_w or negedge rst_n) begin
w_en = ($random() % 10) > 3 ? 1'b1 : 1'b0;
if (rst_n == 1'b1 && w_en && ~rf_full) begin
w_data <= w_data + 1'd1;
end
end
always @(posedge clk_r) begin
$display("INFO: r_en:%b rf_empty:%b, r_data:%b, arrival at %t", r_en, rf_empty, r_data, $time);
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.vcd");
$dumpvars();
end
`endif
endmodule
| 6.710434 |
module test_trig_gen (
input gclk_40m,
input trigger_select,
input htrig,
input strig_cmd,
input [3:0] strig_config,
input sptrig_en,
input [15:0] sptrig_period,
input [15:0] test_l0_latency,
input [15:0] test_l1_latency,
input [15:0] test_l2a_latency,
output reg test_l0 = 1'b0,
output reg test_l1 = 1'b0,
output reg test_l2a = 1'b0,
output reg test_trig = 1'b0,
input BusyFlag,
input reset
);
parameter st0 = 0;
parameter st1 = 1;
parameter st2 = 2;
parameter st3 = 3;
parameter st4 = 4;
parameter st5 = 5;
parameter st6 = 6;
parameter st7 = 7;
parameter st5d = 8;
reg [3:0] st = st0;
reg [2:0] sta = st0;
reg [15:0] clkcnt = 16'd0;
reg [15:0] clkcnta = 16'd0;
reg l0_trig = 1'b0;
//l0_trig generation
always @(posedge gclk_40m)
if (reset) begin
l0_trig <= 1'b0;
clkcnta <= 16'd0;
sta <= st0;
end else
case (sta)
st0: begin
l0_trig <= 1'b0;
clkcnta <= 16'd0;
if (BusyFlag) sta <= st0;
else if (htrig & trigger_select) sta <= st1;
else if (strig_cmd & (!trigger_select)) sta <= st1;
else if (sptrig_en & (!trigger_select)) sta <= st1;
else sta <= st0;
end
st1: begin
l0_trig <= 1'b1;
clkcnta <= 16'd0;
sta <= st2;
end
st2: begin
l0_trig <= 1'b0;
clkcnta <= clkcnta + 16'd1;
if (clkcnta == sptrig_period) sta <= st0;
else sta <= st2;
end
default: begin
l0_trig <= 1'b0;
clkcnta <= 16'd0;
sta <= st0;
end
endcase
//trigger sequence generation
always @(posedge gclk_40m)
if (reset) begin
test_l0 <= 1'b0;
test_l1 <= 1'b0;
test_l2a <= 1'b0;
test_trig <= 1'b0;
clkcnt <= 16'h0;
st <= st0;
end else
case (st)
st0: begin
test_l0 <= 1'b0;
test_l1 <= 1'b0;
test_l2a <= 1'b0;
test_trig <= 1'b0;
clkcnt <= 16'h0;
if (l0_trig) st <= st1;
else st <= st0;
end
//assert l0,set clk_cnt_set = 1;
st1: begin
if (strig_config[0]) begin
test_l0 <= 1'b1;
test_trig <= 1'b1;
end else begin
test_l0 <= 1'b0;
test_trig <= 1'b0;
end
test_l1 <= 1'b0;
test_l2a <= 1'b0;
clkcnt <= clkcnt + 16'd1;
st <= st2;
end
st2: begin
test_l0 <= 1'b0;
test_l1 <= 1'b0;
test_l2a <= 1'b0;
test_trig <= 1'b0;
clkcnt <= clkcnt + 16'd1;
if (clkcnt == test_l0_latency) st <= st3;
else st <= st2;
end
st3: begin
test_l1 <= 1'b0;
test_l2a <= 1'b0;
clkcnt <= clkcnt + 16'd1;
if(strig_config[1]) //
begin
test_l0 <= 1'b1;
test_trig <= 1'b1;
end else begin
test_l0 <= 1'b0;
test_trig <= 1'b0;
end
st <= st4;
end
st4: begin
test_l0 <= 1'b0;
test_l1 <= 1'b0;
test_l2a <= 1'b0;
test_trig <= 1'b0;
clkcnt <= clkcnt + 16'd1;
if (clkcnt == test_l1_latency) st <= st5;
else st <= st4;
end
//assert l1,set clk_cnt_set = 1;
st5: begin
test_l0 <= 1'b0;
test_l2a <= 1'b0;
clkcnt <= clkcnt + 16'd1;
if(strig_config[2]) //
begin
test_l1 <= 1'b1;
test_trig <= 1'b1;
end else begin
test_l1 <= 1'b0;
test_trig <= 1'b0;
end
st <= st5d;
end
//add one clock duration to l1 trigger
st5d: begin
test_l0 <= 1'b0;
test_l2a <= 1'b0;
test_l1 <= 1'b0;
clkcnt <= clkcnt + 16'd1;
if(strig_config[2]) //
begin
test_trig <= 1'b1;
end else begin
test_trig <= 1'b0;
end
st <= st6;
end
st6: begin
test_l0 <= 1'b0;
test_l1 <= 1'b0;
test_l2a <= 1'b0;
test_trig <= 1'b0;
clkcnt <= clkcnt + 16'd1;
if (clkcnt == test_l2a_latency) st <= st7;
else st <= st6;
end
//assert l1,set clk_cnt_set = 1;
st7: begin
test_l0 <= 1'b0;
test_l1 <= 1'b0;
test_trig <= 1'b0;
clkcnt <= clkcnt + 16'd1;
if (strig_config[3]) //
test_l2a <= 1'b1;
else test_l2a <= 1'b0;
st <= st0;
end
default: begin
test_l0 <= 1'b0;
test_l1 <= 1'b0;
test_l2a <= 1'b0;
test_trig <= 1'b0;
clkcnt <= 16'h0;
st <= st0;
end
endcase
endmodule
| 7.485104 |
module test_tristate_buffer;
reg in;
reg en;
wire out_h;
wire out_l;
tsb_h #(1) ts_h(in, out_h, en);
tsb_l #(1) ts_l(in, out_l, en);
localparam N = 4;
reg [1:N] test_in = 8'b0011;
reg [1:N] test_en = 8'b0101;
reg [1:N] exp_out_h = 8'bz0z1;
reg [1:N] exp_out_l = 8'b0z1z;
integer i;
integer pass;
integer overall_pass;
initial begin
$dumpfile("test_tristate_buffer.vcd");
$dumpvars(0, test_tristate_buffer);
overall_pass = 1;
for (i = 1; i <= N; i = i + 1) begin
#1;
in = test_in[i];
en = test_en[i];
#1;
pass = (out_h === exp_out_h[i]);
if (!pass)
$display("tri_h in=%0d, en=%0d => out=%0d, exp=%0d [%s]", in, en, out_h, exp_out_h[i], `CHECK);
if (overall_pass)
overall_pass = pass;
pass = (out_l === exp_out_l[i]);
if (!pass)
$display("tri_l in=%0d, en=%0d => out=%0d, exp=%0d [%s]", in, en, out_l, exp_out_l[i], `CHECK);
if (overall_pass)
overall_pass = pass;
$display();
end
if (overall_pass)
$display("test: tsb: PASS");
else
$display("test: tsb: FAIL");
$finish();
end
endmodule
| 6.877788 |
module: TX
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_tx;
// Inputs
reg clock;
reg tx_en;
reg [7:0] data_in;
reg reset;
// Outputs
wire tx;
// Instantiate the Unit Under Test (UUT)
TX uut (
.clock(clock),
.tx(tx),
.tx_en(tx_en),
.data_in(data_in),
.reset(reset)
);
initial begin
// Initialize Inputs
clock = 0;
tx_en = 0;
data_in = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#10;
reset =1 ;
#5
tx_en = 1;
data_in=8'b11001001;
#5
tx_en =0;
#1200
/*tx_en = 1;
data_in=8'b01101101;
#5
tx_en =0;
#1400*/
$finish;
// Add stimulus here
end
always #2.5 clock = ~ clock;
endmodule
| 8.797909 |
module test_tx_checksum_256;
// Parameters
parameter DATA_WIDTH = 256;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 0;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 0;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USE_INIT_VALUE = 1;
parameter DATA_FIFO_DEPTH = 4096;
parameter CHECKSUM_FIFO_DEPTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg s_axis_cmd_csum_enable = 0;
reg [7:0] s_axis_cmd_csum_start = 0;
reg [7:0] s_axis_cmd_csum_offset = 0;
reg [15:0] s_axis_cmd_csum_init = 0;
reg s_axis_cmd_valid = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire s_axis_cmd_ready;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, s_axis_cmd_csum_enable,
s_axis_cmd_csum_start, s_axis_cmd_csum_offset, s_axis_cmd_csum_init,
s_axis_cmd_valid);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, s_axis_cmd_ready);
// dump file
$dumpfile("test_tx_checksum_256.lxt");
$dumpvars(0, test_tx_checksum_256);
end
tx_checksum #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USE_INIT_VALUE(USE_INIT_VALUE),
.DATA_FIFO_DEPTH(DATA_FIFO_DEPTH),
.CHECKSUM_FIFO_DEPTH(CHECKSUM_FIFO_DEPTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
.s_axis_cmd_csum_enable(s_axis_cmd_csum_enable),
.s_axis_cmd_csum_start(s_axis_cmd_csum_start),
.s_axis_cmd_csum_offset(s_axis_cmd_csum_offset),
.s_axis_cmd_csum_init(s_axis_cmd_csum_init),
.s_axis_cmd_valid(s_axis_cmd_valid),
.s_axis_cmd_ready(s_axis_cmd_ready)
);
endmodule
| 8.158623 |
module test_tx_checksum_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 0;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 0;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USE_INIT_VALUE = 1;
parameter DATA_FIFO_DEPTH = 4096;
parameter CHECKSUM_FIFO_DEPTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg s_axis_cmd_csum_enable = 0;
reg [7:0] s_axis_cmd_csum_start = 0;
reg [7:0] s_axis_cmd_csum_offset = 0;
reg [15:0] s_axis_cmd_csum_init = 0;
reg s_axis_cmd_valid = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire s_axis_cmd_ready;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, s_axis_cmd_csum_enable,
s_axis_cmd_csum_start, s_axis_cmd_csum_offset, s_axis_cmd_csum_init,
s_axis_cmd_valid);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, s_axis_cmd_ready);
// dump file
$dumpfile("test_tx_checksum_64.lxt");
$dumpvars(0, test_tx_checksum_64);
end
tx_checksum #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USE_INIT_VALUE(USE_INIT_VALUE),
.DATA_FIFO_DEPTH(DATA_FIFO_DEPTH),
.CHECKSUM_FIFO_DEPTH(CHECKSUM_FIFO_DEPTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
.s_axis_cmd_csum_enable(s_axis_cmd_csum_enable),
.s_axis_cmd_csum_start(s_axis_cmd_csum_start),
.s_axis_cmd_csum_offset(s_axis_cmd_csum_offset),
.s_axis_cmd_csum_init(s_axis_cmd_csum_init),
.s_axis_cmd_valid(s_axis_cmd_valid),
.s_axis_cmd_ready(s_axis_cmd_ready)
);
endmodule
| 8.158623 |
module test_tx_mac #(
parameter mac_aw = 10, // 16-bit words
parameter big_endian = 0
) (
input clk,
// There is an implied DPRAM _not_ included in this module.
// These ports access its read port, with assumed 1-cycle latency
// The packet length is stored as the first word of a buffer.
// Endian-ness is configurable.
output [mac_aw-1:0] host_addr,
input [15:0] host_d,
// Request from host to transmit a packet, already converted to
// (or at least usable in) our clk domain.
// OK to just latch buf_start_addr on one host clock cycle,
// and raise the start signal on the next.
// Also OK to construct buf_start_addr with a handful of
// static 0 at the lsb (representing granularity of buffer starts),
// could save a few registers in that clock domain crossing.
input start,
input [mac_aw-1:0] buf_start_addr,
output done, // 4-phase handshake with start signal
// Connection to precog module
output req,
output [10:0] len_req, // can represent 1 MTU, in octets
// Connection to output multiplexer (xformer.v)
input strobe,
output [7:0] mac_data
);
reg [mac_aw-1:0] buffer_point; // in words
reg [2:0] mode = 0;
reg [10:0] len_req_r = 0;
reg req_r = 0, done_r = 0;
reg odd_octet = 0;
wire even_octet = ~odd_octet;
// There's a total of two cycles latency from setting buffer_point
// to being able to use the result of reading that DPRAM entry.
always @(posedge clk)
case (mode)
0:
if (start) begin
mode <= 1;
buffer_point <= buf_start_addr;
end
1: begin
mode <= 2;
buffer_point <= buffer_point + 1;
end
2: begin
mode <= 3;
len_req_r <= host_d;
odd_octet <= 0;
req_r <= 1;
end
3:
if (strobe) begin
odd_octet <= ~odd_octet;
buffer_point <= buffer_point + even_octet;
len_req_r <= len_req_r - 1;
if (len_req_r == 1) begin
mode <= 4;
done_r <= 1;
req_r <= 0;
end
end
4: begin
if (~start) begin
mode <= 0;
done_r <= 0;
end
end
endcase
assign host_addr = buffer_point;
assign len_req = len_req_r;
assign mac_data = (odd_octet ^ big_endian) ? host_d[15:8] : host_d[7:0];
assign done = done_r;
assign req = req_r;
endmodule
| 8.703978 |
module test_tx_tb;
parameter mac_aw = 8;
reg clk;
integer cc;
reg [15:0] host_mem[0:(1<<mac_aw)-1];
integer out_file;
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("test_tx.vcd");
$dumpvars(5, test_tx_tb);
end
$readmemh("host_mem", host_mem);
out_file = $fopen("test_tx.out", "w");
$display("Non-checking testbench. Will always PASS");
for (cc = 0; cc < 200; cc = cc + 1) begin
clk = 0;
#4; // 125 MHz
clk = 1;
#4;
end
$display("PASS");
$finish(0);
end
wire strobe; // will be xformer.v or precog?
// Packet send requests hard-coded here
reg start = 0;
reg [mac_aw-1:0] buf_start_addr;
wire done;
always @(posedge clk) begin
case (cc)
10: buf_start_addr <= 0;
11: start <= 1;
50: buf_start_addr <= 60;
51: start <= 1;
120: buf_start_addr <= 30;
121: start <= 1;
160: buf_start_addr <= 0;
161: start <= 1;
endcase
if (done) start <= 0;
end
// Normally host_mem would be DPRAM, but this testbench
// doesn't need a host-write port. Instead, it gets filled
// by the $readmemh() above.
wire [mac_aw-1:0] host_addr;
reg [15:0] host_d;
always @(posedge clk) host_d <= host_mem[host_addr];
// Center of DUT complex
wire req;
wire [10:0] len_req;
wire [7:0] mac_data;
test_tx_mac #(
.mac_aw(mac_aw)
) mac (
.clk(clk),
.host_addr(host_addr),
.host_d(host_d),
.start(start),
.buf_start_addr(buf_start_addr),
.done(done),
.req(req),
.len_req(len_req),
.strobe(strobe),
.mac_data(mac_data)
);
// Randomized delay from req to strobe
reg [3:0] del1 = 0;
reg req_d = 0;
always @(posedge clk) begin
req_d <= req;
if (req & ~req_d) del1 <= $random;
else if (del1 != 0) del1 <= del1 - 1;
end
assign strobe = req & req_d & (del1 == 0);
// Push Tx data to output file
integer rc;
always @(negedge clk) if (strobe && out_file != 0) rc = $fputc(mac_data, out_file);
endmodule
| 7.634402 |
module test_uart;
// Testbench uses a 48 MHz clock
// Want to interface to 115200 baud UART
// 10000000 / 115200 = 87 Clocks Per Bit.
parameter c_CLOCK_MHZ = 48;
parameter c_UART_SPEED = 115200;
parameter c_CLOCK_PERIOD_NS = 1000 / c_CLOCK_MHZ;
parameter c_CLKS_PER_BIT = c_CLOCK_MHZ * 1000000 / c_UART_SPEED;
parameter c_CLKS_PER_BYTE = (c_CLKS_PER_BIT + 7) / 8;
parameter c_BIT_PERIOD = c_CLKS_PER_BIT * c_CLOCK_PERIOD_NS;
integer i;
integer j;
reg [15:0] prescale = c_CLKS_PER_BYTE;
reg clk = 0;
reg rst = 0;
// Inputs
reg m_axis_tready = 0;
reg rxd = 1;
// Outputs
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire rx_busy;
wire rx_overrun_error;
wire rx_frame_error;
// Inputs
reg [7:0] s_axis_tdata = 8'd0;
reg s_axis_tvalid = 1'b0;
reg [9:0] r_Tx_Data = 0;
// Outputs
wire s_axis_tready;
wire txd;
wire tx_busy;
// Write a byte to RX pin
task UART_WRITE_RX_AND_RCV;
input [7:0] i_Data;
integer ii;
begin
m_axis_tready <= 1;
// Write Start Bit
#(c_BIT_PERIOD) rxd <= 1'b0;
// Write Data
for (ii = 0; ii < 8; ii = ii + 1) begin
#(c_BIT_PERIOD) rxd <= i_Data[ii];
end
// Write Stop Bit
#(c_BIT_PERIOD) rxd <= 1'b1;
@(posedge m_axis_tvalid);
end
endtask
// Send a byte and read back data from TX pin
task UART_SEND_AND_READ_TX;
output [9:0] o_Data;
integer ii;
begin
// Send byte
@(posedge clk);
s_axis_tvalid <= 1'b1;
@(posedge clk);
s_axis_tvalid <= 1'b0;
@(posedge tx_busy);
// Read Data
for (ii = 0; ii < 10; ii = ii + 1) begin
#(c_BIT_PERIOD) o_Data[ii] <= txd;
end
@(posedge s_axis_tready);
end
endtask
always #(c_CLOCK_PERIOD_NS / 2) clk <= !clk;
initial begin
$dumpfile("test_uart.vcd");
$dumpvars(0, test_uart);
// Exercise Rx
j = 0;
for (i = 0; i < 256; i = i + 1) begin
UART_WRITE_RX_AND_RCV(i);
if (m_axis_tdata == i) j = j + 1;
else $display("RX Test Failed - Incorrect Byte Received");
end
if (j == 256) $display("RX Test Passed - Correct Bytes Received");
// Exercise Tx
j = 0;
for (i = 0; i < 256; i = i + 1) begin
s_axis_tdata <= i;
UART_SEND_AND_READ_TX(r_Tx_Data);
// Check that the correct byte was sent
if (r_Tx_Data[8:1] == i) j = j + 1;
else $display("TX Test Failed - Incorrect Byte Sent");
end
if (j == 256) $display("TX Test Passed - Correct Bytes Sent");
$finish;
end
uart #(
.DATA_WIDTH(8)
) UUT (
.clk(clk),
.rst(rst),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
// input
.rxd(rxd),
// status
.rx_busy(rx_busy),
.rx_overrun_error(rx_overrun_error),
.rx_frame_error(rx_frame_error),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
// output
.txd(txd),
// status
.tx_busy(tx_busy),
// configuration
.prescale(prescale)
);
endmodule
| 7.673351 |
module test_uart_rx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg m_axis_tready = 0;
reg rxd = 1;
reg [15:0] prescale = 0;
// Outputs
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire busy;
wire overrun_error;
wire frame_error;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, m_axis_tready, rxd, prescale);
$to_myhdl(m_axis_tdata, m_axis_tvalid, busy, overrun_error, frame_error);
// dump file
$dumpfile("test_uart_rx.lxt");
$dumpvars(0, test_uart_rx);
end
uart_rx #(
.DATA_WIDTH(8)
) UUT (
.clk(clk),
.rst(rst),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
// input
.rxd(rxd),
// status
.busy(busy),
.overrun_error(overrun_error),
.frame_error(frame_error),
// configuration
.prescale(prescale)
);
endmodule
| 7.014426 |
module test_uart_tx;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 8'd0;
reg s_axis_tvalid = 1'b0;
reg [15:0] prescale = 0;
// Outputs
wire s_axis_tready;
wire txd;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tvalid, prescale);
$to_myhdl(s_axis_tready, txd, busy);
// dump file
$dumpfile("test_uart_tx.lxt");
$dumpvars(0, test_uart_tx);
end
uart_tx #(
.DATA_WIDTH(8)
) UUT (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
// output
.txd(txd),
// status
.busy(busy),
// configuration
.prescale(prescale)
);
endmodule
| 7.694888 |
module test_uart_tx_buffer ();
reg clk = 0;
always #1 clk = ~clk;
reg ena, sent;
initial begin
ena = 0;
end
always #2 ena = ~ena;
reg [15:0] data_transmit = {8'd10, 8'd97};
parameter LEN = 2;
reg last_ena;
reg last_tx_sent;
reg tx_ena;
reg sending = 0;
reg [7:0] count;
reg [(LEN+1)*8-1:0] send_buf;
uart_tx transmitter (
clk,
send_buf[(LEN+1)*8-1:LEN*8],
tx_ena,
tx_sent,
bit_out
);
always @(posedge clk) begin
if (~sending & ~last_ena & ena) begin
send_buf <= {8'd0, data_transmit};
sending <= 1;
sent <= 0;
tx_ena <= 0;
count <= 8'd255;
end
if (sending & ~tx_ena & count != LEN - 1) begin
count <= count + 1;
send_buf <= {send_buf[LEN*8-1:0], 8'd0};
tx_ena <= 1;
end
if (tx_sent & ~last_tx_sent) begin
tx_ena <= 0;
if (count == LEN - 1) begin
sent <= 1;
sending <= 0;
end
end
last_tx_sent <= tx_sent;
last_ena <= ena;
end
endmodule
| 6.689567 |
module test_ULA;
reg [1:0] Operacao;
reg signed [7:0] in1;
reg signed [7:0] in2;
wire saida_comp;
wire signed [7:0] saida;
initial begin
#1 $display("Soma sem sinal");
in1 = 0;
in2 = 1;
Operacao = 0;
#1 $display("Soma com sinal");
in1 = -1;
Operacao = 1;
#1 $display("Multiplicacao com sinal");
in2 = 2;
in1 = 2;
Operacao = 2;
end
initial begin
$monitor("Operacao=%d in1=%d in2=%d saida=%d saida_comp=%d\n", Operacao, in1, in2, saida,
saida_comp);
end
ULA gate1 (
Operacao,
in1,
in2,
saida_comp,
saida
);
endmodule
| 6.912582 |
module (TEST)
module Unit_test (clk, updown, reset, teller,
full, empty, alarm, display1, display2, display3, pcount, tcount);
// We have five inputs to get from the user
input wire clk, reset, updown;
input [2:0] teller;
// We give four outputs
// Two for empty or flag
// ,one for showing the number of people in queue
// and one for showing the waiting time
output full, empty, alarm;
output [3:0] pcount;
output [6:0] display1, display2, display3;
output [1:0] tcount;
wire [4:0]wtime;
// We use this to show two digits in seven segment
wire [3:0] first_digit = wtime % 10;
wire [3:0] second_digit = wtime / 10;
// We start counting the pcount whether it's increasing or decreasing
UpDown_counter counter (clk, reset, updown, pcount, alarm);
// For flags
flags f (pcount, empty, full);
// We prepare the tellers situation with 2bit instead of 3bit
Teller t (teller,tcount);
// We calculate the waiting time by getting it from the rom
waiting_time wt(pcount, tcount, wtime);
// It's time to display the results above
seg d1 (first_digit, display1);
seg d2 (second_digit, display2);
seg d3 (pcount, display3);
endmodule
| 7.772727 |
module unit_test_t ();
reg clk, reset, updown;
reg [2:0] teller;
wire full, empty, alarm;
wire [3:0] pcount;
wire [1:0] tcount;
wire [6:0] display1, display2, display3;
initial begin
clk = 0;
reset = 1;
// Up
#100;
reset = 0;
updown = 1;
teller[2] = 0;
teller[1] = 0;
teller[0] = 0;
#100;
reset = 0;
updown = 1;
teller[2] = 0;
teller[1] = 0;
teller[0] = 1;
#100;
reset = 0;
updown = 1;
teller[2] = 0;
teller[1] = 1;
teller[0] = 0;
#100;
reset = 0;
updown = 1;
teller[2] = 0;
teller[1] = 1;
teller[0] = 1;
#100;
reset = 0;
updown = 1;
teller[2] = 1;
teller[1] = 0;
teller[0] = 0;
#100;
reset = 0;
updown = 1;
teller[2] = 1;
teller[1] = 0;
teller[0] = 1;
#100;
reset = 0;
updown = 1;
teller[2] = 1;
teller[1] = 1;
teller[0] = 0;
#100;
reset = 0;
updown = 1;
teller[2] = 1;
teller[1] = 1;
teller[0] = 1;
// Down
#100;
reset = 0;
updown = 0;
teller[2] = 0;
teller[1] = 0;
teller[0] = 0;
#100;
reset = 0;
updown = 0;
teller[2] = 0;
teller[1] = 0;
teller[0] = 1;
#100;
reset = 0;
updown = 0;
teller[2] = 0;
teller[1] = 1;
teller[0] = 0;
#100;
reset = 0;
updown = 0;
teller[2] = 0;
teller[1] = 1;
teller[0] = 1;
#100;
reset = 0;
updown = 0;
teller[2] = 1;
teller[1] = 0;
teller[0] = 0;
#100;
reset = 0;
updown = 0;
teller[2] = 1;
teller[1] = 0;
teller[0] = 1;
#100;
reset = 0;
updown = 0;
teller[2] = 1;
teller[1] = 1;
teller[0] = 0;
#100;
reset = 0;
updown = 0;
teller[2] = 1;
teller[1] = 1;
teller[0] = 1;
end
always #50 clk <= ~clk;
Unit_test tst (
clk,
updown,
reset,
teller,
full,
empty,
alarm,
display1,
display2,
display3,
pcount,
tcount
);
endmodule
| 6.897001 |
module contains the following parts:
*
* 1. A routine which provides procedural stimulus to the inputs of the
* controller design.
*
* 2. A routine to generate a test vector file by recording the stimulus.
*
* 3. A routine to generate an expected results file based on the outputs
* of the controller design.
****************************************************************************/
`timescale 1ns / 1ns
module test_vector_generator;
`define period 10
`define setup_time 2
`define fetch_cycle 80
`define prop_delay 5 /* time for changes on inputs to reach outputs */
`define outs rd,wr,ld_ir,ld_acc,ld_pc,inc_pc,halt,data_e,sel
reg [2:0] opcode;
reg rst, zero, clk;
integer vector_file ;
control i1(`outs, opcode, zero, clk, rst);
/*****************************************************************************
* Generate the clock
****************************************************************************/
initial
begin
clk=1;
forever #(`period/2) clk = !clk;
end
initial //CREATE INPUT STIMULUS WITH PROCEDURAL STATEMENTS
begin
$timeformat(-9, 1, " ns", 9); //display time in nanoseconds
//reset the system
{zero, opcode, rst} = 0;
//test all instructions except halt with zero bit = 0
#(`fetch_cycle - `setup_time - 10)
rst = 1;
for (opcode = 1; opcode < 7; opcode = opcode + 1)
#`fetch_cycle ; //change opcode just before fetch
opcode = 7; #`fetch_cycle
//test all instructions except halt with zero bit = 1
zero = 1;
for (opcode = 1; opcode < 7; opcode = opcode + 1)
#`fetch_cycle ; //change opcode just before fetch
opcode = 7; #`fetch_cycle
//test halt instruction
opcode = 0; #`fetch_cycle
$display("\n*** Completed generating new pattern files. ***\n");
$finish;
end
initial //WRITE INPUT STUMULUS TO TEST VECTOR FILE
begin
$display("\n*** Generating test vector file ",
"\"test_vectors.pat\"...");
vector_file = $fopen("test_vectors.pat");
$fdisplay(vector_file,"//TEST VECTORS FOR TESTING THE SEQUENCE CONTROLLER");
$fdisplay(vector_file,"//");
$fdisplay(vector_file,"//THE VECTOR ORDER IS: rst zero_bit opcode");
$fdisplay(vector_file,"//");
//write first pattern to file at end of time 0
$fstrobe(vector_file,"%b_%b_%b", rst, zero, opcode);
forever #`fetch_cycle //write input pattern to file at every fetch
$fstrobe(vector_file,"%b_%b_%b", rst, zero, opcode);
end
/*****************************************************************************
* Block to generate a new file of expected results based on the current test
* pattern file and decoder model.
****************************************************************************/
initial
begin : gen_results
integer result_file;
$display("\n*** Generating a new expected results file...");
result_file = $fopen("expected_results.pat");
$fdisplay(result_file,"//EXPECTED RESULT PATTERNS FOR TESTING THE ",
"VeriRisc SEQUENCE CONTROLLER");
$fdisplay(result_file,"//");
$fdisplay(result_file,"//THE PATTERN ORDER IS: rd wr ld_ir ld_acc ",
"ld_pc inc_pc halt data_e sel");
$fdisplay(result_file,"//");
wait (opcode)
forever @(posedge clk)
#`prop_delay $fstrobe(result_file, `outs);
end
endmodule
| 7.358377 |
module vga_bounceball_test;
// input
reg clk;
reg nreset;
// output
wire vga_hs;
wire vga_vs;
wire [2:0] red;
wire [2:0] green;
wire [2:0] blue;
reg xpos_ball;
reg ypos_ball;
// Instantiate the Unit Under Test (UUT)
vga_bounceball uut (
.clk(clk),
.nreset(nreset),
.vga_hs(vga_hs),
.vga_vs(vga_vs),
.red(red),
.green(green),
.blue(blue)
);
initial begin
$dumpfile("vga_bounceball.vcd");
$dumpvars(0, uut);
// $monitor("At time %t, cs %0d, clk %0d, mosi %0d, debug1 %0d, debug2 %0d", $time, spi_cs, spi_clk, spi_mosi, debug1, debug2);
// Initialize Inputs
clk = 0;
nreset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
repeat (10) begin
#10;
clk = ~clk;
end
nreset = 1;
// Add stimulus here
repeat (400000) begin
#10;
clk = ~clk;
end
repeat (40000000) begin
#10;
clk = ~clk;
end
end
// dds_tlc5615 d1 (clk,nreset,spi_cs,spi_clk,spi_mosi,debug1,debug2);
endmodule
| 6.522684 |
module Test_VGA_Keyboard;
reg clk, rst;
reg ps2_clk, ps2_data;
wire ready, hsync, vsync;
wire [3:0] r, g, b;
reg [63:0] counter;
Keyboard_DEMO demo (
.clk(clk),
.rst(rst),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.ready(ready),
.hsync(hsync),
.vsync(vsync),
.r(r),
.g(g),
.b(b)
);
task RESET;
begin
rst = 0;
clk = 0;
ps2_clk = 1;
ps2_data = 1;
counter = 0;
#5 rst = 1;
#5 rst = 0;
end
endtask
task CLOCK;
input [63:0] count;
integer k;
begin
for (k = 0; k < count; k = k + 1) begin
#5 clk = 1;
#5 clk = 0;
counter = counter + 1;
end
end
endtask
reg [10:0] payload;
task PS2_TRANSMIT;
input [7:0] send;
integer k;
begin
payload = {
1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0
};
$display("payload = 0b%b", payload);
for (k = 0; k < 11; k = k + 1) begin
ps2_data = payload[k];
ps2_clk = 1;
$display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send,
ps2_data, k);
CLOCK(1);
ps2_clk = 0;
CLOCK(1);
end
ps2_clk = 1;
CLOCK(1);
end
endtask
parameter LOAD_RAM = 32'd2400;
parameter FULL_CYCLE = 32'd1_555_738;
initial begin
#10 #10 RESET;
CLOCK(LOAD_RAM);
//// pressing A key
CLOCK(5);
PS2_TRANSMIT(`A_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`A_SCAN_CODE);
CLOCK(10);
//// press shift key
PS2_TRANSMIT(`SHIFT_CODE_LEFT);
CLOCK(10);
//// press lowercase a key
PS2_TRANSMIT(`A_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`A_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`SHIFT_CODE_LEFT);
CLOCK(10);
//// press B scancode
PS2_TRANSMIT(`B_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`B_SCAN_CODE);
CLOCK(10);
//// press C scancode
PS2_TRANSMIT(8'h21);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(8'h21);
CLOCK(10);
//// press backspace
PS2_TRANSMIT(8'h66);
CLOCK(10);
CLOCK(FULL_CYCLE);
PS2_TRANSMIT(8'h21);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(8'h21);
CLOCK(10);
CLOCK(FULL_CYCLE);
#10 $stop;
#5 $finish;
end
endmodule
| 6.863595 |
module test_vga_nexys3 (
input wire clk,
input wire clk_base,
input wire clk_bus,
input wire rst,
input wire cs,
input wire [7:0] mode,
output wire [31:0] data,
output wire [7:0] state,
// VGA interfaces
output wire vga_h_sync,
output wire vga_v_sync,
output wire [2:0] vga_red,
output wire [2:0] vga_green,
output wire [2:1] vga_blue
);
parameter CLK_FREQ = 100;
wire ack;
wire [31:0] dout;
reg [31:0] data_buf;
reg cs_prev;
always @(posedge clk_bus) begin
if (rst) cs_prev <= 0;
else cs_prev <= cs;
end
reg cs_buf;
always @(posedge clk_bus) begin
if (rst) cs_buf <= 0;
else if (cs & ~cs_prev) cs_buf <= 1;
else if (ack) cs_buf <= 0;
end
wire wb_cyc, wb_stb;
wire [31:2] wb_addr;
wire [2:0] wb_cti;
wire [1:0] wb_bte;
wire [31:0] wb_data;
wire wb_ack;
wb_vga_nexys3 #(
.CLK_FREQ(CLK_FREQ),
.DEV_ADDR_BITS(8)
) WB_VGA (
.clk(clk),
.rst(rst),
.clk_base(clk_base),
.h_sync(vga_h_sync),
.v_sync(vga_v_sync),
.r_color(vga_red),
.g_color(vga_green),
.b_color(vga_blue),
.wbm_clk_i(clk_bus),
.wbm_cyc_o(wb_cyc),
.wbm_stb_o(wb_stb),
.wbm_addr_o(wb_addr),
.wbm_cti_o(wb_cti),
.wbm_bte_o(wb_bte),
.wbm_sel_o(),
.wbm_we_o(),
.wbm_data_i(wb_data),
.wbm_data_o(),
.wbm_ack_i(wb_ack),
.wbs_clk_i(clk_bus),
.wbs_cs_i(cs_buf),
.wbs_addr_i(6'b0),
.wbs_sel_i(4'b1111),
.wbs_data_i({mode[7:4], 24'b0, mode[3:0]}),
.wbs_we_i(1'b1),
.wbs_data_o(dout),
.wbs_ack_o(ack)
);
assign wb_ack = wb_cyc & wb_stb,
wb_data = mode[7] ? {wb_addr[17:2], wb_addr[17:2]} : {24'h072007, wb_addr[9:2]};
always @(posedge clk_bus) begin
if (rst) data_buf <= 0;
else if (ack) data_buf <= dout;
end
assign data = data_buf;
assign state = {wb_cyc, wb_stb, 1'b0, wb_ack, 3'b0, ack};
endmodule
| 7.789579 |
module test_vga_sword (
input wire clk,
input wire clk_base,
input wire clk_bus,
input wire rst,
input wire cs,
input wire [7:0] mode,
output wire [31:0] data,
output wire [7:0] state,
// VGA interfaces
output wire vga_h_sync,
output wire vga_v_sync,
output wire [3:0] vga_red,
output wire [3:0] vga_green,
output wire [3:0] vga_blue
);
parameter CLK_FREQ = 100;
wire ack;
wire [31:0] dout;
reg [31:0] data_buf;
reg cs_prev;
always @(posedge clk_bus) begin
if (rst) cs_prev <= 0;
else cs_prev <= cs;
end
reg cs_buf;
always @(posedge clk_bus) begin
if (rst) cs_buf <= 0;
else if (cs & ~cs_prev) cs_buf <= 1;
else if (ack) cs_buf <= 0;
end
wire wb_cyc, wb_stb;
wire [31:2] wb_addr;
wire [2:0] wb_cti;
wire [1:0] wb_bte;
wire [31:0] wb_data;
wire wb_ack;
wb_vga_sword #(
.CLK_FREQ(CLK_FREQ),
.DEV_ADDR_BITS(8)
) WB_VGA (
.clk(clk),
.rst(rst),
.clk_base(clk_base),
.h_sync(vga_h_sync),
.v_sync(vga_v_sync),
.r_color(vga_red),
.g_color(vga_green),
.b_color(vga_blue),
.wbm_clk_i(clk_bus),
.wbm_cyc_o(wb_cyc),
.wbm_stb_o(wb_stb),
.wbm_addr_o(wb_addr),
.wbm_cti_o(wb_cti),
.wbm_bte_o(wb_bte),
.wbm_sel_o(),
.wbm_we_o(),
.wbm_data_i(wb_data),
.wbm_data_o(),
.wbm_ack_i(wb_ack),
.wbs_clk_i(clk_bus),
.wbs_cs_i(cs_buf),
.wbs_addr_i(6'b0),
.wbs_sel_i(4'b1111),
.wbs_data_i({mode[7:4], 24'b0, mode[3:0]}),
.wbs_we_i(1'b1),
.wbs_data_o(dout),
.wbs_ack_o(ack)
);
assign wb_ack = wb_cyc & wb_stb,
wb_data = mode[7] ? {wb_addr[17:2], wb_addr[17:2]} : {24'h072007, wb_addr[9:2]};
always @(posedge clk_bus) begin
if (rst) data_buf <= 0;
else if (ack) data_buf <= dout;
end
assign data = data_buf;
assign state = {wb_cyc, wb_stb, 1'b0, wb_ack, 3'b0, ack};
endmodule
| 6.918621 |
module test_wave (
input sclk,
output signed [13:0] data_out
);
//--------------------------------------------------------//
parameter Freq_I = 32'd4294967; //frequence_I = 500k
parameter Freq_Q = 32'd12884902; //frequence_Q = 1.5M
parameter cnt_width = 8'd32;
//--------------------------------------------------------//
//--------------------------------------------------------//
reg [cnt_width-1:0] cnt_I = 0;
reg [cnt_width-1:0] cnt_Q = 0;
wire [ 9:0] addr_I;
wire [ 9:0] addr_Q;
always @(posedge sclk) begin
cnt_I <= cnt_I + Freq_I;
cnt_Q <= cnt_Q + Freq_Q;
end
assign addr_I = cnt_I[cnt_width-1:cnt_width-10];
assign addr_Q = cnt_Q[cnt_width-1:cnt_width-10];
//--------------------------------------------------------//
//-----------------����ROM��--------------------//
wire signed [13:0] cos_50;
wire signed [13:0] cos_150;
ROM ROM_inst0 (
.clka (sclk),
.addra(addr_I),
.douta(cos_50),
.clkb (sclk),
.addrb(addr_Q),
.doutb(cos_150)
);
//---------------------------------------------------------//
/*
//----------------���üӷ���------------------//
wire signed [13:0] data_add;
ADD ADD_inst1(
.A (cos_50),
.B (cos_150),
.CLK (sclk),
.S (data_add)
);
*/
assign data_out = {cos_150[13], cos_150[13:1]} + {cos_50[13], cos_50[13:1]};
endmodule
| 6.672295 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [9:0] test_vector_idx = 0;
reg [7:0] test_vector[0:1023];
integer i;
initial begin
i = 0;
// Zero bytes
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
// Garbage
test_vector[i++] = 8'h23;
test_vector[i++] = 8'hE0;
test_vector[i++] = 8'h01;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'hFA;
test_vector[i++] = 8'h77;
// Command 1 - WR_AINCR
test_vector[i++] = 8'hA3; // CMD
test_vector[i++] = 8'd03; // CNT0
test_vector[i++] = 8'd00; // ADDR0
test_vector[i++] = 8'hA0; // DATA
test_vector[i++] = 8'hA1; // DATA
test_vector[i++] = 8'hA2; // DATA
test_vector[i++] = 8'hA3; // DATA
test_vector[i++] = 8'hA4; // DATA
test_vector[i++] = 8'hA5; // DATA
test_vector[i++] = 8'hA6; // DATA
test_vector[i++] = 8'hA7; // DATA
test_vector[i++] = 8'hA8; // DATA
test_vector[i++] = 8'hA9; // DATA
test_vector[i++] = 8'hAA; // DATA
test_vector[i++] = 8'hAB; // DATA
test_vector[i++] = 8'hAC; // DATA
test_vector[i++] = 8'hAD; // DATA
test_vector[i++] = 8'hAE; // DATA
test_vector[i++] = 8'hAF; // DATA
// Command 2 - WR_AINCR
test_vector[i++] = 8'hA3; // CMD
test_vector[i++] = 8'd00; // CNT0
test_vector[i++] = 8'd00; // ADDR0
test_vector[i++] = 8'hB0; // DATA
test_vector[i++] = 8'hB1; // DATA
test_vector[i++] = 8'hB2; // DATA
test_vector[i++] = 8'hB3; // DATA
// Command 3 - WR_FIXED
test_vector[i++] = 8'hA1; // CMD
test_vector[i++] = 8'd02; // CNT0
test_vector[i++] = 8'd01; // ADDR0
test_vector[i++] = 8'hB0; // DATA
test_vector[i++] = 8'hB1; // DATA
test_vector[i++] = 8'hB2; // DATA
test_vector[i++] = 8'hB3; // DATA
test_vector[i++] = 8'hB4; // DATA
test_vector[i++] = 8'hB5; // DATA
test_vector[i++] = 8'hB6; // DATA
test_vector[i++] = 8'hB7; // DATA
test_vector[i++] = 8'hB8; // DATA
test_vector[i++] = 8'hB9; // DATA
test_vector[i++] = 8'hBA; // DATA
test_vector[i++] = 8'hBB; // DATA
// Command 4 - RD_FIXED
test_vector[i++] = 8'hA2; // CMD
test_vector[i++] = 8'd01; // CNT0
test_vector[i++] = 8'd01; // ADDR0
// Command 5 - WR_AINCR
test_vector[i++] = 8'hA3; // CMD
test_vector[i++] = 8'd01; // CNT0
test_vector[i++] = 8'd05; // ADDR0
test_vector[i++] = 8'hC0; // DATA
test_vector[i++] = 8'hC1; // DATA
test_vector[i++] = 8'hC2; // DATA
test_vector[i++] = 8'hC3; // DATA
test_vector[i++] = 8'hC4; // DATA
test_vector[i++] = 8'hC5; // DATA
test_vector[i++] = 8'hC6; // DATA
test_vector[i++] = 8'hC7; // DATA
// Command 6 - RD_AINCR
test_vector[i++] = 8'hA4; // CMD
test_vector[i++] = 8'd07; // CNT0
test_vector[i++] = 8'd00; // ADDR0
// Garbage
test_vector[i++] = 8'h23;
test_vector[i++] = 8'hE0;
test_vector[i++] = 8'h01;
//
for (i = i; i < 1024; i = i + 1) begin
test_vector[i] = 8'b0;
end
end
assign o_valid = i_enable;
assign o_data = test_vector[test_vector_idx];
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction happens, increment idx
test_vector_idx <= test_vector_idx + 10'd1;
end
end
endmodule
| 6.890266 |
module test_wbcon;
localparam WB_ADDR_WIDTH = 8;
localparam COUNT_WIDTH = 8;
wb_mem_dly #(
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.STALL_WS(0),
.ACK_WS(0)
) mem (
.i_clk(clk),
.i_rst(rst),
// wb
.i_wb_cyc(wb_cyc),
.i_wb_stb(wb_stb),
.o_wb_stall(wb_stall),
.o_wb_ack(wb_ack),
.i_wb_we(wb_we),
.i_wb_addr(wb_addr),
.i_wb_data(wb_data_w),
.i_wb_sel(wb_sel),
.o_wb_data(wb_data_r)
);
stream_gen rx_stream (
.i_clk(clk),
.i_enable(rx_en),
.i_ready(rx_ready),
.o_data(rx_data),
.o_valid(rx_valid)
);
wbcon #(
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.COUNT_WIDTH (COUNT_WIDTH)
) dut (
.i_clk(clk),
.i_rst(rst),
// wb
.o_wb_cyc(wb_cyc),
.o_wb_stb(wb_stb),
.i_wb_stall(wb_stall),
.i_wb_ack(wb_ack),
.o_wb_we(wb_we),
.o_wb_addr(wb_addr),
.o_wb_data(wb_data_w),
.o_wb_sel(wb_sel),
.i_wb_data(wb_data_r),
// rx
.o_rx_ready(rx_ready),
.i_rx_data(rx_data),
.i_rx_valid(rx_valid),
// tx
.i_tx_ready(tx_ready),
.o_tx_data(tx_data),
.o_tx_valid(tx_valid)
);
reg clk = 0;
reg rst = 0;
reg rx_en = 1;
// wb
wire wb_cyc;
wire wb_stb;
wire wb_stall;
wire wb_ack;
wire wb_we;
wire [WB_ADDR_WIDTH-1:0] wb_addr;
wire [31:0] wb_data_w;
wire [3:0] wb_sel;
wire [31:0] wb_data_r;
// rx stream
wire [7:0] rx_data;
wire rx_valid;
wire rx_ready;
// tx stream
wire [7:0] tx_data;
wire tx_valid;
reg tx_ready = 0;
always #5 clk = ~clk;
always @(posedge clk) begin
if (rx_valid && rx_ready) begin
$display("Rx: 0x%02x", rx_data);
end
if (tx_valid && tx_ready) begin
$display("Tx: 0x%02x", tx_data);
end
if (wb_cyc && wb_stb && !wb_stall) begin
$display("WB: req addr=0x%0x sel=%4b we=%b wdata=0x%08x", wb_addr, wb_sel, wb_we, wb_data_w);
end
if (wb_cyc && wb_ack) begin
$display("WB: ack rdata=0x%08x", wb_data_r);
end
end
initial begin
$dumpfile("test_wbcon.vcd");
$dumpvars(0);
repeat (5) @(posedge clk);
rst <= 1;
repeat (5) @(posedge clk);
rst <= 0;
repeat (5) @(posedge clk);
tx_ready <= 1;
repeat (10) @(posedge clk);
rx_en <= 0;
repeat (10) @(posedge clk);
tx_ready <= 0;
repeat (10) @(posedge clk);
rx_en <= 1;
repeat (50) @(posedge clk);
tx_ready <= 1;
repeat (150) @(posedge clk);
$finish;
end
endmodule
| 6.98367 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = d;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction happens, increment data
d <= d + 8'd1;
end
end
endmodule
| 6.890266 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [9:0] test_vector_idx = 0;
reg [7:0] test_vector[0:1023];
integer i;
initial begin
i = 0;
// Zero bytes
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
// Garbage
test_vector[i++] = 8'h23;
test_vector[i++] = 8'hFE;
test_vector[i++] = 8'h01;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'hFA;
test_vector[i++] = 8'h77;
// Command 1
test_vector[i++] = 8'hA1; // CMD
test_vector[i++] = 8'hAA; // CNT
test_vector[i++] = 8'hBB; // CNT
test_vector[i++] = 8'hCC; // ADDR
test_vector[i++] = 8'hDD; // ADDR
test_vector[i++] = 8'h80; // DATA
test_vector[i++] = 8'h90; // DATA
// Command 2
test_vector[i++] = 8'hA2; // CMD
test_vector[i++] = 8'hAA; // CNT
test_vector[i++] = 8'hBB; // CNT
test_vector[i++] = 8'hCC; // ADDR
test_vector[i++] = 8'hDD; // ADDR
// Command 3
test_vector[i++] = 8'hA3; // CMD
test_vector[i++] = 8'hAA; // CNT
test_vector[i++] = 8'hBB; // CNT
test_vector[i++] = 8'hCC; // ADDR
test_vector[i++] = 8'hDD; // ADDR
test_vector[i++] = 8'h80; // DATA
test_vector[i++] = 8'h90; // DATA
// Command 4
test_vector[i++] = 8'hA4; // CMD
test_vector[i++] = 8'hAA; // CNT
test_vector[i++] = 8'hBB; // CNT
test_vector[i++] = 8'hCC; // ADDR
test_vector[i++] = 8'hDD; // ADDR
// Garbage
test_vector[i++] = 8'h23;
test_vector[i++] = 8'hFE;
test_vector[i++] = 8'h01;
//
for (i = i; i < 1024; i = i + 1) begin
test_vector[i] = 8'b0;
end
end
assign o_valid = i_enable;
assign o_data = test_vector[test_vector_idx];
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction happens, increment idx
test_vector_idx <= test_vector_idx + 10'd1;
end
end
endmodule
| 6.890266 |
module test_wbcon_tx;
reg clk = 0;
reg rst = 0;
reg mreq_valid = 0;
wire mreq_ready;
wire exec_mreq_valid;
wire exec_mreq_ready;
reg exec_mreq_done = 0;
//
wire [7:0] tx_data;
wire tx_valid;
reg tx_ready = 1;
//
reg [7:0] body_data = 8'hAA;
reg body_valid = 1;
wire body_ready;
wbcon_tx dut (
.i_clk(clk),
.i_rst(rst),
//
.o_tx_data(tx_data),
.o_tx_valid(tx_valid),
.i_tx_ready(tx_ready),
//
.i_body_data(body_data),
.i_body_valid(body_valid),
.o_body_ready(body_ready),
//
.i_mreq_valid(mreq_valid),
.o_mreq_ready(mreq_ready),
//
.o_mreq_valid(exec_mreq_valid),
.i_mreq_ready(exec_mreq_ready)
);
assign exec_mreq_ready = exec_mreq_valid & exec_mreq_done;
always #5 clk = ~clk;
always @(posedge clk) begin
if (tx_valid && tx_ready) $display("TX: %02x", tx_data);
if (mreq_valid && mreq_ready) $display(">>> MREQ UP ACK");
if (exec_mreq_valid && exec_mreq_ready) $display(">>> MREQ DOWN ACK");
if (body_valid && body_ready) $display("BODY: %02x", body_data);
end
initial begin
$dumpfile("test_wbcon_tx.vcd");
$dumpvars(0);
repeat (5) @(posedge clk);
rst <= 1;
repeat (1) @(posedge clk);
rst <= 0;
repeat (5) @(posedge clk);
// Long confirmation
mreq_valid <= 1;
repeat (5) @(posedge clk);
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
mreq_valid <= 0;
repeat (10) @(posedge clk);
// Immediate confirmation
mreq_valid <= 1;
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
mreq_valid <= 0;
repeat (10) @(posedge clk);
// Short confirmation 1
mreq_valid <= 1;
repeat (1) @(posedge clk);
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
mreq_valid <= 0;
repeat (10) @(posedge clk);
// Short confirmation 2
mreq_valid <= 1;
repeat (2) @(posedge clk);
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
mreq_valid <= 0;
repeat (10) @(posedge clk);
// Short confirmation 3
mreq_valid <= 1;
repeat (3) @(posedge clk);
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
mreq_valid <= 0;
repeat (10) @(posedge clk);
// Immediate restart with immediate confirmation (x2)
mreq_valid <= 1;
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
@(posedge clk);
while (!mreq_ready) @(posedge clk);
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
mreq_valid <= 0;
repeat (10) @(posedge clk);
// Immediate restart with short confirmation (x2)
mreq_valid <= 1;
//
@(posedge clk);
while (!exec_mreq_valid) @(posedge clk);
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
//
@(posedge clk);
while (!exec_mreq_valid) @(posedge clk);
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
//
@(posedge clk);
while (!exec_mreq_valid) @(posedge clk);
exec_mreq_done <= 1;
@(posedge clk);
while (!mreq_ready) @(posedge clk);
exec_mreq_done <= 0;
//
mreq_valid <= 0;
repeat (10) @(posedge clk);
$finish;
end
endmodule
| 6.536109 |
module test_wb_adapter_16_32;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 16;
parameter WBM_SELECT_WIDTH = 2;
parameter WBS_DATA_WIDTH = 32;
parameter WBS_SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbm_adr_i, wbm_dat_i, wbm_we_i, wbm_sel_i, wbm_stb_i,
wbm_cyc_i, wbs_dat_i, wbs_ack_i, wbs_err_i, wbs_rty_i);
$to_myhdl(wbm_dat_o, wbm_ack_o, wbm_err_o, wbm_rty_o, wbs_adr_o, wbs_dat_o, wbs_we_o,
wbs_sel_o, wbs_stb_o, wbs_cyc_o);
// dump file
$dumpfile("test_wb_adapter_16_32.lxt");
$dumpvars(0, test_wb_adapter_16_32);
end
wb_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.WBM_DATA_WIDTH(WBM_DATA_WIDTH),
.WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
.WBS_DATA_WIDTH(WBS_DATA_WIDTH),
.WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
| 8.256746 |
module test_wb_adapter_32_16;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 32;
parameter WBM_SELECT_WIDTH = 4;
parameter WBS_DATA_WIDTH = 16;
parameter WBS_SELECT_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbm_adr_i, wbm_dat_i, wbm_we_i, wbm_sel_i, wbm_stb_i,
wbm_cyc_i, wbs_dat_i, wbs_ack_i, wbs_err_i, wbs_rty_i);
$to_myhdl(wbm_dat_o, wbm_ack_o, wbm_err_o, wbm_rty_o, wbs_adr_o, wbs_dat_o, wbs_we_o,
wbs_sel_o, wbs_stb_o, wbs_cyc_o);
// dump file
$dumpfile("test_wb_adapter_32_16.lxt");
$dumpvars(0, test_wb_adapter_32_16);
end
wb_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.WBM_DATA_WIDTH(WBM_DATA_WIDTH),
.WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
.WBS_DATA_WIDTH(WBS_DATA_WIDTH),
.WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
| 8.256746 |
module test_wb_adapter_32_8;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 32;
parameter WBM_SELECT_WIDTH = 4;
parameter WBS_DATA_WIDTH = 8;
parameter WBS_SELECT_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbm_adr_i, wbm_dat_i, wbm_we_i, wbm_sel_i, wbm_stb_i,
wbm_cyc_i, wbs_dat_i, wbs_ack_i, wbs_err_i, wbs_rty_i);
$to_myhdl(wbm_dat_o, wbm_ack_o, wbm_err_o, wbm_rty_o, wbs_adr_o, wbs_dat_o, wbs_we_o,
wbs_sel_o, wbs_stb_o, wbs_cyc_o);
// dump file
$dumpfile("test_wb_adapter_32_8.lxt");
$dumpvars(0, test_wb_adapter_32_8);
end
wb_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.WBM_DATA_WIDTH(WBM_DATA_WIDTH),
.WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
.WBS_DATA_WIDTH(WBS_DATA_WIDTH),
.WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
| 8.256746 |
module test_wb_adapter_8_32;
// Parameters
parameter ADDR_WIDTH = 32;
parameter WBM_DATA_WIDTH = 8;
parameter WBM_SELECT_WIDTH = 1;
parameter WBS_DATA_WIDTH = 32;
parameter WBS_SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [WBM_DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [WBM_SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [WBS_DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [WBM_DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [WBS_DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [WBS_SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbm_adr_i, wbm_dat_i, wbm_we_i, wbm_sel_i, wbm_stb_i,
wbm_cyc_i, wbs_dat_i, wbs_ack_i, wbs_err_i, wbs_rty_i);
$to_myhdl(wbm_dat_o, wbm_ack_o, wbm_err_o, wbm_rty_o, wbs_adr_o, wbs_dat_o, wbs_we_o,
wbs_sel_o, wbs_stb_o, wbs_cyc_o);
// dump file
$dumpfile("test_wb_adapter_8_32.lxt");
$dumpvars(0, test_wb_adapter_8_32);
end
wb_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.WBM_DATA_WIDTH(WBM_DATA_WIDTH),
.WBM_SELECT_WIDTH(WBM_SELECT_WIDTH),
.WBS_DATA_WIDTH(WBS_DATA_WIDTH),
.WBS_SELECT_WIDTH(WBS_SELECT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
| 8.256746 |
module test_wb_arbiter_2;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = (DATA_WIDTH / 8);
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm0_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm0_dat_i = 0;
reg wbm0_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm0_sel_i = 0;
reg wbm0_stb_i = 0;
reg wbm0_cyc_i = 0;
reg [ADDR_WIDTH-1:0] wbm1_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm1_dat_i = 0;
reg wbm1_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm1_sel_i = 0;
reg wbm1_stb_i = 0;
reg wbm1_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm0_dat_o;
wire wbm0_ack_o;
wire wbm0_err_o;
wire wbm0_rty_o;
wire [DATA_WIDTH-1:0] wbm1_dat_o;
wire wbm1_ack_o;
wire wbm1_err_o;
wire wbm1_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbm0_adr_i, wbm0_dat_i, wbm0_we_i, wbm0_sel_i, wbm0_stb_i,
wbm0_cyc_i, wbm1_adr_i, wbm1_dat_i, wbm1_we_i, wbm1_sel_i, wbm1_stb_i, wbm1_cyc_i,
wbs_dat_i, wbs_ack_i, wbs_err_i, wbs_rty_i);
$to_myhdl(wbm0_dat_o, wbm0_ack_o, wbm0_err_o, wbm0_rty_o, wbm1_dat_o, wbm1_ack_o, wbm1_err_o,
wbm1_rty_o, wbs_adr_o, wbs_dat_o, wbs_we_o, wbs_sel_o, wbs_stb_o, wbs_cyc_o);
// dump file
$dumpfile("test_wb_arbiter_2.lxt");
$dumpvars(0, test_wb_arbiter_2);
end
wb_arbiter_2 #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
) UUT (
.clk(clk),
.rst(rst),
.wbm0_adr_i(wbm0_adr_i),
.wbm0_dat_i(wbm0_dat_i),
.wbm0_dat_o(wbm0_dat_o),
.wbm0_we_i(wbm0_we_i),
.wbm0_sel_i(wbm0_sel_i),
.wbm0_stb_i(wbm0_stb_i),
.wbm0_ack_o(wbm0_ack_o),
.wbm0_err_o(wbm0_err_o),
.wbm0_rty_o(wbm0_rty_o),
.wbm0_cyc_i(wbm0_cyc_i),
.wbm1_adr_i(wbm1_adr_i),
.wbm1_dat_i(wbm1_dat_i),
.wbm1_dat_o(wbm1_dat_o),
.wbm1_we_i(wbm1_we_i),
.wbm1_sel_i(wbm1_sel_i),
.wbm1_stb_i(wbm1_stb_i),
.wbm1_ack_o(wbm1_ack_o),
.wbm1_err_o(wbm1_err_o),
.wbm1_rty_o(wbm1_rty_o),
.wbm1_cyc_i(wbm1_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
| 7.035949 |
module test_wb_async_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg wbm_clk = 0;
reg wbm_rst = 0;
reg wbs_clk = 0;
reg wbs_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(wbm_clk, wbm_rst, wbs_clk, wbs_rst, current_test, wbm_adr_i, wbm_dat_i, wbm_we_i,
wbm_sel_i, wbm_stb_i, wbm_cyc_i, wbs_dat_i, wbs_ack_i, wbs_err_i, wbs_rty_i);
$to_myhdl(wbm_dat_o, wbm_ack_o, wbm_err_o, wbm_rty_o, wbs_adr_o, wbs_dat_o, wbs_we_o,
wbs_sel_o, wbs_stb_o, wbs_cyc_o);
// dump file
$dumpfile("test_wb_async_reg.lxt");
$dumpvars(0, test_wb_async_reg);
end
wb_async_reg #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
) UUT (
.wbm_clk (wbm_clk),
.wbm_rst (wbm_rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i (wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_clk (wbs_clk),
.wbs_rst (wbs_rst),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o (wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
| 7.700978 |
module test_wb_dp_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg a_clk = 0;
reg a_rst = 0;
reg b_clk = 0;
reg b_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] a_adr_i = 0;
reg [DATA_WIDTH-1:0] a_dat_i = 0;
reg a_we_i = 0;
reg [SELECT_WIDTH-1:0] a_sel_i = 0;
reg a_stb_i = 0;
reg a_cyc_i = 0;
reg [ADDR_WIDTH-1:0] b_adr_i = 0;
reg [DATA_WIDTH-1:0] b_dat_i = 0;
reg b_we_i = 0;
reg [SELECT_WIDTH-1:0] b_sel_i = 0;
reg b_stb_i = 0;
reg b_cyc_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] a_dat_o;
wire a_ack_o;
wire [DATA_WIDTH-1:0] b_dat_o;
wire b_ack_o;
initial begin
// myhdl integration
$from_myhdl(a_clk, a_rst, b_clk, b_rst, current_test, a_adr_i, a_dat_i, a_we_i, a_sel_i,
a_stb_i, a_cyc_i, b_adr_i, b_dat_i, b_we_i, b_sel_i, b_stb_i, b_cyc_i);
$to_myhdl(a_dat_o, a_ack_o, b_dat_o, b_ack_o);
// dump file
$dumpfile("test_wb_dp_ram.lxt");
$dumpvars(0, test_wb_dp_ram);
end
wb_dp_ram #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
) UUT (
.a_clk (a_clk),
.a_adr_i(a_adr_i),
.a_dat_i(a_dat_i),
.a_dat_o(a_dat_o),
.a_we_i (a_we_i),
.a_sel_i(a_sel_i),
.a_stb_i(a_stb_i),
.a_ack_o(a_ack_o),
.a_cyc_i(a_cyc_i),
.b_clk (b_clk),
.b_adr_i(b_adr_i),
.b_dat_i(b_dat_i),
.b_dat_o(b_dat_o),
.b_we_i (b_we_i),
.b_sel_i(b_sel_i),
.b_stb_i(b_stb_i),
.b_ack_o(b_ack_o),
.b_cyc_i(b_cyc_i)
);
endmodule
| 7.622853 |
module test_wb_drp;
// Parameters
parameter ADDR_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wb_adr_i = 0;
reg [15:0] wb_dat_i = 0;
reg wb_we_i = 0;
reg wb_stb_i = 0;
reg wb_cyc_i = 0;
reg [15:0] drp_di = 0;
reg drp_rdy = 0;
// Outputs
wire [15:0] wb_dat_o;
wire wb_ack_o;
wire [ADDR_WIDTH-1:0] drp_addr;
wire [15:0] drp_do;
wire drp_en;
wire drp_we;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wb_adr_i, wb_dat_i, wb_we_i, wb_stb_i, wb_cyc_i, drp_di,
drp_rdy);
$to_myhdl(wb_dat_o, wb_ack_o, drp_addr, drp_do, drp_en, drp_we);
// dump file
$dumpfile("test_wb_drp.lxt");
$dumpvars(0, test_wb_drp);
end
wb_drp #(
.ADDR_WIDTH(ADDR_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_i(wb_we_i),
.wb_stb_i(wb_stb_i),
.wb_ack_o(wb_ack_o),
.wb_cyc_i(wb_cyc_i),
.drp_addr(drp_addr),
.drp_do(drp_do),
.drp_di(drp_di),
.drp_en(drp_en),
.drp_we(drp_we),
.drp_rdy(drp_rdy)
);
endmodule
| 6.871205 |
module test_wb_mux_2;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs0_dat_i = 0;
reg wbs0_ack_i = 0;
reg wbs0_err_i = 0;
reg wbs0_rty_i = 0;
reg [ADDR_WIDTH-1:0] wbs0_addr = 0;
reg [ADDR_WIDTH-1:0] wbs0_addr_msk = 0;
reg [DATA_WIDTH-1:0] wbs1_dat_i = 0;
reg wbs1_ack_i = 0;
reg wbs1_err_i = 0;
reg wbs1_rty_i = 0;
reg [ADDR_WIDTH-1:0] wbs1_addr = 0;
reg [ADDR_WIDTH-1:0] wbs1_addr_msk = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs0_adr_o;
wire [DATA_WIDTH-1:0] wbs0_dat_o;
wire wbs0_we_o;
wire [SELECT_WIDTH-1:0] wbs0_sel_o;
wire wbs0_stb_o;
wire wbs0_cyc_o;
wire [ADDR_WIDTH-1:0] wbs1_adr_o;
wire [DATA_WIDTH-1:0] wbs1_dat_o;
wire wbs1_we_o;
wire [SELECT_WIDTH-1:0] wbs1_sel_o;
wire wbs1_stb_o;
wire wbs1_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbm_adr_i, wbm_dat_i, wbm_we_i, wbm_sel_i, wbm_stb_i,
wbm_cyc_i, wbs0_dat_i, wbs0_ack_i, wbs0_err_i, wbs0_rty_i, wbs0_addr, wbs0_addr_msk,
wbs1_dat_i, wbs1_ack_i, wbs1_err_i, wbs1_rty_i, wbs1_addr, wbs1_addr_msk);
$to_myhdl(wbm_dat_o, wbm_ack_o, wbm_err_o, wbm_rty_o, wbs0_adr_o, wbs0_dat_o, wbs0_we_o,
wbs0_sel_o, wbs0_stb_o, wbs0_cyc_o, wbs1_adr_o, wbs1_dat_o, wbs1_we_o, wbs1_sel_o,
wbs1_stb_o, wbs1_cyc_o);
// dump file
$dumpfile("test_wb_mux_2.lxt");
$dumpvars(0, test_wb_mux_2);
end
wb_mux_2 #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs0_adr_o(wbs0_adr_o),
.wbs0_dat_i(wbs0_dat_i),
.wbs0_dat_o(wbs0_dat_o),
.wbs0_we_o(wbs0_we_o),
.wbs0_sel_o(wbs0_sel_o),
.wbs0_stb_o(wbs0_stb_o),
.wbs0_ack_i(wbs0_ack_i),
.wbs0_err_i(wbs0_err_i),
.wbs0_rty_i(wbs0_rty_i),
.wbs0_cyc_o(wbs0_cyc_o),
.wbs0_addr(wbs0_addr),
.wbs0_addr_msk(wbs0_addr_msk),
.wbs1_adr_o(wbs1_adr_o),
.wbs1_dat_i(wbs1_dat_i),
.wbs1_dat_o(wbs1_dat_o),
.wbs1_we_o(wbs1_we_o),
.wbs1_sel_o(wbs1_sel_o),
.wbs1_stb_o(wbs1_stb_o),
.wbs1_ack_i(wbs1_ack_i),
.wbs1_err_i(wbs1_err_i),
.wbs1_rty_i(wbs1_rty_i),
.wbs1_cyc_o(wbs1_cyc_o),
.wbs1_addr(wbs1_addr),
.wbs1_addr_msk(wbs1_addr_msk)
);
endmodule
| 6.699358 |
module test_wb_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] adr_i = 0;
reg [DATA_WIDTH-1:0] dat_i = 0;
reg we_i = 0;
reg [SELECT_WIDTH-1:0] sel_i = 0;
reg stb_i = 0;
reg cyc_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] dat_o;
wire ack_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, adr_i, dat_i, we_i, sel_i, stb_i, cyc_i);
$to_myhdl(dat_o, ack_o);
// dump file
$dumpfile("test_wb_ram.lxt");
$dumpvars(0, test_wb_ram);
end
wb_ram #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
) UUT (
.clk (clk),
.adr_i(adr_i),
.dat_i(dat_i),
.dat_o(dat_o),
.we_i (we_i),
.sel_i(sel_i),
.stb_i(stb_i),
.ack_o(ack_o),
.cyc_i(cyc_i)
);
endmodule
| 7.612469 |
module test_wb_reg;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter SELECT_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] wbm_adr_i = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i = 0;
reg wbm_we_i = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i = 0;
reg wbm_stb_i = 0;
reg wbm_cyc_i = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i = 0;
reg wbs_ack_i = 0;
reg wbs_err_i = 0;
reg wbs_rty_i = 0;
// Outputs
wire [DATA_WIDTH-1:0] wbm_dat_o;
wire wbm_ack_o;
wire wbm_err_o;
wire wbm_rty_o;
wire [ADDR_WIDTH-1:0] wbs_adr_o;
wire [DATA_WIDTH-1:0] wbs_dat_o;
wire wbs_we_o;
wire [SELECT_WIDTH-1:0] wbs_sel_o;
wire wbs_stb_o;
wire wbs_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbm_adr_i, wbm_dat_i, wbm_we_i, wbm_sel_i, wbm_stb_i,
wbm_cyc_i, wbs_dat_i, wbs_ack_i, wbs_err_i, wbs_rty_i);
$to_myhdl(wbm_dat_o, wbm_ack_o, wbm_err_o, wbm_rty_o, wbs_adr_o, wbs_dat_o, wbs_we_o,
wbs_sel_o, wbs_stb_o, wbs_cyc_o);
// dump file
$dumpfile("test_wb_reg.lxt");
$dumpvars(0, test_wb_reg);
end
wb_reg #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SELECT_WIDTH(SELECT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wbm_adr_i(wbm_adr_i),
.wbm_dat_i(wbm_dat_i),
.wbm_dat_o(wbm_dat_o),
.wbm_we_i(wbm_we_i),
.wbm_sel_i(wbm_sel_i),
.wbm_stb_i(wbm_stb_i),
.wbm_ack_o(wbm_ack_o),
.wbm_err_o(wbm_err_o),
.wbm_rty_o(wbm_rty_o),
.wbm_cyc_i(wbm_cyc_i),
.wbs_adr_o(wbs_adr_o),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_o(wbs_we_o),
.wbs_sel_o(wbs_sel_o),
.wbs_stb_o(wbs_stb_o),
.wbs_ack_i(wbs_ack_i),
.wbs_err_i(wbs_err_i),
.wbs_rty_i(wbs_rty_i),
.wbs_cyc_o(wbs_cyc_o)
);
endmodule
| 7.04094 |
module KGP_MiniRISC (
input clk,
rst,
output [3:0] opcode,
output [10:0] funct,
output [4:0] shamt,
output [31:0] pc_in,
output [31:0] reg_show1,
reg_show2,
reg_show3,
reg_show4,
reg_show5,
output [31:0] reg_show6,
reg_show7,
reg_show8,
reg_show9,
reg_show10
);
wire ALUSrc, IMMSel, MemWrite, MemRead;
wire [2:0] ALUOp;
wire [1:0] WriteReg, MemRegPC;
//wire [15:0] mem_before_extend;
//wire [21:0] branch_22_before_extend;
//wire alu_zero, alu_carry, alu_sign;
wire [31:0] ins, aluout;
mem_time_system sys (
.clk(clk),
.rst(rst),
.ins(ins),
.pc_in(pc_in),
.opcode(opcode),
.funct(funct),
.shamt(shamt),
.ALUOp(ALUOp),
.ALUSrc(ALUSrc),
.IMMSel(IMMSel),
.WriteReg(WriteReg),
.MemRegPC(MemRegPC),
.aluout(aluout),
.MemWrite(MemWrite),
.MemRead(MemRead),
.reg_show1(reg_show1),
.reg_show2(reg_show2),
.reg_show3(reg_show3),
.reg_show4(reg_show4),
.reg_show5(reg_show5),
.reg_show6(reg_show6),
.reg_show7(reg_show7),
.reg_show8(reg_show8),
.reg_show9(reg_show9),
.reg_show10(reg_show10)
);
main_control controlunit (
.ALUSrc(ALUSrc),
.IMMSel(IMMSel),
.MemWrite(MemWrite),
.MemRead(MemRead),
.ALUOp(ALUOp),
.WriteReg(WriteReg),
.MemRegPC(MemRegPC),
.opcode(opcode)
);
endmodule
| 6.590719 |
module used in used in GZIP.
*/
`timescale 1 ns / 10 ps
module test_word_merge;
integer i;
// Declare input/output variables
reg clk;
reg rst_n;
reg in_valid =0;
reg in_last =0;
reg [5:0] in_size=0;
reg [31:0] in_data=0;
reg [31:0] total_value = 0;
wire out_valid;
wire out_last;
wire [3:0] out_bvalid;
wire [31:0] out_data;
// Create clock signal - 100MHz
always
#5 clk = ~clk;
// Instantiate DUT
word_merge64 word_merge_i0(
// Module inputs
.clock(clk),
.reset(!rst_n),
.in_valid,
.in_last,
.in_size,
.in_data,
// Module outputs
.out_valid,
.out_last,
//.out_bvalid,
.out_data
);
initial
begin
$display($time, "<< Starting the Simulation >>");
clk = 0;
rst_n = 0;
in_valid = 0;
in_last = 0;
repeat(15) @(posedge clk);
rst_n = 1;
$display($time, "************************** WordMerge TEST **************************");
load_data_task(32'h555, 5'd12, 0);
load_data_task(32'hAAA, 5'd12, 0);
load_data_task(32'hDD, 5'd8, 0);
repeat(10) @(posedge clk);
load_data_task(32'hB, 5'd4, 0);
load_data_task(32'hC, 5'd4, 0);
load_data_task(32'hD, 5'd4, 0);
load_data_task(32'hE, 5'd4, 0);
load_data_task(32'hF, 5'd4, 0);
load_data_task(32'h1, 5'd4, 0);
load_data_task(32'h2, 5'd4, 0);
load_data_task(32'h3, 5'd4, 0);
repeat(10) @(posedge clk);
load_data_task(32'h3FFFF, 5'd18, 0);
load_data_task(32'hAAAAA, 5'd20, 0); // raman 6 biti in plus
repeat(20) @(posedge clk);
// Mai punem 17 biti si astia sunt ultimii
load_data_task(32'h2, 5'd2, 0); // ar trebui sa avem stocat 02 | 2A = 0x AA ; 8 biti valizi
load_data_task(32'hFFF, 5'd3, 0);
load_data_task(32'h0, 5'd1, 0);
load_data_task(32'hB, 5'd4, 0);
load_data_task(32'hCD, 5'd7, 0);
load_data_task(32'h1, 5'd1, 1); // va trebui sa avem pe iesire 18+6=24 biti = 00cdb7aa
//load_data_task(32'hFFFFFFFF, 5'd31, 0);
//load_data_task(32'hFFFFFFFF, 5'd30, 0);
//total_value = total_value + in_data[in_size:0];
$display($time, "************************** WordMerge test is DONE **************************");
end
// Display the result of the sliding window module
always @(posedge clk)
display_output_data(out_valid, out_last, out_bvalid, out_data);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Testing tasks
task load_data_task;
input [31:0] in_data_t;
input [5:0] in_size_t;
input in_last_t;
begin
in_valid = 1;
in_last = in_last_t;
in_size = in_size_t;
in_data = in_data_t;
$display($time, " Loading in_data=%h in_size=%d in_last=%b", in_data, in_size, in_last_t);
@(posedge clk);
in_valid = 0;
in_last = 0;
//@(posedge clk);
end
endtask //of load_data
// Task used to display data from the lz77 encoder
task display_output_data;
input out_valid;
input out_last;
input [3:0] out_bvalid;
input [31:0] out_data;
begin
if(out_valid || out_last) $display($time, "======================= Output character out_data=%h out_bvalid=%d out_last=%b =======================",
out_data, out_bvalid, out_last);
end
endtask
endmodule
| 7.760949 |
module used in used in GZIP.
*/
`timescale 1 ns / 10 ps
module test_word_merge64();
integer i;
// Declare input/output variables
reg clk;
reg rst_n;
reg in_valid =0;
reg in_last =0;
reg [6:0] in_size=0;
reg [63:0] in_data=0;
reg [63:0] total_value = 0;
wire out_valid;
wire out_last;
//wire [3:0] out_bvalid;
wire [63:0] out_data;
// Create clock signal - 100MHz
always
#5 clk = ~clk;
// Instantiate DUT
word_merge64 word_merge_i0(
// Module inputs
.clock(clk),
.reset(!rst_n),
.in_valid,
.in_last,
.in_size,
.in_data,
// Module outputs
.out_valid,
.out_last,
//.out_bvalid,
.out_data
);
initial
begin
$display($time, "<< Starting the Simulation >>");
clk = 0;
rst_n = 0;
in_valid = 0;
in_last = 0;
repeat(15) @(posedge clk);
rst_n = 1;
$display($time, "************************** WordMerge64 TEST **************************");
load_data_task(64'h555, 6'd12, 0);
load_data_task(64'hAAA, 6'd12, 0);
load_data_task(64'hDD, 6'd8, 0);
repeat(10) @(posedge clk);
load_data_task(64'hB, 6'd4, 0);
load_data_task(64'hC, 6'd4, 0);
load_data_task(64'hD, 6'd4, 0);
load_data_task(64'hE, 6'd4, 0);
load_data_task(64'hF, 6'd4, 0);
load_data_task(64'h1, 6'd4, 0);
load_data_task(64'h2, 6'd4, 0);
load_data_task(64'h3, 6'd4, 0);
repeat(10) @(posedge clk);
load_data_task(64'hABACAE123, 6'd36, 0);
load_data_task(64'h1, 6'd1, 0);
load_data_task(64'h5A5A5E0, 6'd27, 0);
/*repeat(20) @(posedge clk);
// Mai punem 17 biti si astia sunt ultimii
load_data_task(32'h2, 5'd2, 0); // ar trebui sa avem stocat 02 | 2A = 0x AA ; 8 biti valizi
load_data_task(32'hFFF, 5'd3, 0);
load_data_task(32'h0, 5'd1, 0);
load_data_task(32'hB, 5'd4, 0);
load_data_task(32'hCD, 5'd7, 0);
load_data_task(32'h1, 5'd1, 1); // va trebui sa avem pe iesire 18+6=24 biti = 00cdb7aa */
//load_data_task(32'hFFFFFFFF, 5'd31, 0);
//load_data_task(32'hFFFFFFFF, 5'd30, 0);
//total_value = total_value + in_data[in_size:0];
$display($time, "************************** WordMerge test is DONE **************************");
end
// Display the result of the sliding window module
always @(posedge clk)
display_output_data(out_valid, out_last, out_data);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Testing tasks
task load_data_task;
input [63:0] in_data_t;
input [6:0] in_size_t;
input in_last_t;
begin
in_valid = 1;
in_last = in_last_t;
in_size = in_size_t;
in_data = in_data_t;
$display($time, " Loading in_data=%h in_size=%d in_last=%b", in_data, in_size, in_last_t);
@(posedge clk);
in_valid = 0;
in_last = 0;
//@(posedge clk);
end
endtask //of load_data
// Task used to display data from the lz77 encoder
task display_output_data;
input out_valid;
input out_last;
//input [3:0] out_bvalid
input [63:0] out_data;
begin
if(out_valid || out_last) $display($time, "======================= Output character out_data=%h out_last=%b =======================",
out_data, out_last);
end
endtask
endmodule
| 7.760949 |
module : i_memory_interface
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module test_wrapper #(
parameter CORE = 0,
parameter DATA_WIDTH = 32,
parameter INDEX_BITS = 6,
parameter OFFSET_BITS = 3,
parameter ADDRESS_BITS = 11,
parameter PROGRAM = "../software/applications/binaries/<your_program>"
) (
input clock,
input reset,
input read,
input write,
input [ADDRESS_BITS-1:0] read_address,
input [ADDRESS_BITS-1:0] write_address,
input [DATA_WIDTH-1:0] in_data,
output reg [DATA_WIDTH-1:0] out_data
);
reg read_reg;
reg write_reg;
reg [ADDRESS_BITS-1:0] read_address_reg;
reg [ADDRESS_BITS-1:0] write_address_reg;
reg [DATA_WIDTH-1:0] in_data_reg;
BRAM #(
//BRAM_ADDRESS_STALL #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDRESS_BITS),
.INIT_FILE(PROGRAM)
) RAM (
.clock(clock),
.readEnable(read_reg),
.readAddress(read_address_reg),
.readData(out_data_wire),
.writeEnable(write_reg),
.writeAddress(write_address_reg),
.writeData(in_data_reg)
);
always@(posedge clock) begin
read_reg <= read;
write_reg <= write;
read_address_reg <= read_address;
out_data <= out_data_wire;
write_reg <= write;
write_address_reg <= write_address;
in_data_reg <= in_data;
end
endmodule
| 8.392825 |
module Write_MUX (
CLK,
RST,
HWDATA,
HWDATA_1,
HWDATA_2,
SEL
);
input [1:0] SEL;
input RST, CLK;
input [31:0] HWDATA_1, HWDATA_2;
output reg [31:0] HWDATA;
always @(posedge CLK or posedge RST) begin
if(SEL == 2'b01 && RST != 1) // Master 1 selected
begin
HWDATA = HWDATA_1;
end
else if(SEL == 2'b10 && RST != 1) // Master 2 selected
begin
HWDATA = HWDATA_2;
end
else if(RST == 1) // Async reset
begin
HWDATA = 32'bx;
end else begin
HWDATA = 32'bx;
end
end
endmodule
| 7.749282 |
module: test_with_alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module KGP_MiniRISC_tb;
// Inputs
reg clk;
reg rst;
integer i;
// Outputs
wire [3:0] opcode;
wire [10:0] funct;
wire [4:0] shamt;
wire [31:0] pc_in;
wire [31:0] reg_show1, reg_show2, reg_show3, reg_show4, reg_show5;
wire [31:0] reg_show6, reg_show7, reg_show8, reg_show9, reg_show10;
// Instantiate the Unit Under Test (UUT)
KGP_MiniRISC uut (
.clk(clk),
.rst(rst),
.opcode(opcode),
.funct(funct),
.shamt(shamt),
.pc_in(pc_in),
.reg_show1(reg_show1),
.reg_show2(reg_show2),
.reg_show3(reg_show3),
.reg_show4(reg_show4),
.reg_show5(reg_show5),
.reg_show6(reg_show6),
.reg_show7(reg_show7),
.reg_show8(reg_show8),
.reg_show9(reg_show9),
.reg_show10(reg_show10)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
#5;
rst = 1;
#5;
rst = 0;
$monitor($time, " pc: %d, opcde: %d, funct: %d, shamt: %d", pc_in, opcode, funct, shamt);
for(i=0;i<100;i=i+1) begin
$monitor($time, " pc: %d, opcde: %d, funct: %d, shamt: %d, $1: %d, $2: %d, $3: %d, $4: %d, $5: %d, $6: %d, $7: %d, $8: %d, $9: %d",
pc_in, opcode, funct, shamt, reg_show1, reg_show2, reg_show3, reg_show4, reg_show5, reg_show6, reg_show7, reg_show8, reg_show9);
//$monitor($time, " pc: %d, $1: %d, $2: %d, $3: %d", pc_in, uut.sys.regs.registers[0], uut.sys.regs.registers[1], uut.sys.regs.registers[2]);
#5;
end
// Add stimulus here
end
always #5 clk = ~clk;
endmodule
| 6.769852 |
module test_xfcp_mod_axil_32;
// Parameters
parameter XFCP_ID_TYPE = 16'h0001;
parameter XFCP_ID_STR = "AXIL Master";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
parameter COUNT_SIZE = 16;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter STRB_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in_tdata = 0;
reg up_xfcp_in_tvalid = 0;
reg up_xfcp_in_tlast = 0;
reg up_xfcp_in_tuser = 0;
reg up_xfcp_out_tready = 0;
reg m_axil_awready = 0;
reg m_axil_wready = 0;
reg [1:0] m_axil_bresp = 0;
reg m_axil_bvalid = 0;
reg m_axil_arready = 0;
reg [DATA_WIDTH-1:0] m_axil_rdata = 0;
reg [1:0] m_axil_rresp = 0;
reg m_axil_rvalid = 0;
// Outputs
wire up_xfcp_in_tready;
wire [7:0] up_xfcp_out_tdata;
wire up_xfcp_out_tvalid;
wire up_xfcp_out_tlast;
wire up_xfcp_out_tuser;
wire [ADDR_WIDTH-1:0] m_axil_awaddr;
wire [2:0] m_axil_awprot;
wire m_axil_awvalid;
wire [DATA_WIDTH-1:0] m_axil_wdata;
wire [STRB_WIDTH-1:0] m_axil_wstrb;
wire m_axil_wvalid;
wire m_axil_bready;
wire [ADDR_WIDTH-1:0] m_axil_araddr;
wire [2:0] m_axil_arprot;
wire m_axil_arvalid;
wire m_axil_rready;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, up_xfcp_in_tdata, up_xfcp_in_tvalid, up_xfcp_in_tlast,
up_xfcp_in_tuser, up_xfcp_out_tready, m_axil_awready, m_axil_wready, m_axil_bresp,
m_axil_bvalid, m_axil_arready, m_axil_rdata, m_axil_rresp, m_axil_rvalid);
$to_myhdl(up_xfcp_in_tready, up_xfcp_out_tdata, up_xfcp_out_tvalid, up_xfcp_out_tlast,
up_xfcp_out_tuser, m_axil_awaddr, m_axil_awprot, m_axil_awvalid, m_axil_wdata,
m_axil_wstrb, m_axil_wvalid, m_axil_bready, m_axil_araddr, m_axil_arprot,
m_axil_arvalid, m_axil_rready);
// dump file
$dumpfile("test_xfcp_mod_axil_32.lxt");
$dumpvars(0, test_xfcp_mod_axil_32);
end
xfcp_mod_axil #(
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.COUNT_SIZE(COUNT_SIZE),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready),
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready)
);
endmodule
| 6.880446 |
module test_xfcp_mod_i2c_master;
// Parameters
parameter XFCP_ID_TYPE = 16'h2C00;
parameter XFCP_ID_STR = "I2C Master";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
parameter DEFAULT_PRESCALE = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in_tdata = 0;
reg up_xfcp_in_tvalid = 0;
reg up_xfcp_in_tlast = 0;
reg up_xfcp_in_tuser = 0;
reg up_xfcp_out_tready = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
// Outputs
wire up_xfcp_in_tready;
wire [7:0] up_xfcp_out_tdata;
wire up_xfcp_out_tvalid;
wire up_xfcp_out_tlast;
wire up_xfcp_out_tuser;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, up_xfcp_in_tdata, up_xfcp_in_tvalid, up_xfcp_in_tlast,
up_xfcp_in_tuser, up_xfcp_out_tready, i2c_scl_i, i2c_sda_i);
$to_myhdl(up_xfcp_in_tready, up_xfcp_out_tdata, up_xfcp_out_tvalid, up_xfcp_out_tlast,
up_xfcp_out_tuser, i2c_scl_o, i2c_scl_t, i2c_sda_o, i2c_sda_t);
// dump file
$dumpfile("test_xfcp_mod_i2c_master.lxt");
$dumpvars(0, test_xfcp_mod_i2c_master);
end
xfcp_mod_i2c_master #(
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.DEFAULT_PRESCALE(DEFAULT_PRESCALE)
) UUT (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
| 6.880446 |
module test_xfcp_mod_wb_32;
// Parameters
parameter XFCP_ID_TYPE = 16'h0001;
parameter XFCP_ID_STR = "WB Master";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
parameter COUNT_SIZE = 16;
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 32;
parameter WB_SELECT_WIDTH = (WB_DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in_tdata = 0;
reg up_xfcp_in_tvalid = 0;
reg up_xfcp_in_tlast = 0;
reg up_xfcp_in_tuser = 0;
reg up_xfcp_out_tready = 0;
reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
// Outputs
wire up_xfcp_in_tready;
wire [7:0] up_xfcp_out_tdata;
wire up_xfcp_out_tvalid;
wire up_xfcp_out_tlast;
wire up_xfcp_out_tuser;
wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
wire [WB_DATA_WIDTH-1:0] wb_dat_o;
wire wb_we_o;
wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
wire wb_stb_o;
wire wb_cyc_o;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, up_xfcp_in_tdata, up_xfcp_in_tvalid, up_xfcp_in_tlast,
up_xfcp_in_tuser, up_xfcp_out_tready, wb_dat_i, wb_ack_i, wb_err_i);
$to_myhdl(up_xfcp_in_tready, up_xfcp_out_tdata, up_xfcp_out_tvalid, up_xfcp_out_tlast,
up_xfcp_out_tuser, wb_adr_o, wb_dat_o, wb_we_o, wb_sel_o, wb_stb_o, wb_cyc_o);
// dump file
$dumpfile("test_xfcp_mod_wb_32.lxt");
$dumpvars(0, test_xfcp_mod_wb_32);
end
xfcp_mod_wb #(
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.COUNT_SIZE(COUNT_SIZE),
.WB_DATA_WIDTH(WB_DATA_WIDTH),
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.WB_SELECT_WIDTH(WB_SELECT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o)
);
endmodule
| 6.880446 |
module test_xfcp_switch_4;
// Parameters
parameter PORTS = 4;
parameter XFCP_ID_TYPE = 16'h0100;
parameter XFCP_ID_STR = "XFCP Switch";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in_tdata = 0;
reg up_xfcp_in_tvalid = 0;
reg up_xfcp_in_tlast = 0;
reg up_xfcp_in_tuser = 0;
reg up_xfcp_out_tready = 0;
reg [PORTS*8-1:0] down_xfcp_in_tdata = 0;
reg [PORTS-1:0] down_xfcp_in_tvalid = 0;
reg [PORTS-1:0] down_xfcp_in_tlast = 0;
reg [PORTS-1:0] down_xfcp_in_tuser = 0;
reg [PORTS-1:0] down_xfcp_out_tready = 0;
// Outputs
wire up_xfcp_in_tready;
wire [7:0] up_xfcp_out_tdata;
wire up_xfcp_out_tvalid;
wire up_xfcp_out_tlast;
wire up_xfcp_out_tuser;
wire [PORTS-1:0] down_xfcp_in_tready;
wire [PORTS*8-1:0] down_xfcp_out_tdata;
wire [PORTS-1:0] down_xfcp_out_tvalid;
wire [PORTS-1:0] down_xfcp_out_tlast;
wire [PORTS-1:0] down_xfcp_out_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, up_xfcp_in_tdata, up_xfcp_in_tvalid, up_xfcp_in_tlast,
up_xfcp_in_tuser, up_xfcp_out_tready, down_xfcp_in_tdata, down_xfcp_in_tvalid,
down_xfcp_in_tlast, down_xfcp_in_tuser, down_xfcp_out_tready);
$to_myhdl(up_xfcp_in_tready, up_xfcp_out_tdata, up_xfcp_out_tvalid, up_xfcp_out_tlast,
up_xfcp_out_tuser, down_xfcp_in_tready, down_xfcp_out_tdata, down_xfcp_out_tvalid,
down_xfcp_out_tlast, down_xfcp_out_tuser);
// dump file
$dumpfile("test_xfcp_switch_4.lxt");
$dumpvars(0, test_xfcp_switch_4);
end
xfcp_switch #(
.PORTS(PORTS),
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR)
) UUT (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.down_xfcp_in_tdata(down_xfcp_in_tdata),
.down_xfcp_in_tvalid(down_xfcp_in_tvalid),
.down_xfcp_in_tready(down_xfcp_in_tready),
.down_xfcp_in_tlast(down_xfcp_in_tlast),
.down_xfcp_in_tuser(down_xfcp_in_tuser),
.down_xfcp_out_tdata(down_xfcp_out_tdata),
.down_xfcp_out_tvalid(down_xfcp_out_tvalid),
.down_xfcp_out_tready(down_xfcp_out_tready),
.down_xfcp_out_tlast(down_xfcp_out_tlast)
);
endmodule
| 6.623789 |
module test_xgmii #(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH / 8)
) (
input wire clk,
input wire rst,
inout wire [DATA_WIDTH-1:0] xgmii_d,
inout wire [CTRL_WIDTH-1:0] xgmii_c,
inout wire xgmii_clk_en
);
endmodule
| 6.504648 |
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