code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input ASYNCRESET
);
wire [3:0] reg_PR4_inst0_out;
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_PR4_inst0 (
.clk (CLK),
.arst(ASYNCRESET),
.in (I),
.out (reg_PR4_inst0_out)
);
assign O = reg_PR4_inst0_out;
endmodule
| 7.117303 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign coreir_commonlib_mux4x4_inst0_in_data[2] = I2;
assign coreir_commonlib_mux4x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux4x4_inst0_in_data[0] = I0;
commonlib_muxn__N4__width4 coreir_commonlib_mux4x4_inst0 (
.in_data(coreir_commonlib_mux4x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux4x4_inst0_out)
);
assign O = coreir_commonlib_mux4x4_inst0_out;
endmodule
| 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 (
.in_data(coreir_commonlib_mux2x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x4_inst0_out)
);
assign O = coreir_commonlib_mux2x4_inst0_out;
endmodule
| 8.559964 |
module test_regfile_enable_magma (
input [1:0] write_addr,
input [3:0] write_data,
input write_enable,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data),
.write_0_en(write_enable)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data,
input write_0_en
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
if (write_0_en) begin
data[write_0_addr] <= write_0_data;
end
end
assign read_0_data = write_0_addr == read_0_addr & write_0_en ? write_0_data : data[read_0_addr];
endmodule
| 7.958996 |
module test_regfile_enable_verilog (
input [1:0] write_addr,
input [3:0] write_data,
input write_enable,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data),
.write_0_en(write_enable)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
| 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
.in1(muxN_1_out),
.sel(in_sel[1]),
.out(_join_out)
);
wire [3:0] muxN_0_in_data[1:0];
assign muxN_0_in_data[1] = in_data[1];
assign muxN_0_in_data[0] = in_data[0];
commonlib_muxn__N2__width4 muxN_0 (
.in_data(muxN_0_in_data),
.in_sel(sel_slice0_out),
.out(muxN_0_out)
);
wire [3:0] muxN_1_in_data[1:0];
assign muxN_1_in_data[1] = in_data[3];
assign muxN_1_in_data[0] = in_data[2];
commonlib_muxn__N2__width4 muxN_1 (
.in_data(muxN_1_in_data),
.in_sel(sel_slice1_out),
.out(muxN_1_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice0 (
.in (in_sel),
.out(sel_slice0_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice1 (
.in (in_sel),
.out(sel_slice1_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input ASYNCRESET
);
wire [3:0] reg_PR4_inst0_out;
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_PR4_inst0 (
.clk (CLK),
.arst(ASYNCRESET),
.in (I),
.out (reg_PR4_inst0_out)
);
assign O = reg_PR4_inst0_out;
endmodule
| 7.117303 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign coreir_commonlib_mux4x4_inst0_in_data[2] = I2;
assign coreir_commonlib_mux4x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux4x4_inst0_in_data[0] = I0;
commonlib_muxn__N4__width4 coreir_commonlib_mux4x4_inst0 (
.in_data(coreir_commonlib_mux4x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux4x4_inst0_out)
);
assign O = coreir_commonlib_mux4x4_inst0_out;
endmodule
| 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 (
.in_data(coreir_commonlib_mux2x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x4_inst0_out)
);
assign O = coreir_commonlib_mux2x4_inst0_out;
endmodule
| 8.559964 |
module test_regfile_two_ports_magma (
input [1:0] write_addr0,
input [3:0] write_data0,
input [1:0] write_addr1,
input [3:0] write_data1,
input [1:0] read_addr0,
output [3:0] read_data0,
input [1:0] read_addr1,
output [3:0] read_data1,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
wire [3:0] my_regfile_read_1_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.read_0_addr(read_addr0),
.read_0_data(my_regfile_read_0_data),
.read_1_addr(read_addr1),
.read_1_data(my_regfile_read_1_data),
.write_0_addr(write_addr0),
.write_0_data(write_data0),
.write_1_addr(write_addr1),
.write_1_data(write_data1)
);
assign read_data0 = my_regfile_read_0_data;
assign read_data1 = my_regfile_read_1_data;
endmodule
| 6.909877 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] read_1_addr,
output [3:0] read_1_data,
input [1:0] write_0_addr,
input [3:0] write_0_data,
input [1:0] write_1_addr,
input [3:0] write_1_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
data[write_1_addr] <= write_1_data;
end
assign read_0_data = write_1_addr == read_0_addr ? write_1_data : write_0_addr == read_0_addr ? write_0_data : data[read_0_addr];
assign read_1_data = write_1_addr == read_1_addr ? write_1_data : write_0_addr == read_1_addr ? write_0_data : data[read_1_addr];
endmodule
| 7.958996 |
module test_regfile_two_ports_verilog (
input [1:0] write_addr0,
input [3:0] write_data0,
input [1:0] write_addr1,
input [3:0] write_data1,
input [1:0] read_addr0,
output [3:0] read_data0,
input [1:0] read_addr1,
output [3:0] read_data1,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
wire [3:0] my_regfile_read_1_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.read_0_addr(read_addr0),
.read_0_data(my_regfile_read_0_data),
.read_1_addr(read_addr1),
.read_1_data(my_regfile_read_1_data),
.write_0_addr(write_addr0),
.write_0_data(write_data0),
.write_1_addr(write_addr1),
.write_1_data(write_data1)
);
assign read_data0 = my_regfile_read_0_data;
assign read_data1 = my_regfile_read_1_data;
endmodule
| 6.909877 |
module test_registers;
// Inputs
reg clk;
reg RegWrite;
reg [4:0] ReadReg1;
reg [4:0] ReadReg2;
reg [4:0] WriteReg;
reg [31:0] WriteRegData;
// Outputs
wire [31:0] ReadData1;
wire [31:0] ReadData2;
// Instantiate the Unit Under Test (UUT)
Registers_32 uut (
.clk(clk),
.RegWrite(RegWrite),
.ReadReg1(ReadReg1),
.ReadReg2(ReadReg2),
.WriteReg(WriteReg),
.WriteRegData(WriteRegData),
.ReadData1(ReadData1),
.ReadData2(ReadData2)
);
initial begin
// Initialize Inputs
clk = 0;
RegWrite = 1;
ReadReg1 = 7;
ReadReg2 = 8;
WriteReg = 3;
WriteRegData = 10;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.267008 |
module test_register_32 ();
//由于待测模块中有一个inout类型的端口, 测试比较复杂:
//用wire型的data_bus连接待测模块的这个端口
//用io的值选择data_bus在待测模块外面如何连接:
//io=1, 此时应该向寄存器写入数据, 将data_bus_in连接到data_bus, 并在always中不断改变data_bus_in的值(所以data_bus_in是reg类型)
//io=0, 此时应该从寄存器内读取数据, 则将data_bus连接到data_bus_out, 用以在波形中更好的展示输入输出结果
wire [31:0] data_bus_out;
wire [31:0] data_bus;
reg [31:0] data_bus_in = 0;
reg en = 1, clear = 0, io = 0, clk = 0;
register_32 r32 (
data_bus,
en,
clear,
io,
clk
);
assign data_bus = (io) ? data_bus_in : 32'bz;
assign data_bus_out = !(io) ? data_bus : 32'bz;
always begin
#4 clk = 1;
#1 clk = 0;
#4 data_bus_in = data_bus_in + 1;
#1{en, clear, io} = {en, clear, io} + 1;
// io = ~io;
end
endmodule
| 7.267008 |
module test_register_32_bits;
wire [31:0] Out;
reg [31:0] In;
reg EN, CLR, CLK; //Las entradas del módulo deben ser tipo reg
register_32_bits testReg (
Out,
In,
EN,
CLR,
CLK
);
initial begin
#1 In = 32'heeeeffff;
EN <= 0;
CLR <= 1;
end
initial begin
$monitor("In= %h\nOut=%h\nEN=%h\nCLR=%h\nCLK=%h\n", In, Out, EN, CLR, CLK);
end
initial begin
CLK <= 0;
repeat (5) begin
#1 CLK <= ~CLK;
end
end
endmodule
| 7.267008 |
module test_register_mips32 ();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 5;
reg [(ADDR_WIDTH -1):0] Rs_addr, Rt_addr, Rd_addr;
reg [(DATA_WIDTH -1):0] Rd_in;
reg [3:0] Rd_Byte_w_en;
reg clk;
wire [(DATA_WIDTH -1):0] Rs_out, Rt_out;
register_mips32 t1 (
.Rs_addr(Rs_addr),
.Rt_addr(Rt_addr),
.Rd_addr(Rd_addr),
.Rd_in(Rd_in),
.clk(clk),
.Rd_Byte_w_en(Rd_Byte_w_en),
.Rs_out(Rs_out),
.Rt_out(Rt_out)
);
always #1 clk = ~clk;
initial begin
clk = 1'b1;
Rs_addr = 1;
Rt_addr = 2;
Rd_in = 32'b1001000;
#3 Rd_addr = 1;
#3 Rd_Byte_w_en = 4'b0000;
#3 Rd_addr = 2;
#3 Rd_in = 32'b00001111111;
Rd_Byte_w_en = 4'b1110;
#3 $stop;
end
endmodule
| 7.267008 |
module prova_registro ();
parameter N = 3;
reg [N-1:0] ingresso;
reg clk;
reg beta;
wire [N-1:0] uscita;
registro #(N) R (
uscita,
clk,
beta,
ingresso
);
initial begin
clk = 0;
end
always begin
if (clk == 0) #5 clk = 1;
else #1 clk = 0;
end
initial begin
$dumpfile("prova_registro.vcd");
$dumpvars;
//beta = 1;
//ingresso = 118;
#5 beta = 0;
#5 ingresso = 119;
#5 beta = 1;
#5 ingresso = 120;
#5 beta = 0;
#5 beta = 1;
#5 ingresso = 121;
#10 $finish;
end
endmodule
| 6.76205 |
module test_registru_multifunctional;
reg [3:0] intrare;
reg clk, rst;
reg [4:0] intrarile_pe_1_bite;
wire [3:0] out;
registru_multifunctional reg1 (
intrare,
clk,
rst,
intrarile_pe_1_bite[4],
intrarile_pe_1_bite[3],
intrarile_pe_1_bite[2],
intrarile_pe_1_bite[1],
intrarile_pe_1_bite[0],
out
);
/*
initial begin
clk = 1'b0;
rst = 1'b0;
repeat(4) #10 clk = ~clk;
forever #10 clk = ~clk;
end */
always #25 clk = ~clk;
initial begin
clk = 0;
rst = 0;
intrare = 4'b1010;
intrarile_pe_1_bite = 5'b01000;
#50 intrare = 4'b1010;
intrarile_pe_1_bite = 5'b00100;
#50 intrare = 4'b1010;
intrarile_pe_1_bite = 5'b00010;
#50 rst = 1'b0;
#50 intrare = 4'b1010;
intrarile_pe_1_bite = 5'b00001;
#50 intrare = 4'b1101;
intrarile_pe_1_bite = 5'b11000;
rst = 0;
#50 intrare = 4'b1111;
intrarile_pe_1_bite = 5'b01000;
#50 intrare = 4'b1101;
intrarile_pe_1_bite = 5'b11010;
end
endmodule
| 6.964609 |
module test_replicator;
parameter WAY = 2;
parameter WIRE = 8;
reg [ WIRE-1:0] in;
wire [WAY*WIRE-1:0] out;
replicator #(
.WAY (WAY),
.WIRE(WIRE)
) replicator (
out,
in
);
initial begin
$dumpfile("signal_replicator.vcd");
$dumpvars;
$display("\t\ttime\tin,\tout");
$monitor("%d\t%b\t%b\n", $time, in, out);
in = 187;
#10;
in = 203;
#10;
end
endmodule
| 6.585774 |
module Test_Resp_MUX;
// Inputs
reg CLK;
reg RST;
reg [1:0] HRESP_1;
reg [1:0] HRESP_2;
reg [1:0] HRESP_3;
reg [1:0] SEL;
// Outputs
wire [1:0] HRESP;
// Instantiate the Unit Under Test (UUT)
Resp_MUX uut (
.CLK(CLK),
.RST(RST),
.HRESP(HRESP),
.HRESP_1(HRESP_1),
.HRESP_2(HRESP_2),
.HRESP_3(HRESP_3),
.SEL(SEL)
);
always #12 CLK = !CLK;
initial begin
#500 RST = 1; // Random reset stimuli
#50 RST = 0;
end
initial begin
// Initialize Inputs
CLK = 0;
RST = 0;
HRESP_1 = 0;
HRESP_2 = 0;
HRESP_3 = 0;
SEL = 0;
// Wait 100 ns for global reset to finish
#15;
// Add stimulus here
#200 HRESP_1[1:0] = $random;
HRESP_2[1:0] = $random;
HRESP_3[1:0] = $random;
SEL = 2'b00;
RST = 0;
#200 HRESP_1[1:0] = $random;
HRESP_2[1:0] = $random;
HRESP_3[1:0] = $random;
SEL = 2'b01;
RST = 0;
#200 HRESP_1[1:0] = $random;
HRESP_2[1:0] = $random;
HRESP_3[1:0] = $random;
SEL = 2'b10;
RST = 0;
#200 HRESP_1[1:0] = $random;
HRESP_2[1:0] = $random;
HRESP_3[1:0] = $random;
SEL = 2'b11;
RST = 0;
#200 HRESP_1[1:0] = $random;
HRESP_2[1:0] = $random;
HRESP_3[1:0] = $random;
SEL = 2'b00;
RST = 0;
end
endmodule
| 7.497159 |
module test_ripple_counter ();
parameter N = 4;
//inputs for DUT
reg clk, rst;
//outputs for DUt
wire [N-1:0] up;
wire [N-1:0] down;
ripple_counter DUT (
.clk(clk),
.rst(rst),
.upcount(up),
.downcount(down)
);
initial begin
$display($time, " << Simulation Results >>");
$monitor($time, "clk = %b, rst = %b, upcount = %b, downcount =%b", clk, rst, up, down);
end
always #10 clk = ~clk;
initial begin
clk = 1;
rst = 1;
#5 rst = 1;
#20 rst = 0;
#315 $finish;
end
endmodule
| 7.028022 |
module tb_ripple;
// reg clk;
// reg rst;
// wire [3:0] out;
// ripple_counter r0 ( .clk (clk),
// .rst (rst),
// .out (out));
// always #5 clk = ~clk;
// initial begin
// rst <= 0;
// clk <= 0;
// repeat (4) @ (posedge clk);
// rst <= 1;
// repeat (25) @ (posedge clk);
// $finish;
// end
//endmodule
| 7.091181 |
module: road
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_road;
// Inputs
reg sensor;
reg clk;
// Outputs
wire [7:0] timer;
wire en;
wire green_main;
wire yellow_main;
wire red_main;
wire green_secondary;
wire yellow_secondary;
wire red_secondary;
// Instantiate the Unit Under Test (UUT)
road uut (
.timer(timer),
.en(en),
.green_main(green_main),
.yellow_main(yellow_main),
.red_main(red_main),
.green_secondary(green_secondary),
.yellow_secondary(yellow_secondary),
.red_secondary(red_secondary),
.sensor(sensor),
.clk(clk)
);
initial begin
// Initialize Inputs
sensor = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#40;
sensor = 1;
// Add stimulus here
end
always #20.83 clk<=~clk;
endmodule
| 7.046116 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module corebit_const #(
parameter value = 1
) (
output out
);
assign out = value;
endmodule
| 7.833235 |
module test_romb_coreir (
output [15:0] RDATAOUT,
input CLK
);
wire [15:0] SB_RAM40_4K_inst0_RDATA;
wire bit_const_0_None_out;
wire bit_const_1_None_out;
wire [10:0] const_0_11_out;
wire [15:0] const_0_16_out;
wire [10:0] const_1_11_out;
SB_RAM40_4K #(
.INIT_0(256'h0000000000000000000000000000000000000000000000000000000000ff0001),
.INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.READ_MODE(0),
.WRITE_MODE(0)
) SB_RAM40_4K_inst0 (
.RDATA(SB_RAM40_4K_inst0_RDATA),
.RADDR(const_1_11_out),
.RCLK(CLK),
.RCLKE(bit_const_1_None_out),
.RE(bit_const_1_None_out),
.WCLK(CLK),
.WCLKE(bit_const_0_None_out),
.WE(bit_const_0_None_out),
.WADDR(const_0_11_out),
.MASK(const_0_16_out),
.WDATA(const_0_16_out)
);
corebit_const #(.value(1'b0)) bit_const_0_None (.out(bit_const_0_None_out));
corebit_const #(.value(1'b1)) bit_const_1_None (.out(bit_const_1_None_out));
coreir_const #(
.value(11'h000),
.width(11)
) const_0_11 (
.out(const_0_11_out)
);
coreir_const #(
.value(16'h0000),
.width(16)
) const_0_16 (
.out(const_0_16_out)
);
coreir_const #(
.value(11'h001),
.width(11)
) const_1_11 (
.out(const_1_11_out)
);
assign RDATAOUT = SB_RAM40_4K_inst0_RDATA;
endmodule
| 7.158187 |
module test_RSA;
reg clk;
reg reset_n;
reg [63:0] Message;
wire [63:0] decrypted_message;
wire [63:0] encrypted_message;
wire [63:0] n;
wire [63:0] encrypt_key;
initial begin
clk = 1'b0;
reset_n = 1'b0;
#40;
reset_n = 1'b1;
Message = 'd2321;
#4000000;
Message = 'd8;
#4000000;
Message = 'd542;
#4000000;
Message = 'd1580;
#4000000;
Message = 'd1453;
#4000000;
Message = 'd874;
#4000000000000;
end
always #20 clk = ~clk;
RSA_decryptor RSA_decryptor_inst (
.clk (clk),
.rst (reset_n),
.encrypted_message (encrypted_message),
.msg_received_sig (done_encrypt),
.n (n),
.decrypted_message (decrypted_message),
.donegcd (donegcd),
.encrypt_key (encrypt_key)
);
RSA_encryptor RSA_encryptor_inst (
.clk(clk),
.rst(reset_n),
.Message(Message), //from TB
.encrypted_msg(encrypted_message),
.n(n),
.exponent(encrypt_key),
.public_key_rcvd(donegcd),
.done_encrypt(done_encrypt)
);
endmodule
| 6.648616 |
module: RX
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_rx;
// Inputs
reg clock;
reg RX_en;
reg RX;
reg reset;
// Outputs
wire data_ready;
wire [7:0] data;
wire Pb_error;
wire Sb_error;
// Instantiate the Unit Under Test (UUT)
RX uut (
.clock(clock),
.RX_en(RX_en),
.RX(RX),
.reset(reset),
.data_ready(data_ready),
.data(data),
.Pb_error(Pb_error),
.Sb_error(Sb_error)
);
initial begin
// Initialize Inputs
clock = 0;
RX_en = 0;
RX = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#10;
reset = 1;
#5
RX_en = 1;
#5
RX_en = 0;
RX=1;
#5
RX=0;
#151
RX=1;
#100
RX=1;
#100
RX=0;
#100
RX=1;
#100
RX=1;
#100
RX=0;
#300
RX=1;
#100
RX=0;
#200
$finish;
// Add stimulus here
end
always #2.5 clock = ~ clock;
endmodule
| 7.774549 |
module Test_RX_ATRP_AR_TXA (
input clk,
output wire [11:0] TXA,
input [5:0] M,
output wire [11:0] D_RXA,
output wire [11:0] Xns,
output wire RXP,
output wire RXN,
output wire [10:0] AMP,
output wire res,
output wire [7:0] N_RXPN,
output wire en_TX,
output wire err
);
wire ce_rx;
//-- ARINC-429
AR_TXA DD1 (
.clk(clk),
.TXA(TXA),
.M(M),
.en_tx(en_TX)
);
//-- ------------
RX_TIMER DD2 (
.clk(clk),
.ce(ce_rx),
.RXP(RXP),
.res(res),
.RXN(RXN),
.N_RXPN(N_RXPN),
.err(err)
);
//-- ARINC-429
RX_MTRP DD3 (
.Inp(TXA),
.MEM_dat(D_RXA),
.clk(clk),
.RXP(RXP),
.ce(ce_rx),
.RXN(RXN),
.res(res),
.Xns(Xns),
.AMP(AMP)
);
endmodule
| 6.861472 |
module test_rx_checksum_256;
// Parameters
parameter DATA_WIDTH = 256;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
// Outputs
wire [15:0] m_axis_csum;
wire m_axis_csum_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast);
$to_myhdl(m_axis_csum, m_axis_csum_valid);
// dump file
$dumpfile("test_rx_checksum_256.lxt");
$dumpvars(0, test_rx_checksum_256);
end
rx_checksum #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tlast(s_axis_tlast),
.m_axis_csum(m_axis_csum),
.m_axis_csum_valid(m_axis_csum_valid)
);
endmodule
| 7.463546 |
module test_rx_checksum_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
// Outputs
wire [15:0] m_axis_csum;
wire m_axis_csum_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast);
$to_myhdl(m_axis_csum, m_axis_csum_valid);
// dump file
$dumpfile("test_rx_checksum_64.lxt");
$dumpvars(0, test_rx_checksum_64);
end
rx_checksum #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tlast(s_axis_tlast),
.m_axis_csum(m_axis_csum),
.m_axis_csum_valid(m_axis_csum_valid)
);
endmodule
| 7.463546 |
module test_rx_hash_256;
// Parameters
parameter DATA_WIDTH = 256;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [40*8-1:0] hash_key = 0;
// Outputs
wire [31:0] m_axis_hash;
wire [3:0] m_axis_hash_type;
wire m_axis_hash_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
hash_key);
$to_myhdl(m_axis_hash, m_axis_hash_type, m_axis_hash_valid);
// dump file
$dumpfile("test_rx_hash_256.lxt");
$dumpvars(0, test_rx_hash_256);
end
rx_hash #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tlast(s_axis_tlast),
.hash_key(hash_key),
.m_axis_hash(m_axis_hash),
.m_axis_hash_type(m_axis_hash_type),
.m_axis_hash_valid(m_axis_hash_valid)
);
endmodule
| 7.574975 |
module test_rx_hash_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [40*8-1:0] hash_key = 0;
// Outputs
wire [31:0] m_axis_hash;
wire [3:0] m_axis_hash_type;
wire m_axis_hash_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
hash_key);
$to_myhdl(m_axis_hash, m_axis_hash_type, m_axis_hash_valid);
// dump file
$dumpfile("test_rx_hash_64.lxt");
$dumpvars(0, test_rx_hash_64);
end
rx_hash #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tlast(s_axis_tlast),
.hash_key(hash_key),
.m_axis_hash(m_axis_hash),
.m_axis_hash_type(m_axis_hash_type),
.m_axis_hash_valid(m_axis_hash_valid)
);
endmodule
| 7.574975 |
module Test_RX_MTRP (
input clk,
output wire [11:0] MTRP,
input st,
output wire [11:0] MEM_dat,
input [5:0] M,
output wire [11:0] Xmax,
input S,
output wire [11:0] Xns,
input res,
output wire [11:0] Xmin,
output wire [11:0] REF_P,
output wire [11:0] REF_N,
output wire RXP,
output wire RXN,
output wire [10:0] AMP
);
wire ce;
Gen_MTRP DD2 (
.clk(clk),
.MTRP(MTRP),
.st(st),
.ce(ce),
.M(M),
.S(S)
);
RX_MTRP DD3 (
.Inp(MTRP),
.MEM_dat(MEM_dat),
.clk(clk),
.RXP(RXP),
.ce(ce),
.RXN(RXN),
.res(res),
.Xmax(Xmax),
.Xns(Xns),
.Xmin(Xmin),
.REF_P(REF_P),
.REF_N(REF_N),
.AMP(AMP)
);
endmodule
| 7.315729 |
module test_tx_rx(output reg finished, output reg [15:0] errors);
/*
* primary goals:
* test transmit and receive of extended-id CAN frames on a bus.
* secondary goals:
* test basic data bus connectivity for 8051 and wishbone bus.
*/
`include "testbench/fixture.inc"
localparam baudrate_prescaler = 6'h0;
localparam sync_jump_width = 2'h1;
localparam tseg1 = 4'hf;
localparam tseg2 = 3'h2;
localparam bitclocks = clocks_per_bit(baudrate_prescaler, tseg2, tseg1);
localparam triple_sampling = 0;
localparam extended_mode = 1;
localparam remote_transmission_request = 0;
integer i = 0;
integer dut_sender = 0;
integer dut_receiver = 0;
integer value = 0;
integer expect = 0;
reg [28:0] tx_id;
reg [3:0] tx_data_length;
reg [63:0] tx_data;
reg [1:0] rx_errors;
initial begin
finished = 0;
errors = 0;
wait(start_test);
for(i=1; i<=5; i=i+1) begin
setup_device(i,
sync_jump_width, baudrate_prescaler,
triple_sampling, tseg2, tseg1, extended_mode);
end
// BRP clocks are needed before we can do work with the bus.
repeat (8 * bitclocks) @(posedge clk);
// send from all DUTs and check that all other DUTs received.
for(dut_sender=1; dut_sender<=5; dut_sender=dut_sender+1) begin
// make sure bus is idle
if(1!=canbus_tap_rx) begin
errors += 1;
$error("CAN bus should be idle but is not.");
end
// transmit frame from one device
tx_id = 28'h0123456+dut_sender;
tx_data_length = 8;
tx_data = 64'hdead_beef_badc_0ffe+dut_sender;
send_frame(dut_sender, remote_transmission_request, extended_mode, tx_data_length, tx_id, tx_data);
verify_transmit_finished(dut_sender);
// check reception on other devices
repeat (20) @(posedge clk);
for(dut_receiver=1; dut_receiver<=5; dut_receiver=dut_receiver+1) begin
if(dut_receiver != dut_sender) begin
get_interrupt_register(dut_receiver, value);
expect = 8'h01;
if(value != expect) begin
errors += 1;
$error("DUT%d interrupt should be 'RX complete' (0x%02X) but is 0x%02X",
dut_receiver, expect, value);
end
value = get_rx_fifo_framecount(dut_receiver);
expect = 1;
if(value == expect) begin
receive_and_verify_frame(dut_receiver, remote_transmission_request, extended_mode, tx_id, tx_data_length, tx_data, rx_errors);
errors = errors + rx_errors;
end else begin
errors += 1;
$error("DUT%d has %d frames in fifo, but there should be %d.",
dut_receiver, value, expect);
end
end
end
// check that interrupts have not reappeared.
for(i = 1; i <= 5; i=i+1) begin
get_interrupt_register(i, value);
expect = 8'h0;
if(value != expect) begin
errors += 1;
$error("DUT%d interrupt should be 'NONE' (0x%02X) but is 0x%02X",
i, expect, value);
end
end
repeat (20) @(posedge clk);
end
finished = 1;
end
endmodule
| 7.629638 |
module test_scan_controller_tb (
input wire clk,
input wire reset,
input wire [1:0] driver_sel,
input wire [8:0] active_select,
input wire [7:0] inputs,
input wire set_clk_div,
output wire [7:0] outputs,
output wire ready,
output wire slow_clk
);
// signals for user_project_wrapper
wire [`MPRJ_IO_PADS-1:0] io_in;
wire [`MPRJ_IO_PADS-1:0] io_out;
wire [`MPRJ_IO_PADS-1:0] io_oeb;
// map inputs to user_project_wrapper signals
assign io_in[20:12] = active_select;
assign io_in[28:21] = inputs;
assign io_in[11] = set_clk_div;
assign io_in[9:8] = driver_sel;
assign outputs = io_out[36:29];
assign ready = io_out[37];
assign slow_clk = io_out[10];
// 7 seg signals
wire [6:0] seven_seg = outputs[6:0];
`ifdef SIM_ICARUS
initial begin
string f_name;
$timeformat(-9, 2, " ns", 20);
if ($value$plusargs("WAVE_FILE=%s", f_name)) begin
$display("%0t: Capturing wave file %s", $time, f_name);
$dumpfile(f_name);
$dumpvars(0, test_scan_controller_tb);
end else begin
$display("%0t: No filename provided - disabling wave capture", $time);
end
end
`endif
user_project_wrapper user_project_wrapper (
`ifdef GL_TEST
.vccd1 (1'b1),
.vssd1 (1'b0),
`endif
.wb_clk_i(clk),
.wb_rst_i(reset),
.io_in (io_in),
.io_out (io_out),
.io_oeb (io_oeb)
);
endmodule
| 7.530278 |
module: scan_new
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_scan_new;
// Inputs
reg start;
reg clk;
reg rst;
// Outputs
wire [13:0] read_select;
wire scan_start;
// Instantiate the Unit Under Test (UUT)
scan_new uut (
.read_select(read_select),
.scan_start(scan_start),
.start(start),
.clk(clk),
.rst(rst)
);
always #1 clk = ~clk;
initial begin
// Initialize Inputs
start = 0;
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100
start = 1;
rst = 0;
#100000000 $finish;
// Add stimulus here
end
endmodule
| 6.832349 |
module test_sdram_read (
input iCLK,
input iRST,
input iTEST_WRITE_DONE,
input iWAIT_REQUEST,
output oRD_EN,
output [24:0] oRD_ADDR,
input [15:0] iRD_DATA,
input iRD_DATAVALID,
output [ 7:0] oDATA,
input [9:0] iSW,
input iUPDATE_FRAME,
input iUPDATE_Y
);
/*
Reading the data in sdram
*/
// states
parameter ST_IDLE = 4'd0;
parameter ST_READ_REQ = 4'd1;
parameter ST_READ_STALLED = 4'd2;
parameter ST_READ_DONE = 4'd15;
reg [3:0] states, states_next;
reg [19:0] counter_idle, counter_idle_next;
reg [15:0] data_captured;
reg [ 9:0] y_coord;
reg [ 5:0] frame_id;
assign oRD_EN = (states == ST_READ_REQ) || (states == ST_READ_STALLED);
assign oDATA = (iSW[0] == 0) ? data_captured[15:8] : data_captured[7:0];
// =============================
// read addr managing
// =============================
assign oRD_ADDR[24:19] = frame_id;
assign oRD_ADDR[18:9] = y_coord;
assign oRD_ADDR[8:0] = iSW[9:1];
always @(posedge iRST or posedge iCLK) begin
if (iRST) begin
frame_id <= 0;
y_coord <= 0;
end else begin
if (iUPDATE_FRAME) frame_id <= iSW[5:0];
if (iUPDATE_Y) y_coord <= iSW[9:0];
end
end
// end of read addr managing
// states_next
always @(*)
case (states)
ST_IDLE: // asserted write_done allows the reading when counter_idle hits 0
states_next = (counter_idle == 0 && iTEST_WRITE_DONE) ? ST_READ_REQ : ST_IDLE;
ST_READ_REQ: begin // send read request
if (iWAIT_REQUEST) states_next = ST_READ_STALLED;
else begin
states_next = ST_READ_DONE;
end
end
ST_READ_STALLED: begin
if (iWAIT_REQUEST) states_next = ST_READ_STALLED;
else begin
states_next = ST_READ_DONE;
end
end
default: states_next = ST_IDLE;
endcase
always @(*) begin
counter_idle_next = counter_idle + 1'b1;
end
// sequential part
always @(posedge iRST or posedge iCLK) begin
if (iRST) begin
states <= ST_IDLE;
counter_idle <= 1;
end else begin
states <= states_next;
counter_idle <= counter_idle_next;
end
end
// output of the result of reading operation
always @(posedge iRST or negedge iCLK) begin
if (iRST) begin
data_captured <= 16'd0;
end else begin
if (iRD_DATAVALID) begin
data_captured <= iRD_DATA;
end
end
end
endmodule
| 8.6682 |
module fake_SD_card_FAT32_reader (
input iCLK,
input iRST,
input iTRIGGER,
output [15:0] oDATA,
output oDATA_READY,
output oLAST_DATA
);
// Simulate a slow SD card module by slowing the clock
reg [2:0] clock_counter;
wire CLOCK;
always @(posedge iCLK) begin
clock_counter <= clock_counter + 1'b1;
end
assign CLOCK = clock_counter[2];
// states
parameter ST_IDLE = 4'd0;
parameter ST_PREPARE_DATA = 4'd1;
parameter ST_SEND_REQ = 4'd2;
parameter ST_PREP_LAST = 4'd3;
parameter ST_REQ_LAST = 4'd4;
parameter ST_DONE_AND_WAIT = 4'd5;
parameter STRIP_WIDTH = 12; // in unit of pixels
reg [3:0] states, states_next;
reg [24:0] counter, counter_next;
reg [15:0] data, data_next;
wire [ 5:0] frame_id;
wire [ 9:0] line_id;
wire [ 8:0] twobytes_id;
reg [15:0] rDATA;
reg rDATA_READY;
reg rLAST_DATA;
assign frame_id = counter[24:19];
assign line_id = counter[18:9];
assign twobytes_id = counter[8:0];
always @(posedge CLOCK) begin
// retarding the output signals
rDATA <= data;
rDATA_READY <= (states == ST_SEND_REQ) || (states == ST_REQ_LAST);
rLAST_DATA <= (states == ST_REQ_LAST);
end
assign oDATA = rDATA;
assign oDATA_READY = rDATA_READY;
assign oLAST_DATA = rLAST_DATA;
// states_next
always @(*)
case (states)
ST_IDLE: states_next = (iTRIGGER) ? ST_PREPARE_DATA : ST_IDLE;
ST_PREPARE_DATA: states_next = ST_SEND_REQ;
ST_SEND_REQ: states_next = (counter == 25'h1ff_fffe) ? ST_PREP_LAST : ST_PREPARE_DATA;
ST_PREP_LAST: states_next = ST_REQ_LAST;
ST_REQ_LAST: states_next = ST_DONE_AND_WAIT;
ST_DONE_AND_WAIT: states_next = (!iTRIGGER) ? ST_IDLE : ST_DONE_AND_WAIT;
default: states_next = ST_IDLE;
endcase
// counter_next
always @(*)
case (states)
ST_IDLE: counter_next = 25'd0;
ST_PREPARE_DATA: counter_next = counter;
ST_SEND_REQ: counter_next = counter + 1'b1;
ST_PREP_LAST: counter_next = counter;
ST_REQ_LAST: counter_next = counter;
default: counter_next = 25'd0;
endcase
// data_next
always @(*)
case (states)
ST_IDLE: data_next = 16'd0;
ST_PREPARE_DATA, ST_PREP_LAST: begin
if (line_id == 10'd0) data_next = 16'hffff;
else if ((twobytes_id >= frame_id * 8) && (twobytes_id < frame_id * 8 + STRIP_WIDTH / 2))
data_next = {2'b11, line_id[9:7], 3'b111, 2'b11, line_id[9:7], 3'b111};
else data_next = 16'd0;
end
default: data_next = data;
endcase
// sequential part
always @(posedge iRST or posedge CLOCK) begin
if (iRST) begin
states <= ST_IDLE;
counter <= 25'd0;
data <= 16'd0;
end else begin
states <= states_next;
counter <= counter_next;
data <= data_next;
end
end
endmodule
| 6.824462 |
module test_sequential_regdec_left;
reg [2:0] sequenceur;
reg [7:0] bus_in;
reg clk, reset;
wire [7:0] bus_out;
supply0 masse;
sequential_regdec_left tester (
sequenceur,
bus_in,
masse,
clk,
reset,
bus_out
);
initial begin
$dumpfile("build/memory/signal/signal_test_sequential_regdec.vcd");
$dumpvars;
$display("\t\ttime,\tsequenceur,\tbus_in,\t\tclk,\treset,\tbus_out");
$monitor("%d\t%d\t\t%d\t\t%b\t%d\t%d", $time, sequenceur, bus_in[7:0], clk, reset,
bus_out[7:0]);
sequenceur = 0;
bus_in = 127;
clk = 0;
reset = 1;
#100;
reset = 0;
clk = 1;
#100;
clk = 0;
sequenceur = 1;
#100;
clk = 1;
#100;
clk = 0;
sequenceur = 2;
#100;
clk = 1;
#100;
clk = 0;
sequenceur = 3;
#100;
clk = 1;
#100;
clk = 0;
end
endmodule
| 7.101484 |
module test_sequential_regdec_right;
reg [2:0] sequenceur;
reg [7:0] bus_in;
reg clk, reset;
wire [7:0] bus_out;
supply0 masse;
sequential_regdec_right tester (
sequenceur,
bus_in,
masse,
clk,
reset,
bus_out
);
initial begin
$dumpfile("build/memory/signal/signal_test_sequential_regdec.vcd");
$dumpvars;
$display("\t\ttime,\tsequenceur,\tbus_in,\t\tclk,\treset,\tbus_out");
$monitor("%d\t%d\t\t%d\t\t%b\t%d\t%d", $time, sequenceur, bus_in[7:0], clk, reset,
bus_out[7:0]);
sequenceur = 0;
bus_in = 127;
clk = 0;
reset = 1;
#100;
reset = 0;
clk = 1;
#100;
clk = 0;
sequenceur = 1;
#100;
clk = 1;
#100;
clk = 0;
sequenceur = 2;
#100;
clk = 1;
#100;
clk = 0;
sequenceur = 3;
#100;
clk = 1;
#100;
clk = 0;
end
endmodule
| 7.101484 |
module test_serializer;
reg reset = 0;
reg enable = 1;
reg [47:0] in = 48'b101011010111101011101011101010101010101001110101; // test input data
wire out; //serialized output
wire complete;
initial begin
$display("\n----------------------- Serializer test -------------------------\n");
$display("input: %b \n", in);
$dumpfile("tests/vcd/test_serializer.vcd");
$dumpvars(0, test_serializer);
#2 reset = 1;
#2 reset = 0;
#96 $display("finished");
reset = 1; //counter reset to zero, reading first item
#4 $finish;
end
reg clk = 1;
always #1 clk = !clk;
serializer ser (
.enable(enable),
.clk(clk),
.reset(reset),
.in(in),
.out(out),
.complete(complete)
);
initial $monitor("At time %t: out: %b complete: %b", $time, out, complete);
endmodule
| 6.696129 |
module _test_serial_JKlatchUP_rst;
reg [7:0] j, k;
reg clk, reset;
wire [7:0] s1, s2;
supply1 power;
integer i;
serial_JKlatchUP_rst #(
.SIZE(8)
) test_serial_JKlatchUP_rst (
j,
k,
clk,
reset,
s1,
s2
);
initial begin
reset = 1;
j = 0;
k = 0;
clk = 0;
i = 0;
$dumpfile("signal_JKlatchUP.vcd");
$dumpvars;
$display("\t\ttime, \tj, \t\tk, \t\tclk, reset, \ts1, \t\ts2");
$monitor("%d \t%b \t%b \t%b \t%b \t%b \t%b", $time, j, k, clk, reset, s1, s2);
end
always begin
if (reset && clk == 1) begin
reset = 0;
end
if (i >= 10 && !clk) begin
$finish;
end
clk <= ~clk;
j <= {$random} % 255;
k <= {$random} % 255;
#5;
end
always @(posedge clk) begin
i++;
end
endmodule
| 6.521444 |
module Test_ServoController;
parameter SIGNAL_BIT_WIDTH = 15;
parameter ADDRESS_BIT_WIDTH = 2;
parameter PWM_SIGNAL_COUNT = 4;
parameter FULL_CYCLE = 32'd20_000;
reg success_flag;
reg clk, rst, cs;
reg [31:0] data_reg;
wire [31:0] data;
reg test_write_enable;
reg [ADDRESS_BIT_WIDTH-1:0] addr;
wire [PWM_SIGNAL_COUNT-1:0] signal;
ServoController servo (
.clk(clk),
.rst(rst),
.cs(cs), // chip select
.addr(addr[1:0]),
.data(data[14:0]),
.signal(signal)
);
assign data = (test_write_enable) ? data_reg : 32'bZ;
integer i;
task RESET;
begin
success_flag = 1;
rst = 0;
clk = 0;
cs = 0;
test_write_enable = 0;
#5 rst = 1;
#5 rst = 0;
end
endtask
;
task CLOCK;
input [31:0] count;
integer k;
begin
for (k = 0; k < count; k = k + 1) begin
#5 clk = 1;
#5 clk = 0;
end
end
endtask
task CHECK_OUTPUT;
input [2:0] select;
input level;
begin
if (signal[select] != level) begin
success_flag = 0;
$display("!!ERROR!! @ %d signal[%d] = 0x%X !== 0x%X", $time, select, signal[select], level);
end
end
endtask
;
task LOAD_COMPARE_VALUE; // task definition starts here
input [31:0] select;
input [31:0] value;
begin
#1 cs = 1;
addr = select;
test_write_enable = 1;
data_reg = value;
CLOCK(1);
#1 test_write_enable = 0;
cs = 0;
#1 addr = 0;
end
endtask
initial begin
#10 #10 RESET;
LOAD_COMPARE_VALUE(2'b00, 32'd1000);
CLOCK(FULL_CYCLE);
CLOCK(500);
CHECK_OUTPUT(2'b00, 1);
CLOCK(505);
CHECK_OUTPUT(2'b00, 0);
CLOCK(500);
CHECK_OUTPUT(2'b00, 0);
CLOCK(FULL_CYCLE - 1505);
LOAD_COMPARE_VALUE(2'b00, 32'd1500);
LOAD_COMPARE_VALUE(2'b01, 32'd1500);
CLOCK(FULL_CYCLE);
CLOCK(500);
CHECK_OUTPUT(2'b00, 1);
CHECK_OUTPUT(2'b01, 1);
CLOCK(500);
CHECK_OUTPUT(2'b00, 1);
CHECK_OUTPUT(2'b01, 1);
CLOCK(400);
CHECK_OUTPUT(2'b00, 1);
CHECK_OUTPUT(2'b01, 1);
CLOCK(200);
CHECK_OUTPUT(2'b00, 0);
CHECK_OUTPUT(2'b01, 0);
CLOCK(FULL_CYCLE - (500 + 500 + 400 + 200));
LOAD_COMPARE_VALUE(2'b00, 32'd2500);
LOAD_COMPARE_VALUE(2'b01, 32'd2500);
LOAD_COMPARE_VALUE(2'b10, 32'd2500);
LOAD_COMPARE_VALUE(2'b11, 32'd2500);
CLOCK(FULL_CYCLE);
CLOCK(FULL_CYCLE);
LOAD_COMPARE_VALUE(2'b00, 32'd500);
LOAD_COMPARE_VALUE(2'b01, 32'd1000);
LOAD_COMPARE_VALUE(2'b10, 32'd1500);
LOAD_COMPARE_VALUE(2'b11, 32'd2000);
CLOCK(FULL_CYCLE);
CLOCK(500);
CHECK_OUTPUT(2'b00, 1);
CHECK_OUTPUT(2'b01, 1);
CHECK_OUTPUT(2'b10, 1);
CHECK_OUTPUT(2'b11, 1);
CLOCK(500);
CHECK_OUTPUT(2'b00, 0);
CHECK_OUTPUT(2'b01, 0);
CHECK_OUTPUT(2'b10, 1);
CHECK_OUTPUT(2'b11, 1);
CLOCK(500);
CHECK_OUTPUT(2'b00, 0);
CHECK_OUTPUT(2'b01, 0);
CHECK_OUTPUT(2'b10, 0);
CHECK_OUTPUT(2'b11, 1);
CLOCK(500);
CHECK_OUTPUT(2'b00, 0);
CHECK_OUTPUT(2'b01, 0);
CHECK_OUTPUT(2'b10, 0);
CHECK_OUTPUT(2'b11, 0);
CLOCK(500);
CHECK_OUTPUT(2'b00, 0);
CHECK_OUTPUT(2'b01, 0);
CHECK_OUTPUT(2'b10, 0);
CHECK_OUTPUT(2'b11, 0);
CLOCK(FULL_CYCLE - (500 * 5));
// Print out Success/Failure message
if (success_flag == 0) begin
$display("*FAILED* TEST!");
end else begin
$display("**PASSED** TEST!");
end
#10 $stop;
#5 $finish;
end
endmodule
| 7.208023 |
module test_setup ();
// clock_generator_0_wb_system_to_wb_example_0_wb_system wires:
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
// Ad-hoc wires:
wire wb_example_0_start_to_wb_example_bench_0_start;
wire wb_example_0_done_to_wb_example_bench_0_done;
wire wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
wire wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
// clock_generator_0 port wires:
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
// wb_example.bench_0 port wires:
wire wb_example_bench_0_clk_i;
wire wb_example_bench_0_done;
wire wb_example_bench_0_rst_i;
wire wb_example_bench_0_start;
// wb_example_0 port wires:
wire wb_example_0_clk_i;
wire wb_example_0_done;
wire wb_example_0_rst_i;
wire wb_example_0_start;
// clock_generator_0 assignments:
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_example_bench_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemrst = clock_generator_0_rst_o;
assign wb_example_bench_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
// wb_example.bench_0 assignments:
assign wb_example_bench_0_clk_i = wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
assign wb_example_bench_0_done = wb_example_0_done_to_wb_example_bench_0_done;
assign wb_example_bench_0_rst_i = wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
assign wb_example_0_start_to_wb_example_bench_0_start = wb_example_bench_0_start;
// wb_example_0 assignments:
assign wb_example_0_clk_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
assign wb_example_0_done_to_wb_example_bench_0_done = wb_example_0_done;
assign wb_example_0_rst_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
assign wb_example_0_start = wb_example_0_start_to_wb_example_bench_0_start;
// IP-XACT VLNV: tut.fi:other.test:clock_generator:1.1
clock_generator clock_generator_0 (
// Interface: wb_system
.clk_o(clock_generator_0_clk_o),
.rst_o(clock_generator_0_rst_o)
);
// IP-XACT VLNV: tut.fi:other.subsystem.test:wb_example.bench:1.0
TestInitializer #(
.WAIT_TIME(1200)
) wb_example_bench_0 (
// These ports are not in any interface
.clk_i(wb_example_bench_0_clk_i),
.done (wb_example_bench_0_done),
.rst_i(wb_example_bench_0_rst_i),
.start(wb_example_bench_0_start)
);
// IP-XACT VLNV: tut.fi:other.subsystem:wb_example:1.0
wb_example_0 wb_example_0 (
// Interface: wb_system
.clk_i(wb_example_0_clk_i),
.rst_i(wb_example_0_rst_i),
// These ports are not in any interface
.start(wb_example_0_start),
.done (wb_example_0_done)
);
endmodule
| 6.59498 |
module test_shifter_5 (
input clk,
input rst,
input start,
output reg [1:0] status
);
reg [3:0] M_test_counter_d, M_test_counter_q = 1'h0;
localparam IDLE_state = 2'd0;
localparam TEST_state = 2'd1;
localparam PASS_state = 2'd2;
localparam FAIL_state = 2'd3;
reg [1:0] M_state_d, M_state_q = IDLE_state;
wire [8-1:0] M_shifter_out;
reg [8-1:0] M_shifter_a;
reg [8-1:0] M_shifter_b;
reg [6-1:0] M_shifter_alufn;
shifter_13 shifter (
.a(M_shifter_a),
.b(M_shifter_b),
.alufn(M_shifter_alufn),
.out(M_shifter_out)
);
always @* begin
M_state_d = M_state_q;
M_test_counter_d = M_test_counter_q;
status = 1'h0;
M_shifter_a = 1'h0;
M_shifter_b = 1'h0;
M_shifter_alufn = 6'h00;
if (start == 1'h0) begin
M_state_d = IDLE_state;
end
case (M_state_q)
IDLE_state: begin
status = 1'h0;
if (start == 1'h1) begin
M_state_d = TEST_state;
end
end
TEST_state: begin
case (M_test_counter_q)
4'h0: begin
M_shifter_alufn = 6'h20;
M_shifter_a = 8'hff;
M_shifter_b = 8'h07;
if (M_shifter_out != 8'h80) begin
M_state_d = FAIL_state;
end
end
4'h1: begin
M_shifter_alufn = 6'h20;
M_shifter_a = 8'h00;
M_shifter_b = 8'h07;
if (M_shifter_out != 8'h00) begin
M_state_d = FAIL_state;
end
end
4'h2: begin
M_shifter_alufn = 6'h20;
M_shifter_a = 8'h35;
M_shifter_b = 8'h04;
if (M_shifter_out != 8'h50) begin
M_state_d = FAIL_state;
end
end
4'h3: begin
M_shifter_alufn = 6'h21;
M_shifter_a = 8'hff;
M_shifter_b = 8'h07;
if (M_shifter_out != 8'h01) begin
M_state_d = FAIL_state;
end
end
4'h4: begin
M_shifter_alufn = 6'h21;
M_shifter_a = 8'h00;
M_shifter_b = 8'h07;
if (M_shifter_out != 8'h00) begin
M_state_d = FAIL_state;
end
end
4'h5: begin
M_shifter_alufn = 6'h21;
M_shifter_a = 8'h35;
M_shifter_b = 8'h04;
if (M_shifter_out != 8'h03) begin
M_state_d = FAIL_state;
end
end
4'h6: begin
M_shifter_alufn = 6'h23;
M_shifter_a = 8'hff;
M_shifter_b = 8'h07;
if (M_shifter_out != 8'hff) begin
M_state_d = FAIL_state;
end
end
4'h7: begin
M_shifter_alufn = 6'h23;
M_shifter_a = 8'h00;
M_shifter_b = 8'h07;
if (M_shifter_out != 8'h00) begin
M_state_d = FAIL_state;
end
end
4'h8: begin
M_shifter_alufn = 6'h23;
M_shifter_a = 8'h35;
M_shifter_b = 8'h04;
if (M_shifter_out != 8'h03) begin
M_state_d = FAIL_state;
end
end
4'hf: begin
M_state_d = PASS_state;
end
endcase
end
PASS_state: begin
status = 1'h1;
end
FAIL_state: begin
status = 2'h2;
end
endcase
M_test_counter_d = M_test_counter_q + 1'h1;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_test_counter_q <= 1'h0;
end else begin
M_test_counter_q <= M_test_counter_d;
end
end
endmodule
| 7.186684 |
module Test_ShiftLoadRegister ();
reg i_rst, sck, load, i_we, miso;
reg [7:0] tx_packet;
wire [7:0] rx_packet;
SHIFTLOADREG #(8) buff (
.rst(i_rst),
.clk(sck),
.load(load),
.en(i_we),
.in(miso),
.D(tx_packet),
.Q(rx_packet)
);
initial begin
i_rst = 1;
sck = 0;
load = 0;
i_we = 0;
miso = 0;
tx_packet = 8'h01;
#5 i_rst = 0;
#25 load = 1;
#10 load = 0;
i_we = 1;
#80 $stop;
end
always #5 sck = !sck;
endmodule
| 7.129724 |
module shift_register_BCD_6;
wire [3:0] BCD_5;
wire [3:0] BCD_4;
wire [3:0] BCD_3;
wire [3:0] BCD_2;
wire [3:0] BCD_1;
wire [3:0] BCD_0;
reg [3:0] d_5;
reg [3:0] d_4;
reg [3:0] d_3;
reg [3:0] d_2;
reg [3:0] d_1;
reg [3:0] d_0;
reg clk;
reg rst_n;
shift_register_BCD_6 U0 (
BCD_5,
BCD_4,
BCD_3,
BCD_2,
BCD_1,
BCD_0,
d_5,
d_4,
d_3,
d_2,
d_1,
d_0,
clk,
rst_n
);
always #10 clk = ~clk;
initial begin
d_5 = 4'd0;
d_4 = 4'd1;
d_3 = 4'd2;
d_2 = 4'd3;
d_1 = 4'd4;
d_0 = 4'd4;
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
endmodule
| 6.854847 |
module test_shuffle;
parameter WAY = 3;
parameter WIRE = 5;
reg [WIRE-1:0] e1, e2, e3;
wire [WAY*WIRE-1:0] out;
shuffle #(
.WAY (WIRE),
.WIRE(WAY)
) inst_shuffle (
out,
{e3, e2, e1}
);
initial begin
$dumpfile("signal_test_shuffle.vcd");
$dumpvars;
$display("\t\ttime, \tout\t\t\te1\te2\te3\n");
$monitor("%d \t%b \t%b \t%b \t%b\n", $time, out, e1, e2, e3);
e1 <= 5'b11111;
e2 <= 5'b00000;
e3 <= 5'b00000;
#10;
e1 <= 5'b00000;
e2 <= 5'b11111;
e3 <= 5'b00000;
#10;
e1 <= 5'b00000;
e2 <= 5'b00000;
e3 <= 5'b11111;
#10;
end
endmodule
| 7.116976 |
module test_signal (
input clk,
input [15:0] in,
output reg [15:0] out
);
//assign out = {{B{in[W-1]}},in[W-1-:O_W-B]};
always @(posedge clk) begin
out <= in;
end
endmodule
| 7.333985 |
module test_signal_sync;
localparam RST_DURATION = 50; //ns
localparam CLK_PERIOD = 10; //ns
localparam SIGNAL_PERIOD = 100; //ns
// Inputs
reg clk_i;
reg rst_i;
reg signal_i;
// Outputs
wire signal_o;
wire valid_o;
wire edge_o;
wire posedge_o;
wire negedge_o;
// Instantiate the Unit Under Test (UUT)
signal_sync uut (
.clk_i(clk_i),
.rst_i(rst_i),
.signal_i(signal_i),
.signal_o(signal_o),
.valid_o(valid_o),
.edge_o(edge_o),
.posedge_o(posedge_o),
.negedge_o(negedge_o)
);
// Reset pulse generator
initial begin : reset_generator
rst_i = 1'b1;
#(RST_DURATION);
rst_i = 1'b0;
end
// Main oscillator
initial begin : clk_generator
clk_i = 1'b0;
#(RST_DURATION);
forever begin
clk_i = #(CLK_PERIOD / 2) ~clk_i;
end
end
// Main stimulus
initial begin : stimulus_generator
signal_i = 0;
#(RST_DURATION);
forever begin
signal_i = #(SIGNAL_PERIOD / 2) ~signal_i;
end
end
endmodule
| 7.59309 |
module: signExt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_signExt;
// Inputs
reg [15:0] immed;
// Outputs
wire [31:0] out;
// Instantiate the Unit Under Test (UUT)
signExt uut (
.immed(immed),
.out(out)
);
initial begin
// Initialize Inputs
immed = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
immed = 16'b0011111111111111;
#10;
immed = 16'b1100000000000000;
#10;
end
endmodule
| 6.532526 |
module f2_test (
a,
b,
c,
d,
z
);
input a, b, c, d;
output z;
reg z, temp1, temp2;
always @(a or b or c or d) begin
temp1 = a ^ b;
temp2 = c ^ d;
z = temp1 ^ temp2;
end
endmodule
| 6.539927 |
module f9_MyCounter (
clock,
preset,
updown,
presetdata,
counter
);
input clock, preset, updown;
input [1:0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if (preset) counter <= presetdata;
else if (updown) counter <= counter + 1;
else counter <= counter - 1;
endmodule
| 7.280849 |
module f2_test (
input [1:0] in,
output out
);
assign out = in[0] && in[1];
endmodule
| 6.539927 |
module f2_test (
input [1:0] in,
output [1:0] out
);
assign out[0] = in[0];
assign out[1] = in[1];
endmodule
| 6.539927 |
module f2_test (
input [1:0] in,
input enable,
output reg [2:0] out
);
always @(in or enable)
if (!enable) out = 3'b000;
else begin
case (in)
2'b00: out = 3'b001;
2'b01: out = 3'b010;
2'b10: out = 3'b010;
2'b11: out = 3'b100;
endcase
end
endmodule
| 6.539927 |
module f2_test (
input in,
output out
);
assign out = -in;
endmodule
| 6.539927 |
module f2_test (
input [1:0] in,
input select,
output reg out
);
always @(in or select)
case (select)
0: out = in[0];
1: out = in[1];
endcase
endmodule
| 6.539927 |
module f2_test (
input [2:0] in,
output out
);
assign out = !(in[0] & in[1] & in[2]);
endmodule
| 6.539927 |
module f2_test (
input [2:0] in,
output out
);
assign out = ~(in[0] | in[1] | in[2]);
endmodule
| 6.539927 |
module f2_test (
input [1:0] in,
output out
);
assign out = in[0] || in[1];
endmodule
| 6.539927 |
module f2_test (
input in,
input clk,
output reg out
);
always @(negedge clk) out <= in;
endmodule
| 6.539927 |
module f2_test (
input [31:0] IN,
input [ 5:0] SHIFT,
output [31:0] OUT
);
assign OUT = IN << SHIFT;
endmodule
| 6.539927 |
module f8_test (
input [3:0] IN,
input [2:0] SHIFT,
output [3:0] OUT
);
assign OUT = IN >> SHIFT;
endmodule
| 7.583792 |
module f9_test (
input [63:0] IN,
input [ 6:0] SHIFT,
output [63:0] OUT
);
assign OUT = IN >> SHIFT;
endmodule
| 6.818192 |
module f10_test (
input [7:0] IN,
input [3:0] SHIFT,
output [7:0] OUT
);
assign OUT = IN >> SHIFT;
endmodule
| 7.142357 |
module f2_test (
input [3:0] in,
input [1:0] select,
output reg out
);
always @(in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule
| 6.539927 |
module f8_test (
input in,
output out
);
assign out = ~in;
endmodule
| 7.583792 |
module f2_test (
input in,
output out
);
assign out = ~in;
endmodule
| 6.539927 |
module f2_TECH_AND5 (
input [4:0] in,
output out
);
assign out = ∈
endmodule
| 6.9174 |
module f3_TECH_NAND2 (
input [1:0] in,
output out
);
assign out = ~(&in);
endmodule
| 6.838201 |
module f4_TECH_NAND2 (
input [1:0] in,
output out
);
assign out = ~(&in);
endmodule
| 6.824305 |
module f5_TECH_NAND2 (
input [1:0] in,
output out
);
assign out = ~(&in);
endmodule
| 7.219721 |
module f6_TECH_NOR18 (
input [17:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.590859 |
module f6_TECH_NOR2 (
input [1:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.893604 |
module f7_TECH_NOR18 (
input [17:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.779355 |
module f7_TECH_NOR4 (
input [3:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.646228 |
module f7_TECH_NOR2 (
input [1:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.872539 |
module f8_TECH_NOR18 (
input [17:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.986617 |
module f8_TECH_NOR4 (
input [3:0] in,
output out
);
assign out = ~(|in);
endmodule
| 6.631019 |
module f8_TECH_NOR2 (
input [1:0] in,
output out
);
assign out = ~(|in);
endmodule
| 7.149186 |
module f10_TECH_OR5 (
input [4:0] in,
output out
);
assign out = |in;
endmodule
| 6.634688 |
module f11_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 6.783093 |
module f12_TECH_XOR5 (
input [4:0] in,
output out
);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
| 6.535766 |
module f12_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 7.227307 |
module f13_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 7.239592 |
module f14_TECH_XOR5 (
input [4:0] in,
output out
);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
| 6.778662 |
module f14_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 7.179551 |
module f15_TECH_XOR5 (
input [4:0] in,
output out
);
assign out = in[0] ^ in[1] ^ in[2] ^ in[3] ^ in[4];
endmodule
| 6.596125 |
module f15_TECH_XOR2 (
input [1:0] in,
output out
);
assign out = in[0] ^ in[1];
endmodule
| 7.163836 |
module f2_test (
clk,
cond,
data
);
input cond;
input clk;
output data;
wire synth_net;
wire synth_net_0;
wire synth_net_1;
wire synth_net_2;
wire synth_net_3;
wire synth_net_4;
wire synth_net_5;
wire synth_net_6;
wire synth_net_7;
wire synth_net_8;
wire synth_net_9;
wire synth_net_10;
wire synth_net_11;
wire tmp;
AND2 synth_AND (
.in ({synth_net_0, synth_net_1}),
.out(synth_net_2)
);
AND2 synth_AND_0 (
.in ({synth_net_3, synth_net_4}),
.out(synth_net_5)
);
AND2 synth_AND_1 (
.in ({synth_net_6, synth_net_7}),
.out(synth_net_8)
);
AND2 synth_AND_2 (
.in ({synth_net_9, synth_net_10}),
.out(synth_net_11)
);
BUF synth_BUF (
.in (synth_net),
.out(synth_net_0)
);
BUF synth_BUF_0 (
.in (data),
.out(synth_net_3)
);
BUF synth_BUF_1 (
.in (synth_net_8)
, .out(tmp)
);
BUF synth_BUF_2 (
.in (tmp),
.out(synth_net_9)
);
MUX2 synth_MUX (
.in({synth_net_2, synth_net_5}),
.select(cond),
.out(synth_net_6)
);
MUX2 synth_MUX_0 (
.in({synth_net_1, synth_net_4}),
.select(cond),
.out(synth_net_7)
);
FF synth_FF (
.d (synth_net_11),
.clk(clk),
.q (data)
);
VCC synth_VCC (.out(synth_net));
VCC synth_VCC_0 (.out(synth_net_1));
VCC synth_VCC_1 (.out(synth_net_4));
VCC synth_VCC_2 (.out(synth_net_10));
endmodule
| 6.539927 |
module f2_test (
input [2:0] in,
output out
);
assign out = ~(in[0] ^ in[1] ^ in[2]);
endmodule
| 6.539927 |
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