code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x10 (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire Mux2_inst8_O;
wire Mux2_inst9_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),
.O(Mux2_inst1_O)
);
Mux2 Mux2_inst2 (
.I({I1[2], I0[2]}),
.S(S),
.O(Mux2_inst2_O)
);
Mux2 Mux2_inst3 (
.I({I1[3], I0[3]}),
.S(S),
.O(Mux2_inst3_O)
);
Mux2 Mux2_inst4 (
.I({I1[4], I0[4]}),
.S(S),
.O(Mux2_inst4_O)
);
Mux2 Mux2_inst5 (
.I({I1[5], I0[5]}),
.S(S),
.O(Mux2_inst5_O)
);
Mux2 Mux2_inst6 (
.I({I1[6], I0[6]}),
.S(S),
.O(Mux2_inst6_O)
);
Mux2 Mux2_inst7 (
.I({I1[7], I0[7]}),
.S(S),
.O(Mux2_inst7_O)
);
Mux2 Mux2_inst8 (
.I({I1[8], I0[8]}),
.S(S),
.O(Mux2_inst8_O)
);
Mux2 Mux2_inst9 (
.I({I1[9], I0[9]}),
.S(S),
.O(Mux2_inst9_O)
);
assign O = {
Mux2_inst9_O,
Mux2_inst8_O,
Mux2_inst7_O,
Mux2_inst6_O,
Mux2_inst5_O,
Mux2_inst4_O,
Mux2_inst3_O,
Mux2_inst2_O,
Mux2_inst1_O,
Mux2_inst0_O
};
endmodule
| 6.548523 |
module Test (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire [9:0] my_mux_O;
Mux2x10 my_mux (
.I0(I0),
.I1(I1),
.S (S),
.O (my_mux_O)
);
assign O = my_mux_O;
endmodule
| 7.402791 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x10 (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire Mux2_inst8_O;
wire Mux2_inst9_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),
.O(Mux2_inst1_O)
);
Mux2 Mux2_inst2 (
.I({I1[2], I0[2]}),
.S(S),
.O(Mux2_inst2_O)
);
Mux2 Mux2_inst3 (
.I({I1[3], I0[3]}),
.S(S),
.O(Mux2_inst3_O)
);
Mux2 Mux2_inst4 (
.I({I1[4], I0[4]}),
.S(S),
.O(Mux2_inst4_O)
);
Mux2 Mux2_inst5 (
.I({I1[5], I0[5]}),
.S(S),
.O(Mux2_inst5_O)
);
Mux2 Mux2_inst6 (
.I({I1[6], I0[6]}),
.S(S),
.O(Mux2_inst6_O)
);
Mux2 Mux2_inst7 (
.I({I1[7], I0[7]}),
.S(S),
.O(Mux2_inst7_O)
);
Mux2 Mux2_inst8 (
.I({I1[8], I0[8]}),
.S(S),
.O(Mux2_inst8_O)
);
Mux2 Mux2_inst9 (
.I({I1[9], I0[9]}),
.S(S),
.O(Mux2_inst9_O)
);
assign O = {
Mux2_inst9_O,
Mux2_inst8_O,
Mux2_inst7_O,
Mux2_inst6_O,
Mux2_inst5_O,
Mux2_inst4_O,
Mux2_inst3_O,
Mux2_inst2_O,
Mux2_inst1_O,
Mux2_inst0_O
};
endmodule
| 6.548523 |
module Test (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire [9:0] my_mux_O;
Mux2x10 my_mux (
.I0(I0),
.I1(I1),
.S (S),
.O (my_mux_O)
);
assign O = my_mux_O;
endmodule
| 7.402791 |
module: Mario
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_mario;
// Inputs
reg clk;
reg clk_walk_anim;
reg clk_hero_anim;
reg rstn;
reg left;
reg right;
reg jump;
reg level;
reg hero;
// Outputs
wire [5:0] id;
wire [10:0] w;
wire [10:0] h;
// Instantiate the Unit Under Test (UUT)
Mario uut (
.clk(clk),
.clk_walk_anim(clk_walk_anim),
.clk_hero_anim(clk_hero_anim),
.rstn(rstn),
.left(left),
.right(right),
.jump(jump),
.level(level),
.hero(hero),
.id(id),
.w(w),
.h(h)
);
initial begin
// Initialize Inputs
rstn = 1;
left = 0;
right = 0;
jump = 0;
level = 0;
hero = 0;
#4;
rstn = 0;
#20;
left = 1;
#20;
right = 1;
#20;
left = 0;
#20;
right = 0;
#50;
jump = 1;
#20;
jump = 0;
#20;
level = 1;
#20;
hero = 1;
#20;
level = 0;
#100;
// Add stimulus here
end
always begin
clk_walk_anim = 0;
clk_hero_anim = 0;
clk = 0;
#2;
clk = 1;
#2;
clk_walk_anim = 1;
clk_hero_anim = 1;
clk = 0;
#2;
clk = 1;
#2;
end
endmodule
| 9.086647 |
module test_max_finder_tree;
// Parameters
parameter DATA_WIDTH = 8;
parameter PORT_COUNT = 16;
parameter ADDR_WIDTH = $clog2(PORT_COUNT);
// Inputs
reg [PORT_COUNT*DATA_WIDTH-1:0] values;
// Outputs
wire [DATA_WIDTH-1:0] max_val;
wire [ADDR_WIDTH-1:0] max_ptr;
initial begin
// myhdl integration
$from_myhdl(values);
$to_myhdl(max_val, max_ptr);
// dump file
$dumpfile("test_max_finder_tree.lxt");
$dumpvars(0, test_max_finder_tree);
end
max_finder_tree #(
.PORT_COUNT(PORT_COUNT),
.DATA_WIDTH(DATA_WIDTH)
) UUT (
.values (values),
.max_val(max_val),
.max_ptr(max_ptr)
);
endmodule
| 7.491518 |
module test_Mem;
reg EscreveMemoria;
reg LeMemoria;
reg [7:0] Endereco;
reg [7:0] DadoSalvo;
reg clock;
wire [7:0] DadoCarregado;
initial begin
EscreveMemoria = 1;
LeMemoria = 0;
DadoSalvo = 10;
Endereco = 7;
clock = 0;
#1 clock = 1;
#1;
$display("Valor salvo no endereco 7: %b", gate1.Memoria[7]);
$display("");
#1 clock = 0;
EscreveMemoria = 0;
LeMemoria = 1;
#1;
$display("Valor carregado do endereco 7: %b", DadoCarregado);
end
initial begin
$monitor(
"EscreveMemoria=%d LeMemoria=%d DadoSalvo=%d clock=%d DadoCarregado=%d Endereco=%d",
EscreveMemoria, LeMemoria, DadoSalvo, clock, DadoCarregado, Endereco);
end
BancoMemoria gate1 (
EscreveMemoria,
LeMemoria,
Endereco,
DadoSalvo,
clock,
DadoCarregado
);
endmodule
| 6.80341 |
module test_Memory_Unit ();
parameter word_size = 10;
parameter memory_size = 256;
parameter address_size = 8;
wire [word_size-1:0] data_out;
reg [word_size-1:0] data_in;
reg [address_size-1:0] address;
reg clk, write;
Memory_Unit mem1 (
data_out,
data_in,
address,
clk,
write
);
initial begin
clk = 0;
end
always #5 clk = ~clk;
initial begin
#35 address = 0;
data_in = 10'b01010_10101;
#35 address = 1;
write = 1;
#35 data_in = 10'b011_0001111;
#35 data_in = 10'b100_0000011; //store to address = 3
#35 address = 4;
write = 0;
#35 address = 5;
write = 1;
data_in = 10'b11_0010_0000; //save 32 to r0
end
endmodule
| 7.376101 |
module test_mesh_to_ring_stitch #(
parameter cycle_time_p = 20,
localparam num_tiles_x_p = 8,
localparam num_tiles_y_p = 8,
parameter reset_cycles_lo_p = 1,
parameter reset_cycles_hi_p = 5
);
import bsg_noc_pkg::*; // {P=0, W, E, N, S}
// clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #(.cycle_time_p(cycle_time_p)) clock_gen (.o(clk));
bsg_nonsynth_reset_gen #(
.num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen (
.clk_i (clk)
, .async_reset_o(reset)
);
localparam b_lp = 1;
localparam f_lp = 1;
localparam x_lp = (num_tiles_x_p);
localparam y_lp = (num_tiles_y_p);
logic [x_lp-1:0][y_lp-1:0][$clog2(x_lp*y_lp)-1:0] ids;
logic [x_lp-1:0][y_lp-1:0][b_lp-1:0] back_in, back_out;
logic [x_lp-1:0][y_lp-1:0][f_lp-1:0] fwd_in, fwd_out;
bsg_mesh_to_ring_stitch #(
.y_max_p(y_lp)
, .x_max_p(x_lp)
, .width_back_p(b_lp)
, .width_fwd_p(f_lp)
) m2r (
.id_o (ids)
, .back_data_in_o (back_in)
, .back_data_out_i(back_out)
, .fwd_data_in_o (fwd_in)
, .fwd_data_out_i (fwd_out)
);
always @(posedge clk) begin
if (reset) begin
back_out <= $bits(back_in)'(1);
fwd_out <= $bits(fwd_in)'(1);
end else begin
back_out <= back_in;
fwd_out <= fwd_in;
end
end
integer xx, yy;
always @(negedge clk) begin
for (yy = 0; yy < y_lp; yy = yy + 1) begin
for (xx = 0; xx < x_lp; xx = xx + 1) $write("%b", fwd_in[xx][yy]);
$write(" ");
for (xx = 0; xx < x_lp; xx = xx + 1) $write("%b", back_in[xx][yy]);
$write("\n");
end
$write("\n");
end
endmodule
| 7.186067 |
module Test_MES_AMP_SIN (
output wire S, //S=1, sin(x)>0
input clk,
output wire ce_tact, //ce_tact
input ce,
output wire [`m:0] SIN, //SIN
input [`m-1:0] NT,
output wire ce_S1, //ce_SAMPL1
input [`m:0] NS,
output wire ce_S2, //ce_SAMPL2
input we,
output wire [`m:0] S1, //SAMPL1
output wire [`m:0] S2, //SAMPL2
output wire [`m-1:0] mod_S1, // SAMPL1
output wire [`m-1:0] mod_S2, // SAMPL2
output wire ok_SQ, //
output wire [`m*2-1:0] AMP_QV, //
output wire [`m-1:0] AMP_SIN
); // SIN
//
Gen_SIN DD1 (
.ce (ce),
.SIN(SIN),
.clk(clk),
.S (S)
);
// SIN
MES_AMP_SIN_XT DD2 (
.clk(clk),
.ce_tact(ce_tact),
.ce(ce),
.ce_S1(ce_S1),
.NT(NT),
.ce_S2(ce_S2),
.SIN(SIN),
.S1(S1),
.we(we),
.S2(S2),
.mod_S1(mod_S1),
.mod_S2(mod_S2),
.AMP_QV(AMP_QV),
.ok_SQ(ok_SQ),
.AMP_SIN(AMP_SIN)
);
endmodule
| 6.76262 |
module test_microstore_rom;
reg [ 6:0] index; //Las entradas deben ser tipo reg
reg [ 6:0] counter;
wire [44:0] out; // Las salidas deben ser tipo wire
parameter sim_time = 15;
microstore_rom rom (
out,
index
);
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
counter = 0;
index = 0;
repeat (8) #2 counter = counter + 1;
end
always @(counter) begin
case (counter)
6'd0: begin
index = counter;
end
6'd1: begin
index = counter;
end
3'd2: begin
index = counter;
end
6'd3: begin
index = counter;
end
6'd4: begin
index = counter;
end
6'd5: begin
index = counter;
end
6'd6: begin
index = counter;
end
6'd7: begin
index = counter;
end
endcase
end
initial begin
$display("\tIndex\t\tCase:");
$monitor("\t%b\t\t%b", index, out);
end
endmodule
| 6.932146 |
module test_mii #(
parameter DATA_WIDTH = 4
) (
input wire clk,
input wire rst,
inout wire [DATA_WIDTH-1:0] mii_d,
inout wire mii_er,
inout wire mii_en,
inout wire mii_clk_en
);
endmodule
| 7.576411 |
module and (a,b,c,d,A_b, Z);
//ports
input [24:0] A_b;
input [-5:5] c;
input [5:-5] d;
input [7:4] a;
input [0:3] b;
output Z;
//wires
wire [24:0] A_b;
wire Z;
endmodule
| 6.739547 |
module test_MMU_XRAM(
input wire clk,
input wire rst_n,
output reg [`VAW-1:0] X_wr,
output reg [`VAW-1:0] X_rd,
output reg [`INTWIDTH*`CORE_N-1:0] X_din,
input wire [`INTWIDTH*`KSIZE-1:0] X_dout,
output reg wr_finish,
output reg X_din_valid,
input wire X_dout_valid,
);
endmodule
| 6.618375 |
module test_moa_8x8p1_tree;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
moa_8x8p1_tree U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.x5(x5),
.x6(x6),
.x7(x7),
.summ(summ)
);
// clock
always #5 clk = ~clk;
// reset
initial begin
clk = 0;
rst_n = 0;
#8;
rst_n = 1;
#2000;
$finish();
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.dump");
$dumpvars(0, test_moa_8x8p1_tree);
end
`endif
// stimulus
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
counter <= 8'd0;
x0 <= 8'd0;
x1 <= 8'd0;
x2 <= 8'd0;
x3 <= 8'd0;
x4 <= 8'd0;
x5 <= 8'd0;
x6 <= 8'd0;
x7 <= 8'd0;
end else begin
counter <= counter + 1'b1;
x0 <= counter + 1;
x1 <= counter + 2;
x2 <= counter + 3;
x3 <= counter + 4;
x4 <= counter + 4;
x5 <= counter + 3;
x6 <= counter + 2;
x7 <= counter + 1;
end
end
// check
always @(posedge clk) begin
if (rst_n == 1'b1) begin
$display("counter:%d summ:%d x0:%d\n", counter, summ, x0);
//if (summ != (counter-1)*8) begin
//$display("ERROR: summ %d != (counter-1)*8 %d:%d, arrival at %t",summ,(counter-1)*8,counter,$time);
//end
end
end
endmodule
| 6.902023 |
module test_moa_8x8p2_rt8_fa42;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
moa_8x8p2_rt8_fa42 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.x5(x5),
.x6(x6),
.x7(x7),
.summ(summ)
);
// clock
always #5 clk = ~clk;
// reset
initial begin
clk = 0;
rst_n = 0;
#8;
rst_n = 1;
#2000;
$finish();
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.dump");
$dumpvars(0, test_moa_8x8p2_rt8_fa42);
end
`endif
// stimulus
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
counter <= 8'd0;
x0 <= 8'd0;
x1 <= 8'd0;
x2 <= 8'd0;
x3 <= 8'd0;
x4 <= 8'd0;
x5 <= 8'd0;
x6 <= 8'd0;
x7 <= 8'd0;
end else begin
counter <= counter + 1'b1;
x0 <= counter + 1;
x1 <= counter + 2;
x2 <= counter + 3;
x3 <= counter + 4;
x4 <= counter + 4;
x5 <= counter + 3;
x6 <= counter + 2;
x7 <= counter + 1;
end
end
// check
always @(posedge clk) begin
if (rst_n == 1'b1) begin
$display("counter:%d summ:%d x0:%d\n", counter, summ, x0);
//if (summ != (counter-1)*8) begin
//$display("ERROR: summ %d != (counter-1)*8 %d:%d, arrival at %t",summ,(counter-1)*8,counter,$time);
//end
end
end
endmodule
| 6.902023 |
module test_moa_8x8p2_rt8_mfa42;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
moa_8x8p2_rt8_mfa42 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.x5(x5),
.x6(x6),
.x7(x7),
.summ(summ)
);
// clock
always #5 clk = ~clk;
// reset
initial begin
clk = 0;
rst_n = 0;
#8;
rst_n = 1;
#2000;
$finish();
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.dump");
$dumpvars(0, test_moa_8x8p2_rt8_mfa42);
end
`endif
// stimulus
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
counter <= 8'd0;
x0 <= 8'd0;
x1 <= 8'd0;
x2 <= 8'd0;
x3 <= 8'd0;
x4 <= 8'd0;
x5 <= 8'd0;
x6 <= 8'd0;
x7 <= 8'd0;
end else begin
counter <= counter + 1'b1;
x0 <= counter + 1;
x1 <= counter + 2;
x2 <= counter + 3;
x3 <= counter + 4;
x4 <= counter + 4;
x5 <= counter + 3;
x6 <= counter + 2;
x7 <= counter + 1;
end
end
// check
always @(posedge clk) begin
if (rst_n == 1'b1) begin
$display("counter:%d summ:%d x0:%d\n", counter, summ, x0);
//if (summ != (counter-1)*8) begin
//$display("ERROR: summ %d != (counter-1)*8 %d:%d, arrival at %t",summ,(counter-1)*8,counter,$time);
//end
end
end
endmodule
| 6.902023 |
module test_modify_clock_freq ();
reg CLOCK;
reg [15:0] COUNT_LIMIT;
wire PULSE;
modify_clock_freq dut (
CLOCK,
COUNT_LIMIT,
PULSE
);
initial begin
CLOCK = 0;
COUNT_LIMIT = 0;
//COUNT_LIMIT = 16'b0000000000000001; #100;
//COUNT_LIMIT = 16'b0000000000000010; #200;
//COUNT_LIMIT = 16'b0000000000000100; #200;
COUNT_LIMIT = 16'b1111111111111111;
#400;
end
always begin
#5 CLOCK = ~CLOCK;
end
endmodule
| 7.508179 |
module: modul01
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_modul01;
// Inputs
reg in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
modul01 uut (
.out(out),
.in(in)
);
initial begin
// Initialize Inputs
in = 0;
// Wait 100 ns for global reset to finish
#100;
in = 1;
// Add stimulus here
end
endmodule
| 6.931787 |
module: modul03
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_modul03;
// Inputs
reg in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
modul03 uut (
.out(out),
.in(in)
);
initial begin
// Initialize Inputs
in = 0;
// Wait 100 ns for global reset to finish
#100;
in = 1;
// Add stimulus here
end
endmodule
| 6.813018 |
module: modular_multip
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_modular;
// Inputs
reg clk;
reg reset;
reg [2:0] X;
reg [2:0] Y;
reg [2:0] Z;
// Outputs
wire [4:0] T;
wire [3:0] state;
wire [1:0] i;
wire [4:0] R;
// Instantiate the Unit Under Test (UUT)
modular_multip uut (
.clk(clk),
.reset(reset),
.X(X),
.Y(Y),
.Z(Z),
.T(T),
.state(state),.i(i),.R(R)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
X = 0;
Y = 0;
Z = 0;
reset=1;
#50
reset=0;
X=3'b111;
Y=3'b111;
Z=3'b111;
#800
reset=1;
#50
reset=0;
X=3'b001;
Y=3'b010;
Z=3'b011;
#800
reset=1;
#50
reset=0;
X=3'b100;
Y=3'b101;
Z=3'b111;
// Add stimulus here
end
always
#10
clk=~clk;
endmodule
| 6.974456 |
module test_module03 ();
// Inputs
reg in;
reg [1:0] sel;
// Outputs
/* verilator lint_off UNUSED */
wire [3:0] out;
/* verilator lint_on UNUSED */
// Instantiate the Unit Under Test (UUT)
module03 uut (
.out(out),
.sel(sel),
.in (in)
);
initial begin
$dumpfile("waves03.vcd");
$dumpvars(0, test_module03);
// Initialize Inputs
in = 0;
sel = 2'b00;
#10;
in = 1;
sel = 2'b00;
#10;
in = 0;
sel = 2'b01;
#10;
in = 1;
sel = 2'b01;
#10;
in = 0;
sel = 2'b10;
#10;
in = 1;
sel = 2'b10;
#10;
in = 0;
sel = 2'b11;
#10;
in = 1;
sel = 2'b11;
#10;
end
endmodule
| 7.139646 |
module test_module (
gpio_io,
clk_i,
resetn_i,
apb_penable_i,
apb_psel_i,
apb_pwrite_i,
apb_paddr_i,
apb_pwdata_i,
apb_prdata_o,
apb_pslverr_o,
apb_pready_o,
int_o
);
inout [7:0] gpio_io;
input clk_i;
input resetn_i;
input apb_penable_i;
input apb_psel_i;
input apb_pwrite_i;
input [5:0] apb_paddr_i;
input [31:0] apb_pwdata_i;
output [31:0] apb_prdata_o;
output apb_pslverr_o;
output apb_pready_o;
output int_o;
gpio0_ipgen_lscc_gpio #(
.FAMILY("MachXO3L"),
.IO_LINES_COUNT(8),
.EXTERNAL_BUF(0),
.OUT_RESET_VAL("32'h00000000"),
.DIRECTION_DEF_VAL("32'h000000FF"),
.IF_USER_INTF("APB")
) lscc_gpio_inst (
.gpio_io(gpio_io[7:0]),
.gpio_i(8'b00000000),
.gpio_o(),
.gpio_en_o(),
.clk_i(clk_i),
.resetn_i(resetn_i),
.lmmi_request_i(1'b0),
.lmmi_wr_rdn_i(1'b0),
.lmmi_offset_i(4'b0000),
.lmmi_wdata_i(8'b00000000),
.lmmi_rdata_o(),
.lmmi_rdata_valid_o(),
.lmmi_ready_o(),
.apb_penable_i(apb_penable_i),
.apb_psel_i(apb_psel_i),
.apb_pwrite_i(apb_pwrite_i),
.apb_paddr_i(apb_paddr_i[5:0]),
.apb_pwdata_i(apb_pwdata_i[31:0]),
.apb_prdata_o(apb_prdata_o[31:0]),
.apb_pslverr_o(apb_pslverr_o),
.apb_pready_o(apb_pready_o),
.int_o(int_o)
);
endmodule
| 6.581827 |
module test_mono_cpu_mips ();
reg clk;
wire [31:0] pc;
mono_cpu cpu (
.clk(clk),
.pc (pc)
);
initial clk = 1'b1;
always begin
#1 clk = ~clk;
if (pc == 32'h98 || pc == 32'h90) $stop;
end
endmodule
| 7.728514 |
module Test_Motherboard;
reg success_flag;
reg rst, clk;
initial begin
success_flag = 1;
rst = 0;
clk = 0;
#5 rst = 1;
#5 rst = 0;
#5
// Print out Success/Failure message
if (success_flag == 0) begin
$display("*FAILED* TEST!");
end else begin
$display("**PASSED** TEST!");
end
#10 $stop;
#5 $finish;
end
endmodule
| 6.674003 |
module top (
input clk,
input rst,
input [10:0] switch,
output reg [1:0] direction,
output pwm,
output [1:0] led
);
wire [9:0] duty;
assign led[0] = pwm;
assign led[1] = (direction == `MOTOR_FORWARD);
assign duty[9:0] = switch[9:0];
always @(posedge clk) begin
direction <= (switch[10] == 1'b0) ? `MOTOR_BACKWARD : `MOTOR_FORWARD;
end
motor_pwm motor_pwm_0 (
.clk(clk),
.reset(rst),
.duty(duty),
.pmod_1(pwm)
);
endmodule
| 7.233807 |
module PWM_gen (
input wire clk,
input wire reset,
input [31:0] freq,
input [9:0] duty,
output reg PWM
);
wire [31:0] count_max = 100_000_000 / freq;
wire [31:0] count_duty = count_max * duty / 1024;
reg [31:0] count;
always @(posedge clk, posedge reset) begin
if (reset) begin
count <= 0;
PWM <= 0;
end else if (count < count_max) begin
count <= count + 1;
if (count < count_duty) PWM <= 1;
else PWM <= 0;
end else begin
count <= 0;
PWM <= 0;
end
end
endmodule
| 6.517179 |
module test_mul16 (
input [15:0] a,
input [15:0] b,
output [15:0] out
);
assign out = a * b;
endmodule
| 6.773596 |
module test_multiplier;
reg a0, a1, a2, b0, b1, b2;
wire [6:0] led_o, led_t;
multiplier M1 (
a0,
a1,
a2,
b0,
b1,
b2,
led_o,
led_t
);
initial begin
a0 = 1'b0;
a1 = 1'b0;
a2 = 1'b0; //0x4
b0 = 1'b0;
b1 = 1'b0;
b2 = 1'b1;
#10 a0 = 1'b0;
a1 = 1'b1;
a2 = 1'b0; //2x4
b0 = 1'b0;
b1 = 1'b0;
b2 = 1'b1;
#10 a0 = 1'b0;
a1 = 1'b1;
a2 = 1'b0; //2x6
b0 = 1'b0;
b1 = 1'b1;
b2 = 1'b1;
#10 a0 = 1'b0;
a1 = 1'b0;
a2 = 1'b1; //4x6
b0 = 1'b0;
b1 = 1'b1;
b2 = 1'b1;
end
initial #50 $finish;
endmodule
| 6.529891 |
module test_multiplier_6 (
input clk,
input rst,
input start,
output reg [1:0] status
);
reg [4:0] M_test_counter_d, M_test_counter_q = 1'h0;
localparam IDLE_state = 2'd0;
localparam TEST_state = 2'd1;
localparam PASS_state = 2'd2;
localparam FAIL_state = 2'd3;
reg [1:0] M_state_d, M_state_q = IDLE_state;
wire [8-1:0] M_mul_out;
reg [8-1:0] M_mul_a;
reg [8-1:0] M_mul_b;
reg [6-1:0] M_mul_alufn;
multiplier_14 mul (
.a(M_mul_a),
.b(M_mul_b),
.alufn(M_mul_alufn),
.out(M_mul_out)
);
always @* begin
M_state_d = M_state_q;
M_test_counter_d = M_test_counter_q;
status = 1'h0;
M_mul_a = 1'h0;
M_mul_b = 1'h0;
M_mul_alufn = 6'h00;
if (start == 1'h0) begin
M_state_d = IDLE_state;
end
case (M_state_q)
IDLE_state: begin
status = 1'h0;
if (start == 1'h1) begin
M_state_d = TEST_state;
end
end
TEST_state: begin
case (M_test_counter_q)
4'h0: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'h00;
M_mul_b = 8'h00;
if (M_mul_out != 8'h00) begin
M_state_d = FAIL_state;
end
end
4'h1: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'h01;
M_mul_b = 8'h01;
if (M_mul_out != 8'h01) begin
M_state_d = FAIL_state;
end
end
4'h2: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'hff;
M_mul_b = 8'hff;
if (M_mul_out != 8'h01) begin
M_state_d = FAIL_state;
end
end
4'h3: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'h01;
M_mul_b = 8'h35;
if (M_mul_out != 8'h35) begin
M_state_d = FAIL_state;
end
end
4'h4: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'h35;
M_mul_b = 8'h53;
if (M_mul_out != 8'h2f) begin
M_state_d = FAIL_state;
end
end
4'h5: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'h03;
M_mul_b = 8'h03;
if (M_mul_out != 8'h09) begin
M_state_d = FAIL_state;
end
end
4'h6: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'hc0;
M_mul_b = 8'hc0;
if (M_mul_out != 8'h00) begin
M_state_d = FAIL_state;
end
end
4'h7: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'hfd;
M_mul_b = 8'hfc;
if (M_mul_out != 8'h0c) begin
M_state_d = FAIL_state;
end
end
4'h8: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'h02;
M_mul_b = 8'hfc;
if (M_mul_out != 8'hf8) begin
M_state_d = FAIL_state;
end
end
4'h9: begin
M_mul_alufn = 6'h02;
M_mul_a = 8'h80;
M_mul_b = 8'h40;
if (M_mul_out != 8'h00) begin
M_state_d = FAIL_state;
end
end
4'hf: begin
M_state_d = PASS_state;
end
endcase
end
PASS_state: begin
status = 1'h1;
end
FAIL_state: begin
status = 2'h2;
end
endcase
M_test_counter_d = M_test_counter_q + 1'h1;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_test_counter_q <= 1'h0;
end else begin
M_test_counter_q <= M_test_counter_d;
end
end
endmodule
| 6.529891 |
module test_multi_cycle_cpu ();
reg clk;
reg resetn;
wire [31:0] IF_pc;
wire [31:0] IF_inst;
wire [31:0] ID_pc;
wire [31:0] EXE_pc;
wire [31:0] MEM_pc;
wire [31:0] WB_pc;
wire [2:0] display_state;
wire [31:0] rf_data;
wire [31:0] mem_data;
multi_cycle_cpu multi_cycle_cpu (
.clk(clk),
.resetn(resetn),
// display data
.rf_addr(5'd8), // input
.mem_addr(32'h10), // input
.rf_data(rf_data), // output...
.mem_data(mem_data),
.IF_pc(IF_pc),
.IF_inst(IF_inst),
.ID_pc(ID_pc),
.EXE_pc(EXE_pc),
.MEM_pc(MEM_pc),
.WB_pc(WB_pc),
.display_state(display_state)
);
initial begin
clk = 1;
resetn = 0;
end
always #0.5 begin
resetn = 1;
clk = ~clk;
end
// Զcpuģ
endmodule
| 6.517225 |
module test_multX ();
parameter WIRE = 8;
reg [WIRE-1:0] A, B;
wire [WIRE-1:0] out;
multX #(
.WIRE(WIRE)
) inst_multX (
A,
B,
8'b0,
out
);
initial begin
$dumpfile("signal_multX.vcd");
$dumpvars;
$display("\t\ttime,\tA,\tB, \tout");
$monitor("%d \t%d \t%d \t%d", $time, A, B, out);
A <= 0;
B <= 0;
#10;
A <= 3;
B <= 5;
#10;
A <= 8;
B <= 12;
#10;
A <= 3;
B <= 10;
#10;
end
endmodule
| 6.708963 |
module test_mul_add16 (
input [15:0] a,
input [15:0] b,
input [15:0] c,
output [15:0] out
);
assign out = (a * b) + c;
endmodule
| 6.744817 |
module test_mux;
parameter SIZE_CTRL = 2;
parameter WIRE = 1;
wire [WIRE - 1 : 0] out;
reg [2 ** SIZE_CTRL - 1 : 0] in;
reg [1 : 0] ctrl;
mux #(
.SIZE_CTRL(SIZE_CTRL),
.WIRE(WIRE)
) mux0 (
ctrl,
in,
out
);
initial begin
$dumpfile("signal_mux.vcd");
$dumpvars;
$display("\t\ttime,\tout, \tin[0],\tin[1], \tin[2], \tin[3],\tctrl");
$monitor("%d \t%b \t%b \t%b \t%b \t%b \t%d", $time, out, in[0], in[1], in[2], in[3], ctrl);
in[0] = 1;
in[1] = 0;
in[2] = 1;
in[3] = 0;
ctrl[0] = 0;
ctrl[1] = 0;
#5;
ctrl[0] = 1;
ctrl[1] = 0;
#5;
ctrl[0] = 0;
ctrl[1] = 1;
#5;
ctrl[0] = 1;
ctrl[1] = 1;
#5;
end
endmodule
| 7.502555 |
module test_mux16;
reg [0:15] in;
reg [0:3] sel;
wire out;
mux16to1 mux (
out,
in,
sel
);
initial begin
$monitor("in :%b | sel : %b | out: %b", in, sel, out);
end
initial begin
in = 16'b0100000000000000;
sel = 4'b0000;
#3 in = 16'b0100000000000000;
sel = 4'b0001;
#3 in = 16'b0010000000000000;
sel = 4'b0010;
#3 in = 16'b0001000000000000;
sel = 4'b0011;
#3 in = 16'b0000100000000000;
sel = 4'b0100;
#3 in = 16'b0000010000000000;
sel = 4'b0101;
#3 in = 16'b0000001000000000;
sel = 4'b0110;
#3 in = 16'b0000000100000000;
sel = 4'b0111;
#3 in = 16'b0000000010000000;
sel = 4'b1000;
#3 in = 16'b0000000001000000;
sel = 4'b1001;
#3 in = 16'b0000000000100000;
sel = 4'b1010;
#3 in = 16'b0000000000010000;
sel = 4'b1011;
#3 in = 16'b0000000000001000;
sel = 4'b1100;
#3 in = 16'b0000000000000100;
sel = 4'b1101;
#3 in = 16'b0000000000000010;
sel = 4'b1110;
#3 in = 16'b0000000000000001;
sel = 4'b1111;
end
endmodule
| 7.029338 |
module test_mux8;
parameter SIZE_CTRL = 2;
parameter WIRE = 8;
localparam NB_IN = 2 ** SIZE_CTRL;
localparam SIZE_IN = NB_IN * WIRE;
wire [ WIRE - 1 : 0] out;
reg [SIZE_IN - 1 : 0] in;
reg [SIZE_CTRL-1 : 0] ctrl;
integer cpt1;
integer cpt2;
reg xin;
mux #(
.SIZE_CTRL(SIZE_CTRL),
.WIRE(WIRE)
) mux0 (
ctrl,
in,
out
);
initial begin
$dumpfile("signal_mux8.vcd");
$dumpvars;
xin = 0;
cpt1 = -1;
cpt2 = 0;
while (
++cpt1
< NB_IN) begin
while (cpt2 < (cpt1 + 1) * WIRE) begin
in[cpt2] = xin;
xin = ~xin;
cpt2++;
end
xin = ~xin;
$display("\t\tin[%d] = %b", cpt1, in[cpt1*WIRE+:8]); //:cpt1 * WIRE]);
end
$display("\t\ttime, \tout, \t\tctrl");
$monitor("%d\t%b\t%b", $time, out[7:0], ctrl[1:0]);
ctrl[0] = 0;
ctrl[1] = 0;
#5;
ctrl[0] = 1;
ctrl[1] = 0;
#5;
ctrl[0] = 0;
ctrl[1] = 1;
#5;
ctrl[0] = 1;
ctrl[1] = 1;
#5;
end
endmodule
| 7.373202 |
module: mux_16to1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_mux_16to1;
// Inputs
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
reg [31:0] D;
reg [31:0] E;
reg [31:0] F;
reg [31:0] G;
reg [31:0] H;
reg [31:0] I;
reg [31:0] J;
reg [31:0] K;
reg [31:0] L;
reg [31:0] M;
reg [31:0] N;
reg [31:0] O;
reg [31:0] P;
reg [3:0] S;
// Outputs
wire [31:0] Z;
// Instantiate the Unit Under Test (UUT)
mux_16to1 uut (
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F),
.G(G),
.H(H),
.I(I),
.J(J),
.K(K),
.L(L),
.M(M),
.N(N),
.O(O),
.P(P),
.S(S),
.Z(Z)
);
initial begin
// Initialize Inputs
A = 32'd11;
B = 32'd12;
C = 32'd13;
D = 32'd14;
E = 32'd15;
F = 32'd16;
G = 32'd17;
H = 32'd18;
I = 32'd19;
J = 32'd20;
K = 32'd21;
L = 32'd22;
M = 32'd23;
N = 32'd24;
O = 32'd25;
P = 32'd26;
S = 4'b0000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (S = 0; S != 4'b1111; S = S + 1) begin
#10;
$display("switch value=%b, output=%d", S, Z);
end
end
endmodule
| 7.639724 |
module test_mux_16x1;
reg [31:0] I0; //Las entradas del módulo deben ser tipo reg
reg [31:0] I1; //Las entradas del módulo deben ser tipo reg
reg [31:0] I2; //Las entradas del módulo deben ser tipo reg
reg [31:0] I3; //Las entradas del módulo deben ser tipo reg
reg [31:0] I4; //Las entradas del módulo deben ser tipo reg
reg [31:0] I5; //Las entradas del módulo deben ser tipo reg
reg [31:0] I6; //Las entradas del módulo deben ser tipo reg
reg [31:0] I7; //Las entradas del módulo deben ser tipo reg
reg [31:0] I8; //Las entradas del módulo deben ser tipo reg
reg [31:0] I9; //Las entradas del módulo deben ser tipo reg
reg [31:0] I10; //Las entradas del módulo deben ser tipo reg
reg [31:0] I11; //Las entradas del módulo deben ser tipo reg
reg [31:0] I12; //Las entradas del módulo deben ser tipo reg
reg [31:0] I13; //Las entradas del módulo deben ser tipo reg
reg [31:0] I14; //Las entradas del módulo deben ser tipo reg
reg [31:0] I15; //Las entradas del módulo deben ser tipo reg
wire [31:0] Y; //Las salidas deben ser tipo wire
reg [ 3:0] S;
parameter sim_time = 1000;
mux_16x1 mux2 (
Y,
S,
I0,
I1,
I2,
I3,
I4,
I5,
I6,
I7,
I8,
I9,
I10,
I11,
I12,
I13,
I14,
I15
);
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
I0 = 32'h0;
I1 = 32'h1;
I2 = 32'h2;
I3 = 32'h3;
I4 = 32'h4;
I5 = 32'h5;
I6 = 32'h6;
I7 = 32'h7;
I8 = 32'h8;
I9 = 32'h9;
I10 = 32'hA;
I11 = 32'hB;
I12 = 32'hC;
I13 = 32'hD;
I14 = 32'hE;
I15 = 32'hF;
S = 4'b0000;
repeat (16) #16 S = S + 1'b1;
end
initial begin
$display(
" S \t I15 \t I14 \t I13 \t I12 \t I11 \t I10 \t I9 \t I8 \t I7 \t I6 \t I5 \t I4 \t I3 \t I2 \t I1 \t I0 \t Y "); //imprime header
$monitor(" %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h ", S, I15, I14, I13, I12, I11,
I10, I9, I8, I7, I6, I15, I4, I3, I2, I1, I0, Y); //imprime las señales
end
endmodule
| 6.773965 |
module mux_16to1_test;
// Inputs
reg [15:0] A;
reg [15:0] B;
reg [15:0] C;
reg [15:0] D;
reg [15:0] E;
reg [15:0] F;
reg [15:0] G;
reg [15:0] H;
reg [15:0] I;
reg [15:0] J;
reg [15:0] K;
reg [15:0] L;
reg [15:0] M;
reg [15:0] O;
reg [15:0] P;
reg [15:0] Q;
reg [ 3:0] S;
// Outputs
wire [15:0] Z;
// Instantiate the Unit Under Test (UUT)
mux_16to1 uut (
.A(A),
.B(B),
.C(C),
.D(D),
.E(E),
.F(F),
.G(G),
.H(H),
.I(I),
.J(J),
.K(K),
.L(L),
.M(M),
.O(O),
.P(P),
.Q(Q),
.S(S),
.Z(Z)
);
integer i = 0;
initial begin
// Initialize Inputsn
A = 16'b0000000000000000;
B = 16'b0000000000001111;
C = 16'b0000000011110000;
D = 16'b0000000011111111;
E = 16'b0000111100000000;
F = 16'b0000111100001111;
G = 16'b0000111111110000;
H = 16'b0000111111111111;
I = 16'b1111000000000000;
J = 16'b1111000000001111;
K = 16'b1111000011110000;
L = 16'b1111000011111111;
M = 16'b1111111100000000;
O = 16'b1111111100001111;
P = 16'b1111111111110000;
Q = 16'b1111111111111111;
for (i = 0; i < 16; i = i + 1) begin
S = i;
#10; //test when S = 1...16
end
$finish;
end
endmodule
| 6.563488 |
module test_mux_1_2 (
data0,
data1,
ctrl,
out
);
input [0:0] data0, data1;
input [1:0] ctrl;
output [0:0] out;
wire [0:0] data0, data1;
wire [1:0] ctrl;
wire [0:0] out;
AO22XL g18 (
.A0(data0),
.A1(ctrl[0]),
.B0(data1),
.B1(ctrl[1]),
.Y (out)
);
endmodule
| 6.593147 |
module test_mux_1_32 (
data0,
data1,
data2,
data3,
data4,
data5,
data6,
data7,
data8,
data9,
data10,
data11,
data12,
data13,
data14,
data15,
data16,
data17,
data18,
data19,
data20,
data21,
data22,
data23,
data24,
data25,
data26,
data27,
data28,
data29,
data30,
data31,
ctrl,
out
);
input [0:0] data0, data1, data2, data3, data4, data5, data6, data7,
data8, data9, data10, data11, data12, data13, data14, data15,
data16, data17, data18, data19, data20, data21, data22, data23,
data24, data25, data26, data27, data28, data29, data30, data31;
input [31:0] ctrl;
output [0:0] out;
wire [0:0] data0, data1, data2, data3, data4, data5, data6, data7,
data8, data9, data10, data11, data12, data13, data14, data15,
data16, data17, data18, data19, data20, data21, data22, data23,
data24, data25, data26, data27, data28, data29, data30, data31;
wire [31:0] ctrl;
wire [ 0:0] out;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
wire n_16, n_17, n_18, n_19;
OR4X1 g1149 (
.A(n_17),
.B(n_19),
.C(n_18),
.D(n_16),
.Y(out)
);
NAND4XL g1150 (
.A(n_10),
.B(n_15),
.C(n_5),
.D(n_0),
.Y(n_19)
);
NAND4XL g1151 (
.A(n_1),
.B(n_3),
.C(n_13),
.D(n_9),
.Y(n_18)
);
NAND4XL g1152 (
.A(n_4),
.B(n_2),
.C(n_14),
.D(n_7),
.Y(n_17)
);
NAND4XL g1153 (
.A(n_6),
.B(n_8),
.C(n_11),
.D(n_12),
.Y(n_16)
);
AOI22X1 g1160 (
.A0(data28),
.A1(ctrl[28]),
.B0(data29),
.B1(ctrl[29]),
.Y (n_15)
);
AOI22X1 g1154 (
.A0(data19),
.A1(ctrl[19]),
.B0(data20),
.B1(ctrl[20]),
.Y (n_14)
);
AOI22X1 g1159 (
.A0(data3),
.A1(ctrl[3]),
.B0(data4),
.B1(ctrl[4]),
.Y (n_13)
);
AOI22X1 g1169 (
.A0(data0),
.A1(ctrl[0]),
.B0(data8),
.B1(ctrl[8]),
.Y (n_12)
);
AOI22X1 g1168 (
.A0(data9),
.A1(ctrl[9]),
.B0(data10),
.B1(ctrl[10]),
.Y (n_11)
);
AOI22X1 g1155 (
.A0(data30),
.A1(ctrl[30]),
.B0(data31),
.B1(ctrl[31]),
.Y (n_10)
);
AOI22X1 g1161 (
.A0(data1),
.A1(ctrl[1]),
.B0(data2),
.B1(ctrl[2]),
.Y (n_9)
);
AOI22X1 g1162 (
.A0(data12),
.A1(ctrl[12]),
.B0(data13),
.B1(ctrl[13]),
.Y (n_8)
);
AOI22X1 g1165 (
.A0(data17),
.A1(ctrl[17]),
.B0(data18),
.B1(ctrl[18]),
.Y (n_7)
);
AOI22X1 g1163 (
.A0(data14),
.A1(ctrl[14]),
.B0(data15),
.B1(ctrl[15]),
.Y (n_6)
);
AOI22X1 g1164 (
.A0(data26),
.A1(ctrl[26]),
.B0(data27),
.B1(ctrl[27]),
.Y (n_5)
);
AOI22X1 g1157 (
.A0(data23),
.A1(ctrl[23]),
.B0(data25),
.B1(ctrl[25]),
.Y (n_4)
);
AOI22X1 g1156 (
.A0(data5),
.A1(ctrl[5]),
.B0(data6),
.B1(ctrl[6]),
.Y (n_3)
);
AOI22X1 g1166 (
.A0(data21),
.A1(ctrl[21]),
.B0(data22),
.B1(ctrl[22]),
.Y (n_2)
);
AOI22X1 g1158 (
.A0(data7),
.A1(ctrl[7]),
.B0(data11),
.B1(ctrl[11]),
.Y (n_1)
);
AOI22X1 g1167 (
.A0(data16),
.A1(ctrl[16]),
.B0(data24),
.B1(ctrl[24]),
.Y (n_0)
);
endmodule
| 6.655391 |
module test_mux_1_4 (
data0,
data1,
data2,
data3,
ctrl,
out
);
input [0:0] data0, data1, data2, data3;
input [3:0] ctrl;
output [0:0] out;
wire [0:0] data0, data1, data2, data3;
wire [3:0] ctrl;
wire [0:0] out;
wire n_0, n_1;
NAND2X1 g36 (
.A(n_1),
.B(n_0),
.Y(out)
);
AOI22X1 g37 (
.A0(data1),
.A1(ctrl[1]),
.B0(data2),
.B1(ctrl[2]),
.Y (n_1)
);
AOI22X1 g38 (
.A0(data0),
.A1(ctrl[0]),
.B0(data3),
.B1(ctrl[3]),
.Y (n_0)
);
endmodule
| 6.647864 |
module test_mux_2to1_32bit ();
reg [31:0] inp1, inp2;
reg sel;
wire [31:0] outp;
mux_2to1_32bit mx (
outp,
inp1,
inp2,
sel
);
initial begin
$monitor(" inp1: %b ", inp1, " inp2: %b ", inp2, " sel: ", sel, " outp: %b ", outp);
end
initial begin
inp1 = 32'b00000000000000000000000000000000;
inp2 = 32'b11111111111111111111111111111111;
sel = 1'b0;
#100 sel = 1'b1;
#1000 $finish;
end
endmodule
| 7.468822 |
module test_mux_2to1_8bit ();
reg [7:0] inp1, inp2;
reg sel;
wire [7:0] outp;
mux_2to1_8bit mx (
outp,
inp1,
inp2,
sel
);
initial begin
inp1 = 8'b10101010;
inp2 = 8'b01010101;
sel = 1'b0;
#100 sel = 1'b1;
#1000 $finish;
end
initial $monitor(" inp1 = %b ", inp1, " inp2 = %b ", inp2, " sel = ", sel, " outp = %b", outp);
endmodule
| 7.468822 |
module test_mux_2x1;
reg [2:0] I;
reg [31:0] I0; //Las entradas del módulo deben ser tipo reg
reg [31:0] I1; //Las entradas del módulo deben ser tipo reg
wire [31:0] Y; //Las salidas deben ser tipo wire
reg S;
parameter sim_time = 100;
mux_2x1 mux1 (
Y,
S,
I0,
I1
); // Instanciación del módulo
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
I = 3'b000; //Genera las combinaciones de las entradas
I0 = 32'h0;
I1 = 32'hFFFFFFFF;
S = 1'b0;
repeat (1) #10 S = S + 1'b1; //cada 10 unidades de tiempo
end
initial begin
$display(" S I I1 I0 Y"); //imprime header
$monitor(" %b %b %b %b %b", S, I, I1, I0, Y); //imprime las señales
end
endmodule
| 6.929887 |
module test_mux_2x1_4;
reg [2:0] I;
reg [3:0] I0; //Las entradas del módulo deben ser tipo reg
reg [3:0] I1; //Las entradas del módulo deben ser tipo reg
wire [3:0] Y; //Las salidas deben ser tipo wire
reg S;
parameter sim_time = 100;
mux_2x1_4 mux1 (
Y,
S,
I0,
I1
); // Instanciación del módulo
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
I = 3'b000; //Genera las combinaciones de las entradas
I0 = 4'b0;
I1 = 4'b1111;
S = 1'b0;
repeat (1) #10 S = S + 1'b1; //cada 10 unidades de tiempo
end
initial begin
$display(" S I I1 I0 Y"); //imprime header
$monitor(" %b %b %b %b %b", S, I, I1, I0, Y); //imprime las señales
end
endmodule
| 6.810985 |
module test_mux_32to1 ();
// Inputs
reg [31:0] X;
reg [4:0] S;
// Outputs
wire Z;
// Instantiate the Unit Under Test (UUT)
mux_32to1 uut (
.X(X),
.S(S),
.Z(Z)
);
initial begin
// Initialize Inputs
X = 32'b11000000000000000000000001010101;
S = 4'b0000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
for (S = 0; S != 4'b1111; S = S + 1) begin
#10;
$display("switch value=%b, output=%d", S, Z);
end
end
endmodule
| 8.005332 |
module test_mux_3to1_32bit ();
reg [31:0] in1, in2, in3;
reg [ 1:0] sel;
wire [31:0] outp;
mux_3to1_32bit mx (
outp,
in1,
in2,
in3,
sel
);
initial begin
$monitor(" in1: %b", in1, " in2: %b", in2, " in3: %b", in3, " sel: %b", sel, " out: %b", outp);
end
initial begin
in1 = 32'b0;
in2 = 32'b11111111111111111111111111111111;
in3 = {16'b0, 16'b1111111111111111};
sel = 2'b00;
#10 sel = 2'b01;
#100 sel = 2'b10;
#500 sel = 2'b11;
#1000 $finish;
end
endmodule
| 7.240672 |
module test_mux_4in_1out ();
reg in0, in1, in2, in3;
reg [1:0] select;
wire out;
mux_4in_1out mux4in1out (
{in3, in2, in1, in0},
select,
out
);
always #0.1 in0 = ~in0;
always #0.5 in1 = ~in1;
always #1 in2 = ~in2;
always #5 in3 = ~in3;
initial begin
$dumpfile("out_mux.vcd");
$dumpvars(0, test_mux_4in_1out);
in0 = 0;
in1 = 0;
in2 = 0;
in3 = 0;
select = 2'b00;
#20 select = 2'b01;
#20 select = 2'b10;
#20 select = 2'b11;
#20 $finish;
end
endmodule
| 7.490018 |
module test_mux_4x1;
reg [31:0] I0; //Las entradas del módulo deben ser tipo reg
reg [31:0] I1; //Las entradas del módulo deben ser tipo reg
reg [31:0] I2; //Las entradas del módulo deben ser tipo reg
reg [31:0] I3; //Las entradas del módulo deben ser tipo reg
wire [31:0] Y; //Las salidas deben ser tipo wire
reg [ 1:0] S;
parameter sim_time = 1000;
mux_4x1 mux1 (
Y,
S,
I0,
I1,
I2,
I3
); // Instanciación del módulo
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
I0 = 32'h0;
I1 = 32'hFFFFFFFF;
I2 = 32'hFFFF0000;
I3 = 32'h0000FFFF;
S = 1'b0;
repeat (3) #10 S = S + 1'b1; //cada 10 unidades de tiempo
end
initial begin
$display(" S \t I3 \t I2 \t I1 \t I0 \t Y "); //imprime header
$monitor(" %h %h %h %h %h %h", S, I3, I2, I1, I0, Y); //imprime las señales
end
endmodule
| 7.00211 |
module test_mux_4x1_4;
reg [3:0] I0; //Las entradas del módulo deben ser tipo reg
reg [3:0] I1; //Las entradas del módulo deben ser tipo reg
reg [3:0] I2; //Las entradas del módulo deben ser tipo reg
reg [3:0] I3; //Las entradas del módulo deben ser tipo reg
wire [3:0] Y; //Las salidas deben ser tipo wire
reg [1:0] S;
parameter sim_time = 1000;
mux_4x1_4 mux1 (
Y,
S,
I0,
I1,
I2,
I3
); // Instanciación del módulo
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
I0 = 4'b0101;
I1 = 4'b1111;
I2 = 4'b0000;
I3 = 4'b1010;
S = 1'b0;
repeat (3) #10 S = S + 1'b1; //cada 10 unidades de tiempo
end
initial begin
$display(" S \t I3 \t I2 \t I1 \t I0 \t Y "); //imprime header
$monitor(" %b %b %b %b %b %b", S, I3, I2, I1, I0, Y); //imprime las señales
end
endmodule
| 7.361327 |
module test_mux_4x1_cu;
reg I0; //Las entradas del módulo deben ser tipo reg
reg I1; //Las entradas del módulo deben ser tipo reg
reg I2; //Las entradas del módulo deben ser tipo reg
reg I3; //Las entradas del módulo deben ser tipo reg
wire Y; //Las salidas deben ser tipo wire
reg [1:0] S;
parameter sim_time = 1000;
mux_4x1_4_cu mux1 (
Y,
S,
I0,
I1,
I2,
I3
); // Instanciación del módulo
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
I0 = 1'b1;
I1 = 1'b0;
I2 = 1'b1;
I3 = 1'b0;
S = 1'b0;
repeat (3) #10 S = S + 1'b1; //cada 10 unidades de tiempo
end
initial begin
$display(" S \t I3 \t I2 \t I1 \t I0 \t Y "); //imprime header
$monitor(" %b %b %b %b %b %b", S, I3, I2, I1, I0, Y); //imprime las señales
end
endmodule
| 7.361327 |
module test_mux_4_1 ();
// Inputs.
reg a;
reg b;
reg c;
reg d;
reg [1:0] sel;
reg i;
reg j;
reg k;
reg l;
/* verilator lint_off UNUSED */
reg out;
wire res;
/* verilator lint_on UNUSED */
// Initializing UUT.
mux_4_1 UUT (
.out (res),
.in0 (a),
.in1 (b),
.in2 (c),
.in3 (d),
.sel0(sel[0]),
.sel1(sel[1])
);
initial begin
$dumpfile("waves.vcd");
$dumpvars(0, test_mux_4_1);
// Initializing inputs.
sel = 0;
repeat (4) begin
i = 0;
repeat (2) begin
j = 0;
repeat (2) begin
k = 0;
repeat (2) begin
l = 0;
repeat (2) begin
a = i;
b = j;
c = k;
d = l;
#10; // Wait 10s.
l++;
end
k++;
end
j++;
end
i++;
end
sel++;
end
end
endmodule
| 6.882895 |
module test_mux_8_2 (
data0,
data1,
ctrl,
out
);
input [7:0] data0, data1;
input [1:0] ctrl;
output [7:0] out;
wire [7:0] data0, data1;
wire [1:0] ctrl;
wire [7:0] out;
AO22XL g107 (
.A0(data0[1]),
.A1(ctrl[0]),
.B0(data1[1]),
.B1(ctrl[1]),
.Y (out[1])
);
AO22XL g111 (
.A0(data0[2]),
.A1(ctrl[0]),
.B0(data1[2]),
.B1(ctrl[1]),
.Y (out[2])
);
AO22XL g106 (
.A0(data0[7]),
.A1(ctrl[0]),
.B0(data1[7]),
.B1(ctrl[1]),
.Y (out[7])
);
AO22XL g110 (
.A0(data0[0]),
.A1(ctrl[0]),
.B0(data1[0]),
.B1(ctrl[1]),
.Y (out[0])
);
AO22XL g104 (
.A0(data0[4]),
.A1(ctrl[0]),
.B0(data1[4]),
.B1(ctrl[1]),
.Y (out[4])
);
AO22XL g108 (
.A0(data0[5]),
.A1(ctrl[0]),
.B0(data1[5]),
.B1(ctrl[1]),
.Y (out[5])
);
AO22XL g105 (
.A0(data0[6]),
.A1(ctrl[0]),
.B0(data1[6]),
.B1(ctrl[1]),
.Y (out[6])
);
AO22XL g109 (
.A0(data0[3]),
.A1(ctrl[0]),
.B0(data1[3]),
.B1(ctrl[1]),
.Y (out[3])
);
endmodule
| 7.324161 |
module TEST_MUX_Four_1 ();
reg [3:0] D;
reg [1:0] S;
wire Out;
initial begin
#100 D = 4'b0001;
S = 2'b00;
#100 D = 4'b0010;
S = 2'b10;
#100 D = 4'b0000;
S = 2'b01;
#100 D = 4'b1000;
S = 2'b11;
#100 $stop;
end
Four_1_Mux Inst0 (
Out,
S,
D
);
endmodule
| 6.609162 |
module test_myDAC ();
reg CLOCK;
reg RESET;
reg btnU;
reg btnD;
wire [3:0] JA;
wire LED;
myDAC dut (
CLOCK,
RESET,
btnU,
btnD,
JA,
LED
);
initial begin
CLOCK = 0;
RESET = 0;
btnU = 0;
btnD = 0;
end
always begin
#5 CLOCK = ~CLOCK;
end
endmodule
| 6.663396 |
module test_uart;
// Transmitter Ports
reg i_Tx_Dv;
reg [7:0] i_Tx_Byte;
reg i_clk;
// Receiver Ports:
wire [7:0] o_Rx_Byte;
wire o_Rx_Dv;
// Define Parameter : Purpose : To get the clock of 10MHz and the Baud Rate of 115200.
// So the CLK_CY_PER_BIT = 87 (Approx.)
parameter IN_CLK_PER = 100; // For input clk of 10MHz (`timescale 1ns/1ps)
parameter CLK_CY_PER_BIT = 87;
parameter BIT_PERIOD = 8600;
//Instantiate the DUT :
uart_top #(
.CLK_CY_PER_BIT(CLK_CY_PER_BIT)
) uut (
.i_clk(i_clk),
.i_Tx_Dv(i_Tx_Dv),
.i_Tx_Byte(i_Tx_Byte),
.o_Rx_Byte(o_Rx_Byte),
.o_Rx_Dv(o_Rx_Dv)
);
// Clock Build Block:
initial begin
i_clk <= 0;
forever #(IN_CLK_PER / 2) i_clk <= ~(i_clk);
end
initial begin
@(posedge i_clk);
i_Tx_Dv <= 1'b1;
i_Tx_Byte <= 8'h8B;
@(posedge i_clk);
i_Tx_Dv <= 1'b0;
@(posedge uut.UART_TX_INST.o_Tx_Done);
$display("Transmitter has Done transmitting to the Serial Line");
end
initial begin
@(posedge o_Rx_Dv);
$display(" Recieved Data : %h", o_Rx_Byte);
$finish;
end
endmodule
| 7.673351 |
module test_uart_rx;
//Define the variables same as the ports of DUT (UART Receiver)
reg i_clk;
reg i_Rx_Serial;
wire o_Rx_Dv;
wire [7:0] o_Rx_Byte;
// To Cross checke wheather the data is received is correct or not:
reg r_parity_check;
reg [7:0] r_in_Byte;
reg [10:0] r_in_serial;
reg [3:0] r_bit_idx;
reg r_parity;
// Define Parameter : Purpose : To get the clock of 10MHz and the Baud Rate of 115200.
// So the CLK_CY_PER_BIT = 87 (Approx.)
parameter IN_CLK_PER = 100; // For input clk of 10MHz (`timescale 1ns/1ps)
parameter CLK_CY_PER_BIT = 87;
parameter BIT_PERIOD = 8600;
// Instantiate the DUT:
uart_rx #(
.CLK_CY_PER_BIT(CLK_CY_PER_BIT)
) UART_RX_INST (
.i_clk(i_clk),
.i_Rx_Serial(i_Rx_Serial),
.o_Rx_Byte(o_Rx_Byte),
.o_Rx_Dv(o_Rx_Dv)
);
// Clock Buliding Block:
initial begin
i_clk <= 0;
r_bit_idx <= 0;
r_in_Byte <= 8'h8B;
forever #(IN_CLK_PER / 2) i_clk <= ~(i_clk);
end
// In this initial block we manually Send the Serial line bit input to the UART Receiver.
// 1. Wait for single clock period initially.
// 2. For two clock period keep the Serial Input Line High.
// 3. Create a Data Frame With the sequence {START bit, 8-bit DATA(8'h8B), Parity bit, STOP bit }
// 4. Feed to the Serial Line with the Wait of single bit period.
initial begin
@(posedge i_clk);
r_parity <= ^(r_in_Byte);
@(negedge i_clk);
r_in_serial <= {1'b1, r_parity, r_in_Byte, 1'b0};
repeat (2) begin
i_Rx_Serial <= 1;
@(posedge i_clk);
end
for (r_bit_idx = 0; r_bit_idx <= 10; r_bit_idx = r_bit_idx + 1) begin
i_Rx_Serial <= r_in_serial[r_bit_idx];
#(BIT_PERIOD);
end
r_parity_check <= ^(o_Rx_Byte);
if (r_in_Byte == o_Rx_Byte) $display("Correct Byte Received Test PASSED");
else $display("Correct Byte Received Test FAILED");
if (r_parity == r_parity_check) $display("Parity Check Test PASSED");
else $display("Parity Check Test FAILED");
if (r_in_Byte == o_Rx_Byte && r_parity == r_parity_check) $display("UART Receiver Test PASSED");
else $display("UART Receiver Test FAILED");
end
initial begin
@(posedge o_Rx_Dv);
$finish;
end
endmodule
| 7.014426 |
module test_uart_tx;
// Definig the variables same as port of DUT(UART TX):
reg i_clk;
reg i_Tx_Dv;
reg [7:0] i_Tx_Byte;
wire o_Tx_Active;
wire o_Tx_Serial;
wire o_Tx_Done;
//Internal variable to save the expected parity output:
reg r_exp_parity;
// Purpose : Define the parameter to get the clk of 10MHz and Baud Rate of 115200:
// So the CLK_CY_PER_BIT = 87 (Approx.)
parameter IN_CLK_PER = 100; // For input clk of 10MHz (`timescale 1ns/1ps)
parameter CLK_CY_PER_BIT = 87;
parameter BIT_PERIOD = 8600;
// Instantiate the DUT ( uart_tx module):
uart_tx #(
.CLK_CY_PER_BIT(CLK_CY_PER_BIT)
) UART_TX_INST (
.i_clk(i_clk),
.i_Tx_Dv(i_Tx_Dv),
.i_Tx_Byte(i_Tx_Byte),
.o_Tx_Active(o_Tx_Active),
.o_Tx_Serial(o_Tx_Serial),
.o_Tx_Done(o_Tx_Done)
);
// Clock Build Block:
initial begin
i_clk <= 0;
forever #(IN_CLK_PER / 2) i_clk <= ~(i_clk);
end
initial begin
@(posedge i_clk);
i_Tx_Dv <= 0;
i_Tx_Byte <= 0;
@(posedge i_clk);
i_Tx_Dv <= 1;
i_Tx_Byte <= 8'hAA;
r_exp_parity <= ^(i_Tx_Byte);
@(posedge i_clk);
i_Tx_Dv <= 0;
@(o_Tx_Done);
if (r_exp_parity == UART_TX_INST.r_parity_out) $display("Parity Check TEST PASSED");
else $display("Parity Check TEST FAILED");
$finish;
end
endmodule
| 7.694888 |
module test_my_mux4way16 ();
reg [15:0] a;
reg [15:0] b;
reg [15:0] c;
reg [15:0] d;
reg [ 1:0] s;
reg [15:0] expected;
wire [15:0] e;
my_mux4way16 u1 (
e,
a,
b,
c,
d,
s
);
initial begin
a = 16'b0101010101010101;
b = 16'b1010101010101010;
c = 16'b0000000011111111;
d = 16'b1111111100000000;
s = 2'b00;
expected = 16'b0101010101010101;
#1 s = 2'b01;
expected = 16'b1010101010101010;
#1 s = 2'b10;
expected = 16'b0000000011111111;
#1 s = 2'b11;
expected = 16'b1111111100000000;
end
initial $monitor("my_mux4way16 %d %b %b %b %b %b (%b %b)", $time, a, b, c, d, s, e, expected);
endmodule
| 7.012634 |
module test_my_mux8way16 ();
reg [15:0] a;
reg [15:0] b;
reg [15:0] c;
reg [15:0] d;
reg [15:0] e;
reg [15:0] f;
reg [15:0] g;
reg [15:0] h;
reg [ 2:0] sel;
reg [15:0] expected;
wire [15:0] j;
my_mux8way16 u1 (
j,
a,
b,
c,
d,
e,
f,
g,
h,
sel
);
initial begin
a = 16'b0101010101010101;
b = 16'b1010101010101010;
c = 16'b0000000011111111;
d = 16'b1111111100000000;
e = 16'b0011001100110011;
f = 16'b1100110011001100;
g = 16'b0000111100001111;
h = 16'b1111000011110000;
sel = 3'b000;
expected = 16'b0101010101010101;
#1 sel = 3'b001;
expected = 16'b1010101010101010;
#1 sel = 3'b010;
expected = 16'b0000000011111111;
#1 sel = 3'b011;
expected = 16'b1111111100000000;
#1 sel = 3'b100;
expected = 16'b0011001100110011;
#1 sel = 3'b101;
expected = 16'b1100110011001100;
#1 sel = 3'b110;
expected = 16'b0000111100001111;
#1 sel = 3'b111;
expected = 16'b1111000011110000;
end
initial
$monitor(
"my_mux8way16 %d %b %b %b %b %b %b %b %b %b (%b %b)",
$time,
a,
b,
c,
d,
e,
f,
g,
h,
sel,
j,
expected
);
endmodule
| 7.517702 |
module test_N16;
parameter period = 5;
reg clk, rstn;
reg [15:0] in1, in2;
wire [16:0] res;
CAP_N16_R4_P2 DUT (
.clk (clk),
.rstn(rstn),
.in1 (in1),
.in2 (in2),
.res (res)
);
always #period clk = ~clk;
//reset
initial begin
clk = 0;
rstn = 0;
in1 = 0;
in2 = 0;
#8;
rstn = 1;
#100;
$finish();
end
// stimulus
always @(negedge clk) begin
if (rstn == 1) begin
in1 <= in1 + 10;
in2 <= in2 + 20;
end
end
always @(posedge clk) begin
if (rstn == 1) begin
if (in1 + in2 != res) begin
$display("INFO: ERROR: in1:%d + in2:%d != res:%d, arrival at %t", in1, in2, res, $time);
end
end
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.vcd");
$dumpvars();
end
`endif
endmodule
| 6.58306 |
module test_nco (
input wire clk,
output wire [23:0] wave
);
wire [11:0] ph;
nco #(
.WIDTH(12),
.PHASE(23)
) nco (
.clk(clk),
.inc(2237),
.out(ph)
);
wire [16:0] sin;
sincos sc (
.clk(clk),
.phase(ph),
.out_sin(sin),
.out_cos()
);
assign wave = {1'b00, ~sin[16], sin[15:0], 6'b0};
endmodule
| 7.397517 |
module test_next_pc;
wire [31:0] cur_pc;
reg [31:0] imm;
reg branch;
reg zero;
wire [31:0] next_pc;
reg ce;
//reg [31:0] addr;
wire [31:0] inst;
reg clk;
reg rst_n;
initial begin
clk = 0;
rst_n = 0;
#100 rst_n = 1'b1;
ce = 1'b1;
branch = 1'b0;
zero = 1'b0;
end
always #20 clk = ~clk;
next_pc next_pc0 (
.pc(cur_pc),
.imm(imm),
.branch(branch),
.zero(zero),
.next_pc(next_pc)
);
inst_mem inst_mem0 (
.ce (ce),
.addr(cur_pc),
.inst(inst)
);
pc pc0 (
.clk (clk),
.rst_n(rst_n),
.next_pc(next_pc),
.cur_pc (cur_pc)
);
endmodule
| 6.571956 |
module test_not (
N1,
N2
);
input N1;
output N2;
not INV1_1 (N2, N1);
endmodule
| 6.747666 |
module: ntsc_clean
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_ntsc_clean;
// Inputs
reg clock_65mhz;
reg ntsc_flag;
reg [35:0] ntsc_pixels;
// Outputs
wire clean_ntsc_flag;
wire [35:0] clean_ntsc_pixels;
// Instantiate the Unit Under Test (UUT)
ntsc_clean uut (
.clock_65mhz(clock_65mhz),
.ntsc_flag(ntsc_flag),
.ntsc_pixels(ntsc_pixels),
.clean_ntsc_flag(clean_ntsc_flag),
.clean_ntsc_pixels(clean_ntsc_pixels)
);
initial begin
// Initialize Inputs
clock_65mhz = 0;
ntsc_flag = 0;
ntsc_pixels = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.704849 |
module test_num ();
reg [7:0] mem[3:0];
wire [7:0] a;
assign a = mem[0];
initial begin
mem[0] = 8'b0000_0000;
#1 $display("a = %b", a);
$finish();
end
endmodule
| 6.630698 |
module
module test_numbers_top(
input Clock,
input reset,
output HS_probe,
output VS_probe,
output hsync,
output vsync,
output [3:0]VGA_R,
output [3:0]VGA_G,
output [3:0]VGA_B
);
wire display_on;
wire [9:0] hpos;
wire [9:0] vpos;
video_sync_generator hvsync_gen(
.clk(Clock),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.display_on(display_on),
.hpos(hpos),
.vpos(vpos)
);
wire [3:0] digit = hpos[7:4];
wire [2:0] xofs = hpos[3:1];
wire [2:0] yofs = vpos[3:1];
wire [4:0] bits;
digits10_array numbers(
.digit(digit),
.yofs(yofs),
.bits(bits)
);
assign VGA_R = {4{display_on && 0}};
assign VGA_G = {4{display_on && bits[xofs ^ 3'b111]}};
assign VGA_B = {4{display_on && 0}};
endmodule
| 6.755183 |
module test_ofb_dec;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
OFB_dec e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("ofb_enc.txt", msg);
//$display("f=%b",msg[1]);
f = $fopen("ofb_dec.txt", "w");
#10
for (i = 1; i <= 131072; i = i + 1) begin
#1 message = msg[i];
//$display("%b",msg[i]);
key = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
//$monitor("%d",i);
//$display("%b",ciphertext);
//$fwrite(f,"%d",i);
iv = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
$fwrite(f, "%b\n", ciphertext);
end
#10 $fclose(f);
end
endmodule
| 6.528458 |
module test_ofb_enc;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
OFB_enc e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("binary.txt", msg);
//$display("f=%b",msg[1]);
f = $fopen("ofb_enc.txt", "w");
#10
for (i = 1; i <= 131072; i = i + 1) begin
#1 message = msg[i];
//$display("%b",msg[i]);
key = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
//$monitor("%d",i);
//$display("%b",ciphertext);
//$fwrite(f,"%d",i);
iv = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
$fwrite(f, "%b\n", ciphertext);
end
#10 $fclose(f);
end
endmodule
| 6.615351 |
module open_drain_pin #(
parameter tick_interval = 32'd27000000
) (
input clk_i,
input rst_ni,
input listen_first_i,
output led_recv_o,
output reg led_done_o = 1'b1,
inout pin_io
);
localparam INIT = 3'd0;
localparam LISTEN = 3'd1;
localparam TALK = 3'd2;
localparam IDLE = 3'd3;
localparam WAIT = 3'd4;
reg [ 2:0] state = INIT;
reg [ 3:0] listen_counter = 4'b0000;
reg [31:0] tick_counter = 32'd0;
reg [ 3:0] talk_counter = 4'b0000;
reg pin_r = 1'bz;
assign pin_io = pin_r;
assign led_recv_o = pin_io;
always @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin
state <= INIT;
tick_counter <= 32'd0;
talk_counter <= 4'd0;
pin_r <= 1'bz;
led_done_o <= 1'b1;
end else begin
case (state)
INIT: begin
led_done_o <= 1'b1;
tick_counter <= 32'b0;
talk_counter <= 4'd0;
pin_r <= 1'bz;
state <= WAIT;
end
WAIT: begin
tick_counter <= tick_counter + 1'b1;
if (tick_counter >= tick_interval) begin
state <= (listen_first_i) ? LISTEN : TALK;
tick_counter <= 32'd0;
end
end
LISTEN: begin
if (listen_counter >= 4'd5) begin
state <= (listen_first_i) ? TALK : IDLE;
led_done_o <= 1'b0;
end
end
IDLE: begin
end
TALK: begin
if (talk_counter >= 4'd5) begin
pin_r <= 1'bz;
state <= (listen_first_i) ? IDLE : LISTEN;
tick_counter <= 32'd0;
end else begin
if (tick_counter < tick_interval) begin
if (tick_counter < tick_interval / 2) pin_r <= 1'bz;
else pin_r <= 1'b0;
tick_counter <= tick_counter + 1'b1;
end else begin
pin_r <= 1'bz;
talk_counter <= talk_counter + 1'b1;
tick_counter <= 32'd0;
end
end
end // case: TALK
default: state <= state;
endcase // case (state)
end // else: !if(~rst_ni)
end // always @ (posedge clk_i or negedge rst_ni)
// Increment listen counter
always @(posedge pin_io or negedge rst_ni) begin
if (~rst_ni) listen_counter <= 4'b0;
else if (state == LISTEN) listen_counter <= listen_counter + 1'b1;
end
endmodule
| 8.290052 |
module test_open_drain #(
parameter tick_interval = 32'd27000000
) (
input clk_i,
input rst_ni,
inout pin1_io,
inout pin2_io,
output led_recv_1_o,
output led_done_1_o,
output led_recv_2_o,
output led_done_2_o
);
open_drain_pin #(
.tick_interval(tick_interval)
) p1 (
.clk_i(clk_i),
.rst_ni(rst_ni),
.listen_first_i(1'b1),
.pin_io(pin1_io),
.led_recv_o(led_recv_1_o),
.led_done_o(led_done_1_o)
);
open_drain_pin #(
.tick_interval(tick_interval)
) p2 (
.clk_i(clk_i),
.rst_ni(rst_ni),
.listen_first_i(1'b0),
.pin_io(pin2_io),
.led_recv_o(led_recv_2_o),
.led_done_o(led_done_2_o)
);
endmodule
| 7.970321 |
module i2c_tb ();
reg clk_r = 1'b0;
reg rst_nr = 1'b1;
always #1 clk_r = ~clk_r;
wire pin;
pullup (pin);
wire led_recv_1;
wire led_recv_2;
wire led_done_1;
wire led_done_2;
test_open_drain #(
.tick_interval(10)
) odt (
.clk_i (clk_r),
.rst_ni(rst_nr),
.pin1_io(pin),
.pin2_io(pin),
.led_recv_1_o(led_recv_1),
.led_done_1_o(led_done_1),
.led_recv_2_o(led_recv_2),
.led_done_2_o(led_done_2)
);
initial begin
$display("Starting Testbench...");
#1 rst_nr <= 1;
#1 rst_nr <= 0;
#1 rst_nr <= 1;
#400;
$finish();
end
initial begin
$dumpfile("output/test_open_drain_dump.vcd");
$dumpvars(3);
end
endmodule
| 7.100397 |
module ROM128x32 (
addr,
data
);
input [6:0] addr;
output [31:0] data;
reg [31:0] data;
reg [31:0] mem[0:127];
integer i;
initial begin
// Initialize the instruction memory
$readmemh(`IMEM_INIT, mem);
$display("Reading instruction memory......");
end
always @(addr) data = mem[addr];
endmodule
| 7.116055 |
module test;
// Clock period, ns
parameter CLOCK_PERIOD = 500;
// Pulse width, gap and break delay
parameter PWID = 500;
parameter PGAP = 500;
parameter BREAK = 25000; // 25us
// time constants
localparam USEC = 1000;
localparam MSEC = 1000000;
// Output waveform file for this test
initial begin
$dumpfile("tests/test_output.lxt2");
$dumpvars(0, test);
end
// 2MHz reference clock
reg refclk;
initial refclk = 1'b0;
always #(CLOCK_PERIOD / 2) refclk = !refclk;
// POST port interface
reg testreq;
wire testack;
initial testreq = 1'b0;
// LCD interface
wire [3:0] lcd_data;
wire lcd_rs, lcd_e;
// Transmit interface is omitted, display adapters always tx 0x00
// Instantiate the module we're testing
postcode p (
.refclk (refclk),
.testreq(testreq),
.testack(testack),
.lcd_data(lcd_data),
.lcd_rs(lcd_rs),
.lcd_e(lcd_e),
.txin(8'd0), // always transmit 0x00, display interface
.tx_pending(1'b1)
);
`include "tasks.v"
// Count the number of E-strobes
reg [7:0] lcd_e_count;
initial lcd_e_count = 0;
always @(posedge lcd_e) lcd_e_count += 1;
// Testbench
initial begin
// Startup delay
#25
// Four pulses to initialise the FSM to a known state
pulsebreak(
4);
// Three pulses for OUTPUT
pulsebreak(3);
$display($time, "<< sent OUTPUT req, lastAck=%d >>", lastAck);
if (lastAck != 1'b1) begin
$display("*** DUT ERROR at time %d. Output-ready was not received when expected.", $time);
#5 $finish;
end
// Send a byte
lcd_e_count = 0;
outbyte(8'h09);
$display($time, "<< LCD state PreRead -- data 0x%X, RS=%d E-strobes=%d >>", lcd_data, lcd_rs,
lcd_e_count);
if (lcd_e_count != 0) begin
$display("*** DUT ERROR at time %d. LCD E-strobe count mismatch -- is %d, wanted 0.", $time,
lcd_e_count);
$finish;
end
// Send an INPUT chaser and see if we got an E-strobe from the LCD
lcd_e_count = 0;
pulsebreak(12);
#1000;
$display($time, "<< LCD state PostRead -- data 0x%X, RS=%d E-strobes=%d >>", lcd_data, lcd_rs,
lcd_e_count);
if (lcd_e_count != 1) begin
$display("*** DUT ERROR at time %d. LCD E-strobe count mismatch -- is %d, wanted 1.", $time,
lcd_e_count);
$finish;
end
$display("<OK> Output test completed. reqcount=%d, time=%d", reqcount, $time);
#(5 * USEC);
$finish;
end
endmodule
| 7.816888 |
module test_p2s (
pdata24,
pdata16,
sdata24,
sdata16
);
input pdata24, pdata16;
output sdata24, sdata16;
input [23:0] pdata24;
input [15:0] pdata16;
//<statements>
endmodule
| 6.953236 |
module test_padder1;
// Inputs
reg [31:0] in;
reg [ 1:0] byte_num;
// Outputs
wire [31:0] out;
reg [31:0] wish;
// Instantiate the Unit Under Test (UUT)
padder1 uut (
.in(in),
.byte_num(byte_num),
.out(out)
);
initial begin
// Initialize Inputs
in = 0;
byte_num = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in = 32'h90ABCDEF;
byte_num = 0;
wish = 32'h01000000;
check;
byte_num = 1;
wish = 32'h90010000;
check;
byte_num = 2;
wish = 32'h90AB0100;
check;
byte_num = 3;
wish = 32'h90ABCD01;
check;
$display("Good!");
$finish;
end
task check;
begin
#(`P);
if (out !== wish) begin
$display("E");
$finish;
end
end
endtask
endmodule
| 6.510528 |
module TOP;
//ALU inputs
wire [63:0] out;
reg [63:0] MM_A, MM_B;
reg [31:0] imm;
reg [2:0] op;
wire [63:0] out;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
op = 3'b010;
MM_A = 64'h0000_0000_0000_0082;
MM_B = 64'h0000_0000_0000_0028;
#`cycle //1
$strobe ("time: %0d found error at: a = %x, b = %x, recieved out = %x",
$time, MM_A, MM_B, out);
if(out != 64'h0000_0000_0000_00AA);
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
MM_A = 64'h0000_0000_0000_7FFF;
MM_B = 64'h0000_0000_0000_7FFF;
#`cycle //3
$strobe ("time: %0d found error at: a = %x, b = %x, recieved out = %x",
$time, MM_A, MM_B, out);
if(out != 64'h0000_0000_0000_7FFF)
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
MM_A = 64'h0000_0000_0000_7FFF;
MM_B = 64'h0000_0000_0000_0001;
#`cycle //5
$strobe ("time: %0d found error at: a = %x, b = %x, recieved out = %x",
$time, MM_A, MM_B, out);
if(out != 64'h0000_0000_0000_7FFF)
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
MM_A = 64'h0000_0000_0000_8001;
MM_B = 64'h0000_0000_0000_8FF0;
#`cycle //7
$strobe ("time: %0d found error at: a = %x, b = %x, recieved out = %x",
$time, MM_A, MM_B, out);
if(out != 64'h0000_0000_0000_8000)
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("paddsw.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
/*
always @(*)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, recieved out = %x",
$time, MM_A, MM_B, out);
else
$strobe ("correct: time: %0d: a = %x, b = %x, out = %x",
$time, MM_A, MM_B, out);
*/
alu64 u_alu64(out, MM_A, MM_B, imm, op);
endmodule
| 7.259416 |
module test_panel_adapter (
input clk,
input test_panel_select_n,
input [15:0] led_vals_in,
output [15:0] led_vals_out
);
synchronous_two_input_multiplexer #(
.WIDTH(16)
) mux (
.clk(clk),
.select(test_panel_select_n),
.in0({led_vals_in[7:0], led_vals_in[15:8]}),
.in1(led_vals_in),
.out(led_vals_out)
);
endmodule
| 6.999476 |
module f8_test (
in1,
in2,
out1,
out2,
io1,
io2
);
inout [1:0] io1;
inout [0:1] io2;
output [1:0] out1;
output [0:1] out2;
input [1:0] in1;
input [0:1] in2;
endmodule
| 7.583792 |
module f9_test (
q,
d,
clk,
reset
);
output reg q;
input d, clk, reset;
always @(posedge clk, negedge reset)
if (!reset) q <= 0;
else q <= d;
endmodule
| 6.818192 |
module f2_test #(
parameter v2kparam = 5
) (
in,
out,
io,
vin,
vout,
vio
);
input in;
output out;
inout io;
input [3:0] vin;
output [v2kparam:0] vout;
inout [0:3] vio;
parameter myparam = 10;
endmodule
| 6.635754 |
module test ();
import alu_ops::*;
`include "../lib/display_snippet.sv"
logic clk = 0;
cpu CPU (
1'b0,
clk
);
////////////////////////////////////////////////////////////////////////////////////////////////////
// TESTS ===========================================================================================
////////////////////////////////////////////////////////////////////////////////////////////////////
localparam MAX_PC = 100;
`DEFINE_CODE_VARS(MAX_PC)
//string_bits CODE [MAX_PC];
//string CODE_NUM [MAX_PC];
//string TEMP_STRING;
//string_bits CODE_TEXT [MAX_PC];
logic [47:0] data = 0;
int addr;
string rom1 = "roms/pattern1.rom";
string rom2 = "roms/pattern2.rom";
string rom3 = "roms/pattern3.rom";
string rom4 = "roms/pattern4.rom";
string rom5 = "roms/pattern5.rom";
string rom6 = "roms/pattern6.rom";
int n_file1;
int n_file2;
int n_file3;
int n_file4;
int n_file5;
int n_file6;
integer counter = 0;
integer pcAddress = 0;
initial begin
pcAddress = 0;
for (pcAddress = 0; pcAddress < 256; pcAddress++) begin
// make b count in opposite direction so it's distinctive in test
// aluop t a b cond
`INSTRUCTION_N(pcAddress, pcAddress, pcAddress, 7 - pcAddress, pcAddress, 0, `SET_FLAGS,
`CM_STD, `DIRECT, pcAddress, pcAddress);
$display("CODE : %-s", CODE_NUM[pcAddress]);
end
// address, target, devA, devB, operation, condition, flagControl, addressMode, absoluteAddress, immedValue
// `INSTRUCTION_S(pcAddress, marlo, not_used, immed, A, A, `NA_FLAGS, `REGISTER, 16'(pcAddress), 8'(pcAddress) ); pcAddress++;
// `INSTRUCTION_S(pcAddress, marhi, not_used, immed, B, C, `SET_FLAGS, `DIRECT , 16'(pcAddress), 8'(pcAddress) ); pcAddress++;
n_file1 = $fopen(rom1, "wb");
n_file2 = $fopen(rom2, "wb");
n_file3 = $fopen(rom3, "wb");
n_file4 = $fopen(rom4, "wb");
n_file5 = $fopen(rom5, "wb");
n_file6 = $fopen(rom6, "wb");
for (addr = 0; addr < pcAddress; addr++) begin
$display("CODE : %-s", CODE_NUM[addr]);
// little endian
data = `ROM(addr);
#1000 $fwrite(n_file1, "%c", data[7:0]);
$fwrite(n_file2, "%c", data[15:8]);
$fwrite(n_file3, "%c", data[23:16]);
$fwrite(n_file4, "%c", data[31:24]);
$fwrite(n_file5, "%c", data[39:32]);
$fwrite(n_file6, "%c", data[47:40]);
$display("written %d", addr, " = %8b %8b %8b %8b %8b %8b", data[47:40], data[39:32],
data[31:24], data[23:16], data[15:8], data[7:0],);
end
$fclose(n_file1);
$fclose(n_file2);
$fclose(n_file3);
$fclose(n_file4);
$fclose(n_file5);
$fclose(n_file6);
$display("DONE");
$finish();
end
endmodule
| 6.913895 |
module test_patterns (
input reset,
input clk,
input active_pixel,
input hsync_in,
input vsync_in,
output reg [7:0] r_out,
output reg [7:0] g_out,
output reg [7:0] b_out
);
reg [11:0] ramp = 12'd0;
always @(posedge clk) begin
if (reset) ramp <= 8'd0;
else if (hsync_in) ramp <= 8'd0;
else ramp <= ramp + 1;
end
always @(posedge clk) begin
r_out <= ramp[10:3];
g_out <= ramp[10:3];
b_out <= ramp[10:3];
end
endmodule
| 7.186961 |
module test_pattern_2 (
/*
just mux output between two values. not sure if this is useful.
versus real az.
*/
input clk, // master clk.
input [`NUM_BITS - 1 : 0] reg_direct, // synchronous on spi_clk.
input [`NUM_BITS - 1 : 0] reg_direct2, // synchronous on spi_clk.
output reg [`NUM_BITS-1:0] out //output reg -> driving wire. not working.
);
reg [31:0] counter = 0;
reg [1: 0] state = 0; // sig/zero . could have 4 mode representation. // is a single reg a single state
always @(posedge clk) begin
// default.
counter <= counter + 1;
if(counter == `CLK_FREQ / 10 ) // 10Hz.
begin
// reset counter - overide
counter <= 0;
// for the test-- spin the precharge switch - but keep mux constant - by repeating the patterns.
// for mux leakage - don't want to spin pre-charge, but do need the floated mux.
if (state) begin
state <= 0;
out <= reg_direct;
end else begin
state <= 1;
out <= reg_direct2;
end
end // counter
end // posedge clk
endmodule
| 6.982463 |
module test_pattern_previo_640x480 (
CLK100MHZ,
VGA_HS,
VGA_VS,
VGA_R,
VGA_G,
VGA_B
);
input CLK100MHZ;
output VGA_HS, VGA_VS;
output [3:0] VGA_R, VGA_G, VGA_B;
wire [9:0] vc_visible, hc_visible;
reg [1:0] counter_clk_vga, counter_clk_vga_next;
wire clk_vga;
always @(*) counter_clk_vga_next = counter_clk_vga + 2'd1;
always @(posedge CLK100MHZ) counter_clk_vga <= counter_clk_vga_next;
assign clk_vga = counter_clk_vga[1];
wire [2:0] rgb_out;
driver_vga_640x480 m_driver (
clk_vga,
VGA_HS,
VGA_VS,
hc_visible,
vc_visible
);
videotestpattern_640x480 m_pattern (
clk_vga,
hc_visible,
vc_visible,
rgb_out
);
assign VGA_R = {4{rgb_out[2]}};
assign VGA_G = {4{rgb_out[1]}};
assign VGA_B = {4{rgb_out[0]}};
endmodule
| 6.982463 |
module test_pattern_tb #() ();
localparam ADDRESS_WIDTH = 16;
localparam DATA_WIDTH = 8;
localparam DATA_BYTES = 1;
reg rst_i;
reg clk_i;
wire [ADDRESS_WIDTH-1:0] adr_o;
reg [ DATA_WIDTH-1:0] dat_i;
wire [ DATA_WIDTH-1:0] dat_o;
wire we_o;
wire [ DATA_BYTES-1:0] sel_o;
wire stb_o;
reg cyc_i;
wire cyc_o;
reg ack_i;
wire [ 2:0] cti_o;
wire clk;
wire rst;
test_pattern #() test_pattern_inst (
.rst_i(rst_i),
.clk_i(clk_i),
.adr_o(adr_o),
.dat_i(dat_i),
.dat_o(dat_o),
.we_o (we_o),
.sel_o(sel_o),
.stb_o(stb_o),
.cyc_i(cyc_i),
.cyc_o(cyc_o),
.ack_i(ack_i),
.cti_o(cti_o)
);
localparam CLOCK_PERIOD = 100; // Clock period in ps
localparam INITIAL_RESET_CYCLES = 10; // Number of cycles to reset when simulation starts
// Clock signal generator
initial clk_i = 1'b0;
always begin
#(CLOCK_PERIOD / 2);
clk_i = ~clk_i;
end
// Initial reset
initial begin
rst_i = 1'b1;
repeat (INITIAL_RESET_CYCLES) @(posedge clk_i);
rst_i = 1'b0;
end
assign clk = clk_i;
assign rst = rst_i;
// Test cycle
initial begin
end
initial begin
dat_i = 0;
cyc_i = 0;
end
always @(posedge clk) begin
ack_i <= cyc_o;
if (cyc_o) begin
dat_i <= adr_o + 8'h10;
end
end
endmodule
| 6.982463 |
module test_PC;
reg [7:0] valorEntradaPC;
reg EscrevePC, clock;
wire [7:0] valorPC;
initial begin
clock = 0;
EscrevePC = 1;
valorEntradaPC = 1;
#1 clock = 1;
#1 clock = 0;
valorEntradaPC = 2;
#1 clock = 1;
EscrevePC = 0;
#1 EscrevePC = 1;
#1 clock = 0;
#1 clock = 1;
end
initial begin
$monitor("Time=%0d valorEntradaPC=%d clock=%d EscrevePC=%d valorPC=%d", $time, valorEntradaPC,
clock, EscrevePC, valorPC);
end
ProgramCounter gate1 (
EscrevePC,
clock,
valorEntradaPC,
valorPC
);
endmodule
| 6.560331 |
module test_pcie_us_axi_master_wr_128;
// Parameters
parameter AXIS_PCIE_DATA_WIDTH = 128;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32);
parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_ADDR_WIDTH = 64;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8);
parameter AXI_ID_WIDTH = 8;
parameter AXI_MAX_BURST_LEN = 256;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0;
reg s_axis_cq_tvalid = 0;
reg s_axis_cq_tlast = 0;
reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
reg m_axi_awready = 0;
reg m_axi_wready = 0;
reg [AXI_ID_WIDTH-1:0] m_axi_bid = 0;
reg [1:0] m_axi_bresp = 0;
reg m_axi_bvalid = 0;
// Outputs
wire s_axis_cq_tready;
wire [AXI_ID_WIDTH-1:0] m_axi_awid;
wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr;
wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst;
wire m_axi_awlock;
wire [3:0] m_axi_awcache;
wire [2:0] m_axi_awprot;
wire m_axi_awvalid;
wire [AXI_DATA_WIDTH-1:0] m_axi_wdata;
wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
wire m_axi_bready;
wire status_error_uncor;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_cq_tdata, s_axis_cq_tkeep, s_axis_cq_tvalid,
s_axis_cq_tlast, s_axis_cq_tuser, m_axi_awready, m_axi_wready, m_axi_bid,
m_axi_bresp, m_axi_bvalid);
$to_myhdl(s_axis_cq_tready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awvalid, m_axi_wdata, m_axi_wstrb,
m_axi_wlast, m_axi_wvalid, m_axi_bready, status_error_uncor);
// dump file
$dumpfile("test_pcie_us_axi_master_wr_128.lxt");
$dumpvars(0, test_pcie_us_axi_master_wr_128);
end
pcie_us_axi_master_wr #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.status_error_uncor(status_error_uncor)
);
endmodule
| 7.787107 |
module test_pcie_us_axi_master_wr_256;
// Parameters
parameter AXIS_PCIE_DATA_WIDTH = 256;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32);
parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_ADDR_WIDTH = 64;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8);
parameter AXI_ID_WIDTH = 8;
parameter AXI_MAX_BURST_LEN = 256;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0;
reg s_axis_cq_tvalid = 0;
reg s_axis_cq_tlast = 0;
reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
reg m_axi_awready = 0;
reg m_axi_wready = 0;
reg [AXI_ID_WIDTH-1:0] m_axi_bid = 0;
reg [1:0] m_axi_bresp = 0;
reg m_axi_bvalid = 0;
// Outputs
wire s_axis_cq_tready;
wire [AXI_ID_WIDTH-1:0] m_axi_awid;
wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr;
wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst;
wire m_axi_awlock;
wire [3:0] m_axi_awcache;
wire [2:0] m_axi_awprot;
wire m_axi_awvalid;
wire [AXI_DATA_WIDTH-1:0] m_axi_wdata;
wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
wire m_axi_bready;
wire status_error_uncor;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_cq_tdata, s_axis_cq_tkeep, s_axis_cq_tvalid,
s_axis_cq_tlast, s_axis_cq_tuser, m_axi_awready, m_axi_wready, m_axi_bid,
m_axi_bresp, m_axi_bvalid);
$to_myhdl(s_axis_cq_tready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awvalid, m_axi_wdata, m_axi_wstrb,
m_axi_wlast, m_axi_wvalid, m_axi_bready, status_error_uncor);
// dump file
$dumpfile("test_pcie_us_axi_master_wr_256.lxt");
$dumpvars(0, test_pcie_us_axi_master_wr_256);
end
pcie_us_axi_master_wr #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.status_error_uncor(status_error_uncor)
);
endmodule
| 7.787107 |
module test_pcie_us_axi_master_wr_512;
// Parameters
parameter AXIS_PCIE_DATA_WIDTH = 512;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32);
parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_ADDR_WIDTH = 64;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8);
parameter AXI_ID_WIDTH = 8;
parameter AXI_MAX_BURST_LEN = 256;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0;
reg s_axis_cq_tvalid = 0;
reg s_axis_cq_tlast = 0;
reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
reg m_axi_awready = 0;
reg m_axi_wready = 0;
reg [AXI_ID_WIDTH-1:0] m_axi_bid = 0;
reg [1:0] m_axi_bresp = 0;
reg m_axi_bvalid = 0;
// Outputs
wire s_axis_cq_tready;
wire [AXI_ID_WIDTH-1:0] m_axi_awid;
wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr;
wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst;
wire m_axi_awlock;
wire [3:0] m_axi_awcache;
wire [2:0] m_axi_awprot;
wire m_axi_awvalid;
wire [AXI_DATA_WIDTH-1:0] m_axi_wdata;
wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
wire m_axi_bready;
wire status_error_uncor;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_cq_tdata, s_axis_cq_tkeep, s_axis_cq_tvalid,
s_axis_cq_tlast, s_axis_cq_tuser, m_axi_awready, m_axi_wready, m_axi_bid,
m_axi_bresp, m_axi_bvalid);
$to_myhdl(s_axis_cq_tready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awvalid, m_axi_wdata, m_axi_wstrb,
m_axi_wlast, m_axi_wvalid, m_axi_bready, status_error_uncor);
// dump file
$dumpfile("test_pcie_us_axi_master_wr_512.lxt");
$dumpvars(0, test_pcie_us_axi_master_wr_512);
end
pcie_us_axi_master_wr #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.status_error_uncor(status_error_uncor)
);
endmodule
| 7.787107 |
module test_pcie_us_axi_master_wr_64;
// Parameters
parameter AXIS_PCIE_DATA_WIDTH = 64;
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH / 32);
parameter AXIS_PCIE_CQ_USER_WIDTH = 85;
parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
parameter AXI_ADDR_WIDTH = 64;
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH / 8);
parameter AXI_ID_WIDTH = 8;
parameter AXI_MAX_BURST_LEN = 256;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0;
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0;
reg s_axis_cq_tvalid = 0;
reg s_axis_cq_tlast = 0;
reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
reg m_axi_awready = 0;
reg m_axi_wready = 0;
reg [AXI_ID_WIDTH-1:0] m_axi_bid = 0;
reg [1:0] m_axi_bresp = 0;
reg m_axi_bvalid = 0;
// Outputs
wire s_axis_cq_tready;
wire [AXI_ID_WIDTH-1:0] m_axi_awid;
wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr;
wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst;
wire m_axi_awlock;
wire [3:0] m_axi_awcache;
wire [2:0] m_axi_awprot;
wire m_axi_awvalid;
wire [AXI_DATA_WIDTH-1:0] m_axi_wdata;
wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
wire m_axi_bready;
wire status_error_uncor;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_cq_tdata, s_axis_cq_tkeep, s_axis_cq_tvalid,
s_axis_cq_tlast, s_axis_cq_tuser, m_axi_awready, m_axi_wready, m_axi_bid,
m_axi_bresp, m_axi_bvalid);
$to_myhdl(s_axis_cq_tready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst,
m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awvalid, m_axi_wdata, m_axi_wstrb,
m_axi_wlast, m_axi_wvalid, m_axi_bready, status_error_uncor);
// dump file
$dumpfile("test_pcie_us_axi_master_wr_64.lxt");
$dumpvars(0, test_pcie_us_axi_master_wr_64);
end
pcie_us_axi_master_wr #(
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_MAX_BURST_LEN)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_cq_tdata(s_axis_cq_tdata),
.s_axis_cq_tkeep(s_axis_cq_tkeep),
.s_axis_cq_tvalid(s_axis_cq_tvalid),
.s_axis_cq_tready(s_axis_cq_tready),
.s_axis_cq_tlast(s_axis_cq_tlast),
.s_axis_cq_tuser(s_axis_cq_tuser),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.status_error_uncor(status_error_uncor)
);
endmodule
| 7.787107 |
module top;
wire clock, reset;
clockgen clkg (
.clk(clock),
.rst(reset)
);
design_wrapper dut (
.clock(clock),
.reset(reset)
);
`ifdef VCD
initial begin
$dumpfile(`VCD_FILE);
$dumpvars;
end
`endif
`include "tracegen.v"
endmodule
| 6.535004 |
module test_pet2001ps2_key;
// Inputs
reg [3:0] keyrow;
reg ps2_clk;
reg ps2_data;
reg clk;
reg reset;
// Outputs
wire [7:0] keyin;
// Instantiate the Unit Under Test (UUT)
pet2001ps2_key
uut (
.keyin(keyin),
.keyrow(keyrow),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.clk(clk),
.reset(reset)
);
// Way fast PS/2 rate.
parameter PS2_CLK_RATE = 20;
task putbit;
input bit;
begin
ps2_data <= #1 bit;
repeat (PS2_CLK_RATE) @(posedge clk);
ps2_clk <= #1 0;
repeat (PS2_CLK_RATE * 2) @(posedge clk);
ps2_clk <= #1 1;
repeat (PS2_CLK_RATE) @(posedge clk);
end
endtask
task putbyte;
input [7:0] b;
integer i;
reg parity;
begin
parity = ~^{b};
putbit(0);
for (i=0; i<8; i=i+1)
putbit(b[i]);
putbit(parity);
putbit(1);
repeat (PS2_CLK_RATE * 2) @(posedge clk);
end
endtask // putbyte
reg [7:0] expctrows[15:0];
task checkrows;
integer i;
begin
for (i=0; i<16; i=i+1) begin
keyrow <= 4'd0 + i;
@(posedge clk);
$display("[%t] row: %b keyin: %b", $time, keyrow, keyin);
if (keyin !== expctrows[i]) begin
$display("[%t] checkrows: INCORRECT row expecting %b",
$time, expctrows[i]);
$stop;
end
end
$display("------------------");
end
endtask // checkrows
initial begin:test0
integer i;
// Initialize Inputs
keyrow = 0;
ps2_clk = 1;
ps2_data = 0;
clk = 0;
reset = 1;
// Intialize check row data
for (i=0; i<16; i=i+1)
expctrows[i] = 8'hff;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
repeat (10) @(posedge clk);
reset <= 0;
// Let reset sequence happen.
repeat (20) @(posedge clk);
$display("Initial row state:");
checkrows();
putbyte(8'h1A); // press Z
$display("Press Z");
expctrows[7] = 8'hfe;
checkrows();
putbyte(8'hF0);
putbyte(8'h1A); // release Z
expctrows[7] = 8'hff;
$display("Release Z");
checkrows();
putbyte(8'h1A); // press Z
expctrows[7] = 8'hfe;
putbyte(8'h2C); // press T
expctrows[3] = 8'hfb;
$display("Press Z and T");
checkrows();
putbyte(8'h2C); // press T again
putbyte(8'hF0); // release T
putbyte(8'h2C);
expctrows[3] = 8'hff;
$display("Release T (still Z?)");
checkrows();
putbyte(8'hF0);
putbyte(8'h1A); // release Z
expctrows[7] = 8'hff;
$display("Release Z");
checkrows();
$display("[%t] SUCCESS!", $time);
$finish;
end // initial begin
always #5.0 clk = ~clk;
endmodule
| 7.003772 |
module test_pet2001uart_keys;
reg [3:0] keyrow;
wire [7:0] keyin;
reg [7:0] uart_data;
reg uart_strobe;
reg clk;
reg reset;
initial begin
keyrow = 4'hf;
uart_data = 8'd0;
uart_strobe = 1'b0;
clk = 1'b0;
reset = 1'b1;
end
always #10.0 clk = ~clk; // 50Mhz
// Wait a few clocks, release reset, a few more clocks, strobe '^D'.
initial begin
repeat (20) @(posedge clk);
reset <= 1'b0;
repeat (100) @(posedge clk);
uart_data <= 8'h0d;
uart_strobe <= 1'b1;
@(posedge clk);
uart_strobe <= 1'b0;
end
// Scan keyrows much like a PET would.
always @(posedge clk) begin
if (keyrow == 4'd9) keyrow <= 4'd0;
else keyrow <= keyrow + 1'b1;
repeat (20) @(posedge clk);
end
// DUT
pet2001uart_keys pet2001uart_keys_0 (
.keyrow(keyrow),
.keyin(keyin),
.uart_data(uart_data),
.uart_strobe(uart_strobe),
.clk(clk),
.reset(reset)
);
endmodule
| 6.691541 |
module for Pet2001_Arty and Pet2001Real_Arty.
//
module test_Pet2001_Arty;
reg [2:0] SW;
reg BTN;
wire [3:0] VGA_R;
wire [3:0] VGA_G;
wire [3:0] VGA_B;
wire VGA_HSYNC;
wire VGA_VSYNC;
wire AUDIO;
wire CASS_WR;
reg CASS_RD;
reg PS2_CLK;
reg PS2_DATA;
wire LED;
reg CLK100;
initial begin
SW = 3'b000;
BTN = 1'b0;
PS2_CLK = 1'b1;
PS2_DATA = 1'b1;
CASS_RD = 1'b1;
CLK100 = 1'b0;
end
always #5.0 CLK100 = ~CLK100; // outboard clock 100Mhz
// DUT
Pet2001_Arty dut(.SW(SW),
.BTN(BTN),
.LED(LED),
.AUDIO(AUDIO),
.CASS_WR(CASS_WR),
.CASS_RD(CASS_RD),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HSYNC(VGA_HSYNC),
.VGA_VSYNC(VGA_VSYNC),
.PS2_CLK(PS2_CLK),
.PS2_DATA(PS2_DATA),
.CLK(CLK100)
);
endmodule
| 7.92237 |
module test_PE_0 ();
parameter cycle = 10;
reg clk;
reg rst;
wire [31:0] PE_0_dout_N;
wire [31:0] PE_0_dout_S;
wire [31:0] PE_0_dout_W;
wire [31:0] PE_0_dout_E;
reg init, run;
reg [27:0] PE_inst;
reg [31:0] din_N_i;
reg [31:0] din_S_i;
reg [31:0] din_W_i;
reg [31:0] din_E_i;
//---------------end-----------------//
always #(cycle / 2) clk = ~clk;
integer i;
initial begin
clk = 1'b1;
rst = 1'b1;
#10 rst = 1'b0;
init = 'b1;
PE_inst = 'h965b70;
#20 init = 'b0;
run = 'b1;
#10 run = 'b0;
end
reg init_i;
reg [27:0] PE_inst_i;
reg run_i;
always @(posedge clk) begin
if (rst) begin
din_N_i <= 'd3;
din_W_i <= 'd4;
din_S_i <= 'd5;
din_E_i <= 'd6;
end else begin
din_N_i <= din_N_i + 'b1;
din_W_i <= din_W_i + 'b1;
din_S_i <= din_S_i + 'b1;
din_E_i <= din_E_i + 'b1;
end
end
always @(posedge clk) begin
init_i <= init;
run_i <= run;
PE_inst_i = PE_inst;
end
PE_D pe_0 (
.clk (clk),
.rst (rst),
.PE_inst(PE_inst_i),
.init (init_i),
.run (run_i),
.din_N (din_N_i), //上
.din_W (din_W_i), //下
.din_S (din_S_i), //左
.din_E (din_E_i),
.dout_N (PE_0_dout_N),
.dout_S (PE_0_dout_S),
.dout_W (PE_0_dout_W),
.dout_E (PE_0_dout_E)
);
endmodule
| 6.671543 |
module test_pid;
localparam RATE_BIT_WIDTH = 36;
localparam VELOCITY_BIT_WIDTH = 36;
localparam ROTATION_BIT_WIDTH = 36;
// rates represented in 2's complement fixed point
wire [RATE_BIT_WIDTH-1:0] yaw_rate_out;
wire [RATE_BIT_WIDTH-1:0] roll_rate_out;
wire [RATE_BIT_WIDTH-1:0] pitch_rate_out;
// rates represented in 2's complement fixed point
wire [RATE_BIT_WIDTH-1:0] yaw_rate_in;
wire [RATE_BIT_WIDTH-1:0] roll_rate_in;
wire [RATE_BIT_WIDTH-1:0] pitch_rate_in;
// velocities represented in 2's complement fixed point
wire [VELOCITY_BIT_WIDTH-1:0] x_velocity;
wire [VELOCITY_BIT_WIDTH-1:0] y_velocity;
wire [VELOCITY_BIT_WIDTH-1:0] z_velocity;
// rotations represented in 2's complement fixed point
wire [ROTATION_BIT_WIDTH-1:0] x_rotation;
wire [ROTATION_BIT_WIDTH-1:0] y_rotation;
wire [ROTATION_BIT_WIDTH-1:0] z_rotation;
wire clk;
// line up the parameters here to the ones internal to the receiver module
pid #(RATE_BIT_WIDTH, VELOCITY_BIT_WIDTH, ROTATION_BIT_WIDTH) DUT (
.yaw_rate_out(yaw_rate_out),
.roll_rate_out(roll_rate_out),
.pitch_rate_out(pitch_rate_out),
.yaw_rate_in(yaw_rate_in),
.roll_rate_in(roll_rate_in),
.pitch_rate_in(pitch_rate_in),
.x_velocity(x_velocity),
.y_velocity(y_velocity),
.z_velocity(z_velocity),
.x_rotation(x_rotation),
.y_rotation(y_rotation),
.z_rotation(z_rotation),
.sys_clk(sys_clk)
);
initial begin
$display("%m successful");
end
endmodule
| 8.032064 |
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