code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_deserializer;
reg reset = 0;
reg enable = 1;
wire complete;
reg in = 0; //serialized input
reg [7:0] framesize = 11; //serialized input
wire [135:0] out; //deserialized data
reg [135:0] input_values = 136'b1010101010101011010100100100101010100100101010101101010101010100101011010010101101101111010111010111010101010101101101010101101101010100; // test input data
reg [5:0] counter = 0;
initial begin
$display("\n----------------------- Deserializer test -------------------------\n");
$dumpfile("tests/vcd/test_deserializer.vcd");
$dumpvars(0, test_deserializer);
#2 reset = 1;
#2 reset = 0;
#94 enable = 0; //out should remain the same for 2 cycles
$display("Enabled\n");
#26 reset = 1;
#2 $finish;
end
reg clk = 0;
always #1 clk = !clk;
always #2 counter = counter + 1; //next item on array
always @(posedge clk) begin
in <= input_values[counter];
end
always @(posedge complete) begin
$display("Disabled\n");
enable = 0;
end
deserializer des (
.clk(clk),
.reset(reset),
.in(in),
.out(out),
.enable(enable),
.complete(complete),
.framesize(framesize)
);
initial $monitor("At time %t: %b, out: %b complete: %b", $time, in, out, complete);
endmodule
| 6.908859 |
module Test_DET_FSK_tf;
// Inputs
reg clk;
reg st;
reg [7:0] dat;
reg [7:0] Mamp;
// Outputs
wire [11:0] FSK_SH;
wire S;
wire ce_SIN;
wire en_tx;
wire TX_bit;
wire ce_tx_bit;
wire [11:0] DFSK_SH;
wire OCD;
wire [11:0] AMP;
wire [12:0] bf_SH;
wire FSK_tact;
wire [6:0] cb_tact;
wire FSK_start;
wire FSK_en_rx;
wire [3:0] cb_rx_bit;
wire FSK_res;
wire [10:0] F1_AMP;
wire [10:0] F2_AMP;
wire RX_bit;
wire ok_rx_bit;
// Instantiate the Unit Under Test (UUT)
Test_DET_FSK uut (
.clk(clk),
.FSK_SH(FSK_SH),
.st(st),
.S(S),
.dat(dat),
.ce_SIN(ce_SIN),
.Mamp(Mamp),
.en_tx(en_tx),
.TX_bit(TX_bit),
.ce_tx_bit(ce_tx_bit),
.DFSK_SH(DFSK_SH),
.OCD(OCD),
.AMP(AMP),
.bf_SH(bf_SH),
.FSK_tact(FSK_tact),
.cb_tact(cb_tact),
.FSK_start(FSK_start),
.FSK_en_rx(FSK_en_rx),
.cb_rx_bit(cb_rx_bit),
.FSK_res(FSK_res),
.F1_AMP(F1_AMP),
.F2_AMP(F2_AMP),
.RX_bit(RX_bit),
.ok_rx_bit(ok_rx_bit)
);
always begin
clk = 0;
#10;
clk = 1;
#10;
end
initial begin
st = 0;
dat = 0;
Mamp = 0; //
#1000000;
st = 1;
dat = 8'h0F;
Mamp = 16; //Mamp=1,2,128
#20;
st = 0;
end
endmodule
| 7.017777 |
module DFFI (
input I,
input CLK,
output O
);
wire GP_DFFI_inst0_nQ;
GP_DFFI GP_DFFI_inst0 (
.D (I),
.CLK(CLK),
.nQ (GP_DFFI_inst0_nQ)
);
assign O = GP_DFFI_inst0_nQ;
endmodule
| 6.611138 |
module test_dff_sync;
reg d, clk, rst;
wire q;
always @(posedge clk) begin
$monitor("d = %b, clk = %b, rst = %b, q = %b", d, clk, rst, q);
end
initial begin
forever begin
clk = 0;
#5 clk = 1;
#5 clk = 0;
end
end
initial begin
d = 0;
rst = 1;
#4 d = 1;
rst = 0;
#50 d = 1;
rst = 1;
#20 d = 0;
rst = 0;
end
dff_sync_clear dff (
d,
rst,
clk,
q
);
endmodule
| 6.584259 |
module Test_DFTn (
output wire S, //
input clk,
output wire [11:0] SIN, //
input st,
output wire ce_tact, // DFT
input [7:0] M,
output wire ce_sd, //
output wire ce_SIN, //
output wire ce_bit, //
output wire [10:0] modY, //
output wire [6:0] k, // , k=|k*n|modNP
output wire D, //
output wire [6:0] n
); // ,
//-- ( )
TIMER DD1 (
.clk(clk),
.ce(ce_tact), //( ce_tact 100*Fbit=100*2200Hz=220kHz)
.st(st),
.ce_bit(ce_bit)
); //( ce_bit Fbit=2200Hz)
//--
//--M - ( M=128 Amp=2000)
//--D - ( D=0 Fsin=2200Hz, D=1 Fsin=1200Hz)
Gen_FSK_SIN DD2 (
.clk(clk),
.S(S), //S=1 sin>0
.D(D),
.SIN(SIN),
.Mamp(M),
.ce_SIN(ce_SIN), //
.ce_sd(ce_sd)
); //
//-- n-
DFTn DD3 (
.X(SIN),
.modY(modY),
.ce(ce_tact),
.k(k),
.clk(clk),
.st(st),
.ce_bit(ce_bit),
.n(n)
);
//-- D=0,1 n=1,2,...,99
Gen_Dn DD4 (
.st (ce_bit),
.D (D),
.clk(clk),
.n (n)
);
endmodule
| 7.05426 |
module test_direct;
reg CLK;
reg [255:0] memData;
reg [31:0] nextAddr;
wire [7:0] dataReturn;
wire hit;
wire [255:0] toMemData;
GT_direct_map map (
.CLK(CLK),
.memData(memData),
.nextAddr(nextAddr),
.dataReturn(dataReturn),
.hit(hit),
.toMemData(toMemData)
);
initial begin
$display("Beginning direct test");
CLK = 0;
nextAddr = 32'h00100001;
$display("Addr\thit\tdata\ttoVictimCache");
$monitor("%h\t%h\t%h\t%h", nextAddr, hit, dataReturn, toMemData);
memData = 256'hFFFF_EEEE_DDDD_CCCC_BBBB_AAAA_9999_8888_7777_6666_5555_4444_3333_2222_1111_0000;
$display("Writing Data");
#2 nextAddr = 32'h00200002;
#2 nextAddr = 32'h00300003;
$display("Overwrite");
#2 nextAddr = 32'h023000F3;
#2 $display("Reading Data");
memData = 0;
#2 nextAddr = 32'h00300003;
#2 nextAddr = 32'h00200002;
#50 $stop;
end
always begin
#1 CLK = ~CLK;
end
endmodule
| 6.647316 |
modules for testbench
// notes :
//
// Copyright Illinois Institute of Technology
//
// Top level stimulus module
module stimulus;
reg [7:0] op1, op2;
reg clock, state0;
reg Clk;
wire [3:0] qj, qjn;
wire [10:0] Sum1, Carry1;
wire [10:0] Sum2, Carry2;
integer handle3;
integer desc3;
divide16 div1 (qj, qjn, Sum1, Carry1, Sum2, Carry2,
op1, op2, clock, state0);
initial
begin
Clk = 1'b1;
forever #5 Clk = ~Clk;
end
initial
begin
handle3 = $fopen("divide16.out");
#100 $finish;
end
always
begin
desc3 = handle3;
#5 $fdisplay(desc3, "%b | %b %b %b || %h %h %h %h %h %h",
clock, op1, op2, state0,
Sum1, Carry1, Sum2, Carry2, qj, qjn);
end
initial
begin
#0 clock = 1'b0;
#0 state0 = 1'b1;
#0 op1 = 8'b10101111;
#0 op2 = 8'b11000101;
//#0 op1 = 8'b10000000;
//#0 op2 = 8'b10000000;
//#0 op1 = 8'b10010011;
//#0 op2 = 8'b11000000;
#20 clock = 1'b1;
#20 clock = 1'b0;
#20 state0 = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
end
endmodule
| 6.862012 |
modules for testbench
// notes :
//
// Copyright Illinois Institute of Technology
//
// Top level stimulus module
module stimulus;
reg [7:0] N;
reg [7:0] D;
reg state0, clock;
reg Clk;
wire [9:0] w;
wire [1:0] q;
integer handle3;
integer desc3;
divide2 dut1 (w, q, D, N, state0, clock);
initial
begin
Clk = 1'd1;
forever #5 Clk = ~Clk;
end
initial
begin
handle3 = $fopen("divide2.out");
#100 $finish;
end
always
begin
desc3 = handle3;
#5 $fdisplay(desc3, "%h %h %b %b || %h %h", N, D, state0, clock,
w, q);
end
initial
begin
#0 N = 8'h9F;
#0 D = 8'hC5;
#0 clock = 1'b0;
#0 state0 = 1'b1;
#10 clock = 1'b1;
#10 clock = 1'b0;
#0 state0 = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
#10 clock = 1'b1;
#10 clock = 1'b0;
end
endmodule
| 6.862012 |
module: div_steps
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_div_steps;
// Inputs
reg [31:0] dividend;
reg [31:0] divisor;
reg clk;
reg clk_en;
reg divide;
reg reset;
// Outputs
wire [63:0] quot;
wire done;
// Instantiate the Unit Under Test (UUT)
div_steps uut (
.dividend_i(dividend),
.divisor_i(divisor),
.quotient_o(quot),
.clk_i(clk),
.clk_en_i(clk_en),
.rst_i(reset),
.divide_i(divide),
.done_o(done)
);
initial begin
// Initialize Inputs
dividend = 0;
divisor = 0;
clk = 0;
clk_en = 1;
divide = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 1;
#100;
reset = 0;
dividend = 2;
divisor = 1;
divide = 1;
#2000;
dividend = 200;
divisor = 3;
divide = 1;
#2000;
dividend = 32'h60002000;
divisor = 32'h56000000;
divide = 1;
#2000;
dividend = 32'h40002000;
divisor = 13;
divide = 1;
#2000;
dividend = 32'hDfff1234;
divisor = 3;
divide = 1;
#2000;
dividend = 3;
divisor = 32'hdfff1234;
divide = 1;
#2000;
// Add stimulus here
end
initial begin
#100;
forever
begin
clk = 1;
#5;
clk = 0;
if (divide == 1)
divide = 0;
#5;
end;
end
endmodule
| 7.153916 |
module testfixture;
//`define direction_matrix "../dat/compare.dat"
//`define H_matrix "../dat/H.dat"
`define sequence "../dat/BinaryInput.dat"
`define data_size "../dat/data_size.dat"
reg clk = 0;
reg rst_n;
reg [`BP_WIDTH-1:0] S;
reg [`BP_WIDTH-1:0] T;
reg s_update;
wire [`CALC_WIDTH-1:0] max_o;
wire busy;
reg valid;
reg ack;
reg new_seq;
wire array_num;
wire tb_valid;
wire [`N*`DIRECTION_WIDTH-1:0] row_k0;
wire [`N*`DIRECTION_WIDTH-1:0] row_k1;
wire [`ADDRESS_WIDTH-1:0] tb_x;
wire [`ADDRESS_WIDTH-1:0] tb_y;
reg tb_busy;
reg [`MEM_AMOUNT_WIDTH-1:0] mem_block_num;
reg [`ADDRESS_WIDTH-1:0] row_num;
reg [`log_N-1:0] PE_end;
reg [`SEQ_MAX_LEN*2-1:0] seq[0:7];
reg [11:0] seq_len[0:7]; //sequence length
integer err_cnt;
integer k_DP;
integer i_DP;
integer j_DP;
integer s_size;
integer t_size;
integer iter;
integer cal;
`ifdef SDF
initial $sdf_annotate(`SDFFILE, top);
`endif
initial begin
$fsdbDumpfile("DP.fsdb");
$fsdbDumpvars;
$fsdbDumpMDA;
end
initial begin
$timeformat(-9, 1, " ns", 9); //Display time in nanoseconds
$readmemb(`sequence, seq);
$readmemh(`data_size, seq_len);
$display("--------------------------- [ Simulation Starts !! ] ---------------------------");
end
always #(`cycle / 2) clk = ~clk;
//systolic systolic( .clk(clk), .reset_i(rst_n), .S(S), .T(T), .s_update(s_update), .max_o(), .busy(busy), .ack(ack), .valid(valid));
DP DP (
.clk_i(clk),
.reset_i(rst_n),
.S(S),
.T(T),
.s_update(s_update),
.max_o(),
.busy(busy),
.ack(ack),
.valid(valid),
.new_seq(new_seq),
.PE_end(PE_end),
.tb_valid(tb_valid),
.array_num(array_num),
.tb_busy(tb_busy),
.mem_block_num(mem_block_num),
.row_num(row_num),
.row_k0(row_k0),
.row_k1(row_k1),
.tb_x(tb_x),
.tb_y(tb_y)
);
initial begin
rst_n = 1;
err_cnt = 0;
s_update = 0;
ack_DP = 0;
valid = 0;
new_seq = 0;
/*for tb testing only*/
tb_busy = 0;
mem_block_num = 0;
row_num = 3;
/*for tb testing only*/
#`cycle;
rst_n = 0;
#(`cycle * 2);
rst_n = 1;
#(`cycle / 4)
for (
k_DP = 0; k_DP < 8; k_DP = k_DP + 2
) // how much pair of sequence alignment
begin
@(negedge clk);
s_size = seq_len[k_DP];
t_size = seq_len[k_DP+1];
cal = seq_len[k_DP];
new_seq = 1;
#`cycle;
new_seq = 0;
if(s_size > `N) //need to be calculated iteratively
begin
iter = s_size / `N;
if (s_size % `N != 0) iter = iter + 1;
end
ack = 1;
for (j_DP = 0; j_DP < iter; j_DP = j_DP + 1) begin
@(negedge clk);
if (cal <= `N) PE_end = cal - 1;
else PE_end = `N - 1;
for (
i_DP = (`N - 1) * 2; i_DP >= 0; i_DP = i_DP - 2
) //S signal serial in
begin
#`cycle;
S = seq[k_DP][(j_DP*2*`N+i_DP)+:2];
end
cal = cal - `N;
ack = 0;
s_update = 1;
#`cycle;
s_update = 0;
ack = 1;
#`cycle;
for (
i_DP = 0; i_DP < t_size * 2; i_DP = i_DP + 2
) //T signal serial in
begin
T = seq[k_DP+1][i_DP+:2];
valid = 1;
#`cycle;
end
valid = 0;
wait (busy == 0);
end
end
$finish;
end
initial begin
#`terminate_cycle;
$display(
"================================================================================================================");
$display("(/`n`)/ ~# There is something wrong with your code!!");
$display("Time out!! The simulation didn't finish after %d cycles!!, Please check it!!!",
`terminate_cycle);
$display(
"================================================================================================================");
$finish;
end
endmodule
| 6.999147 |
module test_dqs (
input rst, // reset
input refclk, // 200MHz/300MHz for delay calibration
input clk_in,
input set,
input ld_dly_data,
input ld_dly_tri,
input [7:0] dly_data,
input [3:0] data_in,
input [3:0] tri_in,
inout dqs,
inout ndqs,
output dqs_received,
output dly_ready,
// input dqs_tri_a,
output dqs_tri
);
wire refclk_b = refclk; // use buffer
wire clk, clk_div;
//wire dqs_data,dqs_tri; // after odelay
wire dqs_data; // after odelay
wire pre_dqs_data, pre_dqs_tri; // before odelay
BUFR #(
.BUFR_DIVIDE("2")
) clk_div_i (
.I (clk_in),
.O (clk_div),
.CLR(rst),
.CE (1'b1)
);
BUFR #(
.BUFR_DIVIDE("BYPASS")
) clk_i (
.I (clk_in),
.O (clk),
.CLR(1'b0),
.CE (1'b1)
);
oserdes_mem oserdes_dqs_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(data_in), // parallel data in
.tin(tri_in), // parallel tri-state in
.dout_dly(), // data out to be connected to odelay input
.dout_iob(pre_dqs_data), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
.tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
);
idelay_ctrl #(
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(refclk_b),
.rst(rst),
.rdy(dly_ready)
);
odelay_fine_pipe #(
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i (
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
odelay_fine_pipe #(
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_tri_dly_i (
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_tri),
.delay(dly_data),
.data_in(pre_dqs_tri),
.data_out(dqs_tri)
);
//wire dqs_tri_a;
//(* keep = "true" *) BUF buf0_i(.O(dqs_tri_a), .I(dqs_tri));
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O (dqs_received),
.IO (dqs),
.IOB(ndqs),
.I (dqs_data),
// .T(dqs_tri_a));
.T (1'b0)
);
endmodule
| 6.983332 |
module test_dqs01 (
input [1:0] dqs_data,
inout [1:0] dqs,
inout [1:0] ndqs,
output [1:0] dqs_received,
input [1:0] dqs_tri
);
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i0 (
.O (dqs_received[0]),
.IO (dqs[0]),
.IOB(ndqs[0]),
.I (dqs_data[0]),
.T (dqs_tri[0])
);
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i1 (
.O (dqs_received[1]),
.IO (dqs[1]),
.IOB(ndqs[1]),
.I (dqs_data[1]),
.T (dqs_tri[1])
);
endmodule
| 6.804808 |
module test_dqs02 (
input rst, // reset
input refclk, // 200MHz/300MHz for delay calibration
input clk_in,
// input set,
// input ld_dly_data,
// input ld_dly_tri,
// input [7:0] dly_data,
input [3:0] data_in,
// input [3:0] tri_in,
inout dqs,
// inout ndqs,
output dqs_received,
output dly_ready
// input dqs_tri_a,
// output dqs_tri
// output dqs_data
);
wire refclk_b = refclk; // use buffer
wire clk, clk_div;
//wire dqs_data,dqs_tri; // after odelay
//wire dqs_data; // after odelay
//wire pre_dqs_data,pre_dqs_tri; // before odelay
wire dqs_data;
BUFR #(
.BUFR_DIVIDE("2")
) clk_div_i (
.I (clk_in),
.O (clk_div),
.CLR(rst),
.CE (1'b1)
);
BUFR #(
.BUFR_DIVIDE("BYPASS")
) clk_i (
.I (clk_in),
.O (clk),
.CLR(1'b0),
.CE (1'b1)
);
oserdes_mem oserdes_dqs_i (
.clk(clk), // serial output clock
.clk_div(clk_div), // oclk divided by 2, front aligned
.rst(rst), // reset
.din(data_in), // parallel data in
// .tin(tri_in), // parallel tri-state in
.tin(), // parallel tri-state in
.dout_dly(), //pre_dqs_data), // data out to be connected to odelay input
.dout_iob(dqs_data), // data out to be connected directly to the output buffer
.tout_dly(), // tristate out to be connected to odelay input
// .tout_iob(pre_dqs_tri) // tristate out to be connected directly to the tristate control of the output buffer
.tout_iob() // tristate out to be connected directly to the tristate control of the output buffer
);
idelay_ctrl #(
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(refclk_b),
.rst(rst),
.rdy(dly_ready)
);
/*
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
*/
/*
odelay_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_data_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_data),
.delay(dly_data[7:3]),
.data_in(pre_dqs_data),
.data_out(dqs_data)
);
*/
/*
odelay_fine_pipe # (
.IODELAY_GRP("IODELAY_MEMORY"),
.DELAY_VALUE(0),
.REFCLK_FREQUENCY(300.0),
.HIGH_PERFORMANCE_MODE("FALSE")
) dqs_tri_dly_i(
.clk(clk_div),
.rst(rst),
.set(set),
.ld(ld_dly_tri),
.delay(dly_data),
.data_in(pre_dqs_tri),
.data_out(dqs_tri)
);
*/
//wire dqs_tri_a;
//(* keep = "true" *) BUF buf0_i(.O(dqs_tri_a), .I(dqs_tri));
/*
IOBUFDS #(
.DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O(dqs_received),
.IO(dqs),
.IOB(ndqs),
.I(dqs_data),
// .T(dqs_tri));
.T());
*/
IOBUF #(
// .DQS_BIAS("FALSE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
) iobufs_dqs_i (
.O (dqs_received),
.IO(dqs),
.I (dqs_data),
// .T(dqs_tri));
.T (dqs_data)
);
endmodule
| 6.768085 |
module test_dram;
parameter CYCLE = 10; // use "CYCLE" to represent the period
parameter DRAM_DATA_WIDTH = 32;
parameter DRAM_ADDR_WIDTH = 13;
///// declare input(reg) and output(wire) /////
reg clk;
reg rst_n;
reg DRAM_enable;
wire DRAM_data_valid;
wire [DRAM_DATA_WIDTH-1:0] DRAM_data_out;
// dram write
reg en_a;
reg [DRAM_ADDR_WIDTH-1:0] addr_a;
reg [DRAM_DATA_WIDTH-1:0] data;
// dram read
wire en_b;
wire [DRAM_ADDR_WIDTH-1:0] addr_b;
wire [DRAM_DATA_WIDTH-1:0] q;
///// declare module /////
two_port_ram_sclk #(
.DATA_WIDTH(DRAM_DATA_WIDTH),
.ADDR_WIDTH(DRAM_ADDR_WIDTH)
) u_dram (
.clk(clk),
.en_a(en_a),
.addr_a(addr_a),
.data(data),
.en_b(en_b),
.addr_b(addr_b),
.q(q)
);
dram_read_controller #(
.DATA_WIDTH(DRAM_DATA_WIDTH),
.ADDR_WIDTH(DRAM_ADDR_WIDTH)
) u_dram_controller (
.clk(clk),
.rst_n(rst_n),
.enable(DRAM_enable),
.valid(DRAM_data_valid),
.out(DRAM_data_out),
// connect dram
.dram_out(q),
.dram_read_en(en_b),
.dram_addr(addr_b)
);
///// fsdb /////
initial begin
$fsdbDumpfile("dram.fsdb");
$fsdbDumpvars(0, test_dram, "+mda");
end
///// clock /////
always #(CYCLE / 2) clk = ~clk;
///// test patterns /////
initial begin
// initialize the input signals
clk = 0;
rst_n = 0;
DRAM_enable = 0;
#(CYCLE) rst_n = 1;
// initialize dram
init_dram();
$display("%d ns: Initialize DRAM finish", $time);
#(CYCLE);
// read data from image and write to dram
read_image_to_dram("./image/chess_48x48_en.yuv");
$display("%d ns: Read image finish", $time);
#(CYCLE);
// begin test
$display("%d ns: Begin test", $time);
#(4 * CYCLE) DRAM_enable = 1;
#(16 * CYCLE) DRAM_enable = 0;
#(4 * CYCLE) DRAM_enable = 1;
#(16 * CYCLE) DRAM_enable = 0;
#(CYCLE) $finish;
end
`include "simple_task.v"
endmodule
| 8.3701 |
module: dut_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_dut_top;
// Inputs
reg clk;
reg nrst;
reg enable;
reg fifo_full;
// Outputs
wire fifo_wr_en;
wire [7:0] dut_dout;
localparam Clock=10;
localparam one_ns = 1000;
// Instantiate the Unit Under Test (UUT)
dut_top uut (
.clk(clk),
.nrst(nrst),
.enable(enable),
.fifo_full(fifo_full),
.fifo_wr_en(fifo_wr_en),
.dut_dout(dut_dout)
);
initial begin
// Initialize Inputs
clk = 0;
nrst = 0;
enable = 0;
fifo_full = 0;
#50000 nrst = 1;
// Add stimulus here
#(500*Clock*one_ns);
enable = 1;
#(1000*Clock*one_ns);
$stop;
end
always begin
#(Clock* one_ns* 0.5) clk=~clk;
end
endmodule
| 6.660571 |
module test_dvsd_pe;
reg en;
reg [7:0] in;
wire eno, gs;
wire [2:0] out;
dvsd_pe uut (
.in (in),
.en (en),
.out(out),
.eno(eno),
.gs (gs)
);
initial begin
$dumpfile("dvsd_pe.vcd");
$dumpvars(0, test_dvsd_pe);
in = 8'b00000000;
en = 0;
#10;
in = 8'b00000001;
en = 1;
#10;
in = 8'b00000010;
en = 1;
#10;
in = 8'b00000100;
en = 1;
#10;
in = 8'b00001000;
en = 1;
#10;
in = 8'b00010000;
en = 1;
#10;
in = 8'b00100000;
en = 1;
#10;
in = 8'b01000000;
en = 1;
#10;
in = 8'b10000000;
en = 1;
#10;
end
endmodule
| 7.731165 |
module test_DW_ahb;
reg hclk;
supply1 logic_1;
supply0 logic_0;
wire dummy_wire;
wire [ 63:0] addr64;
wire [ 64:0] addr65;
wire [ 15:0] zero16 = 0;
wire [ (6*8)-1:0] testcase_id;
wire [`NUM_AHB_MASTERS:0] bus_hbusreq;
wire [`NUM_IAHB_SLAVES:0] bus_hsel;
wire [`NUM_AHB_MASTERS:0] bus_hlock;
wire [`NUM_AHB_MASTERS:0] bus_hgrant;
wire [ 15:0] abus_hbusreq;
wire [ 15:0] abus_hsel;
wire [ 15:0] abus_hlock;
wire [ 15:0] abus_hgrant;
test_DW_ahb_shell vshell (
hclk,
hclk
);
i_ahb_DW_ahb U_ahb (.hclk(hclk));
assign addr65[64:`HADDR_WIDTH] = 0;
assign addr65[`HADDR_WIDTH-1:0] = U_ahb.haddr;
assign addr64 = addr65[63:0];
//# The following are used in the connection of the AHB monitor or ACT monitor
assign bus_hsel = abus_hsel[`NUM_IAHB_SLAVES:0];
assign bus_hbusreq = abus_hbusreq[`NUM_AHB_MASTERS:0];
assign bus_hlock = abus_hlock[`NUM_AHB_MASTERS:0];
assign bus_hgrant = abus_hgrant[`NUM_AHB_MASTERS:0];
assign abus_hbusreq[0] = 1'b0;
assign abus_hbusreq[1] = 1'b1;
assign abus_hlock[0] = 1'b0;
assign abus_hlock[1] = U_ahb.hlock_m1;
assign abus_hgrant[0] = ~(|abus_hgrant[1:1]);
assign abus_hgrant[1] = 1'b1;
assign abus_hsel[0] = 1'b0;
assign abus_hsel[1] = (U_ahb.hsel_s1 === 1'b1) ? 1'b1 : 1'b0;
assign abus_hsel[2] = (U_ahb.hsel_s2 === 1'b1) ? 1'b1 : 1'b0;
assign abus_hsel[3] = (U_ahb.hsel_s3 === 1'b1) ? 1'b1 : 1'b0;
assign abus_hsel[4] = (U_ahb.hsel_s4 === 1'b1) ? 1'b1 : 1'b0;
// Only run this check for unencrypted VCS RTL sims.
`ifdef VCS
`ifdef RTL
`ifdef AHB_ENCRYPT
`else
// Insert module to check condition relating to STAR 9000231009
// "DW_ahb : need to select slave output even if HTRANS=IDLE."
// NOTE : bus* signal from DW_ahb contain default slave busses
// as well, which we are not interested in for this check.
tb_check_idle_resp #(`NUM_IAHB_SLAVES,
`AHB_DATA_WIDTH
) U_tb_check_idle_resp (
// Inputs - System.
.hclk_i (U_ahb.hclk),
.hresetn_i(U_ahb.hresetn),
// Inputs - AHB bus.
.htrans_i (U_ahb.htrans),
.hsel_i (U_ahb.hsel[`NUM_IAHB_SLAVES:1]),
.hready_i (U_ahb.hready),
.hrdata_bus_i(U_ahb.bus_hrdata[((`NUM_IAHB_SLAVES+1)*`AHB_DATA_WIDTH)-1:`AHB_DATA_WIDTH]),
.hrdata_i (U_ahb.hrdata)
);
`endif
`endif
`endif
// ----------------------------------------
// dump control
// ----------------------------------------
`ifdef DUMP_DEPTH
initial begin
`ifdef VCS
$vcdpluson(`DUMP_DEPTH);
`else
`ifdef DUMP_FILE
`else
`define DUMP_FILE "test.vcd"
`endif
$dumpfile(`DUMP_FILE);
$dumpvars(`DUMP_DEPTH);
`endif
end
`endif
// ----------------------------------------
// sdf simulations
// ----------------------------------------
`ifdef SDF_FILE
initial begin
$display("About to sdf-annotate the design from %s", `SDF_FILE);
$sdf_annotate(`SDF_FILE, U_ahb,,, `SDF_LEVEL);
end
`endif
// ----------------------------------------
// required for toggle coverage
// ----------------------------------------
`ifdef CODE_COVERAGE
initial begin
//$set_toggle_mode(1);
//$start_toggle("U_ahb");
end
`endif
// ----------------------------------------
// clock generators
// ----------------------------------------
initial begin
hclk = 1;
forever begin
#(`PERIOD / 2.0) hclk = ~hclk;
end
end
endmodule
| 6.666869 |
module test_D_flip_flop ();
reg D = 0, en = 0, clk = 0, clear = 0, set = 0;
wire Q, NQ;
D_flip_flop dff (
D,
en,
clk,
clear,
set,
Q,
NQ
);
always begin
#5 clk = 1;
#10 clk = 0;
#5{en, clear, set, D} = {en, clear, set, D} + 1;
end
endmodule
| 6.637852 |
module test_ecb_dec;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
//ECB_dec e(ciphertext, message, key);
ECB_dec e (
ciphertext,
message,
key
);
initial begin
#10 $readmemb("ecb_enc.txt", msg);
//$display("f=%b",msg[1]);
f = $fopen("ecb_dec.txt", "w");
#10
for (i = 1; i <= 131072; i = i + 1) begin
#1 message = msg[i];
//$display("%b",msg[i]);
key = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
//$monitor("%d",i);
$display("%b", ciphertext);
//$fwrite(f,"%d",i);
$fwrite(f, "%b\n", ciphertext);
end
#10 $fclose(f);
end
endmodule
| 7.232516 |
module test_ecb_enc;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
ECB_enc e (
ciphertext,
message,
key
);
//ECB_dec e(ciphertext, message, key);
initial begin
#10 $readmemb("binary.txt", msg);
//$display("f=%b",msg[1]);
f = $fopen("ecb_enc.txt", "w");
#10
for (i = 1; i <= 131072; i = i + 1) begin
#1 message = msg[i];
//$display("%b",msg[i]);
key = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
//$monitor("%d",i);
$display("%b", ciphertext);
//$fwrite(f,"%d",i);
$fwrite(f, "%b\n", ciphertext);
end
#10 $fclose(f);
end
endmodule
| 7.258174 |
module: entry_park
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_entry_park;
// Inputs
reg entry;
reg [7:0] parking_capacity;
// Outputs
wire [2:0] park_number;
// Instantiate the Unit Under Test (UUT)
entry_park uut (
.entry(entry),
.parking_capacity(parking_capacity),
.park_number(park_number)
);
initial begin
entry = 1; parking_capacity = 8'b11111111; #200; // park_number = 111
entry = 0; parking_capacity = 8'b11111111; #200; // park_number = ZZZ
entry = 1; parking_capacity = 8'b00101100; #200; // park_number = 101
entry = 1; parking_capacity = 8'b00000000; #200; // park_number = ZZZ
entry = 1; parking_capacity = 8'b00000001; #200; // park_number = 000
end
endmodule
| 6.500393 |
module test_environment ();
parameter DATA_WIDTH = 8;
parameter CLOCK_PERIOD = 5;
parameter TRANSACTION_NR = 30; // Number of transactions for the forth test scenario
parameter RST_DELAY = 30; // Initial waiting period before reset
parameter RST_DURATION = 2; // Duration of the reset pulse
parameter TEST_SCENARIO = 3; // 0 = test scenario with values specified in the testbench, 1 = test scenario with random values, 2 = test scenario with corner case values 3 = test scenario with multiple transactions
parameter WAIT_BEFORE_READY = 20; // Number of clock cycles before the module drives the res_ready signal in 1
//Internal signals
wire clk;
wire rstn;
wire sw_rst;
wire op_val;
wire res_ready;
wire [4*DATA_WIDTH-1 : 0] op_data;
wire op_ready;
wire res_val;
wire [4*DATA_WIDTH+2 : 0] res_data;
// Modules instantiation
complex_nr_mult_4 #(DATA_WIDTH) DUT (
.clk (clk),
.rstn (rstn),
.sw_rst (sw_rst),
.op_val (op_val),
.res_ready(res_ready),
.op_data (op_data),
.op_ready (op_ready),
.res_val (res_val),
.res_data (res_data)
);
// Signal generation for op interface and result valid
complex_nr_mult_tb #(DATA_WIDTH, TEST_SCENARIO) TESTBENCH (
.clk (clk),
.rstn (rstn),
.op_ready(op_ready),
.sw_rst (sw_rst),
.op_val (op_val),
.op_data (op_data)
);
// Clock and reset generator
clock_rst_gen #(CLOCK_PERIOD, RST_DELAY, RST_DURATION) CLK_AND_RST_GEN (
.clk (clk),
.rstn(rstn)
);
// Generator for result reaady signal
result_if_drv #(WAIT_BEFORE_READY) RESULT_IF_DRV (
.clk (clk),
.rstn (rstn),
.sw_rst (sw_rst),
.res_val (res_val),
.res_ready(res_ready)
);
// Monitor module => compares the expected results with the results generated by the DUT
monitor_complex_multiplier #(DATA_WIDTH) MONITOR (
.clk (clk),
.rstn (rstn),
.sw_rst (sw_rst),
.op_val (op_val),
.res_ready(res_ready),
.op_data (op_data),
.op_ready (op_ready),
.res_val (res_val),
.res_data (res_data)
);
endmodule
| 7.608497 |
module test_err_pipe (
clock,
reset,
start,
done,
out,
T0,
T0_frac,
mem_Mux1Sel,
mem_Mux2Sel,
mem_Mux3Sel,
mem_Mux4Sel,
test_write_addr,
test_read_addr,
test_write,
test_write_en
);
input clock, reset, start;
output done;
output [15:0] out;
input [15:0] T0, T0_frac;
input mem_Mux1Sel, mem_Mux2Sel, mem_Mux3Sel, mem_Mux4Sel;
input [11:0] test_write_addr, test_read_addr;
input [31:0] test_write;
input test_write_en;
reg [11:0] mem_Mux1Out, mem_Mux4Out;
reg [31:0] mem_Mux2Out;
reg mem_Mux3Out;
wire [11:0] scratch_mem_write_addr, scratch_mem_read_addr;
wire [31:0] scratch_mem_out, scratch_mem_in;
wire scratch_mem_write_en;
wire [11:0] constant_mem_read_addr;
wire [31:0] constant_mem_in;
wire [15:0] sub_in, sub_outa, sub_outb, add_in, add_outa, add_outb;
wire [31:0] L_sub_outa, L_sub_outb, L_sub_in;
test_err i_test_err (
clock,
reset,
start,
done,
out,
T0,
T0_frac,
add_outa,
add_outb,
add_in,
sub_outa,
sub_outb,
sub_in,
L_sub_outa,
L_sub_outb,
L_sub_in,
scratch_mem_read_addr,
scratch_mem_write_addr,
scratch_mem_in,
scratch_mem_out,
scratch_mem_write_en,
constant_mem_read_addr,
constant_mem_in
);
add i_add_1 (
.a (add_outa),
.b (add_outb),
.sum(add_in)
);
sub i_sub_1 (
.a(sub_outa),
.b(sub_outb),
.diff(sub_in)
);
L_sub i_L_sub_1 (
.a(L_sub_outa),
.b(L_sub_outb),
.overflow(L_sub_overflow),
.diff(L_sub_in)
);
//mem write address mux
always @(*) begin
case (mem_Mux1Sel)
'd0: mem_Mux1Out = scratch_mem_write_addr;
'd1: mem_Mux1Out = test_write_addr;
endcase
end
//mem input mux
always @(*) begin
case (mem_Mux2Sel)
'd0: mem_Mux2Out = scratch_mem_out;
'd1: mem_Mux2Out = test_write;
endcase
end
//mem write enable mux
always @(*) begin
case (mem_Mux3Sel)
'd0: mem_Mux3Out = scratch_mem_write_en;
'd1: mem_Mux3Out = test_write_en;
endcase
end
//mem read address mux
always @(*) begin
case (mem_Mux4Sel)
'd0: mem_Mux4Out = scratch_mem_read_addr;
'd1: mem_Mux4Out = test_read_addr;
endcase
end
Scratch_Memory_Controller test_scratch_mem (
.addra(mem_Mux1Out),
.dina (mem_Mux2Out),
.wea (mem_Mux3Out),
.clk (clock),
.addrb(mem_Mux4Out),
.doutb(scratch_mem_in)
);
Constant_Memory_Controller test_constant_mem (
.addra(constant_mem_read_addr),
.dina ('d0),
.wea (1'd0),
.clock(clock),
.douta(constant_mem_in)
);
endmodule
| 6.793341 |
module test_err_tb;
`include "paramList.v"
// Inputs
reg clock;
reg reset;
reg start;
reg [15:0] T0;
reg [15:0] T0_frac;
reg mem_Mux1Sel;
reg mem_Mux2Sel;
reg mem_Mux3Sel;
reg mem_Mux4Sel;
reg [11:0] test_write_addr;
reg [11:0] test_read_addr;
reg [31:0] test_write;
reg test_write_en;
// Outputs
wire done;
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
test_err_pipe uut (
.clock(clock),
.reset(reset),
.start(start),
.done(done),
.out(out),
.T0(T0),
.T0_frac(T0_frac),
.mem_Mux1Sel(mem_Mux1Sel),
.mem_Mux2Sel(mem_Mux2Sel),
.mem_Mux3Sel(mem_Mux3Sel),
.mem_Mux4Sel(mem_Mux4Sel),
.test_write_addr(test_write_addr),
.test_read_addr(test_read_addr),
.test_write(test_write),
.test_write_en(test_write_en)
);
reg [31:0] T0_in[0:4999];
reg [31:0] T0_frac_in[0:4999];
reg [31:0] L_exc_err_in[0:4999];
reg [31:0] flag_out[0:4999];
//file read in for inputs and output tests
initial begin // samples out are samples from ITU G.729 test vectors
$readmemh("test_err_t0_in.out", T0_in);
$readmemh("test_err_t0_frac_in.out", T0_frac_in);
$readmemh("test_err_L_exc_err_in.out", L_exc_err_in);
$readmemh("test_err_flag_out.out", flag_out);
end
integer i, j;
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
start = 0;
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
reset = 1;
// Wait 50 ns for global reset to finish
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
reset = 0;
@(posedge clock) #5;
for (j = 0; j < 256; j = j + 1) begin
//TEST1
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
mem_Mux1Sel = 0;
mem_Mux2Sel = 0;
mem_Mux3Sel = 0;
mem_Mux4Sel = 0;
test_read_addr = 0;
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
for (i = 0; i < 4; i = i + 1) begin
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
mem_Mux1Sel = 1;
mem_Mux2Sel = 1;
mem_Mux3Sel = 1;
mem_Mux4Sel = 1;
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
test_write_addr = {L_EXC_ERR[11:2], i[1:0]};
test_write = L_exc_err_in[4*j+i];
test_write_en = 1;
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
end
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
mem_Mux1Sel = 0;
mem_Mux2Sel = 0;
mem_Mux3Sel = 0;
mem_Mux4Sel = 0;
@(posedge clock);
@(posedge clock);
T0 = T0_in[j];
T0_frac = T0_frac_in[j];
@(posedge clock) #5;
start = 1;
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
start = 0;
// Add stimulus here
wait (done);
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
mem_Mux4Sel = 1;
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
if (out != flag_out[j])
$display($time, " ERROR: out[%d] = %x, expected = %x", j, out, flag_out[j]);
else if (out == flag_out[j]) $display($time, " CORRECT: out[%d] = %x", j, out);
@(posedge clock);
@(posedge clock);
@(posedge clock);
@(posedge clock) #5;
end //j for loop
end
initial forever #10 clock = ~clock;
endmodule
| 7.503106 |
module test_eth_axis_rx;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire busy;
wire error_header_early_termination;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser, m_eth_hdr_ready, m_eth_payload_axis_tready);
$to_myhdl(s_axis_tready, m_eth_hdr_valid, m_eth_dest_mac, m_eth_src_mac, m_eth_type,
m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast, m_eth_payload_axis_tuser, busy,
error_header_early_termination);
// dump file
$dumpfile("test_eth_axis_rx.lxt");
$dumpvars(0, test_eth_axis_rx);
end
eth_axis_rx #(
.DATA_WIDTH (DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH (KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(busy),
.error_header_early_termination(error_header_early_termination)
);
endmodule
| 7.267792 |
module test_eth_axis_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire busy;
wire error_header_early_termination;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser, m_eth_hdr_ready, m_eth_payload_axis_tready);
$to_myhdl(s_axis_tready, m_eth_hdr_valid, m_eth_dest_mac, m_eth_src_mac, m_eth_type,
m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast, m_eth_payload_axis_tuser, busy,
error_header_early_termination);
// dump file
$dumpfile("test_eth_axis_rx_64.lxt");
$dumpvars(0, test_eth_axis_rx_64);
end
eth_axis_rx #(
.DATA_WIDTH (DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH (KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(busy),
.error_header_early_termination(error_header_early_termination)
);
endmodule
| 7.267792 |
module test_eth_axis_tx;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_eth_payload_axis_tready;
wire s_eth_hdr_ready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_eth_hdr_valid, s_eth_dest_mac, s_eth_src_mac, s_eth_type,
s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast, s_eth_payload_axis_tuser, m_axis_tready);
$to_myhdl(s_eth_hdr_ready, s_eth_payload_axis_tready, m_axis_tdata, m_axis_tkeep,
m_axis_tvalid, m_axis_tlast, m_axis_tuser, busy);
// dump file
$dumpfile("test_eth_axis_tx.lxt");
$dumpvars(0, test_eth_axis_tx);
end
eth_axis_tx #(
.DATA_WIDTH (DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH (KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// Status signals
.busy(busy)
);
endmodule
| 7.267792 |
module test_eth_axis_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_eth_payload_axis_tready;
wire s_eth_hdr_ready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_eth_hdr_valid, s_eth_dest_mac, s_eth_src_mac, s_eth_type,
s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast, s_eth_payload_axis_tuser, m_axis_tready);
$to_myhdl(s_eth_hdr_ready, s_eth_payload_axis_tready, m_axis_tdata, m_axis_tkeep,
m_axis_tvalid, m_axis_tlast, m_axis_tuser, busy);
// dump file
$dumpfile("test_eth_axis_tx_64.lxt");
$dumpvars(0, test_eth_axis_tx_64);
end
eth_axis_tx #(
.DATA_WIDTH (DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH (KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// Status signals
.busy(busy)
);
endmodule
| 7.267792 |
module test_eth_mac (
//inout wire tx_clk,
input wire tx_clk,
inout wire tx_rst,
inout wire [63:0] tx_axis_tdata,
inout wire [ 7:0] tx_axis_tkeep,
inout wire tx_axis_tlast,
inout wire [16:0] tx_axis_tuser,
inout wire tx_axis_tvalid,
inout wire tx_axis_tready,
inout wire [95:0] tx_ptp_time,
inout wire [95:0] tx_ptp_ts,
inout wire [15:0] tx_ptp_ts_tag,
inout wire tx_ptp_ts_valid,
//inout wire rx_clk,
input wire rx_clk,
inout wire rx_rst,
inout wire [63:0] rx_axis_tdata,
inout wire [ 7:0] rx_axis_tkeep,
inout wire rx_axis_tlast,
inout wire [96:0] rx_axis_tuser,
inout wire rx_axis_tvalid,
inout wire [95:0] rx_ptp_time
);
endmodule
| 7.16086 |
module test_eth_mac_1g_gmii;
// Parameters
parameter TARGET = "SIM";
parameter IODDR_STYLE = "IODDR2";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg gtx_clk = 0;
reg gtx_rst = 0;
reg [7:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg gmii_rx_clk = 0;
reg [7:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
reg mii_tx_clk = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire rx_clk;
wire rx_rst;
wire tx_clk;
wire tx_rst;
wire tx_axis_tready;
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire gmii_tx_clk;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire tx_error_underflow;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire [1:0] speed;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, gtx_clk, gtx_rst, tx_axis_tdata, tx_axis_tvalid,
tx_axis_tlast, tx_axis_tuser, gmii_rx_clk, gmii_rxd, gmii_rx_dv, gmii_rx_er,
mii_tx_clk, ifg_delay);
$to_myhdl(rx_clk, rx_rst, tx_clk, tx_rst, tx_axis_tready, rx_axis_tdata, rx_axis_tvalid,
rx_axis_tlast, rx_axis_tuser, gmii_tx_clk, gmii_txd, gmii_tx_en, gmii_tx_er,
tx_error_underflow, rx_error_bad_frame, rx_error_bad_fcs, speed);
// dump file
$dumpfile("test_eth_mac_1g_gmii.lxt");
$dumpvars(0, test_eth_mac_1g_gmii);
end
eth_mac_1g_gmii #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
) UUT (
.gtx_clk(gtx_clk),
.gtx_rst(gtx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rx_clk(gmii_rx_clk),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_tx_clk(gmii_tx_clk),
.mii_tx_clk(mii_tx_clk),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.speed(speed),
.ifg_delay(ifg_delay)
);
endmodule
| 7.35377 |
module test_eth_mac_1g_rgmii;
// Parameters
parameter TARGET = "SIM";
parameter IODDR_STYLE = "IODDR2";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter USE_CLK90 = "TRUE";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg gtx_clk = 0;
reg gtx_clk90 = 0;
reg gtx_rst = 0;
reg [7:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rgmii_rx_clk = 0;
reg [3:0] rgmii_rxd = 0;
reg rgmii_rx_ctl = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire rx_clk;
wire rx_rst;
wire tx_clk;
wire tx_rst;
wire tx_axis_tready;
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire rgmii_tx_clk;
wire [3:0] rgmii_txd;
wire rgmii_tx_ctl;
wire tx_error_underflow;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire [1:0] speed;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, gtx_clk, gtx_clk90, gtx_rst, tx_axis_tdata, tx_axis_tvalid,
tx_axis_tlast, tx_axis_tuser, rgmii_rx_clk, rgmii_rxd, rgmii_rx_ctl, ifg_delay);
$to_myhdl(rx_clk, rx_rst, tx_clk, tx_rst, tx_axis_tready, rx_axis_tdata, rx_axis_tvalid,
rx_axis_tlast, rx_axis_tuser, rgmii_tx_clk, rgmii_txd, rgmii_tx_ctl,
tx_error_underflow, rx_error_bad_frame, rx_error_bad_fcs, speed);
// dump file
$dumpfile("test_eth_mac_1g_rgmii.lxt");
$dumpvars(0, test_eth_mac_1g_rgmii);
end
eth_mac_1g_rgmii #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.USE_CLK90(USE_CLK90),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
) UUT (
.gtx_clk(gtx_clk),
.gtx_clk90(gtx_clk90),
.gtx_rst(gtx_rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(rgmii_rx_clk),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.rgmii_tx_clk(rgmii_tx_clk),
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.speed(speed),
.ifg_delay(ifg_delay)
);
endmodule
| 7.35377 |
module test_eth_mac_mii;
// Parameters
parameter TARGET = "SIM";
parameter CLOCK_INPUT_STYLE = "BUFIO2";
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg mii_rx_clk = 0;
reg [3:0] mii_rxd = 0;
reg mii_rx_dv = 0;
reg mii_rx_er = 0;
reg mii_tx_clk = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire rx_clk;
wire rx_rst;
wire tx_clk;
wire tx_rst;
wire tx_axis_tready;
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [3:0] mii_txd;
wire mii_tx_en;
wire mii_tx_er;
wire tx_error_underflow;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, tx_axis_tdata, tx_axis_tvalid, tx_axis_tlast,
tx_axis_tuser, mii_rx_clk, mii_rxd, mii_rx_dv, mii_rx_er, mii_tx_clk, ifg_delay);
$to_myhdl(rx_clk, rx_rst, tx_clk, tx_rst, tx_axis_tready, rx_axis_tdata, rx_axis_tvalid,
rx_axis_tlast, rx_axis_tuser, mii_txd, mii_tx_en, mii_tx_er, tx_error_underflow,
rx_error_bad_frame, rx_error_bad_fcs);
// dump file
$dumpfile("test_eth_mac_mii.lxt");
$dumpvars(0, test_eth_mac_mii);
end
eth_mac_mii #(
.TARGET(TARGET),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
) UUT (
.rst(rst),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.mii_rx_clk(mii_rx_clk),
.mii_rxd(mii_rxd),
.mii_rx_dv(mii_rx_dv),
.mii_rx_er(mii_rx_er),
.mii_tx_clk(mii_tx_clk),
.mii_txd(mii_txd),
.mii_tx_en(mii_tx_en),
.mii_tx_er(mii_tx_er),
.tx_error_underflow(tx_error_underflow),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
| 7.35377 |
module test_eth_phy_10g_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 125000 / 6.4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg [DATA_WIDTH-1:0] xgmii_txd = 0;
reg [CTRL_WIDTH-1:0] xgmii_txc = 0;
reg [DATA_WIDTH-1:0] serdes_rx_data = 0;
reg [HDR_WIDTH-1:0] serdes_rx_hdr = 1;
reg tx_prbs31_enable = 0;
reg rx_prbs31_enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] xgmii_rxd;
wire [CTRL_WIDTH-1:0] xgmii_rxc;
wire [DATA_WIDTH-1:0] serdes_tx_data;
wire [HDR_WIDTH-1:0] serdes_tx_hdr;
wire serdes_rx_bitslip;
wire [6:0] rx_error_count;
wire rx_bad_block;
wire rx_block_lock;
wire rx_high_ber;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, rx_clk, rx_rst, tx_clk, tx_rst, xgmii_txd, xgmii_txc,
serdes_rx_data, serdes_rx_hdr, tx_prbs31_enable, rx_prbs31_enable);
$to_myhdl(xgmii_rxd, xgmii_rxc, serdes_tx_data, serdes_tx_hdr, serdes_rx_bitslip,
rx_error_count, rx_bad_block, rx_block_lock, rx_high_ber);
// dump file
$dumpfile("test_eth_phy_10g_64.lxt");
$dumpvars(0, test_eth_phy_10g_64);
end
eth_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
) UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.tx_prbs31_enable(tx_prbs31_enable),
.rx_prbs31_enable(rx_prbs31_enable)
);
endmodule
| 7.284581 |
module test_eth_phy_10g_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter SERDES_PIPELINE = 2;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 1250 / 6.4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] serdes_rx_data = 0;
reg [HDR_WIDTH-1:0] serdes_rx_hdr = 1;
reg rx_prbs31_enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] xgmii_rxd;
wire [CTRL_WIDTH-1:0] xgmii_rxc;
wire serdes_rx_bitslip;
wire [6:0] rx_error_count;
wire rx_bad_block;
wire rx_block_lock;
wire rx_high_ber;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, serdes_rx_data, serdes_rx_hdr, rx_prbs31_enable);
$to_myhdl(xgmii_rxd, xgmii_rxc, serdes_rx_bitslip, rx_error_count, rx_bad_block, rx_block_lock,
rx_high_ber);
// dump file
$dumpfile("test_eth_phy_10g_rx_64.lxt");
$dumpvars(0, test_eth_phy_10g_rx_64);
end
eth_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
) UUT (
.clk(clk),
.rst(rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
endmodule
| 7.284581 |
module test_eth_phy_10g_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter SERDES_PIPELINE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] xgmii_txd = 0;
reg [CTRL_WIDTH-1:0] xgmii_txc = 0;
reg tx_prbs31_enable = 0;
// Outputs
wire [DATA_WIDTH-1:0] serdes_tx_data;
wire [HDR_WIDTH-1:0] serdes_tx_hdr;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, xgmii_txd, xgmii_txc, tx_prbs31_enable);
$to_myhdl(serdes_tx_data, serdes_tx_hdr);
// dump file
$dumpfile("test_eth_phy_10g_tx_64.lxt");
$dumpvars(0, test_eth_phy_10g_tx_64);
end
eth_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE)
) UUT (
.clk(clk),
.rst(rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
| 7.284581 |
module
module ram #(
parameter ADDR_WIDTH=6,
parameter DATA_WIDTH=8
) (
input [DATA_WIDTH-1:0] data,
input [ADDR_WIDTH-1:0] addr,
input we, clk,
output reg [DATA_WIDTH-1:0] q
);
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
always @(posedge clk) begin
if (we)
ram[addr] <= data; // write data to RAM at address addr when we is high
q <= ram[addr]; // assign the RAM value at address addr to q
end
endmodule
| 7.233831 |
module test_ex1;
`include "lib/helpers.vh"
// Inputs
reg reset;
reg clk;
// Outputs
wire out;
// Checker
reg [4:0] total;
// Instantiate the Unit Under Test (UUT)
ex1 uut (
.out (out),
.reset(reset),
.clk (clk)
);
reg count = 0;
initial begin
// Initialize Inputs
reset = 1;
clk = 0;
// Initialize Checker Vars
total = 0;
// Wait 100 ns for global reset to finish
#(`CLK_PERIOD);
reset = 0;
if (out != 0) begin
$write("LED: ");
show_LEDs(out, 1);
$display("- FAILED");
$display("Check LED initial state!");
err_exit(total, `EX1_TOTAL, `EX1_SCORE);
end else begin
$write("LED: ");
show_LEDs(out, 1);
$display("- PASSED");
total = total + 1;
end
#((`LED_TMR + `OUT_SYNC) * `CLK_PERIOD)
if (out != 1) begin
$write("LED: ");
show_LEDs(out, 1);
$display("- FAILED");
$display("Check LED on state!");
err_exit(total, `EX1_TOTAL, `EX1_SCORE);
end else begin
$write("LED: ");
show_LEDs(out, 1);
$display("- PASSED");
total = total + 1;
end
#((`LED_TMR + `OUT_SYNC) * `CLK_PERIOD)
if (out != 0) begin
$write("LED: ");
show_LEDs(out, 1);
$display("- FAILED");
$display("Check LED off state!");
err_exit(total, `EX1_TOTAL, `EX1_SCORE);
end else begin
$write("LED: ");
show_LEDs(out, 1);
$display("- PASSED");
total = total + 1;
end
succ_exit(total, `EX1_TOTAL, `EX1_SCORE);
end
always #(`CLK_PERIOD / 2) clk = !clk;
endmodule
| 6.861294 |
module test_ex2;
`include "lib/helpers.vh"
// Inputs
reg reset;
reg clk;
// Outputs
wire [7:0] out;
wire [3:0] state;
// Checker
reg [4:0] total;
reg [4:0] exp_state;
// Instantiate the Unit Under Test (UUT)
ex2 uut (
.out(out),
.currentState(state),
.reset(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
reset = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#(`CLK_PERIOD / 2) reset = 1;
#(`CLK_PERIOD) reset = 0;
// Initialize Checker Vars
total = 0;
wait (state == 0);
if (out != 0) begin
$display("Initial state not found! - FAILED");
err_exit(total, `EX2_TOTAL, `EX2_SCORE);
end
;
for (exp_state = 1; exp_state < 16; exp_state = exp_state + 1) begin
wait (state == exp_state) @(out);
if (out != exp_output(exp_state)) $display("%s : t%d - FAILED", show_LEDs(out, 8), exp_state);
else begin
$display("%s : t%d - PASSED", show_LEDs(out, 8), exp_state);
total = total + 1;
end
;
end
;
@(state);
if (state != 1) $display("The machine did not go back to first state. - FAILED");
else total = total + 1;
#(`CLK_PERIOD / 2) reset = 1;
#(`CLK_PERIOD)
if (state != 0) $display("The machine did not change at reset. - FAILED");
else total = total + 1;
reset = 0;
succ_exit(total, `EX2_TOTAL, `EX2_SCORE);
end
always #(`CLK_PERIOD / 2) clk = !clk;
endmodule
| 6.898797 |
module test_ex3;
`include "lib/helpers.vh"
// Inputs
reg button;
reg reset;
reg clk;
// Outputs
wire [7:0] out;
// Checker
reg [4:0] total;
// Instantiate the Unit Under Test (UUT)
ex3 uut (
.out(out),
.button_debounced(button),
.reset(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
button = 0;
reset = 0;
clk = 0;
// Initialize Checker Vars
total = 0;
// Wait 100 ns for global reset to finish
@(out)
if (out == 0) total = total + 1;
else begin
$display("Initial state not found! - FAILED");
err_exit(total, `EX3_TOTAL, `EX3_SCORE);
end
@(out)
if (out == 240) begin
$display("SMPHR: %b - PASSED", out);
$display("Waiting %0d clock periods...", `SMPHR_RED_TMR);
total = total + 1;
end else begin
$display("SMPHR: %b - FAILED", out);
$display("Semaphore expected RED light after initialization! - FAILED");
err_exit(total, `EX3_TOTAL, `EX3_SCORE);
end
#(`CLK_PERIOD / 2) // desync
button = 1;
#(`CLK_PERIOD) button = 0;
#((`SMPHR_RED_TMR + `SMPHR_TMR_START + `SMPHR_TMR_STOP + `OUT_SYNC) * `CLK_PERIOD)
if (out == 15) begin
$display("SMPHR: %b - PASSED", out);
$display("Waiting %0d clock periods...", `SMPHR_GRN_TMR);
total = total + 1;
end else begin
$display("SMPHR: %b - FAILED", out);
$display("Check out value and red-to-green delay!");
err_exit(total, `EX3_TOTAL, `EX3_SCORE);
end
#((`SMPHR_GRN_TMR + `SMPHR_TMR_STOP + `OUT_SYNC) * `CLK_PERIOD)
if (out == 240) begin
$display("SMPHR: %b - PASSED", out);
total = total + 1;
end else begin
$display("SMPHR: %b - FAILED", out);
$display("Check out value and green-to-red delay!");
err_exit(total, `EX3_TOTAL, `EX3_SCORE);
end
succ_exit(total, `EX3_TOTAL, `EX3_SCORE);
end
always #(`CLK_PERIOD / 2) clk = !clk;
endmodule
| 7.355491 |
module test_ex4;
`include "lib/helpers.vh"
// Inputs
reg A;
reg G;
reg C;
reg T;
reg reset;
reg clk;
// Outputs
wire mutant;
wire super_mutant;
wire [2:0] current_state;
// Checker
reg [4:0] total;
// Instantiate the Unit Under Test (UUT)
ex4 uut (
.mutant(mutant),
.super_mutant(super_mutant),
.currentState(current_state),
.A(A),
.G(G),
.C(C),
.T(T),
.reset(reset),
.clk(clk)
);
initial begin
// Initialize Inputs
A = 0;
G = 0;
C = 0;
T = 0;
reset = 1;
clk = 0;
// Initialize Checker Vars
total = 0;
// Wait 100 ns for global reset to finish
#(`CLK_PERIOD)
if (mutant == 0 && current_state == 0) total = total + 1;
else begin
$display("Expecting STATE_0 as current state after reset! - FAILED");
err_exit(total, `EX4_TOTAL, `EX4_SCORE);
end
reset = 0;
G = 1;
#(`CLK_PERIOD)
if (mutant == 0 && current_state == 1) total = total + 1;
else begin
$display("Expecting STATE_1 as current state for 'G' input string! - FAILED");
err_exit(total, `EX4_TOTAL, `EX4_SCORE);
end
G = 0;
#(`CLK_PERIOD) G = 1;
#(`CLK_PERIOD)
if (mutant == 0 && current_state == 2) total = total + 1;
else begin
$display("Expecting STATE_2 as current state for 'GG' input string! - FAILED");
err_exit(total, `EX4_TOTAL, `EX4_SCORE);
end
T = 1;
G = 0;
#(`CLK_PERIOD)
if (mutant == 0 && current_state == 3) total = total + 1;
else begin
$display("Expecting STATE_3 as current state for 'GGT' input string! - FAILED");
err_exit(total, `EX4_TOTAL, `EX4_SCORE);
end
T = 0;
C = 1;
#(`CLK_PERIOD) C = 0;
if (mutant == 1) total = total + 1;
else begin
$display("Mutant should be found for 'GGTC' input string! - FAILED");
err_exit(total, `EX4_TOTAL, `EX4_SCORE);
end
if (mutant == 1 && current_state == 4) total = total + 1;
else begin
$display("Expecting STATE_4 as current state for 'GGTC' input string! - FAILED");
err_exit(total, `EX4_TOTAL, `EX4_SCORE);
end
succ_exit(total, `EX4_TOTAL, `EX4_SCORE);
end
always begin
#(`CLK_PERIOD / 2) clk = ~clk;
end
endmodule
| 6.874489 |
module test_example ();
// Inputs.
reg in;
// Outputs.
/* verilator lint_off UNUSED */
wire out;
/* verilator lint_on UNUSED */
// Initialize Unit Under Test (UUT).
example some_name (
.out(out),
.in (in)
);
initial begin
$dumpfile("waves.vcd");
$dumpvars(0, test_example);
// Initialize inputs.
in = 0;
// We wait 100 s for the global reset.
#100;
// We add stimuli.
#100 in = 1;
#100 in = 0;
#100;
end
endmodule
| 6.528766 |
module: exit_park
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_exit_park;
// Inputs
reg exit;
reg [2:0] token;
reg [2:0] pattern;
// Outputs
wire [7:0] park_location;
// Instantiate the Unit Under Test (UUT)
exit_park uut (
.exit(exit),
.token(token),
.pattern(pattern),
.park_location(park_location)
);
initial begin
exit = 0; token = 3'b000; pattern = 3'b000; #250; // park_location = zzzzzzzz
exit = 1; token = 3'b000; pattern = 3'b111; #250; // park_location = 10000000
exit = 1; token = 3'b100; pattern = 3'b110; #250; // park_location = 00000100
exit = 1; token = 3'b101; pattern = 3'b101; #250; // park_location = 00000001
end
endmodule
| 7.197993 |
module: expr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_expr;
// Inputs
reg clk;
reg clr;
reg [7:0] in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
expr uut (
.clk(clk),
.clr(clr),
.in(in),
.out(out)
);
initial begin
// Initialize Inputs
clk = 0;
clr = 0;
in = 0;
#1 clr = 1;
#1 clr = 0;
in = "1";
#2 in = "+";
#2 in = "1";
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #1 clk = ~clk;
endmodule
| 7.006903 |
module: ext
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_ext;
// Inputs
reg [15:0] imm;
reg [1:0] EOp;
// Outputs
wire [31:0] ext;
// Instantiate the Unit Under Test (UUT)
ext uut (
.imm(imm),
.EOp(EOp),
.ext(ext)
);
initial begin
// Initialize Inputs
imm = -10;
EOp = 3;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.228997 |
module test_fastcounter;
localparam NBITS = 9;
localparam NBITS_STAGE = 4;
reg clk = 0;
reg rst = 0;
reg [1:0] mode = 0;
reg dir = 0;
reg en = 0;
reg load = 0;
reg [NBITS-1:0] load_q = 0;
wire pend, nend, carry, carry_dly, epulse;
wire [NBITS-1:0] q;
reg en_gated = 0;
always @(posedge clk) begin
en_gated <= en_gated ? 1'b0 : en;
end
fastcounter #(
.NBITS(NBITS),
.NBITS_STAGE(NBITS_STAGE)
) dut (
.i_clk(clk),
.i_rst(rst),
//
.i_mode(mode),
.i_dir(dir),
.i_en(en_gated),
.i_load(load),
.i_load_q(load_q),
//
.o_end(pend),
.o_nend(nend),
.o_carry(carry),
.o_carry_dly(carry_dly),
.o_epulse(epulse),
//
.o_q(q)
);
always #5 clk = ~clk;
initial begin
$dumpfile("test_fastcounter.vcd");
$dumpvars;
// Reset
rst <= 1;
@(posedge clk);
rst <= 0;
//
// OVERFLOW
//
mode <= 2;
// Load
load_q <= 'h33;
load <= 1;
@(posedge clk);
load <= 0;
// Idle
repeat (15) @(posedge clk);
// Enable
en <= 1;
// Count
repeat (600) @(posedge clk);
// Change direction
dir <= 1;
// Count
repeat (600) @(posedge clk);
// Change direction
dir <= 0;
// Count
repeat (600) @(posedge clk);
//
// AUTORELOAD
//
mode <= 0;
// Load
load_q <= 'h33;
load <= 1;
@(posedge clk);
load <= 0;
// Idle
repeat (15) @(posedge clk);
// Enable
en <= 1;
// Count
repeat (150) @(posedge clk);
// Set reload to 1
load_q <= 1;
load <= 1;
@(posedge clk);
load <= 0;
// Count
repeat (10) @(posedge clk);
// Set reload to 0
load_q <= 0;
// Count
repeat (10) @(posedge clk);
//
// ONESHOT
//
mode <= 1;
en <= 0;
// Load
load_q <= 'h3F;
load <= 1;
@(posedge clk);
load <= 0;
// Idle
repeat (15) @(posedge clk);
// Enable
en <= 1;
// Count
repeat (150) @(posedge clk);
// Set reload to 5
load_q <= 5;
// Trigger
load <= 1;
@(posedge clk);
load <= 0;
// Wait
repeat (20) @(posedge clk);
// Trigger
load <= 1;
repeat (10) @(posedge clk);
load <= 0;
// Wait
repeat (20) @(posedge clk);
// Set reload to 1
load_q <= 1;
// Trigger
load <= 1;
@(posedge clk);
load <= 0;
// Wait
repeat (20) @(posedge clk);
// Trigger
load <= 1;
repeat (10) @(posedge clk);
load <= 0;
// Wait
repeat (20) @(posedge clk);
// Set reload to 0
load_q <= 0;
// Trigger
load <= 1;
@(posedge clk);
load <= 0;
// Wait
repeat (20) @(posedge clk);
// Trigger
load <= 1;
repeat (10) @(posedge clk);
load <= 0;
// Wait
repeat (20) @(posedge clk);
$finish;
end
endmodule
| 6.533355 |
module: fetch
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_fetch;
// Inputs
reg pcsrc;
reg mux1;
reg clk;
// Outputs
wire adderOutput;
wire instruction;
// Instantiate the Unit Under Test (UUT)
fetch uut (
.pcsrc(pcsrc),
.mux1(mux1),
.clk(clk),
.adderOutput(adderOutput),
.instruction(instruction)
);
initial begin
// Initialize Inputs
pcsrc = 0;
mux1 = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
mux1=5;
#100;
pcsrc=1;
#100;
pcsrc=0;
// Add stimulus here
end
always begin
#50;
clk=~clk;
end
endmodule
| 6.65392 |
module test_fetcher ();
// Inputs
reg clk;
reg rst;
reg [4:0] address;
// Outputs
/* verilator lint_off UNUSED */
wire [7:0] data;
/* verilator lint_off UNUSED */
// Instantiate the Unit Under Test (UUT)
fetcher uut (
.clk(clk),
.rst(rst),
.address(address[3:0]),
.data(data)
);
always #5 clk = ~clk;
initial begin
$dumpfile("waves.vcd");
$dumpvars(0, test_fetcher);
// Initialize Inputs
clk = 1;
rst = 1;
address = 5'bz;
// Wait for global reset to finish
#20;
// Add stimulus here
rst = 0;
for (address = 0; address < 16; address = address + 1) begin
#30;
end
for (address = 0; address < 16; address = address + 1) begin
#30;
end
$finish();
end
endmodule
| 6.856861 |
module test_FIFO_new ();
reg clk;
reg rstn;
reg input_valid;
wire input_enable;
wire output_valid;
reg output_enable;
reg [7:0] data_in;
wire [7:0] data_out;
FIFO_new obj_FIFO (
.clk(clk),
.rstn(rstn),
.input_valid(input_valid),
.input_enable(input_enable),
.output_enable(output_enable),
.output_valid(output_valid),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clk = 1'b0;
rstn = 1'b1;
#0.1 rstn = 1'b0;
#0.2 rstn = 1'b1;
end
initial begin
input_valid = 1;
output_enable = 0;
//0
data_in = 8'h6;
#2;
input_valid = 0;
#2;
input_valid = 1;
data_in = 8'h9;
//`
#2 data_in = 8'h1;
#2 data_in = 8'h2;
//2
#2 data_in = 8'h3;
#2 data_in = 8'h4;
//3
#2 data_in = 8'h5;
#2 data_in = 8'h6;
//4
#2 data_in = 8'h7;
#2 data_in = 8'h8;
//5
#2 data_in = 8'h9;
#2 data_in = 8'ha;
//6
#2 data_in = 8'hb;
#2 data_in = 8'hc;
// 7
#2 data_in = 8'hf;
#2 data_in = 8'he;
// output
#2;
input_valid = 0;
output_enable = 1;
#18;
input_valid = 1;
output_enable = 0;
//0
data_in = 8'h6;
#2;
input_valid = 0;
#2;
input_valid = 1;
data_in = 8'h9;
//`
#2 data_in = 8'h0;
#2 data_in = 8'h9;
//2
#2 data_in = 8'h8;
#2 data_in = 8'h7;
//3
#2 data_in = 8'h6;
#2 data_in = 8'h5;
//4
#2 data_in = 8'h4;
#2 data_in = 8'h3;
//5
#2 data_in = 8'h2;
#2 data_in = 8'h1;
//6
#2 data_in = 8'h1;
#2 data_in = 8'h2;
// 7
#2 data_in = 8'h2;
#2 data_in = 8'h3;
// output
#2;
input_valid = 0;
output_enable = 1;
#18;
input_valid = 1;
end
always begin
#1 clk = ~clk;
end
endmodule
| 7.146648 |
module test_FIFO_random ();
reg clk;
reg rstn;
reg input_valid;
wire input_enable;
wire output_valid;
reg output_enable;
reg [3:0] data_in;
wire [7:0] data_out;
FIFO obj_FIFO (
.clk(clk),
.rstn(rstn),
.input_valid(input_valid),
.input_enable(input_enable),
.output_enable(output_enable),
.output_valid(output_valid),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clk = 1'b0;
rstn = 1'b1;
#0.1 rstn = 1'b0;
#0.2 rstn = 1'b1;
input_valid = 0;
output_enable = 0;
data_in = 4'h0;
end
always begin
#1 clk = ~clk;
end
always begin
#2;
input_valid = $random() % 2;
output_enable = $random() % 2;
data_in = $random() % 16;
end
endmodule
| 7.409369 |
module Test_FIR ();
reg [15:0] tmp_test = 0;
wire [15:0] data_out;
reg clk = 0, reset = 0;
reg signed [15:0] data_in;
FIR uut (
.clk(clk),
.data_in(data_in),
.reset(reset),
.data_out(data_out)
);
always #5 clk = ~clk;
integer in, out;
initial begin
#10 reset = 1;
#30 reset = 0;
in = $fopen("Audio_Noisy_Binary.txt", "r");
out = $fopen("output.txt", "w");
while (!$feof(
in
)) begin
@(negedge clk);
$fscanf(in, "%b\n", data_in);
$fwrite(out, "%b\n", data_out);
if ($feof(in)) $display("finishhhhhhhhed_1\n");
end
#20 $fclose(in);
$fclose(out);
end
endmodule
| 6.862985 |
module test_fir128x16x18;
// Inputs
reg [2:0] ioaddr;
reg iocs;
reg [15:0] din;
reg iowr;
reg iord;
reg clk;
reg rst;
// Outputs
wire [15:0] dout;
// Instantiate the Unit Under Test (UUT)
dfir128x16x18 uut (
.ioaddr(ioaddr),
.iocs(iocs),
.din(din),
.iowr(iowr),
.iord(iord),
.dout(dout),
.clk(clk),
.rst(rst)
);
initial begin
// Initialize Inputs
ioaddr = 0;
iocs = 0;
din = 0;
iowr = 0;
iord = 0;
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// Reset
#5 clk = 0;
rst = 1;
#5 clk = 1;
#5 clk = 0;
rst = 0;
#5 clk = 1;
// Load Coefficients
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 5;
din = 0;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 4;
din = 2048;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 4;
din = 4096;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 4;
din = 8192;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 4;
din = 16384;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 4;
din = 8192;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 4;
din = 4096;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 4;
din = 2048;
#5 clk = 1;
#5 clk = 0;
iocs = 0;
iowr = 0;
ioaddr = 0;
din = 0;
#5 clk = 1;
// Test
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 0;
din = 16384; // data
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 2;
din = 16'h0700; // start
#5 clk = 1;
repeat (7) begin
#5 clk = 0;
iocs = 0;
iowr = 0;
ioaddr = 0;
din = 0;
#5 clk = 1;
end
#5 clk = 0;
iocs = 1;
iord = 1;
ioaddr = 2; // read status
#5 clk = 1;
#5 clk = 0;
iocs = 0;
iord = 0;
ioaddr = 0;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iord = 1;
ioaddr = 0; // read result
#5 clk = 1;
#5 clk = 0;
iocs = 0;
iord = 0;
ioaddr = 0;
#5 clk = 1;
repeat (7) begin
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 0;
din = 0; // data
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iowr = 1;
ioaddr = 2;
din = 16'h0700; // start
#5 clk = 1;
repeat (7) begin
#5 clk = 0;
iocs = 0;
iowr = 0;
ioaddr = 0;
din = 0;
#5 clk = 1;
end
#5 clk = 0;
iocs = 1;
iord = 1;
ioaddr = 2; // read status
#5 clk = 1;
#5 clk = 0;
iocs = 0;
iord = 0;
ioaddr = 0;
#5 clk = 1;
#5 clk = 0;
iocs = 1;
iord = 1;
ioaddr = 0; // read result
#5 clk = 1;
#5 clk = 0;
iocs = 0;
iord = 0;
ioaddr = 0;
#5 clk = 1;
end
#5 clk = 0;
end
endmodule
| 6.862398 |
module Test_FIR;
reg [15:0] din;
reg clk, reset;
wire [15:0] dout_normal, dout_pipeline;
FIR_NORMAL n_myfir (
.reset(reset),
.clk(clk),
.data_in(din),
.data_out(dout_normal)
);
FIR_PIPELINE myfir (
.reset(reset),
.clk(clk),
.data_in(din),
.data_out(dout_pipeline)
);
always #10 clk = ~clk;
integer j, i, out;
reg [15:0] mem[1:441000];
initial begin
j = 0;
clk = 0;
reset = 1;
out = $fopen(
"C:/Users/ALI-PC/Desktop/lessons/verilog HDL/final project/project/02/pipeline/out/out.bin",
"wb"
);
$readmemb(
"C:/Users/ALI-PC/Desktop/lessons/verilog HDL/final project/project/02/pipeline/Audio_Noisy_Binary.txt",
mem);
#25 reset = 0;
#20
for (i = 1; i <= 441000; i = i + 1) begin
#20 din = mem[i];
end
end
always @(posedge clk) begin
if (1) begin
j = j + 1;
if (dout_pipeline !== 16'bx) $fwrite(out, "%b\n", dout_pipeline);
else $fwrite(out, "0000000000000000\n");
end
if (j == 441001) $finish;
end
endmodule
| 6.803173 |
module Test_FIR ();
reg [15:0] tmp_test = 0;
wire [15:0] data_out;
reg clk = 0, reset = 0;
reg signed [15:0] data_in;
reg [5:0] counter = 0;
fir uut (
.clk(clk),
.data_in(data_in),
.reset(reset),
.data_out(data_out)
);
always #5 clk = ~clk;
integer in, out;
initial begin
#10 reset = 1;
data_in = 0;
#30 reset = 0;
in = $fopen("Audio_Noisy_Binary.txt", "r");
out = $fopen("output.txt", "w");
while (!$feof(
in
)) begin
@(negedge clk);
counter <= (counter + 1) % 20;
if (counter == 19) begin
$fscanf(in, "%b\n", data_in);
$fwrite(out, "%b\n", data_out);
if ($feof(in)) $display("finishhhhhhhhed_1\n");
end
end
#20 $fclose(in);
$fclose(out);
end
endmodule
| 6.862985 |
module test_flash_sword (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// flash interfaces
output wire [1:0] flash_ce_n,
output wire flash_rst_n,
output wire flash_oe_n,
output wire flash_we_n,
output wire flash_wp_n,
input wire [1:0] flash_ready,
output wire [ADDR_BITS-1:2] flash_addr,
input wire [31:0] flash_din,
output wire [31:0] flash_dout
);
parameter CLK_FREQ = 100, ADDR_BITS = 25;
wire busy, ack;
wire [31:0] dout;
reg [31:0] data_buf;
reg cs_prev;
always @(posedge clk_bus) begin
if (rst) cs_prev <= 0;
else cs_prev <= cs;
end
reg cs_buf;
always @(posedge clk_bus) begin
if (rst) cs_buf <= 0;
else if (cs & ~cs_prev) cs_buf <= 1;
else if (ack) cs_buf <= 0;
end
/*flash_core #(
.CLK_FREQ(CLK_FREQ),
.ADDR_BITS(ADDR_BITS)
) FLASH_CORE (
.clk(clk),
.rst(rst),
.cs(~cs_prev & cs),
.addr({14'b0, addr}),
.burst(1'b0),
.dout(dout),
.busy(busy),
.ack(ack),
.flash_ce_n(flash_ce_n),
.flash_rst_n(flash_rst_n),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n),
.flash_wp_n(flash_wp_n),
.flash_ready(flash_ready),
.flash_addr(flash_addr),
.flash_din(flash_din),
.flash_dout(flash_dout)
);*/
wb_flash_sword #(
.CLK_FREQ(CLK_FREQ),
.ADDR_BITS(ADDR_BITS),
.HIGH_ADDR(0),
.BUF_ADDR_BITS(4)
) WB_FLASH (
.clk(clk),
.rst(rst),
.flash_busy(busy),
.flash_ce_n(flash_ce_n),
.flash_rst_n(flash_rst_n),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n),
.flash_wp_n(flash_wp_n),
.flash_ready(flash_ready),
.flash_addr(flash_addr),
.flash_din(flash_din),
.flash_dout(flash_dout),
.wbs_clk_i(clk_bus),
.wbs_cyc_i(cs_buf),
.wbs_stb_i(cs_buf),
.wbs_addr_i({22'b0, addr}),
.wbs_cti_i(3'b0),
.wbs_bte_i(2'b0),
.wbs_sel_i(4'b1111),
.wbs_we_i(1'b0),
.wbs_data_i(32'b0),
.wbs_data_o(dout),
.wbs_ack_o(ack)
);
/*wb_bpi_flash WB_BPI_FLASH (
.wbs_clk_i(clk_bus),
.rst(rst),
.wbs_cs_i(cs_buf),
.wbs_addr_i(addr),
.wbs_sel_i(4'b1111),
.wbs_data_i(32'h12345678),
.wbs_we_i(we),
.wbs_data_o(dout),
.wbs_ack_o(ack),
.flash_a(flash_addr),
.flash_ce_n0(flash_ce_n[0]),
.flash_ce_n1(flash_ce_n[1]),
.flash_oe_n(flash_oe_n),
.flash_we_n(flash_we_n),
.flash_dq_i(flash_din),
.flash_dq_o(flash_dout),
.flash_dq_t(flash_wp_n),
.flash_rdy0(flash_ready[0]),
.flash_rdy1(flash_ready[1]),
.flash_rstn(flash_rst_n),
.rcnt()
);*/
always @(posedge clk_bus) begin
if (rst) data_buf <= 0;
else if (ack) data_buf <= dout;
end
assign data = data_buf;
assign state = {
busy, flash_ce_n[0], flash_rst_n, flash_oe_n, flash_we_n, flash_ready[0], flash_ready[1], ack
};
endmodule
| 7.30317 |
module: flip_flop
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_flip_flop;
// Inputs
reg clk,rst, ena;
reg d;
// Outputs
wire q;
// Instantiate the Unit Under Test (UUT)
flip_flop uut (
.clk(clk), .rst(rst), .ena(ena),
.d(d),
.q(q)
);
//create a clock
always #5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
d = 0;
rst = 1;
ena = 0;
repeat (2) @(posedge clk);
rst = 0;
ena = 1;
repeat (2) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
repeat (3) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
ena = 0;
repeat (2) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
repeat (3) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
ena = 1;
repeat (2) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
repeat (3) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
repeat (1) @(negedge clk) d = ~d;
repeat (4) @(posedge clk);
$finish;
end
endmodule
| 6.626827 |
module: alu
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_alu;
// Inputs
reg [31:0] input1;
reg [31:0] input2;
reg [3:0] aluCtr;
// Outputs
wire zero;
wire [31:0] aluRes;
// Instantiate the Unit Under Test (UUT)
alu uut (
.input1(input1),
.input2(input2),
.aluCtr(aluCtr),
.zero(zero),
.aluRes(aluRes)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
aluCtr = 0;
// Wait 100 ns for global reset to finish
#100;
#100 aluCtr = 4'b0000;
#100 input1 = 32'b00000000000000000000000011111111;
#100 input2 = 32'b00000000000000000000000001111111;
#100 aluCtr = 4'b0001;
#100 input1 = 32'b00000000000000000000000000111111;
#100 aluCtr = 4'b0010;
#100 input2 = 32'b00000000000000000000000001101111;
#100 aluCtr = 4'b0110;
#100 input1 = 32'b00000000000000000000000001111000;
#100 aluCtr = 4'b0111;
#100 aluCtr = 4'b1100;
// Add stimulus here
end
endmodule
| 7.023594 |
module: aluCtr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_aluCtr;
// Inputs
reg [1:0] aluOp;
reg [5:0] funct;
// Outputs
wire [3:0] aluCtr;
// Instantiate the Unit Under Test (UUT)
aluCtr uut (
.aluOp(aluOp),
.funct(funct),
.aluCtr(aluCtr)
);
initial begin
// Initialize Inputs
aluOp = 0;
funct = 0;
// Wait 100 ns for global reset to finish
#100;
#100 {aluOp, funct} = 8'b00000000;
#100 {aluOp, funct} = 8'b01000000;
#100 {aluOp, funct} = 8'b10000000;
#100 {aluOp, funct} = 8'b10000010;
#100 {aluOp, funct} = 8'b10000100;
#100 {aluOp, funct} = 8'b10000101;
#100 {aluOp, funct} = 8'b10001010;
// Add stimulus here
end
endmodule
| 6.718252 |
module: Ctr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_Ctr;
// Inputs
reg [5:0] opCode;
// Outputs
wire regDst;
wire aluSrc;
wire memToReg;
wire regWrite;
wire memRead;
wire memWrite;
wire branch;
wire [1:0] aluOp;
wire jump;
// Instantiate the Unit Under Test (UUT)
Ctr uut (
.opCode(opCode),
.regDst(regDst),
.aluSrc(aluSrc),
.memToReg(memToReg),
.regWrite(regWrite),
.memRead(memRead),
.memWrite(memWrite),
.branch(branch),
.aluOp(aluOp),
.jump(jump)
);
initial begin
// Initialize Inputs
opCode = 0;
// Wait 100 ns for global reset to finish
#100;
#100 opCode = 6'b000000;
#100 opCode = 6'b000100;
#100 opCode = 6'b100011;
#100 opCode = 6'b101011;
#100 opCode = 6'b000010;
// Add stimulus here
end
endmodule
| 7.12312 |
module: date_memory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_date_memory;
// Inputs
reg clock_in;
reg [31:0] address;
reg [31:0] writeData;
reg memWrite;
reg memRead;
// Outputs
wire [31:0] readData;
// Instantiate the Unit Under Test (UUT)
date_memory uut (
.clock_in(clock_in),
.address(address),
.writeData(writeData),
.memWrite(memWrite),
.memRead(memRead),
.readData(readData)
);
always
begin
#100;
clock_in=~clock_in;
end
initial begin
// Initialize Inputs
clock_in = 0;
address = 0;
writeData = 0;
memWrite = 0;
memRead = 0;
// Wait 100 ns for global reset to finish
// Add stimulus here
#185;
memWrite=1'b1;
address=15;
writeData=-65536;
#250;
memRead = 1'b1;
memWrite = 1'b0;
end
//always #100 clock_in=~clock_in;
endmodule
| 7.241115 |
module: signext
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_signext;
// Inputs
reg [15:0] inst;
// Outputs
wire [31:0] data;
// Instantiate the Unit Under Test (UUT)
signext uut (
.inst(inst),
.data(data)
);
initial begin
// Initialize Inputs
inst = 0;
// Wait 100 ns for global reset to finish
#100;
#100 inst = 16'b0010001110101101;
#300 inst = 16'b1010001110101101;
// Add stimulus here
end
endmodule
| 7.114626 |
module: Top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_top;
// Inputs
reg CLOCK_IN;
reg RESET;
reg [3:0] SWITCH;
// Outputs
wire [3:0] LED;
// Instantiate the Unit Under Test (UUT)
Top uut (
.CLOCK_IN(CLOCK_IN),
.RESET(RESET),
.SWITCH(SWITCH),
.LED(LED)
);
initial begin
// Initialize Inputs
CLOCK_IN = 0;
RESET = 1;
SWITCH = 0;
// Wait 100 ns for global reset to finish
#100;
RESET=0;
// Add stimulus here
end
always
#20 CLOCK_IN=~CLOCK_IN;
endmodule
| 7.357405 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_whole;
// Inputs
reg clk;
reg [7:0] sw;
reg [7:0] sww;
reg [3:0] push;
// Outputs
wire [7:0] led;
wire [3:0] digit_anode;
wire [7:0] display;
wire [7:0] anode;
wire [7:0] segment;
// Instantiate the Unit Under Test (UUT)
top uut (
.clk(clk),
.sw(sw),
.sww(sww),
.push(push),
.led(led),
.digit_anode(digit_anode),
.display(display),
.anode(anode),
.segment(segment)
);
initial begin
// Initialize Inputs
clk = 0;
sw = 0;
sww = 0;
push = 0;
// Wait 100 ns for global reset to finish
#10;
push=4'b0100;
#200;
push=4'b0000;
#200;
push=4'b0100;
#200;
// Add stimulus here
end
always
begin
clk=0;
#1;
clk=1;
#1;
end
endmodule
| 7.115105 |
module test_fp_ip (
input wire [31:0] a, // a.a
input wire acc, // acc.acc
input wire areset, // areset.reset
input wire [31:0] b, // b.b
input wire clk, // clk.clk
input wire [ 0:0] en, // en.en
output wire [31:0] q // q.q
);
fp_mac mac (
.a(a),
.b(b),
.clk(clk),
.areset(areset),
.en(en),
.q(q),
.acc(acc)
);
endmodule
| 6.672203 |
module test_fp_ip (
input wire clk,
input wire rst,
input wire [2:0] ctrl,
input wire output_ctrl,
inout wire [31:0] data,
input wire do_act,
output [4:0] counter,
output [11:0] ArrWgt_Rd,
output [11:0] ArrWgt_Wr,
output [31:0] ArrWeights_1,
output fp_mac_acc,
output [31:0] fp_mac_a,
output [31:0] fp_mac_b,
output [31:0] fp_mac_q,
output fp_add_en,
output [31:0] fp_add_a,
output [31:0] fp_add_b,
output [31:0] fp_add_output,
output fp_div_en,
output [31:0] fp_div_a,
output [31:0] fp_div_b,
output [31:0] fp_div_output
);
pe PE (
.Clock(clk),
.Reset(rst),
.Ctrl(ctrl),
.OutputCtrl(output_ctrl),
.Data(data),
.EnableAct(do_act),
.counter(counter),
.ArrWgt_Rd(ArrWgt_Rd),
.ArrWgt_Wr(ArrWgt_Wr),
.ArrWeights_1(ArrWeights_1),
.fp_mac_acc(fp_mac_acc),
.fp_mac_a(fp_mac_a),
.fp_mac_b(fp_mac_b),
.fp_mac_output(fp_mac_q),
.fp_add_en(fp_add_en),
.fp_add_a(fp_add_a),
.fp_add_b(fp_add_b),
.fp_add_output(fp_add_output),
.fp_div_en(fp_div_en),
.fp_div_a(fp_div_a),
.fp_div_b(fp_div_b),
.fp_div_output(fp_div_output)
);
endmodule
| 6.672203 |
module
// Methodology: For this to work, change the localparam max in freq_counter to match the clock cycle
// here. The testbench creates a clock signal and a test signal to use in the
// freq_counter module. To see the results, run the simulation for a little while
// longer until the freq_counter's counter has reached the localparam max.
module freq_count_tb();
wire [7:0] freq;
reg clk, in;
initial begin
clk = 0;
in = 0;
// Test frequency is 145 Hz
forever #6897000 in = !in;
end
// Clock is 1000 Hz
always
#1000000 clk = !clk;
freq_counter tb1(
.CLK(clk),
.IN(in),
.freq(freq)
);
endmodule
| 8.654609 |
module test_fsm;
// Inputs
reg clk;
reg reset;
reg [25:0] rom_q;
// Outputs
wire [8:0] rom_addr;
wire [5:0] ram_a_addr;
wire [5:0] ram_b_addr;
wire ram_b_w;
wire [10:0] pe;
wire done;
// Instantiate the Unit Under Test (UUT)
FSM uut (
.clk(clk),
.reset(reset),
.rom_addr(rom_addr),
.rom_q(rom_q),
.ram_a_addr(ram_a_addr),
.ram_b_addr(ram_b_addr),
.ram_b_w(ram_b_w),
.pe(pe),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#(`P / 2);
reset = 1;
#(`P);
reset = 0;
@(posedge done);
$finish;
end
initial #100 forever #(`P / 2) clk = ~clk;
/* rom code format
* wire [5:0] dest, src1, src2, times; wire [1:0] op;
* assign {dest, src1, op, times, src2} = rom_q;
*/
parameter ADD = 2'd0, SUB = 2'd1, CUBIC = 2'd2, MULT = 2'd3;
always @(posedge clk)
case (rom_addr)
0: rom_q <= {6'd10, 6'd11, ADD, 6'd1, 6'd12};
1: rom_q <= {6'd20, 6'd21, SUB, 6'd1, 6'd22};
2: rom_q <= {6'd30, 6'd31, CUBIC, 6'd5, 6'd32};
3: rom_q <= {6'd40, 6'd41, MULT, 6'd33, 6'd42};
default: rom_q <= 0;
endcase
endmodule
| 6.638073 |
module test_fsyn;
// Inputs
reg [15:0] mag;
reg [15:0] frq;
reg fmv;
reg clk;
// Outputs
wire [15:0] avgfrq;
wire fcd;
// Instantiate the Unit Under Test (UUT)
fsyn uut (
.mag(mag),
.frq(frq),
.fmv(fmv),
.avgfrq(avgfrq),
.fcd(fcd),
.clk(clk),
.nfl(0),
.sfs(0)
);
initial begin
// Initialize Inputs
mag = 0;
frq = 0;
fmv = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// no signal
repeat (2048) begin
#5 clk = 0;
fmv = 1;
mag = 0;
frq = 0;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// on frequency low mag. signal (-30 dBFS mag., on frq.)
repeat (2048) begin
#5 clk = 0;
fmv = 1;
mag = 1024;
frq = 0;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// off frequency signal (-18 dBFS mag., +1/4 FS frq.)
repeat (2048) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = 16384;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// near frequency low mag. signal (-18 dBFS mag., +1/64 FS frq.)
repeat (2048) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = 1024;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// off frequency signal (-30 dBFS mag., +1/4 FS frq.)
repeat (64) begin
#5 clk = 0;
fmv = 1;
mag = 1024;
frq = 16384;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// near frequency signal (-18 dBFS mag., -1/64 FS frq.)
repeat (320) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = -1024;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// exact frequency signal (-18 dBFS mag. ctr. frq.)
repeat (512) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = 0;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// near frequency signal (-18 dBFS mag., +1/64 FS frq.)
repeat (256) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = 1024;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// exact frequency signal (-18 dBFS mag., ctr. frq.)
repeat (256) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = 0;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// near frequency signal (-18 dBFS mag., -1/256 FS frq.)
repeat (256) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = -256;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// near frequency signal (-18 dBFS mag., -1/128 FS frq.)
repeat (256) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = -512;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// near frequency signal (-18 dBFS mag., -3/256 FS frq.)
repeat (256) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = -768;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// near frequency signal (-18 dBFS mag., -1/64 FS frq.)
repeat (256) begin
#5 clk = 0;
fmv = 1;
mag = 4096;
frq = -1024;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
// no signal
repeat (2048) begin
#5 clk = 0;
fmv = 1;
mag = 0;
frq = 0;
#5 clk = 1;
#5 clk = 0;
fmv = 0;
#5 clk = 1;
end
end
endmodule
| 7.263405 |
module ALUControl (
ALUOp,
Funct,
ALUOpcode_MC
);
output reg [2:0] ALUOp;
input [2:0] ALUOpcode_MC;
input [3:0] Funct;
always @(*) begin
if (ALUOpcode_MC == 3'b100) begin
case (Funct)
4'b0001: ALUOp <= 3'b100;
4'b0010: ALUOp <= 3'b101;
4'b0011: ALUOp <= 3'b110;
default: ALUOp <= 3'bxxx;
endcase
end else ALUOp <= ALUOpcode_MC;
end
endmodule
| 8.639118 |
module ALU_unit (
A,
B,
ALUOp,
out,
zero
);
input [15:0] A, B;
input [2:0] ALUOp;
output reg [15:0] out;
output zero;
integer i, count;
always @(*) begin
count = B;
if (ALUOp == 3'b000) begin
out = A + B;
end
if (ALUOp == 3'b001) begin
out = A - B;
end
if (ALUOp == 3'b010) begin
out = ~(A & B);
end
if (ALUOp == 3'b011) begin
out = (A | B);
end
if (ALUOp == 3'b100) begin
out = A << B;
end
if (ALUOp == 3'b101) begin
out = A >> B;
end
if (ALUOp == 3'b110) begin
out = A >>> B;
end
end
assign zero = (out == 16'b0);
endmodule
| 6.585557 |
module Register_File (
ReadReg1,
ReadReg2,
ReadReg3,
ReadReg4,
ReadReg5,
WriteReg,
WriteData,
ReadData1,
ReadData2,
ReadData3,
ReadData4,
ReadData5,
RegWrite
);
input [3:0] ReadReg1, ReadReg2, ReadReg3, ReadReg4, ReadReg5, WriteReg;
input [15:0] WriteData;
input RegWrite, clk;
output reg [15:0] ReadData1 = 0, ReadData2 = 0, ReadData3 = 0, ReadData4 = 0, ReadData5 = 0;
integer i;
reg [15:0] Registers[0:15];
initial begin
for (i = 0; i < 16; i = i + 1) Registers[i] = 0;
end
always @(*) begin
Registers[0] = 16'd0;
if (RegWrite == 1'b0) begin
ReadData1 = Registers[ReadReg1];
ReadData2 = Registers[ReadReg2];
ReadData3 = Registers[ReadReg3];
ReadData4 = Registers[ReadReg4];
ReadData5 = Registers[ReadReg5];
end else begin
Registers[WriteReg] <= WriteData;
/*for(i=0;i<16;i=i+1)
$display("%d",Registers[i]);*/
end
end
endmodule
| 6.725474 |
module Instruction_Register (
clk,
D,
WriteEnable,
m,
n,
x,
y,
z,
b1,
b2,
b3,
b4,
b5,
opcode,
funct
);
input [15:0] D;
input WriteEnable, clk;
reg [15:0] Instr;
output [3:0] m, n, x, y, z;
output [15:0] b1, b2, b3, b4, b5;
output [3:0] funct;
output [3:0] opcode;
always @(posedge clk) begin
if (WriteEnable == 1'b1) begin
Instr = D;
end
end
assign x = Instr[3:0];
assign y = Instr[7:4];
assign z = Instr[11:8];
assign m = {2'b11, Instr[11:10]};
assign n = {2'b10, Instr[9:8]};
assign b1 = {
Instr[7], Instr[7], Instr[7], Instr[7], Instr[7], Instr[7], Instr[7], Instr[7], Instr[7:0]
};
assign funct = Instr[3:0];
assign opcode = Instr[15:12];
assign b5 = {
Instr[7], Instr[7], Instr[7], Instr[7], Instr[7], Instr[7], Instr[7], Instr[7:0], 1'b0
};
assign b2 = {8'b0, Instr[7:0]};
assign b3 = {12'b0, Instr[7:4]};
assign b4 = {Instr[11], Instr[11], Instr[11], Instr[11], Instr[11:0]};
endmodule
| 6.510365 |
module Program_Counter (
CLK,
PCSource,
PCSrc0,
PCSrc1,
PCSrc2,
PCWriteInput,
PC,
PCWrite
);
input [1:0] PCSource;
input PCWrite;
input [15:0] PCSrc0, PCSrc1, PCSrc2;
input PCWriteInput, CLK;
output reg [15:0] PC = 0;
always @(posedge CLK) begin
if (PCWriteInput == 1'b1) begin
case (PCSource)
2'd0: PC = PCSrc0;
2'd1: PC = PCSrc1;
2'd2: PC = PCSrc2;
endcase
end
end
endmodule
| 6.785422 |
module test_gate;
reg e1, e2;
wire out_not, out_nor, out_nand, out_and, out_or, out_xor, out_buf, out_xnor;
gate_not not_inst (
out_not,
e1
);
gate_nor nor_inst (
out_nor,
{e2, e1}
);
gate_nand nand_inst (
out_nand,
{e2, e1}
);
gate_and and_inst (
out_and,
{e2, e1}
);
gate_or or_inst (
out_or,
{e2, e1}
);
gate_xor xor_inst (
out_xor,
{e2, e1}
);
gate_buf buf_inst (
out_buf,
e1
);
gate_xnor xnor_inst (
out_xnor,
{e2, e1}
);
initial begin
$dumpfile("signal_test_gate.vcd");
$dumpvars;
$monitor(
"time %d\ne1\t%b\ne2\t%b\nnot\t%b\nnor\t%b\nnand\t%b\nand\t%b\nor\t%b\nbuf\t%b\nxor\t%b\nxnor\t%b\n\n",
$time, e1, e2, out_not, out_nor, out_nand, out_and, out_or, out_buf, out_xor, out_xnor);
e1 <= 0;
e2 <= 0;
#10;
e1 <= 1;
#10;
e1 <= 0;
e2 <= 1;
#10;
e1 <= 1;
#10;
end
endmodule
| 7.566241 |
module TOP;
//ALU inputs
reg [31:0] a, b;
wire [31:0] p;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 32'hffffffff;
b = 32'h00000000;
#`cycle //1
if(p != (a & b))
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 32'ha47ba47b;
b = 32'h5c915c91;
#`cycle //3
if(p != (a & b))
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 32'hbcdabcda;
b = 32'h79867986;
#`cycle //5
if(p != (a & b))
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 32'h96579657;
b = 32'h34563456;
#`cycle //7
if(p != (a & b))
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("generate32.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(error)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, propagate1 = %x, correct propagate1 = %x",
$time, a, b, p, (a & b));
generate32 generate32_test(p, a, b);
endmodule
| 7.259416 |
module test_gmii #(
parameter DATA_WIDTH = 8
) (
input wire clk,
input wire rst,
inout wire [DATA_WIDTH-1:0] gmii_d,
inout wire gmii_er,
inout wire gmii_en,
inout wire gmii_clk_en,
inout wire gmii_mii_sel
);
endmodule
| 6.949965 |
module and2 (
A,
A_b_i,
A_b_o,
A_b_o2
);
//ports
input [7:0] A_b_i;
output [7:0] A_b_o;
output [7:0] A_b_o2;
input A;
//wires
wire [7:0] A_b_i;
wire [7:0] A_b_o;
wire [7:0] A_b_o2;
wire A;
endmodule
| 6.704587 |
module: Goomba
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_goomba;
// Inputs
reg clk;
reg rstn;
reg initial_show;
reg collapsion_impulse;
reg press_impulse;
// Outputs
wire [5:0] id;
wire oriental;
wire [10:0] w;
wire [10:0] h;
wire live;
// Instantiate the Unit Under Test (UUT)
Goomba #(.press_duration(6)) uut(
.clk(clk),
.rstn(rstn),
.initial_show(initial_show),
.collapsion_impulse(collapsion_impulse),
.press_impulse(press_impulse),
.id(id),
.oriental(oriental),
.w(w),
.h(h),
.live(live)
);
initial begin
// Initialize Inputs
rstn = 1;
initial_show = 1;
collapsion_impulse = 0;
press_impulse = 0;
#4;
rstn = 0;
// Wait 100 ns for global reset to finish
#100;
collapsion_impulse = 1;
#50;
press_impulse = 1;
// Add stimulus here
end
always begin
clk = 1;
#2;
clk = 0;
#2;
end
endmodule
| 6.961079 |
module TOP;
//ALU inputs
reg g_in_high, p_in_high, g_in_low, p_in_low;
wire g_out, p_out;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
g_in_high = 0;
p_in_high = 0;
g_in_low = 0;
p_in_low = 0;
#`cycle //1
if(p_out != (p_in_high & p_in_low) || g_out != ((p_in_high & g_in_low) | g_in_high))
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
g_in_high = 1;
p_in_high = 0;
g_in_low = 0;
p_in_low = 0;
#`cycle //3
if(p_out != (p_in_high & p_in_low) || g_out != ((p_in_high & g_in_low) | g_in_high))
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
g_in_high = 0;
p_in_high = 1;
g_in_low = 0;
p_in_low = 0;
#`cycle //5
if(p_out != (p_in_high & p_in_low) || g_out != ((p_in_high & g_in_low) | g_in_high))
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
g_in_high = 0;
p_in_high = 1;
g_in_low = 1;
p_in_low = 1;
#`cycle //7
if(p_out != (p_in_high & p_in_low) || g_out != ((p_in_high & g_in_low) | g_in_high))
begin
error_free = 0;
error = 1;
end
#`error_time //8
error = 0;
g_in_high = 0;
p_in_high = 1;
g_in_low = 1;
p_in_low = 0;
#`cycle //9
if(p_out != (p_in_high & p_in_low) || g_out != ((p_in_high & g_in_low) | g_in_high))
begin
error_free = 0;
error = 1;
end
#`error_time //10
error = 0;
g_in_high = 0;
p_in_high = 0;
g_in_low = 1;
p_in_low = 1;
#`cycle //11
if(p_out != (p_in_high & p_in_low) || g_out != ((p_in_high & g_in_low) | g_in_high))
begin
error_free = 0;
error = 1;
end
#`error_time //12
error = 0;
g_in_high = 0;
p_in_high = 1;
g_in_low = 0;
p_in_low = 0;
#`cycle //13
if(p_out != (p_in_high & p_in_low) || g_out != ((p_in_high & g_in_low) | g_in_high))
begin
error_free = 0;
error = 1;
end
#`error_time //14
error = 0;
g_in_high = 1;
p_in_high = 0;
g_in_low = 1;
p_in_low = 1;
#`cycle //15
if(p_out != (p_in_high & p_in_low) || g_out != ((p_in_high & g_in_low) | g_in_high))
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("gp_group1.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(error)
if(error == 1)
$strobe ("time: %0d found error at: p_in_low = %x, g_in_low = %x, p_in_high = %x, g_in_high = %x, p_out = %x, g_out = %x",
$time, p_in_low, g_in_low, p_in_high, g_in_high, p_out, g_out);
gp_group1 test_gp_group1(g_out, p_out, g_in_high, p_in_high, g_in_low, p_in_low);
endmodule
| 7.259416 |
module test_hexToBcd ();
reg [7:0] hex = 0;
wire [7:0] bcd;
hexToBcd h2b (
bcd,
hex
);
initial begin
#5 hex = 8'd10;
#5 hex = 8'd30;
#5 $finish;
end
endmodule
| 6.700443 |
module test_hvsync_top (
input wire [0 : 0] clk, // clock
input wire [0 : 0] reset, // reset
output wire [0 : 0] hsync, // horizontal sync
output wire [0 : 0] vsync, // vertical sync
output wire [2 : 0] rgb // RGB
);
/*******************************************************
* WIRE AND REG DECLARATION *
*******************************************************/
wire [ 0 : 0] display_on;
wire [15 : 0] hpos;
wire [15 : 0] vpos;
/*******************************************************
* ASSIGNMENT *
*******************************************************/
assign rgb = {
display_on && (((hpos & 7) == 0) || ((vpos & 7) == 0)),
display_on && vpos[4],
display_on && hpos[4]
};
/*******************************************************
* MODULE INSTANCES *
*******************************************************/
hvsync_generator hvsync_gen (
.clk (clk),
.reset (reset),
.hsync (hsync),
.vsync (vsync),
.display_on(display_on),
.hpos (hpos),
.vpos (vpos)
);
endmodule
| 7.126708 |
module test_i2c_master;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [6:0] s_axis_cmd_address = 0;
reg s_axis_cmd_start = 0;
reg s_axis_cmd_read = 0;
reg s_axis_cmd_write = 0;
reg s_axis_cmd_write_multiple = 0;
reg s_axis_cmd_stop = 0;
reg s_axis_cmd_valid = 0;
reg [7:0] s_axis_data_tdata = 0;
reg s_axis_data_tvalid = 0;
reg s_axis_data_tlast = 0;
reg m_axis_data_tready = 0;
reg scl_i = 1;
reg sda_i = 1;
reg [15:0] prescale = 0;
reg stop_on_idle = 0;
// Outputs
wire s_axis_cmd_ready;
wire s_axis_data_tready;
wire [7:0] m_axis_data_tdata;
wire m_axis_data_tvalid;
wire m_axis_data_tlast;
wire scl_o;
wire scl_t;
wire sda_o;
wire sda_t;
wire busy;
wire bus_control;
wire bus_active;
wire missed_ack;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_cmd_address, s_axis_cmd_start, s_axis_cmd_read,
s_axis_cmd_write, s_axis_cmd_write_multiple, s_axis_cmd_stop, s_axis_cmd_valid,
s_axis_data_tdata, s_axis_data_tvalid, s_axis_data_tlast, m_axis_data_tready,
scl_i, sda_i, prescale, stop_on_idle);
$to_myhdl(s_axis_cmd_ready, s_axis_data_tready, m_axis_data_tdata, m_axis_data_tvalid,
m_axis_data_tlast, scl_o, scl_t, sda_o, sda_t, busy, bus_control, bus_active,
missed_ack);
// dump file
$dumpfile("test_i2c_master.lxt");
$dumpvars(0, test_i2c_master);
end
i2c_master UUT (
.clk(clk),
.rst(rst),
.s_axis_cmd_address(s_axis_cmd_address),
.s_axis_cmd_start(s_axis_cmd_start),
.s_axis_cmd_read(s_axis_cmd_read),
.s_axis_cmd_write(s_axis_cmd_write),
.s_axis_cmd_write_multiple(s_axis_cmd_write_multiple),
.s_axis_cmd_stop(s_axis_cmd_stop),
.s_axis_cmd_valid(s_axis_cmd_valid),
.s_axis_cmd_ready(s_axis_cmd_ready),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tvalid(s_axis_data_tvalid),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tlast(s_axis_data_tlast),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tlast(m_axis_data_tlast),
.scl_i(scl_i),
.scl_o(scl_o),
.scl_t(scl_t),
.sda_i(sda_i),
.sda_o(sda_o),
.sda_t(sda_t),
.busy(busy),
.bus_control(bus_control),
.bus_active(bus_active),
.missed_ack(missed_ack),
.prescale(prescale),
.stop_on_idle(stop_on_idle)
);
endmodule
| 7.991605 |
module test_i2c_master_axil;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [3:0] s_axil_awaddr = 0;
reg [2:0] s_axil_awprot = 0;
reg s_axil_awvalid = 0;
reg [31:0] s_axil_wdata = 0;
reg [3:0] s_axil_wstrb = 0;
reg s_axil_wvalid = 0;
reg s_axil_bready = 0;
reg [3:0] s_axil_araddr = 0;
reg [2:0] s_axil_arprot = 0;
reg s_axil_arvalid = 0;
reg s_axil_rready = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
// Outputs
wire s_axil_awready;
wire s_axil_wready;
wire [1:0] s_axil_bresp;
wire s_axil_bvalid;
wire s_axil_arready;
wire [31:0] s_axil_rdata;
wire [1:0] s_axil_rresp;
wire s_axil_rvalid;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axil_awaddr, s_axil_awprot, s_axil_awvalid, s_axil_wdata,
s_axil_wstrb, s_axil_wvalid, s_axil_bready, s_axil_araddr, s_axil_arprot,
s_axil_arvalid, s_axil_rready, i2c_scl_i, i2c_sda_i);
$to_myhdl(s_axil_awready, s_axil_wready, s_axil_bresp, s_axil_bvalid, s_axil_arready,
s_axil_rdata, s_axil_rresp, s_axil_rvalid, i2c_scl_o, i2c_scl_t, i2c_sda_o,
i2c_sda_t);
// dump file
$dumpfile("test_i2c_master_axil.lxt");
$dumpvars(0, test_i2c_master_axil);
end
i2c_master_axil #(
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
.FIXED_PRESCALE(FIXED_PRESCALE),
.CMD_FIFO(CMD_FIFO),
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
.WRITE_FIFO(WRITE_FIFO),
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
.READ_FIFO(READ_FIFO),
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axil_awaddr(s_axil_awaddr),
.s_axil_awprot(s_axil_awprot),
.s_axil_awvalid(s_axil_awvalid),
.s_axil_awready(s_axil_awready),
.s_axil_wdata(s_axil_wdata),
.s_axil_wstrb(s_axil_wstrb),
.s_axil_wvalid(s_axil_wvalid),
.s_axil_wready(s_axil_wready),
.s_axil_bresp(s_axil_bresp),
.s_axil_bvalid(s_axil_bvalid),
.s_axil_bready(s_axil_bready),
.s_axil_araddr(s_axil_araddr),
.s_axil_arprot(s_axil_arprot),
.s_axil_arvalid(s_axil_arvalid),
.s_axil_arready(s_axil_arready),
.s_axil_rdata(s_axil_rdata),
.s_axil_rresp(s_axil_rresp),
.s_axil_rvalid(s_axil_rvalid),
.s_axil_rready(s_axil_rready),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
| 7.991605 |
module test_i2c_master_wbs_16;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [2:0] wbs_adr_i = 0;
reg [15:0] wbs_dat_i = 0;
reg wbs_we_i = 0;
reg [1:0] wbs_sel_i = 0;
reg wbs_stb_i = 0;
reg wbs_cyc_i = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
// Outputs
wire [15:0] wbs_dat_o;
wire wbs_ack_o;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbs_adr_i, wbs_dat_i, wbs_we_i, wbs_sel_i, wbs_stb_i,
wbs_cyc_i, i2c_scl_i, i2c_sda_i);
$to_myhdl(wbs_dat_o, wbs_ack_o, i2c_scl_o, i2c_scl_t, i2c_sda_o, i2c_sda_t);
// dump file
$dumpfile("test_i2c_master_wbs_16.lxt");
$dumpvars(0, test_i2c_master_wbs_16);
end
i2c_master_wbs_16 #(
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
.FIXED_PRESCALE(FIXED_PRESCALE),
.CMD_FIFO(CMD_FIFO),
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
.WRITE_FIFO(WRITE_FIFO),
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
.READ_FIFO(READ_FIFO),
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_stb_i(wbs_stb_i),
.wbs_ack_o(wbs_ack_o),
.wbs_cyc_i(wbs_cyc_i),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
| 7.991605 |
module test_i2c_master_wbs_8;
// Parameters
parameter DEFAULT_PRESCALE = 1;
parameter FIXED_PRESCALE = 0;
parameter CMD_FIFO = 1;
parameter CMD_FIFO_ADDR_WIDTH = 5;
parameter WRITE_FIFO = 1;
parameter WRITE_FIFO_ADDR_WIDTH = 5;
parameter READ_FIFO = 1;
parameter READ_FIFO_ADDR_WIDTH = 5;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [2:0] wbs_adr_i = 0;
reg [7:0] wbs_dat_i = 0;
reg wbs_we_i = 0;
reg wbs_stb_i = 0;
reg wbs_cyc_i = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
// Outputs
wire [7:0] wbs_dat_o;
wire wbs_ack_o;
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, wbs_adr_i, wbs_dat_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
i2c_scl_i, i2c_sda_i);
$to_myhdl(wbs_dat_o, wbs_ack_o, i2c_scl_o, i2c_scl_t, i2c_sda_o, i2c_sda_t);
// dump file
$dumpfile("test_i2c_master_wbs_8.lxt");
$dumpvars(0, test_i2c_master_wbs_8);
end
i2c_master_wbs_8 #(
.DEFAULT_PRESCALE(DEFAULT_PRESCALE),
.FIXED_PRESCALE(FIXED_PRESCALE),
.CMD_FIFO(CMD_FIFO),
.CMD_FIFO_ADDR_WIDTH(CMD_FIFO_ADDR_WIDTH),
.WRITE_FIFO(WRITE_FIFO),
.WRITE_FIFO_ADDR_WIDTH(WRITE_FIFO_ADDR_WIDTH),
.READ_FIFO(READ_FIFO),
.READ_FIFO_ADDR_WIDTH(READ_FIFO_ADDR_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_dat_o(wbs_dat_o),
.wbs_we_i(wbs_we_i),
.wbs_stb_i(wbs_stb_i),
.wbs_ack_o(wbs_ack_o),
.wbs_cyc_i(wbs_cyc_i),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t)
);
endmodule
| 7.991605 |
module test_i2c_slave;
// Parameters
parameter FILTER_LEN = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg release_bus = 0;
reg [7:0] s_axis_data_tdata = 0;
reg s_axis_data_tvalid = 0;
reg s_axis_data_tlast = 0;
reg m_axis_data_tready = 0;
reg scl_i = 1;
reg sda_i = 1;
reg enable = 0;
reg [6:0] device_address = 0;
reg [6:0] device_address_mask = 0;
// Outputs
wire s_axis_data_tready;
wire [7:0] m_axis_data_tdata;
wire m_axis_data_tvalid;
wire m_axis_data_tlast;
wire scl_o;
wire scl_t;
wire sda_o;
wire sda_t;
wire busy;
wire [6:0] bus_address;
wire bus_addressed;
wire bus_active;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, release_bus, s_axis_data_tdata, s_axis_data_tvalid,
s_axis_data_tlast, m_axis_data_tready, scl_i, sda_i, enable, device_address,
device_address_mask);
$to_myhdl(s_axis_data_tready, m_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tlast, scl_o,
scl_t, sda_o, sda_t, busy, bus_address, bus_addressed, bus_active);
// dump file
$dumpfile("test_i2c_slave.lxt");
$dumpvars(0, test_i2c_slave);
end
i2c_slave #(
.FILTER_LEN(FILTER_LEN)
) UUT (
.clk(clk),
.rst(rst),
.release_bus(release_bus),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tvalid(s_axis_data_tvalid),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tlast(s_axis_data_tlast),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tlast(m_axis_data_tlast),
.scl_i(scl_i),
.scl_o(scl_o),
.scl_t(scl_t),
.sda_i(sda_i),
.sda_o(sda_o),
.sda_t(sda_t),
.busy(busy),
.bus_address(bus_address),
.bus_addressed(bus_addressed),
.bus_active(bus_active),
.enable(enable),
.device_address(device_address),
.device_address_mask(device_address_mask)
);
endmodule
| 7.851238 |
module test_i2c_slave_axil_master;
// Parameters
parameter FILTER_LEN = 4;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter STRB_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
reg m_axil_awready = 0;
reg m_axil_wready = 0;
reg [1:0] m_axil_bresp = 0;
reg m_axil_bvalid = 0;
reg m_axil_arready = 0;
reg [DATA_WIDTH-1:0] m_axil_rdata = 0;
reg [1:0] m_axil_rresp = 0;
reg m_axil_rvalid = 0;
reg enable = 0;
reg [6:0] device_address = 0;
// Outputs
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
wire [ADDR_WIDTH-1:0] m_axil_awaddr;
wire [2:0] m_axil_awprot;
wire m_axil_awvalid;
wire [DATA_WIDTH-1:0] m_axil_wdata;
wire [STRB_WIDTH-1:0] m_axil_wstrb;
wire m_axil_wvalid;
wire m_axil_bready;
wire [ADDR_WIDTH-1:0] m_axil_araddr;
wire [2:0] m_axil_arprot;
wire m_axil_arvalid;
wire m_axil_rready;
wire busy;
wire bus_addressed;
wire bus_active;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, i2c_scl_i, i2c_sda_i, m_axil_awready, m_axil_wready,
m_axil_bresp, m_axil_bvalid, m_axil_arready, m_axil_rdata, m_axil_rresp,
m_axil_rvalid, enable, device_address);
$to_myhdl(i2c_scl_o, i2c_scl_t, i2c_sda_o, i2c_sda_t, m_axil_awaddr, m_axil_awprot,
m_axil_awvalid, m_axil_wdata, m_axil_wstrb, m_axil_wvalid, m_axil_bready,
m_axil_araddr, m_axil_arprot, m_axil_arvalid, m_axil_rready, busy, bus_addressed,
bus_active);
// dump file
$dumpfile("test_i2c_slave_axil_master.lxt");
$dumpvars(0, test_i2c_slave_axil_master);
end
i2c_slave_axil_master #(
.FILTER_LEN(FILTER_LEN),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready),
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready),
.busy(busy),
.bus_addressed(bus_addressed),
.bus_active(bus_active),
.enable(enable),
.device_address(device_address)
);
endmodule
| 7.851238 |
module test_i2c_slave_wbm;
// Parameters
parameter FILTER_LEN = 4;
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 16;
parameter WB_SELECT_WIDTH = WB_DATA_WIDTH / 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg i2c_scl_i = 1;
reg i2c_sda_i = 1;
reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
reg enable = 0;
reg [6:0] device_address = 0;
// Outputs
wire i2c_scl_o;
wire i2c_scl_t;
wire i2c_sda_o;
wire i2c_sda_t;
wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
wire [WB_DATA_WIDTH-1:0] wb_dat_o;
wire wb_we_o;
wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
wire bus_addressed;
wire bus_active;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, i2c_scl_i, i2c_sda_i, wb_dat_i, wb_ack_i, wb_err_i, enable,
device_address);
$to_myhdl(i2c_scl_o, i2c_scl_t, i2c_sda_o, i2c_sda_t, wb_adr_o, wb_dat_o, wb_we_o, wb_sel_o,
wb_stb_o, wb_cyc_o, busy, bus_addressed, bus_active);
// dump file
$dumpfile("test_i2c_slave_wbm.lxt");
$dumpvars(0, test_i2c_slave_wbm);
end
i2c_slave_wbm #(
.FILTER_LEN(FILTER_LEN),
.WB_DATA_WIDTH(WB_DATA_WIDTH),
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.WB_SELECT_WIDTH(WB_SELECT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.i2c_scl_i(i2c_scl_i),
.i2c_scl_o(i2c_scl_o),
.i2c_scl_t(i2c_scl_t),
.i2c_sda_i(i2c_sda_i),
.i2c_sda_o(i2c_sda_o),
.i2c_sda_t(i2c_sda_t),
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
.busy(busy),
.bus_addressed(bus_addressed),
.bus_active(bus_active),
.enable(enable),
.device_address(device_address)
);
endmodule
| 7.851238 |
module test_i2s_top_rx;
localparam RST_DURATION = 50; //ns
localparam CLK_PERIOD = 20; //ns
localparam STIMULUS_DATA_COUNT = 10;
// Inputs
reg clk_i;
reg rst_i;
reg sdat_i;
// Outputs
wire [15:0] data_o;
wire lr_chnl_o;
wire write_o;
wire sclk_o;
wire wsel_o;
// Received data
reg [15:0] data_rx[0:1];
// Transmitted data
reg [15:0] data_tx[0:STIMULUS_DATA_COUNT-1];
integer indx_tx;
integer indx_bit_tx;
// Instantiate the Unit Under Test (UUT)
i2s_top_rx uut (
.clk_i(clk_i),
.rst_i(rst_i),
.data_o(data_o),
.lr_chnl_o(lr_chnl_o),
.write_o(write_o),
.sclk_o(sclk_o),
.wsel_o(wsel_o),
.sdat_i(sdat_i)
);
defparam uut.WORD_WIDTH = 16;
// Reset pulse generator
initial begin : reset_generator
rst_i = 1'b1;
#(RST_DURATION);
rst_i = 1'b0;
end
// Main oscillator
initial begin : clk_generator
clk_i = 1'b0;
#(RST_DURATION);
forever begin
clk_i = #(CLK_PERIOD / 2) ~clk_i;
end
end
// I2S transmitter
initial begin : transmitter
read_from_file;
indx_tx = 0;
indx_bit_tx = 15;
sdat_i = 1'b0;
#(RST_DURATION);
forever begin
@(negedge (clk_i)) begin
if (indx_tx < STIMULUS_DATA_COUNT) begin
sdat_i = data_tx[indx_tx][indx_bit_tx];
if (indx_bit_tx > 0) begin
indx_bit_tx = indx_bit_tx - 1;
end else begin
$display("tx: %h", data_tx[indx_tx]);
indx_tx = indx_tx + 1;
indx_bit_tx = 15;
end
end else begin
$stop;
end
end
end
end
// Parallel receiver
always @(negedge (clk_i) or posedge (rst_i)) begin : receiver
if (rst_i) begin
data_rx[0] = 16'h0000;
data_rx[1] = 16'h0000;
end else begin
if (write_o) begin
$display("rx: %h", data_o);
if (lr_chnl_o) begin
data_rx[1] = data_o;
end else begin
data_rx[0] = data_o;
end
end
end
end
task read_from_file;
integer stimulus_file;
begin
stimulus_file = $fopen("stimulus/stimulus.txt", "r");
if (stimulus_file == 0) $finish;
if ($fscanf(stimulus_file, "%b", data_tx) == 0) $finish;
end
endtask
;
endmodule
| 6.66221 |
module test_i2s_top_trx;
localparam RST_DURATION = 50; //ns
localparam CLKT_PERIOD = 10; //ns
localparam CLKR_PERIOD = 100; //ns
localparam STIMULUS_DATA_COUNT = 10;
// Inputs
reg clk_i_t;
reg clk_i_r;
reg rst_i;
reg [15:0] data_i_t;
// Inouts
wire sclk;
wire wsel;
wire sdat;
// Outputs
wire [15:0] data_o_r;
wire lr_chnl_o_t;
wire write_o_t;
wire lr_chnl_o_r;
wire write_o_r;
// Received data
reg [15:0] data_rx[0:1];
// Transmitted data
reg [15:0] data_tx[0:STIMULUS_DATA_COUNT-1];
integer indx_tx;
// Instantiate the Unit Under Test (UUT)
i2s_top_tx uut_t (
.clk_i(clk_i_t),
.rst_i(rst_i),
.data_i(data_i_t),
.lr_chnl_o(lr_chnl_o_t),
.write_o(write_o_t),
.sclk_i(sclk),
.wsel_i(wsel),
.sdat_o(sdat)
);
defparam uut_t.WORD_WIDTH = 16;
// Instantiate the Unit Under Test (UUT)
i2s_top_rx uut_r (
.clk_i(clk_i_r),
.rst_i(rst_i),
.data_o(data_o_r),
.lr_chnl_o(lr_chnl_o_r),
.write_o(write_o_r),
.sclk_o(sclk),
.wsel_o(wsel),
.sdat_i(sdat)
);
defparam uut_r.WORD_WIDTH = 16;
// Reset pulse generator
initial begin : reset_generator
rst_i = 1'b1;
#(RST_DURATION);
rst_i = 1'b0;
end
// Main oscillator TX
initial begin : clk_generator_tx
clk_i_t = 1'b0;
#(RST_DURATION);
forever begin
clk_i_t = #(CLKT_PERIOD / 2) ~clk_i_t;
end
end
// Main oscillator RX
initial begin : clk_generator_rx
clk_i_r = 1'b0;
#(RST_DURATION);
forever begin
clk_i_r = #(CLKR_PERIOD / 2) ~clk_i_r;
end
end
// Parallel transmitter
always @(posedge (clk_i_t) or posedge (rst_i)) begin : transmitter
if (rst_i) begin
data_i_t = 16'h0000;
indx_tx = 0;
read_from_file;
end else begin
if (write_o_t) begin
if (indx_tx < STIMULUS_DATA_COUNT) begin
$display("tx: %h", data_tx[indx_tx]);
data_i_t = data_tx[indx_tx];
indx_tx = indx_tx + 1;
end else begin
$stop;
end
end
end
end
// Parallel receiver
always @(negedge (clk_i_r) or posedge (rst_i)) begin : receiver
if (rst_i) begin
data_rx[0] = 16'h0000;
data_rx[1] = 16'h0000;
end else begin
if (write_o_r) begin
$display("rx: %h", data_o_r);
if (lr_chnl_o_r) begin
data_rx[1] = data_o_r;
end else begin
data_rx[0] = data_o_r;
end
end
end
end
task read_from_file;
integer stimulus_file;
begin
stimulus_file = $fopen("stimulus/stimulus.txt", "r");
if (stimulus_file == 0) $finish;
if ($fscanf(stimulus_file, "%b", data_tx) == 0) $finish;
end
endtask
;
endmodule
| 6.66221 |
module test_i2s_top_tx;
localparam RST_DURATION = 50; //ns
localparam CLK_PERIOD = 10; //ns
localparam SCLK_PERIOD = 100; //ns
localparam STIMULUS_DATA_COUNT = 10;
// Inputs
reg clk_i;
reg rst_i;
reg [15:0] data_i;
reg sclk_i;
reg wsel_i;
// Outputs
wire lr_chnl_o;
wire write_o;
wire sdat_o;
// Received data
reg [15:0] data_rx[0:1];
reg indx_rx;
integer indx_bit_rx;
// Transmitted data
reg [15:0] data_tx[0:STIMULUS_DATA_COUNT-1];
integer indx_tx;
integer indx_bit_tx;
// Instantiate the Unit Under Test (UUT)
i2s_top_tx uut (
.clk_i(clk_i),
.rst_i(rst_i),
.data_i(data_i),
.lr_chnl_o(lr_chnl_o),
.write_o(write_o),
.sclk_i(sclk_i),
.wsel_i(wsel_i),
.sdat_o(sdat_o)
);
defparam uut.WORD_WIDTH = 16;
// Reset pulse generator
initial begin : reset_generator
rst_i = 1'b1;
#(RST_DURATION);
rst_i = 1'b0;
end
// Main oscillator
initial begin : clk_generator
clk_i = 1'b0;
#(RST_DURATION);
forever begin
clk_i = #(CLK_PERIOD / 2) ~clk_i;
end
end
// SCLK oscillator
initial begin : sclk_generator
sclk_i = 1'b0;
#(RST_DURATION);
forever begin
sclk_i = #(SCLK_PERIOD / 2) ~sclk_i;
end
end
// WSEL generator
always @(negedge (sclk_i) or posedge (rst_i)) begin : wsel_generator
if (rst_i) begin
wsel_i = 0;
indx_bit_tx = 15;
end else begin
if (indx_bit_tx == 1) begin
wsel_i = ~wsel_i;
end
if (indx_bit_tx == 0) begin
indx_bit_tx = 15;
end else begin
indx_bit_tx = indx_bit_tx - 1;
end
end
end
// I2S receiver
always @(posedge (sclk_i) or posedge (rst_i)) begin : receiver
if (rst_i) begin
indx_rx = 1'b1;
indx_bit_rx = 0;
data_rx[0] = 0;
data_rx[1] = 0;
end else begin
if (indx_bit_rx == 0) begin
$display("rx: %h", data_rx[indx_rx]);
indx_bit_rx = 15;
indx_rx = ~indx_rx;
end else begin
indx_bit_rx = indx_bit_rx - 1;
end
data_rx[indx_rx][indx_bit_rx] = sdat_o;
end
end
// Parallel transmitter
always @(posedge (clk_i) or posedge (rst_i)) begin : transmitter
if (rst_i) begin
data_i = 16'h0000;
indx_tx = 0;
read_from_file;
end else begin
if (write_o) begin
if (indx_tx < STIMULUS_DATA_COUNT) begin
$display("tx: %h", data_i);
data_i = data_tx[indx_tx];
//$display("tx: %h", data_i);
indx_tx = indx_tx + 1;
end else begin
$stop;
end
end
end
end
task read_from_file;
integer stimulus_file;
begin
stimulus_file = $fopen("stimulus/stimulus.txt", "r");
if (stimulus_file == 0) $finish;
if ($fscanf(stimulus_file, "%b", data_tx) == 0) $finish;
end
endtask
;
endmodule
| 6.66221 |
module test2;
reg [31:0] PC;
wire [31:0] inst;
IMEM dut (
.PC (PC),
.inst(inst)
);
initial begin
PC = 32'h000_0001_0;
$monitor("inst=%0h", inst);
#20;
PC = 32'h000_0002_0;
#50;
end
endmodule
| 6.545213 |
module test_img_control #(
parameter WIDTH = 640,
parameter HEIGHT = 480,
parameter PICWIDTH = 512,
parameter PICHEIGHT = 384
) (
input clk,
input [10:0] h_cnt,
input [9:0] v_cnt,
input vsync,
input inplace,
input display_ena,
input movement_ena,
output [3:0] r,
output [3:0] g,
output [3:0] b
);
wire signed [10:0] x_onpic;
wire signed [ 9:0] y_onpic;
wire [17:0] addr;
wire signed [10:0] x;
wire signed [ 9:0] y;
reg [10:0] offset_x = 0;
reg [ 9:0] offset_y = 0;
wire [31:0] calculate0;
wire [31:0] calculate1;
reg [31:0] k = 100; //k=100: original pic, k=0: zoomed pic
assign x = (h_cnt + offset_x) % WIDTH;
assign y = (v_cnt + offset_y) % HEIGHT;
assign calculate0 = (100 - k) * PICWIDTH / 200 + (k * PICWIDTH * x) / 100 / WIDTH;
assign calculate1 = (100 - k) * PICHEIGHT / 200 + (k * PICHEIGHT * y) / 100 / HEIGHT;
// assign calculate0 = (PICWIDTH * x) / WIDTH;
// assign calculate1 = (PICHEIGHT * y) / HEIGHT;
assign x_onpic = calculate0[10:0];
assign y_onpic = calculate1[9:0];
assign addr = (y_onpic * PICWIDTH + x_onpic - 1);
wire [23:0] pixel_rgb;
wire clk_delayed_5, clk_delayed_10;
shift_clockdelay #(5) clkdelay5 (
clk,
clk_delayed_5
);
shift_clockdelay #(10) clkdelay10 (
clk,
clk_delayed_10
);
pic_blk_mem_testcard picrom (
.clka(clk_delayed_5), // input wire clka
.addra(addr), // input wire [17 : 0] addra
.douta(pixel_rgb) // output wire [15 : 0] douta
);
reg [3:0] r_r;
reg [3:0] g_r;
reg [3:0] b_r;
always @(posedge clk) begin
if (inplace)
if (display_ena) begin
r_r <= pixel_rgb[23:20];
g_r <= pixel_rgb[15:12];
b_r <= pixel_rgb[7:4];
end else begin
r_r <= 4'h0;
g_r <= 4'hf;
b_r <= 4'h0;
end
else begin
r_r <= 4'hZ;
g_r <= 4'hZ;
b_r <= 4'hZ;
end
end
reg [1:0] state = 0;
always @(negedge vsync) begin
if (movement_ena)
if (state == 0) begin
//X-OFFSET
if (offset_x >= 0 && offset_x < WIDTH) begin
offset_x <= offset_x + 1;
end else offset_x <= 0;
if (offset_x == WIDTH) begin
state <= 1;
offset_x <= 0;
end
end else if (state == 1) begin
//Y-OFFSET
if (offset_y >= 0 && offset_y < HEIGHT) begin
offset_y <= offset_y + 1;
end else offset_y <= 0;
if (offset_y == HEIGHT) begin
state <= 2;
offset_y <= 0;
end
end else if (state == 2) begin
//ZOOM-IN
if (k <= 100 && k > 50) begin
k <= k - 1;
end else begin
k <= 50;
state <= 3;
end
end else if (state == 3) begin
//ZOOM-OUT
if (k < 100 && k >= 50) begin
k <= k + 1;
end else begin
k <= 100;
state <= 0;
end
end
end
assign r = r_r;
assign g = g_r;
assign b = b_r;
endmodule
| 7.079247 |
module test_img_feeder (
input wire rst,
input wire clk,
input wire clk_feeder,
output wire [31:0] fifoData_out,
input wire fifoRdclk,
input wire fifoRdreq,
output wire fifoRdempty,
input wire pause
);
reg [11:0] hcnt, vcnt;
wire [31:0] pixel_data;
wire sync_pixel_h;
wire sync_pixel_v;
wire wrreq;
wire wrfull;
fifo_32to32 fifo (
.data({pixel_data[31:2], sync_pixel_v ? 2'b10 : (sync_pixel_h ? 2'b01 : 2'b0)}),
.rdclk(fifoRdclk),
.rdreq(fifoRdreq),
.wrclk(clk_feeder),
.wrreq(wrreq),
.q(fifoData_out),
.rdempty(fifoRdempty),
.wrfull(wrfull)
);
simple img1 (
clk_feeder,
rst,
hcnt,
vcnt,
'd800,
'd600,
pixel_data[31:24],
pixel_data[23:16],
pixel_data[15:8],
pixel_data[7:0],
pause
);
//assign pixel_data = {4'd0, hcnt, 16'd0};
assign sync_pixel_h = (hcnt == 0);
assign sync_pixel_v = (hcnt == 0 && vcnt == 0);
assign wrreq = ~wrfull;
reg [1:0] stopped;
always @(posedge clk_feeder or negedge rst) begin
if (!rst) begin
hcnt <= 0;
vcnt <= 0;
stopped <= 0;
end else if (!wrfull) begin
if (hcnt != 0 | stopped == 2'd1) begin
if (hcnt == 800 - 1) begin
hcnt <= 0;
vcnt <= (vcnt == 600 - 1) ? 0 : vcnt + 1;
end else begin
hcnt <= hcnt + 1;
end
stopped <= 0;
end else begin
stopped <= stopped + 1;
end
end
end
endmodule
| 6.700963 |
module test_immediate_sign_ext;
reg [31:0] Instruction; //Las entradas del módulo deben ser tipo reg
wire [31:0] DataOut;
reg Enable;
reg [1:0] Select;
reg [2:0] counter;
parameter sim_time = 15;
immediate_sign_extension ext (
DataOut,
Instruction,
Enable,
Select
);
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
counter = 0;
Instruction = 32'b00000000000000000000111110001111;
Enable = 0;
repeat (8) #2 counter = counter + 1;
end
always @(counter) begin
case (counter)
3'd0: begin
Select = 0;
end
3'd1: begin
Select = 2'd1;
end
3'd2: begin
Select = 2'd2;
end
3'd3: begin
Select = 2'd3;
end
3'd4: begin
Enable = 1;
Select = 0;
end
3'd5: begin
Select = 2'd1;
end
3'd6: begin
Select = 2'd2;
end
3'd7: begin
Select = 2'd3;
end
endcase
end
initial begin
$display("Instruction, DataOut, Enable, Select"); //imprime header
$monitor("%h\t%h\t%h\t%h", Instruction, DataOut, Enable, Select); //imprime las señales
end
endmodule
| 7.932534 |
module test_in (
input clk,
input rst,
input enable,
output reg finished,
input [23:0] write_count,
input [ 1:0] ready,
output reg [ 1:0] activate,
output reg [31:0] fifo_data,
input [23:0] fifo_size,
output reg strobe
);
//Parameters
//Registers/Wires
reg [23:0] count;
reg [23:0] total_count;
//Sub modules
//Asynchronous Logic
//Synchronous Logic
always @(posedge clk or posedge rst) begin
if (rst) begin
activate <= 0;
fifo_data <= 0;
strobe <= 0;
count <= 0;
total_count <= 0;
finished <= 0;
end else begin
strobe <= 0;
if (!enable) begin
total_count <= 0;
activate <= 0;
finished <= 0;
end else if (total_count < write_count) begin
if ((ready > 0) && (activate == 0)) begin
//A FIFO is available
count <= 0;
if (ready[0]) begin
activate[0] <= 1;
end else begin
activate[1] <= 1;
end
end else if ((activate > 0) && (count < fifo_size)) begin
fifo_data <= total_count;
total_count <= total_count + 1;
count <= count + 1;
strobe <= 1;
end else begin
activate <= 0;
end
end else begin
finished <= 1;
activate <= 0;
end
end
end
endmodule
| 7.063097 |
module test_part_select_inst_0 (
G1,
G2
);
input [3:0] G1;
output G2;
and AND2 (G2, G1[1:0], G1);
endmodule
| 7.104898 |
module test_part_select_inst_1 (
G1,
G2
);
input G1;
output [3:0] G2;
and AND2 (G2[1:0], G1, G1);
endmodule
| 7.104898 |
module test_part_select_assign_0 (
G1,
G2
);
input [3:0] G1;
output G2;
assign G2 = G1[1:0] & G1;
endmodule
| 7.104898 |
module test_part_select_assign_1 (
G1,
G2
);
input G1;
output [3:0] G2;
assign G2[1:0] = G1 & G1;
endmodule
| 7.104898 |
module test_concat_0 (
G1,
G2
);
input G1;
output [1:0] G2;
assign G2 = {G1, G1};
endmodule
| 6.571725 |
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