code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_card_simple #(
H_RES = 640
) (
input wire signed [15:0] i_x,
output wire [7:0] o_red,
output wire [7:0] o_green,
output wire [7:0] o_blue
);
localparam HW = H_RES >> 3; // horizontal colour width = H_RES / 8
// Bands
wire b0 = (i_x >= 0) & (i_x < HW);
wire b1 = (i_x >= HW) & (i_x < HW * 2);
wire b2 = (i_x >= HW * 2) & (i_x < HW * 3);
wire b3 = (i_x >= HW * 3) & (i_x < HW * 4);
wire b4 = (i_x >= HW * 4) & (i_x < HW * 5);
wire b5 = (i_x >= HW * 5) & (i_x < HW * 6);
wire b6 = (i_x >= HW * 6) & (i_x < HW * 7);
wire b7 = (i_x >= HW * 7) & (i_x < HW * 8);
// Colour Output
assign o_red = {8{b0 | b1 | b5}} + {2'b0, {6{b6}}} + {b7, 7'b0};
assign o_green = {8{b1 | b2 | b3}} + {2'b0, {6{b6}}} + {b7, 7'b0};
assign o_blue = {8{b3 | b4 | b5}} + {2'b0, {6{b6}}} + {b7, 7'b0};
endmodule
| 8.417137 |
module test_card_squares #(
H_RES = 640,
V_RES = 480
) (
input wire signed [15:0] i_x,
input wire signed [15:0] i_y,
output wire [7:0] o_red,
output wire [7:0] o_green,
output wire [7:0] o_blue
);
localparam HR = H_RES; // horizontal resolution (pixels)
localparam VR = V_RES; // vertical resolution (lines)
localparam BW = 16; // border width
localparam SQ = VR >> 4; // square unit
localparam SX = (HR >> 1) - 5 * SQ; // square start horizontal
localparam SY = (VR >> 1) - 5 * SQ; // square start vertical
localparam LS = 2; // line spacing
// Borders
wire top = (i_x >= 0) & (i_y >= 0) & (i_x < HR) & (i_y < BW);
wire btm = (i_x >= 0) & (i_y >= VR - BW) & (i_x < HR) & (i_y < VR);
wire lft = (i_x >= 0) & (i_y >= 0) & (i_x < BW) & (i_y < VR);
wire rgt = (i_x >= HR - BW) & (i_y >= 0) & (i_x < HR) & (i_y < VR);
// Squares
wire sq_a = (i_x >= SX) & (i_y >= SY) & (i_x < SX + 4 * SQ) & (i_y < SY + 4 * SQ);
wire sq_b = (i_x >= SX + 2*SQ) & (i_y >= SY + 2*SQ) & (i_x < SX + 6*SQ) & (i_y < SY + 6*SQ);
wire sq_c = (i_x >= SX + 4*SQ) & (i_y >= SY + 4*SQ) & (i_x < SX + 8*SQ) & (i_y < SY + 8*SQ);
wire sq_d = (i_x >= SX + 6*SQ) & (i_y >= SY + 6*SQ) & (i_x < SX + 10*SQ) & (i_y < SY + 10*SQ);
wire sq_e = (i_x >= SX) & (i_y >= SY + 8 * SQ) & (i_x < SX + 2 * SQ) & (i_y < SY + 10 * SQ);
// Lines
wire lns_1 = (i_x >= SX + 8*SQ) & (i_x <= SX + 10*SQ) & ((i_y == SY + 0*LS ) | (i_y == SY + 2*SQ - 0*LS));
wire lns_2 = (i_x >= SX + 8*SQ) & (i_x <= SX + 10*SQ) & ((i_y == SY + 1*LS ) | (i_y == SY + 2*SQ - 1*LS));
wire lns_3 = (i_x >= SX + 8*SQ) & (i_x <= SX + 10*SQ) & ((i_y == SY + 2*LS ) | (i_y == SY + 2*SQ - 2*LS));
wire lns_4 = (i_x >= SX + 8*SQ) & (i_x <= SX + 10*SQ) & ((i_y == SY + 3*LS ) | (i_y == SY + 2*SQ - 3*LS));
wire lns_5 = (i_y >= SY) & (i_y <= SY + 2*SQ) & ((i_x == SX + 8*SQ + 0*LS) | (i_x == SX + 10*SQ - 0*LS));
wire lns_6 = (i_y >= SY) & (i_y <= SY + 2*SQ) & ((i_x == SX + 8*SQ + 1*LS) | (i_x == SX + 10*SQ - 1*LS));
wire lns_7 = (i_y >= SY) & (i_y <= SY + 2*SQ) & ((i_x == SX + 8*SQ + 2*LS) | (i_x == SX + 10*SQ - 2*LS));
wire lns_8 = (i_y >= SY) & (i_y <= SY + 2*SQ) & ((i_x == SX + 8*SQ + 3*LS) | (i_x == SX + 10*SQ - 3*LS));
// Colour Output
assign o_red = {8{lft | top | lns_1 | lns_4 | lns_5 | lns_8 | sq_b | sq_e}};
assign o_green = {8{btm | top | lns_2 | lns_4 | lns_6 | lns_8 | sq_a | sq_d | sq_e}};
assign o_blue = {8{rgt | top | lns_3 | lns_4 | lns_7 | lns_8 | sq_c | sq_e}};
endmodule
| 7.855842 |
module test_case ( /*AUTOARG*/);
/*
`define TB testbench_axi_master_bfm
`define MASTER `TB.master
`define SLAVE `TB.slave
`define MEMORY `SLAVE.memory
*/
`define TB testbench_my_slave
`define MASTER `TB.master
`define SLAVE `TB.slave
`define MEMORY `SLAVE.my_full_ip_v1_0_S00_AXI_inst.mem_data_out
initial begin
`ifdef NCVERILOG
$shm_open("basic.shm");
$shm_probe(`TB, "MAC");
`else
$dumpfile("basic.vcd");
$dumpvars(0, `TB);
`endif
end
integer i;
reg [31:0] read_data;
initial begin
repeat (2000) @(posedge `TB.aclk);
$display("BASIC: Timeout Failure! @ %d", $time);
$finish;
end
initial begin
$display("AXI Master BFM Test: Basic");
@(negedge `TB.aresetn);
@(posedge `TB.aresetn);
repeat (10) @(posedge `TB.aclk);
/*
`MASTER.write_single(32'h0000_0004, 32'hdead_beef, `AXI_BURST_SIZE_WORD, 4'hF);
`MASTER.write_single(32'h0000_0008, 32'h1234_5678, `AXI_BURST_SIZE_WORD, 4'hF);
`MASTER.write_single(32'h0000_000C, 32'hABCD_EF00, `AXI_BURST_SIZE_WORD, 4'hF);
`MASTER.write_single(32'h0000_0010, 32'hAA55_66BB, `AXI_BURST_SIZE_WORD, 4'hF);
*/
for (i = 0; i < 4; i = i + 1) begin
`MASTER.write_single(i * 4, 32'hffff_ffff - i, `AXI_BURST_SIZE_WORD, 4'hF);
end
repeat (10) @(posedge `TB.aclk);
/*
`MASTER.read_single_and_check(32'h0000_0004, 32'hdead_beef, `AXI_BURST_SIZE_WORD, 4'hF);
`MASTER.read_single_and_check(32'h0000_0008, 32'h1234_5678, `AXI_BURST_SIZE_WORD, 4'hF);
`MASTER.read_single_and_check(32'h0000_000C, 32'hABCD_EF00, `AXI_BURST_SIZE_WORD, 4'hF);
`MASTER.read_single_and_check(32'h0000_0010, 32'hAA55_66BB, `AXI_BURST_SIZE_WORD, 4'hF);
*/
for (i = 0; i < 4; i = i + 1) begin
`MASTER.read_single_and_check(i * 4, 32'hffff_ffff - i, `AXI_BURST_SIZE_WORD, 4'hF);
end
for (i = 0; i < 32; i = i + 1) begin
$display("MEMORY[%d] = 0x%04x", i, `MEMORY[i]);
end
`TB.test_passed <= 1;
end
endmodule
| 6.939549 |
module test_case_alu (
output reg clock,
output reg enable,
output reg [ 2:0] funct3,
output reg [ 6:0] funct7,
output reg [31:0] register_data_1,
output reg [31:0] register_data_2,
input [31:0] register_data_out
);
parameter CLOCK_PERIOD = 1;
always begin
#CLOCK_PERIOD clock = !clock;
end
initial begin
clock = 0;
enable = 1;
register_data_1 = 1;
register_data_2 = 2;
// set ALU to sum
funct3 = 0;
// select alu_base
funct7 = 0;
$dumpfile("test_case_alu.vcd");
$dumpvars();
#20
// now select alu_extra SUB
funct3 = 0;
funct7 = 32;
#100 $finish;
end
initial begin
#7
// display all registers in the rs1 output one by one
forever
@(negedge clock) begin
if (register_data_2 < 10) register_data_2 += 1;
else register_data_2 -= 1;
end
end
initial begin
forever
@(posedge clock) begin
$display("%0t", $time);
$display(
"clock = %b, funct7 = %h, funct3 = %h, register_data_1 = %h, register_data_2 = %h, register_data_out = %h",
clock, funct7, funct3, register_data_1, register_data_2, register_data_out);
end
end
endmodule
| 7.296998 |
module test_alu_base (
output reg clock,
output reg enable,
output reg [ 2:0] funct3,
output reg [31:0] register_data_1,
output reg [31:0] register_data_2,
input [31:0] register_data_out
);
parameter CLOCK_PERIOD = 1;
always begin
#CLOCK_PERIOD clock = !clock;
end
initial begin
$dumpfile("test_case_alu_base.vcd");
$dumpvars();
// initialize registers
clock = 0;
enable = 0;
// set ALU to SUM
funct3 = 0;
// set SUM inputs 0, 0 result=> 0
register_data_1 = 0;
register_data_2 = 0;
#5 enable = 1;
// change SUM inputs result=> 3
register_data_1 = 1;
register_data_2 = 2;
#100 $finish;
end
initial begin
#7
// display all registers in the rs1 output one by one
forever
@(negedge clock) begin
if (register_data_2 < 10) register_data_2 += 1;
else register_data_2 = 0;
end
end
initial begin
forever
@(posedge clock) begin
$display("%0t", $time);
$display(
"clock = %b, funct3 = %h, register_data_1 = %h, register_data_2 = %h, register_data_out = %h",
clock, funct3, register_data_1, register_data_2, register_data_out);
end
end
endmodule
| 7.310016 |
module test_case_memory (
output reg clock,
output reg read_enable,
output reg [31:0] read_address,
input [31:0] read_value,
output reg write_enable,
output reg [31:0] write_address,
output reg [31:0] write_value
);
reg clock2;
initial begin
clock = 0;
clock2 = 0;
read_enable = 1;
read_address = 0;
write_enable = 0;
write_address = 0;
read_address = 0;
forever
@(negedge clock2) begin
read_address += 1;
end
end
initial begin
$dumpfile("test_case_memory.vcd");
$dumpvars();
#`FINISH_MEMORY_TIME $finish;
end
always begin
#`CLOCK_HALF_PERIOD clock = !clock;
end
always @(posedge clock) begin
clock2 = !clock2;
end
initial begin
forever
@(posedge clock) begin
$display("read_enable=%x, read_address=%x, read_value= %x", read_enable, read_address,
read_value);
$display("write_enable=%x, write_address=%x, write_value=%x", write_enable, write_address,
write_value);
end
end
endmodule
| 6.789641 |
module test_register_file (
output reg clock,
output reg reset,
output reg write_enable,
output reg [4:0] rs1,
output reg [4:0] rs2,
output reg [4:0] register_write_select,
output reg [31:0] register_data_write,
input [31:0] register_data_1,
input [31:0] register_data_2
);
parameter CLOCK_PERIOD = 1;
always begin
#CLOCK_PERIOD clock = !clock;
end
initial begin
$dumpfile("test_case_register_file.vcd");
$dumpvars(clock);
//initialize registers
clock = 0;
reset = 0;
// write values to all registers
write_enable = 1;
rs1 = 0;
rs2 = 0;
register_write_select = 0;
register_data_write = 0;
// time to read register values
#66;
write_enable = 0;
#100 $finish;
end
initial begin
// write to registers values from 0 to 31
forever
@(negedge clock) begin
register_write_select += 1;
register_data_write += 1;
end
end
initial begin
// display all registers in the rs1 output one by one
forever
@(negedge clock) begin
rs1 += 1;
end
end
initial begin
forever
@(posedge clock) begin
$display("clock = %b, reset = %b, write_enable = %b", clock, reset, write_enable);
$display("rs1 = 0x%x, rs2 = 0x%x, register_write_select = 0x%x", rs1, rs2,
register_write_select);
$display("register_data_write = 0x%x, register_data_1 = 0x%x, register_data_2 = 0x%x",
register_data_write, register_data_1, register_data_2);
end
end
endmodule
| 7.267008 |
module test_case_rv32 (
output reg clock,
output reg enable
);
parameter CLOCK_HALF_PERIOD = 1;
parameter CLOCK_PERIOD = 2;
reg [31:0] cycle_counter;
initial begin
$dumpfile("test_case_rv32.vcd");
$dumpvars();
$monitorh(
"counter=%04d,pc=%08x,instruction=%08x,r0=%08x,r1=%08x,r2=%08x,r3=%08x,r4=%08x,r5=%08x,r6=%08x,r7=%08x,r8=%08x,r9=%08x,r10=%08x,r11=%08x,r12=%08x,r13=%08x,r14=%08x,r15=%08x,r16=%08x,r17=%08x,r18=%08x,r19=%08x,r20=%08x,r21=%08x,r22=%08x,r23=%08x,r24=%08x,r25=%08x,r26=%08x,r27=%08x,r28=%08x,r29=%08x,r30=%08x,r31=%08x",
cycle_counter, test_bench_rv32.pc, test_bench_rv32.instruction,
test_bench_rv32.register_file_0.registers[0], test_bench_rv32.register_file_0.registers[1],
test_bench_rv32.register_file_0.registers[2], test_bench_rv32.register_file_0.registers[3],
test_bench_rv32.register_file_0.registers[4], test_bench_rv32.register_file_0.registers[5],
test_bench_rv32.register_file_0.registers[6], test_bench_rv32.register_file_0.registers[7],
test_bench_rv32.register_file_0.registers[8], test_bench_rv32.register_file_0.registers[9],
test_bench_rv32.register_file_0.registers[10],
test_bench_rv32.register_file_0.registers[11],
test_bench_rv32.register_file_0.registers[12],
test_bench_rv32.register_file_0.registers[13],
test_bench_rv32.register_file_0.registers[14],
test_bench_rv32.register_file_0.registers[15],
test_bench_rv32.register_file_0.registers[16],
test_bench_rv32.register_file_0.registers[17],
test_bench_rv32.register_file_0.registers[18],
test_bench_rv32.register_file_0.registers[19],
test_bench_rv32.register_file_0.registers[20],
test_bench_rv32.register_file_0.registers[21],
test_bench_rv32.register_file_0.registers[22],
test_bench_rv32.register_file_0.registers[23],
test_bench_rv32.register_file_0.registers[24],
test_bench_rv32.register_file_0.registers[25],
test_bench_rv32.register_file_0.registers[26],
test_bench_rv32.register_file_0.registers[27],
test_bench_rv32.register_file_0.registers[28],
test_bench_rv32.register_file_0.registers[29],
test_bench_rv32.register_file_0.registers[30],
test_bench_rv32.register_file_0.registers[31]);
/*
$monitor("clock=%h, pc=%h, instruction=%h, rs1=%h, rs2=%h, rd=%h, rs1_value=%h, rs2_value=%h, rd_value=%h, alu_register_register=%b, opcode=%h, funct7=%h, funct3=%h \n",
clock,
test_bench_rv32.pc,
test_bench_rv32.instruction,
test_bench_rv32.register_file_0.rs1,
test_bench_rv32.register_file_0.rs2,
//test_bench_rv32.execute_0.register_file_0.register_data_write,
test_bench_rv32.register_file_0.rd,
//test_bench_rv32.execute_0.register_file_0.rs1,
test_bench_rv32.execute_0.alu_rv_0.alu_register_register_0.alu_extra_0.rs1_value,
test_bench_rv32.execute_0.alu_rv_0.alu_register_register_0.alu_extra_0.rs2_value,
//test_bench_rv32.execute_0.register_file_0.rs2,
test_bench_rv32.execute_0.alu_rv_0.alu_register_register_0.alu_extra_0.rd_value,
test_bench_rv32.decode_0.alu_register_register_enable,
test_bench_rv32.decode_0.opcode,
test_bench_rv32.execute_0.alu_rv_0.funct7,
test_bench_rv32.execute_0.alu_rv_0.funct3
);
*/
#100 $finish;
end
initial begin
cycle_counter = 0;
forever begin
#CLOCK_PERIOD cycle_counter += 1;
end
end
initial begin
clock = 0;
enable = 1;
test_bench_rv32.program_counter_0.pc = 0;
forever begin
#CLOCK_HALF_PERIOD clock = ~clock;
end
end
initial begin
$readmemh("bin/default_register_init.hex", test_bench_rv32.register_file_0.registers);
end
initial begin
$readmemh("bin/code.hex", test_bench_rv32.memory_0.random_access_memory);
end
endmodule
| 6.531752 |
module: pet2001cass232
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cass232;
// Inputs
reg rx232;
reg cass_motor_n;
reg cass_write;
reg clk;
reg reset;
// Outputs
wire tx232;
wire cass_read;
wire cts232n;
// Instantiate the Unit Under Test (UUT)
pet2001cass232 uut (
.tx232(tx232),
.rx232(rx232),
.cts232n(cts232n),
.cass_motor_n(cass_motor_n),
.cass_write(cass_write),
.cass_read(cass_read),
.clk(clk),
.reset(reset)
);
parameter RS232_BIT_TIME = 26042.0; // 8680=115,200 baud, 26042=38,400
task write_char(input [7:0] c);
begin
while (cts232n)
@(posedge clk);
rx232 <= 1'b0; // start bit
repeat (8) begin
#RS232_BIT_TIME rx232 <= c[0];
c = {1'bx, c[7:1]};
end
#RS232_BIT_TIME rx232 <= 1'b1; // stop
#RS232_BIT_TIME ;
end
endtask // write_char
// Read all characters.
always @(negedge tx232) begin:foo2
reg [7:0] c;
#(RS232_BIT_TIME / 2.0); // move to halfway into bit time for sampling
repeat (8) begin
#(RS232_BIT_TIME) c = { tx232, c[7:1] };
end
#(RS232_BIT_TIME) ; // stop bit
$display("%t: received '%h'", $time, c);
end
initial begin
// Initialize Inputs
rx232 = 1;
cass_motor_n = 1;
cass_write = 0;
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
repeat (20) @(posedge clk);
reset <= 0;
#1000000.0 cass_motor_n <= 0; // 1ms, turn on
#100000.0;
repeat (20) begin
write_char(8'h07);
write_char(8'hff);
write_char(8'he0);
write_char(8'h00);
end
#1000000.0;
#3000000.0 cass_motor_n <= 1; // 3ms, turn off
#1000000.0 ;
cass_motor_n <= 0;
forever begin
@(negedge tx232);
rx232 <= 1'b0;
@(posedge tx232);
rx232 <= 1'b1;
end
end
always @(posedge cts232n) begin
$display("[%t] cts232n=1", $time);
@(negedge cts232n);
$display("[%t] cts232n=0", $time);
end
always #5.0 clk = ~clk;
always #400000.0 cass_write = ~cass_write;
endmodule
| 6.529996 |
module test_cbc_dec;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
CBC_dec e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("cbc_enc.txt", msg);
//$display("f=%b",msg[1]);
f = $fopen("cbc_dec.txt", "w");
#10
for (i = 1; i <= 131072; i = i + 1) begin
#1 message = msg[i];
//$display("%b",msg[i]);
key = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
//$monitor("%d",i);
//$display("%b",ciphertext);
//$fwrite(f,"%d",i);
if (i == 1) iv = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
else iv = msg[i-1];
$fwrite(f, "%b\n", ciphertext);
end
#10 $fclose(f);
end
endmodule
| 7.350289 |
module test_cbc_enc;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
CBC_enc e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("binary.txt", msg);
//$display("f=%b",msg[1]);
f = $fopen("cbc_enc.txt", "w");
#10
for (i = 1; i <= 131072; i = i + 1) begin
#1 message = msg[i];
//$display("%b",msg[i]);
key = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
//$monitor("%d",i);
//$display("%b",ciphertext);
//$fwrite(f,"%d",i);
if (i == 1) iv = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
else iv = ciphertext;
$fwrite(f, "%b\n", ciphertext);
end
#10 $fclose(f);
end
endmodule
| 7.771286 |
module test_pa2_fsm;
// DUT I/O
logic clock;
logic reset;
logic valid;
logic [3:0] num;
logic [3:0] seq;
logic hit;
logic [3:0] cnt, n_cnt;
STATE state, n_state;
// Testbench variables
logic [3:0] int_cnt; // Keeps track of # hits on input
logic [3:0] hit_cnt; // Used to monitor hit output signal
logic [3:0] seq_len;
pa2_fsm dut (
.clock,
.reset,
.valid,
.num,
.seq,
.state,
.n_state,
.cnt,
.n_cnt,
.hit
);
always #5 clock = ~clock;
initial begin
// setup monitor and reset signals
$monitor(
"time: %3.0d vld: %b num: %2.0d seq: %2.0d cnt: %2.0d n_cnt: %2.0d state: %b n_state: %b hit: %b",
$time, valid, num, seq, cnt, n_cnt, state, n_state, hit);
clock = 1'b0;
reset = 1'b0;
valid = 1'b0;
num = 4'h5;
seq = 4'h0;
seq_len = 4'h0;
int_cnt = 4'h0;
hit_cnt = 4'h0;
// Apply reset to DUT
reset = 1'b1;
@(negedge clock);
reset = 1'b0;
// Apply sequence with zero matches
// then wait 11-15 cycles to start over (to allow for hit cycles)
apply_sequence(4'd10, NO_MATCH);
repeat (11) @(negedge clock);
// Apply sequence with all matches
apply_sequence(4'd10, MATCH);
repeat (11) @(negedge clock);
// Apply sequence with length 1 (no match)
apply_sequence(4'd1, NO_MATCH);
repeat (2) @(negedge clock);
// Apply sequence with length 1 (match)
apply_sequence(4'd1, MATCH);
repeat (3) @(negedge clock);
// Go through 5 rounds of random sequences
repeat (5) begin
seq_len = ($random % 4'd10) + 1; // num between 1-10
apply_sequence(seq_len, RAND);
repeat (11) @(negedge clock);
end
@(negedge clock);
$display(" FINISHED : SUCCESS ! \n ");
$finish;
end
// Block to monitor "hit" output
always @(negedge clock) begin
#1;
// Check to see if hit is asserted when it shouldn't be
if (hit && hit_cnt == 0) begin
$display("@@@ FAIL: Hit asserted erroneously!");
$finish;
// Check to see if hit not asserted when it should be
end else if (!hit && hit_cnt > 0) begin
$display("@@@ FAIL: Hit not asserted but should be!");
$finish;
// Decrement counter
end else if (hit && hit_cnt > 0) begin
hit_cnt = hit_cnt - 4'h1;
end
end
// Task to apply a sequence of numbers to the DUT
task apply_sequence;
input [3:0] length;
input OVERRIDE override; // RAND: use random inputs
// MATCH: force seq to match num
// NO_MATCH: force seq to not match num
begin
int_cnt = 4'h0;
valid = 1'b1;
repeat (length) begin
@(negedge clock);
case (override)
RAND: seq = ($random % 'd16); // num between 0-15
MATCH: seq = num;
NO_MATCH: seq = ~num;
endcase
if (seq == num) int_cnt = int_cnt + 4'h1;
end
valid = 1'b0;
// Initialize hit_cnt for hit output monitoring
#2;
hit_cnt = int_cnt;
end
endtask
endmodule
| 7.709212 |
module top;
wire [63:0] x = 64'hDEADBEEFBAADF00D;
wire [31:0] k = 64'h01234567;
wire [63:0] y;
fcell fc (
.IN (x),
.KEY(k),
.OUT(y)
);
initial begin
$display("x = %h", x);
$display("k = %h", k);
end
wire [63:0] x_dec;
ifcell ifc (
.IN (y),
.KEY(k),
.OUT(x_dec)
);
initial begin
#1 $display("y = %h", y);
$display("x' = %h", x_dec);
if (x == x_dec) $display("[PASSED]");
else $display("[FAILED]");
$finish;
end
endmodule
| 6.919222 |
module test_cfb_enc;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
CFB_enc e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("binary.txt", msg);
//$display("f=%b",msg[1]);
f = $fopen("cfb_enc.txt", "w");
#10
for (i = 1; i <= 131072; i = i + 1) begin
#1 message = msg[i];
//$display("%b",msg[i]);
key = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
//$monitor("%d",i);
//$display("%b",ciphertext);
//$fwrite(f,"%d",i);
if (i == 1) iv = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
else iv = ciphertext;
$fwrite(f, "%b\n", ciphertext);
end
#10 $fclose(f);
end
endmodule
| 7.437826 |
module test_cfb_dec;
// Outputs
//wire ;
reg [64:1] key;
integer i;
integer f;
reg [64:1] iv;
reg [64:1] msg[1:131072];
reg [64:1] message;
wire [64:1] ciphertext;
CFB_dec e (
ciphertext,
message,
key,
iv
);
initial begin
#10 $readmemb("cfb_enc.txt", msg);
//$display("f=%b",msg[1]);
f = $fopen("cfb_dec.txt", "w");
#10
for (i = 1; i <= 131072; i = i + 1) begin
#1 message = msg[i];
//$display("%b",msg[i]);
key = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
//$monitor("%d",i);
//$display("%b",ciphertext);
//$fwrite(f,"%d",i);
if (i == 1) iv = 64'b00010011_00110100_01010111_01111001_10011011_10111100_11011111_11110001;
else iv = msg[i-1];
$fwrite(f, "%b\n", ciphertext);
end
#10 $fclose(f);
end
endmodule
| 7.121331 |
module test_char_send (
input clk,
input rst_n,
input [23:0] send_str,
output RsTx
);
reg [30:0] time_cnt;
reg [ 7:0] tx_data_in;
reg tx_en;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) time_cnt <= 'b0;
else if (time_cnt == 50_000_000) //time is 3s
time_cnt <= 'b0;
else time_cnt <= time_cnt + 1'b1;
end
//wire [7:0] char2 = send_str[23:16]; //15-8
//wire [7:0] char1 = send_str[15:8]; //15-8
wire [7:0] char0 = send_str[7:0]; //7-0
// send_str = {x1_l,x1_r,x2_l,x2_r,y,x1,x2};
// send_str total is 16bit
// x1_l, 1bit,send_str[15]
// x1_r, 1bit,send_str[14]
// x2_l, 1bit,send_str[13]
// x2_r, 1bit,send_str[12]
// y, 4bit,send_str[11:8]
// x1, 4bit,send_str[7:4]
// x2 4bit,send_str[3:0]
always @(*) begin
if (time_cnt <= 10) begin
case (time_cnt)
0: tx_data_in = 8'h22;
1: tx_data_in = char0;
2: tx_data_in = 8'h22;
3: tx_data_in = 8'h55;
default: tx_data_in = 8'h55;
endcase
end else tx_data_in = 8'h00;
end
always @(*) begin
if (time_cnt <= 3) tx_en = 1'b1;
else tx_en = 1'b0;
end
UART_TOP UART_TOP_m0 (
.clk (clk),
.rst_n(rst_n),
.RsRx(), //Input from RS-232
.RsTx(RsTx), //Output to RS-232
.tx_data_in (tx_data_in),
.rx_data_out(),
.tx_en(tx_en),
.rx_en(),
.uart_irq() //Interrupt
);
endmodule
| 6.740264 |
module test_cla_8bits;
reg [7:0] m, n;
reg cin;
wire [7:0] sum;
wire cout;
cla_8bits tt (
m,
n,
cin,
cout,
sum
);
initial begin
#40 cin = 1;
m = 8'b10101100;
n = 8'b11010101;
#40 cin = 1;
m = 8'b10001111;
n = 8'b10001111;
#40 cin = 0;
m = 8'b01010101;
n = 8'b10101010;
end
always @(m or n or cin) begin
#20 $display("a=%b b=%b cin=%b cout=%b sum=%b", m, n, cin, cout, sum);
end
endmodule
| 7.384118 |
module: cla_adder_16bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cla_adder_16bit;
// Inputs
reg [15:0] A;
reg [15:0] B;
reg C0;
// Outputs
wire [15:0] S;
wire C16;
wire Pg;
wire Gg;
// Instantiate the Unit Under Test (UUT)
cla_adder_16bit uut (
.A(A),
.B(B),
.S(S),
.C0(C0),
.C16(C16),
.Pg(Pg),
.Gg(Gg)
);
integer error = 0;
initial begin
// Initialize Inputs
A = 0;
B = 0;
C0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
B = 16'd5; //basic low value adding
for (A = 16'd1; A!= 16'd15; A = A + 1 ) begin
#10;
$display("Add: %d + %d = ", A, B, S);
if((A + B + C0 !== S) && (C16 !== 1)) begin //adding errors
$display("ERROR addition error ABOVE");
error = error + 1;
end
if((A + B >= 65536) && (C16 !== 1)) begin //carry errors
$display("ERROR no carry ABOVE");
error = error + 1;
end
if(C16 == 1) begin
$display("WARNING carry");
end
end
B = 16'd84; //using multiple units
for (A = 16'd24; A!= 16'd58; A = A + 1 ) begin
#10;
$display("Add: %d + %d = ", A, B, S);
if((A + B + C0 !== S) && (C16 !== 1)) begin //adding errors
$display("ERROR addition error ABOVE");
error = error + 1;
end
if((A + B >= 65536) && (C16 !== 1)) begin //carry errors
$display("ERROR no carry ABOVE");
error = error + 1;
end
if(C16 == 1) begin
$display("WARNING carry");
end
end
B = 16'd65500; //large values and overflowing
for (A = 16'd24; A!= 16'd58; A = A + 1 ) begin
#10;
$display("Add: %d + %d = ", A, B, S);
if((A + B + C0 !== S) && (C16 !== 1)) begin //adding errors
$display("ERROR addition error ABOVE");
error = error + 1;
end
if((A + B >= 65536) && (C16 !== 1)) begin //carry errors
$display("ERROR no carry ABOVE");
error = error + 1;
end
if(C16 == 1) begin
$display("WARNING carry");
end
end
C0 = 1;
B = 16'd65500; //large values and overflowing
for (A = 16'd24; A!= 16'd58; A = A + 1 ) begin
#10;
$display("Add: %d + %d = ", A, B, S);
if((A + B + C0 !== S) && (C16 !== 1)) begin //adding errors
$display("ERROR addition error ABOVE");
error = error + 1;
end
if((A + B >= 65536) && (C16 !== 1)) begin //carry errors
$display("ERROR no carry ABOVE");
error = error + 1;
end
if(C16 == 1) begin
$display("WARNING carry");
end
end
end
endmodule
| 6.812775 |
module: cla_adder_4bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cla_adder_4bit;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg C0;
// Outputs
wire [3:0] S;
wire C4, Pg, Gg;
// Instantiate the Unit Under Test (UUT)
cla_adder_4bit uut (
.A(A),
.B(B),
.S(S),
.C0(C0),
.C4(C4),
.Pg(Pg),
.Gg(Gg)
);
integer error = 0;
initial begin
// Initialize Inputs
A = 0;
B = 0;
C0 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// for (B = 4'd1; B!=4'd15; B= B + 1) begin
B = 4'd5;
for (A = 4'd1; A!= 4'd15; A = A + 1 ) begin
#10;
$display("Add: %d + %d = ", A, B, S);
if((A + B + C0 !== S) && (C4 !== 1)) begin //adding errors
$display("ERROR addition error ABOVE");
error = error + 1;
end
if((A + B >= 16) && (C4 !== 1)) begin //carry errors
$display("ERROR no carry ABOVE");
error = error + 1;
end
if(C4 == 1) begin
$display("WARNING carry");
end
end
C0 = 1; //test with a carry now
for (A = 4'd1; A!= 4'd15; A = A + 1 ) begin
#10;
$display("Add: %d + %d = ", A, B, S);
if((A + B + C0 !== S) && (C4 !== 1)) begin //adding errors
$display("ERROR addition error ABOVE");
error = error + 1;
end
if((A + B >= 16) && (C4 !== 1)) begin //carry errors
$display("ERROR no carry ABOVE");
error = error + 1;
end
if(C4 == 1) begin
$display("WARNING carry");
end
end
end
endmodule
| 7.376897 |
module: normClkGenerator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ns
`default_nettype none
module test_clk;
// Inputs
reg clk_in;
reg reset_n;
// Outputs
wire clk_out;
// Instantiate the Unit Under Test (UUT)
normClkGenerator uut (
.clk_in(clk_in),
.reset_n(reset_n),
.clk_out(clk_out)
);
initial begin
// Initialize Inputs
clk_in <= 1'b0;
reset_n <= 1'bX;
// Wait 100 ns for global reset to finish
#100;
reset_n <= 1'b0;
#100
reset_n <= 1'b1;
// Add stimulus here
end
always #10 begin
clk_in <= ~clk_in;
end
endmodule
| 6.502821 |
module: clk_divider
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_clk_divider;
localparam T = 10;
// Inputs
reg clk_in;
reg rst;
// Outputs
wire clk_out;
// Instantiate the Unit Under Test (UUT)
clk_divider uut (
.clk_in(clk_in),
.rst(rst),
.clk_out(clk_out)
);
initial begin //intial reset
rst = 1'b1;
#(T/2-10);
rst = 1'b0;
end
always //constant clock running
begin
clk_in = 1'b1;
#(T/2);
clk_in = 1'b0;
#(T/2);
end
endmodule
| 6.64719 |
module test_clock_tb;
wire clk;
test_clock uut (clk);
initial begin
$dumpfile("test_clock_tb.vcd");
$dumpvars(0, test_clock_tb);
#10 $finish;
$display("Test Complete");
end
endmodule
| 7.479708 |
module test_cmera (
input wire CLK_IN, //ϵͳʱ
input wire RST_N, //λ,Ĭ
//camera
input wire CSI_PCLK, //CSIʱ
output wire CSI_XCLK, //CSIϵͳʱ
input wire CSI_HREF, //ͬ
input wire CSI_VSYNC, //֡ͬ
output wire CSI_PWDN, //ģʽ
output wire CSI_RST, //λ
output wire CSI_SOIC, //SCCB,ʱ
inout wire CSI_SOID, //SCCB,
input wire [7:0] CSI_D, //
//lcd
output wire [7:0] R,
output wire [7:0] G,
output wire [7:0] B,
output wire LCD_CLK,
output wire LCD_HSYNC,
output wire LCD_VSYNC,
output wire LCD_DEN,
output wire LCD_PWM, //backlight,set to high
//test
output wire TESTA,
output wire TESTB,
output wire TESTC,
output wire TESTD,
output wire TESTE,
output wire TESTF,
output wire [0:7] OD
);
wire clk_lcd;
wire clk_cam;
wire clk_sccb;
ip_pll pll (
.refclk (CLK_IN), //24M
.clk0_out(clk_lcd), //lcd clk
.clk1_out(clk_cam), //12m,for cam xclk
.clk2_out(clk_sccb) //4m,for sccb init
);
reg init_state;
wire init_ready;
wire sda_oe;
wire sda;
wire sda_in;
wire scl;
camera_init u_camera_init (
.clk(clk_sccb),
.reset_n(RST_N),
.ready(init_ready),
.sda_oe(sda_oe),
.sda(sda),
.sda_in(sda_in),
.scl(scl)
);
assign CSI_SOID = (sda_oe == 1'b1) ? sda : 1'bz;
assign sda_in = CSI_SOID;
assign CSI_SOIC = scl;
assign CSI_PWDN = 1'b0;
assign CSI_RST = 1'b1;
//test
// assign TESTE = (sda_oe == 1'b1) ? sda : 1'bz;
// assign TESTF = scl;
//lcd display
wire [10:0] hsync_cnt;
wire [10:0] vsync_cnt;
wire lcd_rden;
wire [15:0] lcd_rddat; //lcd read
wire [15:0] lcd_rdaddr;
lcd_sync #(
.IMG_W(200),
.IMG_H(164),
.IMG_X(50),
.IMG_Y(50)
) u_lcd_sync (
.clk(clk_lcd),
.rest_n(RST_N),
.lcd_clk(LCD_CLK),
.lcd_pwm(LCD_PWM),
.lcd_hsync(LCD_HSYNC),
.lcd_vsync(LCD_VSYNC),
.lcd_de(LCD_DEN),
.hsync_cnt(hsync_cnt),
.vsync_cnt(vsync_cnt),
.img_ack(lcd_rden),
.addr(lcd_rdaddr)
);
wire camera_wrreq, camera_wclk;
wire [15:0] camera_wrdat;
wire [19:0] camera_addr;
cameraReader u_cameraReader (
.clk(clk_cam),
.reset_n(RST_N),
.csi_xclk(CSI_XCLK),
.csi_pclk(CSI_PCLK),
.csi_data(CSI_D),
.csi_vsync(!CSI_VSYNC),
.csi_hsync(CSI_HREF),
.data_out(camera_wrdat),
.wrreq(camera_wrreq),
.wrclk(camera_wclk),
.wraddr(camera_addr)
);
img_cache uimg (
//write 45000*8
.dia (camera_wrdat),
.addra(camera_addr),
.cea (camera_wrreq),
.clka (camera_wclk),
.rsta (!RST_N),
//read 22500*16
.dob (lcd_rddat),
.addrb(lcd_rdaddr),
.ceb (lcd_rden),
.clkb (clk_lcd),
.rstb (!RST_N)
);
// assign TESTA = fifo_we;
// assign TESTB = CSI_PCLK;
// assign TESTC = CSI_VSYNC;
// assign TESTD = CSI_HREF;
// assign OD = CSI_D;
assign R = lcd_rden ? {lcd_rddat[15:11], lcd_rddat[15:13]} : 8'h00;
assign G = lcd_rden ? {lcd_rddat[10:5], lcd_rddat[10:9]} : 8'h00;
assign B = lcd_rden ? {lcd_rddat[4:0], lcd_rddat[4:2]} : 8'h00;
endmodule
| 6.936452 |
module test_cmp8;
reg [7:0] a, b;
wire eq, less, more;
cmp #(
.WIRE(8)
) test_cmp (
a,
b,
eq,
more,
less
);
initial begin
$dumpfile("signal_cmp.vcd");
$dumpvars;
$display("\t\ttime, \ta, \tb, \teq, \tmore, \tless\n");
$monitor("%d \t%d \t%d \t%b \t%b \t%b", $time, a, b, eq, more, less);
a = 0;
b = 0;
#5;
a = 22;
b = 12;
#5;
a = 12;
b = 22;
#5;
a = 22;
b = 22;
end
endmodule
| 7.668232 |
module test_comb (
input clk,
resetn,
load,
go,
input [2:0] color_in,
input [6:0] coordinate,
output [7:0] x_out,
output [6:0] y_out,
output [2:0] color_out
);
wire ld_x, ld_y, ld_color, writeEn;
control c0 (
.clk(clk),
.resetn(resetn),
.load(load),
.go(go),
.ld_x(ld_x),
.ld_y(ld_y),
.ld_color(ld_color),
.writeEn(writeEn)
);
datapath d0 (
.clk(clk),
.color_in(color_in[2:0]),
.resetn(resetn),
.ld_x(ld_x),
.ld_y(ld_y),
.ld_color(ld_color),
.coordinate(coordinate[6:0]),
.x_out(x_out),
.y_out(y_out),
.color_out(color_out)
);
endmodule
| 6.882408 |
module test_combined;
// Inputs
reg sel;
reg clock;
reg reset;
reg signed [2:0] taps;
reg [7:0] normal_input;
// Outputs
wire [7:0] error;
wire [7:0] total_error;
wire [31:0] count;
// Instantiate the Unit Under Test (UUT)
test_control uut (
.sel(sel),
.clock(clock),
.reset(reset),
.taps(taps),
.normal_input(normal_input),
.error(error),
.total_error(total_error),
.count(count)
);
initial begin
clock = 0;
forever #50 clock = ~clock;
end
initial begin
// Initialize Inputs
reset = 0;
sel = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 1;
sel = 1;
#200;
reset = 0;
sel = 1;
// Add stimulus here
end
initial begin
// Initialize Inputs
normal_input = 8'b0;
taps = 3;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
normal_input = 8'd8;
taps = 3;
#20;
normal_input = 8'd100;
taps = 3;
#20;
normal_input = 8'd250;
taps = 3;
#20;
normal_input = 8'd0;
taps = 3;
#20;
normal_input = -8'd5;
taps = 3;
#20;
end
endmodule
| 7.243963 |
module And2 (
input [1:0] I,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'h8888)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(1'b0),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 And2_inst2 (
.I({I1[2], I0[2]}),
.O(And2_inst2_O)
);
And2 And2_inst3 (
.I({I1[3], I0[3]}),
.O(And2_inst3_O)
);
assign O = {And2_inst3_O, And2_inst2_O, And2_inst1_O, And2_inst0_O};
endmodule
| 7.022857 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Mux2x1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire Mux2_inst0_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
assign O = {Mux2_inst0_O};
endmodule
| 6.963017 |
module FullAdder (
input I0,
input I1,
input CIN,
output O,
output COUT
);
wire SB_LUT4_inst0_O;
wire SB_CARRY_inst0_CO;
SB_LUT4 #(
.LUT_INIT(16'h9696)
) SB_LUT4_inst0 (
.I0(I0),
.I1(I1),
.I2(CIN),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
SB_CARRY SB_CARRY_inst0 (
.I0(I0),
.I1(I1),
.CI(CIN),
.CO(SB_CARRY_inst0_CO)
);
assign O = SB_LUT4_inst0_O;
assign COUT = SB_CARRY_inst0_CO;
endmodule
| 7.610141 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire SB_DFF_inst0_Q;
wire SB_DFF_inst1_Q;
SB_DFF SB_DFF_inst0 (
.C(CLK),
.D(I[0]),
.Q(SB_DFF_inst0_Q)
);
SB_DFF SB_DFF_inst1 (
.C(CLK),
.D(I[1]),
.Q(SB_DFF_inst1_Q)
);
assign O = {SB_DFF_inst1_Q, SB_DFF_inst0_Q};
endmodule
| 6.626169 |
module Counter2 (output [1:0] O, input CLK);
wire [1:0] Add2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2 Add2_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_inst0_O));
Register2 Register2_inst0 (.I(Add2_inst0_O), .O(Register2_inst0_O), .CLK(CLK));
assign O = Register2_inst0_O;
endmodule
| 7.166421 |
module Counter1 (output [0:0] O, input CLK);
wire [0:0] Add1_inst0_O;
wire [0:0] Register1_inst0_O;
Add1 Add1_inst0 (.I0(Register1_inst0_O), .I1(1'd1'), .O(Add1_inst0_O));
Register1 Register1_inst0 (.I(Add1_inst0_O), .O(Register1_inst0_O), .CLK(CLK));
assign O = Register1_inst0_O;
endmodule
| 6.856271 |
module Decode_0_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.171146 |
module Decode_1_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h2)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 6.999049 |
module Decode_2_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h4)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.241425 |
module Decode_3_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 6.911161 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 And2_inst2 (
.I({I1[2], I0[2]}),
.O(And2_inst2_O)
);
And2 And2_inst3 (
.I({I1[3], I0[3]}),
.O(And2_inst3_O)
);
assign O = {And2_inst3_O, And2_inst2_O, And2_inst1_O, And2_inst0_O};
endmodule
| 7.022857 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire Mux2_inst0_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
assign O = {Mux2_inst0_O};
endmodule
| 6.963017 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_inst1 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[1]),
.Q (FDRSE_inst1_Q)
);
assign O = {FDRSE_inst1_Q, FDRSE_inst0_Q};
endmodule
| 6.626169 |
module Counter2 (output [1:0] O, input CLK);
wire [1:0] Add2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2 Add2_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_inst0_O));
Register2 Register2_inst0 (.I(Add2_inst0_O), .O(Register2_inst0_O), .CLK(CLK));
assign O = Register2_inst0_O;
endmodule
| 7.166421 |
module Counter1 (output [0:0] O, input CLK);
wire [0:0] Add1_inst0_O;
wire [0:0] Register1_inst0_O;
Add1 Add1_inst0 (.I0(Register1_inst0_O), .I1(1'd1'), .O(Add1_inst0_O));
Register1 Register1_inst0 (.I(Add1_inst0_O), .O(Register1_inst0_O), .CLK(CLK));
assign O = Register1_inst0_O;
endmodule
| 6.856271 |
module Decode_0_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h1)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.171146 |
module Decode_1_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h2)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 6.999049 |
module Decode_2_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h4)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.241425 |
module Decode_3_2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 6.911161 |
module And2 (
input [1:0] I,
output O
);
wire LUT2_inst0_O;
LUT2 #(
.INIT(4'h8)
) LUT2_inst0 (
.I0(I[0]),
.I1(I[1]),
.O (LUT2_inst0_O)
);
assign O = LUT2_inst0_O;
endmodule
| 7.880137 |
module And2x4 (
input [3:0] I0,
input [3:0] I1,
output [3:0] O
);
wire And2_inst0_O;
wire And2_inst1_O;
wire And2_inst2_O;
wire And2_inst3_O;
And2 And2_inst0 (
.I({I1[0], I0[0]}),
.O(And2_inst0_O)
);
And2 And2_inst1 (
.I({I1[1], I0[1]}),
.O(And2_inst1_O)
);
And2 And2_inst2 (
.I({I1[2], I0[2]}),
.O(And2_inst2_O)
);
And2 And2_inst3 (
.I({I1[3], I0[3]}),
.O(And2_inst3_O)
);
assign O = {And2_inst3_O, And2_inst2_O, And2_inst1_O, And2_inst0_O};
endmodule
| 7.022857 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire LUT3_inst0_O;
LUT3 #(
.INIT(8'hCA)
) LUT3_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.O (LUT3_inst0_O)
);
assign O = LUT3_inst0_O;
endmodule
| 7.615389 |
module Mux2x1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire Mux2_inst0_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
assign O = {Mux2_inst0_O};
endmodule
| 6.963017 |
module Register2 (
input [1:0] I,
output [1:0] O,
input CLK
);
wire FDRSE_inst0_Q;
wire FDRSE_inst1_Q;
FDRSE #(
.INIT(1'h0)
) FDRSE_inst0 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[0]),
.Q (FDRSE_inst0_Q)
);
FDRSE #(
.INIT(1'h0)
) FDRSE_inst1 (
.C (CLK),
.CE(1'b1),
.R (1'b0),
.S (1'b0),
.D (I[1]),
.Q (FDRSE_inst1_Q)
);
assign O = {FDRSE_inst1_Q, FDRSE_inst0_Q};
endmodule
| 6.626169 |
module Counter2 (output [1:0] O, input CLK);
wire [1:0] Add2_inst0_O;
wire [1:0] Register2_inst0_O;
Add2 Add2_inst0 (.I0(Register2_inst0_O), .I1(2'd1'), .O(Add2_inst0_O));
Register2 Register2_inst0 (.I(Add2_inst0_O), .O(Register2_inst0_O), .CLK(CLK));
assign O = Register2_inst0_O;
endmodule
| 7.166421 |
module Counter1 (output [0:0] O, input CLK);
wire [0:0] Add1_inst0_O;
wire [0:0] Register1_inst0_O;
Add1 Add1_inst0 (.I0(Register1_inst0_O), .I1(1'd1'), .O(Add1_inst0_O));
Register1 Register1_inst0 (.I(Add1_inst0_O), .O(Register1_inst0_O), .CLK(CLK));
assign O = Register1_inst0_O;
endmodule
| 6.856271 |
module test_complex_gate;
reg e1, e2, e3;
wire out_aoi, out_ao;
gate_aoi aoi_inst (
out_aoi,
{e3, e2, e1}
);
gate_ao ao_inst (
out_ao,
{e3, e2, e1}
);
initial begin
$dumpfile("signal_test_serial_gate.vcd");
$dumpvars;
$monitor("time %d\ne1\t%b\ne2\t%b\ne3\t%b\naoi\t%b\nao\t%b\n\n", $time, e1, e2, e3, out_aoi,
out_ao);
e1 <= 0;
e2 <= 0;
e3 <= 0;
#10;
e1 <= 1;
#10;
e1 <= 0;
e2 <= 1;
#10;
e1 <= 1;
#10;
e1 <= 0;
e2 <= 0;
e3 <= 1;
#10;
e1 <= 1;
#10;
e1 <= 0;
e2 <= 1;
#10;
e1 <= 1;
#10;
end
endmodule
| 7.497789 |
module test_contador4;
wire [3:0] cuenta, cuenta1;
wire enext, enext1;
reg e;
reg nr, ck;
cont4 dut (
.Cuenta(cuenta),
.Enext(enext),
.nR(nr),
.E(e),
.CK(ck)
);
cont4 dut1 (
.Cuenta(cuenta1),
.Enext(enext1),
.nR(nr),
.E(enext),
.CK(ck)
);
initial begin
nr = 0;
e = 0;
ck = 0;
#15;
nr = 1;
end
always begin
wait (nr == 1);
#10 ck = 0;
#10 ck = 1;
end
initial begin
wait (nr == 1);
#65;
e = 1;
end
endmodule
| 6.891576 |
module test_control ();
event error_detected;
integer error_count;
reg verbose_msg;
// initialize debug variables
initial begin
error_count = 0;
verbose_msg = 0;
end
// count the number error
always @(error_detected) begin
error_count = error_count + 1;
end
// enabling/disabling message
task msg_enable;
input [20*8:1] msg_src;
input msg_enable;
begin
verbose_msg = msg_enable;
if (msg_enable) $display(" At time %t ** %s: enabling messages", $time, msg_src);
else $display(" At time %t ** %s: disabling messages", $time, msg_src);
end
endtask // msg
// generating message
task msg;
input [20*8:1] msg_src;
input [40*8:1] msg_text;
begin
if (verbose_msg) $display(" At time %t ** %s: Msg: %s", $time, msg_src, msg_text);
end
endtask // msg
// generating long message
task msgl;
input [40*8:1] msg_src;
input [80*8:1] msg_text;
begin
if (verbose_msg) $display(" At time %t ** %s: Msg: %s", $time, msg_src, msg_text);
end
endtask // msg
// generating the error message
task err;
input [20*8:1] err_src;
input [40*8:1] err_text;
begin
->error_detected;
$display("Time %0d, %s Error: %s", $time, err_src, err_text);
end
endtask // err
task finish_test;
begin
$display("****************************************");
if (error_count == 0) $display("* TEST: PASSED");
else $display("* TEST: FAILED\n*\tError(s) = %d", error_count);
$display("****************************************");
end
endtask
endmodule
| 6.84566 |
module: controlclk
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_controlclk;
// Inputs
reg Clk;
// Outputs
wire clk_out;
// Instantiate the Unit Under Test (UUT)
controlclk uut (
.Clk(Clk),
.clk_out(clk_out)
);
initial begin
// Initialize Inputs
Clk = 0;
forever begin
#10 Clk = ~Clk;end
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.885783 |
module test_Controle;
reg [2:0] OPcode;
reg bit_menos_sig;
wire halt;
wire addi;
wire jump;
wire beq;
wire dadoEscrito;
wire acessarMemoria;
wire imediato;
wire escreveMemoria;
wire leMemoria;
wire [1:0] operacaoULA;
wire escreveRegistrador;
wire lw;
initial begin
$display("add");
OPcode = 0;
bit_menos_sig = 0;
#1 $display("halt");
bit_menos_sig = 1;
#1 $display("lw");
OPcode = 3; // mesmo o bit_menos_sig=1 nao ocorrera halt
// pq so temos um possivel halt no add
#1 $display("beq");
OPcode = 2;
end
initial begin
$monitor(
"OPcode=%b bit_menos_sig=%b halt=%b addi=%b jump=%b\nbeq=%b dadoEscrito=%b acessarMemoria=%b imediato=%b\nescreveMemoria=%b leMemoria=%b operacaoULA=%b\nescreveRegistrador=%b lw=%b\n\n",
OPcode, bit_menos_sig, halt, addi, jump, beq, dadoEscrito, acessarMemoria, imediato,
escreveMemoria, leMemoria, operacaoULA, escreveRegistrador, lw);
end
Controle gate1 (
OPcode,
bit_menos_sig,
halt,
addi,
jump,
beq,
dadoEscrito,
acessarMemoria,
imediato,
escreveMemoria,
leMemoria,
operacaoULA,
escreveRegistrador,
lw
);
endmodule
| 6.967645 |
module test_Control_Unit ();
parameter word_size = 10, op_size = 4, state_size = 4;
parameter address_size = 8, data_size = 8;
parameter src0_size = 2, src1_size = 2, dest_size = 2, Sel1_size = 3, Sel2_size = 3;
// State Codes
// parameter S_idle = 0, S_fet1 = 1, S_fet2 = 2, S_dec = 3;
// parameter S_ex1 = 4, S_rd1 = 5, S_rd2 = 6;
// parameter S_wr1 = 7, S_wr2 = 8, S_br1 = 9, S_br2 = 10, S_halt = 11, S_nop = 12;
// Opcodes
// parameter ADD = 0, SUB = 1, AND = 2, OR = 3, NOT = 4;
// parameter SIZ = 5'b01010;
// parameter NOP = 5'b01011;
// parameter OP_5 = 4'b0101;
// parameter JUMP = 4'b011x, STORE = 4'b100x,LOAD = 4'b101x, SAVE = 4'b11xx;
// Source and Destination Register Codes
// parameter R0 = 0, R1 = 1, R2 = 2, R3 = 3;
// See textbook for output, input, and reg declarations
wire Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC;
wire [Sel1_size-1:0] Sel_Bus_1a_Mux, Sel_Bus_1b_Mux;
wire [Sel2_size-1:0] Sel_Bus_2_Mux;
wire Load_IR, Load_Add_R, Load_Reg_Z, write;
wire [address_size-1:0] address_decoded;
wire [data_size-1:0] constant_decoded;
reg [word_size-1:0] instruction;
reg zero, clk, rst;
wire [state_size-1:0] state = unit1.state[state_size-1:0];
wire [state_size-1:0] next_state = unit1.next_state[state_size-1:0];
//reg Load_R0,Load_R1,Load_R2,Load_R3,Load_PC,Inc_PC;
//reg Load_IR,Load_Add_R;
Control_Unit unit1 (
Load_R0,
Load_R1,
Load_R2,
Load_R3,
Load_PC,
Inc_PC,
Sel_Bus_1a_Mux,
Sel_Bus_1b_Mux,
Sel_Bus_2_Mux,
Load_IR,
Load_Add_R,
Load_Reg_Z,
write,
address_decoded,
constant_decoded,
instruction,
zero,
clk,
rst
);
initial begin
clk = 0;
end
always #5 clk = ~clk;
initial begin
rst = 1;
zero = 0;
instruction[word_size-1:0] = 10'b0000000110; //r2 = r1 + r0
zero = 0;
instruction[word_size-1:0] = 10'b0100001100; //ro = ~r0
#35 zero = 0;
instruction[word_size-1:0] = 10'b01010_10101; //skip if zero = 1
#35 zero = 1;
instruction[word_size-1:0] = 10'b01010_10101; //skip if zero = 1
#35 zero = 1;
instruction[word_size-1:0] = 10'b01011_10101; //nop
#35 zero = 0;
instruction[word_size-1:0] = 10'b011_0001111; //jump to addr = 15
#35 zero = 1;
instruction[word_size-1:0] = 10'b100_0000011; //store to address = 3
#35 zero = 1;
instruction[word_size-1:0] = 10'b101_0000000; //load from address = 7
#35 zero = 1;
instruction[word_size-1:0] = 10'b11_0010_0000; //save 32 to r0
end
endmodule
| 7.937864 |
modules for testbench
// notes :
//
// Copyright Illinois Institute of Technology
//
// Top level stimulus module
module stimulus;
reg [15:0] endangle;
reg [3:0] addr;
reg load;
reg clock;
reg Clk;
wire [15:0] sin, cos;
wire [15:0] data, currentangle;
integer handle3;
integer desc3;
cordic ef1(sin, cos, data, currentangle,
endangle, addr, load, clock);
initial
begin
Clk = 1'b1;
forever #5 Clk = ~Clk;
end
initial
begin
handle3 = $fopen("cordic.out");
#600 $finish;
end
always
begin
desc3 = handle3;
#5 $fdisplay(desc3, "%b %h %b %b || %b %b %h %h",
endangle, addr, clock, load, sin, cos, data, currentangle);
end
initial
begin
#0 clock = 1'b0;
#0 addr = 4'b0000;
#0 endangle = 16'h2500;
#0 load = 1'b1;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b0001;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b0010;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b0011;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b0100;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b0101;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b0110;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b0111;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b1000;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b1001;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b1010;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b1011;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b1100;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b1101;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b1110;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
#0 addr = 4'b1111;
#0 load = 1'b0;
#20 clock = 1'b1;
#20 clock = 1'b0;
end
endmodule
| 6.862012 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width2 (
input [1:0] in_data[1:0],
input [0:0] in_sel,
output [1:0] out
);
wire [1:0] _join_out;
coreir_mux #(
.width(2)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xOutBits2 (
input [1:0] I0,
input [1:0] I1,
input S,
output [1:0] O
);
wire [1:0] coreir_commonlib_mux2x2_inst0_out;
wire [1:0] coreir_commonlib_mux2x2_inst0_in_data[1:0];
assign coreir_commonlib_mux2x2_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x2_inst0_in_data[0] = I0;
commonlib_muxn__N2__width2 coreir_commonlib_mux2x2_inst0 (
.in_data(coreir_commonlib_mux2x2_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x2_inst0_out)
);
assign O = coreir_commonlib_mux2x2_inst0_out;
endmodule
| 7.816223 |
module Mux2xOutBit (
input I0,
input I1,
input S,
output O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data(coreir_commonlib_mux2x1_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);
assign O = coreir_commonlib_mux2x1_inst0_out[0];
endmodule
| 8.564631 |
module test_correct_io (
G1,
G2,
G3,
G4,
G5_0,
G5_1,
G17,
G18,
G19,
G20,
G21,
G22_0,
G22_1
);
// Comments Inside Module
input G1, G2, G3, G4;
/* Comments Inside Module */
input G5_0, G5_1;
output G17, G18, G19, G20, G21;
output G22_0, G22_1;
wire G8_0, G8_1;
nand NAND2_0 (G8_0, G1, G3);
nor NOR2_0 (G17, G8_1, 1'b1);
and AND2_0 (G18, G2, G5_0);
xor XOR2_0 (G22_0, G5_1, G4);
assign G8_1 = 1'b1;
assign G19 = G1 & G2 & (G3 ^ G4);
assign G20 = G17 ^ (G8_0 & G5_0);
assign G22_1 = G1 & (~G2 | 1'b1);
assign G21 = 1'b0;
endmodule
| 6.559825 |
module test_timer;
// Inputs
reg clk;
reg clrn;
reg loadn;
reg enable;
reg [3:0] data;
// Output
wire [3:0] out;
wire tc;
wire zero;
// Instantiate the Timer
counter_mod10 uut (
.clock (clk),
.clrn (clrn),
.loadn (loadn),
.enable(enable),
.data (data),
.ones (out),
.zero (zero)
);
always #1 clk <= ~clk;
initial begin
$dumpfile("test_timer.vcd");
$dumpvars(0, test_timer);
clk <= 1;
loadn <= 0;
data <= 4'b1001;
clrn <= 1;
enable <= 1;
#2 loadn <= 0;
data <= 4'b0011;
clrn <= 1;
#2 loadn <= 0;
data <= 4'b0010;
clrn <= 1;
#2 loadn <= 1;
data <= 4'b0011;
clrn <= 1;
#30 clrn <= 0;
#500 $finish;
end
endmodule
| 7.012348 |
module test_timer;
// Inputs
reg clk;
reg clrn;
reg loadn;
reg enable;
reg [3:0] data;
// Output
wire [3:0] out;
wire tc;
wire zero;
// Instantiate the Timer
counter_mod6 uut (
.clock (clk),
.clrn (clrn),
.loadn (loadn),
.enable(enable),
.data (data),
.ones (out),
.zero (zero)
);
always #1 clk <= ~clk;
initial begin
$dumpfile("test_timer.vcd");
$dumpvars(0, test_timer);
clk <= 1;
loadn <= 0;
data <= 4'b1001;
clrn <= 1;
enable <= 1;
#2 loadn <= 0;
data <= 4'b0011;
clrn <= 1;
#2 loadn <= 0;
data <= 4'b0010;
clrn <= 1;
#2 loadn <= 1;
data <= 4'b0011;
clrn <= 1;
#30 clrn <= 0;
#500 $finish;
end
endmodule
| 7.012348 |
module: counters
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_counters;
// Inputs
reg clk;
reg reset;
reg uart_REC_dataH;
// Outputs
wire [7:0] cntb;
wire uart_XMIT_dataH;
// Instantiate the Unit Under Test (UUT)
counters uut (
.cntb(cntb),
.clk(clk),
.reset(reset),
.uart_XMIT_dataH(uart_XMIT_dataH),
.uart_REC_dataH(uart_REC_dataH)
);
initial begin
// Initialize Inputs
reset = 1;
uart_REC_dataH = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
// Add stimulus here
end
always begin
clk = 0; #5;
clk = 1; #5;
end
endmodule
| 7.236042 |
module test_counter_4;
reg clk;
reg rst_n;
wire [3:0] q;
counter_4 U0 (
q,
clk,
rst_n
);
always #10 clk = ~clk;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
endmodule
| 6.546598 |
module test_counter_47 ();
reg clk = 0, en = 1, clear = 0, set = 0, add = 1;
reg [5:0] num_i = 1;
wire [5:0] num_o;
counter_47 c47 (
clk,
en,
clear,
set,
add,
num_i,
num_o
);
initial
fork
#23 clear = 1;
#33 clear = 0;
#43 en = 0;
#53 en = 1;
#103 set = 1;
#103 num_i = 16;
#113 num_i = 44;
#123 num_i = 0;
#123 set = 0;
#173 add = 0;
#223 add = 1;
forever #5 clk = ~clk;
join
endmodule
| 6.546598 |
module test_counter_4_1hz;
wire [3:0] b;
reg clk, rst_n;
counter_4_1hz U0 (
b,
clk,
rst_n
);
always #10 clk = ~clk;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
endmodule
| 6.546598 |
module test_counter_down_30;
wire [7:0] cnt;
reg clk;
reg rst_n;
counter_down_30 U0 (
cnt,
clk,
rst_n
);
always #10 clk = ~clk;
initial begin
clk = 0;
rst_n = 1;
#10 rst_n = 0;
#10 rst_n = 1;
end
endmodule
| 6.546598 |
module stream_gen (
input i_clk,
input i_enable,
input i_send_esc,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = i_send_esc ? 8'd27 : d;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction happens, increment
d <= d + 8'd1;
end
end
endmodule
| 6.890266 |
module test_cpstr_desc;
reg clk = 0;
reg rst = 0;
reg en = 0;
wire [7:0] src_data;
wire src_valid;
wire src_ready;
wire [7:0] dst_data;
wire dst_valid;
reg dst_ready = 0;
wire [7:0] esc_data;
wire esc_valid;
reg esc_ready = 0;
reg send_esc = 0;
stream_gen gen (
.i_clk(clk),
.i_enable(en),
.i_ready(src_ready),
.i_send_esc(send_esc),
.o_data(src_data),
.o_valid(src_valid)
);
cpstr_desc dut (
.i_clk(clk),
.i_rst(rst),
//
.i_data(src_data),
.i_valid(src_valid),
.o_ready(src_ready),
//
.o_data(dst_data),
.o_valid(dst_valid),
.i_ready(dst_ready),
//
.o_esc_valid(esc_valid),
.o_esc_data(esc_data),
.i_esc_ready(esc_ready)
);
always #5 clk = ~clk;
always @(posedge clk) begin
if (src_valid && src_ready) begin
$display("SRC: 0x%02x", src_data);
end
if (dst_valid && dst_ready) begin
$display("DST: 0x%02x", dst_data);
end
if (esc_valid && esc_ready) begin
$display("ESC: 0x%02x", dst_data);
end
end
initial begin
$dumpfile("test_cpstr_desc.vcd");
$dumpvars;
repeat (5) @(posedge clk);
rst <= 1;
repeat (1) @(posedge clk);
rst <= 0;
// Pass
repeat (2) @(posedge clk);
en <= 1;
repeat (2) @(posedge clk);
dst_ready <= 1;
esc_ready <= 1;
repeat (5) @(posedge clk);
// Stall
dst_ready <= 0;
repeat (2) @(posedge clk);
// Unstall
dst_ready <= 1;
repeat (4) @(posedge clk);
// generate 4 esc chars
send_esc <= 1;
@(posedge clk);
while (!(src_ready && src_valid)) @(posedge clk);
@(posedge clk);
while (!(src_ready && src_valid)) @(posedge clk);
@(posedge clk);
while (!(src_ready && src_valid)) @(posedge clk);
@(posedge clk);
while (!(src_ready && src_valid)) @(posedge clk);
// some normal bytes
send_esc <= 0;
repeat (4) @(posedge clk);
// generate one esc char + normal byte
send_esc <= 1;
@(posedge clk);
while (!(src_ready && src_valid)) @(posedge clk);
send_esc <= 0;
@(posedge clk);
send_esc <= 1;
@(posedge clk);
while (!(src_ready && src_valid)) @(posedge clk);
send_esc <= 0;
esc_ready <= 0;
repeat (5) @(posedge clk);
esc_ready <= 1;
repeat (5) @(posedge clk);
en <= 0;
repeat (5) @(posedge clk);
$finish;
end
endmodule
| 6.951511 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = (d[2:0] < 5) ? (d + 1) : 8'd27;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction happens, increment
d <= d + 8'd1;
end
end
endmodule
| 6.890266 |
module test_cpstr_esc;
reg clk = 0;
reg rst = 0;
reg en = 0;
wire [7:0] src_data;
wire src_valid;
wire src_ready;
wire [7:0] dst_data;
wire dst_valid;
reg dst_ready = 0;
reg [7:0] esc_data = 0;
reg esc_valid = 0;
wire esc_ready;
stream_gen gen (
.i_clk(clk),
.i_enable(en),
.i_ready(src_ready),
.o_data(src_data),
.o_valid(src_valid)
);
cpstr_esc dut (
.i_clk(clk),
.i_rst(rst),
//
.i_data(src_data),
.i_valid(src_valid),
.o_ready(src_ready),
//
.o_data(dst_data),
.o_valid(dst_valid),
.i_ready(dst_ready),
//
.i_esc_valid(esc_valid),
.i_esc_data(esc_data),
.o_esc_ready(esc_ready)
);
always #5 clk = ~clk;
always @(posedge clk) begin
if (src_valid && src_ready) begin
$display("SRC: 0x%02x", src_data);
end
if (esc_valid && esc_ready) begin
$display("ESC: 0x%02x", esc_data);
end
if (dst_valid && dst_ready) begin
$display("DST: 0x%02x", dst_data);
end
end
initial begin
$dumpfile("test_cpstr_esc.vcd");
$dumpvars;
repeat (5) @(posedge clk);
rst <= 1;
repeat (1) @(posedge clk);
rst <= 0;
// Pass
repeat (2) @(posedge clk);
en <= 1;
repeat (2) @(posedge clk);
dst_ready <= 1;
repeat (5) @(posedge clk);
// Stall
dst_ready <= 0;
repeat (2) @(posedge clk);
// Unstall
dst_ready <= 1;
repeat (4) @(posedge clk);
// Esc
esc_data <= 8'hBE;
esc_valid <= 1;
@(posedge clk);
while (!esc_ready) @(posedge clk);
esc_valid <= 0;
repeat (3) @(posedge clk);
// Esc with stall
repeat (2) @(posedge clk);
esc_valid <= 1;
repeat (1) @(posedge clk);
dst_ready <= 0;
repeat (2) @(posedge clk);
dst_ready <= 1;
@(posedge clk);
while (!esc_ready) @(posedge clk);
esc_valid <= 0;
dst_ready <= 0;
repeat (2) @(posedge clk);
dst_ready <= 1;
repeat (5) @(posedge clk);
// Stall
dst_ready <= 0;
repeat (5) @(posedge clk);
dst_ready <= 1;
repeat (5) @(posedge clk);
en <= 0;
// End
repeat (5) @(posedge clk);
$finish;
end
endmodule
| 7.697817 |
module stream_gen (
input i_clk,
input i_enable,
input i_send_esc,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [7:0] d;
assign o_valid = i_enable;
assign o_data = i_send_esc ? 8'd27 : d;
initial begin
d <= 8'd0;
end
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction happens, increment
d <= d + 8'd1;
end
end
endmodule
| 6.890266 |
module: crc16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_crc16;
// Inputs
reg clk;
reg rst;
reg en;
reg data;
// Outputs
wire [15:0] crc;
// Instantiate the Unit Under Test (UUT)
crc16 uut (
.clk(clk),
.rst(rst),
.en(en),
.data(data),
.crc(crc)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
en = 0;
data = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.832425 |
module test_crc1632p8;
// Inputs
reg iocs;
reg [2:0] ioaddr;
reg [15:0] din;
reg iowr;
reg iord;
reg clk;
reg clk2x;
reg rst;
// Outputs
wire [15:0] dout0, dout1;
// Instantiate the Units Under Test (UUT)
crc1632p8 uut0 (
.iocs(iocs),
.ioaddr(ioaddr),
.din(din),
.iowr(iowr),
.dout(dout0),
.iord(iord),
.clk(clk),
.rst(rst)
);
crc1632 uut1 (
.iocs(iocs),
.ioaddr(ioaddr),
.din(din),
.iowr(iowr),
.dout(dout1),
.iord(iord),
.mclk(clk),
.dclk(clk2x),
.rst(rst)
);
always @(posedge clk2x) clk <= ~clk;
initial begin
// Initialize Inputs
iocs = 0;
ioaddr = 0;
din = 0;
iowr = 0;
iord = 0;
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// hardware reset
#5 clk2x = 0;
rst = 1;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
#5 clk2x = 0;
rst = 0;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
// test with 8 bit data
#5 clk2x = 0;
iocs = 1;
ioaddr = 3;
iowr = 1;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
#5 clk2x = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
repeat (16) begin
#5 clk2x = 0;
iocs = 1;
ioaddr = 0;
iowr = 1;
din = 16'h0037;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
repeat (4) begin
#5 clk2x = 0;
iocs = 0;
iowr = 0;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
end
end
repeat (8) begin
#5 clk2x = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
end
// test with 16 bit data
#5 clk2x = 0;
iocs = 1;
ioaddr = 3;
iowr = 1;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
#5 clk2x = 0;
iocs = 0;
ioaddr = 0;
iowr = 0;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
repeat (8) begin
#5 clk2x = 0;
iocs = 1;
ioaddr = 1;
iowr = 1;
din = 16'h3737;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
repeat (8) begin
#5 clk2x = 0;
iocs = 0;
iowr = 0;
#5 clk2x = 1;
#5 clk2x = 0;
#5 clk2x = 1;
end
end
end
endmodule
| 6.502039 |
module: control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_ctrl;
// Inputs
reg [5:0] op;
reg [5:0] funct;
// Outputs
wire RegDst;
wire RegWrite;
wire ALUSrc;
wire MemRead;
wire MemWrite;
wire MemtoReg;
wire Jump;
wire JumpReg;
wire Branch;
wire [3:0] ALUCtrl;
// Instantiate the Unit Under Test (UUT)
control uut (
.op(op),
.funct(funct),
.RegDst(RegDst),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemRead(MemRead),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.JumpReg(JumpReg),
.Branch(Branch),
.ALUCtrl(ALUCtrl)
);
initial begin
// Initialize Inputs
op = 0;
funct = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#20;
op = 6'h08;
funct = 6'h02;
#20;
op = 6'h0C;
funct = 6'h02;
#20;
op = 6'h0D;
funct = 6'h02;
#20;
op = 6'h0E;
funct = 6'h02;
#20;
op = 6'h0F;
funct = 6'h02;
#20;
op = 6'h23;
funct = 6'h02;
#20;
op = 6'h2B;
funct = 6'h02;
#20;
op = 6'h04;
funct = 6'h02;
#20;
op = 6'h05;
funct = 6'h02;
#20;
op = 6'h0A;
funct = 6'h02;
#20;
op = 6'h00;
funct = 6'h32;
#20;
funct = 6'h34;
#20;
funct = 6'h36;
#20;
funct = 6'h37;
#20;
funct = 6'h38;
#20;
funct = 6'h39;
#20;
funct = 6'h42;
#20;
funct = 6'h02;
#20;
funct = 6'h00;
end
endmodule
| 7.090636 |
module TOP;
//ALU inputs
reg [31:0] a, b;
reg [2:0] op;
reg CF_dataforwarded;
reg AF_dataforwarded;
wire [31:0] out;
wire [31:0] flags;
reg error;
reg error_free;
initial
begin
CF_dataforwarded = 0;
AF_dataforwarded = 0;
error_free = 1;
error = 0;
op = 3'b011;
a = 32'h0000_00AE;
b = 32'h0000_0000;
#`cycle //1
if(out != 32'h0000_0014)
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 32'h0000_002E;
b = 32'h0000_0000;
#`cycle //3
if(out != 32'h0000_0034)
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 32'hbcdabcda;
b = 32'h79867986;
#`cycle //5
if(out != (a + b))
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 32'h96579657;
b = 32'h34563456;
#`cycle //7
if(out != (a + b))
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("daa.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(*)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, recieved out = %x",
$time, a, b, out);
else
$strobe ("correct: time: %0d: a = %x, b = %x, out = %x",
$time, a, b, out);
alu32 u_alu_test (out, flags, a, b, op, CF_dataforwarded, AF_dataforwarded);
endmodule
| 7.259416 |
module test_dac8551;
reg clk = 0;
reg rst = 0;
reg wr = 0;
reg [23:0] wr_data = 0;
wire dac_sclk, dac_mosi, dac_sync_n, busy;
dac8551 #(
.CLK_DIV(2)
) dut (
.i_clk(clk),
.i_rst(rst),
.i_wr(wr),
.i_wr_data(wr_data),
.o_dac_sclk(dac_sclk),
.o_dac_mosi(dac_mosi),
.o_dac_sync_n(dac_sync_n),
.o_busy(busy)
);
always #5 clk = ~clk;
initial begin
$dumpfile("test_dac8551.vcd");
$dumpvars;
// Reset
rst <= 1;
@(posedge clk);
rst <= 0;
// Idle
repeat (5) @(posedge clk);
// Send data
wr_data <= 24'h876543;
wr <= 1;
@(posedge clk);
wr <= 0;
repeat (147) @(posedge clk);
// Send data back to back
wr_data <= 24'h777777;
wr <= 1;
@(posedge clk);
wr <= 0;
repeat (20) @(posedge clk);
wr_data <= 24'hCCCCCC;
wr <= 1;
@(posedge clk);
wr <= 0;
repeat (20) @(posedge clk);
wr_data <= 24'h666666;
wr <= 1;
@(posedge clk);
wr <= 0;
repeat (300) @(posedge clk);
$finish;
end
endmodule
| 6.807932 |
module test_data_join ();
reg clk;
reg rstn;
reg input_valid;
wire input_enable;
wire output_valid;
reg output_enable;
reg [3 : 0] data_in;
wire [7 : 0] data_out;
reg [7 : 0] joined_data;
data_join obj_data_join (
.clk(clk),
.rstn(rstn),
.input_valid(input_valid),
.input_enable(input_enable),
.output_valid(output_valid),
.output_enable(output_enable),
.data_in(data_in),
.data_out(data_out)
);
initial begin
clk = 0;
rstn = 1;
input_valid = 1;
output_enable = 1;
data_in = 0;
#0.1 rstn = 0;
#0.2 rstn = 1;
end
always begin
#1;
clk = ~clk;
end
always begin
#2;
output_enable = $random() % 2;
input_valid = $random() % 2;
data_in = $random() % 16;
end
always @(posedge clk or negedge rstn) begin
if (!rstn) begin
joined_data <= 0;
end else if (output_valid) begin
joined_data <= data_out;
end
end
endmodule
| 7.274198 |
module test_data_mem
(
clk_i,
rst_i,
Addr_i,
Read_en_i,
Read_data_o,
Write_en_i,
Wr_data_i
);
input clk_i, rst_i, Read_en_i, Write_en_i;
input [4:0] Addr_i;
input [`dw-1:0] Wr_data_i;
output [`dw-1:0] Read_data_o;
reg [`dw-1:0] Read_data_o;
reg [`dw-1:0] rf_reg [0:`dw-1];
integer i;
always@(negedge clk_i, `RESET_EDGE rst_i) // clk is negedge
begin
if (rst_i == `RESET_ON)
begin
rf_reg[0] <= 32'b10000000_00000000_00000000_00000010;
//rf_reg[1] <= 32'b10000000_00000000_00000000_00001110; //used for test SRA
rf_reg[1] <= 32'd12;
for (i = 2; i < `dw; i = i + 1)
rf_reg[i] <= `ZERO;
end
else if(Write_en_i)
rf_reg[Addr_i] <= Wr_data_i;
else if(Read_en_i)
Read_data_o <= rf_reg[Addr_i];
else
Read_data_o <= `ZERO;
end
endmodule
| 7.234184 |
module top ();
parameter STEP = 10;
reg [1:0] SEL;
reg [3:0] C0, C1, C2, C3;
wire [3:0] Y;
data_selector data_selector_instance (
.sel(SEL),
.c0 (C0),
.c1 (C1),
.c2 (C2),
.c3 (C3),
.y (Y)
);
initial begin
$dumpfile("test_data_selector.vcd");
$dumpvars(0, data_selector_instance);
C0 <= 4'b0001;
C1 <= 4'b0010;
C2 <= 4'b0011;
C3 <= 4'b0100;
#STEP SEL <= 2'b00;
#STEP $display("output y: %b", Y);
SEL <= 2'b01;
#STEP $display("output y: %b", Y);
SEL <= 2'b10;
#STEP $display("output y: %b", Y);
SEL <= 2'b11;
#STEP $display("output y: %b", Y);
end
endmodule
| 6.832792 |
module test_data_size_sel;
parameter sim_time = 15;
wire [ 1:0] DataSize;
reg [31:0] IR;
reg [ 1:0] DSS;
reg [ 3:0] counter;
data_size_selector dss (
DataSize,
IR,
DSS
);
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
counter = 0;
repeat (10) #2 counter = counter + 1;
end
always @(counter) begin
case (counter)
4'd0: begin
IR <= 32'b11100001111001100101101111011110;
DSS = 2'b00;
end
4'd1: begin
IR <= 32'b1110010101010110010100000_0_0_10100;
DSS = 2'b01;
end
4'd2: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b01;
end
4'd3: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b01;
end
4'd4: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b01;
end
4'd5: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b01;
end
4'd6: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b11;
end
4'd7: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b01;
end
4'd8: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b01;
end
4'd9: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b10;
end
default: begin
IR <= 32'b11100001111001100101101111011110;
DSS <= 2'b11;
end
endcase
end
initial begin
$display("IR\t\t\t\t\t\tDSS\tDataSize"); //imprime header
$monitor("%b\t%b\t%b", IR, DSS, DataSize); //imprime las señales
end
endmodule
| 6.931936 |
module TEST_DCT_COSTABLE #(
parameter PERIOD = 1000
) ();
reg clk = 0;
initial begin
clk = #PERIOD 1;
forever clk = #(PERIOD / 2) ~clk;
end
reg rst = 0;
initial begin
@(posedge clk);
rst <= 1;
repeat (5) @(posedge clk);
rst <= 0;
end
reg [4-1:0] r;
reg [4-1:0] c;
wire [8-1:0] o;
DCT_COSTABLE #(15, 7) dc (
r[0+:3],
c[0+:3],
o
);
initial begin
$display("start");
for (r = 0; r < 8; r = r + 1) begin
for (c = 0; c < 8; c = c + 1) begin
@(posedge clk) $write("%d ", $signed(o));
end
$display("");
end
repeat (10) @(posedge clk);
$display("end");
$finish();
end
endmodule
| 6.504284 |
module test_ddos #(
parameter TIME_WIDTH = 25,
parameter CNT_WIDTH = 10,
parameter HASH_BITS = 16
) (
input wire clk,
input wire rst,
input [ 15:0] len_thresh,
input [TIME_WIDTH-1:0] time_thresh,
input alert,
input [31:0] dst_ip,
input [15:0] payload_len,
input hdr_valid,
output ready,
output [CNT_WIDTH-1:0] occurence,
output alerted,
output occ_valid
);
ddos_detector #(
.TIME_WIDTH(TIME_WIDTH),
.CNT_WIDTH (CNT_WIDTH),
.HASH_BITS (HASH_BITS)
) ddos_inst (
.clk(clk),
.rst(rst),
.len_thresh(len_thresh),
.time_thresh(time_thresh),
.alert(alert),
.dst_ip(dst_ip),
.payload_len(payload_len),
.hdr_valid(hdr_valid),
.ready(ready),
.init_wr_addr(),
.init_wr_en (1'b0),
.occurence(occurence),
.alerted (alerted),
.occ_valid(occ_valid)
);
///////////////////////////////////////////////
////////////// Generating Waveform ////////////
///////////////////////////////////////////////
localparam LINE_WIDTH = TIME_WIDTH + CNT_WIDTH + 1;
localparam URAM_WIDTH = 2 * LINE_WIDTH;
integer i;
initial begin
for (i = 0; i < 2 ** (HASH_BITS - 1); i = i + 1) ddos_inst.mem[i] = {URAM_WIDTH{1'b0}};
$dumpfile("sim_build/test_ddos.fst");
$dumpvars(0, test_ddos);
#1;
end
endmodule
| 8.191907 |
module test_dds2k19;
// Inputs
reg dclk;
reg iq;
reg rst;
reg [31:0] frq;
// Outputs
wire [18:0] doxy;
reg [18:0] x0, x, y;
// Instantiate the Unit Under Test (UUT)
dds2k19 uut (
.doxy(doxy),
.dclk(dclk),
.iq (iq),
.rst (rst),
.frq (frq)
);
always @(posedge dclk) begin
x0 <= doxy; // delay X
if (~iq) x <= x0;
if (~iq) y <= doxy;
end
initial begin
// Initialize Inputs
iq = 0;
dclk = 0;
rst = 0;
frq = 0;
// Wait 100 ns for global reset to finish
#100;
// Clock DDS
repeat (16) begin
#5 iq = 1;
dclk = 0;
rst = 1;
frq = 32'h00040000; // Fo = Fs * 1/16384
#5 iq = 1;
dclk = 1;
#5 iq = 0;
dclk = 0;
#5 iq = 0;
dclk = 1;
end
repeat (16400) begin
#5 iq = 1;
dclk = 0;
rst = 0;
#5 iq = 1;
dclk = 1;
#5 iq = 0;
dclk = 0;
#5 iq = 0;
dclk = 1;
end
end
endmodule
| 6.692283 |
module: debounce
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_debounce;
// Inputs
reg clk;
reg reset;
reg sig_in;
reg unlock;
reg [31:0] pos_in;
reg [31:0] timeout;
// Outputs
wire sig_out;
wire sig_changed;
wire [31:0] pos_out;
wire [31:0] max_bounce;
wire [7:0] cycles;
// Instantiate the Unit Under Test (UUT)
debounce uut (
.clk(clk),
.reset(reset),
.sig_in(sig_in),
.unlock(unlock),
.pos_in(pos_in),
.timeout(timeout),
.sig_out(sig_out),
.sig_changed(sig_changed),
.pos_out(pos_out),
.max_bounce(max_bounce),
.cycles(cycles)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sig_in = 0;
unlock = 0;
pos_in = 0;
timeout = 20;
// Wait 100 ns for global reset to finish
#100;
reset = 1;
#100;
reset = 0;
// Add stimulus here
end
reg [31:0] cycle;
reg [31:0] cycle2;
initial begin
cycle = 0;
cycle2 = 0;
forever
begin
clk = 1;
#3
if (unlock == 1)
begin
unlock = 0;
end
pos_in = pos_in + 1;
case (cycle)
120: begin
sig_in = 1;
end
160: begin
unlock = 1;
end
200: begin
sig_in = 0;
end
240: begin
unlock = 1;
end
300: begin
sig_in = 1;
end
305: begin
sig_in = 0;
end
310: begin
sig_in = 1;
end
345: begin
unlock = 1;
end
350: begin
sig_in = 1;
end
355: begin
sig_in = 0;
end
362: begin
sig_in = 1;
end
365: begin
sig_in = 0;
end
375: begin
sig_in = 1;
end
endcase
#2;
clk = 0;
#5;
cycle = cycle + 1;
end;
end
endmodule
| 6.908371 |
module test_dec;
wire [7:0] D;
reg [2:0] IN;
reg EN;
dec U0 (
.d (D),
.in(IN),
.en(EN)
);
initial begin
IN = 3'b000;
EN = 1'b0;
#5 IN = 3'b001;
EN = 1'b0;
#5 IN = 3'b010;
EN = 1'b0;
#5 IN = 3'b011;
EN = 1'b0;
#5 IN = 3'b100;
EN = 1'b0;
#5 IN = 3'b101;
EN = 1'b0;
#5 IN = 3'b110;
EN = 1'b0;
#5 IN = 3'b111;
EN = 1'b0;
#5 IN = 3'b000;
EN = 1'b1;
#5 IN = 3'b001;
EN = 1'b1;
#5 IN = 3'b010;
EN = 1'b1;
#5 IN = 3'b011;
EN = 1'b1;
#5 IN = 3'b100;
EN = 1'b1;
#5 IN = 3'b101;
EN = 1'b1;
#5 IN = 3'b110;
EN = 1'b1;
#5 IN = 3'b111;
EN = 1'b1;
#5 $finish;
end
endmodule
| 7.203479 |
module Test_Decoder;
// Inputs
reg RST;
reg CLK;
reg [14:0] HADDR;
// Outputs
wire SEL_1;
wire SEL_2;
wire SEL_3;
wire [1:0] SELR;
// Instantiate the Unit Under Test (UUT)
Decoder uut (
.RST (RST),
.CLK (CLK),
.HADDR(HADDR),
.SEL_1(SEL_1),
.SEL_2(SEL_2),
.SEL_3(SEL_3),
.SELR (SELR)
);
always #15 CLK = !CLK;
initial begin
#500 RST = 1; // Reset test
#50 RST = 0;
end
initial begin
// Initialize Inputs
RST = 0;
CLK = 0;
HADDR = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#150 HADDR = 15'b000000000000000;
RST = 0;
#150 HADDR = 15'b010000000000000;
RST = 0; // Slave 1 select
#150 HADDR = 15'b100000000000000;
RST = 0; // Slave 2 select
#150 HADDR = 15'b110000000000000;
RST = 0; // Slave 3 select
#150 HADDR = 15'b000000000000000;
RST = 0;
end
endmodule
| 7.397423 |
module test_demux;
localparam SIZE_CTRL = 2;
parameter WIRE = 1;
wire [((2 ** SIZE_CTRL) * WIRE) - 1 : 0] out;
reg [WIRE - 1 : 0] in;
reg [SIZE_CTRL-1 : 0] ctrl;
demux #(
.SIZE_CTRL(SIZE_CTRL),
.WIRE(WIRE)
) demux0 (
ctrl,
in,
out
);
initial begin
$dumpfile("signal_demux.vcd");
$dumpvars;
$display("\t\ttime, \tout[0],\tout[1],\tout[2],\tout[3],\tin,\tctrl");
$monitor("%d \t%b \t%b \t%b \t%b \t%b \t%d", $time, out[0], out[1], out[2], out[3], in, ctrl);
in[0] = 1;
ctrl[0] = 0;
ctrl[1] = 0;
#5;
ctrl[0] = 1;
ctrl[1] = 0;
#5;
ctrl[0] = 0;
ctrl[1] = 1;
#5;
ctrl[0] = 1;
ctrl[1] = 1;
#5;
end
endmodule
| 7.324994 |
module test_demux8;
parameter SIZE_CTRL = 2;
parameter WIRE = 8;
wire [((2**SIZE_CTRL) * WIRE) - 1 : 0] out;
reg [ WIRE - 1 : 0] in;
reg [ SIZE_CTRL-1 : 0] ctrl;
integer cpt;
reg xin;
demux #(
.SIZE_CTRL(SIZE_CTRL),
.WIRE(WIRE)
) demux0 (
ctrl,
in,
out
);
initial begin
$dumpfile("signal_demux8.vcd");
$dumpvars;
$display("\t\ttime, \tout[0],\tout[1],\tout[2],\tout[3],\tin,\tctrl");
$monitor("%d \t%d \t%d \t%d \t%d \t%d \t%d", $time, out[7:0], out[15:8], out[23:16],
out[31:24], in, ctrl);
cpt = -1;
xin = 0;
while (
++cpt
<= (2 ** SIZE_CTRL) * WIRE - 1) begin
in[cpt] = xin;
xin = ~xin;
end
ctrl[0] = 0;
ctrl[1] = 0;
#5;
ctrl[0] = 1;
ctrl[1] = 0;
#5;
ctrl[0] = 0;
ctrl[1] = 1;
#5;
ctrl[0] = 1;
ctrl[1] = 1;
#5;
end
endmodule
| 6.856134 |
module demux_TB ();
reg in;
reg [1:0] select;
wire out3, out2, out1, out0;
Demux_1_4 my_demux (
in,
select,
{out3, out2, out1, out0}
);
always #3 in = ~in;
initial begin
$dumpfile("out.vcd");
$dumpvars(1, demux_TB);
in = 0;
select = 2'b00;
#20 select = 2'b01;
#20 select = 2'b10;
#20 select = 2'b11;
#20 $finish;
end
endmodule
| 7.176189 |
module demux_TB ();
reg in;
reg [1:0] select;
wire out3, out2, out1, out0;
Demux_1_4 my_demux (
in,
select,
{out3, out2, out1, out0}
);
always #3 in = ~in;
initial begin
$dumpfile("out.vcd");
$dumpvars(1, demux_TB);
in = 0;
select = 2'b00;
#20 select = 2'b01;
#20 select = 2'b10;
#20 select = 2'b11;
#20 $finish;
end
endmodule
| 7.176189 |
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