code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module testVGAOutput1 (
input clk,
input reset,
input sw0,
input sw1,
input sw2,
output reg R,
output reg G,
output reg B,
output reg HSync,
output reg VSync
);
wire HSync0;
wire VSync0;
wire [9:0] Col;
wire [8:0] Row;
wire Col0;
wire Row0;
wire screen_active;
wire PixelClock;
wire [4:0] xSupPix;
wire [3:0] ySupPix;
wire [4:0] xSubCount;
wire [4:0] ySubCount;
wire R0;
wire G0;
wire B0;
reg [8:0] rgbWordLoc; // = 1;
VGA_CTRL vga (
.Reset(reset),
.HSync(HSync0),
.VSync(VSync0),
.Clk50(clk),
.PClk(PixelClock),
.Col(Col),
.Row(Row),
.Col0(Col0),
.Row0(Row0),
.Active(screen_active)
);
VGASuperPixConverter supPixConvert (
Col,
Row,
xSupPix,
ySupPix,
xSubCount,
ySubCount
);
vgaBitGen bitGen (
rgbWordLoc,
xSubCount,
ySubCount,
clk,
R0,
G0,
B0
);
always @(posedge clk) begin
rgbWordLoc = ySupPix;
end
/*
* output HSync/VSync and RGB data
*/
always @(posedge clk) begin
HSync <= HSync0;
VSync <= VSync0;
if (screen_active) begin
begin
R <= R0;
G <= G0;
B <= B0;
end
end else begin
B <= 0;
G <= 0;
R <= 0;
end
end
endmodule
| 7.445325 |
module xnorgate (
output s,
input a,
input b
);
assign s = ~(a ^ b);
endmodule
| 6.74222 |
module testxnorgate;
// ---------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
xnorgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
end
// ------------------------- parte principal
initial begin
$display("Exercicio 3 - Afonso Spinelli - 266304");
$display("Tabela Verdade para porta XNOR - v1.0\n");
$display("~(a ^ b) = s\n");
#1 $display("~(%b ^ %b) = %b", a, b, s);
a = 0;
b = 1;
#1 $display("~(%b ^ %b) = %b", a, b, s);
a = 1;
b = 0;
#1 $display("~(%b ^ %b) = %b", a, b, s);
a = 1;
b = 1;
#1 $display("~(%b ^ %b) = %b", a, b, s);
end
endmodule
| 7.028584 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_01 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 1;
#1 a = 1;
b = 0;
#1 a = 1;
b = 1;
end
endmodule
| 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2;
assign temp1 = ~p & q;
assign temp2 = p & ~q;
assign s = temp1 | temp2;
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_02 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 1;
#1 a = 1;
b = 0;
#1 a = 1;
b = 1;
end
endmodule
| 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2;
and AND1 (temp1, ~p, q);
and AND2 (temp2, p, ~q);
assign s = temp1 | temp2;
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_03 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 1;
#1 a = 1;
b = 0;
#1 a = 1;
b = 1;
end
endmodule
| 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2;
and AND1 (temp1, ~p, q);
and AND2 (temp2, p, ~q);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xor XOR1 (s, a, b);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_04 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 1;
#1 a = 1;
b = 0;
#1 a = 1;
b = 1;
end
endmodule
| 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2, temp3;
not NOT1 (temp3, p);
not NOT2 (temp4, q);
and AND1 (temp1, temp3, q);
and AND2 (temp2, p, temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xor XOR1 (s, a, b);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_05 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 1;
#1 a = 1;
b = 0;
#1 a = 1;
b = 1;
end
endmodule
| 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
wire temp1, temp2, temp3, temp4;
not NOT1 (temp3, p);
not NOT2 (temp4, q);
and AND1 (temp1, temp3, q);
and AND2 (temp2, p, temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a[0],
a[1]
);
initial begin : start
a[0] = 0;
a[1] = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_06 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b", a[0], a[1], s);
#1 a[0] = 0;
a[1] = 1;
#1 a[0] = 1;
a[1] = 0;
#1 a[0] = 1;
a[1] = 1;
end
endmodule
| 6.716539 |
module xorgate (
s,
p
);
output s;
input [0:1] p;
wire temp1, temp2, temp3, temp4;
not NOT1 (temp3, p[0]);
not NOT2 (temp4, p[1]);
and AND1 (temp1, temp3, p[1]);
and AND2 (temp2, p[0], temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a
);
initial begin : start
a[0] = 0;
a[1] = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_07 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^%b = %b", a[0], a[1], s);
#1 a[0] = 0;
a[1] = 1;
#1 a[0] = 1;
a[1] = 0;
#1 a[0] = 1;
a[1] = 1;
end
endmodule
| 6.716539 |
module xorgate (
s,
p
);
output s;
input [0:1] p;
wire [0:3] temp;
not NOT1 (temp[2], p[0]);
not NOT2 (temp[3], p[1]);
and AND1 (temp[0], temp[2], p[1]);
and AND2 (temp[1], p[0], temp[3]);
or OR1 (s, temp[0], temp[1]);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a
);
initial begin : start
a[0] = 0;
a[1] = 0;
end
// parte principal
initial begin : main
$display("Exemplo 05_08 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^%b = %b", a[0], a[1], s);
#1 a[0] = 0;
a[1] = 1;
#1 a[0] = 1;
a[1] = 0;
#1 a[0] = 1;
a[1] = 1;
end
endmodule
| 6.716539 |
module xorgate (
s,
p
);
output s;
input [0:1] p;
wire temp1, temp2, temp3, temp4;
not NOT1 (temp3, p[0]);
not NOT2 (temp4, p[1]);
and AND1 (temp1, temp3, p[1]);
and AND2 (temp2, p[0], temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a
);
initial begin : start
a = 2'b00;
end
// parte principal
initial begin : main
$display("Exemplo 05_09 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b", a[0], a[1], s);
#1 a = 2'b01;
#1 a = 2'b10;
#1 a = 2'b11;
end
endmodule
| 6.716539 |
module xorgate (
s,
p
);
output s;
input [0:1] p;
wire temp1, temp2, temp3, temp4;
not NOT1 (temp3, p[0]);
not NOT2 (temp4, p[1]);
and AND1 (temp1, temp3, p[1]);
and AND2 (temp2, p[0], temp4);
or OR1 (s, temp1, temp2);
endmodule
| 7.421731 |
module testxorgate;
reg [0:1] a;
wire s;
// instancia
xorgate XOR1 (
s,
a
);
initial begin : start
a = 0; // decimal
end
// parte principal
initial begin : main
$display("Exemplo 05_10 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\na ^ b = s\n");
$monitor("%b ^ %b = %b", a[0], a[1], s);
#1 a = 1;
#1 a = 2;
#1 a = 3;
end
endmodule
| 6.716539 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 4'b0011; // 4 valores binarios
b = 4'b0101; // 4 valores binarios
end
// ------------------------- parte principal
initial begin : main
$display("Exemplo0005 - xxx yyy zzz - 999999");
$display("Test xor gate");
$display("\n a ^ b = s\n");
$monitor("%b ^ %b = %b", a, b, s);
#1 a = 0;
b = 0; // valores decimais
#1 a = 4'b0010;
b = 4'b0001; // valores binarios
#1 a = 4'd1;
b = 3; // decimal e decimal
#1 a = 4'o5;
b = 2; // octal e decimal
#1 a = 4'hA;
b = 3; // hexadecimal e decimal
#1 a = 4'h9;
b = 4'o3; // hexadecimal e octal
end
endmodule
| 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
assign s = ((~a & b) | (a & ~b));
endmodule
| 7.421731 |
module testxorgate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Guia-01 - Pedro Tronbin - 410473");
$display("Test XOR gate");
$display("\n( (~a&b) | (a&~b) ) = s\n");
a = 0;
b = 0;
#1 $display("(~%b&%b | %b&~%b) = %b", a, b, a, b, s);
a = 0;
b = 1;
#1 $display("(~%b&%b | %b&~%b) = %b", a, b, a, b, s);
a = 1;
b = 0;
#1 $display("(~%b&%b | %b&~%b) = %b", a, b, a, b, s);
a = 1;
b = 1;
#1 $display("(~%b&%b | %b&~%b) = %b", a, b, a, b, s);
end
endmodule
| 6.716539 |
module test_ly_2257_4 ();
reg clk_in; //输入
reg rst_n;
reg sel;
wire clk_out; //输出
parameter T = 20;
initial begin //初始化 系统复位
clk_in = 0;
rst_n = 0;
sel = 1;
#50 //等待50ns
rst_n = 1;
#400000 sel = 0;
end
always #(T / 2) clk_in = ~clk_in;
ly_2257_4 divider ( //例化
.clk_in (clk_in),
.sel (sel),
.rst_n (rst_n),
.clk_out(clk_out)
);
endmodule
| 7.423298 |
module top (
ena,
rst,
Tsync,
Tgdel,
Tgate,
Tlen,
Sync,
Gate,
Done,
prev_state,
prev_cnt,
prev_cnt_len
);
input ena, rst;
input [7:0] Tsync, Tgdel;
input [15:0] Tgate, Tlen, prev_cnt, prev_cnt_len;
input [4:0] prev_state;
output Sync, Gate, Done;
wire ena, rst;
wire [7:0] Tsync, Tgdel;
wire [15:0] Tgate, Tlen, prev_cnt, prev_cnt_len;
wire [4:0] prev_state;
wire Sync, Gate, Done;
wire n_130, n_142, n_164, n_167, n_290, n_413, n_414, n_415;
wire n_416, n_417, n_418, n_419, n_420, n_421, n_422, n_423;
wire n_424, n_425, n_426, n_427, n_428, n_429, n_430, n_431;
wire n_432, n_433, n_434, n_435, n_436, n_437, n_438, n_439;
wire n_440, n_441, n_442, n_443, n_444, n_445, n_446, n_447;
wire n_448, n_449, n_450, n_451, n_452, n_453, n_454, n_455;
wire n_456, n_457, n_458;
nor g63 (n_290, Done, n_458);
not g70 (Sync, n_290);
nor g91 (n_130, n_438, prev_cnt_len[5], prev_cnt_len[11], prev_state[1]);
nor g103 (n_142, n_440, prev_cnt_len[15], prev_cnt_len[9], prev_state[3]);
nor g105 (n_167, n_448, prev_cnt[10], prev_cnt[6], prev_cnt[15]);
nor g111 (n_164, n_453, prev_cnt[14], prev_cnt[3], prev_state[3]);
not g357 (n_413, prev_state[1]);
not g358 (n_414, prev_cnt_len[3]);
not g359 (n_415, prev_state[0]);
not g360 (n_416, prev_cnt_len[0]);
not g361 (n_417, prev_cnt_len[7]);
not g362 (n_418, prev_cnt_len[13]);
not g363 (n_419, prev_cnt_len[4]);
not g364 (n_420, prev_cnt_len[10]);
not g365 (n_421, prev_state[2]);
not g366 (n_422, prev_cnt_len[1]);
not g367 (n_423, prev_cnt_len[6]);
not g368 (n_424, prev_cnt_len[12]);
not g369 (n_425, prev_cnt[1]);
not g370 (n_426, prev_state[4]);
not g371 (n_427, rst);
not g372 (n_428, prev_cnt[4]);
not g373 (n_429, prev_cnt[8]);
not g374 (n_430, prev_cnt[12]);
not g375 (n_431, prev_cnt[5]);
not g376 (n_432, prev_cnt[9]);
not g377 (n_433, prev_cnt[13]);
not g378 (n_434, prev_cnt[7]);
not g379 (n_435, prev_cnt[11]);
not g380 (n_436, ena);
not g381 (n_437, prev_cnt[0]);
nand g382 (n_438, n_415, n_414);
not g383 (n_439, n_130);
nand g384 (n_440, n_418, n_417, n_416);
not g385 (n_441, n_142);
nand g386 (n_442, n_421, n_420, n_419);
nor g387 (n_443, n_442, rst, n_426, prev_cnt_len[2]);
not g388 (n_444, n_443);
nand g389 (n_445, n_424, n_423, n_422);
nor g390 (n_446, n_445, n_436, prev_cnt_len[14], prev_cnt_len[8]);
not g391 (n_447, n_446);
nor g392 (Done, n_439, n_441, n_444, n_447);
nand g393 (n_448, n_427, n_426, n_425);
not g394 (n_449, n_167);
nand g395 (n_450, n_430, n_429, n_428);
nor g396 (n_451, n_450, n_436, n_421, prev_cnt[2]);
not g397 (n_452, n_451);
nand g398 (n_453, n_433, n_432, n_431);
nand g399 (n_454, n_413, n_435, n_434);
not g400 (n_455, n_454);
nand g401 (n_456, n_164, n_455, n_415, n_437);
nor g402 (Gate, n_449, n_452, n_456);
nand g403 (n_457, ena, n_427, n_426, n_421);
nor g404 (n_458, n_457, prev_state[3], prev_state[1], n_415);
endmodule
| 6.617164 |
module place_holder (
input CLK,
input RST,
output out
);
wire out_wire;
always @(posedge CLK) begin
if (RST) begin
out <= 0;
end else begin
out <= out + 1 + out_wire;
end
end
place_holder_2 test_1 (
.CLK(CLK),
.RST(RST),
.out(out_wire)
);
endmodule
| 7.375365 |
module place_holder_2 (
input CLK,
input RST,
output out
);
always @(posedge CLK) begin
if (RST) begin
out <= 0;
end else begin
out <= out + 2;
end
end
endmodule
| 7.492135 |
module test_3bitAdder;
// Inputs
reg [2:0] A;
reg [2:0] B;
// Outputs
reg [2:0] sum;
wire cy;
// Instantiate the Unit Under Test (UUT)
Adder3bit uut (
.A (A),
.B (B),
.sum(sum),
.cy (cy)
);
initial begin
// Initialize Inputs
A = 3'b000;
B = 3'b000;
#100 A = 3'b010;
B = 3'b011;
#100 A = 3'b111;
B = 3'b100;
#100 A = 3'b111;
B = 3'b110;
#100;
$finish;
end
endmodule
| 7.588542 |
module top (
ena,
rst,
Tsync,
Tgdel,
Tgate,
Tlen,
Sync,
Gate,
Done,
prev_state,
prev_cnt,
prev_cnt_len
);
input ena, rst;
input [7:0] Tsync, Tgdel;
input [15:0] Tgate, Tlen, prev_cnt, prev_cnt_len;
input [4:0] prev_state;
output Sync, Gate, Done;
wire ena, rst;
wire [7:0] Tsync, Tgdel;
wire [15:0] Tgate, Tlen, prev_cnt, prev_cnt_len;
wire [4:0] prev_state;
wire Sync, Gate, Done;
wire n_130, n_142, n_164, n_167, n_290, n_413, n_414, n_415;
wire n_416, n_417, n_418, n_419, n_420, n_421, n_422, n_423;
wire n_424, n_425, n_426, n_427, n_428, n_429, n_430, n_431;
wire n_432, n_433, n_434, n_435, n_436, n_437, n_438, n_439;
wire n_440, n_441, n_442, n_443, n_444, n_445, n_446, n_447;
wire n_448, n_449, n_450, n_451, n_452, n_453, n_454, n_455;
wire n_456, n_457, n_458;
nor g63 (n_290, Done, n_458);
not g70 (Sync, n_290);
nor g91 (n_130, n_438, prev_cnt_len[5], prev_cnt_len[11], prev_state[1]);
nor g103 (n_142, n_440, prev_cnt_len[15], prev_cnt_len[9], prev_state[3]);
nor g105 (n_167, n_448, prev_cnt[10], prev_cnt[6], prev_cnt[15]);
nor g111 (n_164, n_453, prev_cnt[14], prev_cnt[3], prev_state[3]);
not g357 (n_413, prev_state[1]);
not g358 (n_414, prev_cnt_len[3]);
not g359 (n_415, prev_state[0]);
not g360 (n_416, prev_cnt_len[0]);
not g361 (n_417, prev_cnt_len[7]);
not g362 (n_418, prev_cnt_len[13]);
not g363 (n_419, prev_cnt_len[4]);
not g364 (n_420, prev_cnt_len[10]);
not g365 (n_421, prev_state[2]);
not g366 (n_422, prev_cnt_len[1]);
not g367 (n_423, prev_cnt_len[6]);
not g368 (n_424, prev_cnt_len[12]);
not g369 (n_425, prev_cnt[1]);
not g370 (n_426, prev_state[4]);
not g371 (n_427, rst);
not g372 (n_428, prev_cnt[4]);
not g373 (n_429, prev_cnt[8]);
not g374 (n_430, prev_cnt[12]);
not g375 (n_431, prev_cnt[5]);
not g376 (n_432, prev_cnt[9]);
not g377 (n_433, prev_cnt[13]);
not g378 (n_434, prev_cnt[7]);
not g379 (n_435, prev_cnt[11]);
not g380 (n_436, ena);
not g381 (n_437, prev_cnt[0]);
nand g382 (n_438, n_415, n_414);
not g383 (n_439, n_130);
nand g384 (n_440, n_418, n_417, n_416);
not g385 (n_441, n_142);
nand g386 (n_442, n_421, n_420, n_419);
nor g387 (n_443, n_442, rst, n_426, prev_cnt_len[2]);
not g388 (n_444, n_443);
nand g389 (n_445, n_424, n_423, n_422);
nor g390 (n_446, n_445, n_436, prev_cnt_len[14], prev_cnt_len[8]);
not g391 (n_447, n_446);
nor g392 (Done, n_439, n_441, n_444, n_447);
nand g393 (n_448, n_427, n_426, n_425);
not g394 (n_449, n_167);
nand g395 (n_450, n_430, n_429, n_428);
nor g396 (n_451, n_450, n_436, n_421, prev_cnt[2]);
not g397 (n_452, n_451);
nand g398 (n_453, n_433, n_432, n_431);
nand g399 (n_454, n_413, n_435, n_434);
not g400 (n_455, n_454);
nand g401 (n_456, n_164, n_455, n_415, n_437);
nor g402 (Gate, n_449, n_452, n_456);
nand g403 (n_457, ena, n_427, n_426, n_421);
nor g404 (n_458, n_457, prev_state[3], prev_state[1], n_415);
endmodule
| 6.617164 |
module segments_to_bitmap (
segments,
line,
bits
);
input [6:0] segments;
input [2:0] line;
output reg [4:0] bits;
always @(*)
case (line)
0:
bits = (segments[6]?5'b11111:0)
^ (segments[5]?5'b00001:0)
^ (segments[1]?5'b10000:0);
1: bits = (segments[1] ? 5'b10000 : 0) ^ (segments[5] ? 5'b00001 : 0);
2:
bits = (segments[0]?5'b11111:0)
^ (|segments[5:4]?5'b00001:0)
^ (|segments[2:1]?5'b10000:0);
3: bits = (segments[2] ? 5'b10000 : 0) ^ (segments[4] ? 5'b00001 : 0);
4:
bits = (segments[3]?5'b11111:0)
^ (segments[4]?5'b00001:0)
^ (segments[2]?5'b10000:0);
default: bits = 0;
endcase
endmodule
| 7.160964 |
module test_7segment_top (
clk,
reset,
hsync,
vsync,
rgb
);
input clk, reset;
output hsync, vsync;
output [2:0] rgb;
wire display_on;
wire [8:0] hpos;
wire [8:0] vpos;
video_sync_generator hvsync_gen (
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.display_on(display_on),
.hpos(hpos),
.vpos(vpos)
);
wire [3:0] digit = hpos[7:4];
wire [2:0] xofs = hpos[3:1];
wire [2:0] yofs = vpos[4:2];
wire [4:0] bits;
wire [6:0] segments;
seven_segment_decoder decoder (
.digit(digit),
.segments(segments)
);
segments_to_bitmap numbers (
.segments(segments),
.line(yofs),
.bits(bits)
);
wire r = display_on && 0;
wire g = display_on && bits[~xofs];
wire b = display_on && 0;
assign rgb = {b, g, r};
endmodule
| 7.2367 |
module: qadd
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test_add;
// Inputs
reg [31:0] a;
reg [31:0] b;
// Outputs
wire [31:0] c;
// Instantiate the Unit Under Test (UUT)
qadd #(19,32) uut (
.a(a),
.b(b),
.c(c)
);
// These are to monitor the values...
wire [30:0] c_out;
wire [30:0] a_in;
wire [30:0] b_in;
wire a_sign;
wire b_sign;
wire c_sign;
assign a_in = a[30:0];
assign b_in = b[30:0];
assign c_out = c[30:0];
assign a_sign = a[31];
assign b_sign = b[31];
assign c_sign = c[31];
initial begin
// Initialize Inputs
a[30:0] = 0;
a[31] = 0;
b[31] = 1;
b[30:0] = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 a = a+5179347; // why not?
a[31] = 0; // a is negative...
b[31] = 1;
if (a[30:0] > 2.1E9) // input will always be "positive"
begin
a = 0;
b[31] = 1; // b is negative...
b[30:0] = b[30:0] + 3779351;
end
end
end
endmodule
| 7.550078 |
module test_add16 ();
reg [15:0] a;
reg [15:0] b;
reg [15:0] ex_c;
wire [15:0] c;
add16 u1 (
c,
a,
b
);
initial begin
a = 16'b0000000000000000;
b = 16'b0000000000000000;
ex_c = 16'b0000000000000000;
#1 $display("add16 %d %b %b (%b %b)", $time, a, b, c, ex_c);
a = 16'b0000000000000001;
b = 16'b0000000000000001;
ex_c = 16'b0000000000000010;
#1 $display("add16 %d %b %b (%b %b)", $time, a, b, c, ex_c);
a = 16'b0000000000000011;
b = 16'b0000000000000001;
ex_c = 16'b0000000000000100;
#1 $display("add16 %d %b %b (%b %b)", $time, a, b, c, ex_c);
a = 16'b1111111111111111;
b = 16'b0000000000000001;
ex_c = 16'b0000000000000000;
#1 $display("add16 %d %b %b (%b %b)", $time, a, b, c, ex_c);
a = 16'b1111111111111110;
b = 16'b1111111111111110;
ex_c = 16'b1111111111111100;
#1 $display("add16 %d %b %b (%b %b)", $time, a, b, c, ex_c);
a = 16'b1010101010101010;
b = 16'b0101010101010101;
ex_c = 16'b1111111111111111;
#1 $display("add16 %d %b %b (%b %b)", $time, a, b, c, ex_c);
a = 16'b0011110011000011;
b = 16'b0000111111110000;
ex_c = 16'b0100110010110011;
#1 $display("add16 %d %b %b (%b %b)", $time, a, b, c, ex_c);
a = 16'b0001001000110100;
b = 16'b1001100001110110;
ex_c = 16'b1010101010101010;
end
endmodule
| 6.886557 |
module test_add1bit ();
parameter CLOCK_CYCLE = 100;
parameter COUNTER_BIT_NUM = 3;
parameter SIMULATION_PERIOD = 500;
// signal defenition
reg clk;
reg reset;
reg [COUNTER_BIT_NUM -1:0] counter;
wire A;
wire B;
wire C_i;
wire O;
wire C_o;
assign A = counter[0];
assign B = counter[1];
assign C_i = counter[2];
// dump wave file
initial begin
$dumpfile("tmp/dump.vcd");
$dumpvars(0, add1bit_1);
end
// monitor
initial begin
$monitor("[%t] A=%b, B=%d, C_i=%d => O=%b C_o=%b", $time, add1bit_1.A, add1bit_1.B,
add1bit_1.C_i, add1bit_1.O, add1bit_1.C_o);
end
// simulation end
initial begin
#(CLOCK_CYCLE * SIMULATION_PERIOD) $finish;
end
// clock
initial begin
#10 clk <= 1'b0;
forever begin
#(CLOCK_CYCLE / 2) clk <= ~clk;
end
end
// reset
initial begin
#10 reset <= 1'b0;
#300 reset <= 1'b1;
end
// counter
always @(posedge clk or negedge reset) begin
if (~reset) begin
counter <= {COUNTER_BIT_NUM{1'b0}};
end else begin
counter <= counter + {{COUNTER_BIT_NUM - 1{1'b0}}, 1'b1};
end
end
add1bit add1bit_1 (
.A (A),
.B (B),
.C_i(C_i),
.O (O),
.C_o(C_o)
);
endmodule
| 6.840184 |
module testbench_add32 ();
reg [31:0] A;
reg [31:0] B;
wire Overflow; //溢出判定
wire [31:0] result; //输出结果
reg isSub; //运算判定
reg isSign;
Add32 testadd32 (
Overflow,
result,
A,
B,
isSub,
isSign
);
initial begin
isSub = 1'b0;
isSign = 1'b1;
A = -100;
B = -100;
end
initial begin
repeat (100) #10 A = $random % 2147483648;
end
initial begin
repeat (100) #10 B = $random % 2147483648;
end
integer out_file;
initial begin
out_file = $fopen("signed_result.txt", "w");
end
always @(A or B) begin
$fwrite(out_file, "A:%d B:%d fact:%d cal:%d overflow:%d err:%d\n", $signed(A), $signed(B),
$signed(A) + $signed(B), $signed(result), Overflow, result - A - B);
end
endmodule
| 7.504399 |
module test_add8;
parameter WIRE = 8;
reg [7:0] a, b;
reg cin, sub;
wire [7:0] s;
wire cout;
add_sub #(
.WIRE(WIRE)
) test_addX (
a,
b,
cin,
sub,
s,
cout
);
initial begin
$dumpfile("signal_add8.vcd");
$dumpvars;
$display("\t\ttime,\ta,\tb, \tcin, \tsub,\ts,\tcout");
$monitor("%d \t%d \t%d \t%b \t%b \t%d \t%b", $time, a, b, cin, sub, s, cout);
a = 0;
b = 0;
cin = 0;
sub = 0;
#5;
a = 22;
b = 0;
cin = 0;
sub = 0;
#5;
a = 0;
b = 83;
cin = 0;
sub = 0;
#5;
a = 22;
b = 83;
cin = 0;
sub = 0;
#5;
a = 0;
b = 0;
cin = 0;
sub = 1;
#5;
a = 24;
b = 0;
cin = 0;
sub = 1;
#5;
a = 0;
b = 12;
cin = 0;
sub = 1;
#5;
a = 24;
b = 12;
cin = 0;
sub = 1;
#5;
a = 0;
b = 255;
cin = 0;
sub = 1;
end
endmodule
| 7.211015 |
module TOP;
//ALU inputs
reg [15:0] a, b;
reg carry_in;
wire [15:0] sum;
wire [15:0] carry_out;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 16'hfffe;
b = 16'h0001;
#`cycle //1
if(sum != (a + b))
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 16'h1723;
b = 16'h8323;
#`cycle //3
if(sum != (a + b))
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 16'hbcda;
b = 16'h7986;
#`cycle //5
if(sum != (a + b))
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 16'h9657;
b = 16'h3456;
#`cycle //7
if(sum != (a + b))
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! %3.2F ns cycle time ***\n", `cycle);
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("adder.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(*)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, recieved sum = %x, correct sum = %x",
$time, a, b, sum, (a + b));
else
$strobe ("correct: time: %0d: a = %x, b = %x, sum = %x",
$time, a, b, sum);
adder16 u_adder16(sum, carry_out, a, b);
endmodule
| 7.259416 |
module: mux_16to1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_adder2bits();
// Inputs
reg [2:0] A, B; //
// Outputs
wire Co;
wire [1:0] S;
// Instantiate the Unit Under Test (UUT)
adder_2bit uut (
.A(A[1:0]),
.B(B[1:0]),
.Co(Co),
.S(S)
);
integer error = 0;
initial begin
// Wait 100 ns for global reset to finish
#100;
for (B = 3'b0; B!=3'd4; B= B + 1) begin
for (A = 3'd0; A!= 3'd4; A = A + 1 ) begin
#10; // wait for inputs to propagate
if (A + B != S) begin
if (Co != 1) begin
error = error + 1;
$display("Error: %b + %b is %b with carryover %b", A,B,S,Co);
end
end
end
end
end
endmodule
| 7.639724 |
module test_adder_32bit;
reg [31:0] in_1;
reg [31:0] in_2;
wire [31:0] out_put;
wire carry_out;
adder_32bit adder (
in_1,
in_2,
out_put,
carry_out
);
initial begin
$monitor("in1 :%b | in2 :%b | out :%b | cout :%b", in_1, in_2, out_put, carry_out);
end
initial begin
in_1 = 32'b00000000000000000000000000000001;
in_2 = 32'b00000000000000000000000000000001;
#3 in_1 = 32'b00000000000000000000000000000001;
in_2 = 32'b00000000000000000000000000000010;
end
endmodule
| 6.692392 |
module: mux_16to1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_adder_cascaded32();
// Inputs
reg [31:0] A, B;
// Outputs
wire Ov;
wire [31:0] S;
// Instantiate the Unit Under Test (UUT)
adder_cascaded32 uut (
.A(A[31:0]),
.B(B[31:0]),
.S(S),
.Ov(Ov)
);
integer error = 0;
initial begin
// Wait 100 ns for global reset to finish
#100;
// Tests Overflow with 1's in MSB
A[31:0] = 0;
B[31:0] = 0;
B[31] = 1;
A[31] = 1;
#10;
$display("%b + %b is %b with carryover %b", A[31:0],B[31:0],S,Ov);
// Iterates over a choice of high numbers.
for (B = 32'd1; B!=32'd10; B= B + 1) begin
for (A = 32'd1; A!= 32'd10; A = A + 1 ) begin
#100; // wait for inputs to propagate
if (A[31:0] + B[31:0] != S) begin
if (Ov != 1) begin
error = error + 1;
$display("Error: %d + %d is %d with carryover %d", A[31:0],B[31:0],S,Ov);
end
end
end
end
$display("Completed.");
end
endmodule
| 7.639724 |
module Test_Addr_MUX;
// Inputs
reg CLK;
reg RST;
reg [15:0] HADDR_1;
reg [15:0] HADDR_2;
reg [1:0] SEL;
// Outputs
wire [15:0] HADDR;
// Instantiate the Unit Under Test (UUT)
Addr_MUX uut (
.CLK(CLK),
.RST(RST),
.HADDR(HADDR),
.HADDR_1(HADDR_1),
.HADDR_2(HADDR_2),
.SEL(SEL)
);
always #15 CLK = !CLK;
initial begin
#500 RST = 1; // Random reset stimuli
#50 RST = 0;
end
initial begin
// Initialize Inputs
CLK = 0;
RST = 0;
HADDR_1 = 0;
HADDR_2 = 0;
SEL = 0;
// Wait 100 ns for global reset to finish
#15;
// Add stimulus here
#200 HADDR_1[15:0] = $random;
HADDR_2[15:0] = $random;
SEL = 2'b00;
RST = 0; // no master selected
#200 HADDR_1[15:0] = $random;
HADDR_2[15:0] = $random;
SEL = 2'b01;
RST = 0; // master 1
#200 HADDR_1[15:0] = $random;
HADDR_2[15:0] = $random;
SEL = 2'b10;
RST = 0; // master 2
#200 HADDR_1[15:0] = $random;
HADDR_2[15:0] = $random;
SEL = 2'b01;
RST = 0; // master 1
#200 HADDR_1[15:0] = $random;
HADDR_2[15:0] = $random;
SEL = 2'b11;
RST = 0; // no master selected
end
endmodule
| 6.878543 |
module test_addX;
parameter WIRE = 8;
reg [WIRE-1:0] a, b;
reg cin;
wire [WIRE-1:0] out;
wire cout;
addX #(
.WIRE(WIRE)
) addX_inst (
a,
b,
cin,
out,
cout
);
initial begin
$dumpfile("signal_addX.vcd");
$dumpvars;
$display("\t\ttime,\ta,\tb, \tcin, \tout,\tcout");
$monitor("%d \t%d \t%d \t%b \t%d \t%b", $time, a, b, cin, out, cout);
a <= 0;
b <= 0;
cin <= 0;
#100;
a <= 24;
b <= 0;
cin <= 0;
#100;
a <= 0;
b <= 54;
cin <= 0;
#100;
a <= 23;
b <= 54;
cin <= 0;
#100;
a <= 23;
b <= 54;
cin <= 1;
#100;
end
endmodule
| 6.945899 |
module test_add_4;
reg [3:0] a0; // add oprand
reg [3:0] a1;
reg carry_in;
wire [3:0] sum; // the sum of a0 and a1
wire carry_out;
add_4 instance_add_4 (
.in_0(a0),
.in_1(a1),
.cin (carry_in),
.out (sum),
.cout(carry_out)
);
initial begin
a0 = 4'b0000;
a1 = 4'b0000;
carry_in = 1'b0;
end
always begin
#1;
a0 = $random() % 16;
a1 = $random() % 16;
carry_in = $random() % 2;
end
endmodule
| 6.655923 |
module test_add_mul16 (
input [15:0] a,
input [15:0] b,
input [15:0] c,
output [15:0] out
);
assign out = (a + b) * c;
endmodule
| 6.581066 |
module test_aes_16;
// Inputs
reg clk;
reg [15:0] state;
reg [15:0] key;
// Outputs
wire [15:0] out;
// Instantiate the Unit Under Test (UUT)
aes_16 uut (
.clk (clk),
.state(state),
.key (key),
.out (out)
);
initial begin
$dumpfile("aes_16.vcd"); // name of the dump file
$dumpvars(
0,
test_aes_16); // "0" specifies to dump all the variables in code and "Inverter_tb" is the name of module
clk = 0;
state = 0;
key = 0;
#100;
/*
* TIMEGRP "key" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
* TIMEGRP "state" OFFSET = IN 6.4 ns VALID 6 ns AFTER "clk" HIGH;
* TIMEGRP "out" OFFSET = OUT 2.2 ns BEFORE "clk" HIGH;
*/
@(negedge clk);
#2.5;
state = 16'h0734;
key = 16'h4f3c;
#100;
state = 16'hccdd;
key = 16'h0c0d;
#100;
state = 16'h0;
key = 16'h0;
#100;
state = 16'h0;
key = 16'h1;
#100;
state = 16'h1;
key = 16'h0;
$finish;
end
always #10 clk = ~clk;
endmodule
| 6.596262 |
module test_ahb_lite_mem;
`include "sdr_parameters.vh"
`include "ahb_lite.vh"
ahb_lite_mem mem (
.HCLK (HCLK),
.HRESETn(HRESETn),
.HADDR (HADDR),
.HBURST (HBURST),
.HSEL (HSEL),
.HSIZE (HSIZE),
.HTRANS (HTRANS),
.HWDATA (HWDATA),
.HWRITE (HWRITE),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP)
);
always #(tCK / 2) HCLK = ~HCLK;
initial begin
begin
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
ahbPhaseFst(0, READ, HSIZE_X32, St_x);
ahbPhase(4, WRITE, HSIZE_X32, St_x);
ahbPhase(8, WRITE, HSIZE_X32, 32'h76543210);
ahbPhase(4, READ, HSIZE_X32, 32'hFEDCAB98);
ahbPhase(8, READ, HSIZE_X32, St_x);
ahbPhaseLst(8, READ, HSIZE_X32, St_x);
@(posedge HCLK);
@(posedge HCLK);
end
$stop;
$finish;
end
endmodule
| 6.737862 |
module test_ahb_lite_sdram;
`include "sdr_parameters.vh"
`include "ahb_lite.vh"
wire CKE;
wire CSn;
wire RASn;
wire CASn;
wire WEn;
wire [ADDR_BITS - 1 : 0] ADDR;
wire [ BA_BITS - 1 : 0] BA;
wire [ DQ_BITS - 1 : 0] DQ;
wire [ DM_BITS - 1 : 0] DQM;
ahb_lite_sdram #(
.DELAY_tREF (4000),
.DELAY_tRP (1),
.DELAY_tRFC (7),
.DELAY_tRCD (2),
.DELAY_tCAS (1),
.DELAY_afterREAD (3),
.DELAY_afterWRITE(5)
) mem (
.HCLK (HCLK),
.HRESETn(HRESETn),
.HADDR (HADDR),
.HBURST (HBURST),
.HSEL (HSEL),
.HSIZE (HSIZE),
.HTRANS (HTRANS),
.HWDATA (HWDATA),
.HWRITE (HWRITE),
.HRDATA (HRDATA),
.HREADY (HREADY),
.HRESP (HRESP),
.CKE (CKE),
.CSn (CSn),
.RASn(RASn),
.CASn(CASn),
.WEn (WEn),
.ADDR(ADDR),
.BA (BA),
.DQ (DQ),
.DQM (DQM)
);
//memory clock
reg MCLK;
initial begin
MCLK = 1;
#2 //phase shift from main clock
forever
MCLK = #(tCK / 2) ~MCLK;
end
sdr sdram0 (
DQ,
ADDR,
BA,
MCLK,
CKE,
CSn,
RASn,
CASn,
WEn,
DQM
);
//main clock
always #(tCK / 2) HCLK = ~HCLK;
initial begin
begin
HCLK = 0;
HRESETn = 0;
@(posedge HCLK);
@(posedge HCLK);
HRESETn = 1;
@(posedge HCLK);
ahbPhaseFst(0, READ, HSIZE_X32, St_x);
ahbPhase(4, WRITE, HSIZE_X32, St_x);
ahbPhase(8, WRITE, HSIZE_X32, 32'h76543210);
ahbPhase(4, READ, HSIZE_X32, 32'hFEDCAB98);
ahbPhase(8, READ, HSIZE_X32, St_x);
ahbPhase(4, WRITE, HSIZE_X16, St_x);
ahbPhase(6, WRITE, HSIZE_X16, 32'h7654AAAA);
ahbPhase(4, READ, HSIZE_X32, 32'hBBBB3210);
ahbPhase(4, WRITE, HSIZE_X8, St_x);
ahbPhase(6, WRITE, HSIZE_X8, 32'h111111CC);
ahbPhase(9, WRITE, HSIZE_X8, 32'h22DD2222);
ahbPhase(11, WRITE, HSIZE_X8, 32'h3333EE33);
ahbPhase(4, READ, HSIZE_X32, 32'hFF444444);
ahbPhase(8, READ, HSIZE_X32, St_x);
ahbPhaseLst(8, READ, HSIZE_X32, St_x);
@(posedge HCLK);
@(posedge HCLK);
end
#70000 //waiting for auto_refresh
$stop;
$finish;
end
endmodule
| 6.737862 |
module Test_DADDA_8bit_All_Input;
//Parameters
parameter in_size = 15;
parameter [in_size:0] zero = 0;
// Inputs
reg [7:0] A;
reg [7:0] B;
reg [6:0] M;
//reg app;
reg clk = 0;
reg [in_size:0] MUL_exact;
reg [in_size:0] MUL_apprx;
integer RepFile;
real error = 0;
real error_distance = 0;
real error_distance_abs = 0;
real sum_ED = 0;
real sum_ED_abs = 0;
real RE = 0;
real sum_RE = 0;
real NE = 0;
real sum_NE = 0;
integer temp = 0;
integer tot_temp = 0;
real ER = 0;
real MRED = 0;
real MED = 0;
real MNED = 0;
real MAE = 0;
real AE = 0;
real max = 0;
real totalSamples = 10000;
real i = 0, j = 0, k = 0;
// Outputs
wire [15:0] O, OAc;
reg [15:0] apprx, exact;
// Instantiate the Unit Under Test (UUT)
ERCM8_V2_7 uut1 (
.dat_in_a(A),
.dat_in_b(B),
.mask(M),
.dat_o(O)
);
/* Dadda_Module1 uut2 (
.A(A),
.B(B),
.P(OAc)
); */
always begin
#5 clk = ~clk;
end
initial begin
$sdf_annotate("SynERCM8_V2_7.sdf", uut1,,, "TYPICAL");
end
initial begin
RepFile = $fopen("Test_Dadda_8.rep", "w");
$vcdpluson;
// Initialize Inputs
A = 0;
B = 0; //app=0;
M = 7'b0000000;
// Wait 100 ns for global reset to finish
#430;
//for (i=0; i<2; i=i+1) begin
//#10
//A=0;
//app =~ app;
for (j = 0; j < totalSamples; j = j + 1) begin
#10 A = $random;
B = $random;
#430 apprx = O;
exact = A * B;
if (~(exact == apprx)) begin
error = error + 1;
error_distance = exact - apprx;
end
ER = error / totalSamples;
if (exact > apprx) begin
error_distance_abs = exact - apprx;
end else error_distance_abs = apprx - exact;
if (error_distance_abs > max) begin
max = error_distance_abs;
end
sum_ED = sum_ED + error_distance;
sum_ED_abs = sum_ED_abs + error_distance_abs;
MED = sum_ED_abs / totalSamples;
MNED = sum_ED_abs / (65025 * totalSamples);
///////////////////////////////////////
if (~(exact == 0)) begin
RE = error_distance_abs / exact;
sum_RE = sum_RE + RE;
MRED = sum_RE / totalSamples;
end
$fdisplay(RepFile,
"A=%d B=%d exact=%d apprx=%b #error=%f MED=%f MRED=%0.8f MNED=%f ER=%f max = %d",
A, B, exact, apprx, error, MED, MRED, MNED, ER, max);
end
$fclose(RepFile);
$finish;
end
endmodule
| 7.889401 |
module test_alucontrol;
// Inputs
reg [5:0] instruction_function;
reg [1:0] ALUOp;
// Outputs
wire [3:0] alu_control;
// Instantiate the Unit Under Test (UUT)
ALUControl_32 uut (
.instruction_function(instruction_function),
.ALUOp(ALUOp),
.alu_control(alu_control)
);
initial begin
// Initialize Inputs
instruction_function = 0;
ALUOp = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.6455 |
module: alu_control
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_alu_control;
// Inputs
reg [3:0] AluOp1;
reg [1:0] Flag1;
// Outputs
wire [2:0] AluCtrl1;
// Instantiate the Unit Under Test (UUT)
alu_control uut (
.AluOp1(AluOp1),
.Flag1(Flag1),
.AluCtrl1(AluCtrl1)
);
initial begin
// Initialize Inputs
AluOp1 = 0;
Flag1 = 0;
// Wait 100 ns for global reset to finish
#100;
// AluOp1 = 4'b0000;
// Flag1 = 2'b00;
// Add stimulus here
// forever #40 AluOp1 = AluOp1 + 1;
// forever #10 Flag1 = Flag1 + 1;
end
endmodule
| 6.672598 |
module test_ALU_reg (
data_in,
mux_sel,
seg_reg,
adr_reg_a,
adr_reg_b,
op_in,
we,
clk,
a_reset_l,
valid_o,
data_o
);
parameter seg_reg_wl = 4; // segment register width
parameter adr_reg_wl = 4; // address register width
parameter op_wl = 8;
input [15:0] data_in;
input [1:0] mux_sel;
input [seg_reg_wl-1:0] seg_reg; // segment register
input [adr_reg_wl-1:0] adr_reg_a; // address register A
input [adr_reg_wl-1:0] adr_reg_b; // address register B
input [op_wl -1:0] op_in;
input we;
input clk;
input a_reset_l;
output valid_o;
output [15:0] data_o;
wire [15:0]a_bus;
wire [15:0]b_bus;
wire z_from_reg;
wire s_from_reg;
wire c_from_reg;
wire ovr_from_reg;
wire [15:0]c_bus;
wire z_to_reg;
wire s_to_reg;
wire c_to_reg;
wire ovr_to_reg;
wire valid_bus;
wire ce;
wire [15:0]ir_bus;
wire [15:0]reg_bus;
wire [6:0]a_adr_bus;
wire [6:0]b_adr_bus;
reg [3:0]adr_reg_a_int;
always @(*) begin
adr_reg_a_int = adr_reg_a;
adr_reg_a_int[0] = adr_reg_a[0] | valid_bus;
end
zmc_alu zmc_alu_i (
.a_in(a_bus),
.b_in(b_bus),
.op_in(op_in),
.z_flag_in(z_from_reg),
.s_flag_in(s_from_reg),
.c_flag_in(c_from_reg),
.ovr_flag_in(ovr_from_reg),
.clk(clk),
.a_reset_l(a_reset_l),
.c_out(c_bus),
.z_flag_out(z_to_reg),
.s_flag_out(s_to_reg),
.c_flag_out(c_to_reg),
.ovr_flag_out(ovr_to_reg),
.valid_out(valid_bus)
);
flag_reg flag_reg_i (
.clk(clk),
.a_reset_l(a_reset_l),
.ce(1'b1),
.z_flag_in(z_to_reg),
.s_flag_in(s_to_reg),
.c_flag_in(c_to_reg),
.ovr_flag_in(ovr_to_reg),
.z_flag_out(z_from_reg),
.s_flag_out(s_from_reg),
.c_flag_out(c_from_reg),
.ovr_flag_out(ovr_from_reg)
);
data_mux3_1 data_mux3_1 (
.in_1(ir_bus),
.in_2(c_bus),
.in_3(data_in),
.sel (mux_sel),
.out (reg_bus)
);
reg_file reg_file_i (
.clk(clk),
.a_reset_l(a_reset_l),
.a_adr_in(a_adr_bus),
.b_adr_in(b_adr_bus),
.reg_a_in(reg_bus),
.we(we),
.reg_a_out(a_bus),
.reg_b_out(b_bus)
);
zmc_adr_gen zmc_adr_gen_i (
.seg_reg(seg_reg),
.adr_reg_a(adr_reg_a_int),
.adr_reg_b(adr_reg_b),
.a_adr(a_adr_bus),
.b_adr(b_adr_bus)
);
assign valid_o = valid_bus;
assign data_o = c_bus;
endmodule
| 6.776816 |
module test_amoa_8x8p1_rt8_apx2;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
amoa_8x8p1_rt8_apx2 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.x5(x5),
.x6(x6),
.x7(x7),
.summ(summ)
);
// clock
always #5 clk = ~clk;
// reset
initial begin
clk = 0;
rst_n = 0;
#8;
rst_n = 1;
#2000;
$finish();
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.dump");
$dumpvars(0, test_amoa_8x8p1_rt8_apx2);
end
`endif
// stimulus
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
counter <= 8'd0;
x0 <= 8'd0;
x1 <= 8'd0;
x2 <= 8'd0;
x3 <= 8'd0;
x4 <= 8'd0;
x5 <= 8'd0;
x6 <= 8'd0;
x7 <= 8'd0;
end else begin
counter <= counter + 1'b1;
x0 <= counter + 1;
x1 <= counter + 2;
x2 <= counter + 3;
x3 <= counter + 4;
x4 <= counter + 4;
x5 <= counter + 3;
x6 <= counter + 2;
x7 <= counter + 1;
end
end
// check
always @(posedge clk) begin
if (rst_n == 1'b1) begin
$display("counter:%d summ:%d x0:%d\n", counter, summ, x0);
//if (summ != (counter-1)*8) begin
//$display("ERROR: summ %d != (counter-1)*8 %d:%d, arrival at %t",summ,(counter-1)*8,counter,$time);
//end
end
end
endmodule
| 7.831084 |
module test_amoa_8x8p2_rt8_apx2;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
amoa_8x8p2_rt8_apx2 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.x5(x5),
.x6(x6),
.x7(x7),
.summ(summ),
.stall(stall)
);
// clock
always #5 clk = ~clk;
// reset
initial begin
clk = 0;
rst_n = 0;
#8;
rst_n = 1;
#2000;
$finish();
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.dump");
$dumpvars(0, test_amoa_8x8p2_rt8_apx2);
end
`endif
// stimulus
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
counter <= 8'd0;
x0 <= 8'd0;
x1 <= 8'd0;
x2 <= 8'd0;
x3 <= 8'd0;
x4 <= 8'd0;
x5 <= 8'd0;
x6 <= 8'd0;
x7 <= 8'd0;
end else begin
counter <= counter + 1'b1;
x0 <= counter + 1;
x1 <= counter + 2;
x2 <= counter + 3;
x3 <= counter + 4;
x4 <= counter + 4;
x5 <= counter + 3;
x6 <= counter + 2;
x7 <= counter + 1;
end
end
// check
always @(posedge clk) begin
if (rst_n == 1'b1) begin
$display("counter:%d summ:%d x0:%d\n", counter, summ, x0);
//if (summ != (counter-1)*8) begin
//$display("ERROR: summ %d != (counter-1)*8 %d:%d, arrival at %t",summ,(counter-1)*8,counter,$time);
//end
end
end
endmodule
| 7.831084 |
module test_amoa_8x8p2_rt8_apxe4;
reg clk;
reg rst_n;
reg [7:0] x0;
reg [7:0] x1;
reg [7:0] x2;
reg [7:0] x3;
reg [7:0] x4;
reg [7:0] x5;
reg [7:0] x6;
reg [7:0] x7;
reg [7:0] counter;
wire [10:0] summ;
amoa_8x8p2_rt8_apxe4 U0 (
.clk(clk),
.rst_n(rst_n),
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.x4(x4),
.x5(x5),
.x6(x6),
.x7(x7),
.summ(summ),
.stall(stall)
);
// clock
always #5 clk = ~clk;
// reset
initial begin
clk = 0;
rst_n = 0;
#8;
rst_n = 1;
#2000;
$finish();
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.dump");
$dumpvars(0, test_amoa_8x8p2_rt8_apxe4);
end
`endif
// stimulus
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1'b0) begin
counter <= 8'd0;
x0 <= 8'd0;
x1 <= 8'd0;
x2 <= 8'd0;
x3 <= 8'd0;
x4 <= 8'd0;
x5 <= 8'd0;
x6 <= 8'd0;
x7 <= 8'd0;
end else begin
counter <= counter + 1'b1;
x0 <= counter + 1;
x1 <= counter + 2;
x2 <= counter + 3;
x3 <= counter + 4;
x4 <= counter + 4;
x5 <= counter + 3;
x6 <= counter + 2;
x7 <= counter + 1;
end
end
// check
always @(posedge clk) begin
if (rst_n == 1'b1) begin
$display("counter:%d summ:%d x0:%d\n", counter, summ, x0);
//if (summ != (counter-1)*8) begin
//$display("ERROR: summ %d != (counter-1)*8 %d:%d, arrival at %t",summ,(counter-1)*8,counter,$time);
//end
end
end
endmodule
| 7.831084 |
module test_mux_2x1;
reg [31:0] I0; //Las entradas del módulo deben ser tipo reg
wire [4:0] Y; //Las salidas deben ser tipo wire
reg S;
parameter sim_time = 100;
amount_selector sel (
Y,
S,
I0
); // Instanciación del módulo
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
I0 = 32'hFFFFFFFF;
S = 1'b0;
repeat (1) #10 S = S + 1'b1; //cada 10 unidades de tiempo
end
initial begin
$display(" S I I1 I0 Y"); //imprime header
$monitor(" %b %b %b", S, I0, Y); //imprime las señales
end
endmodule
| 6.929887 |
module test_and (
input A,
input B,
output C
);
assign C = A & B;
endmodule
| 7.005269 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire in1_buf;
wire in2_buf;
sky130_fd_sc_hd__and2_1 icg (
.A(in1_buf),
.B(in2_buf),
.X(out)
);
sky130_fd_sc_hd__buf_1 gin1 (
.A(in1),
.X(in1_buf)
);
sky130_fd_sc_hd__buf_1 gin2 (
.A(in2),
.X(in2_buf)
);
endmodule
| 6.705495 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire in1_buf, in1_not;
wire in2_buf, in2_not;
wire out_not;
sky130_fd_sc_hd__inv_1 inv1 (
.A(in1),
.Y(in1_not)
);
sky130_fd_sc_hd__inv_1 inv2 (
.A(in2),
.Y(in2_not)
);
sky130_fd_sc_hd__buf_1 gin1 (
.A(in1_not),
.X(in1_buf)
);
sky130_fd_sc_hd__buf_1 gin2 (
.A(in2_not),
.X(in2_buf)
);
sky130_fd_sc_hd__and2_1 icg (
.A(in1_buf),
.B(in2_buf),
.X(out_not)
);
sky130_fd_sc_hd__inv_1 invOut (
.A(out_not),
.Y(out)
);
endmodule
| 6.705495 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire x, y;
wire z0, z1;
wire z;
wire in1_buf;
wire in2_buf;
sky130_fd_sc_hd__inv_1 inv1 (
.A(in1),
.Y(in1_buf)
);
sky130_fd_sc_hd__inv_1 inv2 (
.A(in2),
.Y(in2_buf)
);
sky130_fd_sc_hd__buf_1 gin1 (
.A(in1_buf),
.X(x)
);
sky130_fd_sc_hd__buf_1 gin2 (
.A(in2_buf),
.X(y)
);
sky130_fd_sc_hd__and2_1 and_gate (
.A(x),
.B(y),
.X(z0)
);
sky130_fd_sc_hd__or2_1 or_gate (
.A(x),
.B(y),
.X(z1)
);
sky130_fd_sc_hd__and2_1 and_gate2 (
.A(z0),
.B(z1),
.X(z)
);
sky130_fd_sc_hd__inv_1 invOut (
.A(z),
.Y(out)
);
endmodule
| 6.705495 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire x, y;
wire z0, z1, z2, z3, z4, z5, z6, z7, z8, z9, z10;
wire out1, out2, out3, out4, out5;
wire in1_buf;
wire in2_buf;
// Compute x = NOT(inp1)
sky130_fd_sc_hd__inv_1 inv1 (
.A(in1),
.Y(in1_buf)
);
// Compute y = NOT(inp2)
sky130_fd_sc_hd__inv_1 inv2 (
.A(in2),
.Y(in2_buf)
);
sky130_fd_sc_hd__buf_1 gin1 (
.A(in1_buf),
.X(x)
);
sky130_fd_sc_hd__buf_1 gin2 (
.A(in2_buf),
.X(y)
);
// z0 = AND(x,y)
sky130_fd_sc_hd__and2_1 and1 (
.A(x),
.B(y),
.X(z0)
);
// z1 = OR(x,y)
sky130_fd_sc_hd__or2_1 or1 (
.A(x),
.B(y),
.X(z1)
);
// z2 = AND(z0,z1)
sky130_fd_sc_hd__and2_1 and2 (
.A(z0),
.B(z1),
.X(z2)
);
// out1 = NOT(z2)
sky130_fd_sc_hd__inv_1 inv3 (
.A(z2),
.Y(out1)
);
// z3 = AND(out1, x)
sky130_fd_sc_hd__and2_1 and3 (
.A(out1),
.B(x),
.X(z3)
);
// z4 = OR(z2,y)
sky130_fd_sc_hd__or2_1 or2 (
.A(z2),
.B(y),
.X(z4)
);
// out2 = NOT(z3)
sky130_fd_sc_hd__inv_1 inv4 (
.A(z3),
.Y(out2)
);
// z5 = XOR(out1, out2)
sky130_fd_sc_hd__xor2_1 xor1 (
.A(out1),
.B(out2),
.X(z5)
);
// z6 = AND(z4, z3)
sky130_fd_sc_hd__and2_1 and4 (
.A(z4),
.B(z3),
.X(z6)
);
// out3 = NOT(z5)
sky130_fd_sc_hd__inv_1 inv5 (
.A(z5),
.Y(out3)
);
// z7 = OR(out3, z2)
sky130_fd_sc_hd__or2_1 or3 (
.A(out3),
.B(z2),
.X(z7)
);
// z8 = XOR(z6, z5)
sky130_fd_sc_hd__xor2_1 xor2 (
.A(z6),
.B(z5),
.X(z8)
);
// out4 = NOT(z7)
sky130_fd_sc_hd__inv_1 inv6 (
.A(z7),
.Y(out4)
);
// z9 = AND(out4, z4)
sky130_fd_sc_hd__and2_1 and5 (
.A(out4),
.B(z4),
.X(z9)
);
// z10 = OR(z8, z7)
sky130_fd_sc_hd__or2_1 or4 (
.A(z8),
.B(z7),
.X(z10)
);
// out5 = XOR(z9, z10)
sky130_fd_sc_hd__xor2_1 xor3 (
.A(z9),
.B(z10),
.X(out5)
);
// Final output
sky130_fd_sc_hd__inv_1 invOut (
.A(out5),
.Y(out)
);
endmodule
| 6.705495 |
module test_and2 (
clk,
in1,
in2,
out
);
input clk; // Not used but for easier verilator common flow
input in1;
input in2;
output out;
wire x, y;
wire z0, z1, z2, z3, z4, z5, z6, z7, z8, z9, z10;
wire out1, out2, out3, out4, out5;
wire in1_buf;
wire in2_buf;
// Compute x = NOT(inp1)
sky130_fd_sc_hd__inv_1 inv1 (
.A(in1),
.Y(in1_buf)
);
// Compute y = NOT(inp2)
sky130_fd_sc_hd__inv_1 inv2 (
.A(in2),
.Y(in2_buf)
);
sky130_fd_sc_hd__buf_1 gin1 (
.A(in1_buf),
.X(x)
);
sky130_fd_sc_hd__buf_1 gin2 (
.A(in2_buf),
.X(y)
);
// z0 = AND(x,y)
sky130_fd_sc_hd__and2_1 and1 (
.A(x),
.B(y),
.X(z0)
);
// z1 = OR(x,y)
sky130_fd_sc_hd__or2_1 or1 (
.A(x),
.B(y),
.X(z1)
);
// z2 = AND(z0,z1,x)
sky130_fd_sc_hd__and3_1 and2 (
.A(z0),
.B(z1),
.C(x),
.X(z2)
);
// out1 = NOT(z2)
sky130_fd_sc_hd__inv_1 inv3 (
.A(z2),
.Y(out1)
);
// z3 = AND(out1, x)
sky130_fd_sc_hd__and2_1 and3 (
.A(out1),
.B(x),
.X(z3)
);
// z4 = OR(z2,y,z3)
sky130_fd_sc_hd__or3_1 or2 (
.A(z2),
.B(y),
.C(z3),
.X(z4)
);
// out2 = NOT(z3)
sky130_fd_sc_hd__inv_1 inv4 (
.A(z3),
.Y(out2)
);
// z5 = XOR(out1, out2)
sky130_fd_sc_hd__xor2_1 xor1 (
.A(out1),
.B(out2),
.X(z5)
);
// z6 = AND(z4, z3, z5)
sky130_fd_sc_hd__and3_1 and4 (
.A(z4),
.B(z3),
.C(z5),
.X(z6)
);
// out3 = NOT(z5)
sky130_fd_sc_hd__inv_1 inv5 (
.A(z5),
.Y(out3)
);
// z7 = OR(out3, z2)
sky130_fd_sc_hd__or2_1 or3 (
.A(out3),
.B(z2),
.X(z7)
);
// z8 = XOR(z6, z5, z7)
sky130_fd_sc_hd__xor3_1 xor2 (
.A(z6),
.B(z5),
.C(z7),
.X(z8)
);
// out4 = NOT(z7)
sky130_fd_sc_hd__inv_1 inv6 (
.A(z7),
.Y(out4)
);
// z9 = AND(out4, z4)
sky130_fd_sc_hd__and2_1 and5 (
.A(out4),
.B(z4),
.X(z9)
);
// z10 = OR(z8, z7, z9)
sky130_fd_sc_hd__or3_1 or4 (
.A(z8),
.B(z7),
.C(z9),
.X(z10)
);
// out5 = XOR(z9, z10)
sky130_fd_sc_hd__xor2_1 xor3 (
.A(z9),
.B(z10),
.X(out5)
);
// Final output
sky130_fd_sc_hd__inv_1 invOut (
.A(out5),
.Y(out)
);
endmodule
| 6.705495 |
module: approx_mul
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_approx;
// Inputs
reg clk;
reg reset;
reg [15:0] in_a;
reg [15:0] in_b;
// Outputs
wire [4:0] shift_a;
wire [4:0] shift_b;
wire [15:0] out_A;
wire [15:0] out_B;
// Instantiate the Unit Under Test (UUT)
approx_mul uut (
.clk(clk),
.reset(reset),
.in_a(in_a),
.in_b(in_b),
.shift_a(shift_a),
.shift_b(shift_b),
.out_A(out_A),
.out_B(out_B)
);
always #5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
in_a = 0;
in_b = 0;
#10
in_a = 16'b0001111111111111;
in_b = 16'b1111111111111111;
// Wait 100 ns for global reset to finish
#10 $finish;
// Add stimulus here
end
endmodule
| 6.677602 |
module test_arbiter_rr;
// Parameters
localparam PORTS = 32;
localparam TYPE = "ROUND_ROBIN";
localparam BLOCK = "REQUEST";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [PORTS-1:0] request = 0;
reg [PORTS-1:0] acknowledge = 0;
// Outputs
wire [PORTS-1:0] grant;
wire grant_valid;
wire [$clog2(PORTS)-1:0] grant_encoded;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, request, acknowledge);
$to_myhdl(grant, grant_valid, grant_encoded);
// dump file
$dumpfile("test_arbiter_rr.lxt");
$dumpvars(0, test_arbiter_rr);
end
arbiter #(
.PORTS(PORTS),
.TYPE (TYPE),
.BLOCK(BLOCK)
) UUT (
.clk(clk),
.rst(rst),
.request(request),
.acknowledge(acknowledge),
.grant(grant),
.grant_valid(grant_valid),
.grant_encoded(grant_encoded)
);
endmodule
| 6.979721 |
module test_ariSHIFT;
reg [15:0] IN;
reg RIGHT;
wire [15:0] OUT;
ari_SHIFT shift0 (
OUT,
IN,
RIGHT
);
initial begin
IN = 16'b1000000000000010;
RIGHT = 1;
#100 RIGHT = 0;
#100 IN = 16'b0000000111000010;
#100 RIGHT = 1;
end
endmodule
| 6.828039 |
module test_arp_cache;
// Parameters
parameter CACHE_ADDR_WIDTH = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg query_request_valid = 0;
reg [31:0] query_request_ip = 0;
reg query_response_ready = 0;
reg write_request_valid = 0;
reg [31:0] write_request_ip = 0;
reg [47:0] write_request_mac = 0;
reg clear_cache = 0;
// Outputs
wire query_request_ready;
wire query_response_valid;
wire query_response_error;
wire [47:0] query_response_mac;
wire write_request_ready;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, query_request_valid, query_request_ip, query_response_ready,
write_request_valid, write_request_ip, write_request_mac, clear_cache);
$to_myhdl(query_request_ready, query_response_valid, query_response_error, query_response_mac,
write_request_ready);
// dump file
$dumpfile("test_arp_cache.lxt");
$dumpvars(0, test_arp_cache);
end
arp_cache #(
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// Query cache
.query_request_valid(query_request_valid),
.query_request_ready(query_request_ready),
.query_request_ip(query_request_ip),
.query_response_valid(query_response_valid),
.query_response_ready(query_response_ready),
.query_response_error(query_response_error),
.query_response_mac(query_response_mac),
// Write cache
.write_request_valid(write_request_valid),
.write_request_ready(write_request_ready),
.write_request_ip(write_request_ip),
.write_request_mac(write_request_mac),
// Configuration
.clear_cache(clear_cache)
);
endmodule
| 7.894332 |
module testfixture;
//`define direction_matrix "../dat/compare.dat"
//`define H_matrix "../dat/H.dat"
`define sequence "../dat/BinaryInput.dat"
`define data_size "../dat/data_size.dat"
reg clk_i = 0;
reg rst_n;
reg [`BP_WIDTH-1:0] S;
reg [`BP_WIDTH-1:0] T;
reg s_update;
wire [`CALC_WIDTH-1:0] max_o;
wire busy;
reg valid;
reg ack;
reg new_seq;
reg [`SEQ_MAX_LEN*2-1:0] seq[0:7];
reg [11:0] seq_len[0:7]; //sequence length
integer err_cnt;
integer k;
integer i;
integer j;
integer s_size;
integer t_size;
integer iter;
`ifdef SDF
initial $sdf_annotate(`SDFFILE, top);
`endif
initial begin
$fsdbDumpfile("ARRAY.fsdb");
$fsdbDumpvars;
$fsdbDumpMDA;
end
initial begin
$timeformat(-9, 1, " ns", 9); //Display time in nanoseconds
$readmemb(`sequence, seq);
$readmemh(`data_size, seq_len);
$display("--------------------------- [ Simulation Starts !! ] ---------------------------");
end
always #(`cycle / 2) clk_i = ~clk_i;
systolic systolic (
.clk(clk_i),
.reset_i(rst_n),
.S(S),
.T(T),
.s_update(s_update),
.max_o(),
.busy(busy),
.ack(ack),
.new_seq(new_seq),
.valid(valid)
);
initial begin
rst_n = 1;
err_cnt = 0;
s_update = 0;
ack = 0;
valid = 0;
new_seq = 0;
#`cycle;
rst_n = 0;
#(`cycle * 2);
rst_n = 1;
#(`cycle / 4)
for (
k = 0; k < 8; k = k + 2
) // how much pair of sequence alignment
begin
@(negedge clk_i);
s_size = seq_len[k];
t_size = seq_len[k+1];
new_seq = 1;
#`cycle;
new_seq = 0;
if(s_size > `N) //need to be calculated iteratively
begin
iter = s_size / `N;
if (s_size % `N != 0) iter = iter + 1;
end
ack = 1;
for (j = 0; j < iter; j = j + 1) begin
@(negedge clk_i);
for (
i = (`N - 1) * 2; i >= 0; i = i - 2
) //S signal serial in
begin
#`cycle;
S = seq[k][(j*2*`N+i)+:2];
end
ack = 0;
s_update = 1;
#`cycle;
s_update = 0;
ack = 1;
#`cycle;
for (
i = 0; i < t_size * 2; i = i + 2
) //T signal serial in
begin
T = seq[k+1][i+:2];
valid = 1;
#`cycle;
end
valid = 0;
wait (busy == 0);
end
end
$finish;
end
initial begin
#`terminate_cycle;
$display(
"================================================================================================================");
$display("(/`n`)/ ~# There is something wrong with your code!!");
$display("Time out!! The simulation didn't finish after %d cycles!!, Please check it!!!",
`terminate_cycle);
$display(
"================================================================================================================");
$finish;
end
endmodule
| 6.999147 |
module datamemory (
write,
addr,
datain,
dataout,
clk,
reset
);
input [31:0] datain;
input [15:0] addr;
input write, clk, reset;
output [31:0] dataout;
reg [31:0] mem[63:0];
assign dataout = mem[addr];
always @(posedge clk) begin
if (reset) begin
mem[0] <= 32'b0000000000000000_0000000000000001;
mem[1] <= 32'b0000000000000000_0000000000000010;
mem[2] <= 32'b0000000000000000_0000000000000001;
mem[3] <= 32'b0000000000000000_0000000000000011;
mem[4] <= 32'b0000000000000000_0000000000000001;
mem[5] <= 32'b0000000000000000_0000000000000010;
mem[6] <= 32'b0000000000000000_0000000000000001;
mem[7] <= 32'b0000000000000000_0000000000000011;
mem[8] <= 32'b0000000000000000_0000000000000001;
mem[9] <= 32'b0000000000000000_0000000000000001;
mem[10] <= 32'b0000000000000000_0000000000000001;
mem[11] <= 32'b0000000000000000_0000000000000001;
mem[12] <= 32'b0000000000000000_0000000000000001;
mem[13] <= 32'b0000000000000000_0000000000000000;
mem[14] <= 32'b0000000000000000_0000000000000001;
mem[15] <= 32'b0000000000000000_0000000000000001;
mem[16] <= 32'b0000000000000000_0000000000000001;
mem[17] <= 32'b0000000000000000_0000000000000001;
mem[18] <= 32'b0000000000000000_0000000000000000;
mem[19] <= 32'b0000000000000000_0000000000000000;
mem[20] <= 32'b0000000000000000_0000000000000000;
mem[21] <= 32'b0000000000000000_0000000000000000;
mem[22] <= 32'b0000000000000000_0000000000000000;
mem[23] <= 32'b0000000000000000_0000000000000000;
mem[24] <= 32'b0000000000000000_0000000000000000;
mem[25] <= 32'b0000000000000000_0000000000000000;
mem[26] <= 32'b0000000000000000_0000000000000000;
mem[27] <= 32'b0000000000000000_0000000000000000;
mem[28] <= 32'b0000000000000000_0000000000000000;
mem[29] <= 32'b0000000000000000_0000000000000000;
mem[30] <= 32'b0000000000000000_0000000000000000;
mem[31] <= 32'b0000000000000000_0000000000000000;
mem[32] <= 32'b0000000000000000_0000000000000000;
end else begin
if (write == 1) mem[addr] <= datain;
end
end
endmodule
| 7.533611 |
module test_asm18 (
input clk_50M,
output reg [7:0] ledout,
input uart_rx_pin,
output reg uart_tx_pin,
input key_86,
input key_87
);
localparam WORD_SIZE = 18;
wire clock_proc;
logic [17:0] data_address_a = 0;
logic [17:0] data_address_b = 0;
logic [17:0] data_write_a = 0;
logic [17:0] data_write_b;
wire [17:0] data_read_a;
wire [17:0] data_read_b;
logic data_wren_a = 0;
logic data_wren_b;
wire [17:0] code_address_a;
wire [17:0] code_address_b;
wire [17:0] code_write_a = 0;
wire [17:0] code_write_b;
wire [17:0] code_read_a;
wire [17:0] code_read_b;
logic code_wren_a = 0;
logic code_wren_b;
logic processor_reset = 1;
logic wait_for_continue;
logic wait_continue_execution = 0;
logic debug_get_param = 0;
logic [3:0] debug_reg_addr = 0;
logic [(WORD_SIZE-1):0] debug_data_out;
`ifdef USE_100MHZ
localparam UART_CLKS_PER_BIT = 200; //500 kbps for 100 MHz clock
fast_pll pll25mhz (
clk_50M,
clock_proc
);
`else
`ifdef USE_25MHZ
localparam UART_CLKS_PER_BIT = 50; //500 kbps for 25 MHz clock
slow_pll pll25mhz (
clk_50M,
clock_proc
);
`else
localparam UART_CLKS_PER_BIT = 100; //500 kbps for 50 MHz clock
assign clock_proc = clk_50M;
`endif
`endif
uart_controller #(
.UART_CLKS_PER_BIT(UART_CLKS_PER_BIT)
) uart_controller0 (
.clock(clock_proc),
.uart_rx_pin(uart_rx_pin),
.uart_tx_pin(uart_tx_pin),
.ledout_pins(ledout),
.data_address(data_address_b),
.data_read(data_read_b),
.data_write(data_write_b),
.data_wren(data_wren_b),
.code_address(code_address_b),
.code_read(code_read_b),
.code_write(code_write_b),
.code_wren(code_wren_b),
.processor_reset(processor_reset),
.wait_for_continue(wait_for_continue),
.wait_continue_execution(wait_continue_execution),
.debug_get_param(debug_get_param),
.debug_reg_addr(debug_reg_addr),
.debug_data_out(debug_data_out)
);
mem_async mem1k_data (
.address_a(data_address_a),
.address_b(data_address_b),
.clock(clock_proc),
.data_a(data_write_a),
.data_b(data_write_b),
.wren_a(data_wren_a),
.wren_b(data_wren_b),
.q_a(data_read_a),
.q_b(data_read_b)
);
mem_async mem1k_code (
.address_a(code_address_a),
.address_b(code_address_b),
.clock(clock_proc),
.data_a(code_write_a),
.data_b(code_write_b),
.wren_a(code_wren_a),
.wren_b(code_wren_b),
.q_a(code_read_a),
.q_b(code_read_b)
);
//processor
processor_staged #(
.ADDR_SIZE(WORD_SIZE),
.WORD_SIZE(WORD_SIZE)
) processor18 (
.clock(clock_proc),
.reset(processor_reset),
//Интерфейс для чтения программы
.code_addr(code_address_a),
.code_word(code_read_a),
//Интерфейс для чтения данных
.memory_write_enable(data_wren_a),
.memory_addr(data_address_a),
.memory_in(data_write_a),
.memory_out(data_read_a),
//Интерфейс для ожидания внешних данных
.wait_for_continue(wait_for_continue),
.wait_continue_execution(wait_continue_execution),
//Debug
.debug_get_param(debug_get_param),
.debug_reg_addr (debug_reg_addr),
.debug_data_out (debug_data_out)
);
endmodule
| 7.135502 |
module comp (
A1,
A2,
Z
);
//ports
input A1;
input A2;
output Z;
//wires
wire A1;
wire A2;
wire Z;
wire [7:0] A_buss2;
wire [1:0] A_buss;
wire B1;
wire B2;
//assignments
assign Z = A2;
assign {Z, B1} = {A2, A1};
assign A_buss = {A2, A1};
assign A_buss = {2{B1}};
assign A_buss2 = {{2{B1}}, A_buss, B2, 3'b10x};
//instances
endmodule
| 6.646188 |
module TEST_ASYNC_FIFO ();
reg wclk, rclk, rst;
localparam [32-1:0] WINT = 514, // 20,// 97,
RINT = 500, //100,//101,
RSTWIDTH = (WINT > RINT ? WINT : RINT) * 2 * 10;
initial begin
$display("WINT:%d, RINT:%d, RSTWIDTH:%d", WINT, RINT, RSTWIDTH);
end
initial begin
wclk = 1'b1;
forever #WINT wclk = ~wclk;
end
initial begin
rclk = 1'b1;
forever #RINT rclk = ~rclk;
end
//initial begin
// forever #10000 $display("tick");
//end
initial begin
$display("assert rst");
rst = 1'b1;
#RSTWIDTH $display("deassert rst");
rst = 1'b0;
#1000000 $display("finish");
$finish();
end
initial begin
wdata = 0;
end
wire enqueue = !full;
always @(posedge wclk) begin
//enqueue <= !full;
if (!rst) begin
if (!full) begin
wdata <= wdata + 1;
end else begin
$display("full! (normal behavior)");
end
end
//$display("%b", enqueue);
end
wire dequeue = !empty;
reg dequeue_reg;
reg [8-1:0] rdata_prev = 0;
localparam diff = 1;
wire [8-1:0] expected = rdata_prev + diff;
always @(posedge rclk) begin
if (dequeue_reg) begin
if (rdata !== expected) begin
//if(rdata[0+:10] != 10'h00 && rdata != rdata_prev+10'h01) begin
$display("\ninvalid rdata? expected:%h, actual:%h", expected, rdata);
//$display("x invalid rdata! expected:%h, actual:%h", rdata_prev+10'h01, rdata);
end else begin
//$write("o");
$display("o %h", rdata);
end
rdata_prev <= rdata;
end
dequeue_reg <= dequeue;
end
wire full, empty, filled_r, filled_w;
reg [8-1:0] wdata;
wire [8-1:0] rdata;
ASYNC_FIFO #(8, 8, 128) af (
rst, // Hold 8 cycle for slower clock
// Write clock region
wclk,
full,
filled_w,
enqueue,
wdata,
// Read clock region
rclk,
empty,
filled_r,
dequeue,
rdata
);
endmodule
| 6.673306 |
module test_axil_cdc;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter STRB_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg s_clk = 0;
reg s_rst = 0;
reg m_clk = 0;
reg m_rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] s_axil_awaddr = 0;
reg [2:0] s_axil_awprot = 0;
reg s_axil_awvalid = 0;
reg [DATA_WIDTH-1:0] s_axil_wdata = 0;
reg [STRB_WIDTH-1:0] s_axil_wstrb = 0;
reg s_axil_wvalid = 0;
reg s_axil_bready = 0;
reg [ADDR_WIDTH-1:0] s_axil_araddr = 0;
reg [2:0] s_axil_arprot = 0;
reg s_axil_arvalid = 0;
reg s_axil_rready = 0;
reg m_axil_awready = 0;
reg m_axil_wready = 0;
reg [1:0] m_axil_bresp = 0;
reg m_axil_bvalid = 0;
reg m_axil_arready = 0;
reg [DATA_WIDTH-1:0] m_axil_rdata = 0;
reg [1:0] m_axil_rresp = 0;
reg m_axil_rvalid = 0;
// Outputs
wire s_axil_awready;
wire s_axil_wready;
wire [1:0] s_axil_bresp;
wire s_axil_bvalid;
wire s_axil_arready;
wire [DATA_WIDTH-1:0] s_axil_rdata;
wire [1:0] s_axil_rresp;
wire s_axil_rvalid;
wire [ADDR_WIDTH-1:0] m_axil_awaddr;
wire [2:0] m_axil_awprot;
wire m_axil_awvalid;
wire [DATA_WIDTH-1:0] m_axil_wdata;
wire [STRB_WIDTH-1:0] m_axil_wstrb;
wire m_axil_wvalid;
wire m_axil_bready;
wire [ADDR_WIDTH-1:0] m_axil_araddr;
wire [2:0] m_axil_arprot;
wire m_axil_arvalid;
wire m_axil_rready;
initial begin
// myhdl integration
$from_myhdl(s_clk, s_rst, m_clk, m_rst, current_test, s_axil_awaddr, s_axil_awprot,
s_axil_awvalid, s_axil_wdata, s_axil_wstrb, s_axil_wvalid, s_axil_bready,
s_axil_araddr, s_axil_arprot, s_axil_arvalid, s_axil_rready, m_axil_awready,
m_axil_wready, m_axil_bresp, m_axil_bvalid, m_axil_arready, m_axil_rdata,
m_axil_rresp, m_axil_rvalid);
$to_myhdl(s_axil_awready, s_axil_wready, s_axil_bresp, s_axil_bvalid, s_axil_arready,
s_axil_rdata, s_axil_rresp, s_axil_rvalid, m_axil_awaddr, m_axil_awprot,
m_axil_awvalid, m_axil_wdata, m_axil_wstrb, m_axil_wvalid, m_axil_bready,
m_axil_araddr, m_axil_arprot, m_axil_arvalid, m_axil_rready);
// dump file
$dumpfile("test_axil_cdc.lxt");
$dumpvars(0, test_axil_cdc);
end
axil_cdc #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH)
) UUT (
.s_clk(s_clk),
.s_rst(s_rst),
.s_axil_awaddr(s_axil_awaddr),
.s_axil_awprot(s_axil_awprot),
.s_axil_awvalid(s_axil_awvalid),
.s_axil_awready(s_axil_awready),
.s_axil_wdata(s_axil_wdata),
.s_axil_wstrb(s_axil_wstrb),
.s_axil_wvalid(s_axil_wvalid),
.s_axil_wready(s_axil_wready),
.s_axil_bresp(s_axil_bresp),
.s_axil_bvalid(s_axil_bvalid),
.s_axil_bready(s_axil_bready),
.s_axil_araddr(s_axil_araddr),
.s_axil_arprot(s_axil_arprot),
.s_axil_arvalid(s_axil_arvalid),
.s_axil_arready(s_axil_arready),
.s_axil_rdata(s_axil_rdata),
.s_axil_rresp(s_axil_rresp),
.s_axil_rvalid(s_axil_rvalid),
.s_axil_rready(s_axil_rready),
.m_clk(m_clk),
.m_rst(m_rst),
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready),
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready)
);
endmodule
| 6.989709 |
module test_axil_ram;
// Parameters
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 16;
parameter STRB_WIDTH = DATA_WIDTH / 8;
parameter PIPELINE_OUTPUT = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] s_axil_awaddr = 0;
reg [2:0] s_axil_awprot = 0;
reg s_axil_awvalid = 0;
reg [DATA_WIDTH-1:0] s_axil_wdata = 0;
reg [STRB_WIDTH-1:0] s_axil_wstrb = 0;
reg s_axil_wvalid = 0;
reg s_axil_bready = 0;
reg [ADDR_WIDTH-1:0] s_axil_araddr = 0;
reg [2:0] s_axil_arprot = 0;
reg s_axil_arvalid = 0;
reg s_axil_rready = 0;
// Outputs
wire s_axil_awready;
wire s_axil_wready;
wire [1:0] s_axil_bresp;
wire s_axil_bvalid;
wire s_axil_arready;
wire [DATA_WIDTH-1:0] s_axil_rdata;
wire [1:0] s_axil_rresp;
wire s_axil_rvalid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axil_awaddr, s_axil_awprot, s_axil_awvalid, s_axil_wdata,
s_axil_wstrb, s_axil_wvalid, s_axil_bready, s_axil_araddr, s_axil_arprot,
s_axil_arvalid, s_axil_rready);
$to_myhdl(s_axil_awready, s_axil_wready, s_axil_bresp, s_axil_bvalid, s_axil_arready,
s_axil_rdata, s_axil_rresp, s_axil_rvalid);
// dump file
$dumpfile("test_axil_ram.lxt");
$dumpvars(0, test_axil_ram);
end
axil_ram #(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT)
) UUT (
.clk(clk),
.rst(rst),
.s_axil_awaddr(s_axil_awaddr),
.s_axil_awprot(s_axil_awprot),
.s_axil_awvalid(s_axil_awvalid),
.s_axil_awready(s_axil_awready),
.s_axil_wdata(s_axil_wdata),
.s_axil_wstrb(s_axil_wstrb),
.s_axil_wvalid(s_axil_wvalid),
.s_axil_wready(s_axil_wready),
.s_axil_bresp(s_axil_bresp),
.s_axil_bvalid(s_axil_bvalid),
.s_axil_bready(s_axil_bready),
.s_axil_araddr(s_axil_araddr),
.s_axil_arprot(s_axil_arprot),
.s_axil_arvalid(s_axil_arvalid),
.s_axil_arready(s_axil_arready),
.s_axil_rdata(s_axil_rdata),
.s_axil_rresp(s_axil_rresp),
.s_axil_rvalid(s_axil_rvalid),
.s_axil_rready(s_axil_rready)
);
endmodule
| 7.467084 |
module test_axis_adapter_64_8;
// Parameters
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 8;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_adapter_64_8.lxt");
$dumpvars(0, test_axis_adapter_64_8);
end
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 8.183024 |
module test_axis_adapter_8_64;
// Parameters
parameter S_DATA_WIDTH = 8;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 64;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_adapter_8_64.lxt");
$dumpvars(0, test_axis_adapter_8_64);
end
axis_adapter #(
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 8.183024 |
module test_axis_arb_mux_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY";
parameter LSB_PRIORITY = "HIGH";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_arb_mux_4.lxt");
$dumpvars(0, test_axis_arb_mux_4);
end
axis_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 7.982128 |
module test_axis_arb_mux_4_64;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE = "PRIORITY";
parameter LSB_PRIORITY = "HIGH";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_arb_mux_4_64.lxt");
$dumpvars(0, test_axis_arb_mux_4_64);
end
axis_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 7.982128 |
module test_axis_async_fifo;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg s_clk = 0;
reg m_clk = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(async_rst, s_clk, m_clk, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid,
s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_async_fifo.lxt");
$dumpvars(0, test_axis_async_fifo);
end
axis_async_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
// Common reset
.async_rst(async_rst),
// AXI input
.s_clk(s_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
endmodule
| 8.12555 |
module test_axis_async_fifo_64;
// Parameters
parameter DEPTH = 32;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg s_clk = 0;
reg m_clk = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(async_rst, s_clk, m_clk, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid,
s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_async_fifo_64.lxt");
$dumpvars(0, test_axis_async_fifo_64);
end
axis_async_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
// Common reset
.async_rst(async_rst),
// AXI input
.s_clk(s_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 8.12555 |
module test_axis_async_fifo_adapter_64_8;
// Parameters
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 8;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg s_clk = 0;
reg s_rst = 0;
reg m_clk = 0;
reg m_rst = 0;
reg [7:0] current_test = 0;
reg [S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(s_clk, s_rst, m_clk, m_rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid,
s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_async_fifo_adapter_64_8.lxt");
$dumpvars(0, test_axis_async_fifo_adapter_64_8);
end
axis_async_fifo_adapter #(
.DEPTH(DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
// AXI input
.s_clk(s_clk),
.s_rst(s_rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_rst(m_rst),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
endmodule
| 8.12555 |
module test_axis_async_fifo_adapter_8_64;
// Parameters
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 8;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 64;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg s_clk = 0;
reg s_rst = 0;
reg m_clk = 0;
reg m_rst = 0;
reg [7:0] current_test = 0;
reg [S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(s_clk, s_rst, m_clk, m_rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid,
s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_async_fifo_adapter_8_64.lxt");
$dumpvars(0, test_axis_async_fifo_adapter_8_64);
end
axis_async_fifo_adapter #(
.DEPTH(DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
// AXI input
.s_clk(s_clk),
.s_rst(s_rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_rst(m_rst),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.s_status_overflow(),
.s_status_bad_frame(),
.s_status_good_frame(),
.m_status_overflow(),
.m_status_bad_frame(),
.m_status_good_frame()
);
endmodule
| 8.12555 |
module test_axis_async_frame_fifo;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg s_clk = 0;
reg m_clk = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire s_status_overflow;
wire s_status_bad_frame;
wire s_status_good_frame;
wire m_status_overflow;
wire m_status_bad_frame;
wire m_status_good_frame;
initial begin
// myhdl integration
$from_myhdl(async_rst, s_clk, m_clk, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid,
s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, s_status_overflow, s_status_bad_frame,
s_status_good_frame, m_status_overflow, m_status_bad_frame, m_status_good_frame);
// dump file
$dumpfile("test_axis_async_frame_fifo.lxt");
$dumpvars(0, test_axis_async_frame_fifo);
end
axis_async_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
// Common reset
.async_rst(async_rst),
// AXI input
.s_clk(s_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
endmodule
| 8.12555 |
module test_axis_async_frame_fifo_64;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg s_clk = 0;
reg m_clk = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire s_status_overflow;
wire s_status_bad_frame;
wire s_status_good_frame;
wire m_status_overflow;
wire m_status_bad_frame;
wire m_status_good_frame;
initial begin
// myhdl integration
$from_myhdl(async_rst, s_clk, m_clk, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid,
s_axis_tlast, s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, s_status_overflow, s_status_bad_frame,
s_status_good_frame, m_status_overflow, m_status_bad_frame, m_status_good_frame);
// dump file
$dumpfile("test_axis_async_frame_fifo_64.lxt");
$dumpvars(0, test_axis_async_frame_fifo_64);
end
axis_async_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
// Common reset
.async_rst(async_rst),
// AXI input
.s_clk(s_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
endmodule
| 8.12555 |
module test_axis_baser_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] encoded_rx_data = 0;
reg [HDR_WIDTH-1:0] encoded_rx_hdr = 1;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
// Outputs
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire [1:0] start_packet;
wire error_bad_frame;
wire error_bad_fcs;
wire rx_bad_block;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, encoded_rx_data, encoded_rx_hdr, ptp_ts);
$to_myhdl(m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tuser, start_packet,
error_bad_frame, error_bad_fcs, rx_bad_block);
// dump file
$dumpfile("test_axis_baser_rx_64.lxt");
$dumpvars(0, test_axis_baser_rx_64);
end
axis_baser_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.ptp_ts(ptp_ts),
.start_packet(start_packet),
.error_bad_frame(error_bad_frame),
.error_bad_fcs(error_bad_fcs),
.rx_bad_block(rx_bad_block)
);
endmodule
| 6.902249 |
module test_axis_baser_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter HDR_WIDTH = 2;
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE;
parameter PTP_TAG_WIDTH = 16;
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] encoded_tx_data;
wire [HDR_WIDTH-1:0] encoded_tx_hdr;
wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag;
wire m_axis_ptp_ts_valid;
wire [1:0] start_packet;
wire error_underflow;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser, ptp_ts, ifg_delay);
$to_myhdl(s_axis_tready, encoded_tx_data, encoded_tx_hdr, m_axis_ptp_ts, m_axis_ptp_ts_tag,
m_axis_ptp_ts_valid, start_packet, error_underflow);
// dump file
$dumpfile("test_axis_baser_tx_64.lxt");
$dumpvars(0, test_axis_baser_tx_64);
end
axis_baser_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.encoded_tx_data(encoded_tx_data),
.encoded_tx_hdr(encoded_tx_hdr),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(start_packet),
.error_underflow(error_underflow)
);
endmodule
| 6.902249 |
module test_axis_broadcast_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_broadcast_4.lxt");
$dumpvars(0, test_axis_broadcast_4);
end
axis_broadcast #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI outputs
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 7.078718 |
module test_axis_crosspoint_4x4;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT*$clog2(S_COUNT)-1:0] select = 0;
// Outputs
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, select);
$to_myhdl(m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid, m_axis_tdest,
m_axis_tuser);
// dump file
$dumpfile("test_axis_crosspoint_4x4.lxt");
$dumpvars(0, test_axis_crosspoint_4x4);
end
axis_crosspoint #(
.S_COUNT(S_COUNT),
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Control
.select(select)
);
endmodule
| 7.920432 |
module test_axis_crosspoint_4x4_64;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT*$clog2(S_COUNT)-1:0] select = 0;
// Outputs
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, select);
$to_myhdl(m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid, m_axis_tdest,
m_axis_tuser);
// dump file
$dumpfile("test_axis_crosspoint_4x4_64.lxt");
$dumpvars(0, test_axis_crosspoint_4x4_64);
end
axis_crosspoint #(
.S_COUNT(S_COUNT),
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Control
.select(select)
);
endmodule
| 7.920432 |
module test_axis_demux_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
reg enable = 0;
reg drop = 0;
reg [$clog2(M_COUNT)-1:0] select = 0;
// Outputs
wire s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, enable, drop, select);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_demux_4.lxt");
$dumpvars(0, test_axis_demux_4);
end
axis_demux #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI outputs
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Control
.enable(enable),
.drop(drop),
.select(select)
);
endmodule
| 8.270314 |
module test_axis_demux_4_64;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
reg enable = 0;
reg drop = 0;
reg [$clog2(M_COUNT)-1:0] select = 0;
// Outputs
wire s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, enable, drop, select);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_demux_4_64.lxt");
$dumpvars(0, test_axis_demux_4_64);
end
axis_demux #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI outputs
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Control
.enable(enable),
.drop(drop),
.select(select)
);
endmodule
| 8.270314 |
module test_axis_eth_fcs;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
// Outputs
wire s_axis_tready;
wire [31:0] output_fcs;
wire output_fcs_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser);
$to_myhdl(s_axis_tready, output_fcs, output_fcs_valid);
// dump file
$dumpfile("test_axis_eth_fcs.lxt");
$dumpvars(0, test_axis_eth_fcs);
end
axis_eth_fcs #(
.DATA_WIDTH (DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH (KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.output_fcs(output_fcs),
.output_fcs_valid(output_fcs_valid)
);
endmodule
| 8.161317 |
module test_axis_eth_fcs_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
// Outputs
wire s_axis_tready;
wire [31:0] output_fcs;
wire output_fcs_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser);
$to_myhdl(s_axis_tready, output_fcs, output_fcs_valid);
// dump file
$dumpfile("test_axis_eth_fcs_64.lxt");
$dumpvars(0, test_axis_eth_fcs_64);
end
axis_eth_fcs #(
.DATA_WIDTH (DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH (KEEP_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.output_fcs(output_fcs),
.output_fcs_valid(output_fcs_valid)
);
endmodule
| 8.161317 |
module test_axis_eth_fcs_check;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
wire error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser,
m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tvalid, m_axis_tlast, m_axis_tuser, busy,
error_bad_fcs);
// dump file
$dumpfile("test_axis_eth_fcs_check.lxt");
$dumpvars(0, test_axis_eth_fcs_check);
end
axis_eth_fcs_check UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy),
.error_bad_fcs(error_bad_fcs)
);
endmodule
| 8.161317 |
module test_axis_eth_fcs_check_64;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [63:0] m_axis_tdata;
wire [7:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
wire error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tuser,
busy, error_bad_fcs);
// dump file
$dumpfile("test_axis_eth_fcs_check_64.lxt");
$dumpvars(0, test_axis_eth_fcs_check_64);
end
axis_eth_fcs_check_64 UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy),
.error_bad_fcs(error_bad_fcs)
);
endmodule
| 8.161317 |
module test_axis_eth_fcs_insert;
// Parameters
parameter ENABLE_PADDING = 0;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser,
m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tvalid, m_axis_tlast, m_axis_tuser, busy);
// dump file
$dumpfile("test_axis_eth_fcs_insert.lxt");
$dumpvars(0, test_axis_eth_fcs_insert);
end
axis_eth_fcs_insert #(
.ENABLE_PADDING (ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy)
);
endmodule
| 8.161317 |
module test_axis_eth_fcs_insert_64;
// Parameters
parameter ENABLE_PADDING = 0;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [63:0] m_axis_tdata;
wire [7:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tuser,
busy);
// dump file
$dumpfile("test_axis_eth_fcs_insert_64.lxt");
$dumpvars(0, test_axis_eth_fcs_insert_64);
end
axis_eth_fcs_insert_64 #(
.ENABLE_PADDING (ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy)
);
endmodule
| 8.161317 |
module test_axis_eth_fcs_insert_64_pad;
// Parameters
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [63:0] s_axis_tdata = 0;
reg [7:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [63:0] m_axis_tdata;
wire [7:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tuser,
busy);
// dump file
$dumpfile("test_axis_eth_fcs_insert_64_pad.lxt");
$dumpvars(0, test_axis_eth_fcs_insert_64_pad);
end
axis_eth_fcs_insert_64 #(
.ENABLE_PADDING (ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy)
);
endmodule
| 8.161317 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.