code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module pc #(
parameter integer DATA_W = 16
) (
input wire clk,
input wire arst_n,
input wire enable,
input wire [DATA_W-1:0] branch_pc,
input wire [DATA_W-1:0] jump_pc,
input wire zero_flag,
input wire branch,
input wire jump,
output reg [DATA_W-1:0] updated_pc,
output reg [DATA_W-1:0] current_pc
);
localparam [DATA_W-1:0] PC_INCREASE = {{(DATA_W - 3) {1'b0}}, 3'd4};
wire [DATA_W-1:0] pc_r, next_pc, next_pc_i;
reg pc_src;
always @(*) pc_src = zero_flag & branch;
mux_2 #(
.DATA_W(DATA_W)
) mux_branch (
.input_a (branch_pc),
.input_b (updated_pc),
.select_a(pc_src),
.mux_out (next_pc_i)
);
mux_2 #(
.DATA_W(DATA_W)
) mux_jump (
.input_a (jump_pc),
.input_b (next_pc_i),
.select_a(jump),
.mux_out (next_pc)
);
reg_arstn_en #(
.DATA_W(DATA_W),
.PRESET_VAL('b0)
) pc_register (
.clk (clk),
.arst_n(arst_n),
.din (next_pc),
.en (enable),
.dout (current_pc)
);
always @(*) updated_pc = current_pc + PC_INCREASE;
endmodule
| 8.050335 |
module testeMemoria(
input CLOCK_50,
input [3:0] KEY,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS,
output [7:0]LEDG,
output [17:0] SRAM_ADDR,
inout [15:0] SRAM_DQ,
output SRAM_WE_N,
output SRAM_OE_N,
output SRAM_UB_N,
output SRAM_LB_N,
output SRAM_CE_N
);
reg [18:0] i;
reg [15:0] j;
reg [3:0] Red;
reg [3:0] Green;
reg [3:0] Blue;
reg CLK_25;
reg clock_state;
reg leitura = 0;
reg escrita = 1;
assign VGA_R = Red;
assign VGA_G = Green;
assign VGA_B = Blue;
assign VGA_HS = (i >= 660 && i <= 756) ? 0:1;
assign VGA_VS = (j >= 494 && j <= 495) ? 0:1;
// Clock 25 hz
always @(posedge CLOCK_50) begin
if (clock_state == 0) begin
CLK_25 = ~CLK_25;
end
else begin
clock_state = ~clock_state;
end
end
// contador de i e j
always @(posedge CLK_25) begin
if (i < 800) begin
i <= i + 1;
end
else begin
i <= 0;
if (j < 525) begin
j <= j + 1;
end
else begin
j <= 0;
end
end
end
// Leitura e Dados > VGA
always @(posedge CLK_25) begin
if (leitura == 1)begin
if (j < 480 && i < 640) begin
oe <= 0;
if (data_reg == 1)
Red <= 4'b1;
Green <= 4'b1;
Blue <= 4'b1;
end
else begin
Red <= 4'b0;
Green <= 4'b0;
Blue <= 4'b0;
end
addr_reg = addr_reg + 1;
end
else begin
oe <= 1;
Red <= 4'b0;
Green <= 4'b0;
Blue <= 4'b0;
end
end
end
always @(CLK_25) begin
if (i == 800 && j == 525)begin
escrita = ~escrita;
leitura = ~leitura;
end
end
// escrita de dados memoria
always @(posedge CLK_25) begin
if (escrita== 1)begin
if (j < 480 && i < 640) begin
we <= 0;
if (i > 300 & i < 400 & j > 300 & j < 400) data_reg <= 1;
else data_reg <= 0;
else
we <= 1;
end
end
endmodule
| 7.523251 |
module: Experiment
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestExperiment;
// Inputs
reg clk;
reg reset;
// Outputs
wire [31:0]x;
wire write;
wire final;
// Instantiate the Unit Under Test (UUT)
Experiment uut (
.clk(clk),
.reset(reset),
.final(final),
.write(write),
.x(x)
);
always #15 clk=!clk;
always @ (posedge clk) begin
if (write==1) begin
$display("%d", $signed(x[31:0])*2.0**-15);
// $fwrite(file,"%d\n",$signed(x[31:0])*2.0**-15);
end
/* if (final==1) begin
$fclose(file);
end*/
end
initial begin
// Initialize Inputs
//file = $fopen ("SimulacionImagen2.txt", "w");
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100
reset=0;
#15
reset=1;
#85;
#1000
#1000;
// Add stimulus here
end
endmodule
| 7.882602 |
module: Experiment2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestExperiment2;
parameter N=16;
parameter nBits=32;
parameter B=2;
parameter M=2;
// Inputs
reg clk;
reg reset;
wire write;
wire [nBits-1:0]x;
// Instantiate the Unit Under Test (UUT)
Experiment2 #(.N(N),.M(M),.nBits(32),.B(B))uut (
.clk(clk),
.write(write),
.x(x),
.reset(reset)
);
always @ (posedge clk) begin
if (write==1) begin
$display("%f", $signed(x[31:0])*(2.0**(-15)));
end
end
always #15 clk=!clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
// Wait 100 ns for global reset to finish
#100
reset=0;
#10
reset=1;
#1000;
// Add stimulus here
end
endmodule
| 6.898896 |
module TestExtremaValueEn (
input iclk,
input irst_n,
input iBig_en1,
input iBig_en2,
input iBig_en3,
output reg oBig_en
);
always @(posedge iclk or negedge irst_n) begin
if (!irst_n) begin
oBig_en <= 0;
end else begin
if (iBig_en1 & iBig_en2 & iBig_en3) begin
oBig_en <= 1;
end else begin
oBig_en <= 0;
end
end
end
endmodule
| 7.804649 |
module test_base_01;
// ------------------------- definir dados
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// ------------------------- parte principal
initial begin
$display("Exemplo0011 - xxx yyy zzz - 999999");
$display("Test number system");
a = 5;
b = 10;
c = 15;
d = 20;
$display("\nPositive value");
$display("a = %d = %3b", a, a);
$display("b = %d = %4b", a, a);
$display("c = %d = %5b", a, a);
$display("b = %d = %4b", b, b);
$display("c = %d = %5b", c, c);
$display("d = %d = %5b", d, d);
$display("d = %d = %5o", d, d);
$display("d = %d = %5h", d, d);
end
endmodule
| 6.932753 |
module teste_guia_11;
reg clk, reset, x;
wire m1, m2, m3, m4, m5;
guia11_ex01.v EX1 (
m1,
x,
clk,
reset
);
guia11_ex02.v EX2 (
m2,
x,
clk,
reset
);
guia11_ex03.v EX3 (
m3,
x,
clk,
reset
);
guia11_ex04.v EX4 (
m4,
x,
clk,
reset
);
guia11_ex05.v EX5 (
m5,
x,
clk,
reset
);
initial begin
$display("Guia 11 - Arquivo de testes");
$display("Eduardo de Abreu Fortes - 384047");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#10 reset = 1;
#10 x = 1;
#10 x = 0;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 0;
#10 x = 0;
#5 $finish;
end // initial
always #5 clk = ~clk;
always @(posedge clk) begin
$display("%4d\t\t%b\t\t\t%b\t\t\t\t\t%b\t\t\t\t\t%b\t\t\t\t\t%b\t\t\t\t%b", $time, x, m1, m2,
m3, m4, m5);
end // always at positive edge clocking changing
endmodule
| 6.698242 |
module soma_completa_1bit (
s0,
s1,
a,
b,
c
);
// operador de soma completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
or OR1 (s1, sa2, sa3);
endmodule
| 7.237842 |
module soma_completa_3bit (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
b0,
b1,
b2
);
// operador de soma completa de 3 bits
input a0, a1, a2, b0, b1, b2;
output s0, s1, s2, s3;
wire sa1, sa2;
// instancia
soma_completa_1bit SC1 (
s0,
sa1,
a0,
b0,
0
);
soma_completa_1bit SC2 (
s1,
sa2,
a1,
b1,
sa1
);
soma_completa_1bit SC3 (
s2,
s3,
a2,
b2,
sa2
);
endmodule
| 7.237842 |
module subt_comp_1b (
s0,
s1,
a,
b,
c
);
// operador de diferena completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_subt SUBT1 (
sa1,
sa2,
a,
b
);
meia_subt SUBT2 (
s0,
sa3,
sa1,
c
);
or OR1 (s1, sa2, sa3);
endmodule
| 7.03597 |
module soma_completa_1bit (
s0,
s1,
a,
b,
c
);
// operador de soma completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
or OR1 (s1, sa2, sa3);
endmodule
| 7.237842 |
module prod_comp_2bits (
s0,
s1,
s2,
s3,
a0,
a1,
b0,
b1
);
// operador de produto completo de 2 bits
input a0, a1, b0, b1;
output s0, s1, s2, s3;
wire sa1, sa2, sa3, sa4;
// instancia
and AND1 (s0, a0, b0);
and AND2 (sa1, a0, b1);
and ADN3 (sa2, a1, b0);
and AND4 (sa3, a1, b1);
meia_soma MS1 (
s1,
sa4,
sa1,
sa2
);
soma_completa_1bit SC1 (
s2,
s3,
sa3,
0,
sa4
);
endmodule
| 6.82542 |
module subt_comp_1bit (
s0,
s1,
a,
b,
c
);
// operador de diferena completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3, sa4;
// instancia
meia_subt SUBT1 (
sa1,
sa2,
a,
b
);
meia_subt SUBT2 (
s0,
sa3,
sa1,
c
);
nor NOR1 (sa4, sa2, sa3);
nor NOR2 (s1, sa4, sa4);
endmodule
| 7.152747 |
module subt_comp_2bit (
s0,
s1,
s2,
a0,
a1,
b0,
b1
);
// operador de diferena completa de 2 bit
input a0, a1, b0, b1;
output s0, s1, s2;
wire sa1;
// instancia
subt_comp_1bit SUBT1 (
s0,
sa1,
a0,
b0,
0
);
subt_comp_1bit SUBT2 (
s1,
s2,
a1,
b1,
sa1
);
endmodule
| 7.422042 |
module soma_comp_1bit (
s0,
s1,
a,
b,
c
);
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3, sa4, sa5;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
nand NAND1 (sa4, sa2, sa2);
nand NAND2 (sa5, sa3, sa3);
nand NAND3 (s1, sa4, sa5);
endmodule
| 7.023876 |
module soma_comp_2bit (
s0,
s1,
s2,
a0,
a1,
b0,
b1
);
input a0, a1, b0, b1;
output s0, s1, s2;
wire sa1;
// instancia
soma_comp_1bit SC1 (
s0,
sa1,
a0,
b0,
0
);
soma_comp_1bit SC2 (
s1,
s2,
a1,
b1,
sa1
);
endmodule
| 7.012556 |
module soma_completa_1bit (
s0,
s1,
a,
b,
c
);
// operador de soma completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
or OR1 (s1, sa2, sa3);
endmodule
| 7.237842 |
module soma_completa_4bit (
s0,
s1,
s2,
s3,
auxCR,
auxOVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
// operador de soma completa de 4 bits
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, auxCR, auxOVR;
wire sa1, sa2, sa3;
// instancia
soma_completa_1bit SC1 (
s0,
sa1,
a0,
b0,
0
);
soma_completa_1bit SC2 (
s1,
sa2,
a1,
b1,
sa1
);
soma_completa_1bit SC3 (
s2,
sa3,
a2,
b2,
sa2
);
soma_completa_1bit SC4 (
s3,
auxCR,
a3,
b3,
sa3
);
not NOT1 (auxOVR, sa3);
endmodule
| 7.237842 |
module soma_ovr_cr (
s0,
s1,
s2,
s3,
CR,
OVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
// operador de soma completa de 4 bits, detector de carry e de overflow
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, OVR, CR;
wire auxOVR;
// instancia
soma_completa_4bit SOMA (
s0,
s1,
s2,
s3,
CR,
auxOVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
and AND1 (OVR, auxOVR, CR);
endmodule
| 6.972168 |
module comparador_log (
s,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
input a0, a1, a2, a3, b0, b1, b2, b3;
output s;
wire sa1, sa2, sa3, sa4;
xor XOR1 (sa1, a0, b0);
xor XOR2 (sa2, a1, b1);
xor XOR3 (sa3, a2, b2);
xor XOR4 (sa4, a3, b3);
or OR1 (s, sa1, sa2, sa3, sa4);
endmodule
| 6.729621 |
module meiaDiferenca (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
wire sa1;
xor XOR1 (s0, a, b);
not NOT1 (sa1, a);
and AND1 (s1, sa1, b);
endmodule
| 8.132121 |
module soma_completa_1bit (
s0,
s1,
a,
b,
c
);
// operador de soma completa de 1 bit
input a, b, c;
output s0, s1;
wire sa1, sa2, sa3;
// instancia
meia_soma MEIA1 (
sa1,
sa2,
a,
b
);
meia_soma MEIA2 (
s0,
sa3,
sa1,
c
);
or OR1 (s1, sa2, sa3);
endmodule
| 7.237842 |
module soma_completa_4bit (
s0,
s1,
s2,
s3,
auxCR,
auxOVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
// operador de soma completa de 4 bits
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, auxCR, auxOVR;
wire sa1, sa2, sa3;
// instancia
soma_completa_1bit SC1 (
s0,
sa1,
a0,
b0,
0
);
soma_completa_1bit SC2 (
s1,
sa2,
a1,
b1,
sa1
);
soma_completa_1bit SC3 (
s2,
sa3,
a2,
b2,
sa2
);
soma_completa_1bit SC4 (
s3,
auxCR,
a3,
b3,
sa3
);
not NOT1 (auxOVR, sa3);
endmodule
| 7.237842 |
module soma_ovr_cr (
s0,
s1,
s2,
s3,
CR,
OVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
// operador de soma completa de 4 bits, detector de carry e de overflow
input a0, a1, a2, a3, b0, b1, b2, b3;
output s0, s1, s2, s3, OVR, CR;
wire auxOVR;
// instancia
soma_completa_4bit SOMA (
s0,
s1,
s2,
s3,
CR,
auxOVR,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
and AND1 (OVR, auxOVR, CR);
endmodule
| 6.972168 |
module comparador_log (
s,
a0,
a1,
a2,
a3,
b0,
b1,
b2,
b3
);
input a0, a1, a2, a3, b0, b1, b2, b3;
output s;
wire sa1, sa2, sa3, sa4;
xor XOR1 (sa1, a0, b0);
xor XOR2 (sa2, a1, b1);
xor XOR3 (sa3, a2, b2);
xor XOR4 (sa4, a3, b3);
or OR1 (s, sa1, sa2, sa3, sa4);
endmodule
| 6.729621 |
module complemento_2 (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
a3
);
input a0, a1, a2, a3;
output s0, s1, s2, s3;
wire sa0, sa1, sa2, sa3, CR, OVR;
complemento_1 COMP1 (
sa0,
sa1,
sa2,
sa3,
a0,
a1,
a2,
a3
);
soma_ovr_cr SOMA1 (
s0,
s1,
s2,
s3,
CR,
OVR,
sa0,
sa1,
sa2,
sa3,
1,
0,
0,
0
);
endmodule
| 6.625481 |
module meiaDiferenca (
s0,
s1,
a,
b
);
input a, b;
output s0, s1;
wire sa1;
xor XOR1 (s0, a, b);
not NOT1 (sa1, a);
and AND1 (s1, sa1, b);
endmodule
| 8.132121 |
module incremento (
s0,
s1,
s2,
s3,
a0,
a1,
a2,
a3
);
input a0, a1, a2, a3;
output s0, s1, s2, s3;
wire CR, OVR;
soma_ovr_cr SOMA1 (
s0,
s1,
s2,
s3,
CR,
OVR,
a0,
a1,
a2,
a3,
1,
0,
0,
0
);
endmodule
| 6.976155 |
module produto (
s,
erro,
x
);
input [3:0] x;
output [3:0] s;
output erro;
assign s[0] = 0;
assign s[1] = x[0];
assign s[2] = x[1];
assign s[3] = x[2];
xor XOR1 (erro, x[3], x[2]);
endmodule
| 7.220624 |
module numero_01 (
s,
a,
b,
c,
d
);
input a, b, c, d;
output s;
wire sa1, sa2, sa3, sa4, sa5, sa6;
// instancia
not NOT1 (sa1, d);
not NOT2 (sa2, a);
not NOT3 (sa3, b);
and AND1 (sa4, a, b, sa1);
and AND2 (sa5, sa2, c);
and AND3 (sa6, sa3, c);
or OR1 (s, sa4, sa5, sa6);
endmodule
| 6.633437 |
module exercicio_01 (
qL,
q,
s,
r
);
// latch sr com portas nor
output q, qL;
input s, r;
nor NOR1 (qL, s, q);
nor NOR2 (q, r, qL);
endmodule
| 6.88485 |
module exercicio_02 (
qL,
q,
s,
r
);
// latch sr com portas nand
output q, qL;
input s, r;
nand NAND1 (q, s, qL);
nand NAND2 (qL, r, q);
endmodule
| 7.495124 |
module exercicio_03 (
qL,
q,
d,
pr,
cl
);
// latch d com portas nand, preset e clear
output q, qL;
input d, pr, cl;
wire dL;
not NOT1 (dL, d);
nand NAND1 (q, d, qL, pr);
nand NAND2 (qL, dL, q, cl);
endmodule
| 7.149001 |
module exercicio_04 (
qL,
q,
s,
r,
pr,
cl
);
// latch sr com portas nand, preset e clear
output q, qL;
input s, r, pr, cl;
nand NAND1 (q, s, qL, pr);
nand NAND2 (qL, r, q, cl);
endmodule
| 7.294467 |
module exercicio_05 (
qL,
q,
d
);
// latch d a partir de sr, sem preset e clear
output q, qL;
input d;
wire dL;
// negar o d
not NOT1 (dL, d);
// metodo com latch do tipo sr
exercicio_01 SR (
qL,
q,
d,
dL
);
endmodule
| 7.10458 |
module teste_guia_11;
reg clk, reset, x;
wire m1, m2, m3, m4, m5;
numero01_seq101_mealy NUM1 (
m1,
x,
clk,
reset
);
numero02_seq0101_moore NUM2 (
m2,
x,
clk,
reset
);
numero03_seq1001_mealy NUM3 (
m3,
x,
clk,
reset
);
numero04_seq010_101 NUM4 (
m4,
x,
clk,
reset
);
numero05_seq000_111 NUM5 (
m5,
x,
clk,
reset
);
initial begin
$display(
"Guia 11 - Mariana Ramos de Brito - 405820\nTime\t\tX\tSequencia 101 com intersecao\tSequencia 0101 sem intersecao\tSequencia 1001 com intersecao\tSequencia 101 ou 010\tSequencia 000 ou 111");
// initial values
clk = 1;
reset = 0;
x = 0;
// input signal changing
#10 reset = 1;
#10 x = 1;
#10 x = 0;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 1;
#10 x = 1;
#10 x = 0;
#10 x = 1;
#10 x = 0;
#10 x = 0;
#10 x = 0;
#5 $finish;
end // initial
always #5 clk = ~clk;
always @(posedge clk) begin
$display("%4d\t\t%b\t\t\t%b\t\t\t\t\t%b\t\t\t\t\t%b\t\t\t\t\t%b\t\t\t\t%b", $time, x, m1, m2,
m3, m4, m5);
end // always at positive edge clocking changing
endmodule
| 6.698242 |
module flipflopD (
q,
d,
clk
);
output q;
input d;
input clk;
reg q = 0;
always @(posedge clk) begin
q <= d;
end // always borda de subida do clock
endmodule
| 7.073663 |
module teste_numero01;
reg clk, x;
wire q1, q2, q3, q4, q5;
// definir flipflops
flipflopD FLIP1 (
q1,
x,
clk
);
flipflopD FLIP2 (
q2,
q1,
clk
);
flipflopD FLIP3 (
q3,
q2,
clk
);
flipflopD FLIP4 (
q4,
q3,
clk
);
flipflopD FLIP5 (
q5,
q4,
clk
);
initial begin
$display(
"Guia 12 - Mariana Ramos de Brito - 405820\nNumero 01: registrador de deslocamento para a direita.\n\nTempo\tX\tA\tB\tC\tD\tE");
// initial values
clk = 1;
x = 1;
// input signal changing
#10 x = 0;
#10 x = 0;
#10 x = 0;
#10 x = 0;
#5 $finish;
end // initial
always #5 clk = ~clk;
always @(negedge clk) begin
$display("%4d\t\t%b\t%b\t%b\t%b\t%b\t%b", $time, x, q1, q2, q3, q4, q5);
end // always at positive edge clocking changing
endmodule
| 7.187823 |
module flipflopD (
q,
d,
clk,
pr
);
output q;
input d;
input clk;
input pr;
reg q = 0;
always @(posedge clk or pr) begin
if (pr) q <= 1;
else q <= d;
end // always borda de subida do clock
endmodule
| 7.073663 |
module teste_numero02;
reg clk, load, d4, d3, d2, d1, d0;
wire q1, q2, q3, q4, q5, pr1, pr2, pr3, pr4, pr5;
//definir presets
and AND1 (pr1, load, d4);
and AND2 (pr2, load, d3);
and AND3 (pr3, load, d2);
and AND4 (pr4, load, d1);
and AND5 (pr5, load, d0);
// definir flipflops
flipflopD FLIP1 (
q1,
0,
clk,
pr1
);
flipflopD FLIP2 (
q2,
q1,
clk,
pr2
);
flipflopD FLIP3 (
q3,
q2,
clk,
pr3
);
flipflopD FLIP4 (
q4,
q3,
clk,
pr4
);
flipflopD FLIP5 (
q5,
q4,
clk,
pr5
);
initial begin
$display(
"Guia 12 - Mariana Ramos de Brito - 405820\nNumero 02: conversor paralelo-serie.\n\nTempo\tLoad\t\tD4\tD3\tD2\tD1\tD0\t\tA\tB\tC\tD\tE");
// initial values
clk = 1;
load = 0;
d4 = 0;
d3 = 0;
d2 = 0;
d1 = 0;
d0 = 0;
// input signal changing
#10 load = 1;
d4 = 1;
d3 = 0;
d2 = 1;
d1 = 1;
d0 = 0;
#10 load = 0;
d4 = 1;
d3 = 0;
d2 = 1;
d1 = 1;
d0 = 0;
#10 load = 1;
d4 = 0;
d3 = 0;
d2 = 1;
d1 = 0;
d0 = 0;
#10 load = 0;
d4 = 1;
d3 = 1;
d2 = 0;
d1 = 1;
d0 = 0;
#10 load = 0;
d4 = 1;
d3 = 1;
d2 = 0;
d1 = 1;
d0 = 0;
#10 load = 0;
d4 = 1;
d3 = 1;
d2 = 0;
d1 = 1;
d0 = 0;
#10 load = 1;
d4 = 1;
d3 = 1;
d2 = 1;
d1 = 1;
d0 = 1;
#10 load = 1;
d4 = 0;
d3 = 0;
d2 = 1;
d1 = 1;
d0 = 0;
#5 $finish;
end // initial
always #5 clk = ~clk;
always @(negedge clk) begin
$display("%4d\t\t%b\t\t%b\t%b\t%b\t%b\t%b\t\t%b\t%b\t%b\t%b\t%b\n", $time, load, d4, d3, d2,
d1, d0, q1, q2, q3, q4, q5);
end // always at positive edge clocking changing
endmodule
| 7.187823 |
module flipflopD (
q,
d,
clk
);
output q;
input d;
input clk;
reg q = 0;
always @(posedge clk) begin
q <= d;
end // always borda de subida do clock
endmodule
| 7.073663 |
module teste_numero04;
reg clk, x;
wire q1, q2, q3, q4, q5;
// definir flipflops
flipflopD FLIP1 (
q5,
x,
clk
);
flipflopD FLIP2 (
q4,
q5,
clk
);
flipflopD FLIP3 (
q3,
q4,
clk
);
flipflopD FLIP4 (
q2,
q3,
clk
);
flipflopD FLIP5 (
q1,
q2,
clk
);
initial begin
$display(
"Guia 12 - Mariana Ramos de Brito - 405820\nNumero 04: registrador de deslocamento para a esquerda.\n\nTempo\tX\tA\tB\tC\tD\tE");
// initial values
clk = 1;
x = 1;
// input signal changing
#10 x = 0;
#10 x = 0;
#10 x = 0;
#10 x = 0;
#5 $finish;
end // initial
always #5 clk = ~clk;
always @(negedge clk) begin
$display("%4d\t\t%b\t%b\t%b\t%b\t%b\t%b", $time, x, q1, q2, q3, q4, q5);
end // always at positive edge clocking changing
endmodule
| 7.187823 |
module teste_Program_conter_module (
input clock,
input reset_geral,
input modo_preemptivo,
input reset_cont_preempcao,
input [4:0] quantum,
input halt,
input [1:0] jump_prog,
output [31:0] PC,
output [31:0] PC_mais_1,
output flag_faz_preempcao,
output [31:0] salva_PC
);
Program_Counter Program_counter_0 (
.clock(clock),
.PC_in(PC_mais_1),
.PC(PC),
.PC_mais_1(PC_mais_1),
.reset_geral(reset_geral),
.reset_cont_preempcao(reset_cont_preempcao),
.quantum(quantum),
.modo_preemptivo(modo_preemptivo),
.salva_PC(salva_PC),
.flag_faz_preempcao(flag_faz_preempcao),
.halt(halt),
.jump_prog(jump_prog)
);
endmodule
| 8.160279 |
module teste_s (
input iCLK_50,
input [17:0] iSW,
input [3:0] iKEY,
output [17:0] oLEDR,
output [8:0] oLEDG,
output [6:0] oHEX0_D,
oHEX1_D,
oHEX2_D,
oHEX3_D,
oHEX4_D,
oHEX5_D,
oHEX6_D,
oHEX7_D,
output oHEX0_DP,
oHEX1_DP,
oHEX2_DP,
oHEX3_DP,
oHEX4_DP,
oHEX5_DP,
oHEX6_DP,
oHEX7_DP
);
wire [3:0] f1;
wire f2;
assign oLEDR = iSW;
assign oLEDG[0] = iKEY[0];
assign oLEDG[1] = ~iKEY[0];
assign oLEDG[2] = iKEY[1];
assign oLEDG[3] = ~iKEY[1];
assign oLEDG[4] = iKEY[2];
assign oLEDG[5] = ~iKEY[2];
assign oLEDG[6] = iKEY[3];
assign oLEDG[7] = ~iKEY[3];
assign oHEX0_DP = 1'b1;
assign oHEX1_DP = 1'b1;
assign oHEX1_D = 7'b1111111;
assign oHEX2_DP = 1'b1;
assign oHEX2_D = 7'b1111111;
assign oHEX3_DP = 1'b1;
assign oHEX4_DP = 1'b1;
assign oHEX5_DP = 1'b1;
assign oHEX6_DP = 1'b1;
assign oHEX6_D = 7'b1111111;
assign oHEX7_DP = 1'b1;
assign oHEX7_D = 7'b1111111;
add4v_s a0 (
.clock(iCLK_50),
.iA(iSW[3:0]),
.iB(iSW[17:14]),
.oSUM(f1[3:0]),
.oCARRY(f2)
); //modulo somador
decoder7_s t0 (
.In(iSW[3:0]),
.Out(oHEX0_D),
.clock(iCLK_50)
);
decoder7_s t1 (
.In(iSW[17:14]),
.Out(oHEX3_D),
.clock(iCLK_50)
);
decoder7_s t2 (
.In(f1[3:0]),
.Out(oHEX4_D),
.clock(iCLK_50)
);
show_carry_s s0 (
.carry (f2),
.display(oHEX5_D),
.clock (iCLK_50)
);
endmodule
| 7.293189 |
module testfixture1;
reg clk;
reg reset;
reg fft_en;
wire fir_valid;
wire fin;
reg [15:0] fir_d; // 8 integer + 8 fraction
wire [31:0] fft_d;
wire [3:0] freq;
wire [15:0] fft_real = fft_d[31:16];
wire [15:0] fft_imag = fft_d[15:0];
reg en;
reg [15:0] fir_mem[0:1023];
initial $readmemh("FFT_in.dat", fir_mem);
reg [15:0] fftr_mem[0:1023];
initial $readmemh("Golden1_FFT_real.dat", fftr_mem);
reg [15:0] ffti_mem[0:1023];
initial $readmemh("Golden1_FFT_imag.dat", ffti_mem);
integer i, j, k, l, count;
integer fft_fail;
fft DUT (
.clk(clk),
.rst(reset),
.fir_data(fir_d),
.fir_valid(fft_en),
.fft_data(fft_d),
.fft_valid(fft_valid),
.freq(freq),
.fft_fin(fin)
);
/*
* fir_data: input of fft
* fir_valid: input enable
* fft_data: output of fft
* fft_valid: ?
* freq: ?
* fin: ?
*/
initial begin
$dumpfile("FAS.vcd");
$dumpvars;
end
initial begin
#0;
clk = 1'b0;
reset = 1'b0;
i = 0;
j = 0;
k = 0;
l = 0;
fft_fail = 0;
count = 0;
end
always begin
#(`CYCLE / 2) clk = ~clk;
end
initial begin
en = 0;
#(`CYCLE * 0.5) reset = 1'b1;
#(`CYCLE * 2);
#0.5;
reset = 1'b0;
en = 1;
end
// data input & ready
always @(negedge clk) begin
if (en) begin
if (i >= 1024) fir_d <= 0;
else begin
fir_d <= fir_mem[i];
i <= i + 1;
end
end
fft_en <= en;
if (fin) count = count + 1;
if (count >= 64) begin
$display("-----------------------------------------------------");
$display("-------------End of sim ----------------------------");
$finish;
end
end
// Terminate the simulation, FAIL
initial begin
#(`CYCLE * `End_CYCLE);
$display("-----------------------------------------------------");
$display("-------------End of time ----------------------------");
$finish;
end
endmodule
| 6.530037 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testForFuck;
// Inputs
reg data_ready;
reg tsre;
reg tbre;
reg Clk0;
reg Rst;
// Outputs
wire data_ready_out;
wire tsre_out;
wire rdn;
wire wrn;
wire Ram2_EN;
wire Ram2_OE;
wire Ram2_WE;
wire [17:0] Ram2_address;
wire Ram1_EN;
wire Ram1_OE;
wire Ram1_WE;
wire [17:0] Ram1_address;
wire [15:0] Src1;
wire [15:0] Src2;
wire [15:0] RegPeek1;
wire [15:0] PcAddr4;
// Bidirs
wire [15:0] Ram2_data;
wire [15:0] Ram1_data;
// Instantiate the Unit Under Test (UUT)
top uut (
.data_ready(data_ready),
.tsre(tsre),
.tbre(tbre),
.data_ready_out(data_ready_out),
.tsre_out(tsre_out),
.rdn(rdn),
.wrn(wrn),
.Clk0(Clk0),
.Rst(Rst),
.Ram2_EN(Ram2_EN),
.Ram2_OE(Ram2_OE),
.Ram2_WE(Ram2_WE),
.Ram2_address(Ram2_address),
.Ram2_data(Ram2_data),
.Ram1_EN(Ram1_EN),
.Ram1_OE(Ram1_OE),
.Ram1_WE(Ram1_WE),
.Ram1_address(Ram1_address),
.Ram1_data(Ram1_data),
.Src1(Src1),
.Src2(Src2),
.RegPeek1(RegPeek1),
.PcAddr4(PcAddr4)
);
initial begin
// Initialize Inputs
data_ready = 0;
tsre = 0;
tbre = 0;
Clk0 = 0;
Rst = 0;
Clk = 0;
forever #50 Clk = ~Clk;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.115105 |
module: Parse32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testforparse;
// Inputs
reg clk;
reg [31:0] data;
// Outputs
wire [63:0] odata;
// Instantiate the Unit Under Test (UUT)
Parse32 uut (
.clk(clk),
.data(data),
.odata(odata)
);
initial begin
// Initialize Inputs
clk = 0;
data = 0;
data=32'b00010010001101000101011001111000;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always
begin
#1;
clk=0;
#1;
clk=1;
end
endmodule
| 6.764872 |
module testForPC;
wire [31:0] nowPc;
wire [31:0] instruct;
wire [31:0] nextPc;
reg clk;
reg rstn;
reg clear;
reg jump;
reg [31:0] imm;
initial begin
clk = 0;
rstn = 0;
jump = 0;
#10 rstn = 1'b1;
clear = 1'b1;
#10 jump = 1'b1;
imm = 32'b0000_0000_0000_0000_0000_0000_0000_1000;
#10 jump = 0;
end
always #10 clk = ~clk;
pcAdder pcAdder0 (
.nowPc(nowPc),
.nextPc(nextPc),
.clear(clear),
.jump(jump),
.imm(imm)
);
instMem instMem0 (
.clear(clear),
.address(nowPc),
.instruct(instruct)
);
PC PC (
.rstn(rstn),
.clk(clk),
.nextPc(nextPc),
.nowPc(nowPc)
);
endmodule
| 7.113817 |
module testForregFile;
reg clk;
reg rstn;
reg [4:0] Wadd;
reg [31:0] Wdata;
reg isWreg;
reg [4:0] Radd1;
wire [31:0] Rdata1;
reg [4:0] Radd2;
wire [31:0] Rdata2;
reg [5:0] ALUctr;
wire [31:0] result;
regFile regFile0 (
.clk(clk),
.rstn(rstn),
.Wadd(Wadd),
.Wdata(Wdata),
.isWreg(isWreg),
.Radd1(Radd1),
.Radd2(Radd2),
.Rdata1(Rdata1),
.Rdata2(Rdata2)
);
ALU ALU0 (
.rs1(Rdata1),
.rs2(Rdata2),
.ALUctr(ALUctr),
.res(result)
);
initial begin
clk = 0;
rstn = 0;
#100;
rstn = 1'b1;
isWreg = 1'b1;
Wadd = 5'b00000;
Wdata = 32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100;
Wadd = 5'b00001;
Wdata = 32'b0000_0000_0000_0000_0000_0000_0000_0010;
#100;
Radd1 = 5'b00000;
Radd2 = 5'b00001;
ALUctr = 6'b000000;
end
always #10 clk = ~clk;
endmodule
| 7.096511 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testforwhole;
// Inputs
reg CCLK;
reg BTN2;
reg BTN1;
reg BTN3;
reg [3:0] SW;
// Outputs
wire LCDRS;
wire LCDRW;
wire LCDE;
wire [3:0] LCDDAT;
wire [7:0] LED;
wire [31:0] disp_num;
wire [31:0] PC,AAdat,BBdat,Result;
wire [2:0]ALUoper;
wire JUMP_ID_EX,BEQ_EX_MEM,BNE_EX_MEM,ZERO_EX_MEM;
// Instantiate the Unit Under Test (UUT)
top uut (
.CCLK(CCLK),
.BTN1(BTN1),
.BTN2(BTN2),
.BTN3(BTN3),
.SW(SW),
.LCDRS(LCDRS),
.LCDRW(LCDRW),
.LCDE(LCDE),
.LCDDAT(LCDDAT)/*,
.LED(LED),
.disp_num(disp_num),
.PC(PC),
.AAdat(AAdat),
.BBdat(BBdat),
.Result(Result),
.ALUoper(ALUoper),
.JUMP_ID_EX(JUMP_ID_EX),
.BEQ_EX_MEM(BEQ_EX_MEM),
.BNE_EX_MEM(BNE_EX_MEM),
.ZERO_EX_MEM(ZERO_EX_MEM)*/
);
initial begin
// Initialize Inputs
CCLK = 0;
BTN2 = 0;
BTN1 = 0;
SW = 4'b1011;
// Wait 100 ns for global reset to finish
#100;
SW = 4'b0001; //addi $s0, $zero, 5
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=0;
BTN2=1; //ori $s1, $s1, 3
#10;
BTN2=0;
#100;
SW = 4'b0011;
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0100;
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0101;
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0110;
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0011;
BTN1=1;
BTN2=1;//sub $s3, $s0, $s1
#10;
BTN2=0;
#100;
SW = 4'b0100;
BTN1=1;
BTN2=1;//and $s4, $s0, $s1
#10;
BTN2=0;
#100;
SW = 4'b0101;
BTN1=1;
BTN2=1;//or $s5, $s0, $s1
#10;
BTN2=0;
#100;
SW = 4'b0000;
BTN1=1;
BTN2=1;//srl $s0, $s0, 2
#10;
BTN2=0;
#100;
SW = 4'b0000;
BTN1=1;
BTN2=1;//sll $s0, $s0, 31
#10;
BTN2=0;
#100;
SW = 4'b0000;
BTN1=1;
BTN2=1;//sra $s0, $s0, 31
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//sw $s2, 0($zero)
#10;
BTN2=0;
#100;
SW = 4'b0011;
BTN1=1;
BTN2=1;//lw $s3, 0($zero)
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//subi $s2, $s2, 1
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//jump:beq $s2, $s3, 2
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//addi $s2, $s2, 1
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//j jump
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//bne $s2, $s3, 2
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//subi $s2, $s3, 1
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//addi $s2, $s2, 1
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
end
always
begin
#1;
CCLK=0;
#1;
CCLK=1;
end
endmodule
| 7.115105 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testforwholen;
// Inputs
reg CCLK;
reg BTN1;
reg BTN2;
reg BTN3;
reg [3:0] SW;
// Outputs
wire LCDRS;
wire LCDRW;
wire LCDE;
wire [3:0] LCDDAT;
wire [7:0] LED;
// Instantiate the Unit Under Test (UUT)
top uut (
.CCLK(CCLK),
.BTN1(BTN1),
.BTN2(BTN2),
.BTN3(BTN3),
.SW(SW),
.LCDRS(LCDRS),
.LCDRW(LCDRW),
.LCDE(LCDE),
.LCDDAT(LCDDAT),
.LED(LED)
);
initial begin
// Initialize Inputs
CCLK = 0;
BTN2 = 0;
BTN1 = 0;
SW = 4'b1011;
// Wait 100 ns for global reset to finish
#100;
SW = 4'b0001; //addi $s0, $zero, 5
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=0;
BTN2=1; //ori $s1, $s1, 3
#10;
BTN2=0;
#100;
SW = 4'b0011;
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0100;
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0101;
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0110;
BTN1=0;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
SW = 4'b0011;
BTN1=1;
BTN2=1;//sub $s3, $s0, $s1
#10;
BTN2=0;
#100;
SW = 4'b0100;
BTN1=1;
BTN2=1;//and $s4, $s0, $s1
#10;
BTN2=0;
#100;
SW = 4'b0101;
BTN1=1;
BTN2=1;//or $s5, $s0, $s1
#10;
BTN2=0;
#100;
SW = 4'b0000;
BTN1=1;
BTN2=1;//srl $s0, $s0, 2
#10;
BTN2=0;
#100;
SW = 4'b0000;
BTN1=1;
BTN2=1;//sll $s0, $s0, 31
#10;
BTN2=0;
#100;
SW = 4'b0000;
BTN1=1;
BTN2=1;//sra $s0, $s0, 31
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//sw $s2, 0($zero)
#10;
BTN2=0;
#100;
SW = 4'b0011;
BTN1=1;
BTN2=1;//lw $s3, 0($zero)
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//subi $s2, $s2, 1
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//jump:beq $s2, $s3, 2
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//addi $s2, $s2, 1
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//j jump
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//bne $s2, $s3, 2
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//subi $s2, $s3, 1
#10;
BTN2=0;
#100;
SW = 4'b0010;
BTN1=1;
BTN2=1;//addi $s2, $s2, 1
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
BTN2=1;
#10;
BTN2=0;
#100;
end
always
begin
#1;
CCLK=0;
#1;
CCLK=1;
end
endmodule
| 7.115105 |
module testFU ();
reg [31:0] rs_data, rt_data, memwb_data;
reg [4:0] rs_addr, rt_addr, exmem_rd_addr, memwb_rd_addr;
reg [3:0] exmem_byte_en, memwb_byte_en;
wire [31:0] input_A, input_B;
wire [1:0] A_sel, B_sel;
ForwardUnit m0 (
.rs_data(rs_data),
.rt_data(rt_data),
.memwb_data(memwb_data),
.rs_addr(rs_addr),
.rt_addr(rt_addr),
.exmem_rd_addr(exmem_rd_addr),
.memwb_rd_addr(memwb_rd_addr),
.exmem_byte_en(exmem_byte_en),
.memwb_byte_en(memwb_byte_en),
.input_A(input_A),
.input_B(input_B),
.A_sel(A_sel),
.B_sel(B_sel)
);
initial begin
rs_data = 32'h50505050;
rt_data = 32'ha0a0a0a0;
memwb_data = 32'h3c3c3c3c;
exmem_rd_addr = 5'd0;
memwb_rd_addr = 5'd0;
exmem_byte_en = 4'b1111;
memwb_byte_en = 4'b1111;
end
always begin
//add $3,$2,$1;
//sub $5,$3,$4;
//should forward from Ex/Mem,A_sel = 2'01,B_sel = 2'b00
rs_addr = 5'd3;
rt_addr = 5'd4;
exmem_rd_addr = 5'd3;
#20;
//add $3,$2,$1;
//or $6,$2,$1;
//sub $5,$3,$4;
//should forward from Mem/Wr,A_sel = 2'b10,B_sel = 2'b00;
rs_addr = 5'd3;
rt_addr = 5'd4;
exmem_rd_addr = 5'd6;
memwb_rd_addr = 5'd3;
#20;
//add $1,$1,$2;
//add $1,$1,$3;
//add $1,$1,$4;
//should forward from Ex/Mem,A_sel = 2'b01,B_sel = 2'b00;
rs_addr = 5'd1;
rt_addr = 5'd4;
exmem_rd_addr = 5'd1;
memwb_rd_addr = 5'd1;
#20;
//add $1,$2,$3;
//add $2,$3,$4;
//Not forward,A_sel = 2'b00,B_sel = 2'b00;
rs_addr = 5'd3;
rt_addr = 5'd4;
exmem_rd_addr = 5'd1;
#20;
//add $1,$2,$3;
//add $4,$1,$3;
//sub $5,$4,$1;
//Two forward together,A_sel = 2'b01,B_sel = 2'b10;
rs_addr = 5'd4;
rt_addr = 5'd1;
exmem_rd_addr = 5'd4;
memwb_rd_addr = 5'd1;
#40;
end
always begin
exmem_byte_en = 4'b1111;
memwb_byte_en = 4'b1111;
#20;
exmem_byte_en = 4'b1111;
memwb_byte_en = 4'b1111;
#20;
exmem_byte_en = 4'b1111;
memwb_byte_en = 4'b1010;
#20;
exmem_byte_en = 4'b1111;
memwb_byte_en = 4'b0000;
#20;
exmem_byte_en = 4'b1111;
memwb_byte_en = 4'b0011;
#20;
exmem_byte_en = 4'b1111;
memwb_byte_en = 4'b0000;
#20;
end
endmodule
| 6.712866 |
module/testfx_spi.v
// Project Name: spi_module
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spi_master_4byte
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testfx_spi;
// Inputs
reg MISO;
reg CLK_IN;
wire [15:0] din;
wire trigger;
wire [9:0] target;
wire CPOL;
wire CPHA;
// Outputs
wire MOSI;
wire SPI_CLK;
wire [9:0] SPI_SS;
wire [15:0] dout;
wire valid;
// Instantiate the Unit Under Test (UUT)
spi_master # (.N(10), .C(16)) uut (
.MISO(MISO),
.MOSI(MOSI),
.SPI_CLK(SPI_CLK),
.SPI_SS(SPI_SS),
.CLK_IN(CLK_IN),
.din(din),
.dout(dout),
.trigger(trigger),
.target(target),
.valid(valid),
.CPOL(CPOL),
.CPHA(CPHA)
);
spi_programmer programmer (
.command(din),
.ss(target),
.ready(valid),
.trigger(trigger),
.clock(CLK_IN),
.CPOL(CPOL),
.CPHA(CPHA)
);
initial begin
// Initialize Inputs
MISO = 0;
CLK_IN = 0;
// Wait 100 ns for global reset to finish
end
always #5 CLK_IN = ~CLK_IN;
endmodule
| 7.102711 |
module testgen;
// Inputs
reg clk;
reg [31:0] out_freq;
reg [31:0] discr_freq;
// Outputs
wire [15:0] sin;
wire [15:0] cos;
// Instantiate the Unit Under Test (UUT)
cordic_gen uut (
.clk(clk),
.out_freq(out_freq),
.discr_freq(discr_freq),
.sin(sin),
.cos(cos)
);
reg [31:0] cnt = 32'b0;
reg [ 1:0] freq = 2'b0;
wire [19:0] arg = uut.my_arg;
initial begin
out_freq = 50;
forever #25000000 out_freq <= out_freq + 50;
end
initial begin
// Initialize Inputs
clk = 0;
discr_freq = 8000;
forever #(100 / 2) clk = ~clk;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.217801 |
module TestGuitarHero (
KEY,
LEDR,
CLOCK_50
);
input [3:0] KEY;
input CLOCK_50;
output [7:0] LEDR;
wire [3:0] empty_data;
assign empty_data = 4'b0000;
wire never_write;
assign never_write = 1'b0;
wire [3:0] track1_out;
ram32x4_track1 track1 (
.address(5'b00000),
.clock(CLOCK_50),
.data(empty_data),
.wren(never_write),
.q(track1_out)
);
assign LEDR[7:4] = track1_out;
endmodule
| 6.986991 |
module testHarness ();
// -----------------------------------
// Local Wires
// -----------------------------------
reg clk;
reg rst;
wire [8:0] adr;
wire [7:0] masterDout;
wire [7:0] masterDin;
wire [7:0] usbSlaveDout;
wire [7:0] usbHostDout;
wire stb;
wire we;
wire ack;
wire host_stb;
wire DPlusPullup;
wire DPlusPullDown;
wire DMinusPullup;
wire DMinusPulDown;
reg USBWireVP;
reg USBWireVM;
wire [1:0] hostUSBWireDataIn;
wire [1:0] hostUSBWireDataOut;
wire hostUSBWireCtrlOut;
wire usbSlaveOE_n;
wire usbSlaveVP_out;
wire usbSlaveVM_out;
wire USBDMinusPullup;
assign USBDMinusPullup = 1'b0;
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, testHarness);
end
pullup (DPlusPullup);
pulldown (DPlusPullDown);
pullup (DMinusPullup);
pulldown (DMinusPullDown);
assign hostUSBWireDataIn = {USBWireVP, USBWireVM};
always @(*) begin
if (hostUSBWireCtrlOut == 1'b1 && usbSlaveOE_n == 1'b1)
{USBWireVP, USBWireVM} <= hostUSBWireDataOut;
else if (hostUSBWireCtrlOut == 1'b0 && usbSlaveOE_n == 1'b0)
{USBWireVP, USBWireVM} <= {usbSlaveVP_out, usbSlaveVM_out};
else if (hostUSBWireCtrlOut == 1'b1 && usbSlaveOE_n == 1'b0) {USBWireVP, USBWireVM} <= 2'bxx;
else if (hostUSBWireCtrlOut == 1'b0 && usbSlaveOE_n == 1'b1) begin
if (USBDPlusPullup == 1'b1) USBWireVP <= DPlusPullup;
else USBWireVP <= DPlusPullDown;
if (USBDMinusPullup == 1'b1) USBWireVM <= DMinusPullup;
else USBWireVM <= DMinusPullDown;
end
end
assign host_stb = stb;
assign masterDin = usbHostDout;
//Parameters declaration:
defparam u_usbHost.HOST_FIFO_DEPTH = 64;
parameter HOST_FIFO_DEPTH = 64;
defparam u_usbHost.HOST_FIFO_ADDR_WIDTH = 6;
parameter HOST_FIFO_ADDR_WIDTH = 6;
usbHost u_usbHost (
.clk_i(clk),
.rst_i(rst),
.address_i(adr[7:0]),
.data_i(masterDout),
.data_o(usbHostDout),
.we_i(we),
.strobe_i(host_stb),
.ack_o(ack),
.usbClk(clk),
.hostSOFSentIntOut(hostSOFSentIntOut),
.hostConnEventIntOut(hostConnEventIntOut),
.hostResumeIntOut(hostResumeIntOut),
.hostTransDoneIntOut(hostTransDoneIntOut),
.USBWireDataIn(hostUSBWireDataIn),
.USBWireDataInTick(USBWireDataInTick),
.USBWireDataOut(hostUSBWireDataOut),
.USBWireDataOutTick(USBWireDataOutTick),
.USBWireCtrlOut(hostUSBWireCtrlOut),
.USBFullSpeed(USBFullSpeed)
);
usbDevice u_usbDevice (
.clk(clk),
.rst(rst),
.usbSlaveVP_in(USBWireVP),
.usbSlaveVM_in(USBWireVM),
.usbSlaveVP_out(usbSlaveVP_out),
.usbSlaveVM_out(usbSlaveVM_out),
.usbSlaveOE_n(usbSlaveOE_n),
.usbDPlusPullup(USBDPlusPullup),
.vBusDetect(1'b1)
);
wb_master_model #(
.dwidth(8),
.awidth(9)
) u_wb_master_model (
.clk (clk),
.rst (rst),
.adr (adr),
.din (masterDin),
.dout(masterDout),
.cyc (),
.stb (stb),
.we (we),
.sel (),
.ack (ack),
.err (1'b0),
.rty (1'b0)
);
//--------------- reset ---------------
initial begin
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
rst <= 1'b1;
@(posedge clk);
rst <= 1'b0;
@(posedge clk);
end
// ****************************** Clock section ******************************
`define CLK_50MHZ_HALF_PERIOD 10
`define CLK_25MHZ_HALF_PERIOD 20
always begin
#`CLK_25MHZ_HALF_PERIOD clk <= 1'b0;
#`CLK_25MHZ_HALF_PERIOD clk <= 1'b1;
end
endmodule
| 7.129426 |
module: IFU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testIFU;
// Inputs
reg clk;
reg reset;
reg [2:0] nPC_sel;
reg [31:0] imm32;
reg [31:0] PC_jr;
reg [31:0] PC_j;
// Outputs
wire [31:0] PCa4;
wire [31:0] instr;
// Instantiate the Unit Under Test (UUT)
IFU uut (
.clk(clk),
.reset(reset),
.nPC_sel(nPC_sel),
.imm32(imm32),
.PC_jr(PC_jr),
.PC_j(PC_j),
.PCa4(PCa4),
.instr(instr)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
nPC_sel = 0;
imm32 = 0;
PC_jr = 0;
PC_j = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.644283 |
module testIm_ctrl (
input clock,
input reset,
input [`SCREEN_X_BITWIDTH:0] x_coord,
input [`SCREEN_Y_BITWIDTH:0] y_coord,
output reg [9:0] test_addr
);
// shift left control
always @(posedge clock or negedge reset) begin
if (reset == 1'b0) begin
test_addr <= 0;
end else if( x_coord >= 300 &&
x_coord < (300 + `SCREEN_X_WIDTH'd`BUFFER_W) &&
y_coord >= 300 &&
y_coord < (300 + `SCREEN_Y_WIDTH'd`BUFFER_H)
)
//shift_left <= 1'd1;
test_addr <= test_addr + 1;
// else if (x_coord == (300 + `SCREEN_X_WIDTH'd`BUFFER_W) &&
// y_coord >= 300 &&
// y_coord < (300 + `SCREEN_Y_WIDTH'd`BUFFER_H - 1)
// )
// //shift_up <= 1'd1;
// test_addr <= test_addr + 1;
else if (x_coord == 0 & y_coord == 0) test_addr <= 0;
else test_addr <= test_addr;
end // always
endmodule
| 7.14564 |
module TestIncDec ();
reg CLK;
always #25 CLK = ~CLK;
wire [15:0] AddrBus;
wire [15:0] d;
wire [15:0] nq;
Reg16 acc (
.clk(CLK),
.d (d),
.nq (nq)
);
// The value on the cbus/dbus contains a ~val of register (register `q` output inversion).
// This value is stored on the BusKeeper. From the BusKeeper inverted value of ~val as `val` is fed to the IDU.
// At the output of the IDU the value is fed to the adl/adh buses as `val`.
// There is an inverter on the register input that loads ~val into the register.
// In the register the value is stored as ~val (inverse hold)
// To simplify testing, we simply put the inverse register value on the cbus/dbus, and the register stores the value in its regular form.
IncDec incdec (
.CLK4(CLK),
.TTB1(1'b0),
.TTB2(1'b0),
.TTB3(1'b1), // +1
.Maybe1(1'b0),
.cbus(nq[7:0]),
.dbus(nq[15:8]),
.adl(d[7:0]),
.adh(d[15:8]),
.AddrBus(AddrBus)
);
initial begin
$display("Test IncDec.");
CLK <= 1'b0;
$dumpfile("TestIncDec.vcd");
$dumpvars(0, incdec);
$dumpvars(1, acc);
repeat (32) @(posedge CLK);
$finish;
end
endmodule
| 6.584179 |
module Reg16 (
clk,
d,
q,
nq
);
input clk;
input [15:0] d;
output [15:0] q;
output [15:0] nq;
reg [15:0] val;
initial val <= 16'h0;
always @(negedge clk) begin
val <= d;
end
assign q = val;
assign nq = ~q;
endmodule
| 7.358075 |
module testbench;
initial begin
$dumpfile("test.vcd");
$dumpvars(0, testbench, sixteenbitdecoder, SpeedClock);
$finish;
end
endmodule
| 7.015571 |
module testbench (
speedy_clock
);
input speedy_clock;
initial begin
$dumpfile("test.vcd");
$display($time, "speedy_clock changed to %d", speedy_clock);
$dumpvars(0, testbench, sixteenbitdecoder, SpeedClock, clock);
$monitor($time, "speedy_clock is now %d", speedy_clock);
#1;
$monitor($time, "speedy_clock is now %d", speedy_clock);
#1;
$monitor($time, "speedy_clock is now %d", speedy_clock);
#1;
$monitor($time, "speedy_clock is now %d", speedy_clock);
#100;
$finish;
end
endmodule
| 6.751666 |
module testingAT;
// Inputs
reg clock;
reg reset;
reg bt_state;
reg [15:0] ep01wireIn;
reg [15:0] ep02wireIn;
parameter uart_cpd = 10'd50;
parameter uart_byte_spacing = 10'd12;
reg [15:0] half_word;
reg user_data_on_line;
reg user_data_done;
// Outputs
wire fpga_txd;
wire fpga_rxd;
wire [15:0] ep20wireOut;
wire [15:0] ep21wireOut;
wire [15:0] ep22wireOut;
wire [15:0] ep23wireOut;
wire [15:0] ep24wireOut;
wire [15:0] ep25wireOut;
wire tx_done;
// Instantiate the Unit Under Test (UUT)
FPGA_Bluetooth_connection uut (
.clock(clock),
.bt_state(bt_state),
.fpga_txd(fpga_txd),
.fpga_rxd(fpga_rxd),
.uart_cpd(uart_cpd),
.uart_byte_spacing_limit(uart_byte_spacing),
.ep01wireIn(ep01wireIn),
.ep02wireIn(ep02wireIn),
.ep20wireOut(ep20wireOut),
.ep21wireOut(ep21wireOut),
.ep22wireOut(ep22wireOut),
.ep23wireOut(ep23wireOut),
.ep24wireOut(ep24wireOut),
.ep25wireOut(ep25wireOut)
);
UART_sender_for_testing help (
.clock(clock),
.reset(reset),
.uart_cpd(uart_cpd),
.uart_byte_spacing(uart_byte_spacing),
.user_data_on_line(user_data_on_line),
.user_data_done(user_data_done),
.tx_done(tx_done),
.half_word(half_word),
.tx_line(fpga_rxd)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
reset = 1'b1;
bt_state = 0;
ep01wireIn = 0;
ep02wireIn = 0;
user_data_on_line = 1'b0;
user_data_done = 1'b0;
half_word = 16'h0000;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#0 reset = 1'b0;
#0 ep02wireIn = 16'h0001;
#50 ep02wireIn = 16'h0004;
#100 ep01wireIn = "AT";
#100 ep02wireIn = 16'h000C;
#150 ep02wireIn = 16'h0014;
#200 ep01wireIn = "+N";
#200 ep02wireIn = 16'h000C;
#250 ep02wireIn = 16'h0014;
#300 ep01wireIn = "AM";
#300 ep02wireIn = 16'h000C;
#350 ep02wireIn = 16'h0014;
#400 ep01wireIn = "E=";
#400 ep02wireIn = 16'h000C;
#450 ep02wireIn = 16'h0014;
#500 ep01wireIn = "OP";
#500 ep02wireIn = 16'h000C;
#550 ep02wireIn = 16'h0034;
#6000 half_word = "OK";
#6000 user_data_on_line = 1'b1;
#6001 user_data_on_line = 1'b0;
#6300 user_data_done = 1'b1;
end
endmodule
| 6.860844 |
module testingDS;
// Inputs
reg clock;
reg reset;
reg bt_state;
reg [15:0] ep01wireIn;
reg [15:0] ep02wireIn;
parameter uart_cpd = 10'd50;
parameter uart_byte_spacing = 10'd12;
reg [15:0] half_word;
reg user_data_on_line;
reg user_data_done;
// Outputs
wire fpga_txd;
wire fpga_rxd;
wire [15:0] ep20wireOut;
wire [15:0] ep21wireOut;
wire [15:0] ep22wireOut;
wire [15:0] ep23wireOut;
wire [15:0] ep24wireOut;
wire [15:0] ep25wireOut;
// wire [127:0] sensor_stream0, sensor_stream1, sensor_stream2, sensor_stream3, sensor_stream4, sensor_stream5, sensor_stream6, sensor_stream7;
// wire [7:0] sensor_stream_ready;
// Instantiate the Unit Under Test (UUT)
FPGA_Bluetooth_connection uut (
.clock(clock),
.bt_state(bt_state),
.fpga_txd(fpga_txd),
.fpga_rxd(fpga_rxd),
.uart_cpd(uart_cpd),
.uart_byte_spacing_limit(uart_byte_spacing),
// .sensor_stream0(sensor_stream0),
// .sensor_stream1(sensor_stream1),
// .sensor_stream2(sensor_stream2),
// .sensor_stream3(sensor_stream3),
// .sensor_stream4(sensor_stream4),
// .sensor_stream5(sensor_stream5),
// .sensor_stream6(sensor_stream6),
// .sensor_stream7(sensor_stream7),
// .sensor_stream_ready(sensor_stream_ready),
// .access_sensor_stream(access_sensor_stream),
.ep01wireIn(ep01wireIn),
.ep02wireIn(ep02wireIn),
.ep20wireOut(ep20wireOut),
.ep21wireOut(ep21wireOut),
.ep22wireOut(ep22wireOut),
.ep23wireOut(ep23wireOut),
.ep24wireOut(ep24wireOut),
.ep25wireOut(ep25wireOut)
);
UART_sender_for_testing help (
.clock(clock),
.reset(reset),
.uart_cpd(uart_cpd),
.uart_byte_spacing(uart_byte_spacing),
.user_data_on_line(user_data_on_line),
.user_data_done(user_data_done),
.tx_done(tx_done),
.half_word(half_word),
.tx_line(fpga_rxd)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
bt_state = 0;
ep01wireIn = 0;
ep02wireIn = 0;
user_data_on_line = 1'b0;
user_data_done = 1'b0;
half_word = 16'h0000;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#0 reset = 1'b0;
#0 ep02wireIn = 16'h0001;
#100 ep02wireIn = 16'h0002;
#200 half_word = 16'h00AA;
#200 user_data_on_line = 1'b1;
#205 user_data_on_line = 1'b0;
#210 user_data_done = 1'b1;
end
endmodule
| 6.617691 |
module testingFIFO_Centre;
// Inputs
reg clock;
reg reset;
reg [8:0] wr_en, rd_en;
// Outputs
wire [15:0] datastream0, datastream1, datastream2, datastream3, datastream4, datastream5, datastream6, datastream7;
wire [8:0] fifo_state_full, fifo_state_empty;
wire [5:0] DS0_rd_count, DS1_rd_count, DS2_rd_count, DS3_rd_count, DS4_rd_count, DS5_rd_count, DS6_rd_count, DS7_rd_count;
wire [3:0] DS0_wr_count, DS1_wr_count, DS2_wr_count, DS3_wr_count, DS4_wr_count, DS5_wr_count, DS6_wr_count, DS7_wr_count;
parameter sensor0 = "Hello World! :-)", sensor1 = "DragonForce TFAF", sensor2 = "Bloody_Radio.exe", sensor3 = "Linkin=Park.xlsx";
parameter sensor4 = "Fly on a Dog[tm]", sensor5 = "Foo^Fighting^ooF", sensor6 = "~~KAWAII~~~~~~~~", sensor7 = "*I LIKE PICKLES*";
// Instantiate the Unit Under Test (UUT)
FIFO_centre uut (
.read_clock(clock),
.write_clock(clock),
.reset(reset),
.DS0_in(sensor0),
.DS1_in(sensor1),
.DS2_in(sensor2),
.DS3_in(sensor3),
.DS4_in(sensor4),
.DS5_in(sensor5),
.DS6_in(sensor6),
.DS7_in(sensor7),
.DS0_out(datastream0),
.DS1_out(datastream1),
.DS2_out(datastream2),
.DS3_out(datastream3),
.DS4_out(datastream4),
.DS5_out(datastream5),
.DS6_out(datastream6),
.DS7_out(datastream7),
.DS0_rd_count(DS0_rd_count),
.DS1_rd_count(DS1_rd_count),
.DS2_rd_count(DS2_rd_count),
.DS3_rd_count(DS3_rd_count),
.DS4_rd_count(DS4_rd_count),
.DS5_rd_count(DS5_rd_count),
.DS6_rd_count(DS6_rd_count),
.DS7_rd_count(DS7_rd_count),
.DS0_wr_count(DS0_wr_count),
.DS1_wr_count(DS1_wr_count),
.DS2_wr_count(DS2_wr_count),
.DS3_wr_count(DS3_wr_count),
.DS4_wr_count(DS4_wr_count),
.DS5_wr_count(DS5_wr_count),
.DS6_wr_count(DS6_wr_count),
.DS7_wr_count(DS7_wr_count),
.AT_in(),
.AT_out(),
.AT_rd_count(),
.AT_wr_count(),
.write_enable(wr_en),
.read_enable (rd_en),
.full_flag (fifo_state_full),
.empty_flag(fifo_state_empty)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
wr_en = 9'h000;
rd_en = 9'h000;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#0 reset = 1'b0;
#0 wr_en = 9'h0FF;
#1 wr_en = 9'h07F;
#10 wr_en = 9'h033;
#150 rd_en = 9'h0a0;
end
endmodule
| 6.849459 |
module testingHandleAppCommands;
// Inputs
reg clock;
reg reset;
reg start;
reg [15:0] half_word;
reg user_data_on_line;
reg user_data_done;
wire [7:0] rx_data;
wire data_line;
wire rx_done;
parameter uart_cpd = 10'd50;
parameter uart_byte_spacing = 10'd12;
// Outputs
wire [7:0] stream_select;
wire ds_sending_flag;
// wire [1:0] ds_curr, ds_next;
// wire [7:0] commands, operands;
// Instantiate the Unit Under Test (UUT)
handle_app_commands uut (
// .ds_curr(ds_curr),
// .ds_next(ds_next),
// .commands(commands),
// .operands(operands),
.clock(clock),
.reset(reset),
.start(start),
.uart_done(rx_done),
.uart_cpd(uart_cpd),
.uart_byte_spacing(uart_byte_spacing),
.uart_byte(rx_data),
.stream_select(stream_select),
.ds_sending_flag(ds_sending_flag)
);
UART_sender_for_testing help (
.clock(clock),
.reset(reset),
.uart_cpd(uart_cpd),
.uart_byte_spacing(uart_byte_spacing),
.user_data_on_line(user_data_on_line),
.user_data_done(user_data_done),
.tx_done(tx_done),
.half_word(half_word),
.tx_line(data_line)
);
UART_rx rx (
.clk(clock),
.resetn(~reset),
.cycles_per_databit(uart_cpd),
.rx_line(data_line),
.rx_data(rx_data),
.rx_collecting_data(),
.rx_data_valid(rx_done)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
reset = 1'b1;
start = 1'b0;
half_word = 16'h0000;
user_data_on_line = 1'b0;
user_data_done = 1'b0;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#100 reset = 1'b0;
#100 start = 1'b1;
#102 half_word = 16'h0078;
#102 user_data_on_line = 1'b1;
#105 user_data_on_line = 1'b0;
#122 half_word = 16'h0101;
#122 user_data_on_line = 1'b1;
#125 user_data_on_line = 1'b0;
#142 half_word = 16'h00FF;
#142 user_data_on_line = 1'b1;
#145 user_data_on_line = 1'b0;
#145 user_data_done = 1'b1;
#20000 reset = 1'b1;
end
endmodule
| 7.336225 |
module testingHandleATResponse;
// Inputs
reg clock;
reg reset;
reg start;
reg RFIFO_rd_en;
reg [15:0] half_word;
reg user_data_on_line;
reg user_data_done;
wire [7:0] rx_data;
wire data_line;
wire rx_done;
wire rx_collecting_data;
parameter uart_cpd = 10'd50;
parameter uart_byte_spacing = 10'd12;
// Outputs
wire at_response_flag;
wire [15:0] RFIFO_out;
wire [7:0] RFIFO_wr_count;
wire [6:0] RFIFO_rd_count;
wire [9:0] atr_timer_limit;
wire [1:0] at_curr, at_next;
wire l_atr_timer, rn_atr_timer, atr_timer_done;
// Instantiate the Unit Under Test (UUT)
handle_at_response uut (
.clock(clock),
.reset(reset),
.start(start),
.uart_done(rx_done),
.uart_collecting_data(rx_collecting_data),
.RFIFO_in(rx_data),
.RFIFO_out(RFIFO_out),
.RFIFO_rd_en(RFIFO_rd_en),
.RFIFO_rd_count(RFIFO_rd_count),
.RFIFO_wr_count(RFIFO_wr_count),
.RFIFO_full(RFIFO_full),
.RFIFO_empty(RFIFO_empty),
.uart_byte_spacing(uart_byte_spacing),
.uart_cpd(uart_cpd),
.at_response_flag(at_response_flag)
);
UART_sender_for_testing help (
.clock(clock),
.reset(reset),
.uart_cpd(uart_cpd),
.uart_byte_spacing(uart_byte_spacing),
.user_data_on_line(user_data_on_line),
.user_data_done(user_data_done),
.tx_done(tx_done),
.half_word(half_word),
.tx_line(data_line)
);
UART_rx rx (
.clk(clock),
.resetn(~reset),
.cycles_per_databit(uart_cpd),
.rx_line(data_line),
.rx_data(rx_data),
.rx_collecting_data(rx_collecting_data),
.rx_data_valid(rx_done)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
reset = 1'b1;
start = 1'b0;
user_data_done = 1'b0;
half_word = 16'h00;
user_data_on_line = 1'b0;
RFIFO_rd_en = 1'b0;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#100 reset = 1'b0;
#100 start = 1'b1;
#110 half_word = "OK";
#110 user_data_on_line = 1'b1;
#111 user_data_on_line = 1'b0;
#220 half_word = "AT";
#220 user_data_on_line = 1'b1;
#221 user_data_on_line = 1'b0;
#300 user_data_done = 1'b1;
#5000 RFIFO_rd_en = 1'b1;
#7500 reset = 1'b1;
end
endmodule
| 7.336225 |
module testingISR;
// Inputs
reg clock;
reg resetn;
reg [7:0] stream_active;
// Outputs
wire [7:0] i_s_request;
// Instantiate the Unit Under Test (UUT)
ion_sensor_requester uut (
.clock(clock),
.resetn(resetn),
.stream_active(stream_active),
.i_s_request(i_s_request)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
resetn = 0;
stream_active = 0;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#0 resetn = 1'b1;
#0 stream_active = 8'hFF;
#1000 stream_active = 8'h00;
#2000 stream_active = 8'hAA;
end
endmodule
| 6.799413 |
module TestingKeyboard;
// Inputs
reg CLK;
reg PS2_CLK;
reg PS2_DATA;
// Outputs
wire scan_err;
wire [10:0] scan_code;
wire [3:0] COUNT;
wire TRIG_ARR;
wire [7:0] CODEWORD;
wire [7:0] LED;
// Instantiate the Unit Under Test (UUT)
Keyboard uut (
.CLK(CLK),
.PS2_CLK(PS2_CLK),
.PS2_DATA(PS2_DATA),
.scan_err(scan_err),
.scan_code(scan_code),
.TRIG_ARR(TRIG_ARR),
.COUNT(COUNT),
.CODEWORD(CODEWORD),
.LED(LED)
);
initial begin
CLK = 1;
forever begin
#1 CLK = ~CLK;
end
end
initial begin
// Initialize Inputs
PS2_CLK = 1;
PS2_DATA = 1;
// Wait 100 ns for global reset to finish
#100;
#45 PS2_DATA = 0; //START 0
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //1
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //2
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //3
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //4
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //5
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //6
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //7
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //8
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //PARITY 9
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; // STOP 10
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
// Add stimulus here
#45 PS2_DATA = 0; //START 0
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //1
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //2
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //3
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //4
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //5
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //6
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //7
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //8
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //PARITY 9
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; // STOP 10
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
//BRAKE CODE
#45 PS2_DATA = 0; //START 0
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //1
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //2
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //3
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //4
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //5
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //6
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; //7
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //8
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 0; //PARITY 9
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
#45 PS2_DATA = 1; // STOP 10
#5 PS2_CLK = 0;
#50 PS2_CLK = 1;
end
endmodule
| 6.639893 |
module testingRC;
// Inputs
reg clock;
reg reset;
reg [7:0] tx_data;
reg start;
reg want_at;
reg RFIFO_rd_en;
parameter cpd = 10'd50;
parameter rc_timer_cap = 10'd12;
wire data_line;
// Outputs
wire byte_sent;
wire at_response_flag;
wire [15:0] RFIFO_out;
wire [7:0] RFIFO_wr_count;
wire [6:0] RFIFO_rd_count;
wire ds_sending_flag;
wire [7:0] stream_select;
wire [7:0] commands, operands;
wire l_r_ds_sending_flag, r_r_ds_sending_flag, ds_sending_flag_value, c, n;
wire [1:0] rc_curr, rc_next;
wire [9:0] rc_timer, n_rc_timer;
// Instantiate the Unit Under Test (UUT)
receiver_centre uut (
.clock(clock),
.reset(reset),
.uart_cpd(cpd),
.uart_spacing_limit(rc_timer_cap),
.fpga_rxd(data_line),
.want_at(want_at),
.RFIFO_rd_en(RFIFO_rd_en),
.RFIFO_out(RFIFO_out),
.RFIFO_wr_count(RFIFO_wr_count),
.RFIFO_rd_count(RFIFO_rd_count),
.at_response_flag(at_response_flag),
.stream_select(stream_select),
.ds_sending_flag(ds_sending_flag),
.commands(commands),
.operands(operands),
.l_r_ds_sending_flag(l_r_ds_sending_flag),
.r_r_ds_sending_flag(r_r_ds_sending_flag),
.ds_sending_flag_value(ds_sending_flag_value),
.rc_curr(rc_curr),
.rc_next(rc_next),
.c(c),
.n(n),
.rc_timer(rc_timer),
.n_rc_timer(n_rc_timer)
);
UART_tx santas_little_helper (
.clk(clock),
.resetn(~reset),
.start(start),
.cycles_per_databit(cpd),
.tx_line(data_line),
.tx_data(tx_data),
.tx_done(byte_sent)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
want_at = 1'b0;
RFIFO_rd_en = 1'b0;
tx_data = 8'h00;
start = 1'b0;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#100 reset = 1'b0;
#100 want_at = 1'b1;
#220 tx_data = "O";
#250 start = 1'b1;
#275 start = 1'b0;
#620 tx_data = "K";
#650 start = 1'b1;
#675 start = 1'b0;
#800 RFIFO_rd_en = 1'b1;
#801 RFIFO_rd_en = 1'b0;
#1000 want_at = 1'b0;
#1020 tx_data = 8'h00;
#1021 start = 1'b1;
#1055 start = 1'b0;
#1056 tx_data = 8'h78;
#1056 start = 1'b1;
#1075 start = 1'b0;
#1420 tx_data = 8'h01;
#1450 start = 1'b1;
#1475 start = 1'b0;
end
endmodule
| 6.699752 |
module testingTimer;
// Inputs
reg clock;
reg l_timer;
reg resetn_timer;
parameter timer_cap = 10'd12;
// Outputs
wire timer_done;
// Instantiate the Unit Under Test (UUT)
timer_10bit uut (
.clock(clock),
.resetn_timer(resetn_timer),
.timer_active(l_timer),
.timer_final_value(timer_cap),
.timer_done(timer_done)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
resetn_timer = 1'b0;
l_timer = 1'b0;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#100 resetn_timer = 1'b1;
#100 l_timer = 1'b1;
#200 l_timer = 1'b1;
#300 resetn_timer = 1'b0;
end
endmodule
| 7.474451 |
module testingUARTrx;
// Inputs
reg clock;
reg reset;
reg start;
reg [7:0] tx_data;
// Outputs
wire [7:0] rx_data;
wire data_line;
wire collecting_data;
wire rx_data_valid;
wire tx_done;
wire [3:0] i, n_i;
// parameter cpd = 10'd50;
// parameter timer_cap = 10'd12;
parameter cpd = 10'd11;
parameter timer_cap = 10'd385;
UART_rx uut (
.i (i),
.n_i(n_i),
.clk(clock),
.resetn(~reset),
.cycles_per_databit(cpd),
.rx_line(data_line),
.rx_data(rx_data),
.collecting_data(collecting_data),
.rx_data_valid(rx_data_valid)
);
UART_tx santas_little_helper (
.clk(clock),
.resetn(~reset),
.start(start),
.cycles_per_databit(cpd),
.tx_line(data_line),
.tx_data(tx_data),
.tx_done(tx_done)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
start = 1'b0;
tx_data = 8'h00;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#100 reset = 1'b0;
#100 tx_data = 8'hF0;
#110 start = 1'b1;
#150 start = 1'b0;
#600 tx_data = 8'hE1;
#610 start = 1'b1;
#650 start = 1'b0;
#1100 tx_data = 8'hD2;
#1110 start = 1'b1;
#1150 start = 1'b0;
#1600 tx_data = 8'hC3;
#1610 start = 1'b1;
#1650 start = 1'b0;
#2100 tx_data = 8'hB4;
#2110 start = 1'b1;
#2150 start = 1'b0;
#2600 tx_data = 8'hA5;
#2610 start = 1'b1;
#2650 start = 1'b0;
#3100 tx_data = 8'h96;
#3110 start = 1'b1;
#3150 start = 1'b0;
#3600 tx_data = 8'h87;
#3610 start = 1'b1;
#3650 start = 1'b0;
#4100 tx_data = 8'h78;
#4110 start = 1'b1;
#4150 start = 1'b0;
#4600 tx_data = 8'h69;
#4610 start = 1'b1;
#4650 start = 1'b0;
#5100 tx_data = 8'h5A;
#5110 start = 1'b1;
#5150 start = 1'b0;
#5600 tx_data = 8'h4B;
#5610 start = 1'b1;
#5650 start = 1'b0;
#6100 tx_data = 8'h3C;
#6110 start = 1'b1;
#6150 start = 1'b0;
#6600 tx_data = 8'h2D;
#6610 start = 1'b1;
#6650 start = 1'b0;
#7100 tx_data = 8'h1E;
#7110 start = 1'b1;
#7150 start = 1'b0;
#7600 tx_data = 8'h0F;
#7610 start = 1'b1;
#7650 start = 1'b0;
#7655 reset = 1'b1;
end
endmodule
| 7.386238 |
module testingUARTtx;
// Inputs
reg clock;
reg resetn;
reg start;
reg [7:0] ep01wireIn;
reg [9:0] cpd;
// Outputs
wire fpga_txd;
wire done;
wire l_tx_timer, rn_tx_timer;
wire [2:0] c;
wire [2:0] n;
// Instantiate the Unit Under Test (UUT)
UART_tx uut (
.clk(clock),
.resetn(resetn),
.start(start),
.cycles_per_databit(cpd),
.tx_line(fpga_txd),
.tx_data(ep01wireIn),
.tx_done(done)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
resetn = 0;
ep01wireIn = 8'h00;
start = 0;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#0 ep01wireIn = 8'h45;
#0 resetn = 1'b1;
#10 cpd = 10'h00d;
#50 start = 1'b1;
#150 start = 1'b0;
end
endmodule
| 7.857074 |
module testingUART_sender_for_testing;
// Inputs
reg clock;
reg reset;
reg user_data_on_line;
reg user_data_done;
reg [15:0] half_word;
// Outputs
wire tx_done;
wire tx_line;
// wire [2:0] fbc_curr, fbc_next;
// Instantiate the Unit Under Test (UUT)
UART_sender_for_testing uut (
// .fbc_curr(fbc_curr), .fbc_next(fbc_next),
.clock(clock),
.reset(reset),
.uart_cpd(10'd50),
.uart_byte_spacing(10'd12),
.user_data_on_line(user_data_on_line),
.user_data_done(user_data_done),
.tx_done(tx_done),
.half_word(half_word),
.tx_line(tx_line)
);
always begin
#1 clock = !clock;
end
initial begin
// Initialize Inputs
clock = 0;
reset = 1;
user_data_on_line = 0;
user_data_done = 0;
half_word = 16'd0;
// Wait 100 us for global reset to finish
#100;
// Add stimulus here
#0 reset = 1'b0;
#10 half_word = 16'h4154;
#10 user_data_on_line = 1'b1;
#11 user_data_on_line = 1'b0;
#30 half_word = 16'h6174;
#30 user_data_on_line = 1'b1;
#40 user_data_on_line = 1'b0;
#40 user_data_done = 1'b1;
end
endmodule
| 7.960251 |
module test_interface (
clk,
priv_sda,
priv_scl,
parallel_out,
byte_ready,
sop,
eot
);
input clk, priv_sda, priv_scl;
output [7:0] parallel_out;
wire [8:0] sda_out;
output byte_ready, sop, eot;
i2c_listen priv (
priv_sda,
sda_out,
priv_scl,
clk,
byte_ready,
sop,
eot
);
assign parallel_out = sda_out[8:1];
endmodule
| 6.515982 |
module testing_life ();
localparam N = 8;
reg clk;
reg nrst;
reg [(N*N)-1:0] seeds;
wire [(N*N)-1:0] cells;
wire [N-1:0] wcells[N-1:0];
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
assign wcells[i] = cells[(N*(N-i))-1 : N*(N-1-i)];
end
endgenerate
GameOfLife #(
.N(N)
) itsmylife (
.clk (clk),
.nrst (nrst),
.seeds(seeds),
.cells(cells)
);
always #5 clk = ~clk;
integer x;
initial begin
/*$monitor("%b", wcells);
for(x = 0; x < N; x = x+1) begin
$display("%b", wcells[x]);
end
$monitor("%b\n%b\n%b\n%b\n%b\n%b\n",
cells[(N*N) -1 : N*(N-1)],
cells[(N*(N-1))-1 : N*(N-2)],
cells[(N*(N-2))-1 : N*(N-3)],
cells[(N*(N-3))-1 : N*(N-4)],
cells[(N*(N-4))-1 : N*(N-5)],
cells[(N*(N-5))-1 : N*(N-6)]
);*/
$monitor(
"%b\n%b\n%b\n%b\n%b\n%b\n%b\n%b\n", cells[(N*N)-1 : N*(N-1)], cells[(N*(N-1))-1 : N*(N-2)],
cells[(N*(N-2))-1 : N*(N-3)], cells[(N*(N-3))-1 : N*(N-4)], cells[(N*(N-4))-1 : N*(N-5)],
cells[(N*(N-5))-1 : N*(N-6)], cells[(N*(N-6))-1 : N*(N-7)], cells[(N*(N-7))-1 : N*(N-8)]);
clk <= 0;
nrst <= 0;
seeds <= 64'b01000000_00100000_11100000_00000000_00000000_00000000_00000000_00000000;
//seeds <= 36'b010000_001000_111000_000000_000000_000000;
#7;
nrst <= 1;
#10000;
/*
$display("%b", wcells[0]);
$display("%b", cells[35:30]);
#200;*/
$finish;
end
endmodule
| 6.568681 |
module testing_pc ();
wire [31:0] PC, PCNext, PCPlus4;
reg [31:0] PCTarget;
reg clk, reset, PCSrc;
mux2 #(32) pcnext (
PCNext,
PCPlus4,
PCTarget,
PCSrc
);
pc pc_inst (
PC,
clk,
reset,
PCNext
);
adder pc_plus4 (
PCPlus4,
PC,
32'd4
);
initial begin
forever #10 clk = ~clk;
end
initial begin
clk = 0;
reset = 1;
PCSrc = 0;
PCTarget = 20;
#50 reset = 0;
#60 PCSrc = 1;
#10 PCSrc = 0;
end
endmodule
| 6.947718 |
module testing_reg (
input wire clk,
reset,
input wire a,
b,
output wire c,
output wire seq_reg_tb,
seq_next_tb,
//TestBench signals below
output wire [1:0] state_tb,
output wire [1:0] testing_reg2_tb
//TestBench signals above
);
//state declaration
localparam [1:0] toggleWAIT = 2'b00, toggle1 = 2'b01, toggle2 = 2'b10, toggleDONE = 2'b11;
//signal declaration
reg [1:0] state_reg, state_next;
reg testing_reg1;
reg [1:0] testing_reg2;
reg seq_reg, seq_next;
//FSM
always @(posedge clk, posedge reset)
if (reset) begin
state_reg <= toggleWAIT;
seq_reg <= 0;
end else begin
state_reg <= state_next;
seq_reg <= seq_next;
end
//FSM next-state logic
always @* begin
state_next = state_reg;
testing_reg1 = 0;
testing_reg2 = 0;
seq_next = seq_reg;
case (state_reg)
//
toggleWAIT: begin
if (a) begin
state_next = toggle1;
testing_reg1 = 1;
testing_reg2 = 1;
seq_next = 1;
end else begin
seq_next = 0;
testing_reg1 = 0;
testing_reg2 = 0;
end
end
//
toggle1: begin
if (b) begin
state_next = toggleWAIT;
//testing_reg1=1;
testing_reg2 = 2;
end
end
default: state_next = toggleWAIT;
endcase
end
assign c = testing_reg1;
//TestBench signals below
assign state_tb = state_reg;
assign testing_reg2_tb = testing_reg2;
assign seq_reg_tb = seq_reg;
assign seq_next_tb = seq_next;
//TestBench signals above
endmodule
| 8.333389 |
module testing_reg_tb ();
//---------------------------------------------------------
// inputs to the DUT are reg type
reg CLOCK_50, reset, a, b;
//--------------------------------------------------------
// outputs from the DUT are wire type
wire testing_reg1;
wire [1:0] state_tb;
wire [1:0] testing_reg2_tb;
wire seq_reg_tb, seq_next_tb;
//---------------------------------------------------------
// instantiate the Device Under Test (DUT)
// using named instantiation
testing_reg testing_reg (
.clk(CLOCK_50), //pll to 200mhz
.reset(reset),
.a(a),
.b(b),
.c(testing_reg1),
.testing_reg2_tb(testing_reg2_tb),
.state_tb(state_tb),
.seq_reg_tb(seq_reg_tb),
.seq_next_tb(seq_next_tb)
);
//----------------------------------------------------------
always #10 CLOCK_50 = ~CLOCK_50;
//-----------------------------------------------------------
/*****************************************************************************
* BLOCK 0 -> Reset check *
*****************************************************************************/
// initial blocks are sequential and start at time 0
initial begin
$display($time, " <<BLOCK 0: Starting the Simulation >>");
// at time 0 reset input value
CLOCK_50 = 0;
reset = 0;
a = 0;
b = 0;
//#5 reset = 1;
#500;
// let the simulation run for 500ns
$display($time, " <<BLOCK 0: Simulation Complete >>");
$stop;
end
/*****************************************************************************
* BLOCK 1 -> FSM and Logic test *
*****************************************************************************/
//integer i;
initial begin
#55 $display($time, " << run 1 >>");
a = 1;
#50 b = 1;
//end
end
endmodule
| 6.833693 |
module TestInitializer #(
parameter WAIT_TIME = 100, // How long to wait after reset is deassereted.
parameter V_WAIT_TIME = WAIT_TIME // How long to wait after reset is deassereted.
) (
// These ports are not in any interface
input clk_i, // The mandatory clock, as this is synchronous logic.
input done, // Output used to signal that the masters are done sending.
input rst_i, // The mandatory reset, as this is synchronous logic.
output reg start // Input used to signal that is is ok to start the masters.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
initial begin
start = 0;
@(posedge rst_i); // wait for reset
start = 1;
@(posedge clk_i);
@(posedge clk_i);
@(posedge clk_i);
start = 0; // generate the falling edge
#V_WAIT_TIME
if (done == 1'b0) $display("not done!");
else $display("done high");
$stop;
end
endmodule
| 7.433451 |
module key_gen (
in_key,
rcon,
out_key
);
input [0:127] in_key;
input [0:31] rcon;
output [0:127] out_key;
wire [0:127] out_key;
//shifting operation
wire [0:127] key, key2;
assign key[96:103] = in_key[104:111];
assign key[104:111] = in_key[112:119];
assign key[112:119] = in_key[120:127];
assign key[120:127] = in_key[96:103];
assign key[0:95] = in_key[0:95];
//sub_bytes operation
sbox s1 (
key[96:99],
key[100:103],
key2[96:103]
);
sbox s2 (
key[104:107],
key[108:111],
key2[104:111]
);
sbox s3 (
key[112:115],
key[116:119],
key2[112:119]
);
sbox s4 (
key[120:123],
key[124:127],
key2[120:127]
);
//multiplication with rcon values
//xor with different columns
//out_key is also numbered column wise
//column1
assign out_key[0:7] = in_key[0:7] ^ key2[96:103] ^ rcon[0:7];
assign out_key[8:15] = in_key[8:15] ^ key2[104:111] ^ rcon[8:15];
assign out_key[16:23] = in_key[16:23] ^ key2[112:119] ^ rcon[16:23];
assign out_key[24:31] = in_key[24:31] ^ key2[120:127] ^ rcon[24:31];
//column2
assign out_key[32:39] = in_key[32:39] ^ out_key[0:7];
assign out_key[40:47] = in_key[40:47] ^ out_key[8:15];
assign out_key[48:55] = in_key[48:55] ^ out_key[16:23];
assign out_key[56:63] = in_key[56:63] ^ out_key[24:31];
//column3
assign out_key[64:71] = in_key[64:71] ^ out_key[32:39];
assign out_key[72:79] = in_key[72:79] ^ out_key[40:47];
assign out_key[80:87] = in_key[80:87] ^ out_key[48:55];
assign out_key[88:95] = in_key[88:95] ^ out_key[56:63];
//column4
assign out_key[96:103] = in_key[96:103] ^ out_key[64:71];
assign out_key[104:111] = in_key[104:111] ^ out_key[72:79];
assign out_key[112:119] = in_key[112:119] ^ out_key[80:87];
assign out_key[120:127] = in_key[120:127] ^ out_key[88:95];
endmodule
| 8.515486 |
module testLcd_controller;
// Inputs
reg rst;
reg clk;
reg rs_in;
reg [7:0] data_in;
reg strobe_in;
reg [7:0] period_clk_ns;
// Outputs
wire lcd_e;
wire [3:0] lcd_nibble;
wire lcd_rs;
wire lcd_rw;
wire disable_flash;
wire done;
// Instantiate the Unit Under Test (UUT)
lcd_controller uut (
.rst(rst),
.clk(clk),
.rs_in(rs_in),
.data_in(data_in),
.strobe_in(strobe_in),
.period_clk_ns(period_clk_ns),
.lcd_e(lcd_e),
.lcd_nibble(lcd_nibble),
.lcd_rs(lcd_rs),
.lcd_rw(lcd_rw),
.disable_flash(disable_flash),
.done(done)
);
// Create clock
always begin
#10 clk = ~clk; // Toogle the clock each 10ns (20ns period is 50Mhz)
end
initial begin
// Initialize Inputs
$display($time, " << Starting the Simulation >>");
$monitor("lcd_e=%b,lcd_nibble=%b,done=%b", lcd_e, lcd_nibble, done);
rst = 1;
clk = 0;
rs_in = 0;
data_in = 0;
strobe_in = 0;
period_clk_ns = 20; // Indicate the number of time at each cycle (20 ns in our case)
// Wait for one clock cycle to reset
#20;
rst = 0;
// One advantege over of Verilog over VHDL (Access to internal signals...)
// Like wait until... from Verilog
@(posedge uut.lcd_init_done);
data_in = 65;
#20 strobe_in = 1;
#20 strobe_in = 0;
@(posedge done);
// Finish simulation (on VHDL assert false report...)
$finish;
end
endmodule
| 7.059745 |
module
*
*
* MIT License
*/
module LUATest;
// Inputs
reg [15:0] InputX;
reg [15:0] InputY;
reg Start;
// Outputs
wire [31:0] Address;
wire Ready;
`defClock(Clk, 2);
// Instantiate the Unit Under Test (UUT)
LUA #(
.DATA_WIDTH(16),
.BLOCK_SIZE(10)
) uut (
.Clk(Clk),
.InputX(InputX),
.InputY(InputY),
.Start(Start),
.Address(Address),
.Ready(Ready)
);
`startTest("LUA")
// Initialize Inputs
InputX = 0;
InputY = 0;
Start = 0;
Clk = 0;
#100;
`describe("Test BLOCK_SIZE=10, X=4, Y=5");
Start = 0; wait(Ready == 1);
InputX = 4;
InputY = 5;
Start = 1;
wait(Ready == 0);
Start = 0;
wait(Ready == 1);
`assert(Address, 54);
`endTest
endmodule
| 7.860622 |
module: MapGen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestMapGen;
// Inputs
reg clk;
reg reset;
// Outputs
wire finishedGen;
wire [47:0] logicMap;
// Instantiate the Unit Under Test (UUT)
MapGen uut (
.clk(clk),
.reset(reset),
.finishedGen(finishedGen),
.logicMap(logicMap)
);
always #5 clk = !clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#2000;
reset = 1;
#1000;
reset = 0;
#2000;
reset = 1;
#1000;
reset = 0;
#2000;
reset = 1;
#1000;
reset = 0;
#2000;
reset = 1;
#1000;
reset = 0;
#2000;
$finish;
end
endmodule
| 7.298786 |
module debouncer (
O_reg_0,
PS2Clk_IBUF,
CLK50MHZ_BUFG
);
output O_reg_0;
input PS2Clk_IBUF;
input CLK50MHZ_BUFG;
wire CLK50MHZ_BUFG;
wire Iv;
wire O_i_1_n_0;
wire O_i_2_n_0;
wire O_reg_0;
wire PS2Clk_IBUF;
wire clear;
wire \count[0]_i_1_n_0 ;
wire \count[1]_i_1_n_0 ;
wire \count[2]_i_1_n_0 ;
wire \count[3]_i_1_n_0 ;
wire \count[4]_i_1_n_0 ;
wire [4:0] count_reg;
LUT2 #(
.INIT(4'h6)
) Iv_i_1 (
.I0(PS2Clk_IBUF),
.I1(Iv),
.O (clear)
);
FDRE #(
.INIT(1'b0)
) Iv_reg (
.C (CLK50MHZ_BUFG),
.CE(clear),
.D (PS2Clk_IBUF),
.Q (Iv),
.R (1'b0)
);
LUT6 #(
.INIT(64'h0040000000000000)
) O_i_1 (
.I0(count_reg[2]),
.I1(count_reg[0]),
.I2(count_reg[1]),
.I3(count_reg[3]),
.I4(count_reg[4]),
.I5(O_i_2_n_0),
.O (O_i_1_n_0)
);
LUT2 #(
.INIT(4'h9)
) O_i_2 (
.I0(Iv),
.I1(PS2Clk_IBUF),
.O (O_i_2_n_0)
);
FDRE #(
.INIT(1'b0)
) O_reg (
.C (CLK50MHZ_BUFG),
.CE(O_i_1_n_0),
.D (PS2Clk_IBUF),
.Q (O_reg_0),
.R (1'b0)
);
LUT6 #(
.INIT(64'h4444444444C44444)
) \count[0]_i_1 (
.I0(count_reg[0]),
.I1(O_i_2_n_0),
.I2(count_reg[4]),
.I3(count_reg[3]),
.I4(count_reg[1]),
.I5(count_reg[2]),
.O (\count[0]_i_1_n_0 )
);
LUT6 #(
.INIT(64'h1000FF00FF000000)
) \count[1]_i_1 (
.I0(count_reg[2]),
.I1(count_reg[3]),
.I2(count_reg[4]),
.I3(O_i_2_n_0),
.I4(count_reg[1]),
.I5(count_reg[0]),
.O (\count[1]_i_1_n_0 )
);
LUT6 #(
.INIT(64'h0D00F000F000F000)
) \count[2]_i_1 (
.I0(count_reg[4]),
.I1(count_reg[3]),
.I2(count_reg[2]),
.I3(O_i_2_n_0),
.I4(count_reg[1]),
.I5(count_reg[0]),
.O (\count[2]_i_1_n_0 )
);
LUT6 #(
.INIT(64'h7F00007F80000080)
) \count[3]_i_1 (
.I0(count_reg[1]),
.I1(count_reg[0]),
.I2(count_reg[2]),
.I3(PS2Clk_IBUF),
.I4(Iv),
.I5(count_reg[3]),
.O (\count[3]_i_1_n_0 )
);
LUT6 #(
.INIT(64'h7FFF000080000000)
) \count[4]_i_1 (
.I0(count_reg[3]),
.I1(count_reg[1]),
.I2(count_reg[0]),
.I3(count_reg[2]),
.I4(O_i_2_n_0),
.I5(count_reg[4]),
.O (\count[4]_i_1_n_0 )
);
FDRE #(
.INIT(1'b0)
) \count_reg[0] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[0]_i_1_n_0 ),
.Q (count_reg[0]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \count_reg[1] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[1]_i_1_n_0 ),
.Q (count_reg[1]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \count_reg[2] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[2]_i_1_n_0 ),
.Q (count_reg[2]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \count_reg[3] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[3]_i_1_n_0 ),
.Q (count_reg[3]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \count_reg[4] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[4]_i_1_n_0 ),
.Q (count_reg[4]),
.R (1'b0)
);
endmodule
| 6.564102 |
module game_logic (
\state_reg[0]_0 ,
Q,
D,
E
);
output \state_reg[0]_0 ;
output [0:0] Q;
input [2:0] D;
input [0:0] E;
wire [2:0] D;
wire [0:0] E;
wire [0:0] Q;
wire [2:0] state;
wire \state_reg[0]_0 ;
LUT2 #(
.INIT(4'hE)
) \data[7]_i_4 (
.I0(state[2]),
.I1(state[0]),
.O (\state_reg[0]_0 )
);
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0)
) \state_reg[0] (
.CLR(1'b0),
.D (D[0]),
.G (E),
.GE (1'b1),
.Q (state[0])
);
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b1)
) \state_reg[1] (
.CLR(1'b0),
.D (D[1]),
.G (E),
.GE (1'b1),
.Q (Q)
);
(* XILINX_LEGACY_PRIM = "LD" *)
LDCE #(
.INIT(1'b0)
) \state_reg[2] (
.CLR(1'b0),
.D (D[2]),
.G (E),
.GE (1'b1),
.Q (state[2])
);
endmodule
| 6.517449 |
module: MatchingGame
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestMatchingGame;
// Inputs
reg clk;
reg rst;
reg btnU;
reg btnD;
reg btnL;
reg btnR;
reg btnS;
// Outputs
wire [7:0] rgb;
wire hsync;
wire vsync;
// Instantiate the Unit Under Test (UUT)
MatchingGame uut (
.clk(clk),
.rst(rst),
.btnU(btnU),
.btnD(btnD),
.btnL(btnL),
.btnR(btnR),
.btnS(btnS),
.rgb(rgb),
.hsync(hsync),
.vsync(vsync)
);
always #5 clk = !clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
btnU = 0;
btnD = 0;
btnL = 0;
btnR = 0;
btnS = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#50000;
btnS = 1;
#2600000;
btnS = 0;
#1000;
btnL = 1;
#2600000;
btnL = 0;
#1000;
btnS = 1;
#2600000;
btnS = 0;
#2600000;
rst = 1;
#26000000;
rst = 0;
#26000000;
$finish;
end
endmodule
| 7.932909 |
module testmealy (
Clock,
Resetn,
w,
z
);
input Clock, Resetn, w;
output reg z;
reg y, Y;
parameter A = 0, B = 1;
//Define the next state and output combinational circuits
always @(w, y)
case (y)
A:
if (w) begin
z = 0;
Y = B;
end else begin
z = 0;
Y = A;
end
B:
if (w) begin
z = 1;
Y = B;
end else begin
z = 0;
Y = A;
end
endcase
always @(negedge Resetn, posedge Clock)
if (Resetn == 0) y <= A;
else y <= Y;
endmodule
| 6.591325 |
module
*
* MIT License
*/
module TestMiniCalc
#(
parameter INPUT_BIT_WIDTH = 8,
parameter INSTR_BIT_WIDTH = 4,
parameter CODE_INSTR_NOP = 4'b1111,
parameter CODE_INSTR_ADD_SUB = 4'b0111,
parameter CODE_INSTR_MIN_MAX = 4'b1011,
parameter CODE_INSTR_MUL = 4'b1101,
parameter CODE_INSTR_DIV = 4'b1110
);
// Inputs
`defClock(Clk, 2);
reg [INSTR_BIT_WIDTH-1:0] Instruction;
reg [INPUT_BIT_WIDTH-1:0] InputA;
reg [INPUT_BIT_WIDTH-1:0] InputB;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] OutputA;
wire [INPUT_BIT_WIDTH-1:0] OutputB;
// Instantiate the Unit Under Test (UUT)
MiniCalc uut (
.Clk(Clk),
.Instruction(Instruction),
.InputA(InputA),
.InputB(InputB),
.OutputA(OutputA),
.OutputB(OutputB)
);
`startTest("MiniCalc")
// Initialize Input
Clk = 0;
Instruction = CODE_INSTR_NOP;
InputA = 0;
InputB = 0;
#100;
`describe("Test add/sub operation");
`do_op(CODE_INSTR_ADD_SUB, 6, 3, 9, 3);
`do_op(CODE_INSTR_ADD_SUB, 8, 5, 13, 3);
`describe("Test min/max operation");
`do_op(CODE_INSTR_MIN_MAX, 6, 3, 6, 3);
`do_op(CODE_INSTR_MIN_MAX, 10, 2, 10, 2);
`do_op(CODE_INSTR_MIN_MAX, 3, 11, 11, 3);
`do_op(CODE_INSTR_MIN_MAX, 0, 2, 2, 0);
`describe("Test min/max operation when swapping");
`do_op(CODE_INSTR_MIN_MAX, 8, 5, 8, 5);
`do_op(CODE_INSTR_MIN_MAX, 5, 8, 8, 5);
`describe("Test mul operation");
`do_op(CODE_INSTR_MUL, 6, 3, 18, 0);
`describe("Test nop operation");
`do_op(CODE_INSTR_NOP, 6, 3, 0, 0);
`describe("Test div operation");
`do_op(CODE_INSTR_DIV, 15, 2, 7, 1);
`endTest
endmodule
| 7.131449 |
module
*
*
* MIT License
*/
module TestMinMax
#(
parameter INPUT_BIT_WIDTH = 32
);
// Inputs
`defClock(Clk, 2);
reg [INPUT_BIT_WIDTH-1:0] InputA;
reg [INPUT_BIT_WIDTH-1:0] InputB;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] Max;
wire [INPUT_BIT_WIDTH-1:0] Min;
// Instantiate the Unit Under Test (UUT)
MinMax #(
.INPUT_BIT_WIDTH(INPUT_BIT_WIDTH)
) uut (
.Clk(Clk),
.InputA(InputA),
.InputB(InputB),
.Max(Max),
.Min(Min)
);
`startTest("MinMax")
// Initialize Inputs
Clk = 0;
InputA = 0;
InputB = 0;
#500;
`describe("Test InputA = InputB");
InputA = 12; InputB = 12; #2;
`assert(Max, 12);
`assert(Min, 12);
InputA = 0; InputB = 0; #2;
`assert(Max, 0);
`assert(Min, 0);
`describe("Test InputA > InputB");
InputA = 100; InputB = 0; #2;
`assert(Max, 100);
`assert(Min, 0);
InputA = 1024; InputB = 1023; #2;
`assert(Max, 1024);
`assert(Min, 1023);
`describe("Test InputA < InputB");
InputA = 99; InputB = 100; #2;
`assert(Max, 100);
`assert(Min, 99);
InputA = 15; InputB = 1024; #2;
`assert(Max, 1024);
`assert(Min, 15);
`endTest
endmodule
| 7.860622 |
module PPR_Sim (
Clk,
Starter,
Aout,
Zout
);
input Clk, Starter;
output Aout, Zout;
wire Start;
sigLatch TestStart0 (
Clk,
Starter,
Start
);
reg mode = 0;
reg [15:0] Ctr = 0;
reg [4:0] TimeDiv = 0;
reg A = 0;
reg Z = 0;
assign Aout = A;
assign Zout = Z;
always @(*) begin
if (mode == 0) begin
if (Start == 1) mode = 1;
else mode = 0;
end else begin
if (Ctr == 2048) mode = 0;
else mode = 1;
end
end
//time division
always @(posedge Clk) begin
if (mode == 1) TimeDiv <= TimeDiv + 1;
else TimeDiv <= 0;
end
//z ctrl
always @(posedge Clk) begin
if (Start == 1) Z <= 1;
else if (Ctr == 2048) Z <= 1;
else Z <= 0;
end
//a, ctr ctrl
always @(posedge Clk) begin
if (mode == 1) begin
if (TimeDiv == 5'b11111) begin
A <= ~A;
if (A == 1) Ctr <= Ctr + 1;
end else A <= A;
end else begin
A <= 0;
Ctr <= 0;
end
end
endmodule
| 7.397908 |
module is used to check the data flow in and out of the RX FIFO in Ozy_Janus.v,
through the NWire_xmit in Ozy to the NWire_rcv in Mercury. It should match the
defined FPGA Test Mode data stream. If not it generates
an error called tmc_err which can then be used to flash a code on an LED
*/
`timescale 1 ns/100 ps
module TestModeChecker (rst, clk, data, rdy, tmc_err);
input wire rst;
input wire clk;
input wire [31:0] data;
input wire rdy;
output wire tmc_err;
localparam TMC_IDLE = 0,
TMC_GO = 1;
reg [1:0] tmc_state;
reg [1:0] tmc_state_next;
wire seq_err;
reg [7:0] seq_cnt;
wire [7:0] sp1;
assign tmc_err = (tmc_state != TMC_GO);
always @(posedge clk)
begin
if (rst)
tmc_state <= TMC_IDLE;
else
tmc_state <= tmc_state_next;
if (rst)
seq_cnt <= 3'd1;
else if (tmc_state == TMC_GO)
begin
if (seq_cnt == 8'hFD)
seq_cnt <= 8'h01;
else if (rdy)
seq_cnt <= seq_cnt + 3'd4; // next value we should see when rdy goes high
end
end
assign sp1 = seq_cnt + 1'b1;
assign seq_err = ({8'b0,seq_cnt, 8'b0,sp1} != data) & rdy;
always @*
begin
case(tmc_state)
TMC_IDLE: // wait until we see the 00010002 data
begin
if ((data == 32'h00010002) && rdy)
tmc_state_next = TMC_GO;
else
tmc_state_next = TMC_IDLE;
end
TMC_GO: // continue to check data sequence
begin
if (seq_err)
tmc_state_next = TMC_IDLE;
else
tmc_state_next = TMC_GO;
end
default:
tmc_state_next = TMC_IDLE;
endcase
end
endmodule
| 6.563484 |
module TestModule (
RSTb,
CLK,
REb,
OEb,
CEb,
ADDR,
USER_DATA
);
input RSTb, CLK, REb, OEb, CEb;
input [21:0] ADDR;
output [63:0] USER_DATA;
reg [63:0] internal_data;
wire [15:0] xxx;
assign USER_DATA = (CEb == 0 && OEb == 0) ? {xxx, swap_bits(xxx), ~swap_bits(xxx), ~xxx} : 64'bz;
lfsr16_counter lfsr_counter (
.clk(CLK),
.resetB(RSTb),
.ceB(CEb | REb),
.lfsr_done(),
.lfsr(xxx)
);
/*
always @(posedge CLK or negedge RSTb)
begin
if( RSTb == 0 )
internal_data <= 0;
else
if( REb == 0 )
internal_data <= {10'h15F, ADDR[0], ADDR[1], ADDR[2], ADDR[3], ADDR[4], ADDR[5], ADDR[7], ADDR[7],
ADDR[8], ADDR[9], ADDR[10], ADDR[11], ADDR[12], ADDR[13], ADDR[14], ADDR[15],
ADDR[16], ADDR[17], ADDR[18], ADDR[19], ADDR[20], ADDR[21],
10'h2A0, ADDR};
end
*/
function [15:0] swap_bits;
input [15:0] y;
begin
swap_bits[15] = y[0];
swap_bits[14] = y[1];
swap_bits[13] = y[2];
swap_bits[12] = y[3];
swap_bits[11] = y[4];
swap_bits[10] = y[5];
swap_bits[9] = y[6];
swap_bits[8] = y[7];
swap_bits[7] = y[8];
swap_bits[6] = y[9];
swap_bits[5] = y[10];
swap_bits[4] = y[11];
swap_bits[3] = y[12];
swap_bits[2] = y[13];
swap_bits[1] = y[14];
swap_bits[0] = y[15];
end
endfunction
endmodule
| 6.575788 |
module testmoore (
Clock,
Resetn,
w,
z
);
input Clock, Resetn, w;
output z;
reg [2:1] y, Y;
parameter [2:1] A = 2'b00, B = 2'b01, C = 2'b10;
//Define the next state combinational circuit
always @(w, y)
case (y)
A:
if (w) Y = B;
else Y = A;
B:
if (w) Y = C;
else Y = A;
C:
if (w) Y = C;
else Y = A;
default: Y = 2'bxx;
endcase
//Define the sequential block
always @(negedge Resetn, posedge Clock)
if (Resetn == 0) y <= A;
else y <= Y;
//Define output
assign z = (y == C);
endmodule
| 6.845855 |
module TestMotherboard;
integer clock_count;
reg clk;
reg rst;
reg ps2_clk;
reg ps2_data;
wire hsync;
wire vsync;
wire [3:0] r;
wire [3:0] g;
wire [3:0] b;
Motherboard #(
.CLOCK_DIVIDER(1)
) motherboard (
//// input 100 MHz clock
.clk100Mhz(clk),
.rst(rst),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
//// Horizontal sync pulse for VGA controller
.hsync(hsync),
//// Vertical sync pulse for VGA controller
.vsync(vsync),
//// RGB 4-bit singal that go to a DAC (range 0V <-> 0.7V) to generate a color intensity
.r(r),
.g(g),
.b(b),
.clk_select(1'b1),
.button_clock(1'b1)
);
reg [10:0] payload;
task PS2_TRANSMIT;
input [7:0] send;
integer k;
begin
payload = {
1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0
};
$display("payload = 0b%b", payload);
for (k = 0; k < 11; k = k + 1) begin
CLOCK(2);
ps2_data = payload[k];
ps2_clk = 1;
$display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send,
ps2_data, k);
CLOCK(2);
ps2_clk = 0;
CLOCK(2);
end
ps2_clk = 1;
CLOCK(2);
end
endtask
task RESET;
begin
rst = 0;
clock_count = 0;
clk = 0;
ps2_clk = 1;
ps2_data = 1;
#5 rst = 1;
#5 rst = 0;
clk = 0;
end
endtask
;
task CLOCK;
input [31:0] count;
integer k;
begin
for (k = 0; k < count; k = k + 1) begin
#5 clk = 1;
clock_count = clock_count + 1;
#5 clk = 0;
end
end
endtask
parameter FULL_CYCLE = 32'd5000;
initial begin
#10 #10 RESET;
CLOCK(FULL_CYCLE);
//// Send a A code
PS2_TRANSMIT(`A_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`A_SCAN_CODE);
//// Send a B code
PS2_TRANSMIT(`B_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`B_SCAN_CODE);
//// Send a C code
PS2_TRANSMIT(`C_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`C_SCAN_CODE);
//// Send a D code
PS2_TRANSMIT(`D_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`D_SCAN_CODE);
//// Send a Backspace code
PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
//// Send a D code
PS2_TRANSMIT(`E_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`E_SCAN_CODE);
//// Send a Backspace Code
PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
//// Send a Backspace Code
PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`BACKSPACE_SCAN_CODE);
//// Send a Newline Code
PS2_TRANSMIT(`NEWLINE_SCAN_CODE);
CLOCK(10);
PS2_TRANSMIT(`BREAK_CODE);
CLOCK(10);
PS2_TRANSMIT(`NEWLINE_SCAN_CODE);
CLOCK(20);
//// Rest of the program should run after this.
CLOCK(FULL_CYCLE);
#10 $stop;
#5 $finish;
end
endmodule
| 7.213054 |
module TestMPR #(
parameter bits = 32
) ();
reg clk, we_a, we_b;
reg [2:0] addr_a, addr_b;
reg [bits-1:0] d_in_a, d_in_b;
wire [bits-1:0] q_out_a, q_out_b;
integer i;
MPR #(bits) test (
clk,
we_a,
we_b,
addr_a,
addr_b,
d_in_a,
d_in_b,
q_out_a,
q_out_b
);
always #10 clk = ~clk;
initial begin
clk = 0;
we_a = 0;
addr_a = 3'bx;
d_in_a = {bits{1'bx}};
we_b = 0;
addr_b = 3'bx;
d_in_b = {bits{1'bx}};
$display("Test de scriere a\n");
for (i = 0; i < 4; i = i + 1) begin
@(negedge clk);
#5 addr_a = i;
we_a = 1;
d_in_a = 15 - i;
$display("scriem in memorie [%d] = [%d]", addr_a, d_in_a);
end
;
$display("Test de scriere b\n");
for (i = 4; i < 8; i = i + 1) begin
@(negedge clk);
#5 addr_b = i;
we_b = 1;
d_in_b = 15 - i;
$display("scriem in memorie [%d] = [%d]", addr_b, d_in_b);
end
;
@(negedge clk);
$display("test de citire a");
for (i = 0; i < 4; i = i + 1) begin
@(negedge clk);
#5;
addr_a = i;
we_a = 0;
$display("citim din memorie [%d] = [%d]", addr_a, q_out_a);
end
;
@(negedge clk);
$display("test de citire b");
for (i = 4; i < 8; i = i + 1) begin
@(negedge clk);
#5;
addr_b = i;
we_b = 0;
$display("citim din memorie [%d] = [%d]", addr_b, q_out_b);
end
@(negedge clk);
$display("sciere si citire din aceeasi locatie de memorie la acelasi moment de timp");
#5 addr_a = 5;
we_a = 1;
d_in_a = 99;
@(negedge clk);
$display("sciere si citire din aceeasi locatie de memorie la acelasi moment de timp");
#5 addr_b = 5;
we_b = 1;
d_in_b = 99;
@(negedge clk);
#5 we_a = 1;
addr_a = 3'bx;
d_in_a = {bits{1'bx}};
@(negedge clk);
#5 we_b = 1;
addr_b = 3'bx;
d_in_b = {bits{1'bx}};
@(negedge clk);
$finish;
end
endmodule
| 6.762207 |
module: mul
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testmul;
// Inputs
reg [31:0] data_a;
reg [31:0] data_b;
reg sign;
// Outputs
wire [63:0] data_c;
// Instantiate the Unit Under Test (UUT)
mul uut (
.data_c(data_c),
.data_a(data_a),
.data_b(data_b),
.sign(sign)
);
initial begin
// Initialize Inputs
data_a = 0;
data_b = 0;
sign = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
initial begin
forever #20 data_b = data_b + 1;
end
always begin
#200 data_a = 32'hffff0001;
end
endmodule
| 6.736081 |
module
*
*
* MIT License
*/
module TestClaAdder;
// Inputs
reg [15:0] InputA;
reg [15:0] InputB;
reg Start;
// Outputs
wire [31:0] Product;
wire Ready;
`defClock(Clk, 2);
// Instantiate the Unit Under Test (UUT)
Multiplier #(
.DATA_WIDTH(16)
) uut (
.Clk(Clk),
.InputA(InputA),
.InputB(InputB),
.Start(Start),
.Product(Product),
.Ready(Ready)
);
`startTest("Multiplier")
// Initialize Inputs
InputA = 0;
InputB = 0;
Start = 0;
Clk = 0;
#100;
`describe("Multiply 4*5");
Start = 0; wait(Ready == 1);
InputA = 4;
InputB = 5;
Start = 1;
wait(Ready == 0);
Start = 0;
wait(Ready == 1);
`assert(Product, 20);
`endTest
endmodule
| 7.860622 |
module: mux2x32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testmux32;
// Inputs
reg [31:0] a0;
reg [31:0] a1;
reg s;
// Outputs
wire [31:0] y;
// Instantiate the Unit Under Test (UUT)
mux2x32 uut (
.a0(a0),
.a1(a1),
.s(s),
.y(y)
);
initial begin
// Initialize Inputs
a0 = 10;
a1 = 32;
s = 0;
// Wait 100 ns for global reset to finish
#100;
s = 1;
#100;
s = 0;
// Add stimulus here
end
endmodule
| 6.518985 |
module: mux4x32
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testmux432;
// Inputs
reg [31:0] a0;
reg [31:0] a1;
reg [31:0] a2;
reg [31:0] a3;
reg [1:0] s;
// Outputs
wire [31:0] y;
// Instantiate the Unit Under Test (UUT)
mux4x32 uut (
.a0(a0),
.a1(a1),
.a2(a2),
.a3(a3),
.s(s),
.y(y)
);
initial begin
// Initialize Inputs
a0 = 1;
a1 = 2;
a2 = 3;
a3 = 4;
s = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#100;
s = 1;
#100;
s = 2;
#100;
s = 3;
end
endmodule
| 6.598578 |
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