code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TestMuxDecoder (
output [3:0] Y,
input [3:0] X,
input [1:0] S
);
wire w0, w1;
mux_4_1 mux_4_1_test (
w0,
X,
S
);
and (w1, w0, 1'b0);
decoder_2_4 decoder_2_4_test (
Y,
{w1, 1'b0}
);
endmodule
| 7.398303 |
module testmux_16;
reg[0:15] in;
reg[0:3] sel;
wire out;
mux16to1 mux(out, in sel)l
initial
begin
$monitor("in = %b| sel = %b | out = %b", in, sel, out);
end
initial
begin
in=16'b1000000000000000; sel=4'b0000;
end
endmodule
| 6.523727 |
module nandgate (
output s,
input a,
input b
);
assign s = ~(a & b);
endmodule
| 7.298658 |
module testNeuron (
input clk,
input reset
);
// Parameters
// Wires
wire [30:0] d_index; // <31,0>
// Registers
reg [31:0] bias_mem [0:1000]; // <32,0>
reg [31:0] counter; // <32,0>
reg [31:0] data_mem [0:1000]; // <32,0>
reg [31:0] rout_fptr; // <32,0>
reg [31:0] tap_mem [0:1000]; // <32,0>
// Other
float_24_8 bias; // <1,0>
float_24_8 data; // <1,0>
float_24_8 out; // <1,0>
float_24_8 tap; // <1,0>
////////////////////////////////////////////////////////////////////////////////
// neuron
////////////////////////////////////////////////////////////////////////////////
neuron neuron (
.bias (bias),
.clk (clk),
.data (data),
.out (out),
.reset(reset),
.tap (tap)
);
// Stop the test when the data runs out
always @(posedge clk) begin
if (reset) begin
end else begin
if ((counter == 'd1000)) begin
$finish;
end
end
end
// Delay the bias to line up the data
assign d_index = counter[30:0] - 31'd1;
// Load data
initial begin
$readmemh("/home/andy/IdeaProjects/NeuralHDL/tests/neuron/data/data.hex", data_mem);
end
assign data = data_mem[counter];
// Load tap
initial begin
$readmemh("/home/andy/IdeaProjects/NeuralHDL/tests/neuron/data/tap.hex", tap_mem);
end
assign tap = tap_mem[counter];
// Load bias
initial begin
$readmemh("/home/andy/IdeaProjects/NeuralHDL/tests/neuron/data/bias.hex", bias_mem);
end
assign bias = bias_mem[counter];
// Store Store out
initial begin
rout_fptr = $fopen("/home/andy/IdeaProjects/NeuralHDL/tests/neuron/data/rout.hex", "w");
end
always @(posedge clk) begin
if (reset) begin
end else begin
$fdisplay(rout_fptr, "%h ", out);
end
end
// Counter to Index Test
always @(posedge clk) begin
if (reset) begin
counter <= 32'd0;
end else begin
counter <= counter[31:0] + 32'd1;
end
end
// Initial Statement
initial begin
end
// DUT
endmodule
| 6.747162 |
module TestNewSituation1 ();
reg [23:0] Minisys_Switches;
wire [23:0] Minisys_Lights;
reg Minisys_Clock;
reg [4:0] Minisys_Button;
always begin
#1 Minisys_Clock = ~Minisys_Clock; //ⲿclock
end
TopAll use_main (
Minisys_Switches,
Minisys_Lights,
Minisys_Clock,
Minisys_Button
);
initial begin
Minisys_Clock = 1'b0;
Minisys_Button = 5'b00000;
Minisys_Switches[23:0] = 24'h0;
#100 Minisys_Button = 5'b01000;
#50 Minisys_Button = 5'b00000;
#4000
// ʱ ЧԲˡ
// case 000.
Minisys_Switches[23:0] = 24'h1; // aֵ
#10000 Minisys_Switches[20] = 1; // enterֵ
#10000
// assert: ұߵĵʾ1. ߵĵʾenterڵȴ¡ʾcase0 ʾ
Minisys_Switches[20] = 0; // ½case 0 Ҫ
#10000 Minisys_Switches[20] = 1; //ٴ1.
#100003 Minisys_Switches[20] = 1; //ʱҵӦ1
end
endmodule
| 6.676423 |
module testnorgate;
// ---------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
norgate NOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
end
// ------------------------- parte principal
initial begin
$display("Exercicio 2 - Afonso Spinelli - 266304");
$display("Tabela Verdade para porta NOR - v1.0\n");
$display("~(a | b) = s\n");
//a = 0; b = 0;
#1 $display("~(%b | %b) = %b", a, b, s);
a = 0;
b = 1;
#1 $display("~(%b | %b) = %b", a, b, s);
a = 1;
b = 0;
#1 $display("~(%b | %b) = %b", a, b, s);
a = 1;
b = 1;
#1 $display("~(%b | %b) = %b", a, b, s);
end
endmodule
| 6.695863 |
module notgate (
s,
p
);
output [3:0] s;
input [3:0] p;
assign s[0] = ~p[0];
assign s[1] = ~p[1];
assign s[3:2] = ~p[3:2];
endmodule
| 7.575943 |
module testnotgate;
reg [3:0] a;
wire [3:0] s;
// instancia
notgate NOT1 (
s,
a
);
// parte principal
initial begin
$display("Exemplo 04_02 - xxx yyy zzz - 999999");
$display("Test NOT gate");
$display("\n~a = s\n");
a = 0000;
#1 $display("~%4b = %4b", a, s);
a = 1001;
#1 $display("~%4b = %4b", a, s);
end
endmodule
| 7.480879 |
module or3gate (
output s,
input a,
input b,
input c
);
assign s = (a | b | c);
endmodule
| 7.416224 |
module testor3entgate;
// ---------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
or3gate OR1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
c = 0;
end
// ------------------------- parte principal
initial begin
$display("Exercicio 4 - Afonso Spinelli - 266304");
$display("Tabela Verdade para porta OR com 3 entradas - v1.0\n");
$display("(a | b | c) = s\n");
#1 $display("(%b | %b | %b) = %b", a, b, c, s);
a = 0;
b = 0;
c = 1;
#1 $display("(%b | %b | %b) = %b", a, b, c, s);
a = 0;
b = 1;
c = 0;
#1 $display("(%b | %b | %b) = %b", a, b, c, s);
a = 0;
b = 1;
c = 1;
#1 $display("(%b | %b | %b) = %b", a, b, c, s);
a = 1;
b = 0;
c = 0;
#1 $display("(%b | %b | %b) = %b", a, b, c, s);
a = 1;
b = 0;
c = 1;
#1 $display("(%b | %b | %b) = %b", a, b, c, s);
a = 1;
b = 1;
c = 0;
#1 $display("(%b | %b | %b) = %b", a, b, c, s);
a = 1;
b = 1;
c = 1;
#1 $display("(%b | %b | %b) = %b", a, b, c, s);
end
endmodule
| 7.712876 |
module ougate (
s,
p,
q
);
output s;
input p, q;
assign s = p | q;
endmodule
| 6.763244 |
module nandgate (
s1,
p1,
q1,
r1
);
output s1;
input p1, q1, r1;
assign s = ~(p1 & q1 & r1);
endmodule
| 7.298658 |
module testPal ();
reg clk;
reg [7:0] data;
wire [11:0] rgb;
paletteROM #(
.PALETTEFILE("pal24bit.mem"),
.DEPTH(192)
) pal (
.clk (clk),
.data (data),
.color(rgb)
);
always #1 clk = !clk;
always begin
#4;
data <= data + 1;
end
initial begin
clk = 0;
data = 0;
end
endmodule
| 6.801587 |
module debouncer (
O_reg_0,
PS2Clk_IBUF,
CLK50MHZ_BUFG
);
output O_reg_0;
input PS2Clk_IBUF;
input CLK50MHZ_BUFG;
wire CLK50MHZ_BUFG;
wire Iv;
wire O_i_1_n_1;
wire O_i_2_n_1;
wire O_reg_0;
wire PS2Clk_IBUF;
wire clear;
wire \count[0]_i_1_n_1 ;
wire \count[1]_i_1_n_1 ;
wire \count[2]_i_1_n_1 ;
wire \count[3]_i_1_n_1 ;
wire \count[4]_i_1_n_1 ;
wire [4:0] count_reg;
LUT2 #(
.INIT(4'h6)
) Iv_i_1 (
.I0(PS2Clk_IBUF),
.I1(Iv),
.O (clear)
);
FDRE #(
.INIT(1'b0)
) Iv_reg (
.C (CLK50MHZ_BUFG),
.CE(clear),
.D (PS2Clk_IBUF),
.Q (Iv),
.R (1'b0)
);
LUT6 #(
.INIT(64'h0040000000000000)
) O_i_1 (
.I0(count_reg[2]),
.I1(count_reg[0]),
.I2(count_reg[1]),
.I3(count_reg[3]),
.I4(count_reg[4]),
.I5(O_i_2_n_1),
.O (O_i_1_n_1)
);
LUT2 #(
.INIT(4'h9)
) O_i_2 (
.I0(Iv),
.I1(PS2Clk_IBUF),
.O (O_i_2_n_1)
);
FDRE #(
.INIT(1'b0)
) O_reg (
.C (CLK50MHZ_BUFG),
.CE(O_i_1_n_1),
.D (PS2Clk_IBUF),
.Q (O_reg_0),
.R (1'b0)
);
LUT6 #(
.INIT(64'h4444444444C44444)
) \count[0]_i_1 (
.I0(count_reg[0]),
.I1(O_i_2_n_1),
.I2(count_reg[4]),
.I3(count_reg[3]),
.I4(count_reg[1]),
.I5(count_reg[2]),
.O (\count[0]_i_1_n_1 )
);
LUT6 #(
.INIT(64'h1000FF00FF000000)
) \count[1]_i_1 (
.I0(count_reg[2]),
.I1(count_reg[3]),
.I2(count_reg[4]),
.I3(O_i_2_n_1),
.I4(count_reg[1]),
.I5(count_reg[0]),
.O (\count[1]_i_1_n_1 )
);
LUT6 #(
.INIT(64'h0D00F000F000F000)
) \count[2]_i_1 (
.I0(count_reg[4]),
.I1(count_reg[3]),
.I2(count_reg[2]),
.I3(O_i_2_n_1),
.I4(count_reg[1]),
.I5(count_reg[0]),
.O (\count[2]_i_1_n_1 )
);
LUT6 #(
.INIT(64'h7F00007F80000080)
) \count[3]_i_1 (
.I0(count_reg[1]),
.I1(count_reg[0]),
.I2(count_reg[2]),
.I3(PS2Clk_IBUF),
.I4(Iv),
.I5(count_reg[3]),
.O (\count[3]_i_1_n_1 )
);
LUT6 #(
.INIT(64'h7FFF000080000000)
) \count[4]_i_1 (
.I0(count_reg[3]),
.I1(count_reg[1]),
.I2(count_reg[0]),
.I3(count_reg[2]),
.I4(O_i_2_n_1),
.I5(count_reg[4]),
.O (\count[4]_i_1_n_1 )
);
FDRE #(
.INIT(1'b0)
) \count_reg[0] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[0]_i_1_n_1 ),
.Q (count_reg[0]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \count_reg[1] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[1]_i_1_n_1 ),
.Q (count_reg[1]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \count_reg[2] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[2]_i_1_n_1 ),
.Q (count_reg[2]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \count_reg[3] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[3]_i_1_n_1 ),
.Q (count_reg[3]),
.R (1'b0)
);
FDRE #(
.INIT(1'b0)
) \count_reg[4] (
.C (CLK50MHZ_BUFG),
.CE(1'b1),
.D (\count[4]_i_1_n_1 ),
.Q (count_reg[4]),
.R (1'b0)
);
endmodule
| 6.564102 |
module TEST_PATTERN #(
parameter addr_width = 14,
data_width = 4
) (
input wire clk,
input wire [addr_width-1:0] addr,
output reg [data_width-1:0] dout
);
`ifdef WITH_64K
(* ram_style = "distributed" *) reg [data_width-1:0] pattern[2**addr_width-1:0];
`else
(* ram_style = "block" *) reg [data_width-1:0] pattern[2**addr_width-1:0];
`endif
initial $readmemb("testpattern.bin", pattern);
always @(posedge clk) begin
dout <= pattern[addr];
end
endmodule
| 7.021295 |
module Sync_To_Count (
input i_Clk,
input rst,
input i_HSync,
input i_VSync,
output reg o_HSync = 0,
output reg o_VSync = 0,
output reg [10:0] o_Col_Count = 0,
output reg [10:0] o_Row_Count = 0
);
wire w_Frame_Start;
// Register syncs to align with output data.
always @(posedge i_Clk) begin
o_VSync <= i_VSync;
o_HSync <= i_HSync;
end
// Keep track of Row/Column counters.
always @(posedge i_Clk) begin
if (w_Frame_Start) begin
o_Row_Count <= 0;
end else begin
if (h_Frame_Start) begin
o_Col_Count <= 0;
o_Row_Count <= o_Row_Count + 1;
end else begin
o_Col_Count <= o_Col_Count + 1;
end
end
end
// Vertical sync resets the module
assign w_Frame_Start = (~o_VSync & i_VSync);
assign h_Frame_Start = (~o_HSync & i_HSync);
endmodule
| 7.118986 |
module testPC (
clock,
jumpValue,
branch,
imPC,
thisPC,
nextPC
);
input jumpValue, branch, clock;
input [31:0] imPC;
output [31:0] thisPC, nextPC;
//initialize PC
wire PCSrc;
// wire [31:0] nextJumpPC; //you could directly save it into latch input
wire [31:0] NextPC; //thisPC,
//chose input into the pc
assign nextPC = PCSrc ? imPC : NextPC;
PC_register pc (
clock,
1'b1,
1'b0,
thisPC,
nextPC
);
wire [31:0] currentPC = thisPC;
//calculate nextPC
wire of;
wire [31:0] im1 = 32'b1;
CLA_32bit addPC (
currentPC,
im1,
1'b0,
NextPC,
of
);
//get the instruction from imem
// assign address_imem = currentPC[11:0];
// wire [31:0] instruction = q_imem;
and andBranch (PCSrc, jumpValue, branch);
endmodule
| 6.841887 |
module testpc4_sim ();
reg clk, clrn, e;
wire [31:0] pc;
wire [31:0] pc4;
TextPC4 test (
clk,
clrn,
e,
pc,
pc4
);
reg [31:0] i;
always begin
clk = 0;
e = 0;
clrn = 1;
#5;
clrn = 0;
#5;
clrn = 1;
clk = 1;
#20;
clk = 0;
#5;
clk = 1;
#5;
clk = 0;
i = 0;
e = 1;
while (i == 32'b0) #5 clk = ~clk;
end
endmodule
| 7.415504 |
module TestPIC16C57 ();
reg clk;
reg rst;
wire [`IO_A_WIDTH - 1:0] portAIO;
wire [`IO_B_WIDTH - 1:0] portBIO;
wire [`IO_C_WIDTH - 1:0] portCIO;
reg [3:0] stage;
reg [`IO_B_WIDTH - 1:0] value1;
reg [`IO_C_WIDTH - 1:0] value2;
assign portBIO = (stage == `STAGE_RESULTH || stage == `STAGE_RESULTV) ? 8'hzz : value1;
assign portCIO = (stage == `STAGE_RESULTH || stage == `STAGE_RESULTV) ? 8'hzz : value2;
reg [`IO_C_WIDTH - 1:0] portAPrev;
initial begin
$init;
clk = 1;
rst = 1;
#0.5 rst = 0; // synchronous active-high reset
portAPrev = 0;
stage = `STAGE_INIT;
// $display("init stage");
// #2000000 $stop();
end
always begin
#5 clk = ~clk;
end
always @(portAIO or portCIO or portBIO) begin
if (portAPrev != portAIO) begin // on port a value chage
portAPrev = portAIO;
if (stage == `STAGE_INIT) begin
if (portAIO == `SIGNAL_CHECK) begin
value1 = $finished;
if (value1 == 8'hFF) begin
$display("==== END ====");
#1000 $stop;
end else begin
stage = `STAGE_READ;
// $display("read stage");
end
end
end else if (stage == `STAGE_READ) begin
if (portAIO == `SIGNAL_READY) begin
value1 = $readNextAdjacentPixel;
end else if (portAIO == `SIGNAL_RESULTH) begin
// $display("result h stage");
stage = `STAGE_RESULTH;
end
end else if (stage == `STAGE_RESULTH) begin
if (portAIO == `SIGNAL_READY) begin
// $printPortOutput({portBIO, portCIO});
$storeConvolH({portBIO, portCIO});
end else if (portAIO == `SIGNAL_RESULTV) begin
// $display("result v stage");
stage = `STAGE_RESULTV;
end
end else if (stage == `STAGE_RESULTV) begin
if (portAIO == `SIGNAL_READY) begin
// $printPortOutput({portBIO, portCIO});
$storeConvolV({portBIO, portCIO});
$storePixel;
end else if (portAIO == `SIGNAL_CHECK) begin
// $display("checking end...");
value1 = $finished;
if (value1 == 8'hFF) begin
$display("==== END ====");
#1000 $stop;
end else begin
stage = `STAGE_READ;
// $display("read stage");
end
end
end
end
end
PIC16C57 duv (
.clk(clk),
.rst(rst),
.portAIO(portAIO),
.portBIO(portBIO),
.portCIO(portCIO)
);
endmodule
| 6.921519 |
module testProject (
input wire [3:0] a,
input wire [3:0] b,
output [3:0] z
);
assign z[0] = a[0] & b[0];
assign z[1] = a[1] | b[1];
assign z[2] = ~(a[2] & b[2]);
assign z[3] = a[3] ^ b[3];
endmodule
| 6.716973 |
module testqflop;
reg data, rst;
wire clk, ack, out;
reg expected;
q_flop qf (
.rst (rst),
.clk (clk),
.data(data),
.ack (ack),
.out (out)
);
q_clock qc (
.rst(rst),
.clk(clk),
.ack(ack)
);
initial begin
$dumpfile("testqflop.vcd");
$dumpvars(0, testqflop);
#0 rst = 1;
data = 1;
expected = 1;
#10 rst = 0;
data = 1;
expected = 1;
#10 rst = 0;
data = 0;
expected = 0;
#10 rst = 0;
data = 1;
expected = 1;
#10 rst = 0;
data = 0;
expected = 0;
end
initial
$monitor(
"[%d] data=%b clk=%b rst=%b ack=%b out=%b, expected out=%b",
$time,
data,
clk,
rst,
ack,
out,
expected
);
endmodule
| 6.688958 |
module vc_TestRandDelaySink #(
parameter p_msg_nbits = 1,
parameter p_num_msgs = 1024
) (
input logic clk,
input logic reset,
// Max delay input
input logic [31:0] max_delay,
// Sink message interface
input logic val,
output logic rdy,
input logic [p_msg_nbits-1:0] msg,
// Goes high once all sink data has been received
output logic done
);
//----------------------------------------------------------------------
// Test random delay
//----------------------------------------------------------------------
logic sink_val;
logic sink_rdy;
logic [p_msg_nbits-1:0] sink_msg;
vc_TestRandDelay #(p_msg_nbits) rand_delay (
.clk (clk),
.reset(reset),
.max_delay(max_delay),
.in_val(val),
.in_rdy(rdy),
.in_msg(msg),
.out_val(sink_val),
.out_rdy(sink_rdy),
.out_msg(sink_msg)
);
//----------------------------------------------------------------------
// Test sink
//----------------------------------------------------------------------
vc_TestSink #(p_msg_nbits, p_num_msgs) sink (
.clk (clk),
.reset(reset),
.val(sink_val),
.rdy(sink_rdy),
.msg(sink_msg),
.done(done)
);
//----------------------------------------------------------------------
// Line Tracing
//----------------------------------------------------------------------
logic [`VC_TRACE_NBITS_TO_NCHARS(p_msg_nbits)*8-1:0] msg_str;
`VC_TRACE_BEGIN
begin
$sformat(msg_str, "%x", msg);
vc_trace.append_val_rdy_str(
trace_str, val, rdy, msg_str
);
end
`VC_TRACE_END
endmodule
| 7.617553 |
module vc_TestRandDelaySource #(
parameter p_msg_nbits = 1,
parameter p_num_msgs = 1024
) (
input logic clk,
input logic reset,
// Max delay input
input logic [31:0] max_delay,
// Source message interface
output logic val,
input logic rdy,
output logic [p_msg_nbits-1:0] msg,
// Goes high once all source data has been issued
output logic done
);
//----------------------------------------------------------------------
// Test source
//----------------------------------------------------------------------
logic src_val;
logic src_rdy;
logic [p_msg_nbits-1:0] src_msg;
vc_TestSource #(p_msg_nbits, p_num_msgs) src (
.clk (clk),
.reset(reset),
.val(src_val),
.rdy(src_rdy),
.msg(src_msg),
.done(done)
);
//----------------------------------------------------------------------
// Test random delay
//----------------------------------------------------------------------
vc_TestRandDelay #(p_msg_nbits, p_max_delay_nbits) rand_delay (
.clk (clk),
.reset(reset),
.max_delay(max_delay),
.in_val(src_val),
.in_rdy(src_rdy),
.in_msg(src_msg),
.out_val(val),
.out_rdy(rdy),
.out_msg(msg)
);
//----------------------------------------------------------------------
// Line Tracing
//----------------------------------------------------------------------
logic [`VC_TRACE_NBITS_TO_NCHARS(p_msg_nbits)*8-1:0] msg_str;
`VC_TRACE_BEGIN
begin
$sformat(msg_str, "%x", msg);
vc_trace.append_val_rdy_str(
trace_str, val, rdy, msg_str
);
end
`VC_TRACE_END
endmodule
| 7.617553 |
module vc_TestRandDelayUnorderedSink #(
parameter p_msg_nbits = 1,
parameter p_num_msgs = 1024
) (
input logic clk,
input logic reset,
// Max delay input
input logic [31:0] max_delay,
// Sink message interface
input logic val,
output logic rdy,
input logic [p_msg_nbits-1:0] msg,
// Goes high once all sink data has been received
output logic done
);
//----------------------------------------------------------------------
// Test random delay
//----------------------------------------------------------------------
logic sink_val;
logic sink_rdy;
logic [p_msg_nbits-1:0] sink_msg;
vc_TestRandDelay #(p_msg_nbits) rand_delay (
.clk (clk),
.reset(reset),
.max_delay(max_delay),
.in_val(val),
.in_rdy(rdy),
.in_msg(msg),
.out_val(sink_val),
.out_rdy(sink_rdy),
.out_msg(sink_msg)
);
//----------------------------------------------------------------------
// Test sink
//----------------------------------------------------------------------
vc_TestUnorderedSink #(p_msg_nbits, p_num_msgs) sink (
.clk (clk),
.reset(reset),
.val(sink_val),
.rdy(sink_rdy),
.msg(sink_msg),
.done(done)
);
//----------------------------------------------------------------------
// Line Tracing
//----------------------------------------------------------------------
logic [`VC_TRACE_NBITS_TO_NCHARS(p_msg_nbits)*8-1:0] msg_str;
`VC_TRACE_BEGIN
begin
$sformat(msg_str, "%x", msg);
vc_trace.append_val_rdy_str(
trace_str, val, rdy, msg_str
);
end
`VC_TRACE_END
endmodule
| 7.617553 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
| 7.868877 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
| 8.40589 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
| 8.40589 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
| 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data(coreir_commonlib_mux2x1_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);
assign O = coreir_commonlib_mux2x1_inst0_out;
endmodule
| 7.639545 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
| 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data(coreir_commonlib_mux2x1_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);
assign O = coreir_commonlib_mux2x1_inst0_out;
endmodule
| 7.639545 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
| 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module commonlib_muxn__N2__width1 (
input [0:0] in_data[1:0],
input [0:0] in_sel,
output [0:0] out
);
wire [0:0] _join_out;
coreir_mux #(
.width(1)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux2xOutBits1 (
input [0:0] I0,
input [0:0] I1,
input S,
output [0:0] O
);
wire [0:0] coreir_commonlib_mux2x1_inst0_out;
wire [0:0] coreir_commonlib_mux2x1_inst0_in_data[1:0];
assign coreir_commonlib_mux2x1_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x1_inst0_in_data[0] = I0;
commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0 (
.in_data(coreir_commonlib_mux2x1_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x1_inst0_out)
);
assign O = coreir_commonlib_mux2x1_inst0_out;
endmodule
| 7.639545 |
module TestRegbit ();
reg CLK;
always #25 CLK = ~CLK;
wire q1;
wire q2;
wire [7:0] full_q;
reg reg_d;
reg [7:0] regFull_d;
reg Load;
regbit reg1 (
.clk(CLK),
.cclk(~CLK),
.d(reg_d),
.ld(Load),
.q(q1)
);
regbit regFull[7:0] (
.clk(CLK),
.cclk(~CLK),
.d(regFull_d),
.ld(Load),
.q(full_q)
);
Fair_regbit reg2 (
.clk(CLK),
.cclk(~CLK),
.d(reg_d),
.ld(Load),
.q(q2)
);
always @(posedge CLK) begin
end
initial begin
$display(
"Check the waves for different implementations of regbit. We need to understand the `ld` signal negedge effect.");
CLK <= 1'b0;
$dumpfile("TestRegbit.vcd");
$dumpvars(0, reg1);
$dumpvars(1, reg2);
$dumpvars(2, regFull[0].d);
$dumpvars(3, regFull[0].q);
// Keep
reg_d <= 0;
regFull_d <= 0;
Load <= 0;
repeat (2) @(posedge CLK);
// Load 1
reg_d <= 1;
regFull_d <= 8'haa;
Load <= 1;
repeat (1) @(posedge CLK);
Load <= 0;
repeat (1) @(posedge CLK);
// Load 0
reg_d <= 0;
regFull_d <= 8'h55;
Load <= 1;
repeat (1) @(posedge CLK);
Load <= 0;
repeat (1) @(posedge CLK);
$finish;
end
endmodule
| 7.440739 |
module testRegfile ();
wire [31:0] now_pc;
wire [31:0] instruction;
wire [31:0] next_pc;
wire MemtoReg, RegWrite;
wire [2:0] MemRead;
wire [1:0] MemWrite;
wire [4:0] Aluop;
wire jalr;
wire Alusrc1, Alusrc2;
wire Add4;
reg clk, rstn;
wire [31:0] imm;
wire Branch;
wire [4:0] reg1 = instruction[19:15];
wire [4:0] reg2 = instruction[24:20];
wire [4:0] reg_dest = instruction[11:7];
wire [31:0] dataToWrite;
wire [31:0] outData1;
wire [31:0] outData2; //from register
wire [31:0] src2;
wire [3:0] operation;
wire [31:0] result;
wire zero;
wire [6:0] Func7 = instruction[31:25];
wire [2:0] Func3 = instruction[14:12];
wire [31:0] readOutData; //from memory
initial begin
clk = 1;
rstn = 0;
//rstn=1'b1;
end
always #30 clk = ~clk;
pc_adder testpc_adder (
.now_pc(now_pc),
.imm(imm),
.readData1(outData1),
.Branch(Branch),
.zero(zero),
.jalr(jalr),
.next_pc(next_pc)
);
Instruction_Mem inst_mem (
.pc(now_pc),
.instruction(instruction)
);
PC testPC (
.clk(clk),
.rstn(rstn),
.next_pc(next_pc),
.now_pc(now_pc)
);
control testcontrol (
.opcode(instruction[6:0]),
.func7(instruction[31:25]),
.func3(instruction[14:12]),
.Alusrc1(Alusrc1),
.Alusrc2(Alusrc2),
.MemtoReg(MemtoReg),
.RegWrite(RegWrite),
.MemRead(MemRead),
.MemWrite(MemWrite),
.Branch(Branch),
.Add4(Add4),
.jalr(jalr),
.Aluop(Aluop)
);
Imm_Generator testimm_gen (
.instruction(instruction),
.imm_out(imm)
);
Registers testReg (
.clk(clk),
.reg1(reg1),
.reg2(reg2),
.reg_dest(reg_dest),
.dataToWrite(dataToWrite),
.outData1(outData1),
.outData2(outData2)
);
endmodule
| 7.117988 |
module testRegister;
reg clk;
reg rst;
reg en;
reg [15:0] in;
wire [15:0] out;
register reg1 (
.clk(clk),
.en (en),
.in (in),
.out(out),
.rst(rst)
);
always #5 clk = !clk;
initial begin
$dumpfile("../test.vcd");
$dumpvars;
end
initial begin
rst = 0;
clk = 0;
en = 0;
in = 16'h0000;
#10 rst = 1;
#10 rst = 0;
#10 in = 16'h1234;
#10 en = 1;
#10 en = 0;
#20 in = 16'h5678;
#10 en = 1;
#20 in = 16'h9ABC;
#10 in = 16'hDEF0;
#10 en = 0;
#10 rst = 1;
#20 $finish;
end
endmodule
| 7.28777 |
module
*
*
* MIT License
*/
module TestRegMux4
#(
parameter INPUT_BIT_WIDTH = 8,
parameter BUS_WIDTH = 2
);
// Inputs
reg [INPUT_BIT_WIDTH-1:0] InputA;
reg [INPUT_BIT_WIDTH-1:0] InputB;
reg [INPUT_BIT_WIDTH-1:0] InputC;
reg [INPUT_BIT_WIDTH-1:0] InputD;
reg [BUS_WIDTH-1:0] Select;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] Output;
// Instantiate the Unit Under Test (UUT)
RegMux4 uut (
.InputA(InputA),
.InputB(InputB),
.InputC(InputC),
.InputD(InputD),
.Select(Select),
.Output(Output)
);
`startTest("RegMux4")
// Initialize Inputs
InputA = 0;
InputB = 0;
InputC = 0;
InputD = 0;
Select = 0;
#100;
`describe("Test small const inputs switching");
InputA = 42;
InputB = 15;
InputC = 2;
InputD = 0;
Select = 0;
`do_select(0, 42);
`do_select(1, 15);
`do_select(2, 2);
`do_select(3, 0);
`endTest
endmodule
| 7.860622 |
module TESTROM #(
parameter length = 32,
parameter DATA_LENGTH = 256,
parameter ROMFILE = "TESTDATA.txt"
) (
input i_clk,
input [9:0] i_addr,
output reg [2*length-1:0] o_data
);
reg [2*length-1:0] mem[0:DATA_LENGTH-1];
initial begin
$readmemh(ROMFILE, mem);
end
always @(posedge i_clk) begin
o_data <= mem[i_addr];
end
endmodule
| 7.440455 |
module testrotor ();
reg [2:0] rotor_type_3 = 3'b010;
reg [2:0] rotor_type_2 = 3'b001;
reg [4:0] rotor_start_3 = 5'b00000;
reg [4:0] rotor_start_2 = 5'b00000;
reg [4:0] rotor_start_1 = 5'b00000;
reg [4:0] ring_position_3 = 5'b00000;
reg [4:0] ring_position_2 = 5'b00000;
reg [4:0] ring_position_1 = 5'b00000;
reg reflector_type = 1'b0;
reg i_clock = 0;
reg reset;
reg rotate = 0;
wire [4:0] rotor1;
wire [4:0] rotor2;
wire [4:0] rotor3;
integer i;
rotor rotorcontrol (
.clock(i_clock),
.rotor1(rotor1),
.rotor2(rotor2),
.rotor3(rotor3),
.reset(reset),
.rotate(rotate),
.rotor_type_2(rotor_type_2),
.rotor_type_3(rotor_type_3),
.rotor_start_1(rotor_start_1),
.rotor_start_2(rotor_start_2),
.rotor_start_3(rotor_start_3)
);
always #(5) i_clock <= !i_clock;
initial begin
$dumpfile("testrotor.vcd");
$dumpvars(0, testrotor);
#5 reset = 1;
#10 reset = 0;
for (i = 0; i < 128; i = i + 1) begin
#10 rotate = 1;
#10 rotate = 0;
#20 $display("Rotors [%c] [%c] [%c]", rotor1 + 65, rotor2 + 65, rotor3 + 65);
end
#10 $finish;
end
endmodule
| 6.886134 |
module writer
# (parameter WIDTH=32)
(input clk,
input reset,
input full,
input almost_full,
input [1:0] id,
input [1:0] to,
input disableme,
output reg [WIDTH-1:0] dataOut,
output reg write);
//dataOut from writer is dataIn for fifo
//[disableme] disable =1, do not write.
reg [10:0] count;
reg [2:0] east;
reg [2:0] west;
reg [2:0] local;
always @ (posedge clk, posedge reset) begin
if (reset) begin
dataOut <=0;
write <=0;
count <=0;
east=2'b00;
west=2'b01;
local=2'b10;
end
else begin
if ((write & almost_full)|(~write & full)| disableme) // note that just checking for full should be fine
write <=1'b0;
else begin
write <= 1'b1;
//dataOut[0]=1, isValid
//dataOut[2:1] 00 East, 01 West, 10 local
dataOut <= {count,id,to,1'b1}; //write to the [to] router
//dataOut <= 16'b0000000000000101;
count <= count + 1;
//$display($time,"dataOut=%b",dataOut);
end
end
end
endmodule
| 6.99624 |
module writer
# (parameter WIDTH=32)
(input clk,
input reset,
input full,
input almost_full,
input [1:0] id,
input [1:0] to,
input disableme,
output reg [WIDTH-1:0] dataOut,
output reg write);
//dataOut from writer is dataIn for fifo
//[disableme] disable =1, do not write.
reg [10:0] count;
reg [2:0] east;
reg [2:0] west;
reg [2:0] local;
always @ (posedge clk, posedge reset) begin
if (reset) begin
dataOut <=0;
write <=0;
count <=0;
east=2'b00;
west=2'b01;
local=2'b10;
end
else begin
if ((write & almost_full)|(~write & full)| disableme) // note that just checking for full should be fine
write <=1'b0;
else begin
write <= 1'b1;
dataOut <= {count,id,to,1'b1}; //write to the [to] router
//dataOut <= 16'b0000000000000101;
count <= count + 1;
//$display($time,"dataOut=%b",dataOut);
end
end
end
endmodule
| 6.99624 |
module testSAPone;
wire [ 7:0] SAP_out;
wire [11:0] con;
wire [ 7:0] bus;
// wire clk_out, clr_out;
reg clk, clr_;
always #5 clk = ~clk;
SAPone sapone1 (
.SAP_out(SAP_out),
.con(con),
.bus(bus),
// .clk_out(clk_out),
// .clr_out(clr_out),
.clk(clk),
.clr_(clr_)
);
// PC pc1(bus[3:0], clk, clr_, cp, ep);
// MAR mar1(mar, clk, lm_, bus[3:0]);
initial begin
clk = 0;
clr_ = 0;
#10 clr_ = 1;
#990 $stop;
end
endmodule
| 6.731384 |
module/SinglePulser.v"
`include "../module/SevenSegment.v"
module testSegment(
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output numsl0,
output numsl1,
output numsl2,
output numsl3,
input clk,
input dp1_raw);
wire dp1;
reg [3:0] num;
reg [9:0] clkcount;
wire clktrigger;
assign clktrigger = clkcount[9];
initial begin
num = 0;
clkcount = 0;
end
SinglePulser sp1(.q(dp1), .d(dp1_raw), .clk(clktrigger));
SevenSegment svseg(a,b,c,d,e,f,g,numsl0,numsl1,numsl2,numsl3,clk,0,4,3,2,num);
always @(posedge clk) begin
clkcount = clkcount + 1;
end
always @(posedge clktrigger) begin
if(dp1) begin
num = num + 1;
end
end
endmodule
| 6.714526 |
module TestSegmentLedHexDecoder;
// Inputs
reg [3:0] HexDigit;
// Outputs
wire SegmentA;
wire SegmentB;
wire SegmentC;
wire SegmentD;
wire SegmentE;
wire SegmentF;
wire SegmentG;
reg [3:0] HexDigitOutput;
// Instantiate the Unit Under Test (UUT)
SegmentLedHexDecoder uut (
.HexDigit(HexDigit),
.Segments({
SegmentG, SegmentF, SegmentE, SegmentD, SegmentC, SegmentB, SegmentA
})
);
// Encoder for led digit -> hex transformation
SegmentLedHexEncoder encoder (
.HexDigit(HexDigitOutput),
.Segments({
SegmentG, SegmentF, SegmentE, SegmentD, SegmentC, SegmentB, SegmentA
})
);
`startTest("SegmentLedHexDecoder")
// Initialize Inputs
#100;
`describe("Render digit 0");
HexDigit = 0; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 1");
HexDigit = 1; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 1");
HexDigit = 2; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 3");
HexDigit = 3; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 4");
HexDigit = 4; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 5");
HexDigit = 5; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 6");
HexDigit = 6; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 7");
HexDigit = 7; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 8");
HexDigit = 8; #2;
`assert(HexDigitOutput, HexDigit);
`describe("Render digit 9");
HexDigit = 9; #2;
`assert(HexDigitOutput, HexDigit);
`endTest
endmodule
| 6.832008 |
module testShift ();
wire [1:0] q1, q2;
reg clock, d;
shiftA s1 (
q1,
clock,
d
);
shiftB s2 (
q2,
clock,
d
);
always #10 clock = ~clock;
initial begin
#0 clock = 0;
d = 0;
#5 d = 1;
#35 d = 0;
#50 $finish;
end
always #8 d = ~d;
endmodule
| 6.545942 |
module
*
*
* MIT License
*/
module TestSignAddSub
#(
parameter INPUT_BIT_WIDTH = 8
);
// Inputs
`defClock(Clk, 2);
reg signed [INPUT_BIT_WIDTH-1:0] InputA;
reg signed [INPUT_BIT_WIDTH-1:0] InputB;
reg AddSubMode;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] Result;
// Instantiate the Unit Under Test (UUT)
SignAddSub uut (
.AddSubMode(AddSubMode),
.InputA(InputA),
.InputB(InputB),
.Clk(Clk),
.Result(Result)
);
`startTest("SignAddSub");
// Initialize Inputs
AddSubMode = 0;
InputA = 0;
InputB = 0;
Clk = 0;
#100;
`describe("Test 20 +/- 8");
`do_add_sub(20, 8);
`describe("Test 100 +/- 100");
`do_add_sub(100, 100);
`describe("Test 0 +/- 0");
`do_add_sub(0, 0);
`endTest
endmodule
| 7.860622 |
module
*
*
* MIT License
*/
module TestSignDivider
#(
parameter INPUT_BIT_WIDTH = 8
);
// Inputs
`defClock(Clk, 2);
reg [INPUT_BIT_WIDTH-1:0] Dividend;
reg [INPUT_BIT_WIDTH-1:0] Divider;
reg Sign;
// Outputs
wire Ready;
wire [INPUT_BIT_WIDTH-1:0] Quotient;
wire [INPUT_BIT_WIDTH-1:0] Remainder;
// Instantiate the Unit Under Test (UUT)
SignDivider uut (
.Ready(Ready),
.Quotient(Quotient),
.Remainder(Remainder),
.Dividend(Dividend),
.Divider(Divider),
.Sign(Sign),
.Clk(Clk)
);
`startTest("SignDivider");
// Initialize Inputs
Dividend = 0;
Divider = 0;
Sign = 0;
Clk = 0;
#100;
`describe("Test 13 / 2");
`do_div(13, 2);
`describe("Test 69 / 42");
`do_div(69, 42);
`describe("Test 255 / 5");
`do_div(255, 5);
`describe("Test 77 / 1");
`do_div(77, 1);
`describe("Test 150 / 150");
`do_div(150, 150);
`endTest
endmodule
| 7.860622 |
module
*
*
* MIT License
*/
module TestSimpleALU
#(
parameter INPUT_BIT_WIDTH = 8,
parameter INSTR_BIT_WIDTH = 5,
parameter FLAGS_COUNT = 1,
parameter CODE_INSTR_NOP = 5'b00000,
parameter CODE_INSTR_ADD = 5'b00001,
parameter CODE_INSTR_SUB = 5'b00010,
parameter CODE_INSTR_MUL = 5'b00011,
parameter CODE_INSTR_DIV = 5'b00100,
parameter CODE_INSTR_SHL = 5'b00101,
parameter CODE_INSTR_SHR = 5'b00110,
parameter CODE_INSTR_ROL = 5'b00111,
parameter CODE_INSTR_ROR = 5'b01000,
parameter CODE_INSTR_AND = 5'b01001,
parameter CODE_INSTR_XOR = 5'b01011,
parameter CODE_INSTR_OR = 5'b01101,
parameter CODE_INSTR_NAND = 5'b01110,
parameter CODE_INSTR_XNOR = 5'b01111,
parameter CODE_INSTR_GTH = 5'b10000,
parameter CODE_INSTR_EQU = 5'b10001
);
// Inputs
`defClock(Clk, 2);
reg [INSTR_BIT_WIDTH-1:0] Instruction;
reg [INPUT_BIT_WIDTH-1:0] InputA;
reg [INPUT_BIT_WIDTH-1:0] InputB;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] ResultA;
wire [INPUT_BIT_WIDTH-1:0] ResultB;
wire [FLAGS_COUNT-1:0] Flags;
wire Ready;
// Instantiate the Unit Under Test (UUT)
SimpleALU uut (
.Clk(Clk),
.Instruction(Instruction),
.InputA(InputA),
.InputB(InputB),
.ResultA(ResultA),
.ResultB(ResultB),
.Flags(Flags),
.Ready(Ready)
);
`startTest("SimpleALU")
// Initialize Inputs
Clk = 0;
Instruction = CODE_INSTR_NOP;
InputA = 0;
InputB = 0;
#100;
`describe("Test add operation");
`do_op(CODE_INSTR_ADD, 15, 7, 22);
`describe("Test gth operation");
`do_op(CODE_INSTR_GTH, 15, 7, 255);
`describe("Test or operation");
`do_op(CODE_INSTR_OR, 15, 7, 15);
`describe("Test sub operation");
`do_op(CODE_INSTR_SUB, 15, 7, 8);
`describe("Test shl operation");
`do_op(CODE_INSTR_SHL, 15, 7, 30);
`describe("Test add operation");
`do_op(CODE_INSTR_MUL, 15, 7, 105);
`describe("Test div operation");
`do_op(CODE_INSTR_DIV, 15, 7, 2);
`endTest
endmodule
| 7.860622 |
module TestSituation1 ();
reg [23:0] Minisys_Switches;
wire [23:0] Minisys_Lights;
reg Minisys_Clock;
reg [4:0] Minisys_Button;
TopAll use_main (
Minisys_Switches,
Minisys_Lights,
Minisys_Clock,
Minisys_Button
);
initial begin
Minisys_Clock = 1'b0;
Minisys_Button = 5'b00000;
#100 Minisys_Button = 5'b01000;
#50 Minisys_Button = 5'b00000;
Minisys_Switches[23:0] = 24'h000000;
#100 Minisys_Switches[21] = 1;
#10000 Minisys_Switches[1:0] = 2'b11;
#10000 Minisys_Switches[16] = 1;
#10000 Minisys_Switches[18] = 1;
#10000 Minisys_Switches[2:0] = 3'b101;
#10000 Minisys_Switches[17] = 1;
#10000 Minisys_Switches[23:21] = 3'b010;
end
//module TOP_all_test(
// );
//reg[23:0]Minisys_Switches;
//wire [23:0]Minisys_Lights;
//reg Minisys_Clock;
//reg Minisys_Button;
// CPUTOP use_main(Minisys_Switches,Minisys_Lights,Minisys_Clock,Minisys_Button);
// initial begin
//Minisys_Switches = 24'b0;
//Minisys_Clock = 1'b0;
//Minisys_Button = 1'b1;
//# 5 Minisys_Button = 1'b0;
////# 20 Minisys_Switches[23] =1;
//# 20 Minisys_Switches[15] =1;
//# 100 Minisys_Switches[15] =0;
//# 20 Minisys_Switches[23] =1;
// end
// always begin
// #100000 $finish;
// end
always begin
#5 Minisys_Clock = ~Minisys_Clock; //ⲿclock
end
endmodule
| 6.510336 |
module vc_TestSource #(
parameter p_msg_nbits = 1,
parameter p_num_msgs = 1024
) (
input logic clk,
input logic reset,
// Source message interface
output logic val,
input logic rdy,
output logic [p_msg_nbits-1:0] msg,
// Goes high once all source msgs has been issued
output logic done
);
//----------------------------------------------------------------------
// Local parameters
//----------------------------------------------------------------------
// Size of a physical address for the memory in bits
localparam c_index_nbits = $clog2(p_num_msgs);
//----------------------------------------------------------------------
// State
//----------------------------------------------------------------------
// Memory which stores messages to send
logic [ p_msg_nbits-1:0] m [p_num_msgs-1:0];
// Index register pointing to next message to send
logic index_en;
logic [c_index_nbits-1:0] index_next;
logic [c_index_nbits-1:0] index;
vc_EnResetReg #(c_index_nbits, {c_index_nbits{1'b0}}) index_reg (
.clk (clk),
.reset(reset),
.en (index_en),
.d (index_next),
.q (index)
);
// Register reset
logic reset_reg;
always_ff @(posedge clk) reset_reg <= reset;
//----------------------------------------------------------------------
// Combinational logic
//----------------------------------------------------------------------
// We use a behavioral hack to easily detect when we have sent all the
// valid messages in the test source. We used to use this:
//
// assign done = !reset_reg && ( m[index] === {p_msg_nbits{1'bx}} );
//
// but Ackerley Tng found an issue with this approach. You can see an
// example in this journal post:
//
// http://brg.csl.cornell.edu/wiki/alt53-2014-03-08
//
// So now we keep the done signal high until the test source is reset.
always_comb begin
if (reset_reg) begin
done <= 1'b0;
end else begin
if (~done) begin
done <= m[index] === {p_msg_nbits{1'bx}};
end
end
end
// Set the source message appropriately
assign msg = m[index];
// Source message interface is valid as long as we are not done
assign val = !reset_reg && !done;
// The go signal is high when a message is transferred
logic go;
assign go = val && rdy;
// We bump the index pointer every time we successfully send a message,
// otherwise the index stays the same.
assign index_en = go;
assign index_next = index + 1'b1;
//----------------------------------------------------------------------
// Assertions
//----------------------------------------------------------------------
always_ff @(posedge clk) begin
if (!reset) begin
`VC_ASSERT_NOT_X(val);
`VC_ASSERT_NOT_X(rdy);
end
end
//----------------------------------------------------------------------
// Line Tracing
//----------------------------------------------------------------------
logic [`VC_TRACE_NBITS_TO_NCHARS(p_msg_nbits)*8-1:0] msg_str;
`VC_TRACE_BEGIN
begin
$sformat(msg_str, "%x", msg);
vc_trace.append_val_rdy_str(
trace_str, val, rdy, msg_str
);
end
`VC_TRACE_END
endmodule
| 8.859833 |
module testSPWMGenerator;
reg CLK, RST, CP, CCW;
reg [ 3:0] SubLevel;
wire [11:0] PWM;
initial begin
RST = 0;
#1 RST = 1;
end
initial begin
CLK = 0;
forever #1 CLK = !CLK;
end
initial begin
CP = 0;
forever #200 CP = !CP;
end
initial begin
CCW = 1;
end
initial begin
SubLevel = 4'b1011;
end
wire PH, PL;
Interface Inst_Interface0 (
.CLK(CLK),
.rst(RST),
.CP(CP),
.CCW(CCW),
.SubLevel(SubLevel),
.REFA(PWM)
);
SPWMGenerator SPWM0 (
.CLK(CLK),
.RST(RST),
.PWM(PWM),
.PH (PH),
.PL (PL)
);
endmodule
| 7.134926 |
module: fibonacci_lfsr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testsss;
// Inputs
reg clk;
reg rst_n;
// Outputs
wire [4:0] data;
// Instantiate the Unit Under Test (UUT)
fibonacci_lfsr uut (
.clk(clk),
.rst_n(rst_n),
.data(data)
);
initial begin
// Initialize Inputs
clk = 0;
rst_n = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.790868 |
module TestStagesTB;
reg clk;
reg signed [15:0] sample;
reg read_file;
integer infile, i, fout, fout2;
integer cycles;
always begin
#0 clk = 0;
#10 clk = 1;
cycles = cycles + 1;
#10;
end
reg valid;
reg s1_ena, s1_rst, s3_rst;
wire signed [15:0] s1_dsample;
wire s1_dvalid;
wire [63:0] s1_acf;
wire s1_valid;
Stage1_Autocorrelation s1_a (
.iClock (clk),
.iEnable(s1_ena),
.iReset (s1_rst),
.iSample (sample),
.iValid (valid),
.oDSample(s1_dsample),
.oDValid (s1_dvalid),
.oACF (s1_acf),
.oValid(s1_valid)
);
wire signed [15:0] s2_dsample;
wire s2_dvalid;
wire s2_valid, s2_done;
wire signed [14:0] s2_model;
wire [3:0] s2_m;
Stage2_FindModel s2_fm (
.iClock (clk),
.iEnable(s1_ena),
.iReset (s1_rst | s2_done),
.iSample (s1_dsample),
.iSValid (s1_dvalid),
.oDSample(s2_dsample),
.oDValid (s2_dvalid),
.iACF (s1_acf),
.iValid(s1_valid),
.oModel(s2_model),
.oM(s2_m),
.oValid(s2_valid),
.oDone(s2_done)
);
wire s3_valid;
wire signed [15:0] residual;
wire frame_done;
Stage3_Encode s3_e (
.iClock (clk),
.iEnable(s1_ena),
.iReset (s3_rst),
.iValid (s2_dvalid),
.iSample(s2_dsample),
.iLoad(s2_valid),
.iModel(s2_model),
.iM(s2_m),
.oResidual(residual),
.oValid(s3_valid),
.oFrameDone(frame_done)
);
/*
wire s3_re1, s3_re2;
wire [15:0] s3_ra1, s3_ra2, s3_rd1, s3_rd2;
.oRamEnable1(s3_re1),
.oRamAddress1(s3_ra1),
.oRamData1(s3_rd1),
.oRamEnable2(s3_re2),
.oRamAddress2(s3_ra2),
.oRamData2(s3_rd2)*/
reg [15:0] output_count, frame_count;
always @(posedge clk) begin
if (read_file) begin
$fscanf(infile, "%d\n", sample);
valid <= 1;
end
if (frame_done) begin
frame_count <= frame_count + 1;
end
if (s1_valid) begin
$display("ACF: %d", s1_acf);
end
end
always @(posedge clk) begin
if (s2_valid) begin
$display("MODEL: %d -- %d", s2_m, s2_model);
end
end
always @(posedge clk) begin
if (s3_valid) begin
$fwrite(fout, "%d\n", residual);
output_count <= output_count + 1;
end
end
initial begin
//infile = $fopen("Pavane16Blocks.txt", "r");
//infile = $fopen("Pavane_PCM_All.txt", "r");
//fout = $fopen("pavane_test_residuals.txt", "w");
infile = $fopen("wakeup_pcm.txt", "r");
fout = $fopen("test_stages_res_out.txt", "w");
//fout = $fopen("wakeup_test_residuals.txt", "w");
//fout2 = $fopen("ld_coefficients2.txt", "w");
s1_ena = 0;
s1_rst = 1;
valid = 0;
read_file = 0;
s3_rst = 1;
output_count = 0;
frame_count = 0;
cycles = 0;
//Skip first 5 seconds of wake up
for (i = 0; i < 4096 * 512; i = i + 1) $fscanf(infile, "%d\n", sample);
#20;
read_file = 1;
s1_rst = 0;
s1_ena = 1;
s3_rst = 0;
for (i = 0; i < 4096 * 16; i = i + 1) #20;
read_file = 0;
valid = 0;
for (i = 0; i < 4096 * 3; i = i + 1) #20;
#60 $stop;
end
endmodule
| 6.626433 |
module TestStepModule #(
parameter WORD_SIZE = 16,
ADDRESS_SIZE = 16
) (
input clk,
rst,
init,
start,
read_step,
input [WORD_SIZE-1:0] step_in,
input [ADDRESS_SIZE-1:0] x0_address,
x1_address,
output done,
proceed,
error,
output [WORD_SIZE-1:0] step_out
);
wire [ADDRESS_SIZE-1:0] memory_address1, memory_address2;
wire [WORD_SIZE-1:0] memory_data1, memory_data2;
wire write_enable;
StepModule step (
clk,
rst,
init,
start,
read_step,
step_in,
x0_address,
x1_address,
memory_data1,
memory_data2,
done,
proceed,
error,
memory_address1,
memory_address2,
step_out
);
RAM #(
.WORD_SIZE(WORD_SIZE),
.ADDRESS_SIZE(ADDRESS_SIZE)
) ram (
clk,
rst,
write_enable,
memory_address1,
memory_address2,
memory_data1,
memory_data2
);
endmodule
| 7.051862 |
module testSyncs ();
// Inputs
reg btnC, btnD, btnU, btnL, btnR;
reg [15:0] sw;
reg clkin;
// Output
wire [3:0] an;
wire dp;
wire [6:0] seg;
wire [15:0] led;
wire HS;
wire [3:0] vgaBlue;
wire [3:0] vgaGreen;
wire [3:0] vgaRed;
wire VS;
wire oops;
wire rgb_oops;
// You may need to replace the instantiation below
// to match your top level module and its port names.
// Instantiate the UUT
top_level UUT (
.btnU(btnU),
.btnD(btnD),
.btnC(btnC),
.btnR(btnR),
.btnL(btnL),
.clkin(clkin),
.seg(seg),
.dp(dp),
.an(an),
.vgaBlue(vgaBlue),
.vgaRed(vgaRed),
.vgaGreen(vgaGreen),
.Vsync(VS),
.Hsync(HS),
.sw(sw),
.led(led)
);
reg good_HS;
reg good_VS;
reg activeH;
reg activeV;
// Clock parameters
parameter PERIOD = 10;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 2;
initial begin
clkin = 1'b0;
#OFFSET clkin = 1'b1;
forever begin
#(PERIOD - (PERIOD * DUTY_CYCLE)) clkin = ~clkin;
end
end
initial // the only input needed is a GSR pulse on sw[0]
begin // if you have others, set them to 0 or 1
sw = 16'b0;
sw[0] = 1'b0;
btnU = 1'b0;
btnC = 1'b0;
btnD = 1'b0;
#600 sw[0] = 1'b1;
#80 sw[0] = 1'b0;
end
// process to generate correct values for HS and activeH
initial begin
#OFFSET;
#0.1;
activeH = 1'b1;
good_HS = 1'b1;
#880;
#700; // to get past gsr pulse and clock delay
// comment out the line below if your HSync is not passed through a
// D FF before leaving the FPGA
//#40; // one more clock for FF delay output
forever begin
activeH = 1'b1;
#(640 * 40);
activeH = 1'b0;
#(15 * 40);
good_HS = 1'b0;
#((96) * 40);
good_HS = 1'b1;
#(49 * 40);
end
end
//correct values for VS and activeV
initial begin
#OFFSET;
#0.1;
activeV = 1'b1;
good_VS = 1'b1;
#880;
#700; // to get past gsr and DCM clock delay
// comment out the line below if your VSync is not passed through a
// D FF before leaving the FPGA
//#40; // one more clock for FF delay output
//btnL=1;
//#200
//btnL=0;
forever begin
activeV = 1'b1;
#(480 * 800 * 40);
activeV = 1'b0;
#(9 * 800 * 40);
good_VS = 1'b0;
#(2 * 800 * 40);
good_VS = 1'b1;
#(34 * 800 * 40);
end
end
// Instantiate the module comparing good and actual sync signals
check_the_sync_signals GUT (
.myHS(HS),
.myVS(VS),
.correct_HS(good_HS),
.correct_VS(good_VS),
.clk(clkin),
.btnR(sw[0]),
.sync_error(oops)
);
// Instantiate the module comparing checking RGB signals are
// low outside the active region
check_the_rgb_signals RUT (
.VB(vgaBlue),
.VG(vgaGreen),
.VR(vgaRed),
.activeH(activeH),
.activeV(activeV),
.clk(clkin),
.btnR(sw[0]),
.rgb_error(rgb_oops)
);
endmodule
| 6.882479 |
module check_the_sync_signals (
input myHS,
input myVS,
input correct_HS,
input correct_VS,
input clk,
input btnR,
output sync_error
);
// sync_error is high when actual and expected sync signals differ
assign sync_error = (myHS ^ correct_HS) | (myVS ^ correct_VS);
// SERRORS is incremented when sync_error is high at the rising edge of betterclk
integer SERRORS;
// since betterclk is divided by 2 in clkcntrl4 the error count
// will be double (each error will be counted twice)
always @(posedge clk) begin
SERRORS <= SERRORS + sync_error; // non-blocking assignment
end
// reset SERRORS on rising edge of gsr
always @(posedge btnR) begin
SERRORS <= 32'b0; // non-blocking assignment
end
endmodule
| 7.356019 |
module check_the_rgb_signals (
VB,
VG,
VR,
activeH,
activeV,
clk,
btnR,
rgb_error
);
input [3:0] VB, VG, VR;
input activeH, activeV;
input clk, btnR;
output rgb_error;
// rgb_error is high when any RGB output is high outside the active region
assign rgb_error = ((|VR) | (|VB) | (|VG)) & ~(activeH * activeV);
// RGBERRORS is incremented when rgb_error is high at the rising edge of betterclk
integer RGBERRORS;
// since betterclk is divided by 2 in clkcntrl4 the error count
// will be double (each error will be counted twice)
always @(posedge clk) begin
RGBERRORS <= RGBERRORS + rgb_error; // non-blocking assignment
end
// reset SERRORS on rising edge of gsr
always @(posedge btnR) begin
RGBERRORS <= 32'b0; // non-blocking assignment
end
endmodule
| 6.912731 |
module __primitive_eq #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 == in1;
endmodule
| 7.008191 |
module __primitive_neq #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 != in1;
endmodule
| 7.979335 |
module __primitive_mod #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 % in1;
endmodule
| 7.339096 |
module __primitive_div #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 / in1;
endmodule
| 7.228843 |
module __primitive_not #(
parameter in0N = 1,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
output wire [out0N-1:0] out0
);
assign out0 = !in0;
endmodule
| 7.979335 |
module __primitive_mul #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 * in1;
endmodule
| 7.339096 |
module __primitive_add #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 + in1;
endmodule
| 7.439769 |
module __primitive_sub #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 - in1;
endmodule
| 7.686847 |
module __primitive_shiftl #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 << in1;
endmodule
| 7.686847 |
module __primitive_shiftr #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 >> in1;
endmodule
| 7.686847 |
module __primitive_gt #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 > in1;
endmodule
| 6.836738 |
module __primitive_gte #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 >= in1;
endmodule
| 6.836738 |
module __primitive_lt #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 < in1;
endmodule
| 7.145377 |
module __primitive_lte #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 1
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 <= in1;
endmodule
| 7.145377 |
module __primitive_complement #(
parameter in0N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
output wire [out0N-1:0] out0
);
assign out0 = ~in0;
endmodule
| 7.597658 |
module __primitive_bitand #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 & in1;
endmodule
| 7.206703 |
module __primitive_bitor #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 | in1;
endmodule
| 7.206703 |
module __primitive_bitxor #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire [ in0N-1:0] in0,
input wire [ in1N-1:0] in1,
output wire [out0N-1:0] out0
);
assign out0 = in0 ^ in1;
endmodule
| 7.206703 |
module __primitive_ap01 #(
parameter in0N = 32,
parameter out1N = 32,
parameter out0N = 0
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0] in0,
input wire in0_valid,
output wire in0_ready,
output wire [out0N-1:0] out0,
output wire out0_valid,
input wire out0_ready,
output wire [out1N-1:0] out1
);
assign out0 = in0 >> out1N;
assign out1 = in0;
assign out0_valid = in0_valid;
assign out_valid = in0_valid && (!(&out1));
assign in0_ready = out0_ready & out_ready;
assign in_ready = 1'b1;
endmodule
| 7.439769 |
module __primitive_ap02 #(
parameter in0N = 32,
parameter out1N = 32,
parameter out2N = 32,
parameter out0N = 0
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0] in0,
input wire in0_valid,
output wire in0_ready,
output wire [out0N-1:0] out0,
output wire out0_valid,
input wire out0_ready,
output wire [out1N-1:0] out1,
output wire [out2N-1:0] out2
);
assign out0 = in0 >> (out1N + out2N);
assign out1 = in0 >> out2N;
assign out2 = in0;
assign out0_valid = in0_valid;
assign out_valid = in0_valid && (!(&out1)) && (!(&out2));
assign in0_ready = out0_ready & out_ready;
assign in_ready = 1'b1;
endmodule
| 7.439769 |
module __primitive_ap20 #(
parameter in0N = 32,
parameter in1N = 32,
parameter in2N = 32,
parameter out0N = in0N + in1N + in2N
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0] in0,
input wire [in1N-1:0] in1,
input wire [in2N-1:0] in2,
input wire in2_valid,
output wire in2_ready,
output wire [out0N-1:0] out0,
output wire out0_valid,
input wire out0_ready
);
assign out0 = {in0, in1, in2};
assign out0_valid = in_valid & in2_valid;
assign in2_ready = out0_ready;
assign in_ready = in_valid & out0_ready;
assign out_valid = 1'b1;
endmodule
| 7.439769 |
module __primitive_pushr1 #(
parameter in0N = 32,
parameter in1N = 32,
parameter out0N = 32
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0] in0,
input wire in0_valid,
output wire in0_ready,
input wire [in1N-1:0] in1,
output wire [out0N-1:0] out0,
output wire out0_valid,
input wire out0_ready
);
assign out0 = {in0, in1};
assign out0_valid = in_valid & in0_valid;
assign in0_ready = out0_ready;
assign in_ready = in_valid & out0_ready;
assign out_valid = 1'b1;
endmodule
| 7.068804 |
module __primitive_pushr2 #(
parameter in0N = 32,
parameter in1N = 32,
parameter in2N = 32,
parameter out0N = in0N + in1N + in2N
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [in0N-1:0] in0,
input wire in0_valid,
output wire in0_ready,
input wire [in1N-1:0] in1,
input wire [in2N-1:0] in2,
output wire [out0N-1:0] out0,
output wire out0_valid,
input wire out0_ready
);
assign out0 = {in0, in1, in2};
assign out0_valid = in_valid & in0_valid;
assign in0_ready = out0_ready;
assign in_ready = in_valid & out0_ready;
assign out_valid = 1'b1;
endmodule
| 7.068804 |
module transparent_buffer #(
parameter N = 32
) (
input wire clk,
input wire nrst,
input wire [N-1:0] in0,
input wire in0_valid,
output wire in0_ready,
output wire [N-1:0] out0,
output wire out0_valid,
input wire out0_ready
);
reg [N-1:0] data;
reg data_valid;
assign in0_ready = !data_valid | out0_ready;
assign out0_valid = data_valid | in0_valid;
assign out0 = in0_valid ? in0 : data;
always @(posedge clk) begin
if (!nrst) begin
data_valid <= 1'b0;
end else if (in0_ready) begin
if (in0_valid) data <= in0;
if (!(in0_valid & out0_ready)) data_valid <= in0_valid;
end
end
endmodule
| 7.056174 |
module __primitive_write_array #(
parameter in0AN = 9,
parameter in0DN = 32,
parameter in1N = 32,
parameter in2N = 32,
parameter out0AN = 9,
parameter out0DN = 32
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
output wire [(in0AN)-1:0] in0_addr,
output wire in0_we,
output wire [(in0DN)-1:0] in0_di,
input wire [(in0DN)-1:0] in0_do,
output wire in0_valid,
input wire in0_ready,
input wire [ in1N-1:0] in1,
input wire [ in2N-1:0] in2,
input wire [(out0AN)-1:0] out0_addr,
input wire out0_we,
input wire [(out0DN)-1:0] out0_di,
output wire [(out0DN)-1:0] out0_do,
input wire out0_valid,
output wire out0_ready
);
reg valid;
wire beat = in_valid & in_ready;
assign in_ready = in0_ready & (!valid | out_ready);
assign in0_addr = in_valid ? in1 : out0_addr;
assign in0_we = in_valid | out0_we;
assign in0_di = in_valid ? in2 : out0_di;
assign out0_do = in0_do;
assign in0_valid = in_valid | out0_valid;
assign out0_ready = !in_valid & in0_ready;
assign out_valid = valid | beat;
always @(posedge clk) begin
if (!nrst) valid <= 1'b0;
else if (beat | out_ready) valid <= beat;
end
endmodule
| 7.019726 |
module __primitive_dup_array #(
parameter in0AN = 9,
parameter in0DN = 32,
parameter out0AN = 9,
parameter out0DN = 32,
parameter out1AN = 9,
parameter out1DN = 32
) (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
output wire [(in0AN)-1:0] in0_addr,
output wire in0_we,
output wire [(in0DN)-1:0] in0_di,
input wire [(in0DN)-1:0] in0_do,
output wire in0_valid,
input wire in0_ready,
input wire [(out0AN)-1:0] out0_addr,
input wire out0_we,
input wire [(out0DN)-1:0] out0_di,
output wire [(out0DN)-1:0] out0_do,
input wire out0_valid,
output wire out0_ready,
input wire [(out1AN)-1:0] out1_addr,
input wire out1_we,
input wire [(out1DN)-1:0] out1_di,
output wire [(out1DN)-1:0] out1_do,
input wire out1_valid,
output wire out1_ready
);
reg last_active;
wire active0 = !out1_valid | last_active == 1;
wire active1 = !out0_valid | last_active == 0;
wire select0 = active0 & out0_valid;
assign in0_addr = select0 ? out0_addr : out1_addr;
assign in0_we = select0 ? out0_we : out1_we;
assign in0_di = select0 ? out0_di : out1_di;
assign out0_do = in0_do;
assign out1_do = in0_do;
assign in0_valid = out0_valid | out1_valid;
assign out0_ready = in0_ready & active0;
assign out1_ready = in0_ready & active1;
assign in_ready = 1'b1;
assign out_valid = 1'b1;
always @(posedge clk) begin
if (!nrst) last_active <= 1'b0;
else if (in0_ready) begin
last_active <= out1_valid & active1;
end
end
endmodule
| 7.228843 |
module tests_axil_map_w_r0 (
input wire clk,
input wire nrst,
input wire in_valid,
output wire in_ready,
output wire out_valid,
input wire out_ready,
input wire [32-1:0] in0,
input wire in0_valid,
output wire in0_ready,
output wire [33-1:0] out0,
output wire out0_valid,
input wire out0_ready
);
wire [32-1:0] lst1 = in0;
reg lst1_valid_reg;
wire lst1_valid = in0_valid;
wire lst1_ready;
assign in0_ready = lst1_ready;
wire inst2_in_ready;
wire lst2_valid;
wire lst2_ready;
wire [32-1:0] int3;
wire [33-1:0] int4;
localparam [2-1:0] int5 = 3;
localparam lst6_valid = 1'b1;
wire lst6_ready;
wire inst7_in_ready;
wire [33-1:0] lst7;
wire lst7_valid;
wire lst7_ready;
reg active = 1'b0;
assign in_ready = ~active & inst2_in_ready;
wire inst2_out_valid;
__primitive_ap01 #(
.in0N (32),
.out0N(0),
.out1N(32)
) __primitive_ap01_inst2 (
.clk(clk),
.nrst(nrst),
.in_valid(active),
.out_valid(inst2_out_valid),
.in_ready(inst2_in_ready),
.out_ready(inst7_in_ready),
.in0(lst1),
.in0_valid(lst1_valid),
.in0_ready(lst1_ready),
.out0_valid(lst2_valid),
.out0_ready(lst2_ready),
.out1(int3)
);
__primitive_add #(
.in0N (32),
.in1N (2),
.out0N(33)
) __primitive_add_inst4 (
.in0 (int3),
.in1 (int5),
.out0(int4)
);
assign lst2_ready = 1'b1;
wire inst7_out_valid;
__primitive_pushr1 #(
.in0N (0),
.in1N (33),
.out0N(33)
) __primitive_pushr1_inst7 (
.clk(clk),
.nrst(nrst),
.in_valid(inst2_out_valid),
.out_valid(inst7_out_valid),
.in_ready(inst7_in_ready),
.out_ready(1'b1),
.in0_valid(lst6_valid),
.in0_ready(lst6_ready),
.in1(int4),
.out0(lst7),
.out0_valid(lst7_valid),
.out0_ready(lst7_ready)
);
wire block1_valid = inst7_out_valid;
wire valid = 1'b0;
assign out_valid = active & valid;
always @(posedge clk) begin
if (!nrst) begin
active <= 1'b0;
end else if (in_valid & ~active) begin
active <= 1'b1;
end else if (valid) begin
if (out_ready) active <= 1'b0;
end else begin
if (block1_valid) begin
end
end
end
assign out0 = lst7;
assign out0_valid = lst7_valid;
assign lst7_ready = out0_ready;
endmodule
| 6.519507 |
module testTimePulseGen;
reg CLK, RST;
reg [4:0] SW;
initial begin
RST = 0;
#1 RST = 1;
end
initial begin
CLK = 0;
forever #1 CLK = !CLK;
end
initial begin
SW = 5'b00000;
#2000 SW = 5'b00010;
#2000 SW = 5'b00100;
#2000 SW = 5'b01000;
#2000 SW = 5'b10000;
end
wire CP;
wire [3:0] Sublevel;
TimePulGenerator T0 (
.CLK(CLK),
.RST(RST),
.SW(SW),
.CP(CP),
.Sublevel(Sublevel)
);
endmodule
| 7.262232 |
module top (
input SCK, // arduino 13
input MOSI, // arduino 11
inout MISO, // arduino 12
input SSEL, // arduino 9
output flashMOSI,
input flashMISO,
output flashSCK,
output flashSSEL
);
assign flashMOSI = MOSI;
assign MISO = flashMISO;
assign flashSCK = SCK;
assign flashSSEL = SSEL;
endmodule
| 7.233807 |
module: top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testTop1;
// Inputs
reg Clk;
// Outputs
wire Ram2_EN;
wire Ram2_OE;
wire Ram2_WE;
wire [17:0] Ram2_address;
wire Ram1_EN;
wire Ram1_OE;
wire Ram1_WE;
wire [17:0] Ram1_address;
// Bidirs
wire [15:0] Ram2_data;
wire [15:0] Ram1_data;
// Instantiate the Unit Under Test (UUT)
top uut (
.Clk(Clk),
.Ram2_EN(Ram2_EN),
.Ram2_OE(Ram2_OE),
.Ram2_WE(Ram2_WE),
.Ram2_address(Ram2_address),
.Ram2_data(Ram2_data),
.Ram1_EN(Ram1_EN),
.Ram1_OE(Ram1_OE),
.Ram1_WE(Ram1_WE),
.Ram1_address(Ram1_address),
.Ram1_data(Ram1_data)
);
initial begin
// Initialize Inputs
Clk = 0;
forever #50 Clk = ~Clk;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.115105 |
module TestTransmit ();
reg clk, TxD_start, Rst;
reg [7:0] TxD_data;
wire TxD, TxD_busy;
async_transmitter ts (
.clk(clk),
.TxD_start(TxD_start),
.TxD_data(TxD_data),
.Rst(Rst),
.TxD(TxD),
.TxD_busy(TxD_busy)
);
initial repeat (10000) #20 clk = ~clk;
initial begin
Rst = 1'b1;
clk = 1'b0;
TxD_start = 1'b0;
#40 Rst = 1'b0;
#200 TxD_start = 1'b1;
TxD_data = 8'd325;
#200 TxD_start = 1'b0;
#1000000 $stop;
end
endmodule
| 7.34831 |
module TestTriangle #(
parameter SIZE = 8'd108
) (
input clk100,
input nextFrame,
output reg [7:0] index,
input VertexBuffer_PreCalc_pop,
output reg VertexBuffer_PreCalc_empty,
output [7:0] count,
input [7:0] sin,
input [223:0] testdata,
output [223:0] VertexBuffer_PreCalc_ReadData
);
reg [7:0] count = 0;
reg [1:0] multsel = 0;
reg signed [19:0] mult;
reg signed [7:0] sinbuf;
reg signed [11:0] x1;
reg signed [11:0] x2;
reg signed [11:0] x3;
reg [11:0] x1_o;
reg [11:0] x2_o;
reg [11:0] x3_o;
assign VertexBuffer_PreCalc_ReadData = {8'h00, x1_o, x2_o, x3_o, testdata[179:0]};
always @(posedge clk100) begin
multsel <= multsel + 1;
sinbuf <= sin;
x1 <= testdata[215:204] - 1280;
x2 <= testdata[203:192] - 1280;
x3 <= testdata[191:180] - 1280;
case (multsel)
0: begin
mult = x1 * sinbuf;
x1_o <= mult[18:7] + 1280;
end
1: begin
mult = x2 * sinbuf;
x2_o <= mult[18:7] + 1280;
end
2: begin
mult = x3 * sinbuf;
x3_o <= mult[18:7] + 1280;
end
endcase
end
always @(posedge clk100) begin
if (nextFrame) begin
count <= count + 1;
index <= 0;
VertexBuffer_PreCalc_empty <= 0;
end else begin
if (VertexBuffer_PreCalc_pop) begin
if (index < SIZE) index <= index + 1;
end
VertexBuffer_PreCalc_empty <= (index == SIZE);
end
end
endmodule
| 6.782869 |
module TestTriangle (
input clk100,
input nextFrame,
output reg [223:0] PreCalc_TriangleFIFO_WriteData,
output reg PreCalc_TriangleFIFO_push,
input PreCalc_TriangleFIFO_wait
);
parameter RESET = 2'd0, PUSH1 = 2'd1, PUSH2 = 2'd2, DONE = 2'd3;
reg [1:0] State = 0;
reg [1:0] Next;
always @(posedge clk100) begin
State <= Next;
end
//Next State decoder
always @* begin
if (nextFrame) Next = RESET;
else
case (State)
RESET: begin
if (PreCalc_TriangleFIFO_wait) Next = RESET;
else Next = PUSH1;
end
PUSH1: Next = PUSH2;
PUSH2: Next = DONE;
DONE: Next = DONE;
default: Next = DONE;
endcase
end
//Registered Output decoder
always @(posedge clk100) begin
if (nextFrame) begin
PreCalc_TriangleFIFO_push <= 0;
PreCalc_TriangleFIFO_WriteData <= 0;
end else
case (Next)
PUSH1: begin
PreCalc_TriangleFIFO_push <= 1;
PreCalc_TriangleFIFO_WriteData <= {
1'h0,
20'h4B000,
20'h4B000,
10'h258,
21'h1FFDF3,
21'h000423,
21'h1FEC00,
10'h00A,
10'h12C,
10'h190,
26'h10,
27'h0,
27'h0
};
end
PUSH2: begin
PreCalc_TriangleFIFO_push <= 1;
PreCalc_TriangleFIFO_WriteData <= {
32'h0, 22'h3FF000, 23'h0, 23'h0, 22'h0, 23'h0, 23'h0, 18'h0, 19'h0, 19'h0
};
end
default: begin
PreCalc_TriangleFIFO_push <= 0;
PreCalc_TriangleFIFO_WriteData <= 0;
end
endcase
end
endmodule
| 6.782869 |
module testTubeControl ();
reg Sys_CLK;
reg Sys_RST;
reg [1:0] Key;
wire [7:0] SEG;
wire [1:0] COM;
wire [3:0] LED;
tubeControl U1 (
.Sys_CLK(Sys_CLK),
.Sys_RST(Sys_RST),
.Key(Key),
.SEG(SEG),
.COM(COM),
.LED(LED)
);
initial begin
Sys_CLK = 0;
Sys_RST = 1;
Key = 0;
#5 Sys_RST = 0;
#50 Key[0] = 1;
#54 Key[0] = 0;
#60 Key[0] = 0;
#70 Key[0] = 1;
#86 Key[0] = 0;
#87 Key[0] = 1;
end
always begin
#1 Sys_CLK = !Sys_CLK;
end
endmodule
| 6.752898 |
module
// Module Name: C:/Users/Rodrigo/Desktop/Universidad/Cuarto/Project/RecLeastSquares/RLS/testUART.v
// Project Name: RLS
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UARTmodule
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testUART;
// Inputs
reg clk;
reg reset;
reg load;
reg start;
// Outputs
wire serialo;
// Instantiate the Unit Under Test (UUT)
UARTmodule uut (
.clk(clk),
.reset(reset),
.load(load),
.start(start),
.serialo(serialo)
);
always #5 clk=!clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
load = 0;
start = 0;
// Wait 100 ns for global reset to finish
#100;
reset=0;
#20
reset=1;
#10
load=1;
#10
load=0;
#10
start=1;
#10
start=0;
#276447232;
// Add stimulus here
end
endmodule
| 6.999332 |
module
*
*
* MIT License
*/
module TestUnsignDividerComb
#(
parameter INPUT_BIT_WIDTH = 8
);
// Inputs
`defClock(Clk, 2);
reg [INPUT_BIT_WIDTH-1:0] Dividend;
reg [INPUT_BIT_WIDTH-1:0] Divider;
// Outputs
wire [INPUT_BIT_WIDTH-1:0] Quotient;
wire [INPUT_BIT_WIDTH-1:0] Remainder;
// Instantiate the Unit Under Test (UUT)
UnsignDividerComb uut (
.Quotient(Quotient),
.Remainder(Remainder),
.Dividend(Dividend),
.Divider(Divider),
.Clk(Clk)
);
`startTest("UnsignDividerComb");
// Initialize Inputs
Dividend = 0;
Divider = 0;
Clk = 0;
#100;
`describe("Test 13 / 2");
`do_div(13, 2);
`describe("Test 69 / 42");
`do_div(69, 42);
`describe("Test 255 / 5");
`do_div(255, 5);
`describe("Test 77 / 1");
`do_div(77, 1);
//`describe("Test 150 / 150");
// `do_div(150, 150);
`endTest
endmodule
| 7.860622 |
module HVSync (
pixelClk,
HSync,
VSync,
R,
G,
B,
LY,
LineBuffer0,
LineBuffer1,
updateBufferSignal
);
input pixelClk;
output HSync;
output VSync;
output [3:0] R;
output [3:0] G;
output [3:0] B;
input [7:0] LY;
input [159:0] LineBuffer0;
input [159:0] LineBuffer1;
input updateBufferSignal;
reg [7:0] oldLY = 8'b0;
reg [9:0] HCount = 10'b0;
reg [9:0] VCount = 10'b0;
wire HCountMax = (HCount == 799);
wire VCountMax = (VCount == 524);
wire [159:0] bufferOutput0;
wire [159:0] bufferOutput1;
reg wr_buffer = 1'b0;
parameter hori_line = 800;
parameter hori_back = 144;
parameter hori_front = 16;
parameter vert_line = 525;
parameter vert_back = 34;
parameter vert_front = 11;
parameter H_sync_cycle = 96;
parameter V_sync_cycle = 2;
parameter H_BLANK = hori_front + H_sync_cycle;
videoRam ppuBuffer0 (
pixelClk,
LineBuffer0,
YValid,
oldLY,
wr_buffer,
bufferOutput0
);
videoRam ppuBuffer1 (
pixelClk,
LineBuffer1,
YValid,
oldLY,
wr_buffer,
bufferOutput1
);
always @(negedge pixelClk) begin
if (HCount == hori_line - 1'b1) begin
HCount <= 10'd0;
if (VCount == vert_line - 1'b1) VCount <= 10'd0;
else VCount <= VCount + 1'b1;
end else HCount <= HCount + 1'b1;
end
assign HSync = (HCount < H_sync_cycle) ? 1'b0 : 1'b1;
assign VSync = (VCount < V_sync_cycle) ? 1'b0 : 1'b1;
reg [1:0] saveRoutineCounter = 2'b00;
always @(posedge pixelClk) begin
if ((oldLY != LY && updateBufferSignal == 1'b1) || saveRoutineCounter != 2'b00) begin
if (saveRoutineCounter == 2'b00) begin
oldLY <= LY;
saveRoutineCounter <= saveRoutineCounter + 1'b1;
end
if (saveRoutineCounter == 2'b01) begin
saveRoutineCounter <= saveRoutineCounter + 1'b1;
end
if (saveRoutineCounter == 2'b10) begin
wr_buffer <= 1'b1;
saveRoutineCounter <= saveRoutineCounter + 1'b1;
end
if (saveRoutineCounter == 2'b11) begin
wr_buffer <= 1'b0;
saveRoutineCounter <= 2'b00;
end
end
end
wire [9:0] XValid;
wire [9:0] YValid;
assign XValid = HCount - hori_back;
assign YValid = VCount - vert_back;
assign R = (YValid >= 10'd0 && YValid < 10'd145 && XValid >= 10'd0 && XValid < 10'd160) ?
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b00 ? 4'b1101 :
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b01 ? 4'b1000 :
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b10 ? 4'b0011 :
4'b0001))) : 4'b0000;
assign G = (YValid >= 10'd0 && YValid < 10'd145 && XValid >= 10'd0 && XValid < 10'd160) ?
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b00 ? 4'b1111 :
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b01 ? 4'b1011 :
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b10 ? 4'b0110 :
4'b0001))) : 4'b0000;
assign B = (YValid >= 10'd0 && YValid < 10'd145 && XValid >= 10'd0 && XValid < 10'd160) ?
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b00 ? 4'b1100 :
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b01 ? 4'b0111 :
({bufferOutput1[XValid], bufferOutput0[XValid]} == 2'b10 ? 4'b0101 :
4'b0010))) : 4'b0000;
endmodule
| 6.979848 |
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