code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_axis_eth_fcs_insert_pad;
// Parameters
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser,
m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tvalid, m_axis_tlast, m_axis_tuser, busy);
// dump file
$dumpfile("test_axis_eth_fcs_insert_pad.lxt");
$dumpvars(0, test_axis_eth_fcs_insert_pad);
end
axis_eth_fcs_insert #(
.ENABLE_PADDING (ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.busy(busy)
);
endmodule
| 8.161317 |
module test_axis_fifo;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_fifo.lxt");
$dumpvars(0, test_axis_fifo);
end
axis_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
| 7.264041 |
module test_axis_fifo_64;
// Parameters
parameter DEPTH = 32;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_fifo_64.lxt");
$dumpvars(0, test_axis_fifo_64);
end
axis_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
| 7.264041 |
module test_axis_fifo_adapter_64_8;
// Parameters
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 8;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_fifo_adapter_64_8.lxt");
$dumpvars(0, test_axis_fifo_adapter_64_8);
end
axis_fifo_adapter #(
.DEPTH(DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
| 7.264041 |
module test_axis_fifo_adapter_8_64;
// Parameters
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 8;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 64;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 0;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 0;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_fifo_adapter_8_64.lxt");
$dumpvars(0, test_axis_fifo_adapter_8_64);
end
axis_fifo_adapter #(
.DEPTH(DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
| 7.264041 |
module test_axis_frame_fifo;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire status_overflow;
wire status_bad_frame;
wire status_good_frame;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, status_overflow, status_bad_frame, status_good_frame);
// dump file
$dumpfile("test_axis_frame_fifo.lxt");
$dumpvars(0, test_axis_frame_fifo);
end
axis_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
| 6.502934 |
module test_axis_frame_fifo_64;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire status_overflow;
wire status_bad_frame;
wire status_good_frame;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, status_overflow, status_bad_frame, status_good_frame);
// dump file
$dumpfile("test_axis_frame_fifo_64.lxt");
$dumpvars(0, test_axis_frame_fifo_64);
end
axis_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
| 6.502934 |
module test_axis_frame_join_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter TAG_ENABLE = 1;
parameter TAG_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg [TAG_WIDTH-1:0] tag = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser,
m_axis_tready, tag);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tvalid, m_axis_tlast, m_axis_tuser, busy);
// dump file
$dumpfile("test_axis_frame_join_4.lxt");
$dumpvars(0, test_axis_frame_join_4);
end
axis_frame_join #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.TAG_ENABLE(TAG_ENABLE),
.TAG_WIDTH(TAG_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// config
.tag(tag),
// status
.busy(busy)
);
endmodule
| 6.502934 |
module test_axis_frame_length_adjust_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg status_ready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire status_valid;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, status_ready, length_min,
length_max);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, status_valid, status_frame_pad, status_frame_truncate,
status_frame_length, status_frame_original_length);
// dump file
$dumpfile("test_axis_frame_length_adjust_64.lxt");
$dumpvars(0, test_axis_frame_length_adjust_64);
end
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule
| 6.502934 |
module test_axis_frame_length_adjust_8;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg status_ready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire status_valid;
wire status_frame_pad;
wire status_frame_truncate;
wire [15:0] status_frame_length;
wire [15:0] status_frame_original_length;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, status_ready, length_min,
length_max);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, status_valid, status_frame_pad, status_frame_truncate,
status_frame_length, status_frame_original_length);
// dump file
$dumpfile("test_axis_frame_length_adjust_8.lxt");
$dumpvars(0, test_axis_frame_length_adjust_8);
end
axis_frame_length_adjust #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_valid(status_valid),
.status_ready(status_ready),
.status_frame_pad(status_frame_pad),
.status_frame_truncate(status_frame_truncate),
.status_frame_length(status_frame_length),
.status_frame_original_length(status_frame_original_length),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule
| 6.502934 |
module test_axis_frame_length_adjust_fifo;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_DEPTH = 4096;
parameter HEADER_FIFO_DEPTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_hdr_ready = 0;
reg m_axis_tready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire m_axis_hdr_valid;
wire m_axis_hdr_pad;
wire m_axis_hdr_truncate;
wire [15:0] m_axis_hdr_length;
wire [15:0] m_axis_hdr_original_length;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_hdr_ready, m_axis_tready,
length_min, length_max);
$to_myhdl(s_axis_tready, m_axis_hdr_valid, m_axis_hdr_pad, m_axis_hdr_truncate,
m_axis_hdr_length, m_axis_hdr_original_length, m_axis_tdata, m_axis_tkeep,
m_axis_tvalid, m_axis_tlast, m_axis_tid, m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_frame_length_adjust_fifo.lxt");
$dumpvars(0, test_axis_frame_length_adjust_fifo);
end
axis_frame_length_adjust_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_DEPTH(FRAME_FIFO_DEPTH),
.HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_hdr_valid(m_axis_hdr_valid),
.m_axis_hdr_ready(m_axis_hdr_ready),
.m_axis_hdr_pad(m_axis_hdr_pad),
.m_axis_hdr_truncate(m_axis_hdr_truncate),
.m_axis_hdr_length(m_axis_hdr_length),
.m_axis_hdr_original_length(m_axis_hdr_original_length),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule
| 6.502934 |
module test_axis_frame_length_adjust_fifo_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_DEPTH = 4096;
parameter HEADER_FIFO_DEPTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_hdr_ready = 0;
reg m_axis_tready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire m_axis_hdr_valid;
wire m_axis_hdr_pad;
wire m_axis_hdr_truncate;
wire [15:0] m_axis_hdr_length;
wire [15:0] m_axis_hdr_original_length;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_hdr_ready, m_axis_tready,
length_min, length_max);
$to_myhdl(s_axis_tready, m_axis_hdr_valid, m_axis_hdr_pad, m_axis_hdr_truncate,
m_axis_hdr_length, m_axis_hdr_original_length, m_axis_tdata, m_axis_tkeep,
m_axis_tvalid, m_axis_tlast, m_axis_tid, m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_frame_length_adjust_fifo_64.lxt");
$dumpvars(0, test_axis_frame_length_adjust_fifo_64);
end
axis_frame_length_adjust_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_DEPTH(FRAME_FIFO_DEPTH),
.HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_hdr_valid(m_axis_hdr_valid),
.m_axis_hdr_ready(m_axis_hdr_ready),
.m_axis_hdr_pad(m_axis_hdr_pad),
.m_axis_hdr_truncate(m_axis_hdr_truncate),
.m_axis_hdr_length(m_axis_hdr_length),
.m_axis_hdr_original_length(m_axis_hdr_original_length),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule
| 6.502934 |
module test_axis_frame_len_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LEN_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0;
reg monitor_axis_tvalid = 0;
reg monitor_axis_tready = 0;
reg monitor_axis_tlast = 0;
// Outputs
wire [LEN_WIDTH-1:0] frame_len;
wire frame_len_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, monitor_axis_tkeep, monitor_axis_tvalid,
monitor_axis_tready, monitor_axis_tlast);
$to_myhdl(frame_len, frame_len_valid);
// dump file
$dumpfile("test_axis_frame_len_64.lxt");
$dumpvars(0, test_axis_frame_len_64);
end
axis_frame_len #(
.DATA_WIDTH (DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH (KEEP_WIDTH),
.LEN_WIDTH (LEN_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI monitor
.monitor_axis_tkeep(monitor_axis_tkeep),
.monitor_axis_tvalid(monitor_axis_tvalid),
.monitor_axis_tready(monitor_axis_tready),
.monitor_axis_tlast(monitor_axis_tlast),
// Status
.frame_len(frame_len),
.frame_len_valid(frame_len_valid)
);
endmodule
| 6.502934 |
module test_axis_frame_len_8;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LEN_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0;
reg monitor_axis_tvalid = 0;
reg monitor_axis_tready = 0;
reg monitor_axis_tlast = 0;
// Outputs
wire [LEN_WIDTH-1:0] frame_len;
wire frame_len_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, monitor_axis_tkeep, monitor_axis_tvalid,
monitor_axis_tready, monitor_axis_tlast);
$to_myhdl(frame_len, frame_len_valid);
// dump file
$dumpfile("test_axis_frame_len_8.lxt");
$dumpvars(0, test_axis_frame_len_8);
end
axis_frame_len #(
.DATA_WIDTH (DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH (KEEP_WIDTH),
.LEN_WIDTH (LEN_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI monitor
.monitor_axis_tkeep(monitor_axis_tkeep),
.monitor_axis_tvalid(monitor_axis_tvalid),
.monitor_axis_tready(monitor_axis_tready),
.monitor_axis_tlast(monitor_axis_tlast),
// Status
.frame_len(frame_len),
.frame_len_valid(frame_len_valid)
);
endmodule
| 6.502934 |
module test_axis_gmii_rx;
// Parameters
parameter DATA_WIDTH = 8;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
reg clk_enable = 1;
reg mii_select = 0;
// Outputs
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire start_packet;
wire error_bad_frame;
wire error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, gmii_rxd, gmii_rx_dv, gmii_rx_er, ptp_ts, clk_enable,
mii_select);
$to_myhdl(m_axis_tdata, m_axis_tvalid, m_axis_tlast, m_axis_tuser, start_packet,
error_bad_frame, error_bad_fcs);
// dump file
$dumpfile("test_axis_gmii_rx.lxt");
$dumpvars(0, test_axis_gmii_rx);
end
axis_gmii_rx #(
.DATA_WIDTH(DATA_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.ptp_ts(ptp_ts),
.clk_enable(clk_enable),
.mii_select(mii_select),
.start_packet(start_packet),
.error_bad_frame(error_bad_frame),
.error_bad_fcs(error_bad_fcs)
);
endmodule
| 6.789139 |
module test_axis_gmii_tx;
// Parameters
parameter DATA_WIDTH = 8;
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE;
parameter PTP_TAG_WIDTH = 16;
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
reg clk_enable = 1;
reg mii_select = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag;
wire m_axis_ptp_ts_valid;
wire start_packet;
wire error_underflow;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tvalid, s_axis_tlast, s_axis_tuser,
ptp_ts, clk_enable, mii_select, ifg_delay);
$to_myhdl(s_axis_tready, gmii_txd, gmii_tx_en, gmii_tx_er, m_axis_ptp_ts, m_axis_ptp_ts_tag,
m_axis_ptp_ts_valid, start_packet, error_underflow);
// dump file
$dumpfile("test_axis_gmii_tx.lxt");
$dumpvars(0, test_axis_gmii_tx);
end
axis_gmii_tx #(
.DATA_WIDTH(DATA_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.clk_enable(clk_enable),
.mii_select(mii_select),
.ifg_delay(ifg_delay),
.start_packet(start_packet),
.error_underflow(error_underflow)
);
endmodule
| 6.789139 |
module test_axis_ll_bridge;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg ll_dst_rdy_in_n = 1;
// Outputs
wire [DATA_WIDTH-1:0] ll_data_out;
wire ll_sof_out_n;
wire ll_eof_out_n;
wire ll_src_rdy_out_n;
wire s_axis_tready;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tvalid, s_axis_tlast, ll_dst_rdy_in_n);
$to_myhdl(ll_data_out, ll_sof_out_n, ll_eof_out_n, ll_src_rdy_out_n, s_axis_tready);
// dump file
$dumpfile("test_axis_ll_bridge.lxt");
$dumpvars(0, test_axis_ll_bridge);
end
axis_ll_bridge #(
.DATA_WIDTH(DATA_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
// locallink output
.ll_data_out(ll_data_out),
.ll_sof_out_n(ll_sof_out_n),
.ll_eof_out_n(ll_eof_out_n),
.ll_src_rdy_out_n(ll_src_rdy_out_n),
.ll_dst_rdy_in_n(ll_dst_rdy_in_n)
);
endmodule
| 8.95397 |
module test_axis_mux_4;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, enable, select);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_mux_4.lxt");
$dumpvars(0, test_axis_mux_4);
end
axis_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
| 7.848933 |
module test_axis_mux_4_64;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg enable = 0;
reg [1:0] select = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, enable, select);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_mux_4_64.lxt");
$dumpvars(0, test_axis_mux_4_64);
end
axis_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Control
.enable(enable),
.select(select)
);
endmodule
| 7.848933 |
module test_axis_ram_switch_1x4_256_64;
// Parameters
parameter FIFO_DEPTH = 512;
parameter SPEEDUP = 0;
parameter S_COUNT = 1;
parameter M_COUNT = 4;
parameter S_DATA_WIDTH = 256;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 64;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT + 1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
parameter RAM_PIPELINE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
wire [S_COUNT-1:0] status_overflow;
wire [S_COUNT-1:0] status_bad_frame;
wire [S_COUNT-1:0] status_good_frame;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, status_overflow, status_bad_frame, status_good_frame);
// dump file
$dumpfile("test_axis_ram_switch_1x4_256_64.lxt");
$dumpvars(0, test_axis_ram_switch_1x4_256_64);
end
axis_ram_switch #(
.FIFO_DEPTH(FIFO_DEPTH),
.SPEEDUP(SPEEDUP),
.S_COUNT(S_COUNT),
.M_COUNT(M_COUNT),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
| 8.06173 |
module test_axis_ram_switch_4x1_64_256;
// Parameters
parameter FIFO_DEPTH = 512;
parameter SPEEDUP = 0;
parameter S_COUNT = 4;
parameter M_COUNT = 1;
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 256;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT + 1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
parameter RAM_PIPELINE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
wire [S_COUNT-1:0] status_overflow;
wire [S_COUNT-1:0] status_bad_frame;
wire [S_COUNT-1:0] status_good_frame;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, status_overflow, status_bad_frame, status_good_frame);
// dump file
$dumpfile("test_axis_ram_switch_4x1_64_256.lxt");
$dumpvars(0, test_axis_ram_switch_4x1_64_256);
end
axis_ram_switch #(
.FIFO_DEPTH(FIFO_DEPTH),
.SPEEDUP(SPEEDUP),
.S_COUNT(S_COUNT),
.M_COUNT(M_COUNT),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
| 8.06173 |
module test_axis_ram_switch_4x4_64_64;
// Parameters
parameter FIFO_DEPTH = 512;
parameter SPEEDUP = 0;
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH > 8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH / 8);
parameter M_DATA_WIDTH = 64;
parameter M_KEEP_ENABLE = (M_DATA_WIDTH > 8);
parameter M_KEEP_WIDTH = (M_DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT + 1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
parameter RAM_PIPELINE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*S_DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*S_KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*M_DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*M_KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
wire [S_COUNT-1:0] status_overflow;
wire [S_COUNT-1:0] status_bad_frame;
wire [S_COUNT-1:0] status_good_frame;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, status_overflow, status_bad_frame, status_good_frame);
// dump file
$dumpfile("test_axis_ram_switch_4x4_64_64.lxt");
$dumpvars(0, test_axis_ram_switch_4x4_64_64);
end
axis_ram_switch #(
.FIFO_DEPTH(FIFO_DEPTH),
.SPEEDUP(SPEEDUP),
.S_COUNT(S_COUNT),
.M_COUNT(M_COUNT),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),
.M_DATA_WIDTH(M_DATA_WIDTH),
.M_KEEP_ENABLE(M_KEEP_ENABLE),
.M_KEEP_WIDTH(M_KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY),
.RAM_PIPELINE(RAM_PIPELINE)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.status_overflow(status_overflow),
.status_bad_frame(status_bad_frame),
.status_good_frame(status_good_frame)
);
endmodule
| 8.06173 |
module test_axis_rate_limit;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg [7:0] rate_num = 0;
reg [7:0] rate_denom = 0;
reg rate_by_frame = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, rate_num, rate_denom,
rate_by_frame);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_rate_limit.lxt");
$dumpvars(0, test_axis_rate_limit);
end
axis_rate_limit #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Configuration
.rate_num(rate_num),
.rate_denom(rate_denom),
.rate_by_frame(rate_by_frame)
);
endmodule
| 8.359557 |
module test_axis_rate_limit_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
reg [7:0] rate_num = 0;
reg [7:0] rate_denom = 0;
reg rate_by_frame = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready, rate_num, rate_denom,
rate_by_frame);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_rate_limit_64.lxt");
$dumpvars(0, test_axis_rate_limit_64);
end
axis_rate_limit #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Configuration
.rate_num(rate_num),
.rate_denom(rate_denom),
.rate_by_frame(rate_by_frame)
);
endmodule
| 8.359557 |
module test_axis_register;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter REG_TYPE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_register.lxt");
$dumpvars(0, test_axis_register);
end
axis_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.REG_TYPE(REG_TYPE)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 8.117412 |
module test_axis_register_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter REG_TYPE = 2;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_register_64.lxt");
$dumpvars(0, test_axis_register_64);
end
axis_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.REG_TYPE(REG_TYPE)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 8.117412 |
module test_axis_srl_fifo;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, count);
// dump file
$dumpfile("test_axis_srl_fifo.lxt");
$dumpvars(0, test_axis_srl_fifo);
end
axis_srl_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.count(count)
);
endmodule
| 7.803038 |
module test_axis_srl_fifo_64;
// Parameters
parameter DEPTH = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire [2:0] count;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser, count);
// dump file
$dumpfile("test_axis_srl_fifo_64.lxt");
$dumpvars(0, test_axis_srl_fifo_64);
end
axis_srl_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.count(count)
);
endmodule
| 7.803038 |
module test_axis_srl_register;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_srl_register.lxt");
$dumpvars(0, test_axis_srl_register);
end
axis_srl_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 7.803038 |
module test_axis_srl_register_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_srl_register_64.lxt");
$dumpvars(0, test_axis_srl_register_64);
end
axis_srl_register #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 7.803038 |
module test_axis_stat_counter;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter TAG_ENABLE = 1;
parameter TAG_WIDTH = 16;
parameter TICK_COUNT_ENABLE = 1;
parameter TICK_COUNT_WIDTH = 32;
parameter BYTE_COUNT_ENABLE = 1;
parameter BYTE_COUNT_WIDTH = 32;
parameter FRAME_COUNT_ENABLE = 1;
parameter FRAME_COUNT_WIDTH = 32;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] monitor_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] monitor_axis_tkeep = 0;
reg monitor_axis_tvalid = 0;
reg monitor_axis_tready = 0;
reg monitor_axis_tlast = 0;
reg monitor_axis_tuser = 0;
reg m_axis_tready = 0;
reg [TAG_WIDTH-1:0] tag = 0;
reg trigger = 0;
// Outputs
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, monitor_axis_tdata, monitor_axis_tkeep,
monitor_axis_tvalid, monitor_axis_tready, monitor_axis_tlast, monitor_axis_tuser,
m_axis_tready, tag, trigger);
$to_myhdl(m_axis_tdata, m_axis_tvalid, m_axis_tlast, m_axis_tuser, busy);
// dump file
$dumpfile("test_axis_stat_counter.lxt");
$dumpvars(0, test_axis_stat_counter);
end
axis_stat_counter #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.TAG_ENABLE(TAG_ENABLE),
.TAG_WIDTH(TAG_WIDTH),
.TICK_COUNT_ENABLE(TICK_COUNT_ENABLE),
.TICK_COUNT_WIDTH(TICK_COUNT_WIDTH),
.BYTE_COUNT_ENABLE(BYTE_COUNT_ENABLE),
.BYTE_COUNT_WIDTH(BYTE_COUNT_WIDTH),
.FRAME_COUNT_ENABLE(FRAME_COUNT_ENABLE),
.FRAME_COUNT_WIDTH(FRAME_COUNT_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// axi monitor input
.monitor_axis_tkeep(monitor_axis_tkeep),
.monitor_axis_tvalid(monitor_axis_tvalid),
.monitor_axis_tready(monitor_axis_tready),
.monitor_axis_tlast(monitor_axis_tlast),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
// configuration
.tag(tag),
.trigger(trigger),
// status
.busy(busy)
);
endmodule
| 7.106469 |
module test_axis_switch_4x4;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT + 1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter S_REG_TYPE = 0;
parameter M_REG_TYPE = 2;
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_switch_4x4.lxt");
$dumpvars(0, test_axis_switch_4x4);
end
axis_switch #(
.M_COUNT(M_COUNT),
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 8.636189 |
module test_axis_switch_4x4_64;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT + 1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter S_REG_TYPE = 0;
parameter M_REG_TYPE = 2;
parameter ARB_TYPE = "ROUND_ROBIN";
parameter LSB_PRIORITY = "HIGH";
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tid, s_axis_tdest, s_axis_tuser, m_axis_tready);
$to_myhdl(s_axis_tready, m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid,
m_axis_tdest, m_axis_tuser);
// dump file
$dumpfile("test_axis_switch_4x4_64.lxt");
$dumpvars(0, test_axis_switch_4x4_64);
end
axis_switch #(
.M_COUNT(M_COUNT),
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE(ARB_TYPE),
.LSB_PRIORITY(LSB_PRIORITY)
) UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 8.636189 |
module test_axis_tap;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] tap_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] tap_axis_tkeep = 0;
reg tap_axis_tvalid = 0;
reg tap_axis_tready = 0;
reg tap_axis_tlast = 0;
reg [ID_WIDTH-1:0] tap_axis_tid = 0;
reg [DEST_WIDTH-1:0] tap_axis_tdest = 0;
reg [USER_WIDTH-1:0] tap_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, tap_axis_tdata, tap_axis_tkeep, tap_axis_tvalid,
tap_axis_tready, tap_axis_tlast, tap_axis_tid, tap_axis_tdest, tap_axis_tuser,
m_axis_tready);
$to_myhdl(m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid, m_axis_tdest,
m_axis_tuser);
// dump file
$dumpfile("test_axis_tap.lxt");
$dumpvars(0, test_axis_tap);
end
axis_tap #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK)
) UUT (
.clk(clk),
.rst(rst),
// AXI tap
.tap_axis_tdata(tap_axis_tdata),
.tap_axis_tkeep(tap_axis_tkeep),
.tap_axis_tvalid(tap_axis_tvalid),
.tap_axis_tready(tap_axis_tready),
.tap_axis_tlast(tap_axis_tlast),
.tap_axis_tid(tap_axis_tid),
.tap_axis_tdest(tap_axis_tdest),
.tap_axis_tuser(tap_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 7.293732 |
module test_axis_tap_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH > 8);
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] tap_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] tap_axis_tkeep = 0;
reg tap_axis_tvalid = 0;
reg tap_axis_tready = 0;
reg tap_axis_tlast = 0;
reg [ID_WIDTH-1:0] tap_axis_tid = 0;
reg [DEST_WIDTH-1:0] tap_axis_tdest = 0;
reg [USER_WIDTH-1:0] tap_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, tap_axis_tdata, tap_axis_tkeep, tap_axis_tvalid,
tap_axis_tready, tap_axis_tlast, tap_axis_tid, tap_axis_tdest, tap_axis_tuser,
m_axis_tready);
$to_myhdl(m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tid, m_axis_tdest,
m_axis_tuser);
// dump file
$dumpfile("test_axis_tap_64.lxt");
$dumpvars(0, test_axis_tap_64);
end
axis_tap #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK)
) UUT (
.clk(clk),
.rst(rst),
// AXI tap
.tap_axis_tdata(tap_axis_tdata),
.tap_axis_tkeep(tap_axis_tkeep),
.tap_axis_tvalid(tap_axis_tvalid),
.tap_axis_tready(tap_axis_tready),
.tap_axis_tlast(tap_axis_tlast),
.tap_axis_tid(tap_axis_tid),
.tap_axis_tdest(tap_axis_tdest),
.tap_axis_tuser(tap_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
| 7.293732 |
module test_axis_wb_master_8_32;
// Parameters
parameter IMPLICIT_FRAMING = 0;
parameter COUNT_SIZE = 16;
parameter AXIS_DATA_WIDTH = 8;
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8);
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 32;
parameter WB_SELECT_WIDTH = (WB_DATA_WIDTH / 8);
parameter READ_REQ = 8'hA1;
parameter WRITE_REQ = 8'hA2;
parameter READ_RESP = 8'hA3;
parameter WRITE_RESP = 8'hA4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
// Outputs
wire input_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
wire [WB_DATA_WIDTH-1:0] wb_dat_o;
wire wb_we_o;
wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, input_axis_tdata, input_axis_tkeep, input_axis_tvalid,
input_axis_tlast, input_axis_tuser, output_axis_tready, wb_dat_i, wb_ack_i,
wb_err_i);
$to_myhdl(input_axis_tready, output_axis_tdata, output_axis_tkeep, output_axis_tvalid,
output_axis_tlast, output_axis_tuser, wb_adr_o, wb_dat_o, wb_we_o, wb_sel_o,
wb_stb_o, wb_cyc_o, busy);
// dump file
$dumpfile("test_axis_wb_master_8_32.lxt");
$dumpvars(0, test_axis_wb_master_8_32);
end
axis_wb_master #(
.IMPLICIT_FRAMING(IMPLICIT_FRAMING),
.COUNT_SIZE(COUNT_SIZE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.WB_DATA_WIDTH(WB_DATA_WIDTH),
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.WB_SELECT_WIDTH(WB_SELECT_WIDTH),
.READ_REQ(READ_REQ),
.WRITE_REQ(WRITE_REQ),
.READ_RESP(READ_RESP),
.WRITE_RESP(WRITE_RESP)
) UUT (
.clk(clk),
.rst(rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
.busy(busy)
);
endmodule
| 8.398776 |
module test_axis_wb_master_8_32_16;
// Parameters
parameter IMPLICIT_FRAMING = 0;
parameter COUNT_SIZE = 16;
parameter AXIS_DATA_WIDTH = 8;
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8);
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 31;
parameter WB_SELECT_WIDTH = 2;
parameter READ_REQ = 8'hA1;
parameter WRITE_REQ = 8'hA2;
parameter READ_RESP = 8'hA3;
parameter WRITE_RESP = 8'hA4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
// Outputs
wire input_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
wire [WB_DATA_WIDTH-1:0] wb_dat_o;
wire wb_we_o;
wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, input_axis_tdata, input_axis_tkeep, input_axis_tvalid,
input_axis_tlast, input_axis_tuser, output_axis_tready, wb_dat_i, wb_ack_i,
wb_err_i);
$to_myhdl(input_axis_tready, output_axis_tdata, output_axis_tkeep, output_axis_tvalid,
output_axis_tlast, output_axis_tuser, wb_adr_o, wb_dat_o, wb_we_o, wb_sel_o,
wb_stb_o, wb_cyc_o, busy);
// dump file
$dumpfile("test_axis_wb_master_8_32_16.lxt");
$dumpvars(0, test_axis_wb_master_8_32_16);
end
axis_wb_master #(
.IMPLICIT_FRAMING(IMPLICIT_FRAMING),
.COUNT_SIZE(COUNT_SIZE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.WB_DATA_WIDTH(WB_DATA_WIDTH),
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.WB_SELECT_WIDTH(WB_SELECT_WIDTH),
.READ_REQ(READ_REQ),
.WRITE_REQ(WRITE_REQ),
.READ_RESP(READ_RESP),
.WRITE_RESP(WRITE_RESP)
) UUT (
.clk(clk),
.rst(rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
.busy(busy)
);
endmodule
| 8.398776 |
module test_axis_wb_master_8_32_imp;
// Parameters
parameter IMPLICIT_FRAMING = 1;
parameter COUNT_SIZE = 16;
parameter AXIS_DATA_WIDTH = 8;
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH / 8);
parameter WB_DATA_WIDTH = 32;
parameter WB_ADDR_WIDTH = 32;
parameter WB_SELECT_WIDTH = (WB_DATA_WIDTH / 8);
parameter READ_REQ = 8'hA1;
parameter WRITE_REQ = 8'hA2;
parameter READ_RESP = 8'hA3;
parameter WRITE_RESP = 8'hA4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [AXIS_DATA_WIDTH-1:0] input_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] input_axis_tkeep = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
reg [WB_DATA_WIDTH-1:0] wb_dat_i = 0;
reg wb_ack_i = 0;
reg wb_err_i = 0;
// Outputs
wire input_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] output_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] output_axis_tkeep;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire [WB_ADDR_WIDTH-1:0] wb_adr_o;
wire [WB_DATA_WIDTH-1:0] wb_dat_o;
wire wb_we_o;
wire [WB_SELECT_WIDTH-1:0] wb_sel_o;
wire wb_stb_o;
wire wb_cyc_o;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, input_axis_tdata, input_axis_tkeep, input_axis_tvalid,
input_axis_tlast, input_axis_tuser, output_axis_tready, wb_dat_i, wb_ack_i,
wb_err_i);
$to_myhdl(input_axis_tready, output_axis_tdata, output_axis_tkeep, output_axis_tvalid,
output_axis_tlast, output_axis_tuser, wb_adr_o, wb_dat_o, wb_we_o, wb_sel_o,
wb_stb_o, wb_cyc_o, busy);
// dump file
$dumpfile("test_axis_wb_master_8_32_imp.lxt");
$dumpvars(0, test_axis_wb_master_8_32_imp);
end
axis_wb_master #(
.IMPLICIT_FRAMING(IMPLICIT_FRAMING),
.COUNT_SIZE(COUNT_SIZE),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.WB_DATA_WIDTH(WB_DATA_WIDTH),
.WB_ADDR_WIDTH(WB_ADDR_WIDTH),
.WB_SELECT_WIDTH(WB_SELECT_WIDTH),
.READ_REQ(READ_REQ),
.WRITE_REQ(WRITE_REQ),
.READ_RESP(READ_RESP),
.WRITE_RESP(WRITE_RESP)
) UUT (
.clk(clk),
.rst(rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tkeep(input_axis_tkeep),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
.output_axis_tdata(output_axis_tdata),
.output_axis_tkeep(output_axis_tkeep),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.wb_adr_o(wb_adr_o),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_we_o(wb_we_o),
.wb_sel_o(wb_sel_o),
.wb_stb_o(wb_stb_o),
.wb_ack_i(wb_ack_i),
.wb_err_i(wb_err_i),
.wb_cyc_o(wb_cyc_o),
.busy(busy)
);
endmodule
| 8.398776 |
module test_axis_xgmii_rx_32;
// Parameters
parameter DATA_WIDTH = 32;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 32'h07070707;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 4'hf;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
// Outputs
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire start_packet;
wire error_bad_frame;
wire error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, xgmii_rxd, xgmii_rxc, ptp_ts);
$to_myhdl(m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tuser, start_packet,
error_bad_frame, error_bad_fcs);
// dump file
$dumpfile("test_axis_xgmii_rx_32.lxt");
$dumpvars(0, test_axis_xgmii_rx_32);
end
axis_xgmii_rx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.ptp_ts(ptp_ts),
.start_packet(start_packet),
.error_bad_frame(error_bad_frame),
.error_bad_fcs(error_bad_fcs)
);
endmodule
| 7.196523 |
module test_axis_xgmii_rx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 64'h0707070707070707;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 8'hff;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
// Outputs
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire [1:0] start_packet;
wire error_bad_frame;
wire error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, xgmii_rxd, xgmii_rxc, ptp_ts);
$to_myhdl(m_axis_tdata, m_axis_tkeep, m_axis_tvalid, m_axis_tlast, m_axis_tuser, start_packet,
error_bad_frame, error_bad_fcs);
// dump file
$dumpfile("test_axis_xgmii_rx_64.lxt");
$dumpvars(0, test_axis_xgmii_rx_64);
end
axis_xgmii_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser),
.ptp_ts(ptp_ts),
.start_packet(start_packet),
.error_bad_frame(error_bad_frame),
.error_bad_fcs(error_bad_fcs)
);
endmodule
| 7.196523 |
module test_axis_xgmii_tx_32;
// Parameters
parameter DATA_WIDTH = 32;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE;
parameter PTP_TAG_WIDTH = 16;
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag;
wire m_axis_ptp_ts_valid;
wire start_packet;
wire error_underflow;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser, ptp_ts, ifg_delay);
$to_myhdl(s_axis_tready, xgmii_txd, xgmii_txc, m_axis_ptp_ts, m_axis_ptp_ts_tag,
m_axis_ptp_ts_valid, start_packet, error_underflow);
// dump file
$dumpfile("test_axis_xgmii_tx_32.lxt");
$dumpvars(0, test_axis_xgmii_tx_32);
end
axis_xgmii_tx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(start_packet),
.error_underflow(error_underflow)
);
endmodule
| 7.196523 |
module test_axis_xgmii_tx_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH / 8);
parameter CTRL_WIDTH = (DATA_WIDTH / 8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_TS_ENABLE = 0;
parameter PTP_TS_WIDTH = 96;
parameter PTP_TAG_ENABLE = PTP_TS_ENABLE;
parameter PTP_TAG_WIDTH = 16;
parameter USER_WIDTH = (PTP_TAG_ENABLE ? PTP_TAG_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire [PTP_TS_WIDTH-1:0] m_axis_ptp_ts;
wire [PTP_TAG_WIDTH-1:0] m_axis_ptp_ts_tag;
wire m_axis_ptp_ts_valid;
wire [1:0] start_packet;
wire error_underflow;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, s_axis_tdata, s_axis_tkeep, s_axis_tvalid, s_axis_tlast,
s_axis_tuser, ptp_ts, ifg_delay);
$to_myhdl(s_axis_tready, xgmii_txd, xgmii_txc, m_axis_ptp_ts, m_axis_ptp_ts_tag,
m_axis_ptp_ts_valid, start_packet, error_underflow);
// dump file
$dumpfile("test_axis_xgmii_tx_64.lxt");
$dumpvars(0, test_axis_xgmii_tx_64);
end
axis_xgmii_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_ENABLE(PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.USER_WIDTH(USER_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(ptp_ts),
.m_axis_ptp_ts(m_axis_ptp_ts),
.m_axis_ptp_ts_tag(m_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(m_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(start_packet),
.error_underflow(error_underflow)
);
endmodule
| 7.196523 |
module test_barrel_shift_mips ();
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 5;
parameter lo_l = 0;
parameter lo_r = 1;
parameter al_r = 2;
parameter ci_r = 3;
reg [(DATA_WIDTH -1):0] data_in;
reg [(ADDR_WIDTH -1):0] shift_count;
reg [1:0] op;
wire [(DATA_WIDTH -1):0] data_out;
barrel_shift_mips t1 (
.data_in(data_in),
.shift_count(shift_count),
.op(op),
.data_out(data_out)
);
initial begin
data_in = 32'h12345678;
shift_count = 4;
op = lo_l;
#1 shift_count = 3;
op = lo_r;
#1 data_in = 32'hf2345678;
shift_count = 2;
op = al_r;
#1 shift_count = 1;
op = ci_r;
#1 $stop;
end
endmodule
| 8.00441 |
module test_base;
reg [2:0] a;
reg [3:0] b;
reg [4:0] c;
reg [4:0] d;
// parte principal
initial begin
$display("Exemplo 03_01 - xxx yyy zzz - 999999");
$display("Test number system");
a = 5;
b = 5;
c = 5;
$display("\nPositive value");
$display("a = %d = %3b", a, a);
$display("b = %d = %4b", b, b);
$display("c = %d = %5b", c, c);
a = -5;
b = -5;
c = -5;
$display("\nNegative value");
$display("a = %d = %3b", a, a);
$display("b = %d = %4b", b, b);
$display("c = %d = %5b", c, c);
a = ~5 + 1;
b = ~5 + 1;
c = ~5 + 1;
$display("\nNegative mixed expression");
$display("a = %d = %3b", a, a);
$display("b = %d = %4b", b, b);
$display("c = %d = %5b", c, c);
a = 5 + 3;
b = 5 + 3;
c = 10 - 5 + 25 + 3 + 1;
$display("\nOverflow");
$display("a = %d = %3b", a, a);
$display("b = %d = %4b", b, b);
$display("c = %d = %5b", c, c);
$display("\nComplement");
$display("0= %d = %3b = %3b", ~1, (1 - 1), ~1);
$display("1= %d = %3b = %3b", ~0, (2 - 1), ~0);
$display("2= %d = %3b = %3b", (1 + 1), (3 - 1), ~0 + ~0);
end
endmodule
| 6.746738 |
module: BlockChecker
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bc;
// Inputs
reg clk;
reg reset;
reg [7:0] in;
// Outputs
wire result;
// Instantiate the Unit Under Test (UUT)
BlockChecker uut (
.clk(clk),
.reset(reset),
.in(in),
.result(result)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
in = 0;
// Wait 100 ns for global reset to finish
//#100;
in = "b";
#2 in = "e";
#2 in = "g";
#2 in = "i";
#2 in = "n";
#2 in = " ";
#2 in = "e";
#2 in = "n";
#2 in = "d";
#2 in = " ";
#2 in = "e";
#2 in = "n";
#2 in = "d";
#2 in = " ";
#2 in = "b";
#2 in = "e";
#2 in = "g";
#2 in = "i";
#2 in = "n";
#2 in = " ";
// Add stimulus here
end
always #1 clk = ~clk;
endmodule
| 6.745481 |
module Test_BCDtoSevenSeg ();
//Inputs
reg [3:0] BCD;
//Outputs
wire [6:0] SEG;
//Instantiate
BCDtoSevenSeg uut (
.BCD(BCD),
.SEG(SEG)
);
//begin test
initial begin
#100 BCD = 4'd1;
#10 BCD = 4'd3;
#10 BCD = 4'd6;
#10 BCD = 4'd9;
end
endmodule
| 6.584545 |
module: main_comparator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench;
// Inputs
reg [2:0] A;
reg [2:0] B;
// Outputs
wire greater;
wire equal;
wire smaller;
// Instantiate the Unit Under Test (UUT)
main_comparator uut (
.A(A),
.B(B),
.greater(greater),
.equal(equal),
.smaller(smaller)
);
integer counter = 0;
integer counter2 = 0;
initial
begin
for (counter = 0; counter < 8; counter = counter + 1)
begin
$display("********************");
for (counter2 = 0; counter2 < 8; counter2 = counter2 + 1)
begin
A = counter;
B = counter2;
#10
$display("A = %d, B = %d, greater = %b, equal = %b, smaller = %b", A, B, greater, equal, smaller);
end
end
end
endmodule
| 7.228589 |
module tb_PC (
//Declaraci�n de wires y Registros
reg clk = 1’b0;
//Cuerpo del Modulo
/* Instanciacion del Modulo asignado */
PC DUV (
//Conexiones
.CLK (clk)
);
//Ingreso de Valores
always @*
#100 clk != clk;
endmodule
| 7.951843 |
module tb_General (
//Declaraci�n de wires y Registros
//Entradas
reg [15:0]op1;
reg [15:0]op2;
reg [2:0]sel;
//Salidas
wire [31:0]res;
wire flag;
//Cuerpo del Modulo
// Instanciacion del Modulo asignado
<Modulo> <Instancia> (
//Conexiones
.i_op1 (op1),
.i_op2 (op2),
.selector (sel),
.Result_op (res),
.Zeroflag (flag)
);
//Ingreso de Valores
initial
begin
//ADD
op1 = 16'd10;
op2 = 16'd22;
sel = 3'b000;
#100;
//SUB
op1 = 16'd20;
op2 = 16'd20;
sel = 3'b001;
#100;
$stop;
end
endmodule
| 7.55327 |
module: adder_2bits_non_delay
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_2bit_non_delay;
// Inputs
reg Cin;
reg A;
reg B;
reg select;
// Outputs
wire Sum;
wire Cout;
// Instantiate the Unit Under Test (UUT)
adder_2bits_non_delay uut (
.Cin(Cin),
.A(A),
.B(B),
.select(select),
.Sum(Sum),
.Cout(Cout)
);
initial begin
// Initialize Inputs
Cin = 0;
A = 0;
B = 0;
select = 0;
// Wait 100 ns for global reset to finish
A = 2'b01; B = 2'b01;
# 200
A = 2'b11; B = 2'b10;
# 200
A = 2'b11; B = 2'b11;
# 200
A = 2'b10; B = 2'b01;
select = 1;
A = 2'b01; B = 2'b01;
# 200
A = 2'b11; B = 2'b10;
# 200
A = 2'b11; B = 2'b11;
# 200
A = 2'b10; B = 2'b01;
$finish;
end
endmodule
| 6.660157 |
module: Comparator_32_bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_32bit_comparator;
// Inputs
reg clk;
reg mode;
reg op;
reg rst;
reg [31:0] a;
reg [31:0] b;
// Outputs
wire L;
wire E;
wire G;
// Instantiate the Unit Under Test (UUT)
Comparator_32_bit uut (
.clk(clk),
.mode(mode),
.op(op),
.rst(rst),
.a(a),
.b(b),
.L(L),
.E(E),
.G(G)
);
initial begin
// Initialize Inputs
clk = 0;
mode = 0;
op = 0;
rst = 0;
a = 32'b10010010100100101011011011010010;
b = 32'b10010010100100101001001111010010;
#5 mode = 1;
#1 rst = 1;
#1 rst = 0;
#255
op = 1;
#1
$finish;
end
always #4 clk = ~clk;
endmodule
| 7.72212 |
module test_bench_3_stage_pipeline;
// Inputs
reg clk;
reg rst;
reg fileid;
// Outputs
wire [15:0] PCOUT;
wire [15:0] INST;
wire [2:0] aluop;
wire [15:0] rdata1;
wire [15:0] rdata2;
wire [15:0] rdata1_ID_EXE;
wire [15:0] rdata2_ID_EXE;
wire [2:0] aluop_ID_EXE;
wire [3:0] waddr_out_ID_EXE;
wire [15:0] aluout;
wire [15:0] aluout_EXE_WB;
wire [3:0] waddr_out_EXE_WB;
// Instantiate the Unit Under Test (UUT)
pipelined_regfile_3stage uut (
.clk(clk),
.rst(rst),
.fileid(fileid),
.PCOUT(PCOUT),
.INST(INST),
.aluop(aluop),
.rdata1(rdata1),
.rdata2(rdata2),
.rdata1_ID_EXE(rdata1_ID_EXE),
.rdata2_ID_EXE(rdata2_ID_EXE),
.aluop_ID_EXE(aluop_ID_EXE),
.waddr_out_ID_EXE(waddr_out_ID_EXE),
.aluout(aluout),
.aluout_EXE_WB(aluout_EXE_WB),
.waddr_out_EXE_WB(waddr_out_EXE_WB)
);
always #15 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
fileid = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#25 rst = 1;
#25 rst = 0;
end
endmodule
| 6.565481 |
module: adder_4bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_4bit_adder;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg select;
// Outputs
wire [3:0] sum;
wire carry_out;
// Instantiate the Unit Under Test (UUT)
adder_4bits uut (
.A(A),
.B(B),
.select(select),
.sum(sum),
.carry_out(carry_out)
);
initial
begin
// Initialize Inputs
select = 0;
// Start giving numbers
// Sumation
A = 4'b0001; B = 4'b0001;
# 200
A = 4'b0011; B = 4'b1010;
# 200
A = 4'b1011; B = 4'b1010;
# 200
A = 4'b1111; B = 4'b1111;
# 200
// Start giving numbers
// Subtractor
select = 1;
A = 4'b0001; B = 4'b0001;
# 200
A = 4'b0011; B = 4'b1010;
# 200
A = 4'b1011; B = 4'b1010;
# 200
A = 4'b1111; B = 4'b1111;
# 200
$finish;
end
endmodule
| 7.207117 |
module: adder_4bits_non_delay
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_4bit_adder_non_delay;
// Inputs
reg [3:0] A;
reg [3:0] B;
reg select;
// Outputs
wire [3:0] sum;
wire carry_out;
// Instantiate the Unit Under Test (UUT)
adder_4bits_non_delay uut (
.A(A),
.B(B),
.select(select),
.sum(sum),
.carry_out(carry_out)
);
initial
begin
// Initialize Inputs
select = 0;
// Start giving numbers
// Sumation
A = 4'b0001; B = 4'b0001;
# 200
A = 4'b0011; B = 4'b1010;
# 200
A = 4'b1011; B = 4'b1010;
# 200
A = 4'b1111; B = 4'b1111;
# 200
// Start giving numbers
// Subtractor
select = 1;
A = 4'b0001; B = 4'b0001;
# 200
A = 4'b0011; B = 4'b1010;
# 200
A = 4'b1011; B = 4'b1010;
# 200
A = 4'b1111; B = 4'b1111;
# 200
$finish;
end
endmodule
| 7.339953 |
module: shift_register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_8bit_shift_register;
// Inputs
reg clk;
reg reset;
reg mode;
reg sin;
reg [7:0] p_in;
// Outputs
wire sout;
wire [7:0] status;
// Instantiate the Unit Under Test (UUT)
shift_register uut (
.clk(clk),
.reset(reset),
.mode(mode),
.sin(sin),
.p_in(p_in),
.sout(sout),
.status(status)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
mode = 0;
sin = 0;
p_in = 8'b10010010;
#5 mode = 1;
#64
$finish;
end
always #4 clk = ~clk;
endmodule
| 7.854242 |
module test_bench_alu;
wire clock;
wire enable;
wire [2:0] funct3;
wire [6:0] funct7;
wire [31:0] register_data_1;
wire [31:0] register_data_2;
wire [31:0] register_data_out;
alu alu_0 (
clock,
enable,
funct3,
funct7,
register_data_1,
register_data_2,
register_data_out
);
test_case_alu test_alu_0 (
clock,
enable,
funct3,
funct7,
register_data_1,
register_data_2,
register_data_out
);
endmodule
| 6.965901 |
module test_bench_alu_base;
wire clock;
wire enable;
wire [ 2:0] funct3;
wire [31:0] register_data_1;
wire [31:0] register_data_2;
wire [31:0] register_data_out;
alu_base alu_base_rv32i (
clock,
enable,
funct3,
register_data_1,
register_data_2,
register_data_out
);
test_alu_base test_alu_base_rv32i (
clock,
enable,
funct3,
register_data_1,
register_data_2,
register_data_out
);
endmodule
| 6.965901 |
module: bit_serial_adder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_bit_serial_adder;
// Inputs
reg clk;
reg rst;
reg mode;
reg [7:0] a;
reg [7:0] b;
// Outputs
wire [7:0] ans;
wire carry;
// Instantiate the Unit Under Test (UUT)
bit_serial_adder uut (
.clk(clk),
.rst(rst),
.mode(mode),
.a(a),
.b(b),
.carry(carry),
.ans(ans)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
mode = 0;
a = 8'b00110011;
b = 8'b10010010;
#5
rst = 1;
mode = 1;
#1
rst = 0;
#63
$finish;
// Add stimulus here
end
always #4 clk = ~clk;
endmodule
| 6.723448 |
module: controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_controller;
// Inputs
reg [31:0] instr;
// Outputs
wire mem_read;
wire mem_write;
wire reg_write;
wire mem_to_reg;
wire [1:0] w_select;
wire j_select;
wire [4:0] ALU_C;
wire comp;
wire [1:0] flag_select;
wire jal;
wire [2:0] jmp_type;
wire [1:0] b_src;
wire jmp_reg;
wire jmp_instr;
// Instantiate the Unit Under Test (UUT)
controller uut (
.instr(instr),
.mem_read(mem_read),
.mem_write(mem_write),
.reg_write(reg_write),
.mem_to_reg(mem_to_reg),
.w_select(w_select),
.j_select(j_select),
.ALU_C(ALU_C),
.comp(comp),
.flag_select(flag_select),
.jal(jal),
.jmp_type(jmp_type),
.b_src(b_src),
.jmp_reg(jmp_reg),
.jmp_instr(jmp_instr)
);
initial begin
// Initialize Inputs
instr = 32'd0;
// Wait 100 ns for global reset to finish
#100;
instr = 32'b01000000000000010000000000000000; //lw
#100
instr = 32'b00000000011000110000000000000100; //xor
#100
instr = 32'b00000000010000010000000000000001; //add
#100
instr = 32'b00000000100000100000000000000010; //comp
#100
instr = 32'b11011000011000000000000000111000; //bz
#100
instr = 32'b11010100011000000000000000110000; //bltz
#100
instr = 32'b11000000000000000000000000001000; //b
#100
$finish;
end
endmodule
| 7.107088 |
module: crc_192bits
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module text_crc192;
// Inputs
reg [175:0] data_in;
reg clk;
// Outputs
wire [191:0]data_out;
// Instantiate the Unit Under Test (UUT)
crc_192bits uut (
.data_in(data_in),
.clk(clk),
.data_out(data_out)
);
initial begin
// Initialize Inputs
data_in = 176'hABCDEF0123456789FEDCBA9876543210ABCDEF123456;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
initial
#20000 $finish;
always
#200 clk=~clk;
endmodule
| 6.630656 |
module: DataMemory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_data_memory;
// Inputs
reg clka;
reg ena;
reg [3:0] wea;
reg [31:0] addra;
reg [31:0] dina;
// Outputs
wire [31:0] douta;
// Instantiate the Unit Under Test (UUT)
DataMemory uut (
.clka(clka),
.ena(ena),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta)
);
initial begin
// Initialize Inputs
clka = 0;
ena = 1'b1;
wea = 4'b0000;
addra = 32'b00000000000000000000000000000000;
dina = 0;
#9
wea = 4'b1111;
addra = 32'b00000000000000000000000000000000;
dina = 32'd54;
#20
wea = 4'b0000;
#20
$finish;
end
always #10 clka = ~clka;
endmodule
| 7.205301 |
module: DFF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_DFF;
// Inputs
reg clk;
reg reset;
reg in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
DFF uut (
.clk(clk),
.reset(reset),
.in(in),
.out(out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
in = 0;
#4 in = 1;
#6 in = 0;
$finish;
end
always #3 clk = ~clk;
endmodule
| 7.075697 |
module: input_shift_register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_input_shift_register;
// Inputs
reg clk;
reg mode;
reg sin;
reg [7:0] p_in;
// Outputs
wire sout;
wire [7:0] status;
// Instantiate the Unit Under Test (UUT)
input_shift_register uut (
.clk(clk),
.mode(mode),
.sin(sin),
.p_in(p_in),
.sout(sout),
.status(status)
);
initial begin
// Initialize Inputs
clk = 0;
mode = 0;
sin = 0;
p_in = 8'b10010010;
#5 mode = 1;
#64
$finish;
end
always #4 clk = ~clk;
endmodule
| 7.303565 |
module: InstructionMemory
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_InstructionMemory;
// Inputs
reg clka;
reg ena;
reg [31:0] addra;
// Outputs
wire [31:0] douta;
// Instantiate the Unit Under Test (UUT)
InstructionMemory uut (
.clka(clka),
.ena(ena),
.addra(addra),
.douta(douta)
);
initial begin
// Initialize Inputs
clka = 0;
ena = 1'b1;
addra = 32'd8;
#40
$finish;
end
always #10 clka = ~clka;
endmodule
| 6.522495 |
module: KGP_RISC_Processor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_KGP_RISC;
// Inputs
reg clka;
reg f_clka;
reg reset;
// Outputs
wire [4:0] write_addr;
wire [31:0] ALUres;
wire [31:0] finalPC;
// Instantiate the Unit Under Test (UUT)
KGP_RISC_Processor uut (
.clka(clka),
.f_clka(f_clka),
.reset(reset),
.write_addr(write_addr),
.ALUres(ALUres),
.finalPC(finalPC)
);
initial begin
// Initialize Inputs
clka = 0;
f_clka = 0;
reset = 0;
#19;
reset = 1;
#50;
reset = 0;
end
always #1 f_clka = ~f_clka;
always #20 clka = ~clka;
endmodule
| 6.688854 |
module: lfsr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_lfsr;
// Inputs
reg clk;
reg reset;
reg mode;
reg [3:0] p_in;
// Outputs
wire [3:0] status;
// Instantiate the Unit Under Test (UUT)
lfsr uut (
.clk(clk),
.reset(reset),
.mode(mode),
.p_in(p_in),
.status(status)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
mode = 0;
p_in = 4'b1111;
#10
mode = 1;
#95
$finish;
end
always #3 clk = ~clk;
endmodule
| 6.832914 |
module: MOD3_FSM
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_MOD3;
// Inputs
reg in;
reg rst;
reg clk;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
MOD3_FSM uut (
.in(in),
.rst(rst),
.clk(clk),
.out(out)
);
initial begin
// Initialize Inputs
in = 0;
rst = 0;
clk = 0;
#1 rst = 1;
#1 rst = 0;
in = 1;
#6 in = 1;
#6 in = 0;
#6 in = 1;
#6 in = 1;
#6
$finish;
end
always #3 clk = ~clk;
endmodule
| 6.903053 |
module: output_shift_register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_output_shift_register;
// Inputs
reg clk;
reg sin;
// Outputs
wire [7:0] status;
// Instantiate the Unit Under Test (UUT)
output_shift_register uut (
.clk(clk),
.sin(sin),
.status(status)
);
initial begin
// Initialize Inputs
clk = 0;
sin = 1;
#64
$finish;
end
always #4 clk = ~clk;
endmodule
| 7.674591 |
module Test_bench_P1;
reg X, Y, Z, K, M; // Entradas
wire WS_OR2, WS_OR3, WS_OR4, WS_OR5, Wout_7, Wout_8; // Salidas
integer i;
AND_inciso2 Indtance0 (
WS_OR2,
X,
Y,
Z,
K,
M
);
AND_inciso3 Indtance1 (
WS_OR3,
X,
Y,
Z,
K,
M
);
initial begin
// Estímulo
// Para iniciar en 00000
X <= 0;
Y <= 0;
Z <= 0;
K <= 0;
M <= 0;
for (i = 0; i < 32; i = i + 1) begin
{X, Y, Z, K, M} = i;
#10;
end
end
initial begin
$monitor("A continuacion la tabla de verdad usada:");
$monitor("X=%0b Y=%0b Z=%0b K=%0b M=%0b ", X, Y, Z, K, M);
// Crear archivo .vcd para gtkwave
$dumpfile("Prueba_P1.vcd");
$dumpvars(0, Test_bench_P1);
end
endmodule
| 7.195387 |
module test_bench_program_counter;
wire clock;
wire [31:0] instruction;
wire [31:0] pc;
test_case_program_counter test_case_program_counter1 (
clock,
instruction,
pc
);
program_counter program_counter1 (
clock,
instruction,
pc
);
endmodule
| 6.73152 |
module Test_bench1;
//used upper case for signals to avoid confusion
/*reg X, Y,Z ,K, M; // Entradas
wire out_7,S_OR; // Salidas
integer i;*/
m1 Indtance0 (
out_7,
X,
Y,
Z,
K,
M
);
m_1 Indtance1 (
S_OR,
X,
Y,
Z,
K,
M
);
//TABLA Indtance2 ();
reg X, Y, Z, K, M; // Entradas
wire out_7, S_OR; // Salidas
integer i;
initial begin
// Estímulo
// Para iniciar en 00000
X <= 0;
Y <= 0;
Z <= 0;
K <= 0;
M <= 0;
for (i = 0; i < 32; i = i + 1) begin
{X, Y, Z, K, M} = i;
#10;
end
end
initial begin
// $monitor("A=%0b B=%0b C=%0b D=%0b E=%0b F=%0b Fmin=%0b", X,Y,Z,K,M, out_7);
// Crear archivo .vcd para gtkwave
$dumpfile("Prueba_P2.vcd");
$dumpvars(0, Test_bench1);
end
endmodule
| 6.94183 |
module: Shift_Register_32bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_bench_shift_register_32bit;
// Inputs
reg clk;
reg reset;
reg mode;
reg sin;
reg [31:0] p_in;
// Outputs
wire sout;
wire [31:0] status;
// Instantiate the Unit Under Test (UUT)
Shift_Register_32bit uut (
.clk(clk),
.reset(reset),
.mode(mode),
.sin(sin),
.p_in(p_in),
.sout(sout),
.status(status)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
mode = 0;
sin = 0;
p_in = 32'b10010010100100101001001010010010;
#5 mode = 1;
#255
$finish;
end
always #4 clk = ~clk;
endmodule
| 7.521511 |
module test_bench_smart_parking ();
reg entry;
reg [7:0] parking_capacity;
reg exit;
reg [2:0] pattern;
reg [7:0] time_out;
reg [7:0] time_in;
wire [7:0] new_capacity;
wire [7:0] time_total;
wire [3:0] parked;
wire [3:0] empty;
smart_parking smart_parking_tb (
.entry(entry),
.parking_capacity(parking_capacity),
.exit(exit),
.pattern(pattern),
.time_in(time_in),
.time_out(time_out),
.new_capacity(new_capacity),
.time_total(time_total),
.parked(parked),
.empty(empty)
);
initial begin
entry <= 1'b0;
parking_capacity <= 8'b11111111;
exit <= 1'b0;
pattern <= 3'b000;
time_in <= 8'b01010101;
time_out <= 8'b10101010;
#100;
entry <= 1'b1;
parking_capacity <= 8'b11111111;
exit <= 1'b0;
pattern <= 3'b000;
time_in <= 8'b01010000;
time_out <= 8'b10101111;
#100;
entry <= 1'b1;
parking_capacity <= 8'b11111111;
exit <= 1'b1;
pattern <= 3'b000;
time_in <= 8'b10000000;
time_out <= 8'b11110101;
#100;
entry <= 1'b0;
parking_capacity <= 8'b01011111;
exit <= 1'b0;
pattern <= 3'b110;
time_in <= 8'b01010101;
time_out <= 8'b11111111;
#100;
entry <= 1'b1;
parking_capacity <= 8'b01011111;
exit <= 1'b0;
pattern <= 3'b100;
time_in <= 8'b00000000;
time_out <= 8'b10101010;
#100;
entry <= 1'b1;
parking_capacity <= 8'b010111111;
exit <= 1'b1;
pattern <= 3'b001;
time_in <= 8'b01010000;
time_out <= 8'b10111110;
#100;
entry <= 1'b0;
parking_capacity <= 8'b000101000;
exit <= 1'b0;
pattern <= 3'b010;
time_in <= 8'b01010101;
time_out <= 8'b11101010;
#100;
entry <= 1'b1;
parking_capacity <= 8'b000101000;
exit <= 1'b0;
pattern <= 3'b111;
time_in <= 8'b01000101;
time_out <= 8'b10101010;
#100;
entry <= 1'b1;
parking_capacity <= 8'b000101000;
exit <= 1'b1;
pattern <= 3'b001;
time_in <= 8'b01000101;
time_out <= 8'b10101010;
#100;
entry <= 1'b0;
parking_capacity <= 8'b000000001;
exit <= 1'b0;
pattern <= 3'b000;
time_in <= 8'b01010101;
time_out <= 8'b10111110;
#100;
entry <= 1'b1;
parking_capacity <= 8'b000000001;
exit <= 1'b0;
pattern <= 3'b011;
time_in <= 8'b00010101;
time_out <= 8'b10101010;
#100;
entry <= 1'b1;
parking_capacity <= 8'b000000001;
exit <= 1'b1;
pattern <= 3'b100;
time_in <= 8'b01010101;
time_out <= 8'b10111010;
#100;
entry <= 1'b0;
parking_capacity <= 8'b000000000;
exit <= 1'b0;
pattern <= 3'b100;
time_in <= 8'b00010100;
time_out <= 8'b10101010;
#100;
entry <= 1'b1;
parking_capacity <= 8'b000000000;
exit <= 1'b0;
pattern <= 3'b010;
time_in <= 8'b01010001;
time_out <= 8'b10111010;
#100;
entry <= 1'b1;
parking_capacity <= 8'b000000000;
exit <= 1'b1;
pattern = 3'b110;
time_in <= 8'b01001101;
time_out <= 8'b11101010;
#100;
$finish;
end
endmodule
| 7.502347 |
module test_bf16;
reg clock = 1'b0;
reg reset = 1'b0;
reg [2:0] io_opc;
reg [15:0] io_a = 16'h41cc;
wire [15:0] io_b = 16'h41ac;
reg io_in_valid = 1'b1;
reg io_out_ready = 1'b1;
reg io_isSqrt = 1'b0;
reg io_kill = 1'b0;
wire io_in_ready;
wire io_out_valid;
wire [15:0] io_y;
reg [15:0] expected_result = 16'h0000;
// Instantiate the BF16Unit module
BF16Unit uut (
.clock(clock),
.reset(reset),
.io_opc(io_opc),
.io_a(io_a),
.io_b(io_b),
.io_in_valid(io_in_valid),
.io_out_ready(io_out_ready),
.io_y(io_y),
.io_in_ready(io_in_ready),
.io_out_valid(io_out_valid),
.io_isSqrt(io_isSqrt),
.io_kill(io_kill)
);
initial begin
// Initialize the inputs
reset = 1;
#10;
reset = 0;
#10;
io_opc = 3'b000; // Set the opcode (you can choose the appropriate opcode)
#10;
io_opc = 3'b001; // Set the opcode (you can choose the appropriate opcode)
#10;
io_opc = 3'b010; // Set the opcode (you can choose the appropriate opcode)
#10;
io_opc = 3'b011; // Set the opcode (you can choose the appropriate opcode)
#10;
// Check the output 'io_y'
// if (io_y == expected_result) begin
// $display("Test PASSED: io_y is correct.");
// end else begin
// $display("Test FAILED: io_y is incorrect. Expected: %h, Actual: %h", expected_result, io_y);
// end
// Finish the simulation
$finish;
end
always begin
#5 clock = ~clock; // Create a 50MHz signal (divided from 100MHz)
end
// Define the expected result based on the opcode and input values
always @(*) begin
case (io_opc)
3'b000: expected_result = 16'h423c; // Example operation, adjust based on opcode
3'b001: expected_result = 16'h4080; // Another example operation
3'b010: expected_result = 16'h4409; // Another example operation
3'b011: expected_result = 16'h4409; // Another example operation
// Add more cases for other opcodes as needed
default: expected_result = 16'h0000; // Default value for undefined opcode
endcase
if (io_y == expected_result) begin
$display("Test PASSED: io_y is correct.");
end else begin
$display("Test FAILED: io_y is incorrect. Expected: %h, Actual: %h", expected_result, io_y);
end
end
endmodule
| 7.916961 |
module test_bidir_pad;
reg in = 0;
wire out;
reg preio = 0;
wire io;
reg oen = 0;
assign io = oen ? preio : 1'bz;
initial begin
$display("\n----------------------- Bidirectional pad test -------------------------\n");
$dumpfile("tests/vcd/test_bidir_pad.vcd");
$dumpvars(0, test_bidir_pad);
$display("'in' reflected in 'io'");
#2 in = 1;
#2 in = 0;
#2 in = 1;
#2 in = 0;
#2 in = 1;
#2 oen = 1;
$display("Now 'io' is driving 'out'");
#2 preio = 1;
#2 preio = 0;
#2 preio = 1;
#2 preio = 0;
#2 preio = 1;
#2 $finish;
end
bidir_pad bp (
.in (in),
.oen(oen),
.out(out),
.io (io)
);
initial $monitor("At time %t: in: %b out: %b, io: %b", $time, in, out, io);
endmodule
| 6.6368 |
module test_bin2bcd16 ();
reg CLK;
reg RST;
reg en;
reg [15:0] bin;
wire [ 3:0] bcd0;
wire [ 3:0] bcd1;
wire [ 3:0] bcd2;
wire [ 3:0] bcd3;
wire [ 3:0] bcd4;
wire busy;
wire fin;
bin2bcd16 inst (
.CLK(CLK),
.RST(RST),
.en (en),
.bin(bin),
.bcd0(bcd0),
.bcd1(bcd1),
.bcd2(bcd2),
.bcd3(bcd3),
.bcd4(bcd4),
.busy(busy),
.fin (fin)
);
integer i;
initial begin
CLK = 1'b0;
RST = 1'b1;
#10;
RST = 1'b0;
#10;
RST = 1'b1;
#10;
for (i = 0; i != 65535; i = i + 1) begin
en = 1;
bin = i;
#10;
while (!fin) begin
en = 0;
#10;
end
$display("input %d, output %d %d %d %d %d", bin, bcd4, bcd3, bcd2, bcd1, bcd0);
#10;
while (busy) begin
#10;
end
end // for (i=0; i!=65535; i=i+1)
$finish;
end
always #5 CLK <= ~CLK;
endmodule
| 6.783003 |
module test_bin2bcd32 ();
reg CLK;
reg RST;
reg en;
reg [31:0] bin;
wire [ 3:0] bcd0;
wire [ 3:0] bcd1;
wire [ 3:0] bcd2;
wire [ 3:0] bcd3;
wire [ 3:0] bcd4;
wire [ 3:0] bcd5;
wire [ 3:0] bcd6;
wire [ 3:0] bcd7;
wire [ 3:0] bcd8;
wire [ 3:0] bcd9;
wire busy;
wire fin;
bin2bcd32 inst (
.CLK(CLK),
.RST(RST),
.en (en),
.bin(bin),
.bcd0(bcd0),
.bcd1(bcd1),
.bcd2(bcd2),
.bcd3(bcd3),
.bcd4(bcd4),
.bcd5(bcd5),
.bcd6(bcd6),
.bcd7(bcd7),
.bcd8(bcd8),
.bcd9(bcd9),
.busy(busy),
.fin (fin)
);
integer i;
initial begin
CLK = 1'b0;
RST = 1'b1;
#10;
RST = 1'b0;
#10;
RST = 1'b1;
#10;
for (i = 0; i != 10000; i = i + 1) begin
en = 1;
bin = $random;
#10;
while (!fin) begin
en = 0;
#10;
end
$display("input %d, output %d%d%d%d%d%d%d%d%d%d", bin, bcd9, bcd8, bcd7, bcd6, bcd5, bcd4,
bcd3, bcd2, bcd1, bcd0);
#10;
while (busy) begin
#10;
end
end // for (i=0; i!=65535; i=i+1)
$finish;
end
always #5 CLK <= ~CLK;
endmodule
| 6.722439 |
module test_bitblock_1;
parameter period = 5;
reg clk, rstn;
reg [10:0] in1;
wire [3:0] yo;
wire ppo;
wire co;
wire out;
bitblock_1 DUT (
.clk(clk),
.rstn(rstn),
.in(in1[4:0]),
.ppi(in1[5]),
.cci(in1[6]),
.ppo(ppo),
.yi(in1[10:7]),
.yo(yo),
.shift_in(1'b0),
.ci(1'b0),
.co(co),
.out(out)
);
always #period clk = ~clk;
//reset
initial begin
clk = 0;
rstn = 0;
in1 = 0;
#8;
rstn = 1;
#200;
$finish();
end
// stimulus
always @(negedge clk) begin
if (rstn == 1) begin
in1 <= in1 + 1;
end
end
always @(posedge clk) begin
$display("INFO: in1:%b yo:%b, ppo:%b, co:%b, out:%b arrival at %t", in1, yo, ppo, co, out,
$time);
end
// dump
`ifdef DUMP
initial begin
$dumpfile("test.vcd");
$dumpvars();
end
`endif
endmodule
| 7.013348 |
module bno055_module_tb ();
wire scl_1;
wire sda_1;
wire scl_2;
wire sda_2;
reg rstn;
reg purn;
wire rstn_imu;
wire [7:0] data_rx;
wire sys_clk;
wire done;
reg go;
reg read_write_in = 1;
reg [3:0] i2c_count;
reg i2c_ack;
reg [7:0] sda_byte;
reg ac_active;
reg ac_active_cmd;
wire valid_strobe;
integer i;
integer j;
GSR GSR_INST (.GSR(rstn));
PUR PUR_INST (.PUR(purn));
defparam OSCH_inst.NOM_FREQ = "38.00";
OSCH OSCH_inst (
.STDBY(1'b0),
.OSC(sys_clk),
.SEDSTDBY()
);
bno055_driver #(0) bno055 (
.scl_1(scl_1),
.sda_1(sda_1),
.scl_2(scl_2),
.sda_2(sda_2),
.rstn((rstn)),
.rstn_imu(rstn_imu),
.ac_active(ac_active),
.valid_strobe(valid_strobe),
.led_data_out(data_rx),
.sys_clk(sys_clk)
); /* synthesis syn_hier=hard */
;
// Generate a slave ACK every 9 i2c SCL posedges, regardless of what data is on the bus
always @(posedge scl_1, negedge rstn) begin
if (~rstn) begin
i2c_count = 1'b0;
i2c_ack = 1'b0;
end else begin
i2c_count = i2c_count + 1'b1;
if (i2c_count == 4'd9) begin
i2c_ack = 1'b1;
#100 i2c_ack = 1'b0;
i2c_count = 1'b0;
sda_byte = 8'b0;
end else begin
i2c_ack = 1'b0;
sda_byte = {sda_byte[6:0], sda_1};
end
end
end
always @(posedge ac_active_cmd, negedge rstn) begin
if (~rstn) ac_active <= `LOW;
else begin
ac_active <= `LOW;
#1000;
ac_active <= `HIGH;
#100;
ac_active <= `LOW;
#1;
end
end
always @(posedge sys_clk, negedge rstn) begin
if (~rstn) ac_active_cmd <= `LOW;
else if (valid_strobe && (~ac_active_cmd)) ac_active_cmd <= `HIGH;
else if (valid_strobe && (ac_active_cmd)) ac_active_cmd <= `LOW;
else ac_active_cmd <= `LOW;
end
assign (pull1, strong0) scl_1 = 1'b1;
assign (pull1, strong0) sda_1 = (i2c_ack == 1'b1) ? 1'b0 : 1'b1;
initial begin
rstn = 1;
#10 rstn = 0;
#10 rstn = 1;
read_write_in = 0;
for (j = 0; j < 2; j = j + 1) begin
for (i = 0; i < 10; i = i + 1) begin
$display("efb_registers %1d EFB#%1d = %h", i[4:0], (j[4:0] + 1),
bno055.i2c.efb_registers[i][j]);
end
end
#1_000_00000;
$stop;
end
endmodule
| 7.052182 |
module test_board (
input rxp_tx,
input rxn_tx,
output txp_tx,
output txn_tx,
input [7:0] rxp_rx,
input [7:0] rxn_rx,
input [7:0] txp_rx,
input [7:0] txn_rx
);
parameter BCLK_PERIOD = 8;
reg bclk;
initial bclk = 0;
always #(BCLK_PERIOD / 2) bclk = ~bclk;
wire [3:0] mgtclk_p;
wire [3:0] mgtclk_n;
top #(
.SIMULATION_P(1)
) u_top (
.bclk(bclk),
.mgtclk_p_in(mgtclk_p),
.mgtclk_n_in(mgtclk_n),
.mgtclk_p_out(mgtclk_p),
.mgtclk_n_out(mgtclk_n),
.mod0_tx(),
.mod1_tx(),
.mod2_tx(),
.rx_loss_tx(),
.tx_fault_tx(),
.tx_dis_tx(),
.rxp_tx(rxp_tx),
.rxn_tx(rxn_tx),
.txp_tx(txp_tx),
.txn_tx(txn_tx),
.mod0_rx(),
.mod1_rx(),
.mod2_rx(),
.rx_loss_rx(),
.tx_fault_rx(),
.tx_dis_rx(),
.rxp_rx(rxp_rx),
.rxn_rx(rxn_rx),
.txp_rx(txp_rx),
.txn_rx(txn_rx)
);
endmodule
| 6.534454 |
module test_bool_4 (
input clk,
input rst,
input start,
output reg [1:0] status
);
reg [3:0] M_test_counter_d, M_test_counter_q = 1'h0;
localparam IDLE_state = 2'd0;
localparam TEST_state = 2'd1;
localparam PASS_state = 2'd2;
localparam FAIL_state = 2'd3;
reg [1:0] M_state_d, M_state_q = IDLE_state;
wire [8-1:0] M_bool_out;
reg [8-1:0] M_bool_a;
reg [8-1:0] M_bool_b;
reg [6-1:0] M_bool_alufn;
boolean_11 bool (
.a(M_bool_a),
.b(M_bool_b),
.alufn(M_bool_alufn),
.out(M_bool_out)
);
always @* begin
M_state_d = M_state_q;
M_test_counter_d = M_test_counter_q;
status = 1'h0;
M_bool_a = 1'h0;
M_bool_b = 1'h0;
M_bool_alufn = 6'h00;
if (start == 1'h0) begin
M_state_d = IDLE_state;
end
case (M_state_q)
IDLE_state: begin
status = 1'h0;
if (start == 1'h1) begin
M_state_d = TEST_state;
end
end
TEST_state: begin
case (M_test_counter_q)
4'h0: begin
M_bool_alufn = 6'h18;
M_bool_a = 8'h35;
M_bool_b = 8'h53;
if (M_bool_out != 8'h11) begin
M_state_d = FAIL_state;
end
end
4'h1: begin
M_bool_alufn = 6'h1e;
M_bool_a = 8'h35;
M_bool_b = 8'h53;
if (M_bool_out != 8'h77) begin
M_state_d = FAIL_state;
end
end
4'h2: begin
M_bool_alufn = 6'h1e;
M_bool_a = 8'h00;
M_bool_b = 8'h00;
if (M_bool_out != 8'h00) begin
M_state_d = FAIL_state;
end
end
4'h3: begin
M_bool_alufn = 6'h1e;
M_bool_a = 8'hff;
M_bool_b = 8'hff;
if (M_bool_out != 8'hff) begin
M_state_d = FAIL_state;
end
end
4'h4: begin
M_bool_alufn = 6'h16;
M_bool_a = 8'h35;
M_bool_b = 8'h53;
if (M_bool_out != 8'h66) begin
M_state_d = FAIL_state;
end
end
4'h5: begin
M_bool_alufn = 6'h1a;
M_bool_a = 8'h35;
if (M_bool_out != 8'h35) begin
M_state_d = FAIL_state;
end
end
4'h6: begin
M_bool_alufn = 6'h1a;
M_bool_a = 8'h00;
if (M_bool_out != 8'h00) begin
M_state_d = FAIL_state;
end
end
4'h7: begin
M_bool_alufn = 6'h1a;
M_bool_a = 8'hff;
if (M_bool_out != 8'hff) begin
M_state_d = FAIL_state;
end
end
4'hf: begin
M_state_d = PASS_state;
end
endcase
end
PASS_state: begin
status = 1'h1;
end
FAIL_state: begin
status = 2'h2;
end
endcase
M_test_counter_d = M_test_counter_q + 1'h1;
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_state_q <= 1'h0;
end else begin
M_state_q <= M_state_d;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
M_test_counter_q <= 1'h0;
end else begin
M_test_counter_q <= M_test_counter_d;
end
end
endmodule
| 7.310343 |
module bram #(
parameter ABITS = 8,
DBITS = 8,
parameter INIT_ADDR = 0,
INIT_DATA = 0
) (
input clk,
input [ABITS-1:0] WR_ADDR,
input [DBITS-1:0] WR_DATA,
input WR_EN,
input [ABITS-1:0] RD_ADDR,
output reg [DBITS-1:0] RD_DATA
);
reg [DBITS-1:0] memory[0:2**ABITS-1];
initial begin
memory[INIT_ADDR] <= INIT_DATA;
end
always @(posedge clk) begin
if (WR_EN) memory[WR_ADDR] <= WR_DATA;
RD_DATA <= memory[RD_ADDR];
end
endmodule
| 7.645509 |
module test_bram16k ();
reg clock = 0;
reg [31:0] data = 0;
reg [8:0] rdaddress = 0;
reg [8:0] wraddress = 0;
reg wren = 0;
wire [31:0] q;
bram16k ram (
clock,
data,
rdaddress,
wraddress,
wren,
q
);
initial
forever begin
clock = 0;
#5;
clock = 1;
#5;
end
initial begin
$display("%t: q=%x", $time, q);
data = 'hDEADBEEF;
wren = 1;
#10;
$display("%t: q=%x", $time, q);
#10;
$display("%t: q=%x", $time, q);
$finish();
end
endmodule
| 7.19611 |
module bram_tb #(
parameter ABITS = 8,
DBITS = 8,
parameter INIT_ADDR = 0,
INIT_DATA = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
bram uut (
.clk (clk),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN (WR_EN),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA)
);
reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16);
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [ABITS-1:0] randaddr1;
reg [ABITS-1:0] randaddr2;
reg [ABITS-1:0] randaddr3;
function [31:0] getaddr(input [3:0] n);
begin
case (n)
0: getaddr = 0;
1: getaddr = 2 ** ABITS - 1;
2: getaddr = 'b101 << (ABITS / 3);
3: getaddr = 'b101 << (2 * ABITS / 3);
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2 * ABITS / 4);
6: getaddr = 'b11011 << (3 * ABITS / 4);
7: getaddr = randaddr1;
8: getaddr = randaddr2;
9: getaddr = randaddr3;
default: begin
getaddr = 1 << (2 * n - 16);
if (!getaddr) getaddr = xorshift64_state;
end
endcase
end
endfunction
reg [DBITS-1:0] memory[0:2**ABITS-1];
reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
integer i, j;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram_tb);
memory[INIT_ADDR] <= INIT_DATA;
xorshift64_next;
xorshift64_next;
xorshift64_next;
xorshift64_next;
randaddr1 = xorshift64_state;
xorshift64_next;
randaddr2 = xorshift64_state;
xorshift64_next;
randaddr3 = xorshift64_state;
xorshift64_next;
clk <= 0;
for (i = 0; i < 512; i = i + 1) begin
WR_DATA = xorshift64_state;
xorshift64_next;
WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR = i == 0 ? INIT_ADDR : getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN = xorshift64_state[55] && ((WR_ADDR & 'hff) != (RD_ADDR & 'hff));
xorshift64_next;
#1;
clk <= 1;
#1;
clk <= 0;
expected_rd = memory[RD_ADDR];
if (WR_EN) memory[WR_ADDR] = WR_DATA;
for (j = 0; j < DBITS; j = j + 1)
expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN,
RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
if (expected_rd_masked !== RD_DATA) begin
->error;
end
end
end
endmodule
| 7.129088 |
module test_bsg;
localparam cycle_time_lp = 20;
localparam width_lp = `WIDTH_P; // width of test input
localparam seed_lp = `SEED_P; // seed for random function
localparam count_width_lp = 8; // width of the cycle counter;
// test runs for (2^count_width_lp) cycles
wire clk;
wire reset;
logic [count_width_lp-1:0] count;
bsg_nonsynth_clock_gen #(.cycle_time_p(cycle_time_lp)) clock_gen (.o(clk));
bsg_nonsynth_reset_gen #(
.num_clocks_p (1)
, .reset_cycles_lo_p(5)
, .reset_cycles_hi_p(5)
) reset_gen (
.clk_i (clk)
, .async_reset_o(reset)
);
bsg_cycle_counter #(
.width_p(count_width_lp)
) cycle_counter (
.clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(count)
);
initial begin
$display("\n\n\n");
$display("==========================================================\n", "Width: %d\n",
width_lp, "Seed : %d\n", seed_lp);
end
logic test_input_yumi, test_input_yumi_r; // yumi_i
logic [width_lp-1:0] test_output, test_output_r; // data_o
logic finish_r;
// test stimulus generation
always_ff @(posedge clk) begin
if (reset) begin
test_input_yumi <= 1'b0;
finish_r <= 1'b0;
end else if (count < {1'b0, {(count_width_lp - 1) {1'b1}}}) // yumi is continuously asserted
test_input_yumi <= 1'b1;
else if (count == {1'b1, {(count_width_lp - 1) {1'b0}}}) // yumi is low after half time
test_input_yumi <= 1'b0;
else
test_input_yumi <= #(4*cycle_time_lp) ~test_input_yumi; // yumi is complimented every 5 clk cycles
if (&count) finish_r <= 1'b1;
if (finish_r) begin
$display("===============================================================\n");
$finish;
end
end
// test output validation
always_ff @(posedge clk) begin
test_input_yumi_r <= test_input_yumi;
test_output_r <= test_output;
/*$display("yumi: %b, test_output: %b\n"
, test_input_yumi, test_output);*/
if (test_input_yumi_r == 1'b0)
assert (test_output == test_output_r)
else $error("previous value is not retained when yumi is not asserted\n");
end
bsg_nonsynth_random_gen #(
.width_p(width_lp)
, .seed_p (seed_lp)
) DUT (
.clk_i (clk)
, .reset_i(reset)
, .yumi_i (test_input_yumi)
, .data_o (test_output)
);
// generated test output (random numbers) are logged to output.log
bsg_nonsynth_ascii_writer #(
.width_p (width_lp)
, .values_p (1)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("%b")
) ascii_writer (
.clk (clk)
, .reset_i(reset)
, .valid_i(test_input_yumi)
, .data_i (test_output)
);
endmodule
| 8.840941 |
module test_bsg_hypotenuse;
//`include "test_bsg_clock_params.v"
localparam cycle_time_lp = 20;
wire clk;
wire reset;
localparam width_lp = 12;
bsg_nonsynth_clock_gen #(.cycle_time_p(cycle_time_lp)) clock_gen (.o(clk));
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(5)
, .reset_cycles_hi_p(5)
) reset_gen (
.clk_i(clk)
, .async_reset_o(reset)
);
logic [width_lp*2-1:0] test_inputs, test_inputs_delayed, test_inputs_delayed_r;
wire [width_lp:0] test_output;
always_ff @(posedge clk) begin
test_inputs_delayed_r <= test_inputs_delayed;
if (~(|test_inputs_delayed) & (&test_inputs_delayed_r)) $finish();
end
bsg_cycle_counter #(
.width_p(width_lp * 2)
) bcc (
.clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(test_inputs)
);
bsg_hypotenuse #(
.width_p(width_lp)
) bed (
.clk(clk)
, .x_i(test_inputs[0+:width_lp])
, .y_i(test_inputs[width_lp+:width_lp])
, .o (test_output)
);
wire bsg_v;
// we use this to pass meta data in parallel
// to the values being computed. this
// might be a return packet header if we were
// using this inside a bsg_test_node
//
bsg_shift_reg #(
.width_p (width_lp * 2)
, .stages_p(width_lp + 4)
) bsr (
.clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i (test_inputs)
, .valid_o(bsg_v)
, .data_o (test_inputs_delayed)
);
localparam width_p1_lp = width_lp + 1;
bsg_nonsynth_ascii_writer #(
.width_p(width_lp + 1)
, .values_p(3)
, .filename_p("output.log")
, .format_p("w")
) ascii_writer (
.clk(clk)
, .reset_i(reset)
, .valid_i(bsg_v)
, .data_i({
test_output
, width_p1_lp'(test_inputs_delayed[0+:width_lp])
, width_p1_lp'(test_inputs_delayed[width_lp+:width_lp])
})
);
endmodule
| 8.120566 |
module TOP;
//ALU inputs
reg [31:0] a, b;
reg [3:0] op;
wire [31:0] out;
wire [3:0] flags;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
op = 3'b000;
a = 32'hffffffff;
b = 32'h00000000;
#`cycle //1
if(out != (a + b))
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 32'ha47ba47b;
b = 32'h5c915c91;
#`cycle //3
if(out != (a + b))
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 32'hbcdabcda;
b = 32'h79867986;
#`cycle //5
if(out != (a + b))
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 32'h96579657;
b = 32'h34563456;
#`cycle //7
if(out != (a + b))
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("alu.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(*)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, recieved out = %x, correct out = %x",
$time, a, b, out, (a + b));
else
$strobe ("correct: time: %0d: a = %x, b = %x, out = %x",
$time, a, b, out);
alu alu_test (out, flags, a, b, op);
endmodule
| 7.259416 |
module: ceasar_decryption
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_caesar;
// Inputs
reg clk;
reg rst_n;
reg [7:0] data_i;
reg valid_i;
reg [15:0] key;
// Outputs
wire [7:0] data_o;
wire valid_o;
wire busy;
// Instantiate the Unit Under Test (UUT)
ceasar_decryption uut (
.clk(clk),
.rst_n(rst_n),
.data_i(data_i),
.valid_i(valid_i),
.key(key),
.busy(busy),
.data_o(data_o),
.valid_o(valid_o)
);
initial begin
// Initialize Inputs
clk = 0;
rst_n = 0;
data_i = 0;
valid_i = 0;
key = 0;
repeat(5)
@(posedge clk);
rst_n = 1;
// Wait 100 ns for global reset to finish
repeat(5)
@(posedge clk);
@(posedge clk);
data_i = 1;
valid_i = 1;
@(posedge clk);
data_i = 2;
valid_i = 1;
@(posedge clk);
valid_i = 0;
data_i = 2;
@(posedge clk);
valid_i = 1;
data_i = 20;
// Add stimulus here
end
always #10 clk = ~clk;
endmodule
| 6.544138 |
module test_calculator ();
reg clock = 0;
always #2 clock = ~clock;
wire [151:0] tx_data;
wire [7:0] tx_len;
reg [7:0] rx_data = 0;
reg rx_received = 0;
wire [3:0] debug_state, debug_input_stage;
calculator calculator (
.tx_data(tx_data),
.tx_len(tx_len),
.tx_ena(tx_ena),
.tx_sending(tx_sending),
.tx_sent(tx_sent),
.rx_data(rx_data),
.rx_received(rx_received),
.clock(clock),
.state(debug_state),
.input_stage(debug_input_stage)
);
sim_uart_tx #(
.LEN(19)
) tx (
clock,
tx_data,
tx_len,
tx_ena,
tx_sending,
tx_sent
);
initial begin
#14 rx_data = `ASCII_MINUS;
rx_received = 1;
#2 rx_received = 0;
#10 $finish;
end
endmodule
| 6.589848 |
module test_calculatorRom ();
wire [15:0] out;
reg [ 9:0] opAB;
calculatorRom cr (
out,
opAB
);
initial begin
#5 opAB = {2'd0, 4'd5, 4'd4};
#5 opAB = {2'd1, 4'd5, 4'd4};
#5 $finish;
end
endmodule
| 6.589848 |
module test_cam (
input wire clk, // board clock: 32 MHz quacho 100 MHz nexys4
input wire rst, // reset button
//CAMARA input/output
output wire CAM_xclk, // System clock input
// colocar aqui las entras y salidas de la camara que hace falta
input wire CAM_pclk,
input wire CAM_vsync,
input wire CAM_href,
input wire CAM_px_data_0,
input wire CAM_px_data_1,
input wire CAM_px_data_2,
input wire CAM_px_data_3,
input wire CAM_px_data_4,
input wire CAM_px_data_5,
input wire CAM_px_data_6,
input wire CAM_px_data_7,
input init,
output error,
output done,
output [2:0] res
);
wire [7:0] CAM_px_data;
assign CAM_px_data[7:0] = {
CAM_px_data_7,
CAM_px_data_6,
CAM_px_data_5,
CAM_px_data_4,
CAM_px_data_3,
CAM_px_data_2,
CAM_px_data_1,
CAM_px_data_0
};
// TAMAÑO DE ADQUISICIÓN DE LA CAMARA
parameter CAM_SCREEN_X = 160;
parameter CAM_SCREEN_Y = 120;
localparam AW = 15; // LOG2(CAM_SCREEN_X*CAM_SCREEN_Y)
localparam DW = 8;
// Clk
wire clk32M;
wire clk25M;
wire clk24M;
// Conexión dual por ram
wire [AW-1:0] DP_RAM_addr_in;
wire [DW-1:0] DP_RAM_data_in;
wire DP_RAM_regW;
wire [AW-1:0] DP_RAM_addr_out;
wire [DW-1:0] DP_RAM_data_out;
/* ****************************************************************************
Asignacin de las seales de control xclk pwdn y reset de la camara
**************************************************************************** */
assign CAM_xclk = clk24M;
assign CAM_pwdn = 0; // power down mode
assign CAM_reset = 0;
/* ****************************************************************************
Este bloque se debe modificar segn sea le caso. El ejemplo esta dado para
fpga Spartan6 lx9 a 32MHz.
usar "tools -> Core Generator ..." y general el ip con Clocking Wizard
el bloque genera un reloj de 25Mhz usado para el VGA y un relo de 24 MHz
utilizado para la camara , a partir de una frecuencia de 32 Mhz
**************************************************************************** */
//assign clk32M =clk;
clk24_25_nexys4 clk24_25_nexys4 (
.CLK_IN1(clk),
.CLK_OUT1(clk25M),
.CLK_OUT2(clk24M),
.RESET(rst)
);
/* ****************************************************************************
buffer_ram_dp buffer memoria dual port y reloj de lectura y escritura separados
Se debe configurar AW segn los calculos realizados en el Wp01
se recomiendia dejar DW a 8, con el fin de optimizar recursos y hacer RGB 332
**************************************************************************** */
buffer_ram_dp #(AW, DW) buffer_ram_dp (
.clk_w(CAM_pclk),
.addr_in(DP_RAM_addr_in),
.data_in(DP_RAM_data_in),
.regwrite(DP_RAM_regW),
.clk_r(clk25M),
.addr_out(DP_RAM_addr_out),
.data_out(DP_RAM_data_out)
);
/*****************************************************************************
Módulo de captura de datos
**************************************************************************** */
wire done_read;
cam_read #(AW) cam_read (
.pclk(CAM_pclk),
.rst(rst),
.vsync(CAM_vsync),
.href(CAM_href),
.px_data(CAM_px_data),
.init(init),
.done(done_read),
.error(error),
.mem_px_addr(DP_RAM_addr_in),
.mem_px_data(DP_RAM_data_in),
.px_wr(DP_RAM_regW)
);
/*****************************************************************************
Módulo Analizador
**************************************************************************** */
Analyzer Analyzer (
.data(DP_RAM_data_out),
.clk (clk25M),
.init(done_read),
.addr(DP_RAM_addr_out),
.done(done),
.res (res)
);
endmodule
| 6.801079 |
module reg_ar_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(enout),
.reset(reset),
.set(set),
.q(q)
);
endmodule
| 7.493109 |
module reg_sr_as_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire resetout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_MUX u_reset0 (
.i0 (enout),
.i1 (1'b0),
.sel(reset),
.o (resetout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(resetout),
.reset(1'b0),
.set(set),
.q(q)
);
endmodule
| 7.286889 |
module reg_ar_ss_w1 (
clk,
d,
en,
reset,
set,
q
);
input clk;
input d;
input en;
input reset;
input set;
output q;
parameter REGSET = "RESET";
wire enout;
wire setout;
AL_MUX u_en0 (
.i0 (q),
.i1 (d),
.sel(en),
.o (enout)
);
AL_DFF #(
.INI((REGSET == "SET") ? 1'b1 : 1'b0)
) u_seq0 (
.clk(clk),
.d(setout),
.reset(reset),
.set(1'b0),
.q(q)
);
AL_MUX u_set0 (
.i0 (enout),
.i1 (1'b1),
.sel(set),
.o (setout)
);
endmodule
| 7.572347 |
module AL_MUX (
input i0,
input i1,
input sel,
output o
);
wire not_sel, sel_i0, sel_i1;
not u0 (not_sel, sel);
and u1 (sel_i1, sel, i1);
and u2 (sel_i0, not_sel, i0);
or u3 (o, sel_i1, sel_i0);
endmodule
| 8.256535 |
module AL_DFF (
input reset,
input set,
input clk,
input d,
output reg q
);
parameter INI = 1'b0;
always @(posedge reset or posedge set or posedge clk) begin
if (reset) q <= 1'b0;
else if (set) q <= 1'b1;
else q <= d;
end
endmodule
| 7.774683 |
module test_cam_bram;
// Parameters
parameter DATA_WIDTH = 64;
parameter ADDR_WIDTH = 5;
parameter SLICE_WIDTH = 9;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] write_addr = 0;
reg [DATA_WIDTH-1:0] write_data = 0;
reg write_delete = 0;
reg write_enable = 0;
reg [DATA_WIDTH-1:0] compare_data = 0;
// Outputs
wire write_busy;
wire [2**ADDR_WIDTH-1:0] match_many;
wire [2**ADDR_WIDTH-1:0] match_single;
wire [ADDR_WIDTH-1:0] match_addr;
wire match;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, write_addr, write_data, write_delete, write_enable,
compare_data);
$to_myhdl(write_busy, match_many, match_single, match_addr, match);
// dump file
$dumpfile("test_cam_bram.lxt");
$dumpvars(0, test_cam_bram);
end
cam_bram #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
endmodule
| 7.110206 |
module test_cam_srl;
// Parameters
parameter DATA_WIDTH = 64;
parameter ADDR_WIDTH = 5;
parameter SLICE_WIDTH = 4;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [ADDR_WIDTH-1:0] write_addr = 0;
reg [DATA_WIDTH-1:0] write_data = 0;
reg write_delete = 0;
reg write_enable = 0;
reg [DATA_WIDTH-1:0] compare_data = 0;
// Outputs
wire write_busy;
wire [2**ADDR_WIDTH-1:0] match_many;
wire [2**ADDR_WIDTH-1:0] match_single;
wire [ADDR_WIDTH-1:0] match_addr;
wire match;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, write_addr, write_data, write_delete, write_enable,
compare_data);
$to_myhdl(write_busy, match_many, match_single, match_addr, match);
// dump file
$dumpfile("test_cam_srl.lxt");
$dumpvars(0, test_cam_srl);
end
cam_srl #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.SLICE_WIDTH(SLICE_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
.write_addr(write_addr),
.write_data(write_data),
.write_delete(write_delete),
.write_enable(write_enable),
.write_busy(write_busy),
.compare_data(compare_data),
.match_many(match_many),
.match_single(match_single),
.match_addr(match_addr),
.match(match)
);
endmodule
| 7.130369 |
module: test_cam
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_cam_TB;
// Inputs
reg clk;
reg rst;
reg pclk;
reg CAM_vsync;
reg CAM_href;
reg [7:0] CAM_px_data;
// Outputs
wire VGA_Hsync_n;
wire VGA_Vsync_n;
wire [3:0] VGA_R;
wire [3:0] VGA_G;
wire [3:0] VGA_B;
wire CAM_xclk;
wire CAM_pwdn;
wire CAM_reset;
// Instantiate the Unit Under Test (UUT)
test_cam uut (
.clk(clk),
.rst(rst),
.VGA_Hsync_n(VGA_Hsync_n),
.VGA_Vsync_n(VGA_Vsync_n),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.CAM_xclk(CAM_xclk),
.CAM_pwdn(CAM_pwdn),
.CAM_reset(CAM_reset),
.CAM_pclk(pclk),
.CAM_vsync(CAM_vsync),
.CAM_href(CAM_href),
.CAM_px_data(CAM_px_data)
);
reg img_generate=0;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
pclk = 0;
CAM_vsync = 1;
CAM_href = 0;
CAM_px_data = 8'b11100000;
// Wait 100 ns for global reset to finish
#20;
rst = 0;
#1000000 img_generate=1;
end
always #0.5 clk = ~clk;
always #2 pclk = ~pclk;
reg [9:0]line_cnt=0;
reg [9:0]row_cnt=0;
parameter TAM_LINE=320; // es 160x2 debido a que son dos pixeles de RGB
parameter TAM_ROW=120;
parameter BLACK_TAM_LINE=4;
parameter BLACK_TAM_ROW=4;
/*************************************************************************
INICIO DE SIMULACION DE SEALES DE LA CAMARA
**************************************************************************/
/*simulacin de contador de pixeles para general Href y vsync*/
initial forever begin
// CAM_px_data=~CAM_px_data;
@(posedge pclk) begin
if (img_generate==1) begin
line_cnt=line_cnt+1;
if (line_cnt >TAM_LINE-1+BLACK_TAM_LINE) begin
line_cnt=0;
row_cnt=row_cnt+1;
if (row_cnt>TAM_ROW-1+BLACK_TAM_ROW) begin
row_cnt=0;
end
end
end
end
end
/*simulacin de la seal vsync generada por la camara*/
initial forever begin
@(posedge pclk) begin
if (img_generate==1) begin
if (row_cnt==0)begin
CAM_vsync = 1;
end
if (row_cnt==BLACK_TAM_ROW/2)begin
CAM_vsync = 0;
end
end
end
end
/*simulacin de la seal href generada por la camara*/
initial forever begin
@(negedge pclk) begin
if (img_generate==1) begin
if (row_cnt>BLACK_TAM_ROW-1)begin
if (line_cnt==0)begin
CAM_href = 1;
end
end
if (line_cnt==TAM_LINE)begin
CAM_href = 0;
end
end
end
end
/*************************************************************************
FIN SIMULACIN DE SEALES DE LA CAMARA
**************************************************************************/
/*************************************************************************
INICIO DE GENERACION DE ARCHIVO test_vga
**************************************************************************/
/* log para cargar de archivo*/
integer f;
initial begin
f = $fopen("test_vga.txt","w");
end
reg clk_w =0;
always #1 clk_w = ~clk_w;
/* ecsritura de log para cargar se cargados en https://ericeastwood.com/lab/vga-simulator/*/
initial forever begin
@(posedge clk_w)
$fwrite(f,"%0t ps: %b %b %b %b %b\n",$time,VGA_Hsync_n, VGA_Vsync_n, VGA_R[3:1],VGA_G[3:1],VGA_B[3:2]);
end
endmodule
| 7.12737 |
module test_card_gradient (
input wire [5:0] i_x,
input wire [7:0] i_y,
output wire [7:0] o_red,
output wire [7:0] o_green,
output wire [7:0] o_blue
);
localparam base_red = 8'h00;
localparam base_green = 8'h10;
localparam base_blue = 8'h4C;
assign o_red = base_red + i_y + {2'b0, i_x};
assign o_green = base_green + i_y;
assign o_blue = base_blue + i_y;
endmodule
| 7.680373 |
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