code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module picorv32_wrapper #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
input clk,
input resetn,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire mem_axi_awvalid;
wire mem_axi_awready;
wire [31:0] mem_axi_awaddr;
wire [ 2:0] mem_axi_awprot;
wire mem_axi_wvalid;
wire mem_axi_wready;
wire [31:0] mem_axi_wdata;
wire [ 3:0] mem_axi_wstrb;
wire mem_axi_bvalid;
wire mem_axi_bready;
wire mem_axi_arvalid;
wire mem_axi_arready;
wire [31:0] mem_axi_araddr;
wire [ 2:0] mem_axi_arprot;
wire mem_axi_rvalid;
wire mem_axi_rready;
wire [31:0] mem_axi_rdata;
axi4_mem_periph #(
.AXI_TEST(AXI_TEST),
.VERBOSE (VERBOSE)
) mem (
.clk (clk),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr),
.mem_axi_awprot (mem_axi_awprot),
.mem_axi_wvalid(mem_axi_wvalid),
.mem_axi_wready(mem_axi_wready),
.mem_axi_wdata (mem_axi_wdata),
.mem_axi_wstrb (mem_axi_wstrb),
.mem_axi_bvalid(mem_axi_bvalid),
.mem_axi_bready(mem_axi_bready),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr),
.mem_axi_arprot (mem_axi_arprot),
.mem_axi_rvalid(mem_axi_rvalid),
.mem_axi_rready(mem_axi_rready),
.mem_axi_rdata (mem_axi_rdata),
.tests_passed(tests_passed)
);
picorv32_axi #(
`ifndef SYNTH_TEST
`ifdef SP_TEST
.ENABLE_REGS_DUALPORT(0),
`endif
`ifdef COMPRESSED_ISA
.COMPRESSED_ISA(1),
`endif
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_TRACE(1)
`endif
) uut (
.clk (clk),
.resetn (resetn),
.trap (trap),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr),
.mem_axi_awprot (mem_axi_awprot),
.mem_axi_wvalid (mem_axi_wvalid),
.mem_axi_wready (mem_axi_wready),
.mem_axi_wdata (mem_axi_wdata),
.mem_axi_wstrb (mem_axi_wstrb),
.mem_axi_bvalid (mem_axi_bvalid),
.mem_axi_bready (mem_axi_bready),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr),
.mem_axi_arprot (mem_axi_arprot),
.mem_axi_rvalid (mem_axi_rvalid),
.mem_axi_rready (mem_axi_rready),
.mem_axi_rdata (mem_axi_rdata),
.irq (irq),
.trace_valid (trace_valid),
.trace_data (trace_data)
);
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file)) firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, mem.memory);
end
integer cycle_counter;
always @(posedge clk) begin
cycle_counter <= resetn ? cycle_counter + 1 : 0;
if (resetn && trap) begin
`ifndef VERILATOR
repeat (10) @(posedge clk);
`endif
$display("TRAP after %1d clock cycles", cycle_counter);
if (tests_passed) begin
$display("ALL TESTS PASSED.");
$finish;
end else begin
$display("ERROR!");
if ($test$plusargs("noerror")) $finish;
$stop;
end
end
end
endmodule
| 6.647596 |
module TestBench ();
reg [3:0] X;
reg [1:0] S;
wire Y;
mux_4_1 mux_4_1_test (
Y,
X,
S
);
initial begin
$dumpfile("TimingDiagram.vcd");
$dumpvars(0, Y, X, S);
X = 4'b0111;
S = 2'b00;
#20;
X = 4'b0101;
S = 2'b01;
#20;
X = 4'b0101;
S = 2'b10;
#20;
X = 4'b0101;
S = 2'b11;
#20;
X = 4'b1100;
S = 2'b11;
#20;
$finish;
end
endmodule
| 7.747207 |
module TB;
wire yy;
reg aa;
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end
gate newGate(.a(aa), .y(yy));
initial
begin
aa = 1'b0;
#5
aa = 1'b0;
#5
aa = 1'b1;
#5
aa = 1'b1;
#5
end
endmodule
| 7.168566 |
module dram #(
parameter AWIDTH = 10,
parameter DWIDTH = 80
) (
input clk,
input [AWIDTH-1:0] addr,
input [DWIDTH-1:0] in,
input we,
output reg [DWIDTH-1:0] out
);
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
initial begin
$readmemh("/home/tanmay/Koios++ - Copy/Multi_tile_design/dram_data.txt", ram,
0); //MAKE THIS DATA RANDOM
end
always @(posedge clk) begin
if (we) begin
ram[addr] <= in;
end
out <= ram[addr];
end
//assign out = ram[addr];
endmodule
| 8.142541 |
module instruction_mem #(
parameter AWIDTH = `INSTR_MEM_AWIDTH,
parameter DWIDTH = `INSTR_WIDTH
) (
input clk,
input [AWIDTH-1:0] addra,
addrb,
input [DWIDTH-1:0] ina,
inb,
input wea,
web,
output reg [DWIDTH-1:0] outa,
outb
);
reg [DWIDTH-1:0] ram[((1<<AWIDTH)-1):0];
// Port A
initial begin
$readmemb("/home/tanmay/Koios++ - Copy/Multi_tile_design/instructions_binary.txt",
ram); //MAKE THIS DATA RANDOM
end
always @(posedge clk) begin
if (wea) begin
ram[addra] <= ina;
end
outa <= ram[addra];
end
// Port B
always @(posedge clk) begin
if (web) begin
ram[addrb] <= inb;
end
outb <= ram[addrb];
end
//assign outa = ram[addra];
//assign outb = ram[addrb];
endmodule
| 7.714331 |
module tb ();
reg [7:0] testcase0[1:0];
reg [7:0] testcase1[1:0];
reg [7:0] testcase2[1:0];
reg [7:0] testcase3[1:0];
reg [7:0] testcase4[1:0];
reg [7:0] testcase5[1:0];
reg [7:0] testcase6[1:0];
reg [7:0] testcase7[1:0];
wire [15:0] result[7:0];
reg [7:0] binary_result;
reg dummy;
csmulti_fullbasecell uut0 (
testcase0[0],
testcase0[1],
result[0]
);
csmulti_fullbasecell uut1 (
testcase1[0],
testcase1[1],
result[1]
);
csmulti_fullbasecell uut2 (
testcase2[0],
testcase2[1],
result[2]
);
csmulti_fullbasecell uut3 (
testcase3[0],
testcase3[1],
result[3]
);
csmulti_fullbasecell uut4 (
testcase4[0],
testcase4[1],
result[4]
);
csmulti_fullbasecell uut5 (
testcase5[0],
testcase5[1],
result[5]
);
csmulti_fullbasecell uut6 (
testcase6[0],
testcase6[1],
result[6]
);
csmulti_fullbasecell uut7 (
testcase7[0],
testcase7[1],
result[7]
);
initial begin
dummy = 1;
testcase0[0] = 8'd255;
testcase0[1] = 8'd255;
testcase1[0] = 8'd150;
testcase1[1] = 8'd100;
testcase2[0] = 8'd23;
testcase2[1] = 8'd45;
testcase3[0] = 8'd11;
testcase3[1] = 8'd243;
testcase4[0] = 8'd121;
testcase4[1] = 8'd212;
testcase5[0] = 8'd88;
testcase5[1] = 8'd25;
testcase6[0] = 8'd96;
testcase6[1] = 8'd231;
testcase7[0] = 8'd1;
testcase7[1] = 8'd255;
#100 binary_result[0] = (result[0] == 16'd65_025);
binary_result[1] = (result[1] == 16'd15_000);
binary_result[2] = (result[2] == 16'd1035);
binary_result[3] = (result[3] == 16'd2673);
binary_result[4] = (result[4] == 16'd25_652);
binary_result[5] = (result[5] == 16'd2200);
binary_result[6] = (result[6] == 16'd22_176);
binary_result[7] = (result[7] == 16'd255);
#100 dummy = 0;
end
endmodule
| 7.002324 |
module PianoTest ();
//输出信号
wire [7:0] ROW, COL_RED, COL_GREEN;
wire Beep;
wire [6:0] SEG;
wire [7:0] SEG_Neg;
//输入信号
reg CLK;
reg [3:0] Switch;
reg [6:0] Key;
//初始化
initial begin
CLK = 1'b0;
Switch = 4'b0000;
Key = 7'b0000000;
end
//实例化程序
Piano m1 (
.ROW(ROW),
.COL_RED(COL_RED),
.COL_GREEN(COL_GREEN),
.CLK(CLK),
.Switch(Switch),
.Key(Key),
.Beep(Beep),
.SEG(SEG),
.SEG_Neg(SEG_Neg)
);
//10MHz时钟
always #50 CLK = ~CLK;
//仿真建议分块进行，进行一个模块仿真时将其余模块注释掉
initial begin
//等待
#100
//切换低音
Switch = 4'b0001;
#2000
//弹奏
Key = 7'b1000000;
#2000 Key = 7'b0100000;
#2000 Key = 7'b0010000;
#2000 Key = 7'b0001000;
#2000 Key = 7'b0000100;
#2000 Key = 7'b0000010;
#2000 Key = 7'b0000001;
#2000 Key = 7'b0000000;
#2000
//切换中音
Switch = 4'b0010;
#200
//弹奏
Key = 7'b1000000;
#2000 Key = 7'b0100000;
#2000 Key = 7'b0010000;
#2000 Key = 7'b0001000;
#200 Key = 7'b0000100;
#2000 Key = 7'b0000010;
#2000 Key = 7'b0000001;
#2000 Key = 7'b0000000;
#2000
//切换高音
Switch = 4'b0100;
#200
//弹奏
Key = 7'b1000000;
#2000 Key = 7'b0100000;
#2000 Key = 7'b0010000;
#2000 Key = 7'b0001000;
#2000 Key = 7'b0000100;
#2000 Key = 7'b0000010;
#1000 Key = 7'b0000001;
#2000 Key = 7'b0000000;
#100
/*
//自动演奏
Switch = 4'b1000;
#3000000000
Switch = 4'b0000;
#100
*/
/*
//蜂鸣器测试
Switch = 4'b0010;
#200
Key = 7'b1000000;
#200000000
Key = 7'b0000000;
Switch = 4'b0000;
#20
*/
$stop;
end
endmodule
| 9.20466 |
module testbench_posenege ();
parameter CLK_PERIOD = 10;
reg clk;
reg rst;
reg pulse;
wire rise_edge;
wire fall_edge;
posenege posenege_test (
.clk (clk),
.rst (rst),
.pulse (pulse),
.rise_edge(rise_edge),
.fall_edge(fall_edge)
);
// ʼλʱ
initial begin
clk <= 0;
rst <= 0;
#1000;
rst <= 1;
end
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
pulse <= 1'b0; // ϵֵ 0
@(posedge rst)
@(posedge clk)
repeat (10) begin
@(posedge clk);
end
#4; // ʹźʱӲͬ
pulse <= 1'b1;
// ӳ 10 ʱ
repeat (10) begin
@(posedge clk);
end
#4;
pulse <= 1'b0;
repeat (10) begin
@(posedge clk);
end
#10_000;
$stop;
end
endmodule
| 7.314512 |
module testbench;
parameter width = 3;
reg clk, rst;
reg [width-1:0] a, b, c;
reg [width-1:0] ans_no1, ans_no2, ans_no3;
wire [width-1:0] no1, no2, no3;
integer i, j, k, l, error, num;
reg [width*3-1:0] ans[0:511];
pplsort sort (
.no1(no1),
.no2(no2),
.no3(no3),
.a (a),
.b (b),
.c (c),
.clk(clk),
.rst(rst)
);
always begin
#(`CYCLE / 2) clk = ~clk;
end //clock generation
initial begin
$readmemb("ans3.txt", ans);
end
initial begin
clk = 1'b0;
rst = 1'b0;
l = 0;
error = 0;
num = 1;
@(negedge clk) rst = 1'b1;
#(`CYCLE * 2) rst = 1'b0;
@(negedge clk);
for (i = 0; i < 8; i = i + 1) begin
for (j = 0; j < 8; j = j + 1) begin
for (k = 0; k < 8; k = k + 1) begin
a = i[width-1:0];
b = j[width-1:0];
c = k[width-1:0];
{ans_no1, ans_no2, ans_no3} = ans[l];
@(negedge clk);
if (ans[l] != {no1, no2, no3}) begin
error = error + 1;
$display($time, "## Error at a=%d, b=%d, c=%d ", a, b, c);
$display($time, "Your result : no1=%d, no2=%d, no3=%d ", no1, no2, no3);
$display($time, "Correct result : no1=%d, no2=%d, no3=%d", ans_no1, ans_no2, ans_no3);
end else if (ans[l] == {no1, no2, no3}) num = num + 1;
l = l + 1;
end
end
end
end
initial begin
#(`CYCLE * 600)
if ((error == 0) && (num == 513)) begin
$display("------------------- Bubble sort check successfully -------------------");
$display(" $$ ");
$display(" $ $");
$display(" $ $");
$display(" $ $");
$display(" $ $");
$display("$$$$$$$$$ $$$$$$$$");
$display("$$$$$$$ $");
$display("$$$$$$$ $");
$display("$$$$$$$ $");
$display("$$$$$$$ $");
$display("$$$$$$$ $");
$display("$$$$$$$$$$$$ $$");
$display("$$$$$ $$$$$$$$$$");
end else if (num != 513 && error == 0) begin
$display("-------------------------------------------------------------------------------");
$display("* *");
$display("* Oops!Something wrong with your code *");
$display("* *");
$display("-------------------------------------------------------------------------------");
end else $display("------------------- There are %d errors -------------------", error);
$finish;
end
endmodule
| 7.015571 |
module testbench_ram_direct_read (
output reg completed
);
`include "../utils.h"
integer ipt;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
reg [17:0] psw;
reg enable;
reg signed [1:0] pt;
reg [17:0] addr;
wire ready;
wire pagefault;
wire [17:0] out;
triram ram (
.clk(clk),
.rst(rst),
.psw(psw),
.e(enable),
.write(1'b0),
.pt(pt),
.addr(addr),
.o(ready),
.pagefault(pagefault),
.out(out)
);
initial begin
completed = 0;
enable = 0;
rst = 1;
#160;
rst = 0;
#10;
for (ipt = -1; ipt <= 1; ipt = ipt + 1) begin
pt = ipt;
psw = 18'h0;
enable = 1;
addr = 18'h0;
#10;
enable = 0;
if (ready !== 1) $error("[ram_direct_read] %d 0 ready", ipt);
if (pagefault !== 0) $error("[ram_direct_read] %d 0 pagefault", ipt);
if (out !== 18'b111111000000000000) $error("[ram_direct_read] %d 0 out", ipt);
psw = 18'h0;
psw[2*(4+ipt)+:2] = 2'b01;
enable = 1;
addr = util_int_to_tryte(1916);
#10;
enable = 0;
if (ready !== 1) $error("[ram_direct_read] %d 1 ready", ipt);
if (pagefault !== 1) $error("[ram_direct_read] %d 1 pagefault", ipt);
#10;
psw = 18'h0;
enable = 1;
addr = util_int_to_tryte(1916);
#10;
enable = 0;
if (ready !== 1) $error("[ram_direct_read] %d 2 ready", ipt);
if (pagefault !== 0) $error("[ram_direct_read] %d 2 pagefault", ipt);
if (out !== 18'b111111000011000000) $error("[ram_direct_read] %d 2 out", ipt);
#10;
psw = 18'h0;
psw[2*(4+ipt)+:2] = 2'b11;
enable = 1;
addr = util_int_to_tryte(697);
#10;
enable = 0;
if (ready !== 1) $error("[ram_direct_read] %d 3 ready", ipt);
if (pagefault !== 1) $error("[ram_direct_read] %d 3 pagefault", ipt);
psw = 18'h0;
enable = 1;
addr = util_int_to_tryte(697);
#10;
enable = 0;
if (ready !== 1) $error("[ram_direct_read] %d 4 ready", ipt);
if (pagefault !== 0) $error("[ram_direct_read] %d 4 pagefault", ipt);
if (out !== 18'b111111001101000100) $error("[ram_direct_read] %d 4 out", ipt);
end
completed = 1;
$display("[ram_direct_read] Test completed.");
end
endmodule
| 7.112385 |
module testbench_ram (
output wire completed
);
wire [0:0] completion;
assign completed = &completion;
testbench_ram_direct_read p_ram_direct_read (completion[0]);
initial begin
#10;
while (!completed) #10;
$display("[ram] Test group completed.");
end
endmodule
| 7.112385 |
module TestBench_RC;
wire [3:0] S;
wire C;
reg [4:0] A, B;
reg [1:0] K;
rippleCarryAdder_4_bit RC (
S,
C,
A[3:0],
B[3:0],
K[0]
);
initial begin
for (A = 5'b00000; A <= 5'b01111; A = A + 5'b00001)
for (B = 5'b00000; B <= 5'b01111; B = B + 5'b00001)
for (K = 2'b00; K <= 2'b01; K = K + 2'b01) #50;
end
initial $monitor($time, "\t A=%d B=%d K=%d S=%d C=%d", A, B, K, S, C);
endmodule
| 6.950823 |
module i2c_tb ();
reg clk, rst, enable, read_write;
reg [7:0] data_write;
wire scl;
wire sda;
//reg SDA;
//wire direction=1;
//assign sda=direction?SDA:1'bZ;
wire [7:0] data;
wire [7:0] data_received;
reg scl_in;
//tri1 sda_in;
i2c_master master1 (
clk,
rst,
enable,
read_write,
data_write,
scl,
sda,
data
);
i2c_slave slave1 (
clk,
rst,
enable,
sda,
scl_in,
data_received
);
initial clk = 0;
always #2 clk = ~clk;
initial begin
rst = 1;
enable = 1;
read_write = 0;
data_write = 8'b10110011;
#10 rst = 0;
#190 $finish;
end
always @(*) scl_in <= scl;
endmodule
| 7.143885 |
module Testbench_reg;
// Inputs
wire clk_in;
// Outputs
wire clk_out_f, clk_out_2f, clk_out_4f;
// Instantiate the Unit Under Test (UUT)
// Test the clock divider in Verilog
Gen_relojes #(
.DIVISOR(32'd6)
) clk_4f (
.clk_in (clk_in),
.clk_out(clk_out_4f)
);
Gen_relojes clk_2f (
.clk_in (clk_out_4f),
.clk_out(clk_out_2f)
);
Gen_relojes clk_f (
.clk_in (clk_out_2f),
.clk_out(clk_out_f)
);
tester_reg test (
.clk_in (clk_in),
.clk_out_f (clk_out_f),
.clk_out_2f(clk_out_2f),
.clk_out_4f(clk_out_4f)
);
endmodule
| 6.631497 |
module TestBench_SEG;
wire [7:0] Y;
reg [4:0] I;
Binary_to_7Seg S0 (
Y[6:0],
I[3:0]
);
initial begin
for (I = 5'b00000; I < 5'b01111; I = I + 5'b00001) #50;
end
initial $monitor($time, "\t I=%b Y=%b", I[3:0], Y[6:0]);
endmodule
| 7.072886 |
module testbench_shift_reg #(
parameter DATA_WIDTH = 8,
parameter LENGTH = 4
);
reg [DATA_WIDTH*LENGTH-1:0] parameters_test;
reg [DATA_WIDTH-1:0] inputs_test;
wire [DATA_WIDTH*LENGTH-1:0] data_test;
wire [DATA_WIDTH-1:0] outputs_test;
reg [1:0] control;
reg clk, reset_n;
shift_reg #(
.DATA_WIDTH(DATA_WIDTH),
.LENGTH(LENGTH)
) shift_register (
.clock(clk),
.reset_n(reset_n),
.ctrl_code(control),
.data_in(parameters_test),
.data_read(outputs_test),
.data_write(inputs_test),
.data_out(data_test)
);
initial $dumpvars;
initial begin
clk = 0;
forever #10 clk = !clk;
end
integer ii;
initial begin
reset_n = 0;
control = 0;
#80;
reset_n = 1;
#20;
for (ii = 0; ii < LENGTH; ii = ii + 1) begin
parameters_test[DATA_WIDTH*ii+:DATA_WIDTH] = ii + 1;
end
control = 1;
#20;
control = 3;
#80;
control = 2;
inputs_test = 5;
#20;
inputs_test = 6;
#20;
inputs_test = 7;
#20;
control = 0;
#20;
control = 3;
#80;
end
endmodule
| 8.087461 |
module testbench_sigma;
reg [3:0] a;
reg [3:0] b;
reg [3:0] s;
reg m;
reg cin_re;
reg clock;
wire cout_re;
wire [3:0] y;
alu_4bit uut (
.a(a),
.b(b),
.s(s),
.m(m),
.cin_re(cin_re),
.cout_re(cout_re),
.y(y)
);
initial begin
a = 0;
b = 0;
s = 4'h9;
m = 0;
cin_re = 1; //no cin
clock = 0;
end
always #50 clock = ~clock;
always @(posedge clock) begin
if (y == 15) begin
a <= 0;
b <= 0;
end else begin
a <= y;
b <= b + 1;
end
end
endmodule
| 6.747363 |
module testbench_signed_cmp;
reg clk;
reg [15:0] a, b;
wire [15:0] less;
signed_cmp comparator (
.clk(clk),
.a(a),
.b(b),
.less(less)
);
initial $dumpvars;
initial begin
clk = 0;
forever #10 clk = !clk;
end
initial begin
a <= 16'h0012;
b <= 16'h0014;
#40;
a <= 16'hffd2;
b <= 16'h0352;
#20;
end
endmodule
| 6.747363 |
module testbench();
//DEFINE PARAMETER
parameter DATA_WIDTH = 64;
parameter ADDR_WIDTH = 16;
wire write_read;
wire error;
wire force_terminate;
wire complete;
wire [ADDR_WIDTH-1:0] address;
wire [DATA_WIDTH-1:0] wdata;
wire [DATA_WIDTH-1:0] rdata;
reg [2:0]memory_sel;
reg [4:0]memtype;
reg [2:0]operation;
reg clk, rst_n, test_mode, error_exceed_ignore;
reg [ADDR_WIDTH-1:0] allowable_faulty;
//GENERATE CLOCK SIGNAL
initial begin
clk = 1;
forever #10 clk = ~clk;
end
//GENERATE RESET SIGNAL
initial begin
rst_n = 0;
#11; rst_n = 1;
end
initial begin
test_mode = 0;
operation = 1;
memory_sel = @MEMORY_SELECTION;
error_exceed_ignore = 0;
allowable_faulty = 16'h00;
//DEFINE MEMTYPE
#21;
test_mode = 1;
//DEFINE OPERATION MODE
//-------------------- 0: marchc ; 1: apnpsf
error_exceed_ignore = 0;
allowable_faulty = 16'h0F;
#1001;
test_mode = 0;
//DEFINE OPERATION MODE
//DEFINE FINISH TIME
//------------------- 103 000: marchc ; 3 016 000: apnpsf
end
//---------- CONNECTION MBIST AND MEMORY TO TEST --------
mbist mbist_1(.clk(clk),
.rst_n(rst_n),
.test_mode(test_mode),
.operation(operation),
.error_exceed_ignore(error_exceed_ignore),
.allowable_faulty(allowable_faulty),
.memtype(memtype),
.memory_sel(memory_sel),
.address_@MEMORY_SELECTION(address),
.write_read_@MEMORY_SELECTION(write_read),
.wdata_@MEMORY_SELECTION(wdata),
.rdata_@MEMORY_SELECTION(rdata),
.error(error),
.force_terminate(force_terminate),
.complete(complete));
fault_mem fault_mem_test(.clk(clk),
.address(address),
.write_read(write_read),
.wdata(wdata),
.rdata(rdata));
always@(posedge error) begin
if (memtype[4:2] == 3'b000) begin
$display("MEMORY IS FAILED AT ADDRESS = : %d", address[8:0]);
end
else if (memtype[4:2] == 3'b001) begin
$display("MEMORY IS FAILED AT ADDRESS = : %d", address[9:0]);
end
else if (memtype[4:2] == 3'b010) begin
$display("MEMORY IS FAILED AT ADDRESS = : %d", address[10:0]);
end
else if (memtype[4:2] == 3'b011) begin
$display("MEMORY IS FAILED AT ADDRESS = : %d", address[11:0]);
end
else if (memtype[4:2] == 3'b100) begin
$display("MEMORY IS FAILED AT ADDRESS = : %d", address[12:0]);
end
else if (memtype[4:2] == 3'b101) begin
$display("MEMORY IS FAILED AT ADDRESS = : %d", address[13:0]);
end
else if (memtype[4:2] == 3'b110) begin
$display("MEMORY IS FAILED AT ADDRESS = : %d", address[14:0]);
end
else begin
$display("MEMORY IS FAILED AT ADDRESS = : %d", address[15:0]);
end
end
/*
initial begin
$monitor ("time=%d,clk=%b,rst_n=%b,test_mode=%b,operation=%b,error_exceed_ignore=%b,allowable_faulty=%h,complete=%b,force_terminate=%b, address=%h, write_read=%b, wdata=%h, rdata=%h \n",$time,clk,rst_n,test_mode,operation,error_exceed_ignore,allowable_faulty,complete,force_terminate, mbist_1.decoder_1.address, mbist_1.decoder_1.write_read, mbist_1.decoder_1.wdata, mbist_1.decoder_1.rdata);
end
*/
//DEFINE WAVEFORM DEBUG
endmodule
| 7.864579 |
module testbench_soc ();
reg clk, reset;
wire [3 : 0] KEY;
wire [3 : 0] LEDG;
wire [6 : 0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;
reg [2:0] ext_int;
SoC_IP_top IP (
.CLOCK_50 (clk),
.KEY (KEY),
.LEDG (LEDG),
.HEX0 (HEX0),
.HEX1 (HEX1),
.HEX2 (HEX2),
.HEX3 (HEX3),
.HEX4 (HEX4),
.HEX5 (HEX5),
.HEX6 (HEX6),
.HEX7 (HEX7)
);
assign KEY = {ext_int, ~reset};
initial begin
clk = 1'b0;
forever clk = #10 ~clk;
end
initial begin
ext_int = 0;
reset = 1;
#50 reset = 0;
#300000 ext_int = 1;
#50 ext_int = 0;
end
endmodule
| 7.030992 |
module Testbench_SramTest;
reg clock;
reg wren;
reg [14:0] address;
reg [7:0] data;
wire [7:0] read;
always begin
#50 clock = ~clock;
$display($time, "%d : %b : %h", read, read, read);
end
always @(posedge clock) address <= address + 1;
SRAM sram (
.clock(clock),
.address(address),
.data(data),
.wren(wren),
.q(read)
);
initial begin
wren = 1'b0;
clock = 1'b0;
address = 15'b0;
data = 8'b00110000;
#21600 $finish;
end
endmodule
| 6.585527 |
module testbench_sum_nmax #(
parameter DATA_WIDTH = 8,
parameter LENGTH = 10
);
reg [2*DATA_WIDTH*LENGTH-1:0] inputs_test;
wire [LENGTH-1:0] outputs_test;
reg [DATA_WIDTH*LENGTH-1:0] biases_test;
reg clk, reset_n, ready;
sum_and_max #(
.DATA_WIDTH(DATA_WIDTH),
.LENGTH(LENGTH)
) dut (
.clk(clk),
.reset_n(reset_n),
.ready(ready),
.input_data(inputs_test),
.biases(biases_test),
.maxi(outputs_test)
);
initial $dumpvars;
initial begin
clk = 0;
forever #10 clk = !clk;
end
integer ii;
initial begin
reset_n = 0;
ready = 0;
#80;
reset_n = 1;
#20;
for (ii = 0; ii < LENGTH; ii = ii + 1) begin
inputs_test[2*DATA_WIDTH*ii+:2*DATA_WIDTH] = ii + 1;
biases_test[DATA_WIDTH*ii+:DATA_WIDTH] = ii - 1;
end
ready = 1;
#20;
for (ii = 0; ii < LENGTH; ii = ii + 1) begin
inputs_test[2*DATA_WIDTH*ii+:2*DATA_WIDTH] = ii + 2;
end
#20;
for (ii = 0; ii < LENGTH; ii = ii + 1) begin
inputs_test[2*DATA_WIDTH*ii+:2*DATA_WIDTH] = ii - 2;
end
#80;
end
endmodule
| 7.503826 |
module testbench_switch ();
reg clk;
always begin
#50 clk = 0;
#50 clk = 1;
end
reg HSEL;
//reg HCLK;
reg HRESETn;
reg HREADY;
reg [31:0] HADDR;
reg [1:0] HTRANS;
reg HWRITE;
reg [2:0] HSIZE;
reg [31:0] HWDATA;
wire HREADYOUT;
reg [14:0] switch;
wire irq;
SWITCH_INPUT peri (
//AHBLITE INTERFACE
.HSEL(HSEL),
//Global Signal
.HCLK(clk),
.HRESETn(HRESETn),
//Address, Control & Write Data
.HREADY(HREADY),
.HADDR(HADDR),
.HTRANS(HTRANS),
.HWRITE(HWRITE),
.HWDATA(HWDATA), //,
.HREADYOUT(HREADYOUT),
.SWITCH_IRQ(irq),
.SWITCH(switch)
);
initial begin
HRESETn = 0;
switch <= 14'h0011;
//#50;
#100;
HRESETn = 1;
#100;
HREADY = 1;
HADDR = 32'h00000000;
HSEL = 1'b1;
HWRITE = 1'b0;
HTRANS = 2'b11;
#500;
switch <= 14'h0031;
end
endmodule
| 6.628471 |
module testbench;
//
// Free Running 50 MHz clock
//
parameter _clk_50mhz_high = 10,
_clk_50mhz_low = 10,
_clk_50mhz_period = _clk_50mhz_high + _clk_50mhz_low;
reg clk_tb;
initial begin
clk_tb <= 'b0;
forever begin
#(_clk_50mhz_low) clk_tb = 1;
#(_clk_50mhz_high) clk_tb = 0;
end
end
//
// Global Asynch reset, KEY[3] on the board is ACTIVE LOW
//
reg reset_tb;
initial begin
reset_tb = 0;
#1 reset_tb = 1;
#2000 reset_tb = 0;
end
//
// DUT to test
//
wire clk_o;
wire rst_o;
wire locked;
system_controller dut (
.clk_pad(clk_tb),
.rst_pad(reset_tb),
.clk_o(clk_o),
.rst_o(rst_o),
.locked(locked)
);
//
// Dump signals for waveform viewing
//
dump dump ();
//
// Testbench controlling tasks
//
`include "testbench_tasks.v"
//
// Include external thread for testing
//
`include "stimulus.v"
endmodule
| 7.015571 |
module testbench_sys_array #(
parameter DATA_WIDTH = 8,
parameter ARRAY_W = 4, //j
parameter ARRAY_L = 4
); //i
reg [DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] parameters_test;
reg [DATA_WIDTH*ARRAY_L-1:0] inputs_test;
wire [2*DATA_WIDTH*ARRAY_W-1:0] outputs_test;
reg clk, reset_n, param_load;
sys_array_basic #(
.DATA_WIDTH(DATA_WIDTH),
.ARRAY_W(ARRAY_W),
.ARRAY_L(ARRAY_L)
) systolic_array (
.clk(clk),
.reset_n(reset_n),
.param_load(param_load),
.parameter_data(parameters_test),
.input_module(inputs_test),
.out_module(outputs_test)
);
initial $dumpvars;
initial begin
clk = 0;
forever #10 clk = !clk;
end
integer ii;
initial begin
reset_n = 0;
param_load = 0;
#80;
reset_n = 1;
#20;
for (ii = 0; ii < 16; ii = ii + 1) begin
parameters_test[DATA_WIDTH*ii+:DATA_WIDTH] = ii + 1;
end
param_load = 1;
#20;
param_load = 0;
#10;
inputs_test[7:0] = 8'd1; //1st clk cycle
#20;
inputs_test[7:0] = 8'd5;
inputs_test[15:8] = 8'd2; //2nd clk cycle
#20;
inputs_test[7:0] = 8'd9;
inputs_test[15:8] = 8'd6;
inputs_test[23:16] = 8'd3; //3rd clk cycle
#20;
inputs_test[7:0] = 8'd13;
inputs_test[15:8] = 8'd10;
inputs_test[23:16] = 8'd7;
inputs_test[31:24] = 8'd4; //4th clock cycle
#20;
inputs_test[15:8] = 8'd14;
inputs_test[23:16] = 8'd11;
inputs_test[31:24] = 8'd8; //5th clock cycle
#20;
inputs_test[23:16] = 8'd15;
inputs_test[31:24] = 8'd12; //6th clock cycle
#20;
inputs_test[31:24] = 8'd16; //7th clk cycle
end
endmodule
| 6.885036 |
module TestBench ();
reg [3:0] X;
reg [1:0] S;
wire [3:0] Y;
TestMuxDecoder TestMuxDecoderTest (
Y,
X,
S
);
initial begin
$dumpfile("TimingDiagram.vcd");
$dumpvars(0, Y, X, S);
X = 4'b0111;
S = 2'b00;
#20;
X = 4'b0101;
S = 2'b01;
#20;
X = 4'b0101;
S = 2'b10;
#20;
X = 4'b0101;
S = 2'b11;
#20;
X = 4'b1100;
S = 2'b11;
#20;
$finish;
end
endmodule
| 7.747207 |
module: timing_generator_VGA
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestBench_timing_generator_VGA;
// Inputs
reg clk;
reg reset;
// Outputs
wire hsync;
wire vsync;
wire video_on;
wire p_tick;
wire [9:0] pixel_x;
wire [9:0] pixel_y;
// Instantiate the Unit Under Test (UUT)
timing_generator_VGA uut (
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.video_on(video_on),
.p_tick(p_tick),
.pixel_x(pixel_x),
.pixel_y(pixel_y)
);
//Para generar clock de 100 MHz
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
begin
// Initialize Inputs
reset = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
#50000000$stop;
end
endmodule
| 7.401997 |
module testbench #(
parameter TARGET = "DEFAULT", // pass through variable for hard macro
parameter TIMEOUT = 5000 // timeout value (cycles)
) (
input clk
);
parameter integer PERIOD_CLK = 10;
parameter integer TCW = 8;
parameter integer IOW = 64;
parameter integer NUMI = 2;
// Local parameters
localparam CW = 32; // UMI width
localparam AW = 64; // UMI width
localparam IDW = 128;
localparam ODW = 512;
// SIM Ctrl signals
wire nreset;
wire go;
reg [15:0] nreset_vec = 16'h0000;
// Reset initialization
always @(posedge clk) begin
nreset_vec <= {nreset_vec[14:0], 1'b1};
end
assign nreset = nreset_vec[14];
assign go = nreset_vec[15];
// control block
initial begin
if ($test$plusargs("trace")) begin
$dumpfile("waveform.fst");
$dumpvars();
end
end
// DUT signals
wire umi_stim2dut_valid;
wire [ CW-1:0] umi_stim2dut_cmd;
wire [ AW-1:0] umi_stim2dut_dstaddr;
wire [ AW-1:0] umi_stim2dut_srcaddr;
wire [IDW-1:0] umi_stim2dut_data;
wire umi_stim2dut_ready;
wire umi_dut2check_valid;
wire [ CW-1:0] umi_dut2check_cmd;
wire [ AW-1:0] umi_dut2check_dstaddr;
wire [ AW-1:0] umi_dut2check_srcaddr;
wire [ODW-1:0] umi_dut2check_data;
reg umi_dut2check_ready;
always @(posedge clk) begin
if (~nreset) umi_dut2check_ready <= 1'b0;
else umi_dut2check_ready <= ~umi_dut2check_ready;
end
umi_packet_merge_greedy #(
.CW (CW),
.AW (AW),
.IDW(IDW),
.ODW(ODW)
) dut (
.clk (clk),
.nreset(nreset),
.umi_in_valid (umi_stim2dut_valid),
.umi_in_cmd (umi_stim2dut_cmd),
.umi_in_dstaddr(umi_stim2dut_dstaddr),
.umi_in_srcaddr(umi_stim2dut_srcaddr),
.umi_in_data (umi_stim2dut_data),
.umi_in_ready (umi_stim2dut_ready),
.umi_out_valid (umi_dut2check_valid),
.umi_out_cmd (umi_dut2check_cmd),
.umi_out_dstaddr(umi_dut2check_dstaddr),
.umi_out_srcaddr(umi_dut2check_srcaddr),
.umi_out_data (umi_dut2check_data),
.umi_out_ready (umi_dut2check_ready)
);
umi_rx_sim #(
.VALID_MODE_DEFAULT(2)
) umi_rx_i (
.clk(clk),
.valid (umi_stim2dut_valid),
.cmd (umi_stim2dut_cmd[CW-1:0]),
.dstaddr(umi_stim2dut_dstaddr[AW-1:0]),
.srcaddr(umi_stim2dut_srcaddr[AW-1:0]),
.data (umi_stim2dut_data[IDW-1:0]),
.ready (umi_stim2dut_ready)
);
// Initialize UMI
integer valid_mode, ready_mode;
initial begin
if (!$value$plusargs("valid_mode=%d", valid_mode)) begin
valid_mode = 2; // default if not provided as a plusarg
end
umi_rx_i.init("client2rtl_0.q");
umi_rx_i.set_valid_mode(valid_mode);
end
// auto-stop
auto_stop_sim #(.CYCLES(50000)) auto_stop_sim_i (.clk(clk));
endmodule
| 6.640835 |
module testbench_util_trit_m1 (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_m1(2'b11) !== 1'b1) $error("[util_trit_m1] #-");
if (util_trit_m1(2'b00) !== 1'b0) $error("[util_trit_m1] #0");
if (util_trit_m1(2'b01) !== 1'b0) $error("[util_trit_m1] #+");
completed = 1;
$display("[util_trit_m1] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_trit_0 (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_0(2'b11) !== 1'b0) $error("[util_trit_0] #-");
if (util_trit_0(2'b00) !== 1'b1) $error("[util_trit_0] #0");
if (util_trit_0(2'b01) !== 1'b0) $error("[util_trit_0] #+");
completed = 1;
$display("[util_trit_0] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_trit_1 (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_1(2'b11) !== 1'b0) $error("[util_trit_1] #-");
if (util_trit_1(2'b00) !== 1'b0) $error("[util_trit_1] #0");
if (util_trit_1(2'b01) !== 1'b1) $error("[util_trit_1] #+");
completed = 1;
$display("[util_trit_1] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_tryte_check (
output reg completed
);
`include "../utils.h"
integer ii;
reg [17:0] tryte;
initial begin
completed = 0;
for (ii = -9841; ii <= 9841; ii = ii + 1) begin
tryte = util_int_to_tryte(tryte);
if (util_tryte_check(tryte) !== tryte) $error("[util_tryte_check] %d", ii);
end
completed = 1;
$display("[util_tryte_check] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_trit_neg (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_neg(2'b11) !== 2'b01) $error("[util_trit_neg] #-");
if (util_trit_neg(2'b00) !== 2'b00) $error("[util_trit_neg] #0");
if (util_trit_neg(2'b01) !== 2'b11) $error("[util_trit_neg] #+");
completed = 1;
$display("[util_trit_neg] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_trit_neg_cond (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_trit_neg_cond(1'b0, 2'b11) !== 2'b11) $error("[util_trit_neg_cond] 0 #-");
if (util_trit_neg_cond(1'b0, 2'b00) !== 2'b00) $error("[util_trit_neg_cond] 0 #0");
if (util_trit_neg_cond(1'b0, 2'b01) !== 2'b01) $error("[util_trit_neg_cond] 0 #+");
if (util_trit_neg_cond(1'b1, 2'b11) !== 2'b01) $error("[util_trit_neg_cond] 1 #-");
if (util_trit_neg_cond(1'b1, 2'b00) !== 2'b00) $error("[util_trit_neg_cond] 1 #0");
if (util_trit_neg_cond(1'b1, 2'b01) !== 2'b11) $error("[util_trit_neg_cond] 1 #+");
completed = 1;
$display("[util_trit_neg_cond] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_halfadder (
output reg completed
);
`include "../utils.h"
function [1:0] trunc2(input integer n);
begin
trunc2 = n[1:0];
end
endfunction
function [3:0] trunc4(input integer n);
begin
trunc4 = n[3:0];
end
endfunction
integer ii0;
integer ii1;
integer ii2;
integer ii3;
reg signed [1:0] t0;
reg signed [1:0] t1;
reg signed [1:0] t2;
reg signed [1:0] t3;
reg [3:0] tres;
initial begin
completed = 0;
for (ii0 = -1; ii0 <= 1; ii0 = ii0 + 1)
for (ii1 = -1; ii1 <= 1; ii1 = ii1 + 1)
for (ii2 = -1; ii2 <= 1; ii2 = ii2 + 1)
for (ii3 = -1; ii3 <= 1; ii3 = ii3 + 1) begin
t0 = trunc2(util_int_to_tryte(ii0));
t1 = trunc2(util_int_to_tryte(ii1));
t2 = trunc2(util_int_to_tryte(ii2));
t3 = trunc2(util_int_to_tryte(ii3));
tres = trunc4(util_int_to_tryte(ii0 + ii1 + ii2 + ii3));
if (util_halfadder(t0, t1, t2, t3) !== tres) begin
$error("[util_halfadder] %d %d %d %d", ii0, ii1, ii2, ii3);
end
end
completed = 1;
$display("[util_halfadder] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_5trits_to_8bits (
output reg completed
);
`include "../utils.h"
function [9:0] trunc10(input integer n);
begin
trunc10 = n[5:0];
end
endfunction
integer ii;
initial begin
completed = 0;
for (ii = -13; ii <= 13; ii = ii + 1) begin
if (ii !== util_5trits_to_8bits(trunc10(util_int_to_tryte(ii))))
$error("[util_5trits_to_8bits] %d", ii);
end
completed = 1;
$display("[util_5trits_to_8bits] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_int_to_tryte (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_int_to_tryte(-29524) !== 18'b111111111111111111) $error("[util_int_to_tryte] -29524");
if (util_int_to_tryte(-29523) !== 18'b111111111111111100) $error("[util_int_to_tryte] -29523");
if (util_int_to_tryte(-9841) !== 18'b111111111111111111) $error("[util_int_to_tryte] -9841");
if (util_int_to_tryte(-9840) !== 18'b111111111111111100) $error("[util_int_to_tryte] -9840");
if (util_int_to_tryte(-10) !== 18'b000000000000110011) $error("[util_int_to_tryte] -10");
if (util_int_to_tryte(-9) !== 18'b000000000000110000) $error("[util_int_to_tryte] -9");
if (util_int_to_tryte(-8) !== 18'b000000000000110001) $error("[util_int_to_tryte] -8");
if (util_int_to_tryte(-7) !== 18'b000000000000110111) $error("[util_int_to_tryte] -7");
if (util_int_to_tryte(-6) !== 18'b000000000000110100) $error("[util_int_to_tryte] -6");
if (util_int_to_tryte(-5) !== 18'b000000000000110101) $error("[util_int_to_tryte] -5");
if (util_int_to_tryte(-4) !== 18'b000000000000001111) $error("[util_int_to_tryte] -4");
if (util_int_to_tryte(-3) !== 18'b000000000000001100) $error("[util_int_to_tryte] -3");
if (util_int_to_tryte(-2) !== 18'b000000000000001101) $error("[util_int_to_tryte] -2");
if (util_int_to_tryte(-1) !== 18'b000000000000000011) $error("[util_int_to_tryte] -1");
if (util_int_to_tryte(0) !== 18'b000000000000000000) $error("[util_int_to_tryte] 0");
if (util_int_to_tryte(1) !== 18'b000000000000000001) $error("[util_int_to_tryte] 1");
if (util_int_to_tryte(2) !== 18'b000000000000000111) $error("[util_int_to_tryte] 2");
if (util_int_to_tryte(3) !== 18'b000000000000000100) $error("[util_int_to_tryte] 3");
if (util_int_to_tryte(4) !== 18'b000000000000000101) $error("[util_int_to_tryte] 4");
if (util_int_to_tryte(5) !== 18'b000000000000011111) $error("[util_int_to_tryte] 5");
if (util_int_to_tryte(6) !== 18'b000000000000011100) $error("[util_int_to_tryte] 6");
if (util_int_to_tryte(7) !== 18'b000000000000011101) $error("[util_int_to_tryte] 7");
if (util_int_to_tryte(8) !== 18'b000000000000010011) $error("[util_int_to_tryte] 8");
if (util_int_to_tryte(9) !== 18'b000000000000010000) $error("[util_int_to_tryte] 9");
if (util_int_to_tryte(10) !== 18'b000000000000010001) $error("[util_int_to_tryte] 10");
if (util_int_to_tryte(9840) !== 18'b010101010101010100) $error("[util_int_to_tryte] 9840");
if (util_int_to_tryte(9841) !== 18'b010101010101010101) $error("[util_int_to_tryte] 9841");
if (util_int_to_tryte(29523) !== 18'b010101010101010100) $error("[util_int_to_tryte] 29523");
if (util_int_to_tryte(29524) !== 18'b010101010101010101) $error("[util_int_to_tryte] 29524");
if (util_int_to_tryte(29526) !== 18'b111111111111111100) $error("[util_int_to_tryte] 29526");
completed = 1;
$display("[util_int_to_tryte] Test completed.");
end
endmodule
| 8.105787 |
module testbench_util_int_to_trits10 (
output reg completed
);
`include "../utils.h"
initial begin
completed = 0;
if (util_int_to_trits10(-29524) !== 20'b11111111111111111111)
$error("[util_int_to_trits10] -29524");
if (util_int_to_trits10(-29523) !== 20'b11111111111111111100)
$error("[util_int_to_trits10] -29523");
if (util_int_to_trits10(-9841) !== 20'b00111111111111111111)
$error("[util_int_to_trits10] -9841");
if (util_int_to_trits10(-9840) !== 20'b00111111111111111100)
$error("[util_int_to_trits10] -9840");
if (util_int_to_trits10(-10) !== 20'b00000000000000110011) $error("[util_int_to_trits10] -10");
if (util_int_to_trits10(-9) !== 20'b00000000000000110000) $error("[util_int_to_trits10] -9");
if (util_int_to_trits10(-8) !== 20'b00000000000000110001) $error("[util_int_to_trits10] -8");
if (util_int_to_trits10(-7) !== 20'b00000000000000110111) $error("[util_int_to_trits10] -7");
if (util_int_to_trits10(-6) !== 20'b00000000000000110100) $error("[util_int_to_trits10] -6");
if (util_int_to_trits10(-5) !== 20'b00000000000000110101) $error("[util_int_to_trits10] -5");
if (util_int_to_trits10(-4) !== 20'b00000000000000001111) $error("[util_int_to_trits10] -4");
if (util_int_to_trits10(-3) !== 20'b00000000000000001100) $error("[util_int_to_trits10] -3");
if (util_int_to_trits10(-2) !== 20'b00000000000000001101) $error("[util_int_to_trits10] -2");
if (util_int_to_trits10(-1) !== 20'b00000000000000000011) $error("[util_int_to_trits10] -1");
if (util_int_to_trits10(0) !== 20'b00000000000000000000) $error("[util_int_to_trits10] 0");
if (util_int_to_trits10(1) !== 20'b00000000000000000001) $error("[util_int_to_trits10] 1");
if (util_int_to_trits10(2) !== 20'b00000000000000000111) $error("[util_int_to_trits10] 2");
if (util_int_to_trits10(3) !== 20'b00000000000000000100) $error("[util_int_to_trits10] 3");
if (util_int_to_trits10(4) !== 20'b00000000000000000101) $error("[util_int_to_trits10] 4");
if (util_int_to_trits10(5) !== 20'b00000000000000011111) $error("[util_int_to_trits10] 5");
if (util_int_to_trits10(6) !== 20'b00000000000000011100) $error("[util_int_to_trits10] 6");
if (util_int_to_trits10(7) !== 20'b00000000000000011101) $error("[util_int_to_trits10] 7");
if (util_int_to_trits10(8) !== 20'b00000000000000010011) $error("[util_int_to_trits10] 8");
if (util_int_to_trits10(9) !== 20'b00000000000000010000) $error("[util_int_to_trits10] 9");
if (util_int_to_trits10(10) !== 20'b00000000000000010001) $error("[util_int_to_trits10] 10");
if (util_int_to_trits10(9840) !== 20'b00010101010101010100)
$error("[util_int_to_trits10] 9840");
if (util_int_to_trits10(9841) !== 20'b00010101010101010101)
$error("[util_int_to_trits10] 9841");
if (util_int_to_trits10(29523) !== 20'b01010101010101010100)
$error("[util_int_to_trits10] 29523");
if (util_int_to_trits10(29524) !== 20'b01010101010101010101)
$error("[util_int_to_trits10] 29524");
if (util_int_to_trits10(29526) !== 20'b11111111111111111100)
$error("[util_int_to_trits10] 29526");
completed = 1;
$display("[util_int_to_trits10] Test completed.");
end
endmodule
| 8.105787 |
module testbench_utils (
output wire completed
);
wire [8:0] completion;
assign completed = &completion;
testbench_util_trit_m1 p_util_trit_m1 (completion[0]);
testbench_util_trit_0 p_util_trit_0 (completion[1]);
testbench_util_trit_1 p_util_trit_1 (completion[2]);
testbench_util_tryte_check p_util_tryte_check (completion[3]);
testbench_util_trit_neg p_util_trit_neg (completion[4]);
testbench_util_trit_neg_cond p_util_trit_neg_cond (completion[5]);
testbench_util_halfadder p_util_halfadder (completion[6]);
testbench_util_5trits_to_8bits p_util_5trits_to_8bits (completion[7]);
testbench_util_int_to_tryte p_util_int_to_tryte (completion[8]);
testbench_util_int_to_trits10 p_util_int_to_trits10 (completion[8]);
initial begin
#10;
while (!completed) #10;
$display("[utils] Test group completed.");
end
endmodule
| 8.105787 |
module testbench #(
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 1;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 0;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (1000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
picorv32_wrapper #(
.VERBOSE(VERBOSE)
) top (
.wb_clk(clk),
.wb_rst(resetn),
.trap(trap),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule
| 6.640835 |
module picorv32_wrapper #(
parameter VERBOSE = 0
) (
input wb_clk,
input wb_rst,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
wire mem_instr;
reg [15:0] count_cycle = 0;
always @(posedge wb_clk) count_cycle <= !wb_rst ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire [31:0] wb_m2s_adr;
wire [31:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel;
wire wb_m2s_we;
wire wb_m2s_cyc;
wire wb_m2s_stb;
wire [31:0] wb_s2m_dat;
wire wb_s2m_ack;
wb_ram #(
.depth (128 * 1024),
.VERBOSE(VERBOSE)
) ram ( // Wishbone interface
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wb_adr_i(wb_m2s_adr),
.wb_dat_i(wb_m2s_dat),
.wb_stb_i(wb_m2s_stb),
.wb_cyc_i(wb_m2s_cyc),
.wb_dat_o(wb_s2m_dat),
.wb_ack_o(wb_s2m_ack),
.wb_sel_i(wb_m2s_sel),
.wb_we_i (wb_m2s_we),
.mem_instr(mem_instr),
.tests_passed(tests_passed)
);
picorv32_wb #(
`ifndef SYNTH_TEST
`ifdef SP_TEST
.ENABLE_REGS_DUALPORT(0),
`endif
`ifdef COMPRESSED_ISA
.COMPRESSED_ISA(1),
`endif
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_TRACE(1)
`endif
) uut (
.trap(trap),
.irq(irq),
.trace_valid(trace_valid),
.trace_data(trace_data),
.mem_instr(mem_instr),
.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
.wbm_adr_o(wb_m2s_adr),
.wbm_dat_i(wb_s2m_dat),
.wbm_stb_o(wb_m2s_stb),
.wbm_ack_i(wb_s2m_ack),
.wbm_cyc_o(wb_m2s_cyc),
.wbm_dat_o(wb_m2s_dat),
.wbm_we_o (wb_m2s_we),
.wbm_sel_o(wb_m2s_sel)
);
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file)) firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, ram.mem);
end
integer cycle_counter;
always @(posedge wb_clk) begin
cycle_counter <= !wb_rst ? cycle_counter + 1 : 0;
if (!wb_rst && trap) begin
`ifndef VERILATOR
repeat (10) @(posedge wb_clk);
`endif
$display("TRAP after %1d clock cycles", cycle_counter);
if (tests_passed) begin
$display("ALL TESTS PASSED.");
$finish;
end else begin
$display("ERROR!");
if ($test$plusargs("noerror")) $finish;
$stop;
end
end
end
endmodule
| 6.647596 |
module wb_ram #(
parameter depth = 256,
parameter memfile = "",
parameter VERBOSE = 0
) (
input wb_clk_i,
input wb_rst_i,
input [31:0] wb_adr_i,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output reg wb_ack_o,
output reg [31:0] wb_dat_o,
input mem_instr,
output reg tests_passed
);
reg verbose;
initial verbose = $test$plusargs("verbose") || VERBOSE;
initial tests_passed = 0;
reg [31:0] adr_r;
wire valid = wb_cyc_i & wb_stb_i;
always @(posedge wb_clk_i) begin
adr_r <= wb_adr_i;
// Ack generation
wb_ack_o <= valid & !wb_ack_o;
if (wb_rst_i) begin
adr_r <= {32{1'b0}};
wb_ack_o <= 1'b0;
end
end
wire ram_we = wb_we_i & valid & wb_ack_o;
wire [31:0] waddr = adr_r[31:2];
wire [31:0] raddr = wb_adr_i[31:2];
wire [3:0] we = {4{ram_we}} & wb_sel_i;
wire [$clog2(depth/4)-1:0] raddr2 = raddr[$clog2(depth/4)-1:0];
wire [$clog2(depth/4)-1:0] waddr2 = waddr[$clog2(depth/4)-1:0];
reg [31:0] mem[0:depth/4-1] /* verilator public */;
always @(posedge wb_clk_i) begin
if (ram_we) begin
if (verbose) $display("WR: ADDR=%08x DATA=%08x STRB=%04b", adr_r, wb_dat_i, we);
if (adr_r[31:0] == 32'h1000_0000)
if (verbose) begin
if (32 <= wb_dat_i[7:0] && wb_dat_i[7:0] < 128) $display("OUT: '%c'", wb_dat_i[7:0]);
else $display("OUT: %3d", wb_dat_i[7:0]);
end else begin
$write("%c", wb_dat_i[7:0]);
`ifndef VERILATOR
$fflush();
`endif
end
else if (adr_r[31:0] == 32'h2000_0000) if (wb_dat_i[31:0] == 123456789) tests_passed = 1;
end
end
always @(posedge wb_clk_i) begin
if (waddr2 < 128 * 1024 / 4) begin
if (we[0]) mem[waddr2][7:0] <= wb_dat_i[7:0];
if (we[1]) mem[waddr2][15:8] <= wb_dat_i[15:8];
if (we[2]) mem[waddr2][23:16] <= wb_dat_i[23:16];
if (we[3]) mem[waddr2][31:24] <= wb_dat_i[31:24];
end
if (valid & wb_ack_o & !ram_we)
if (verbose)
$display("RD: ADDR=%08x DATA=%08x%s", adr_r, mem[raddr2], mem_instr ? " INSN" : "");
wb_dat_o <= mem[raddr2];
end
initial begin
if (memfile != "") $readmemh(memfile, mem);
end
endmodule
| 6.893135 |
module vsdmemsoc_tb;
// Inputs
supply0 vgnd;
supply1 vpwr;
reg ext_clk, reset;
reg wb_clk_i;
reg wb_rst_i;
reg wbs_stb_i;
reg wbs_cyc_i;
reg wbs_we_i;
reg [3:0] wbs_sel_i;
reg [31:0] wbs_dat_i;
reg [7:0] wbs_adr_i;
// Outputs
wire [9:0] OUT;
wire [31:0] wbs_dat_o;
wire wbs_ack_o;
// Other Signals
integer i;
wire [31:0] ROM =
i == 32'h0 ? {12'b1, 5'd0, 3'b000, 5'd9, 7'b0010011} :
i == 32'h1 ? {12'b101011, 5'd0, 3'b000, 5'd10, 7'b0010011} :
i == 32'h2 ? {12'b0, 5'd0, 3'b000, 5'd11, 7'b0010011} :
i == 32'h3 ? {12'b0, 5'd0, 3'b000, 5'd17, 7'b0010011} :
i == 32'h4 ? {7'b0000000, 5'd11, 5'd17, 3'b000, 5'd17, 7'b0110011} :
i == 32'h5 ? {12'b1, 5'd11, 3'b000, 5'd11, 7'b0010011} :
i == 32'h6 ? {1'b1, 6'b111111, 5'd10, 5'd11, 3'b001, 4'b1100, 1'b1, 7'b1100011} :
i == 32'h7 ? {7'b0000000, 5'd11, 5'd17, 3'b000, 5'd17, 7'b0110011} :
i == 32'h8 ? {7'b0100000, 5'd11, 5'd17, 3'b000, 5'd17, 7'b0110011} :
i == 32'h9 ? {7'b0100000, 5'd9, 5'd11, 3'b000, 5'd11, 7'b0110011} :
i == 32'hA ? {1'b1, 6'b111111, 5'd9, 5'd11, 3'b001, 4'b1100, 1'b1, 7'b1100011} :
i == 32'hB ? {7'b0100000, 5'd11, 5'd17, 3'b000, 5'd17, 7'b0110011} :
i == 32'hC ? {1'b1, 6'b111111, 5'd0, 5'd0, 3'b000, 4'b0000, 1'b1, 7'b1100011} :
32'd0 ;
// Instantiate the Unit Under Test (UUT)
vsdmemsoc uut (
.OUT(OUT),
.ext_clk(ext_clk),
`ifdef USE_POWER_PINS
.vccd1(vgnd),
.vssd1(vpwr),
`endif
.ext_rst(reset),
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_stb_i(wbs_stb_i),
.wbs_cyc_i(wbs_cyc_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_dat_i(wbs_dat_i),
.wbs_adr_i(wbs_adr_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o)
);
always @(posedge wb_clk_i) begin
if (i < 32'd16) begin // upload instructions in memory
i <= i + 32'd1;
reset <= 1'b1;
wb_rst_i <= 1'b0;
wbs_stb_i <= 1'b1;
wbs_cyc_i <= 1'b1;
wbs_we_i <= 1'b1;
wbs_sel_i <= 4'b1111;
wbs_adr_i <= i;
wbs_dat_i <= ROM;
end else if (i < 32'd20) begin // intermediate state
i <= i + 32'd1;
wb_rst_i <= 1'b1;
wbs_stb_i <= 1'b0;
wbs_cyc_i <= 1'b0;
wbs_we_i <= 1'b0;
wbs_sel_i <= 4'b0000;
end else if (i < 32'd40) begin // wb read from memory
i <= i + 32'd1;
wb_rst_i <= 1'b0;
wbs_stb_i <= 1'b1;
wbs_cyc_i <= 1'b1;
wbs_we_i <= 1'b0;
wbs_sel_i <= 4'b0000;
wbs_adr_i <= i - 32'd20;
end else if (i < 32'd50) begin // intermediate state
i <= i + 32'd1;
reset <= 1'b1;
wb_rst_i <= 1'b1;
wbs_stb_i <= 1'b0;
wbs_cyc_i <= 1'b0;
wbs_we_i <= 1'b0;
wbs_sel_i <= 4'b0000;
end else begin // run program (core not reset , wb in reset)
reset <= 1'b0;
wb_rst_i <= 1'b1;
wbs_stb_i <= 1'b0;
wbs_cyc_i <= 1'b0;
wbs_we_i <= 1'b0;
wbs_sel_i <= 4'b0000;
end
end
initial begin
$dumpfile("signals.vcd");
$dumpvars(0, vsdmemsoc_tb);
i = 0;
ext_clk = 0;
reset = 0;
wb_clk_i = 0;
wb_rst_i = 0;
wbs_stb_i = 0;
wbs_cyc_i = 0;
wbs_we_i = 0;
wbs_sel_i = 4'b0;
#5000 $finish;
end
always #5 wb_clk_i = ~wb_clk_i;
always #6 ext_clk = ~ext_clk;
endmodule
| 7.032941 |
module testbench_width; //testbench y probador de DAT
reg [3:0] card_in = 0;
reg [31:0] buffer_in = 0;
wire [31:0] buffer_out;
wire [3:0] card_out;
reg clock;
reg new_trans;
reg enable_write, enable_read, Clear_in, reset;
parameter n = 32;
parameter vector_width = 10; //reg_vector has inputs with information coming from registers
reg [vector_width - 1 : 0] reg_vector = 10'b1101111111;
reg fifo_ack_i = 0;
reg card_ack_i = 0;
reg fifo_full = 0;
reg fifo_empty = 0;
reg mode = 1;
reg [10:0] block_amount = 8;
reg direction = 1;
DAT data_module (
buffer_in, //list
buffer_out, //listo
card_in, //listo
card_out, //listo
clock,
fifo_ack_i,
fifo_ack_o,
fifo_enable_o,
card_ack_i,
card_ack_o,
fifo_full,
fifo_empty,
block_amount,
fifo_ready,
new_trans,
reset,
mode,
direction
);
initial begin
Clear_in = 1;
enable_write = 1;
enable_read = 1;
reset = 0;
clock = 0;
#2 new_trans = 1;
#4 card_in = 4'hF;
#5 card_in = 4'hC;
#4 card_in = 4'h1;
#4 card_in = 4'h0;
#6 card_in = 4'hB;
#3 card_in = 4'h0;
#4 card_in = 4'b1011;
#5 card_in = 4'b0000;
#3 card_in = 4'b1110;
#5 card_in = 4'b0111;
#6 card_in = 4'b1101;
#5 card_in = 4'b0000;
#4 card_in = 4'hF;
#5 card_in = 4'hC;
#4 card_in = 4'h1;
#4 card_in = 4'h0;
#6 card_in = 4'hB;
#3 card_in = 4'h0;
#4 card_in = 4'b1011;
#5 card_in = 4'b0000;
#3 card_in = 4'b1110;
#5 card_in = 4'b0111;
#6 card_in = 4'b1101;
#5 card_in = 4'b0000;
#5 mode = 0;
#4 card_in = 4'hF;
#5 card_in = 4'hC;
#4 card_in = 4'h1;
#4 card_in = 4'h0;
#6 card_in = 4'hB;
#3 card_in = 4'h0;
#4 card_in = 4'b1011;
#5 card_in = 4'b0000;
#3 card_in = 4'b1110;
#5 card_in = 4'b0111;
#6 card_in = 4'b1101;
#5 card_in = 4'b0000;
#5 enable_read = 0;
#30 enable_read = 1;
#400 $finish;
end
initial begin
$dumpfile("testbench_width.vcd");
$dumpvars(0, testbench_width);
end
always #2 clock = !clock;
endmodule
| 7.203513 |
module count_tb;
03 localparam DELY=100;
04 reg clk,reset; //测试输入信号,定义为reg 型
05 wire[3:0] cnt; //测试输出信号,定义为wire型
06
07 always#(DELY/2) clk = ~clk; //产生时钟波形
08 initial
09 begin //激励信号定义
10 clk =0; reset=0;
11 #DELY reset=1;
12 #DELY reset=0;
13 #(DELY*100) $finish(2);
14 end
15 //定义结果显示格式
16 initial $monitor($time," clk=%d reset=%d cnt=%d",clk, reset,cnt);
17 //调用测试对象
18 count#(.N(4))U_cnt(
19 .clk (clk )
20 ,.clear (reset)
21 ,.cnt_Q (cnt )
22 );
23
24 endmodule
| 6.703937 |
module 连续赋值模块名 (
// I/O端口列表说明
input 输入端口列表
output 输出端口列表
);
// 数据类型说明
wire 结果信号名；
// 逻辑功能定义
assign <结果信号名> =逻辑表达式 ；
…
assign <结果信号名n>=逻辑表达式n；
endmodule
| 6.634401 |
module 行为描述模块名 (
// I/O端口列表说明
input 输入端口列表
output reg 输出端口列表
);
// 数据类型说明
reg 中间变量
// 逻辑功能定义
always @(敏感事件列表) //行为描述1
begin
if-else、case、for等行为语句
end
.........
always @(敏感事件列表) //行为描述n
begin
if-else、case、for等行为语句
end
endmodule
| 7.098176 |
module testbench_wrapper #(
parameter DATA_WIDTH = 16,
parameter ARRAY_W = 10, //j
parameter ARRAY_L = 784, //i
parameter CLOCK_DIVIDE = 2
);
reg clk, reset_n, param_load, start_comp;
wire [7:0] hex_output;
sys_array_wrapper #(
.DATA_WIDTH(DATA_WIDTH),
.ARRAY_W(ARRAY_W),
.ARRAY_L(ARRAY_L),
.CLOCK_DIVIDE(CLOCK_DIVIDE)
) wrappper (
.clk(clk),
.reset_n(reset_n),
.load_params(param_load),
.start_comp(start_comp),
.hex_connect(hex_output)
);
initial $dumpvars;
initial begin
clk = 0;
forever #10 clk = !clk;
end
initial begin
reset_n = 0;
param_load = 0;
start_comp = 0;
#80;
reset_n = 1;
#20;
param_load = 1;
#20;
param_load = 0;
#10;
start_comp = 1;
#20;
start_comp = 0;
#100;
end
endmodule
| 8.139825 |
module i2c_slave1 ();
reg clk, rst, enable, read_write;
reg [7:0] data_write;
wire scl;
wire sda;
//reg SDA;
//wire direction=1;
//assign sda=direction?SDA:1'bZ;
wire [7:0] data;
wire [7:0] data_received;
reg scl_in;
//tri1 sda_in;
i2c_master master2 (
clk,
rst,
enable,
read_write,
data_write,
scl,
sda,
data
);
i2c_slave slave2 (
clk,
rst,
enable,
sda,
scl_in,
data_received
);
initial clk = 0;
always #2 clk = ~clk;
initial begin
rst = 1;
enable = 1;
read_write = 1;
data_write = 8'b10110011;
#10 rst = 0;
#350 data_write = 8'b10111100;
#590 $finish;
end
always @(*) scl_in <= scl;
endmodule
| 7.302179 |
module TestBench_Zero_Detector;
reg X, clk, rst;
wire Y;
Zero_Detector ZD (
Y,
X,
clk,
rst
);
initial #200 $finish;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
fork
rst = 0;
#2 rst = 1;
#87 rst = 0;
#89 rst = 1;
#10 X = 1;
#30 X = 0;
#40 X = 1;
#50 X = 0;
#52 X = 1;
#54 X = 0;
#70 X = 1;
#80 X = 1;
#90 X = 1;
#100 X = 0;
#120 X = 1;
#160 X = 0;
#170 X = 1;
join
initial $monitor($time, "\t clk=%b X=%b rst=%b Y=%b", clk, X, rst, Y);
endmodule
| 6.655457 |
module for CRC generators *
* ------------------------------------------------ */
module testboard(
input clk,
input rst,
input RsRx,
output [1:0] led,
output [3:0] an,
output [6:0] seg);
wire [15:0] crc1, crc0;
wire uart_en, clk_uart, uart_newdata;
wire [7:0] uart_data;
wire serial, serial_working;
assign led[1] = crc1 != crc0;
assign led[0] = serial_working;
parallel_to_serial serialier(clk,rst,uart_newdata,uart_data,serial,serial_working);
uart_clk_gen uart_clk(clk,rst,uart_en,clk_uart, 1'b1, 3'd2);
uart_rx uart_core(clk,rst,RsRx,clk_uart,uart_en,1'b1,1'b0,2'd0,uart_data,,,uart_newdata);
ssdController4 ssd_cntrl(clk, rst, 4'b1111, crc0[15:12], crc0[11:8], crc0[7:4], crc0[3:0], seg, an);
localparam CRC_SIZE = 16, //Size of CRC value, all following parameters should have this size
INITAL_VAL = 16'hFFFF, //Initial value for CRC reg
CRC_POLY = 16'h1021, //Polynomial for crc calculation
FINAL_XOR = 16'h0;
crc_static #(CRC_SIZE,INITAL_VAL,CRC_POLY,FINAL_XOR) uut_s(clk,rst,serial,serial_working,crc0);
crc_dynamic #(CRC_SIZE) uut_d(clk,rst,serial,serial_working,crc1,INITAL_VAL,CRC_POLY, FINAL_XOR);
endmodule
| 6.830467 |
module buffer (
s,
p
);
output s;
input p;
assign s = p;
endmodule
| 6.861394 |
module testbuffer;
reg a;
wire s;
// instancia
buffer BF1 (
s,
a
);
initial begin : start
a = 0;
end
// parte principal
initial begin : main
$display("Exemplo 00 - xxx yyy zzz - 999999");
$display("Test buffer");
$display("\na = s\n");
$monitor("%b = %b", a, s);
#1 a = 0;
#1 a = 1;
end
endmodule
| 7.153545 |
module testcache ();
reg clk;
reg re, we, we2, we3;
reg [31:0] address, writedata;
wire [31:0] readdatacache, readmissdata;
wire hit, miss, dirty;
// test
memory_system DUT (
clk,
re,
we,
we2,
we3,
address,
writedata,
readdatacache,
hit,
miss,
dirty
);
// generate clock to sequence tests
always begin
clk <= 1;
#5;
clk <= 0;
#5;
end
// check results
initial begin
/*
re <= 1'b0;
we <= 1'b0;
we2 <=1'b0;
we3 <= 1'b0;
address <= 32'h0;
writedata <= 32'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'h7;
#10;
we <= 1'b0;
#10;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h50;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h54;
writedata <= 32'h7;
#10;
we <= 1'b0;
#200;
*/
// Write Miss: Miss generated, gets main memory, write this data to this cache value
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00004012;
writedata <= 32'h12345678;
#10;
we <= 1'b0;
#200;
we2 <= 1'b1;
#5;
we2 <= 1'b0;
#5;
// Read Hit: Hit generated, no need to go to main memory, read out of cache valid
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00004012;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#10;
// Read Miss: !Hit generated, gets main memory, read out of cache is initialized mainmemory value after writing new cache value
re <= 1'b1;
we <= 1'b0;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008012;
writedata <= 32'hxxxxxxxx;
#10;
re <= 1'b0;
#200;
we3 <= 1'b1;
#5;
we3 <= 1'b0;
#20;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008011;
writedata <= 32'h87654321;
#10;
we <= 1'b0;
#200;
// Write Hit: if in cache, write in cache
re <= 1'b0;
we <= 1'b1;
we2 <= 1'b0;
we3 <= 1'b0;
address <= 32'h00008010;
writedata <= 32'h01010101;
#10;
we <= 1'b0;
#200;
end
endmodule
| 6.753808 |
module testcase8_tb ();
reg sys_clk_n;
reg sys_clk_p;
reg reset;
reg requestDatafromDAC;
wire start_DAC;
wire chip_reset_n;
wire sys_clk;
wire needToLoadData;
wire detectRequestData;
testcase8_start_DAC_2 tb7_uut (
.sys_clk_n(sys_clk_n),
.sys_clk_p(sys_clk_p),
.reset(reset),
.start_DAC(start_DAC),
.chip_reset_n(chip_reset_n),
.sys_clk(sys_clk),
.requestDatafromDAC(requestDatafromDAC),
.needToLoadData(needToLoadData),
.detectRequestData(detectRequestData)
);
initial sys_clk_p = 1'b1;
always #(2.5) sys_clk_p = ~sys_clk_p;
initial sys_clk_n = 1'b0;
always #(2.5) sys_clk_n = ~sys_clk_n;
initial begin
reset = 1'b0;
requestDatafromDAC = 0;
#5;
reset = 1'b1;
#5;
reset = 1'b0;
#800 requestDatafromDAC = 1;
#20 requestDatafromDAC = 0;
#2100 requestDatafromDAC = 1;
#20 requestDatafromDAC = 0;
end
endmodule
| 6.567459 |
module
*
*
* MIT License
*/
module TestClaAdder;
// Inputs
reg [7:0] InputA;
reg [7:0] InputB;
reg InputCarry;
// Outputs
wire [7:0] Sum;
wire OutputCarry;
// Instantiate the Unit Under Test (UUT)
ClaAdder uut (
.InputA(InputA),
.InputB(InputB),
.InputCarry(InputCarry),
.Sum(Sum),
.OutputCarry(OutputCarry)
);
`startTest("ClaAdder")
// Initialize Inputs
InputA = 0;
InputB = 0;
InputCarry = 0;
#100;
`describe("Add 5 + 12");
`assertCheckSum(5, 12);
`describe("Add 0 + 0");
`assertCheckSum(0, 0);
`describe("Add 128 + 127");
`assertCheckSum(128, 127);
`endTest
endmodule
| 7.860622 |
module pulse2 (
signal,
clock
);
input clock;
output signal;
reg signal;
always @(posedge clock) begin
signal = 1'b1;
#5 signal = 1'b0;
end
endmodule
| 6.524618 |
module pulse3 (
signal,
clock
);
input clock;
output signal;
reg signal;
always @(negedge clock) begin
signal = 1'b1;
#15 signal = 1'b0;
#15 signal = 1'b1;
end
endmodule
| 6.545395 |
module TestCodeA (
input wire px_clk, // Pixel clock.
input wire [25:0] RGBStr_i, // Input RGB stream.
input wire [ 7:0] sprite, // Sprite data.
output reg [11:0] addr, // Address ROM where pixel sprites are.
output reg [25:0] RGBStr_o // Output RGB stream.
);
`define YC 12:3 // Y Coordinate
`define XC 22:13 // X Coordinate
//reg [10:0] addr;
//reg [25:0] RGBStr_o;
// Orientation codes.
parameter LEFT = 3'b011,
RIGHT = 3'b000,
UP = 3'b010,
DOWN = 3'b001,
LEFT_MIRROR = 3'b111,
RIGHT_MIRROR = 3'b100,
UP_MIRROR = 3'b110,
DOWN_MIRROR = 3'b101;
wire [7:5] orientation;
wire [3:0] bitmap;
wire [3:0] posx;
wire [3:0] posy;
assign orientation = sprite[7:5];
assign bitmap = sprite[3:0];
assign posx = RGBStr_i[17:13];
assign posy = RGBStr_i[7:3];
always @(px_clk) begin
RGBStr_o <= RGBStr_i;
if (RGBStr_i[0:0]) // Visible pixel.
begin
case (orientation)
LEFT: begin
addr <= {bitmap, posy, posx};
end
RIGHT: begin
addr <= {bitmap, posy, ~posx};
end
UP: begin
addr <= {bitmap, posx, ~posy};
end
DOWN: begin
addr <= {bitmap, posx, posy};
end
LEFT_MIRROR: begin
addr <= {bitmap, ~posy, posx};
end
RIGHT_MIRROR: begin
addr <= {bitmap, ~posy, ~posx};
end
UP_MIRROR: begin
addr <= {bitmap, ~posx, ~posy};
end
DOWN_MIRROR: begin
addr <= {bitmap, ~posx, posy};
end
default: begin
addr <= {bitmap, posy, posx};
end
endcase
end
end
endmodule
| 7.821935 |
module testcontroller (
input wire clk,
input wire secure_mode,
input wire test_mode,
input wire reset_n,
output wire enableScanIn,
output wire enableScanOut,
output wire loadkey,
output wire scan_mode
);
wire FFin;
wire FFout;
DFF register (
.reset_n(reset_n),
.clk(clk),
.D(FFin),
.Q(FFout)
);
assign FFin = secure_mode | FFout;
assign loadkey = FFout;
assign enableScanIn = ~FFout;
assign enableScanOut = ~FFout;
assign scan_mode = test_mode & ~FFout;
endmodule
| 6.773203 |
module DFF (
input wire clk,
input wire reset_n,
input wire D,
output reg Q
);
always @(posedge clk) begin
if (reset_n == 1) begin
Q <= D;
end else begin
Q <= 1'b0;
end
end
endmodule
| 7.464833 |
module testCPUController;
reg clk;
reg rst;
reg [15:0] opcode;
cpuController cpuCTRL (
.clk(clk),
.rst(rst),
.opcode(opcode)
);
initial begin
$dumpfile("../test.vcd");
$dumpvars;
end
always #5 clk = !clk;
initial begin
clk = 0;
rst = 1;
opcode = 0;
#10 rst = 0;
#10 opcode = 16'b0000000000100001;
#20 $finish;
end
endmodule
| 6.817465 |
module testdata (
clk,
dataout,
wrsig
);
input clk;
output [7:0] dataout;
output wrsig;
reg [7:0] dataout;
reg wrsig;
reg [7:0] cnt;
reg [4:0] i;
reg [7:0] volt [8:0]; //存储字符voltage:
initial begin
//定义发送的字符
volt[0] <= 118; //存储字符v
volt[1] <= 111; //存储字符o
volt[2] <= 108; //存储字符l
volt[3] <= 116; //存储字符t
volt[4] <= 97; //存储字符a
volt[5] <= 103; //存储字符g
volt[6] <= 101; //存储字符e
volt[7] <= 58; //存储字符:
volt[8] <= 10; //换行符
end
always @(posedge clk) begin
if (cnt == 254) begin
dataout <= volt[i]; //每次数据加"1"
wrsig <= 1'b1; //产生发送命令
cnt <= 0;
i <= i + 1'b1;
if (i == 8) i <= 0;
end else begin
wrsig <= 1'b0;
cnt <= cnt + 8'd1;
end
end
endmodule
| 6.806681 |
module: DataMemoryPipline
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testDataMemory;
// Inputs
reg zero;
reg branch;
reg memRead;
reg memWrite;
reg [31:0] readData2Reg;
reg [31:0] aluRes;
reg clk;
// Outputs
wire pc_src;
wire [31:0] readData;
wire [31:0] aluResOut;
// Instantiate the Unit Under Test (UUT)
DataMemoryPipline uut (
.zero(zero),
.branch(branch),
.memRead(memRead),
.memWrite(memWrite),
.readData2Reg(readData2Reg),
.aluRes(aluRes),
.clk(clk),
.pc_src(pc_src),
.readData(readData),
.aluResOut(aluResOut)
);
initial begin
// Initialize Inputs
zero = 0;
branch = 0;
memRead = 0;
memWrite = 0;
readData2Reg = 0;
aluRes = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
zero = 1;
branch = 1;
memRead = 1;
memWrite = 0;
readData2Reg = 0;
aluRes = 5;
#100;
zero = 0;
branch = 1;
memRead = 0;
memWrite = 1;
readData2Reg = 8;
aluRes = 5;
// Add stimulus here
end
always begin
#50;
clk=~clk;
end
endmodule
| 6.628923 |
module
*
*
* MIT License
*/
module TestDebouncer;
// Inputs
`defClock(Clk, 2);
reg Input;
// Outputs
wire Output;
// Instantiate the Unit Under Test (UUT)
Debouncer #(
.DEBOUNCER_COUNTER_WIDTH(3)
) uut (
.Clk(Clk),
.Input(Input),
.Output(Output)
);
`startTest("Debouncer")
// Initialize Inputs
Clk = 0;
Input = 0;
#500;
`describe("Test oscillating input");
Input = 1; #2; `assert(Output, 0);
Input = 0; #2; `assert(Output, 0);
Input = 1; #2; `assert(Output, 0);
Input = 0; #2; `assert(Output, 0);
Input = 0; #2; `assert(Output, 0);
Input = 0; #2; `assert(Output, 0);
Input = 0; #2; `assert(Output, 0);
Input = 1; #2; `assert(Output, 0);
Input = 1; #2; `assert(Output, 0);
Input = 1; #2; `assert(Output, 0);
Input = 1; #2; `assert(Output, 0);
Input = 1; #2; `assert(Output, 0);
Input = 1; #2; `assert(Output, 1);
for(int i=0;i<20;i=i+1)
begin
Input = 1; #2; `assert(Output, 0);
end
for(int i=0;i<500;i=i+1)
begin
Input = 0; #2; `assert(Output, 0);
end
`endTest
endmodule
| 7.860622 |
module: decode
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testdecode1;
// Inputs
reg [31:0] instruction;
reg [4:0] writeReg;
reg [31:0] writeData;
reg regWrite;
reg clk;
// Outputs
wire [31:0] rd1;
wire [31:0] rd2;
wire [4:0] ins1;
wire [4:0] ins2;
wire [31:0] insOut;
wire [31:0] signEx;
// Instantiate the Unit Under Test (UUT)
decode uut (
.instruction(instruction),
.writeReg(writeReg),
.writeData(writeData),
.regWrite(regWrite),
.clk(clk),
.rd1(rd1),
.rd2(rd2),
.ins1(ins1),
.ins2(ins2),
.insOut(insOut),
.signEx(signEx)
);
initial begin
// Initialize Inputs
instruction = 67;
writeReg = 0;
writeData = 0;
regWrite = 0;
clk = 0;
// Wait 100 ns for global reset to finish
#100;
instruction = 87;
writeReg = 2;
writeData = 35;
regWrite = 1;
// Add stimulus here
end
always begin
#50;
clk=~clk;
end
endmodule
| 6.50658 |
module testDec_flow_control_loop_pipe_sequential_init (
ap_clk,
ap_rst,
ap_start,
ap_ready,
ap_done,
ap_start_int,
ap_ready_int,
ap_done_int,
ap_continue_int,
ap_loop_init,
ap_loop_exit_ready,
ap_loop_exit_done
);
input ap_clk;
input ap_rst;
//Block level handshake with outside loop
input ap_start;
output ap_ready;
output ap_done;
//Block level handshake with loop body
output ap_start_int;
input ap_ready_int;
input ap_done_int;
output ap_continue_int;
//Init live in variables
output ap_loop_init;
wire ap_loop_init;
reg ap_loop_init_int;
reg ap_done;
reg ap_done_cache;
//Exit signal from loop body
input ap_loop_exit_ready;
input ap_loop_exit_done;
// power-on initialization
initial begin
#0 ap_loop_init_int = 1'b1;
#0 ap_done_cache = 1'b0;
end
assign ap_start_int = ap_start;
assign ap_continue_int = 1'b1;
assign ap_ready = ap_loop_exit_ready;
//ap_loop_init is valid for the first II
//of the first loop run so as to enable
//the init block ops which are pushed into
//the first state of the pipeline region
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_loop_init_int <= 1'b1;
end else if (ap_loop_exit_done == 1'b1) begin
ap_loop_init_int <= 1'b1;
end else if (ap_ready_int == 1'b1) begin
ap_loop_init_int <= 1'b0;
end
end
assign ap_loop_init = ap_loop_init_int & ap_start;
// if no ap_continue port and current module is not top module,
// ap_done handshakes with ap_start. Internally, flow control sends out
// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle.
// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int
// is asserted, so DUT can start the next run
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_cache <= 1'b0;
end else if (ap_done_int == 1'b1) begin
ap_done_cache <= 1'b1;
end else if (ap_start_int == 1'b1) begin
ap_done_cache <= 1'b0;
end
end
// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start
always @(*) begin
if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
endmodule
| 7.489365 |
module testdesign (
`ifdef USE_POWER_PINS
inout vdda,
inout vssa,
inout vccd,
inout vssd,
`endif
input wire clk,
input wire reset,
input wire [7:0] in,
output reg [7:0] out,
output reg [15:0] oeb
);
always @(posedge clk) begin
out <= in;
oeb[15:8] <= 1;
oeb[7:0] <= 0;
if (reset) begin
oeb[15:8] <= 0;
out <= 0;
end
end
endmodule
| 7.837218 |
module testDFlipFlop ();
reg clock, nreset, d;
DFlipFlop D1 (
q,
clock,
nreset,
d
);
always #10 clock = ~clock;
initial begin
//$dumpfile("testDFlipFlop.dump");
//$dumpvars(1,D1);
#0 d = 0;
clock = 0;
nreset = 1;
#55 nreset = 0;
#10 d = 0;
clock = 0;
#55 nreset = 1;
#1000 $finish;
end
always #10 d = ~d;
endmodule
| 6.697297 |
module: qdiv
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestDiv;
// Inputs
reg [31:0] i_dividend;
reg [31:0] i_divisor;
reg i_start;
reg i_clk;
// Outputs
wire [31:0] o_quotient_out;
wire o_complete;
wire o_overflow;
// Instantiate the Unit Under Test (UUT)
qdiv uut (
.i_dividend(i_dividend),
.i_divisor(i_divisor),
.i_start(i_start),
.i_clk(i_clk),
.o_quotient_out(o_quotient_out),
.o_complete(o_complete),
.o_overflow(o_overflow)
);
reg [10:0] count;
initial begin
// Initialize Inputs
i_dividend = 1;
i_divisor = 1;
i_start = 0;
i_clk = 0;
count <= 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever #2 i_clk = ~i_clk;
end
always @(posedge i_clk) begin
if (count == 47) begin
count <= 0;
i_start <= 1'b1;
end
else begin
count <= count + 1;
i_start <= 1'b0;
end
end
always @(count) begin
if (count == 47) begin
if ( i_divisor > 32'h1FFFFFFF ) begin
i_divisor <= 1;
i_dividend = (i_dividend << 1) + 3;
end
else
i_divisor = (i_divisor << 1) + 1;
end
end
always @(posedge o_complete)
$display ("%b,%b,%b, %b", i_dividend, i_divisor, o_quotient_out, o_overflow); // Monitor the stuff we care about
endmodule
| 6.558319 |
module: qdiv
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestDiv;
// Inputs
reg [63:0] i_dividend;
reg [63:0] i_divisor;
reg i_start;
reg i_clk;
reg [13:0] count;
reg [8:0] temp_divisor;
reg [8:0] temp_dividend;
// Outputs
wire [63:0] o_quotient_out;
wire o_complete;
wire o_overflow;
// Instantiate the Unit Under Test (UUT)
qdiv #(32,64) uut (
.i_dividend(i_dividend),
.i_divisor(i_divisor),
.i_start(i_start),
.i_clk(i_clk),
.o_quotient_out(o_quotient_out),
.o_complete(o_complete),
.o_overflow(o_overflow)
);
initial begin
// Initialize Inputs
i_dividend = 0;
i_divisor = 0;
i_start = 0;
i_clk = 0;
count = 0;
temp_divisor = 0;
temp_dividend = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
forever begin
#1 i_clk = ~i_clk;
end
end
always @(posedge i_clk) begin
if (count == 1) begin
i_start <= 1;
end
if (count == 3) begin
i_start <= 0;
end
if (count == 220) begin
count = 0; // reset the count
if (temp_divisor > 255) begin // if divisor maxed;
temp_divisor <= 0; // reset to zero
temp_dividend <= temp_dividend + 1; // and increment dividend
end
else begin
temp_divisor <= temp_divisor + 1; // otherwise, increment divisor
end
i_dividend <= temp_dividend << 32; // Set i_dividend
i_divisor <= temp_divisor << 32; // Set i_dividor
end
count <= count + 1; // Update count
end
always @(posedge o_complete) begin
$display ("%b,%b,%b,%b", i_dividend, i_divisor, o_quotient_out, o_overflow);
end
endmodule
| 6.558319 |
module TestDriver;
reg clock = 1'b0;
reg reset = 1'b1;
always #(`CLOCK_PERIOD / 2.0) clock = ~clock;
initial #(`RESET_DELAY) reset = 0;
// Read input arguments and initialize
reg verbose = 1'b0;
wire printf_cond = verbose && !reset;
reg [63:0] max_cycles = 0;
reg [63:0] dump_start = 0;
reg [63:0] trace_count = 0;
reg [2047:0] fsdbfile = 0;
reg [2047:0] vcdplusfile = 0;
reg [2047:0] vcdfile = 0;
int unsigned rand_value;
initial begin
void'($value$plusargs("max-cycles=%d", max_cycles));
void'($value$plusargs("dump-start=%d", dump_start));
verbose = $test$plusargs("verbose");
// do not delete the lines below.
// $random function needs to be called with the seed once to affect all
// the downstream $random functions within the Chisel-generated Verilog
// code.
// $urandom is seeded via cmdline (+ntb_random_seed in VCS) but that
// doesn't seed $random.
rand_value = $urandom;
rand_value = $random(rand_value);
if (verbose) begin
`ifdef VCS
$fdisplay(stderr, "testing $random %0x seed %d", rand_value,
unsigned'($get_initial_random_seed));
`else
$fdisplay(stderr, "testing $random %0x", rand_value);
`endif
end
`ifdef DEBUG
if ($value$plusargs("vcdplusfile=%s", vcdplusfile)) begin
`ifdef VCS
$vcdplusfile(vcdplusfile);
`else
$fdisplay(stderr,
"Error: +vcdplusfile is VCS-only; use +vcdfile instead or recompile with VCS=1");
$fatal;
`endif
end
if ($value$plusargs("fsdbfile=%s", fsdbfile)) begin
`ifdef FSDB
$fsdbDumpfile(fsdbfile);
$fsdbDumpvars("+all");
//$fsdbDumpSVA;
`else
$fdisplay(
stderr,
"Error: +fsdbfile is FSDB-only; use +vcdfile/+vcdplus instead or recompile with FSDB=1");
$fatal;
`endif
end
if ($value$plusargs("vcdfile=%s", vcdfile)) begin
$dumpfile(vcdfile);
$dumpvars(0, testHarness);
end
`ifdef FSDB
`define VCDPLUSON $fsdbDumpon;
`define VCDPLUSCLOSE $fsdbDumpoff;
`elsif VCS
`define VCDPLUSON $vcdpluson(0); $vcdplusmemon(0);
`define VCDPLUSCLOSE $vcdplusclose; $dumpoff;
`else
`define VCDPLUSON $dumpon;
`define VCDPLUSCLOSE $dumpoff;
`endif
`else
// No +define+DEBUG
`define VCDPLUSON
`define VCDPLUSCLOSE
if ($test$plusargs(
"vcdplusfile="
) || $test$plusargs(
"vcdfile="
) || $test$plusargs(
"fsdbfile="
)) begin
$fdisplay(
stderr,
"Error: +vcdfile, +vcdplusfile, or +fsdbfile requested but compile did not have +define+DEBUG enabled");
$fatal;
end
`endif
if (dump_start == 0) begin
// Start dumping before first clock edge to capture reset sequence in waveform
`VCDPLUSON
end
end
`ifdef TESTBENCH_IN_UVM
// UVM library has its own way to manage end-of-simulation.
// A UVM-based testbench will raise an objection, watch this signal until this goes 1, then drop the objection.
reg finish_request = 1'b0;
`endif
reg [255:0] reason = "";
reg failure = 1'b0;
wire success;
integer stderr = 32'h80000002;
always @(posedge clock) begin
`ifdef GATE_LEVEL
if (verbose) begin
$fdisplay(stderr, "C: %10d", trace_count);
end
`endif
trace_count = trace_count + 1;
if (trace_count == dump_start) begin
`VCDPLUSON
end
if (!reset) begin
if (max_cycles > 0 && trace_count > max_cycles) begin
reason = " (timeout)";
failure = 1'b1;
end
if (failure) begin
$fdisplay(stderr, "*** FAILED ***%s after %d simulation cycles", reason, trace_count);
`VCDPLUSCLOSE
$fatal;
end
if (success) begin
if (verbose)
$fdisplay(stderr, "*** PASSED *** Completed after %d simulation cycles", trace_count);
`VCDPLUSCLOSE
`ifdef TESTBENCH_IN_UVM
finish_request = 1;
`else
$finish;
`endif
end
end
end
`MODEL testHarness (
.clock(clock),
.reset(reset),
.io_success(success)
);
endmodule
| 7.441403 |
module egate (
s,
p,
q
);
output s;
input p, q;
assign s = p & q;
endmodule
| 6.731803 |
module testegate;
reg a, b;
wire s;
egate AND1 (
s,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
initial begin : main
$display("Guia02 exercicio 02");
$display("tabela-verdade para porta AND\n");
$display("a & b = s");
$monitor("%b & %b = %b", a, b, s);
#1 a = 0;
b = 1;
#1 a = 1;
b = 0;
#1 a = 1;
b = 1;
end
endmodule
| 6.673264 |
module testnorgate;
reg a, b, c;
wire s;
nor (s, a, b, c);
endmodule
| 6.695863 |
module testeio_MemAddr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 7:0] data_out;
wire [ 7:0] out_port;
wire [ 7:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.599329 |
module testeio_MemOut (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [7:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [ 7:0] data_out;
wire [ 7:0] out_port;
wire [ 7:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.656136 |
module testeio_mem_ack_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.612318 |
module testeio_mem_addr (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
);
output [15:0] out_port;
output [31:0] readdata;
input [1:0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [31:0] writedata;
wire clk_en;
reg [15:0] data_out;
wire [15:0] out_port;
wire [15:0] read_mux_out;
wire [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {16{(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) data_out <= 0;
else if (chipselect && ~write_n && (address == 0)) data_out <= writedata[15 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
| 6.612318 |
module testeio_mem_data (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input [7:0] in_port;
input reset_n;
wire clk_en;
wire [ 7:0] data_in;
wire [ 7:0] read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.742045 |
module testeio_mem_data_ready (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
);
output [31:0] readdata;
input [1:0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [31:0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1{(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0) readdata <= 0;
else if (clk_en) readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
| 6.742045 |
module testeio_onchip_memory2_0 (
// inputs:
address,
chipselect,
clk,
clken,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
);
parameter INIT_FILE = "testeio_onchip_memory2_0.hex";
output [7:0] readdata;
input [7:0] address;
input chipselect;
input clk;
input clken;
input freeze;
input reset;
input reset_req;
input write;
input [7:0] writedata;
wire clocken0;
wire [7:0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram (
.address_a(address),
.clock0(clk),
.clocken0(clocken0),
.data_a(writedata),
.q_a(readdata),
.wren_a(wren)
);
defparam the_altsyncram.byte_size = 8, the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_hint = "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=BOB",
the_altsyncram.lpm_type = "altsyncram", the_altsyncram.maximum_depth = 256,
the_altsyncram.numwords_a = 256, the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED", the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE", the_altsyncram.width_a = 8,
the_altsyncram.widthad_a = 8;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 6.755947 |
module testeio_two_port_mem (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
clk2,
clken,
clken2,
freeze,
reset,
reset2,
reset_req,
reset_req2,
write,
write2,
writedata,
writedata2,
// outputs:
readdata,
readdata2
)
;
parameter INIT_FILE = "testeio_two_port_mem.hex";
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 14: 0] address;
input [ 14: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
input chipselect2;
input clk;
input clk2;
input clken;
input clken2;
input freeze;
input reset;
input reset2;
input reset_req;
input reset_req2;
input write;
input write2;
input [ 31: 0] writedata;
input [ 31: 0] writedata2;
wire clocken0;
wire clocken1;
wire [ 31: 0] readdata;
wire [ 31: 0] readdata2;
wire wren;
wire wren2;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
assign clocken1 = clken2 & ~reset_req2;
assign wren2 = chipselect2 & write2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clock1 (clk2),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (wren),
.wren_b (wren2)
);
defparam the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK1",
the_altsyncram.indata_reg_b = "CLOCK1",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768,
the_altsyncram.numwords_b = 32768,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 15,
the_altsyncram.widthad_b = 15,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 7.88217 |
module testeio_two_port_mem_correct (
// inputs:
address,
address2,
byteenable,
byteenable2,
chipselect,
chipselect2,
clk,
clk2,
clken,
clken2,
freeze,
reset,
reset2,
reset_req,
reset_req2,
write,
write2,
writedata,
writedata2,
// outputs:
readdata,
readdata2
)
;
parameter INIT_FILE = "testeio_two_port_mem_correct.hex";
output [ 31: 0] readdata;
output [ 31: 0] readdata2;
input [ 14: 0] address;
input [ 14: 0] address2;
input [ 3: 0] byteenable;
input [ 3: 0] byteenable2;
input chipselect;
input chipselect2;
input clk;
input clk2;
input clken;
input clken2;
input freeze;
input reset;
input reset2;
input reset_req;
input reset_req2;
input write;
input write2;
input [ 31: 0] writedata;
input [ 31: 0] writedata2;
wire clocken0;
wire clocken1;
wire [ 31: 0] readdata;
wire [ 31: 0] readdata2;
wire wren;
wire wren2;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
assign clocken1 = clken2 & ~reset_req2;
assign wren2 = chipselect2 & write2;
altsyncram the_altsyncram
(
.address_a (address),
.address_b (address2),
.byteena_a (byteenable),
.byteena_b (byteenable2),
.clock0 (clk),
.clock1 (clk2),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (writedata),
.data_b (writedata2),
.q_a (readdata),
.q_b (readdata2),
.wren_a (wren),
.wren_b (wren2)
);
defparam the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.byte_size = 8,
the_altsyncram.byteena_reg_b = "CLOCK1",
the_altsyncram.indata_reg_b = "CLOCK1",
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32768,
the_altsyncram.numwords_a = 32768,
the_altsyncram.numwords_b = 32768,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.width_byteena_b = 4,
the_altsyncram.widthad_a = 15,
the_altsyncram.widthad_b = 15,
the_altsyncram.wrcontrol_wraddress_reg_b = "CLOCK1";
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
| 7.88217 |
module testEnc_flow_control_loop_pipe_sequential_init (
ap_clk,
ap_rst,
ap_start,
ap_ready,
ap_done,
ap_start_int,
ap_ready_int,
ap_done_int,
ap_continue_int,
ap_loop_init,
ap_loop_exit_ready,
ap_loop_exit_done
);
input ap_clk;
input ap_rst;
//Block level handshake with outside loop
input ap_start;
output ap_ready;
output ap_done;
//Block level handshake with loop body
output ap_start_int;
input ap_ready_int;
input ap_done_int;
output ap_continue_int;
//Init live in variables
output ap_loop_init;
wire ap_loop_init;
reg ap_loop_init_int;
reg ap_done;
reg ap_done_cache;
//Exit signal from loop body
input ap_loop_exit_ready;
input ap_loop_exit_done;
// power-on initialization
initial begin
#0 ap_loop_init_int = 1'b1;
#0 ap_done_cache = 1'b0;
end
assign ap_start_int = ap_start;
assign ap_continue_int = 1'b1;
assign ap_ready = ap_loop_exit_ready;
//ap_loop_init is valid for the first II
//of the first loop run so as to enable
//the init block ops which are pushed into
//the first state of the pipeline region
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_loop_init_int <= 1'b1;
end else if (ap_loop_exit_done == 1'b1) begin
ap_loop_init_int <= 1'b1;
end else if (ap_ready_int == 1'b1) begin
ap_loop_init_int <= 1'b0;
end
end
assign ap_loop_init = ap_loop_init_int & ap_start;
// if no ap_continue port and current module is not top module,
// ap_done handshakes with ap_start. Internally, flow control sends out
// ap_conintue_int = 1'b1 so the ap_done_int is asserted high for 1 clock cycle.
// ap_done_cache is used to record ap_done_int, and de-assert if ap_start_int
// is asserted, so DUT can start the next run
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_cache <= 1'b0;
end else if (ap_done_int == 1'b1) begin
ap_done_cache <= 1'b1;
end else if (ap_start_int == 1'b1) begin
ap_done_cache <= 1'b0;
end
end
// if no ap_continue port and current module is not top module, ap_done handshakes with ap_start
always @(*) begin
if ((ap_done_int == 1'b1) || ((ap_done_cache == 1'b1) && (ap_start_int == 1'b0))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
endmodule
| 7.774457 |
module testEnc_mux_134_128_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
din10_WIDTH = 32,
din11_WIDTH = 32,
din12_WIDTH = 32,
din13_WIDTH = 32,
dout_WIDTH = 32
) (
input [127 : 0] din0,
input [127 : 0] din1,
input [127 : 0] din2,
input [127 : 0] din3,
input [127 : 0] din4,
input [127 : 0] din5,
input [127 : 0] din6,
input [127 : 0] din7,
input [127 : 0] din8,
input [127 : 0] din9,
input [127 : 0] din10,
input [127 : 0] din11,
input [127 : 0] din12,
input [ 3 : 0] din13,
output [127 : 0] dout
);
// puts internal signals
wire [ 3 : 0] sel;
// level 1 signals
wire [127 : 0] mux_1_0;
wire [127 : 0] mux_1_1;
wire [127 : 0] mux_1_2;
wire [127 : 0] mux_1_3;
wire [127 : 0] mux_1_4;
wire [127 : 0] mux_1_5;
wire [127 : 0] mux_1_6;
// level 2 signals
wire [127 : 0] mux_2_0;
wire [127 : 0] mux_2_1;
wire [127 : 0] mux_2_2;
wire [127 : 0] mux_2_3;
// level 3 signals
wire [127 : 0] mux_3_0;
wire [127 : 0] mux_3_1;
// level 4 signals
wire [127 : 0] mux_4_0;
assign sel = din13;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
assign mux_1_4 = (sel[0] == 0) ? din8 : din9;
assign mux_1_5 = (sel[0] == 0) ? din10 : din11;
assign mux_1_6 = din12;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
assign mux_2_2 = (sel[1] == 0) ? mux_1_4 : mux_1_5;
assign mux_2_3 = mux_1_6;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
assign mux_3_1 = (sel[2] == 0) ? mux_2_2 : mux_2_3;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0) ? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
| 6.958718 |
module testEnc_mux_144_128_1_1 #(
parameter ID = 0,
NUM_STAGE = 1,
din0_WIDTH = 32,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
din10_WIDTH = 32,
din11_WIDTH = 32,
din12_WIDTH = 32,
din13_WIDTH = 32,
din14_WIDTH = 32,
dout_WIDTH = 32
) (
input [127 : 0] din0,
input [127 : 0] din1,
input [127 : 0] din2,
input [127 : 0] din3,
input [127 : 0] din4,
input [127 : 0] din5,
input [127 : 0] din6,
input [127 : 0] din7,
input [127 : 0] din8,
input [127 : 0] din9,
input [127 : 0] din10,
input [127 : 0] din11,
input [127 : 0] din12,
input [127 : 0] din13,
input [ 3 : 0] din14,
output [127 : 0] dout
);
// puts internal signals
wire [ 3 : 0] sel;
// level 1 signals
wire [127 : 0] mux_1_0;
wire [127 : 0] mux_1_1;
wire [127 : 0] mux_1_2;
wire [127 : 0] mux_1_3;
wire [127 : 0] mux_1_4;
wire [127 : 0] mux_1_5;
wire [127 : 0] mux_1_6;
// level 2 signals
wire [127 : 0] mux_2_0;
wire [127 : 0] mux_2_1;
wire [127 : 0] mux_2_2;
wire [127 : 0] mux_2_3;
// level 3 signals
wire [127 : 0] mux_3_0;
wire [127 : 0] mux_3_1;
// level 4 signals
wire [127 : 0] mux_4_0;
assign sel = din14;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0) ? din0 : din1;
assign mux_1_1 = (sel[0] == 0) ? din2 : din3;
assign mux_1_2 = (sel[0] == 0) ? din4 : din5;
assign mux_1_3 = (sel[0] == 0) ? din6 : din7;
assign mux_1_4 = (sel[0] == 0) ? din8 : din9;
assign mux_1_5 = (sel[0] == 0) ? din10 : din11;
assign mux_1_6 = (sel[0] == 0) ? din12 : din13;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0) ? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0) ? mux_1_2 : mux_1_3;
assign mux_2_2 = (sel[1] == 0) ? mux_1_4 : mux_1_5;
assign mux_2_3 = mux_1_6;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0) ? mux_2_0 : mux_2_1;
assign mux_3_1 = (sel[2] == 0) ? mux_2_2 : mux_2_3;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0) ? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
| 6.958718 |
module testEnc_regslice_both #(
parameter DataWidth = 32
) (
input ap_clk,
input ap_rst,
input [DataWidth-1:0] data_in,
input vld_in,
output ack_in,
output [DataWidth-1:0] data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire [DataWidth-1:0] B_V_data_1_data_in;
reg [DataWidth-1:0] B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg [DataWidth-1:0] B_V_data_1_payload_A;
reg [DataWidth-1:0] B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.565231 |
module testEnc_regslice_both_w1 #(
parameter DataWidth = 1
) (
input ap_clk,
input ap_rst,
input data_in,
input vld_in,
output ack_in,
output data_out,
output vld_out,
input ack_out,
output apdone_blk
);
reg [1:0] B_V_data_1_state;
wire B_V_data_1_data_in;
reg B_V_data_1_data_out;
wire B_V_data_1_vld_reg;
wire B_V_data_1_vld_in;
wire B_V_data_1_vld_out;
reg B_V_data_1_payload_A;
reg B_V_data_1_payload_B;
reg B_V_data_1_sel_rd;
reg B_V_data_1_sel_wr;
wire B_V_data_1_sel;
wire B_V_data_1_load_A;
wire B_V_data_1_load_B;
wire B_V_data_1_state_cmp_full;
wire B_V_data_1_ack_in;
wire B_V_data_1_ack_out;
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_out) & (1'b1 == B_V_data_1_ack_out))) begin
B_V_data_1_sel_rd <= ~B_V_data_1_sel_rd;
end else begin
B_V_data_1_sel_rd <= B_V_data_1_sel_rd;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_in))) begin
B_V_data_1_sel_wr <= ~B_V_data_1_sel_wr;
end else begin
B_V_data_1_sel_wr <= B_V_data_1_sel_wr;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
B_V_data_1_state <= 2'd0;
end else begin
if ((((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) | ((2'd2 == B_V_data_1_state) & (1'b0 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd2;
end else if ((((2'd1 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out)) | ((2'd3 == B_V_data_1_state) & (1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd1;
end else if ((((2'd1 == B_V_data_1_state) & (1'b1 == B_V_data_1_ack_out)) | (~((1'b0 == B_V_data_1_ack_out) & (1'b1 == B_V_data_1_vld_in)) & ~((1'b0 == B_V_data_1_vld_in) & (1'b1 == B_V_data_1_ack_out)) & (2'd3 == B_V_data_1_state)) | ((2'd2 == B_V_data_1_state) & (1'b1 == B_V_data_1_vld_in)))) begin
B_V_data_1_state <= 2'd3;
end else begin
B_V_data_1_state <= 2'd2;
end
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_A)) begin
B_V_data_1_payload_A <= B_V_data_1_data_in;
end
end
always @(posedge ap_clk) begin
if ((1'b1 == B_V_data_1_load_B)) begin
B_V_data_1_payload_B <= B_V_data_1_data_in;
end
end
always @(*) begin
if ((1'b1 == B_V_data_1_sel)) begin
B_V_data_1_data_out = B_V_data_1_payload_B;
end else begin
B_V_data_1_data_out = B_V_data_1_payload_A;
end
end
assign B_V_data_1_ack_in = B_V_data_1_state[1'd1];
assign B_V_data_1_load_A = (~B_V_data_1_sel_wr & B_V_data_1_state_cmp_full);
assign B_V_data_1_load_B = (B_V_data_1_state_cmp_full & B_V_data_1_sel_wr);
assign B_V_data_1_sel = B_V_data_1_sel_rd;
assign B_V_data_1_state_cmp_full = ((B_V_data_1_state != 2'd1) ? 1'b1 : 1'b0);
assign B_V_data_1_vld_out = B_V_data_1_state[1'd0];
assign ack_in = B_V_data_1_ack_in;
assign B_V_data_1_data_in = data_in;
assign B_V_data_1_vld_in = vld_in;
assign vld_out = B_V_data_1_vld_out;
assign data_out = B_V_data_1_data_out;
assign B_V_data_1_ack_out = ack_out;
assign apdone_blk = ((B_V_data_1_state == 2'd3 && ack_out == 1'b0) | (B_V_data_1_state == 2'd1));
endmodule
| 6.565231 |
module testEnc_updateKey_Rcon_ROM_AUTO_1R (
address0,
ce0,
q0,
reset,
clk
);
parameter DataWidth = 8;
parameter AddressWidth = 4;
parameter AddressRange = 10;
input [AddressWidth-1:0] address0;
input ce0;
output reg [DataWidth-1:0] q0;
input reset;
input clk;
reg [DataWidth-1:0] ram[0:AddressRange-1];
initial begin
$readmemh("./testEnc_updateKey_Rcon_ROM_AUTO_1R.dat", ram);
end
always @(posedge clk) begin
if (ce0) begin
q0 <= ram[address0];
end
end
endmodule
| 6.583559 |
module tester ();
reg [3:0] screen[HEIGHT-1:0][WIDTH-1:0][2:0];
parameter WIDTH = 640;
parameter HEIGHT = 480;
parameter LINE = 800;
parameter SCREEN = 525;
parameter N_CASES = 1;
parameter AFTER_HSYNC = 47;
parameter AFTER_VSYNC = 31;
integer i;
integer j;
integer k;
reg clk = 0;
reg [ 10:0] cur_x = 0;
reg [ 10:0] cur_y = 0;
reg [N_CASES:0] pass = 1;
wire [ 3:0] vgaRed;
wire [ 3:0] vgaGreen;
wire [ 3:0] vgaBlue;
wire Hsync;
wire Vsync;
reg x_updated = 0;
reg y_updated = 0;
integer incorrect_1 = 0;
integer incorrect_2 = 0;
reg rx = 1;
wire tx;
reg [ 7:0] K_UP = 8'h77; //w
reg [ 7:0] K_DOWN = 8'h73; //s
reg [ 7:0] K_RIGHT = 8'h64; //d
reg [ 7:0] K_LEFT = 8'h61; //a
reg [ 7:0] K_WHITE = 8'h20; //SPACE
reg [ 7:0] K_MAGENTA = 8'h6d; //m
reg [ 7:0] K_CYAN = 8'h63; //c
reg [ 7:0] K_YELLOW = 8'h79; //y
always #1 clk = ~clk;
// Test System for Test#1 should named `vgaSystem` and have following port
vgaSystem test (
.clk (clk), // board clock: 100 MHz from BASYS3 board
.Hsync (Hsync), // horizontal sync output
.Vsync (Vsync), // vertical sync output
.vgaRed (vgaRed), // 4-bit VGA red output
.vgaGreen(vgaGreen), // 4-bit VGA green output
.vgaBlue (vgaBlue) // 4-bit VGA blue output)
);
initial begin
// Initial Screen
for (i = 0; i < HEIGHT; i = i + 1)
for (j = 0; j < WIDTH; j = j + 1) for (k = 0; k < 2; k = k + 1) screen[i][j][k] = 0;
// Test #1: White circle with radius of 10 pixel
// This testcase will read only 640*480 pixels
// since there are many standard for front/back porch and sync duration
// (More info: http://martin.hinner.info/vga/timing.html)
// However, this test case will check only industry standard one
// (and all of them are working!)
// Wait at least 2 frame to ensure that complete image comes
for (i = 0; i < LINE * SCREEN * 2; i = i + 1) begin
#8 begin
if (cur_x > AFTER_HSYNC && cur_y > AFTER_VSYNC) begin
screen[cur_y-AFTER_VSYNC][cur_x-AFTER_HSYNC][0] <= vgaRed;
screen[cur_y-AFTER_VSYNC][cur_x-AFTER_HSYNC][1] <= vgaGreen;
screen[cur_y-AFTER_VSYNC][cur_x-AFTER_HSYNC][2] <= vgaBlue;
end
if (Hsync == 0) begin
cur_x <= 0;
if (y_updated == 0 && Vsync)
cur_y <= (cur_y + 1 < HEIGHT + AFTER_VSYNC) ? cur_y + 1 : cur_y;
y_updated <= 1;
end else begin
if (Vsync) cur_x <= (cur_x + 1 < WIDTH + AFTER_HSYNC) ? cur_x + 1 : cur_x;
y_updated <= 0;
end
if (Vsync == 0) begin
cur_x <= 0;
cur_y <= 0;
end
end
end
#10 begin
for (i = 0; i < HEIGHT; i = i + 1)
for (j = 0; j < WIDTH; j = j + 1) begin
if(((i-HEIGHT/2)*(i-HEIGHT/2) + (j-WIDTH/2)*(j-WIDTH/2) <= 100*100) &&
(screen[i][j][0] != 15 || screen[i][j][1] != 15 || screen[i][j][2] != 15))
begin
incorrect_1 = incorrect_1 + 1;
end
if(((i-HEIGHT/2)*(i-HEIGHT/2) + (j-WIDTH/2)*(j-WIDTH/2) > 100*100) &&
(screen[i][j][0] != 0 || screen[i][j][1] != 0 || screen[i][j][2] != 0))
begin
incorrect_2 = incorrect_2 + 1;
end
end
// Sorry, I don't have much time for writing test case
pass[0] = (incorrect_1 + incorrect_2) < 960;
end
$display("Test 1(VGA Signal & Output): ");
$display("%s", pass[0] ? "Pass" : "Failed");
$display("%d %d", incorrect_1, incorrect_2);
#1 begin
$display("End of Test\n");
$finish;
end
end
endmodule
| 6.846651 |
module tester_ctrl #(
parameter ADDR_WIDTH = 24
) (
input clk,
input rst_n,
output rd_enable_o,
output wr_enable_o,
input busy_i,
input rd_ready_i,
input [ 15:0] rd_data_i,
output [ 15:0] wr_data_o,
output reg [ADDR_WIDTH-1:0] addr_o,
output [7:0] leds_o
);
localparam INIT = 4'b0000,
WR = 4'b0001,
WR_WAIT = 4'b0010,
WR_INC = 4'b1000,
RD = 4'b0100,
RD_WAIT = 4'b0101,
VAL = 4'b0110,
RD_INC = 4'b1001,
PASS = 4'b0011,
FAIL = 4'b0111;
wire [15:0] checksum;
reg [15:0] rd_data_r;
wire rd_valid;
/* Counter to wait until sdram init cycle is complete. */
reg [ 5:0] init_cnt;
reg [ 3:0] next;
reg [ 3:0] state;
checksum checksum0 (
{{32 - ADDR_WIDTH{1'b0}}, addr_o},
checksum
);
always @(posedge clk)
if (~rst_n) rd_data_r <= 16'd0;
else if (rd_ready_i) rd_data_r <= rd_data_i;
assign rd_valid = (checksum == rd_data_r);
assign wr_enable_o = (state == WR);
assign rd_enable_o = (state == RD);
assign wr_data_o = checksum;
assign leds_o = addr_o[ADDR_WIDTH-1:ADDR_WIDTH-8];
assign init_wait = |init_cnt;
always @(posedge clk)
if (~rst_n) init_cnt <= 6'b11_1111;
else if (init_wait) init_cnt <= init_cnt - 1'b1;
/* Handle Address INC and LED out */
/* rd_flag is for carry over to signify writes are done */
always @(posedge clk)
if (~rst_n) addr_o <= 0;
else if (state[3]) /* RD_INC || WR_INC */
addr_o <= addr_o + 1'b1;
/* Validator state machine */
always @(*) begin
next = state;
case (state)
INIT: if (~init_wait) next = WR;
WR: if (busy_i) next = WR_WAIT;
WR_WAIT: if (~busy_i) next = WR_INC;
WR_INC:
if (&addr_o) /* Address has overflowed go to RD */
next = RD;
else next = WR;
RD: if (busy_i) next = RD_WAIT;
RD_WAIT: if (rd_ready_i) next = VAL;
VAL:
if (~rd_valid) next = FAIL;
else next = RD_INC;
RD_INC:
if (&addr_o) /* Address has overflowed again done */
next = PASS;
else next = RD;
default: next = state;
endcase
end
always @(posedge clk)
if (~rst_n) state <= INIT;
else state <= next;
endmodule
| 6.93984 |
module tester_gmii #(
parameter NUM_OF_HSR_NODE = 4
, HSR_ID = 0
, TX_ENABLE = 0
) (
input wire reset
, output reg gmii_gtxc = 1'b1
, output reg [ 7:0] gmii_txd = 8'h0
, output reg gmii_txen = 1'b0
, output reg gmii_txer = 1'b0
, input wire gmii_rxc
, input wire [ 7:0] gmii_rxd
, input wire gmii_rxdv
, input wire gmii_rxer
//-----------------------------------------------------------
, input wire [47:0] mac_addr
, output reg done = 1'b0 // successfully done
);
//---------------------------------------------------------------------------
localparam CLK125_FREQ = 125_000_000;
localparam CLK125_PERIOD_HALF = 1_000_000_000 / (CLK125_FREQ * 2);
//---------------------------------------------------------------------------
always #CLK125_PERIOD_HALF gmii_gtxc <= ~gmii_gtxc;
//---------------------------------------------------------------------------
`include "task_eth_ip_tcp_udp.v"
//---------------------------------------------------------------------------
reg preamble = 1'b0; // prepend 8-byte preamble when 1
reg crc = 1'b0; // append 4-byte crc when 1
reg broadcast;
reg vlan = 1'b0;
reg [ 47:0] dst_mac = 48'h0;
reg [ 47:0] src_mac = 48'h0;
reg [ 15:0] eth_type = 16'h0;
reg [0:2048*8-1] payload = {2048 * 8{1'b1}};
reg [ 15:0] bnum_payload = 16'h0; // pure ethernet payload
reg [0:2048*8-1] packet = {2048 * 8{1'b0}};
reg [ 15:0] bnum_packet = 16'h0; // from dst-mac to end of payload
//---------------------------------------------------------------------------
integer idx;
//---------------------------------------------------------------------------
initial begin
repeat (5) @(posedge gmii_gtxc);
wait (reset == 1'b1);
src_mac = mac_addr;
wait (reset == 1'b0);
wait (u_fpga.hsr_ready == 1'b1);
repeat (50) @(posedge gmii_gtxc);
if (TX_ENABLE) begin
if (`TEST_TARGET) begin
dst_mac[47:8] = mac_addr[47:8];
dst_mac[7:0] = (HSR_ID + 1) % NUM_OF_HSR_NODE;
broadcast = 1'b0; //broadcast=1'b1;
vlan = 1'b0;
eth_type = 46;
bnum_payload = 46; // 46
preamble = 1'b1; // prepend 8-byte preamble when 1
crc = 1'b1; // append 4-byte crc when 1
for (idx = 0; idx < bnum_payload; idx = idx + 1) begin
payload[8*idx+:8] = idx + 1;
end
build_ethernet_packet(preamble, crc, broadcast, vlan, dst_mac, src_mac, eth_type, payload
, bnum_payload, packet, bnum_packet);
send_ethernet_packet(packet, bnum_packet, 1 // ifg
);
//send_ethernet_packet(
// packet
// , bnum_packet
// , 1 // ifg
//);
//send_ethernet_packet(
// packet
// , bnum_packet
// , 1 // ifg
//);
//send_ethernet_packet(
// packet
// , bnum_packet
// , 1 // ifg
//);
//send_ethernet_packet(
// packet
// , bnum_packet
// , 1 // ifg
//);
//send_ethernet_packet(
// packet
// , bnum_packet
// , 1 // ifg
//);
repeat (bnum_packet * 4) @(posedge gmii_gtxc);
end
end //if (TX_ENABLE) begin
done <= 1'b1;
end
//---------------------------------------------------------------------------
endmodule
| 6.700421 |
module tester_gtx_chk #(
parameter IDLE = 16'h02bc
) (
input [15:0] rx_data,
input [ 1:0] rx_char,
input usrclk,
input usrrst_n,
output err_flag, //data error flag
output [15:0] der //data error rate
);
reg [15:0] rx_data_r;
reg data_err_flag;
reg [15:0] data_err_rate;
reg [15:0] err_cnt;
reg [15:0] cnt_10000;
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
rx_data_r <= 16'b0;
end else begin
if (rx_char == 2'b0) begin
rx_data_r <= rx_data;
end
end
end
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
data_err_flag <= 1'b0;
end else begin
//receive data check
if (rx_char == 2'b00 && rx_data == rx_data_r + 1'b1) begin
data_err_flag <= 1'b0;
end //K character (IDLE) check
else if (rx_char == 2'b01 && rx_data == IDLE) begin
data_err_flag <= 1'b0;
end else begin
data_err_flag <= 1'b1;
end
end
end
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
cnt_10000 <= 16'd0;
end else begin
if (cnt_10000 == 16'd9_999 && rx_char == 1'b0) begin
cnt_10000 <= 16'd0;
end else if (rx_char == 1'b0) begin
cnt_10000 <= cnt_10000 + 1'b1;
end
end
end
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
err_cnt <= 16'b0;
end else begin
if (cnt_10000 == 16'd9_999 && rx_char == 1'b0) begin
err_cnt <= 16'b0;
end //count error number
else if (data_err_flag == 1'b1) begin
err_cnt <= err_cnt + 1'b1;
end
end
end
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
data_err_rate <= 16'b0;
end else begin
//number of error per 10000 data
if (cnt_10000 == 16'd9_999 && rx_char == 1'b0) begin
data_err_rate <= err_cnt;
end
end
end
assign err_flag = data_err_flag;
assign der = data_err_rate;
endmodule
| 7.275511 |
module tester_gtx_gen #(
parameter IDLE = 16'h02bc
) (
input usrclk,
input usrrst_n,
input [7:0] test_len_ctrl, // interval length of each set of data
input test_run_ctrl, // control signal to generate data
output [15:0] txdata, // generate data for gtx
output [ 1:0] txchar // control signal of data for gtx
);
reg [15:0] gtx_data;
reg [ 1:0] gtx_datk;
reg [ 8:0] test_cnt;
reg [15:0] data_cnt;
reg data_flag;
//period of data transmission
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
test_cnt <= 9'd0;
end else begin
if ((test_cnt == test_len_ctrl + 8'd32) && (test_run_ctrl == 1'b1)) begin
test_cnt <= 9'd0;
end else begin
test_cnt <= test_cnt + 1'b1;
end
end
end
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
data_flag <= 1'b0;
end else begin
if ((test_cnt == test_len_ctrl + 8'd32) && (test_run_ctrl == 1'b1)) begin
data_flag <= 1'b1;
end else if (test_cnt == 8'd31) begin
data_flag <= 1'b0;
end
end
end
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
data_cnt <= 16'd0;
end else begin
if (data_flag) begin
data_cnt <= data_cnt + 1'b1;
end
end
end
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
gtx_data <= 16'd0;
end else begin
//transmit incremental data
if (data_flag) begin
gtx_data <= data_cnt;
end //transmit K character
else begin
gtx_data <= IDLE;
end
end
end
always @(posedge usrclk or negedge usrrst_n) begin
if (~usrrst_n) begin
gtx_datk <= 2'b0;
end else begin
if (data_flag) begin
gtx_datk <= 2'b0;
end else begin
gtx_datk <= 2'b01;
end
end
end
assign txdata = gtx_data;
assign txchar = gtx_datk;
endmodule
| 8.496655 |
module tester_pulse_gen;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/******************************************************************
* Parameters for the test bench
******************************************************************/
initial $display("Testbench for unit 'pulse_gen'");
/******************************************************************
* Unit under test, and signals
******************************************************************/
reg clock;
reg reset;
reg toggle;
wire pulse;
pulse_gen uut (
.clk (clock),
.rst (reset),
.toggle(toggle),
.pulse (pulse)
);
/******************************************************************
* USER Defined output
******************************************************************/
task display_signals;
$display("%d\t%b\t%d\t%d\t%d", $time, reset, uut.q, toggle, pulse);
endtask // display_signals
task display_header;
$display("\t\ttime\trst\tq\td\tpulse");
endtask
/******************************************************************
* ALL the User TESTS defined here:
******************************************************************/
task init;
begin
clock = 0;
reset = 0;
toggle = 1'b0;
end
endtask // init
task test_1;
begin
$display("TEST mux on the write address/word");
`wait_N_cycles_n(clock, 5);
toggle <= 1'b1;
`wait_N_cycles_n(clock, 5);
toggle <= 1'b0;
`wait_N_cycles_n(clock, 5);
toggle <= 1'b1;
`wait_N_cycles_n(clock, 5);
toggle <= 1'b0;
`wait_N_cycles_n(clock, 15);
//`wait_1_cycle_n(clock);
//`wait_N_cycles_n(clock,5);
end
endtask
task test_2;
begin
$display("OTHER TESTS");
end
endtask
task test_3;
begin
end
endtask
task test_4;
begin
end
endtask
task test_5;
begin
end
endtask
task test_6;
begin
end
endtask
task test_7;
begin
end
endtask
task test_8;
begin
end
endtask
task test_9;
begin
end
endtask
task test_10;
begin
end
endtask
endmodule
| 7.414258 |
module tester_pulse_sync;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/******************************************************************
* Parameters for the test bench
******************************************************************/
initial $display("Testbench for unit 'pulse_sync'");
/******************************************************************
* Unit under test, and signals
******************************************************************/
reg clock;
reg reset;
reg i_pulse;
wire o_pulse;
pulse_sync uut (
.o_clk (clock),
.rst (reset),
.i_pulse(i_pulse),
.o_pulse(o_pulse)
);
/******************************************************************
* USER Defined output
******************************************************************/
task display_signals;
$display("%d\t%b\t%d\t%d\t%d", $time, reset, uut.q, i_pulse, o_pulse);
endtask // display_signals
task display_header;
$display("\t\ttime\trst\tq\td\tpulse");
endtask
/******************************************************************
* ALL the User TESTS defined here:
******************************************************************/
task init;
begin
clock = 0;
reset = 0;
i_pulse = 1'b0;
end
endtask // init
task test_1;
begin
$display("TEST mux on the write address/word");
`wait_N_cycles_n(clock, 5);
i_pulse <= 1'b1;
`wait_N_cycles_n(clock, 5);
i_pulse <= 1'b0;
`wait_N_cycles_n(clock, 15);
//`wait_1_cycle_n(clock);
//`wait_N_cycles_n(clock,5);
end
endtask
task test_2;
begin
$display("OTHER TESTS");
end
endtask
task test_3;
begin
end
endtask
task test_4;
begin
end
endtask
task test_5;
begin
end
endtask
task test_6;
begin
end
endtask
task test_7;
begin
end
endtask
task test_8;
begin
end
endtask
task test_9;
begin
end
endtask
task test_10;
begin
end
endtask
endmodule
| 7.414258 |
module tester_reset_sync;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/******************************************************************
* Parameters for the test bench
******************************************************************/
initial $display("Testbench for unit 'reset_sync'");
/******************************************************************
* Unit under test, and signals
******************************************************************/
reg clock;
reg reset;
wire sinced_rst;
reset_sync uut (
.clk (clock),
.arst(reset),
.rst (sinced_rst)
);
/******************************************************************
* USER Defined output
******************************************************************/
task display_signals;
$display("%d\t%b\t%b", $time, reset, sinced_rst);
endtask // display_signals
task display_header;
$display("\t\ttime\tarst\trst");
endtask
/******************************************************************
* ALL the User TESTS defined here:
******************************************************************/
task init;
begin
clock = 0;
reset = 0;
end
endtask // init
task test_1;
begin
$display("TEST. Useless");
`wait_N_cycles_n(clock, 5);
end
endtask
task test_2;
begin
$display("OTHER TESTS");
end
endtask
task test_3;
begin
end
endtask
task test_4;
begin
end
endtask
task test_5;
begin
end
endtask
task test_6;
begin
end
endtask
task test_7;
begin
end
endtask
task test_8;
begin
end
endtask
task test_9;
begin
end
endtask
task test_10;
begin
end
endtask
endmodule
| 8.020631 |
module tester_signal_sync;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/******************************************************************
* Parameters for the test bench
******************************************************************/
initial $display("Testbench for unit 'signal_sync'");
/******************************************************************
* Unit under test, and signals
******************************************************************/
reg clock;
reg reset;
reg i_signal;
wire o_signal;
signal_sync uut (
.o_clk (clock),
.rst (reset),
.i_signal(i_signal),
.o_signal(o_signal)
);
/******************************************************************
* USER Defined output
******************************************************************/
task display_signals;
$display("%d\t%b\t%d\t%d\t%d", $time, reset, uut.q, i_signal, o_signal);
endtask // display_signals
task display_header;
$display("\t\ttime\trst\tq\td\tsignal");
endtask
/******************************************************************
* ALL the User TESTS defined here:
******************************************************************/
task init;
begin
clock = 0;
reset = 0;
i_signal = 1'b0;
end
endtask // init
task test_1;
begin
$display("TEST mux on the write address/word");
`wait_N_cycles_n(clock, 5);
i_signal <= 1'b1;
`wait_N_cycles_n(clock, 5);
i_signal <= 1'b0;
`wait_N_cycles_n(clock, 15);
//`wait_1_cycle_n(clock);
//`wait_N_cycles_n(clock,5);
end
endtask
task test_2;
begin
$display("OTHER TESTS");
end
endtask
task test_3;
begin
end
endtask
task test_4;
begin
end
endtask
task test_5;
begin
end
endtask
task test_6;
begin
end
endtask
task test_7;
begin
end
endtask
task test_8;
begin
end
endtask
task test_9;
begin
end
endtask
task test_10;
begin
end
endtask
endmodule
| 8.001525 |
module tester_toggle_gen;
/******************************************************************
* This file declares a couple of redundant functions
******************************************************************/
`include "tester_skeleton.v"
/******************************************************************
* Parameters for the test bench
******************************************************************/
initial $display("Testbench for unit 'toggle_gen'");
/******************************************************************
* Unit under test, and signals
******************************************************************/
reg clock;
reg reset;
wire toggle;
reg pulse;
toggle_gen uut (
.clk (clock),
.rst (reset),
.toggle(toggle),
.pulse (pulse)
);
/******************************************************************
* USER Defined output
******************************************************************/
task display_signals;
$display("%d\t%b\t%d\t%d\t%d", $time, reset, uut.q, toggle, pulse);
endtask // display_signals
task display_header;
$display("\t\ttime\trst\tq\ttoggle\tpulse");
endtask
/******************************************************************
* ALL the User TESTS defined here:
******************************************************************/
task init;
begin
clock <= 0;
reset <= 0;
pulse <= 1'b0;
end
endtask // init
task test_1;
begin
$display("TEST mux on the write address/word");
`wait_N_cycles_n(clock, 5);
pulse <= 1'b1;
`wait_1_cycle_n(clock);
pulse <= 1'b0;
`wait_N_cycles_n(clock, 5);
pulse <= 1'b1;
`wait_1_cycle_n(clock);
pulse <= 1'b0;
`wait_N_cycles_n(clock, 5);
pulse <= 1'b1;
`wait_1_cycle_n(clock);
pulse <= 1'b0;
`wait_N_cycles_n(clock, 5);
end
endtask
task test_2;
begin
$display("OTHER TESTS");
//`wait_1_cycle_n(clock);
//`wait_N_cycles_n(clock,5);
end
endtask
task test_3;
begin
end
endtask
task test_4;
begin
end
endtask
task test_5;
begin
end
endtask
task test_6;
begin
end
endtask
task test_7;
begin
end
endtask
task test_8;
begin
end
endtask
task test_9;
begin
end
endtask
task test_10;
begin
end
endtask
endmodule
| 8.039183 |
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