code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module terminal_demo (
input clk,
reset_n,
// Receiver port
input rd_uart, // left push button
output rx_empty, // LED0
input rx,
// Transmitter port
input [7:0] w_data, // SW0 -> SW7
input wr_uart, // right push button
output tx_full, // LED1
output tx,
// Sseg signals
output [6:0] sseg,
output [0:7] AN,
output DP
);
// Push buttons debouncers/synchronizers
button read_uart (
.clk(clk),
.reset_n(reset_n),
.noisy(rd_uart),
.debounced(),
.p_edge(rd_uart_pedge),
.n_edge(),
._edge()
);
button write_uart (
.clk(clk),
.reset_n(reset_n),
.noisy(wr_uart),
.debounced(),
.p_edge(wr_uart_pedge),
.n_edge(),
._edge()
);
// UART Driver
wire [7:0] r_data;
uart #(
.DBIT(8),
.SB_TICK(16)
) uart_driver (
.clk(clk),
.reset_n(reset_n),
.r_data(r_data),
.rd_uart(rd_uart_pedge),
.rx_empty(rx_empty),
.rx(rx),
.w_data(w_data),
.wr_uart(wr_uart_pedge),
.tx_full(tx_full),
.tx(tx),
.TIMER_FINAL_VALUE(11'd650) // baud rate = 9600 bps
);
// Seven-Segment Driver
sseg_driver(
.clk(clk),
.reset_n(reset_n),
.I0({1'b1, w_data[3:0], 1'b0}),
.I1({1'b1, w_data[7:4], 1'b0}),
.I2(6'd0),
.I3(6'd0),
.I4(6'd0),
.I5(6'd0),
.I6({~rx_empty, r_data[3:0], 1'b0}),
.I7({~rx_empty, r_data[7:4], 1'b0}),
.AN(AN),
.sseg(sseg),
.DP(DP)
);
endmodule
| 7.027718 |
module terminal_tb();
reg clk = 1'b0;
reg n_reset = 1'b1;
wire ps2Clk = 1'b1;
wire ps2Data = 1'b1;
reg n_wr = 1'b1;
reg n_rd = 1'b1;
reg regSel = 1'b0;
reg [7:0] dataIn;
wire [7:0] dataOut;
wire videoR0;
wire videoR1;
wire videoG0;
wire videoG1;
wire videoB0;
wire videoB1;
wire hSync;
wire vSync;
integer i;
task send_byte;
input [7:0] byte;
begin
// Select the control/status register
@(posedge clk)
regSel <= 1'b0;
// Loop until the not-busy bit is set
@(posedge clk)
n_rd <= 1'b0;
@(posedge clk)
n_rd <= 1'b1;
while (!dataOut[1]) begin
@(posedge clk)
n_rd <= 1'b0;
@(posedge clk)
n_rd <= 1'b1;
end
// Select the display
@(posedge clk)
regSel <= 1'b1;
dataIn <= byte;
n_wr <= 1'b0;
@(posedge clk)
n_wr <= 1'b1;
@(posedge clk)
dataIn <= 8'hZZ;
end
endtask // for
SBCTextDisplayRGB DUT
(
.n_reset(n_reset),
.clk(clk),
.n_wr(n_wr),
.n_rd(n_rd),
.regSel(regSel),
.dataIn(dataIn),
.dataOut(dataOut),
.n_int(),
.n_rts(),
// RGB video signals
.videoR0(videoR0),
.videoR1(videoR1),
.videoG0(videoG0),
.videoG1(videoG1),
.videoB0(videoB0),
.videoB1(videoB1),
.hSync(hSync),
.vSync(vSync),
// Monochrome video signals
.video(),
.sync(),
// Keyboard signals
.ps2Clk(ps2Clk),
.ps2Data(ps2Data),
// FN keys passed out as general signals (momentary and toggled versions)
.FNkeys(),
.FNtoggledKeys()
);
initial begin
$dumpvars;
#1000
n_reset = 1'b0;
#1000
n_reset = 1'b1;
#1000
send_byte(8'h0c);
send_byte(8'h0a);
send_byte(8'h0d);
for (i = 0; i < 8; i = i + 1) begin
// Bold off: <ESC>[22m
send_byte(8'h1b);
send_byte(8'h5b);
send_byte(8'h32);
send_byte(8'h32);
send_byte(8'h6d);
// Normal color: <ESC>[3<i>m
send_byte(8'h1b);
send_byte(8'h5b);
send_byte(8'h33);
send_byte(8'h30 + i);
send_byte(8'h6d);
// ABCDE
send_byte(8'h41);
send_byte(8'h42);
send_byte(8'h43);
send_byte(8'h44);
send_byte(8'h45);
// <spc><spc><spc>
send_byte(8'h20);
send_byte(8'h20);
send_byte(8'h20);
// Bright color: <ESC>[9<i>m
send_byte(8'h1b);
send_byte(8'h5b);
send_byte(8'h39);
send_byte(8'h30 + i);
send_byte(8'h6d);
// ABCDE
send_byte(8'h41);
send_byte(8'h42);
send_byte(8'h43);
send_byte(8'h44);
send_byte(8'h45);
// <lf><cr>
send_byte(8'h0a);
send_byte(8'h0d);
end
#20000000 ; // 20ms
$finish;
end
always
#10 clk = !clk;
endmodule
| 7.035226 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
wire [7:0] e;
wire [7:0] f;
assign e = a < b ? a : b;
assign f = e < c ? e : c;
assign min = f < d ? f : d;
endmodule
| 7.203305 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
assign min =(a<b)&(a<c)&(a<d)?a:(b<a)&(b<c)&(b<d)?b:(c<b)&(c<a)&(c<d)?c:d;
endmodule
| 7.203305 |
module top_module (
input [7:0] a,
b,
c,
d,
output [7:0] min
); //
wire [7:0] intermediate_result1;
wire [7:0] intermediate_result2;
assign intermediate_result1 = a < b ? a : b;
assign intermediate_result2 = c < d ? c : d;
assign min = intermediate_result1<intermediate_result2? intermediate_result1: intermediate_result2;
endmodule
| 7.203305 |
module ternary_add (
a,
b,
c,
o
);
parameter WIDTH = 8;
parameter SIGN_EXT = 1'b0;
input [WIDTH-1:0] a, b, c;
output [WIDTH+1:0] o;
wire [WIDTH+1:0] o;
generate
if (!SIGN_EXT) assign o = a + b + c;
else
assign o = {a[WIDTH-1],a[WIDTH-1],a} +
{b[WIDTH-1],b[WIDTH-1],b} +
{c[WIDTH-1],c[WIDTH-1],c};
endgenerate
endmodule
| 7.659901 |
module ternary_adder #(
parameter WIDTH = 32
) (
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
input [WIDTH-1:0] c,
output [WIDTH-1:0] o
);
assign o = a + b + c;
endmodule
| 8.491873 |
module ternary_full_adder_1digit (
input Cin,
input [1:0] X,
Y,
output [1:0] S,
output Cout
);
wire Cin_bar;
wire SumX1, SumX2;
wire SumY1, SumY2;
wire xorhS, hS_bar;
wire [1:0] hS;
wire hC;
ternary_half_adder_1digit hadder (
X,
Y,
hS,
hC
);
not (Cin_bar, Cin);
// Sum0
xor (xorhS, hS[0], hS[1]);
not (hS_bar, xorhS);
and (SumX1, hS_bar, Cin);
and (SumX2, hS[0], Cin_bar);
or (S[0], SumX1, SumX2);
// Sum1
and (SumY1, hS[1], Cin_bar);
and (SumY2, hS[0], Cin);
or (S[1], SumY1, SumY2);
// Cout
and (Cout1, hS[1], Cin);
or (Cout, hC, Cout1);
endmodule
| 6.894655 |
module ternary_full_adder_4digit (
input Cin,
input [1:0] X3,
X2,
X1,
X0,
Y3,
Y2,
Y1,
Y0,
output [1:0] S3,
S2,
S1,
S0,
output Cout
);
wire Carry0, Carry1, Carry2;
ternary_full_adder_1digit adder0 (
Cin,
X0,
Y0,
S0,
Carry0
);
ternary_full_adder_1digit adder1 (
Carry0,
X1,
Y1,
S1,
Carry1
);
ternary_full_adder_1digit adder2 (
Carry1,
X2,
Y2,
S2,
Carry2
);
ternary_full_adder_1digit adder3 (
Carry2,
X3,
Y3,
S3,
Cout
);
endmodule
| 6.894655 |
module ternary_consensus(a[1:0], b[1:0], out[1:0]);
input [1:0] a
input [1:0] b;
output [1:0] out;
// TODO: implementation
endmodule
| 6.795484 |
module ternary_operator_mux (
input i0,
input i1,
input sel,
output y
);
assign y = sel ? i1 : i0;
endmodule
| 7.473079 |
module ternary_operator_mux (
i0,
i1,
sel,
y
);
wire _0_;
wire _1_;
wire _2_;
wire _3_;
input i0;
wire i0;
input i1;
wire i1;
input sel;
wire sel;
output y;
wire y;
sky130_fd_sc_hd__mux2_1 _4_ (
.A0(_0_),
.A1(_1_),
.S (_2_),
.X (_3_)
);
assign _0_ = i0;
assign _1_ = i1;
assign _2_ = sel;
assign y = _3_;
endmodule
| 7.473079 |
module
// is not strictly necessary, but makes the
// grouping clear and unambiguous if you
// want to remove the pipeline registers.
module tern_node (clk,a,b,c,o);
parameter WIDTH = 8;
input clk;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input [WIDTH-1:0] c;
output [WIDTH+2-1:0] o;
reg [WIDTH+2-1:0] o;
always @(posedge clk) begin
o <= a+b+c;
end
endmodule
| 8.198795 |
module ternary_tb ();
reg [1:0] a;
wire [1:0] b;
test t (
a,
b
);
initial begin
$monitor("%d %d", a, b);
a = 2'b0;
#50 $stop;
end
always #10 a = a + 1;
endmodule
| 6.984029 |
module tessera_mem_wbif (
res,
clk,
wb_cyc_i,
wb_stb_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_dat_i,
wb_cab_i,
wb_dat_o,
wb_ack_o,
wb_err_o,
write_req,
write_byte,
write_address,
write_data,
write_ack,
read_req,
read_byte,
read_address,
read_data,
read_ack
);
input res;
input clk;
input wb_cyc_i;
input wb_stb_i;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input [31:0] wb_dat_i;
input wb_cab_i;
output [31:0] wb_dat_o;
output wb_ack_o;
output wb_err_o;
output write_req;
output [3:0] write_byte;
output [31:0] write_address;
output [31:0] write_data;
input write_ack;
output read_req;
output [3:0] read_byte;
output [31:0] read_address;
input [31:0] read_data;
input read_ack;
//
//
//
assign wb_err_o = 1'b0;
//
//
//
reg write_ack_z;
reg read_ack_z;
reg wb_ack;
always @(posedge clk or posedge res)
if (res) write_ack_z <= 1'b0;
else write_ack_z <= write_ack;
always @(posedge clk or posedge res)
if (res) read_ack_z <= 1'b0;
else read_ack_z <= read_ack;
always @(posedge clk or posedge res)
if (res) wb_ack <= 1'b0;
//else wb_ack <= (write_ack_z&&!write_ack)||(read_ack_z&&!read_ack); // release negedge ack(late)
else
wb_ack <= (!write_ack_z&&write_ack)||(!read_ack_z&&read_ack); // release posedge ack(fast)
assign wb_ack_o = (wb_cyc_i && wb_stb_i) ? wb_ack : 1'b0;
//
//
//
reg [31:0] wb_dat;
always @(posedge clk or posedge res)
if (res) wb_dat <= {4{8'h00}};
else wb_dat <= read_data;
assign wb_dat_o = (wb_cyc_i && wb_stb_i) ? wb_dat[31:0] : {4{8'h00}};
//
//
//
reg [ 3:0] write_byte;
reg [31:0] write_address;
reg [31:0] write_data;
//
reg [ 3:0] read_byte;
reg [31:0] read_address;
always @(posedge clk or posedge res)
if (res) begin
write_byte <= {4{1'b0}};
write_address <= 32'd0;
write_data <= {4{8'h00}};
//
read_byte <= {4{1'b0}};
read_address <= 32'd0;
end else begin
write_byte <= wb_sel_i;
write_address <= {8'd0, wb_adr_i[23:0]};
write_data <= wb_dat_i;
//
read_byte <= wb_sel_i;
read_address <= {8'd0, wb_adr_i[23:0]};
end
//
//
//
reg write_req;
reg read_req;
always @(posedge clk or posedge res)
if (res) write_req <= 1'b0;
else if (write_ack) write_req <= 1'b0;
else if (wb_cyc_i && wb_stb_i && !wb_ack_o && !write_ack_z && wb_we_i)
write_req <= 1'b1; // wait ack low
always @(posedge clk or posedge res)
if (res) read_req <= 1'b0;
else if (read_ack) read_req <= 1'b0;
else if (wb_cyc_i && wb_stb_i && !wb_ack_o && !read_ack_z && !wb_we_i)
read_req <= 1'b1; // wait ack low
endmodule
| 7.717731 |
module tessera_ram_tiny (
sys_wb_res,
sys_wb_clk,
wb_cyc_i,
wb_stb_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_dat_i,
wb_cab_i,
wb_dat_o,
wb_ack_o,
wb_err_o
);
// system
input sys_wb_res;
input sys_wb_clk;
// WishBone Slave
input wb_cyc_i;
input wb_stb_i;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input [31:0] wb_dat_i;
input wb_cab_i;
output [31:0] wb_dat_o;
output wb_ack_o;
output wb_err_o;
wire active;
wire mask;
wire [9:2] address;
wire [3:0] write;
wire [3:0] read;
wire [31:0] q;
// 0x0000_0000 - 0x0000_0fff 4Kbyte For Exception,so only 16inst(64Byte). phy is 1024Byte
assign active = wb_cyc_i && wb_stb_i;
assign mask = !(wb_adr_i[7:6] == 2'd0);
assign address = {wb_adr_i[11:8], wb_adr_i[5:2]};
assign write = {4{(active && wb_we_i) && !mask}} & wb_sel_i;
assign read = {4{(active && !wb_we_i) && !mask}} & wb_sel_i;
assign wb_err_o = 1'b0;
//
// 1wait(safety)
//
wire clk;
reg ack;
assign clk = sys_wb_clk;
always @(posedge sys_wb_clk or posedge sys_wb_res)
if (sys_wb_res) ack <= 1'b0;
else ack <= active && !ack;
assign wb_ack_o = (active) ? ack : 1'b0;
//
// no-wait(fast and risky,data valid timing is negedge)
//
// wire clk;
// wire ack;
// assign ack = active;
// assign clk = !sys_wb_clk;
// assign wb_ack_o = active;
assign wb_dat_o = {
((read[3] && ack) ? q[31:24] : 8'h00),
((read[2] && ack) ? q[23:16] : 8'h00),
((read[1] && ack) ? q[15:8] : 8'h00),
((read[0] && ack) ? q[7:0] : 8'h00)
};
// sdram_wbif(DOMAIN WinsboneClock)
RAM_256 i3_RAM_INT (
.address(address), //8bit=256byte,all 1024byte
.clock(clk),
.data(wb_dat_i[31:24]),
.wren(write[3]),
.q(q[31:24])
);
RAM_256 i2_RAM_INT (
.address(address),
.clock(clk),
.data(wb_dat_i[23:16]),
.wren(write[2]),
.q(q[23:16])
);
RAM_256 i1_RAM_INT (
.address(address),
.clock(clk),
.data(wb_dat_i[15:8]),
.wren(write[1]),
.q(q[15:8])
);
RAM_256 i0_RAM_INT (
.address(address),
.clock(clk),
.data(wb_dat_i[7:0]),
.wren(write[0]),
.q(q[7:0])
);
endmodule
| 7.372465 |
module tessera_sdram_wbif (
res,
clk,
wb_cyc_i,
wb_stb_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_dat_i,
wb_cab_i,
wb_dat_o,
wb_ack_o,
wb_err_o,
write_req,
write_byte,
write_address,
write_data,
write_ack,
read_req,
read_byte,
read_address,
read_data,
read_ack
);
input res;
input clk;
input wb_cyc_i;
input wb_stb_i;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input [31:0] wb_dat_i;
input wb_cab_i;
output [31:0] wb_dat_o;
output wb_ack_o;
output wb_err_o;
output write_req;
output [3:0] write_byte;
output [31:0] write_address;
output [31:0] write_data;
input write_ack;
output read_req;
output [3:0] read_byte;
output [31:0] read_address;
input [31:0] read_data;
input read_ack;
//
//
//
assign wb_err_o = 1'b0;
//
//
//
reg write_ack_z;
reg read_ack_z;
reg wb_ack;
always @(posedge clk or posedge res)
if (res) write_ack_z <= 1'b0;
else write_ack_z <= write_ack;
always @(posedge clk or posedge res)
if (res) read_ack_z <= 1'b0;
else read_ack_z <= read_ack;
always @(posedge clk or posedge res)
if (res) wb_ack <= 1'b0;
//else wb_ack <= (write_ack_z&&!write_ack)||(read_ack_z&&!read_ack); // release negedge ack(late)
else
wb_ack <= (!write_ack_z&&write_ack)||(!read_ack_z&&read_ack); // release posedge ack(fast)
assign wb_ack_o = (wb_cyc_i && wb_stb_i) ? wb_ack : 1'b0;
//
//
//
reg [31:0] wb_dat;
always @(posedge clk or posedge res)
if (res) wb_dat <= {4{8'h00}};
else wb_dat <= read_data;
assign wb_dat_o = (wb_cyc_i && wb_stb_i) ? wb_dat[31:0] : {4{8'h00}};
//
//
//
reg [ 3:0] write_byte;
reg [31:0] write_address;
reg [31:0] write_data;
//
reg [ 3:0] read_byte;
reg [31:0] read_address;
always @(posedge clk or posedge res)
if (res) begin
write_byte <= {4{1'b0}};
write_address <= 32'd0;
write_data <= {4{8'h00}};
//
read_byte <= {4{1'b0}};
read_address <= 32'd0;
end else begin
write_byte <= wb_sel_i;
write_address <= wb_adr_i; // masking controler,{8'd0,wb_adr_i[23:0]};
write_data <= wb_dat_i;
//
read_byte <= wb_sel_i;
read_address <= wb_adr_i; // masking controler,{8'd0,wb_adr_i[23:0]};
end
//
//
//
reg write_req;
reg read_req;
always @(posedge clk or posedge res)
if (res) write_req <= 1'b0;
else if (write_ack) write_req <= 1'b0;
else if (wb_cyc_i && wb_stb_i && !wb_ack_o && !write_ack_z && wb_we_i)
write_req <= 1'b1; // wait ack low
always @(posedge clk or posedge res)
if (res) read_req <= 1'b0;
else if (read_ack) read_req <= 1'b0;
else if (wb_cyc_i && wb_stb_i && !wb_ack_o && !read_ack_z && !wb_we_i)
read_req <= 1'b1; // wait ack low
endmodule
| 8.006947 |
module tessera_tic (
wb_rst,
wb_clk,
wb_cyc_o,
wb_adr_o,
wb_dat_i,
wb_dat_o,
wb_sel_o,
wb_ack_i,
wb_err_i,
wb_rty_i,
wb_we_o,
wb_stb_o,
wb_cab_o
);
input wb_rst;
input wb_clk;
output wb_cyc_o;
output [31:0] wb_adr_o;
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
output [3:0] wb_sel_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
output wb_we_o;
output wb_stb_o;
output wb_cab_o;
`ifdef SIM
reg r_wb_cyc_o;
reg [31:0] r_wb_adr_o;
reg [31:0] r_wb_dat_o;
reg [31:0] r_wb_sel_o;
reg r_wb_we_o;
reg r_wb_stb_o;
reg r_wb_cab_o;
initial begin
r_wb_cyc_o = 1'b0;
r_wb_adr_o = 32'h0000_0000;
r_wb_dat_o = 32'h0000_0000;
r_wb_sel_o = 4'b0000;
r_wb_we_o = 1'b0;
r_wb_stb_o = 1'b0;
r_wb_cab_o = 1'b0;
end
`define MISC_OFFSET 1
assign #(`MISC_OFFSET) wb_cyc_o = r_wb_cyc_o;
assign #(`MISC_OFFSET) wb_adr_o = r_wb_adr_o;
assign #(`MISC_OFFSET) wb_dat_o = r_wb_dat_o;
assign #(`MISC_OFFSET) wb_sel_o = r_wb_sel_o;
assign #(`MISC_OFFSET) wb_we_o = r_wb_we_o;
assign #(`MISC_OFFSET) wb_stb_o = r_wb_stb_o;
assign #(`MISC_OFFSET) wb_cab_o = r_wb_cab_o;
task task_wr_ext;
input cab;
input [31:0] adr;
input [3:0] sel;
input [31:0] data;
begin
begin
r_wb_cyc_o <= 1'b1;
r_wb_adr_o <= adr;
r_wb_dat_o <= data;
r_wb_sel_o <= sel;
r_wb_we_o <= 1'b1;
r_wb_stb_o <= 1'b1;
r_wb_cab_o <= cab;
end
begin : label_detect_wr_ext_ack
forever @(posedge wb_clk) if (wb_ack_i == 1'b1) disable label_detect_wr_ext_ack;
end
begin
r_wb_cyc_o <= 1'b0;
r_wb_adr_o <= adr;
r_wb_dat_o <= data;
r_wb_sel_o <= sel;
r_wb_we_o <= 1'b0;
r_wb_stb_o <= 1'b0;
r_wb_cab_o <= 1'b0;
end
@(posedge wb_clk);
end
endtask
task task_rd_ext;
input cab;
input [31:0] adr;
input [3:0] sel;
input [31:0] data;
begin
begin
r_wb_cyc_o <= 1'b1;
r_wb_adr_o <= adr;
r_wb_dat_o <= data;
r_wb_sel_o <= sel;
r_wb_we_o <= 1'b0;
r_wb_stb_o <= 1'b1;
r_wb_cab_o <= cab;
end
begin : label_detect_rd_ext_ack
forever @(posedge wb_clk) if (wb_ack_i == 1'b1) disable label_detect_rd_ext_ack;
end
begin
r_wb_cyc_o <= 1'b0;
r_wb_adr_o <= adr;
r_wb_dat_o <= data;
r_wb_sel_o <= sel;
r_wb_we_o <= 1'b0;
r_wb_stb_o <= 1'b0;
r_wb_cab_o <= 1'b0;
end
@(posedge wb_clk);
end
endtask
`else
assign wb_cyc_o = 1'b0;
assign wb_adr_o = 32'h0000_0000;
assign wb_dat_o = 32'h0000_0000;
assign wb_sel_o = 4'b0000;
assign wb_we_o = 1'b0;
assign wb_stb_o = 1'b0;
assign wb_cab_o = 1'b0;
`endif
endmodule
| 7.178832 |
module tessera_vga_wbif (
res,
clk,
wb_cyc_i,
wb_stb_i,
wb_adr_i,
wb_sel_i,
wb_we_i,
wb_dat_i,
wb_cab_i,
wb_dat_o,
wb_ack_o,
wb_err_o,
enable,
base
);
input res;
input clk;
input wb_cyc_i;
input wb_stb_i;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input [31:0] wb_dat_i;
input wb_cab_i;
output [31:0] wb_dat_o;
output wb_ack_o;
output wb_err_o;
output enable;
output [23:11] base;
reg [31:0] reg1; // bit0 scan_enable
reg [31:0] reg0; // bit23-11 base_address on VRAM
assign wb_err_o = 1'b0;
wire active;
wire write;
wire read;
assign active = wb_cyc_i && wb_stb_i;
assign write = active && wb_we_i;
assign read = active && !wb_we_i;
// write
always @(posedge clk or posedge res)
if (res) begin
reg0 <= 32'h0000_0000;
reg1 <= 32'h0000_0000;
end else if (write) begin
if (wb_adr_i[2] == 1'd1) begin
if (wb_sel_i[3]) reg1[31:24] <= wb_dat_i[31:24];
if (wb_sel_i[2]) reg1[23:16] <= wb_dat_i[23:16];
if (wb_sel_i[1]) reg1[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[0]) reg1[7:0] <= wb_dat_i[7:0];
end else if (wb_adr_i[2] == 1'd0) begin
if (wb_sel_i[3]) reg0[31:24] <= wb_dat_i[31:24];
if (wb_sel_i[2]) reg0[23:16] <= wb_dat_i[23:16];
if (wb_sel_i[1]) reg0[15:8] <= wb_dat_i[15:8];
if (wb_sel_i[0]) reg0[7:0] <= wb_dat_i[7:0];
end
end
// read
assign wb_dat_o = (read) ? (
(wb_adr_i[2]==1'd0) ? reg0:
(wb_adr_i[2]==1'd1) ? reg1:
32'h0000_0000
): 32'h0000_0000;
// ack
assign wb_ack_o = active;
// reg
assign enable = reg1[0];
assign base = reg0[23:11];
endmodule
| 7.32781 |
module test_jbimu;
// Inputs
reg clks;
reg clock;
reg reset;
reg start;
wire miso;
// Outputs
wire [15:0] roll;
wire [15:0] pitch;
wire [15:0] yaw;
wire [15:0] roll_rate;
wire [15:0] pitch_rate;
wire [15:0] yaw_rate;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire done;
wire mosi;
wire sck;
wire ss;
// Instantiate the Unit Under Test (UUT)
jb_imu uut (
.clock(clock),
.reset(reset),
.start(start),
.roll(roll),
.pitch(pitch),
92
.yaw(yaw),
.roll_rate(roll_rate),
.pitch_rate(pitch_rate),
.yaw_rate(yaw_rate),
.accel_x(accel_x),
.accel_y(accel_y),
.accel_z(accel_z),
.done(done),
.miso(miso),
.mosi(mosi),
.sck(sck),
.ss(ss)
);
wire slave_done;
reg [7:0] din;
wire [7:0] slave_dout;
spi_slave slave(
.clk(clks),
.rst(reset),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sck(sck),
.done(slave_done),
.din(din),
.dout(slave_dout)
);
always #10 clock = ~clock; //50Mhz = 20 ns period
always #20 clks = ~clks; //25 Mhz slave clock
always @(slave_done) begin
if(slave_done) begin
din = din + 1'b1;
end
end
initial begin
// Initialize Inputs
clock = 0;
clks=0;
reset = 0;
start = 0;
din = 0;
// Wait 100 ns for global reset to finish
93
reset = 1;
#100;
reset = 0;
// Add stimulus here
din = 8'h00;
#20;
start = 1;
#20;
start = 0;
#10000;
end
endmodule
| 6.632599 |
module test_accumulation_cap (
input clk,
input reset, // async
output [`NUM_BITS-1:0] out
);
// clk_count for the current phase. 31 bits is faster than 24 bits. weird. ??? 36MHz v 32MHz
reg [31:0] clk_count = 0;
// destructure
reg [4-1:0] azmux;
reg [4-1:0] himux;
reg [4-1:0] himux2;
reg sig_pc_sw_ctl;
reg led0;
reg [8-1: 0] monitor;// = { MON7, MON6, MON5,MON4, MON3, MON2, MON1, MON0 } ;
// nice.
assign {monitor, led0, sig_pc_sw_ctl, himux2, himux, azmux} = out;
/* perhaps create some macros for MUX_1OF8_S1.
// not sure. can represent 8|(4-1) for s4. etc.
// most code is not going to care. there will just be a register for the zero, and a register for the signal.
*/
// Can move to reset. but might as well set in the block.
// assign sig_pc_sw_ctl = clk_count;
// it would actually be nice to have control over the led here. we need a mode state variable.
// and the interupt. actually.
// sampling the charge - is a bit difficult. because this is a kind of input modulation...
/*
- actually this functionality - *can* be incorporated into regular AZ switching and measurement.
the gnd and the off signal. are just the normal 2 mode AZ.
- But not charge-injection testing. actually maybe even charge injection.
*/
// always @(posedge clk or posedge reset )
always @(posedge clk or posedge reset)
if (reset) begin
clk_count <= 0;
end else begin
clk_count <= clk_count + 1; // positive clk
// we can trigger on these if we want
case (clk_count)
0: begin
// off
monitor <= 0;
azmux <= 0;
sig_pc_sw_ctl <= 0;
// muxes
himux <= 4'b1001; // s2 select himux2. for leakage test this should be off.
himux2 <= 4'b1011; // select ground to clear charge on cap. s4 - A400-5 gnd. / 8|(4-1).
led0 <= 0;
end
`CLK_FREQ * 1: begin
himux2 <= 4'b1000; // s1 select dcv-source-hi. actually for real. actually we would turn off to test leakage.
// need to be high-z mode to measure. or measure from op-amp.
led0 <= 1;
end
`CLK_FREQ * 2: clk_count <= 0;
endcase
end
endmodule
| 7.187903 |
module ac97 (
ready,
command_address,
command_data,
command_valid,
left_data,
left_valid,
right_data,
right_valid,
left_in_data,
right_in_data,
ac97_sdata_out,
ac97_sdata_in,
ac97_synch,
ac97_bit_clock
);
output ready;
input [7:0] command_address;
input [15:0] command_data;
input command_valid;
input [19:0] left_data, right_data;
input left_valid, right_valid;
output [19:0] left_in_data, right_in_data;
input ac97_sdata_in;
input ac97_bit_clock;
output ac97_sdata_out;
output ac97_synch;
reg ready;
reg ac97_sdata_out;
reg ac97_synch;
reg [7:0] bit_count;
reg [19:0] l_cmd_addr;
reg [19:0] l_cmd_data;
reg [19:0] l_left_data, l_right_data;
reg l_cmd_v, l_left_v, l_right_v;
reg [19:0] left_in_data, right_in_data;
initial begin
ready <= 1'b0;
// synthesis attribute init of ready is "0";
ac97_sdata_out <= 1'b0;
// synthesis attribute init of ac97_sdata_out is "0";
ac97_synch <= 1'b0;
// synthesis attribute init of ac97_synch is "0";
bit_count <= 8'h00;
// synthesis attribute init of bit_count is "0000";
l_cmd_v <= 1'b0;
// synthesis attribute init of l_cmd_v is "0";
l_left_v <= 1'b0;
// synthesis attribute init of l_left_v is "0";
l_right_v <= 1'b0;
// synthesis attribute init of l_right_v is "0";
left_in_data <= 20'h00000;
// synthesis attribute init of left_in_data is "00000";
right_in_data <= 20'h00000;
// synthesis attribute init of right_in_data is "00000";
end
always @(posedge ac97_bit_clock) begin
// Generate the sync signal
if (bit_count == 255) ac97_synch <= 1'b1;
if (bit_count == 15) ac97_synch <= 1'b0;
// Generate the ready signal
if (bit_count == 128) ready <= 1'b1;
if (bit_count == 2) ready <= 1'b0;
// Latch user data at the end of each frame. This ensures that the
// first frame after reset will be empty.
if (bit_count == 255) begin
l_cmd_addr <= {command_address, 12'h000};
l_cmd_data <= {command_data, 4'h0};
l_cmd_v <= command_valid;
l_left_data <= left_data;
l_left_v <= left_valid;
l_right_data <= right_data;
l_right_v <= right_valid;
end
if ((bit_count >= 0) && (bit_count <= 15))
// Slot 0: Tags
case (bit_count[3:0])
4'h0: ac97_sdata_out <= 1'b1; // Frame valid
4'h1: ac97_sdata_out <= l_cmd_v; // Command address valid
4'h2: ac97_sdata_out <= l_cmd_v; // Command data valid
4'h3: ac97_sdata_out <= l_left_v; // Left data valid
4'h4: ac97_sdata_out <= l_right_v; // Right data valid
default: ac97_sdata_out <= 1'b0;
endcase
else if ((bit_count >= 16) && (bit_count <= 35))
// Slot 1: Command address (8-bits, left justified)
ac97_sdata_out <= l_cmd_v ? l_cmd_addr[35-bit_count] : 1'b0;
else if ((bit_count >= 36) && (bit_count <= 55))
// Slot 2: Command data (16-bits, left justified)
ac97_sdata_out <= l_cmd_v ? l_cmd_data[55-bit_count] : 1'b0;
else if ((bit_count >= 56) && (bit_count <= 75)) begin
// Slot 3: Left channel
ac97_sdata_out <= l_left_v ? l_left_data[19] : 1'b0;
l_left_data <= {l_left_data[18:0], l_left_data[19]};
end else if ((bit_count >= 76) && (bit_count <= 95))
// Slot 4: Right channel
ac97_sdata_out <= l_right_v ? l_right_data[95-bit_count] : 1'b0;
else ac97_sdata_out <= 1'b0;
bit_count <= bit_count + 1;
end // always @ (posedge ac97_bit_clock)
always @(negedge ac97_bit_clock) begin
if ((bit_count >= 57) && (bit_count <= 76))
// Slot 3: Left channel
left_in_data <= {
left_in_data[18:0], ac97_sdata_in
};
else if ((bit_count >= 77) && (bit_count <= 96))
// Slot 4: Right channel
right_in_data <= {
right_in_data[18:0], ac97_sdata_in
};
end
endmodule
| 7.075457 |
module squarewave (
clock,
ready,
pcm_data
);
input clock;
input ready;
output [19:0] pcm_data;
reg old_ready;
reg [6:0] index;
reg [19:0] pcm_data;
initial begin
old_ready <= 1'b0;
// synthesis attribute init of old_ready is "0";
index <= 7'h00;
// synthesis attribute init of index is "00";
pcm_data <= 20'h00000;
// synthesis attribute init of pcm_data is "00000";
end
always @(posedge clock) begin
if (ready && ~old_ready) index <= index + 1;
old_ready <= ready;
end
always @(index) begin
if (index[6]) pcm_data <= 20'hF0F00;
else pcm_data <= 20'h05555;
end // always @ (index)
endmodule
| 6.583527 |
module abro (
input clk,
input reset,
input a,
input b,
output z
);
parameter IDLE = 0, SA = 1, SB = 2, SAB = 3;
reg [1:0] cur_state, next_state;
// Output z depends only on the state SAB
// The output z is high when cur_state is SAB
// cur_state is reset to IDLE when reset is high. Otherwise, it takes value of next_state.
// Next state generation logic:
// If cur_state is IDLE and a and b are both high, state changes to SAB
// If cur_state is IDLE, and a is high, state changes to SA
// If cur_state is IDLE, and b is high, state changes to SB
// If cur_state is SA, and b is high, state changes to SAB
// If cur_state is SB, and a is high, state changes to SAB
// If cur_state is SAB, state changes to IDLE
// Implements an FSM in Verilog
always @(posedge clk or posedge reset) begin
if (reset) cur_state <= IDLE;
else cur_state <= next_state;
end
always @(cur_state or a or b) begin
case (cur_state)
IDLE: begin
if (a && b) next_state = SAB;
else if (a) next_state = SA;
else if (b) next_state = SB;
end
SA: begin
if (b) next_state = SAB;
else next_state = SA;
end
SB: begin
if (a) next_state = SAB;
else next_state = SB;
end
SAB: begin
next_state = IDLE;
end
default: next_state = IDLE;
endcase
end
// Output logic:
// Output z is high when cur_state is SAB
assign z = (cur_state == SAB);
endmodule
| 7.130853 |
module fft_audio (
clock_27mhz,
reset,
volume,
audio_in_data,
audio_out_data,
ready,
audio_reset_b,
ac97_sdata_out,
ac97_sdata_in,
ac97_synch,
ac97_bit_clock
);
input clock_27mhz;
input reset;
input [4:0] volume;
output [15:0] audio_in_data;
input [15:0] audio_out_data;
output ready;
//ac97 interface signals
output audio_reset_b;
output ac97_sdata_out;
input ac97_sdata_in;
output ac97_synch;
input ac97_bit_clock;
wire [2:0] source;
assign source = 0; //mic
wire [7:0] command_address;
wire [15:0] command_data;
wire command_valid;
wire [19:0] left_in_data, right_in_data;
wire [19:0] left_out_data, right_out_data;
reg audio_reset_b;
reg [9:0] reset_count;
//wait a little before enabling the AC97 codec
always @(posedge clock_27mhz) begin
if (reset) begin
audio_reset_b = 1'b0;
reset_count = 0;
end else if (reset_count == 1023) audio_reset_b = 1'b1;
else reset_count = reset_count + 1;
end
wire ac97_ready;
ac97 ac97 (
ac97_ready,
command_address,
command_data,
command_valid,
left_out_data,
1'b1,
right_out_data,
1'b1,
left_in_data,
right_in_data,
ac97_sdata_out,
ac97_sdata_in,
ac97_synch,
ac97_bit_clock
);
// generate two pulses synchronous with the clock: first capture, then ready
reg [2:0] ready_sync;
always @(posedge clock_27mhz) begin
ready_sync <= {ready_sync[1:0], ac97_ready};
end
assign ready = ready_sync[1] & ~ready_sync[2];
reg [15:0] out_data;
always @(posedge clock_27mhz) if (ready) out_data <= audio_out_data;
assign audio_in_data = left_in_data[19:4];
assign left_out_data = {out_data, 4'b0000};
assign right_out_data = left_out_data;
// generate repeating sequence of read/writes to AC97 registers
ac97commands cmds (
clock_27mhz,
ready,
command_address,
command_data,
command_valid,
volume,
source
);
endmodule
| 6.829235 |
module tone750hz (
clock,
ready,
pcm_data
);
input clock;
input ready;
output [19:0] pcm_data;
reg [ 8:0] index;
reg [19:0] pcm_data;
initial begin
// synthesis attribute init of old_ready is "0";
index <= 8'h00;
// synthesis attribute init of index is "00";
pcm_data <= 20'h00000;
// synthesis attribute init of pcm_data is "00000";
end
always @(posedge clock) begin
if (ready) index <= index + 1;
end
// one cycle of a sinewave in 64 20-bit samples
always @(index) begin
case (index[5:0])
6'h00: pcm_data <= 20'h00000;
6'h01: pcm_data <= 20'h0C8BD;
6'h02: pcm_data <= 20'h18F8B;
6'h03: pcm_data <= 20'h25280;
6'h04: pcm_data <= 20'h30FBC;
6'h05: pcm_data <= 20'h3C56B;
6'h06: pcm_data <= 20'h471CE;
6'h07: pcm_data <= 20'h5133C;
6'h08: pcm_data <= 20'h5A827;
6'h09: pcm_data <= 20'h62F20;
6'h0A: pcm_data <= 20'h6A6D9;
6'h0B: pcm_data <= 20'h70E2C;
6'h0C: pcm_data <= 20'h7641A;
6'h0D: pcm_data <= 20'h7A7D0;
6'h0E: pcm_data <= 20'h7D8A5;
6'h0F: pcm_data <= 20'h7F623;
6'h10: pcm_data <= 20'h7FFFF;
6'h11: pcm_data <= 20'h7F623;
6'h12: pcm_data <= 20'h7D8A5;
6'h13: pcm_data <= 20'h7A7D0;
6'h14: pcm_data <= 20'h7641A;
6'h15: pcm_data <= 20'h70E2C;
6'h16: pcm_data <= 20'h6A6D9;
6'h17: pcm_data <= 20'h62F20;
6'h18: pcm_data <= 20'h5A827;
6'h19: pcm_data <= 20'h5133C;
6'h1A: pcm_data <= 20'h471CE;
6'h1B: pcm_data <= 20'h3C56B;
6'h1C: pcm_data <= 20'h30FBC;
6'h1D: pcm_data <= 20'h25280;
6'h1E: pcm_data <= 20'h18F8B;
6'h1F: pcm_data <= 20'h0C8BD;
6'h20: pcm_data <= 20'h00000;
6'h21: pcm_data <= 20'hF3743;
6'h22: pcm_data <= 20'hE7075;
6'h23: pcm_data <= 20'hDAD80;
6'h24: pcm_data <= 20'hCF044;
6'h25: pcm_data <= 20'hC3A95;
6'h26: pcm_data <= 20'hB8E32;
6'h27: pcm_data <= 20'hAECC4;
6'h28: pcm_data <= 20'hA57D9;
6'h29: pcm_data <= 20'h9D0E0;
6'h2A: pcm_data <= 20'h95927;
6'h2B: pcm_data <= 20'h8F1D4;
6'h2C: pcm_data <= 20'h89BE6;
6'h2D: pcm_data <= 20'h85830;
6'h2E: pcm_data <= 20'h8275B;
6'h2F: pcm_data <= 20'h809DD;
6'h30: pcm_data <= 20'h80000;
6'h31: pcm_data <= 20'h809DD;
6'h32: pcm_data <= 20'h8275B;
6'h33: pcm_data <= 20'h85830;
6'h34: pcm_data <= 20'h89BE6;
6'h35: pcm_data <= 20'h8F1D4;
6'h36: pcm_data <= 20'h95927;
6'h37: pcm_data <= 20'h9D0E0;
6'h38: pcm_data <= 20'hA57D9;
6'h39: pcm_data <= 20'hAECC4;
6'h3A: pcm_data <= 20'hB8E32;
6'h3B: pcm_data <= 20'hC3A95;
6'h3C: pcm_data <= 20'hCF044;
6'h3D: pcm_data <= 20'hDAD80;
6'h3E: pcm_data <= 20'hE7075;
6'h3F: pcm_data <= 20'hF3743;
endcase // case(index[5:0])
end // always @ (index)
endmodule
| 6.600003 |
module xvga (
vclock,
hcount,
vcount,
hsync,
vsync,
blank
);
input vclock;
output [10:0] hcount;
output [9:0] vcount;
output vsync;
output hsync;
output blank;
reg hsync, vsync, hblank, vblank, blank;
reg [10:0] hcount; // pixel number on current line
reg [ 9:0] vcount; // line number
// horizontal: 1344 pixels total
// display 1024 pixels per line
wire hsyncon, hsyncoff, hreset, hblankon;
assign hblankon = (hcount == 1023);
assign hsyncon = (hcount == 1047);
assign hsyncoff = (hcount == 1183);
assign hreset = (hcount == 1343);
// vertical: 806 lines total
// display 768 lines
wire vsyncon, vsyncoff, vreset, vblankon;
assign vblankon = hreset & (vcount == 767);
assign vsyncon = hreset & (vcount == 776);
assign vsyncoff = hreset & (vcount == 782);
assign vreset = hreset & (vcount == 805);
// sync and blanking
wire next_hblank, next_vblank;
assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank;
assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank;
always @(posedge vclock) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low
blank <= next_vblank | (next_hblank & ~hreset);
end
endmodule
| 6.964566 |
module process_audio (
clock_27mhz,
reset,
sel,
ready,
from_ac97_data,
haddr,
hdata,
hwe
);
input clock_27mhz;
input reset;
input [3:0] sel;
input ready;
input [15:0] from_ac97_data;
output [9:0] haddr, hdata;
output hwe;
wire signed [22:0] xk_re, xk_im;
wire [13:0] xk_index;
// IP Core Gen -> Digital Signal Processing -> Transforms -> FFTs
// -> Fast Fourier Transform v3.2
// Transform length: 16384
// Implementation options: Pipelined, Streaming I/O
// Transform length options: none
// Input data width: 8
// Phase factor width: 8
// Optional pins: CE
// Scaling options: Unscaled
// Rounding mode: Truncation
// Number of stages using Block Ram: 7
// Output ordering: Bit/Digit Reversed Order
fft16384u fft (
.clk(clock_27mhz),
.ce(reset | ready),
.xn_re(from_ac97_data[15:8]),
.xn_im(8'b0),
.start(1'b1),
.fwd_inv(1'b1),
.fwd_inv_we(reset),
.xk_re(xk_re),
.xk_im(xk_im),
.xk_index(xk_index)
);
wire signed [9:0] xk_re_scaled = xk_re >> sel;
wire signed [9:0] xk_im_scaled = xk_im >> sel;
// process fft data
reg [2:0] state;
reg [9:0] haddr;
reg [19:0] rere, imim;
reg [19:0] mag2;
reg hwe;
wire sqrt_done;
always @(posedge clock_27mhz) begin
hwe <= 0;
if (reset) begin
state <= 0;
end else
case (state)
3'h0: if (ready) state <= 1;
3'h1: begin
// only process data with index < 1024
state <= (xk_index[13:10] == 0) ? 2 : 0;
haddr <= xk_index[9:0];
rere <= xk_re_scaled * xk_re_scaled;
imim <= xk_im_scaled * xk_im_scaled;
end
3'h2: begin
state <= 3;
mag2 <= rere + imim;
end
3'h3:
if (sqrt_done) begin
state <= 0;
hwe <= 1;
end
endcase
end
wire [9:0] mag;
sqrt sqmag (
clock_27mhz,
mag2,
state == 2,
mag,
sqrt_done
);
defparam sqmag.NBITS = 20;
assign hdata = mag;
endmodule
| 6.74906 |
module test_keyboard;
reg clk;
reg reset;
reg ps2_clk;
reg ps2_data;
wire [15:0] scancode;
wire strobe;
keyboard keyboard(.clk(clk),
.reset(reset),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.data(scancode),
.strobe(strobe));
task clockout;
input bit;
begin
ps2_data = bit;
ps2_clk = 0;
repeat (100) @(posedge clk);
ps2_clk = 1;
repeat (100) @(posedge clk);
end
endtask
task sendscan;
input [7:0] scan;
begin
@(posedge clk);
clockout(0);
clockout(scan[0]);
clockout(scan[1]);
clockout(scan[2]);
clockout(scan[3]);
clockout(scan[4]);
clockout(scan[5]);
clockout(scan[6]);
clockout(scan[7]);
clockout(0);
clockout(1);
repeat (10000) @(posedge clk);
end
endtask
task pause;
begin
repeat(5000) @(posedge clk);
$display("----");
end
endtask
task sender;
begin
$display("begin test");
#200 begin
reset = 0;
end
#100000;
// press "a"
sendscan(8'h1c);
sendscan(8'hf0);
sendscan(8'h1c);
pause;
// press "b"
sendscan(8'h32);
sendscan(8'hf0);
sendscan(8'h32);
pause;
// enter
sendscan(8'h5a);
sendscan(8'hf0);
sendscan(8'h5a);
pause;
// shift "a"
sendscan(8'h12);
sendscan(8'h1c);
sendscan(8'hf0);
sendscan(8'h1c);
sendscan(8'hf0);
sendscan(8'h12);
pause;
// press "c"
sendscan(8'h21);
sendscan(8'hf0);
sendscan(8'h21);
pause;
// ctrl "a"
sendscan(8'h14);
sendscan(8'h1c);
sendscan(8'hf0);
sendscan(8'h1c);
sendscan(8'hf0);
sendscan(8'h14);
pause;
// press "d"
sendscan(8'h23);
sendscan(8'hf0);
sendscan(8'h23);
pause;
// press "end"
sendscan(8'he0);
sendscan(8'h69);
sendscan(8'he0);
sendscan(8'hf0);
sendscan(8'h69);
pause;
// press "escape"
sendscan(8'h76);
sendscan(8'hf0);
sendscan(8'h76);
pause;
$display("end test");
#5000 $finish;
end
endtask
task monitor;
begin
$display("monitor start");
while (1)
begin
@(posedge clk);
if (strobe)
begin
$display("out: 0x%x %o; ", scancode, scancode);
end
end
$display("monitor end");
end
endtask
initial
begin
$timeformat(-9, 0, "ns", 7);
$dumpfile("test-keyboard.vcd");
$dumpvars(0, test_keyboard);
end
initial
begin
clk = 0;
reset = 1;
ps2_clk = 1;
ps2_data = 1;
fork
monitor;
sender;
join;
end
always
begin
#40 clk = 0;
#40 clk = 1;
end
endmodule
| 6.531392 |
module tests ();
supply0 gnd;
supply1 vdd;
reg gate;
wire out;
mosfet_npn u0 (
.vdd (vdd),
.gate(gate),
.out (out)
);
initial begin
gate <= 0;
$monitor("NMOS, NPN -> gate: %0b, out: %0b (vdd: %0b)", gate, out, vdd);
#10 gate <= 1;
end
endmodule
| 7.016684 |
module tests ();
supply0 gnd;
supply1 vdd;
reg gate;
wire out;
mosfet_pnp u0 (
.vdd (vdd),
.gate(gate),
.out (out)
);
initial begin
gate <= 0;
$monitor("PMOS, PNP -> gate: %0b, out: %0b (vdd: %0b)", gate, out, vdd);
#10 gate <= 1;
end
endmodule
| 7.016684 |
module unit_x (
input [31:0] a,
b,
c,
output [31:0] x
);
assign x = (a & b) | c;
endmodule
| 7.77978 |
module unit_y (
input [31:0] a,
b,
c,
output [31:0] y
);
assign y = a & (b | c);
endmodule
| 8.058142 |
module Test1 (
input clock,
input reset,
input io_vec_set,
input [ 1:0] io_vec_idx,
input [15:0] io_vec_ary_0,
input [15:0] io_vec_ary_1,
input [15:0] io_vec_ary_2,
input [15:0] io_vec_ary_3,
output [15:0] io_vec_ary_out
);
wire [15:0] _GEN_1 = 2'h1 == io_vec_idx ? io_vec_ary_1 : io_vec_ary_0; // @[Test1.scala 35:20 Test1.scala 35:20]
wire [15:0] _GEN_2 = 2'h2 == io_vec_idx ? io_vec_ary_2 : _GEN_1; // @[Test1.scala 35:20 Test1.scala 35:20]
wire [15:0] _GEN_3 = 2'h3 == io_vec_idx ? io_vec_ary_3 : _GEN_2; // @[Test1.scala 35:20 Test1.scala 35:20]
assign io_vec_ary_out = io_vec_set ? _GEN_3 : 16'h0; // @[Test1.scala 33:21 Test1.scala 35:20 Test1.scala 38:20]
endmodule
| 6.682188 |
module Test13BitOut (
input [31:0] PCOut,
input [31:0] BranchTargetAddr,
input [31:0] PCIn,
input [31:0] rs1Read,
input [31:0] rs2Read,
input [31:0] regFileIn,
input [31:0] imm,
input [31:0] shiftLeftOut,
input [31:0] ALU2ndSrc,
input [31:0] ALUOut,
input [31:0] memoryOut,
input [3:0] ssdSel,
output reg [12:0] out
);
always @(*) begin
case (ssdSel)
4'b0000: out = PCOut;
4'b0001: out = (PCOut + 3'b100); //PC +4
4'b0010: out = BranchTargetAddr;
4'b0011: out = PCIn;
4'b0100: out = rs1Read;
4'b0101: out = rs2Read;
4'b0110: out = regFileIn;
4'b0111: out = imm;
4'b1000: out = shiftLeftOut;
4'b1001: out = ALU2ndSrc;
4'b1010: out = ALUOut;
4'b1011: out = memoryOut;
default: out = 13'b0;
endcase
end
endmodule
| 9.051347 |
module BCD_Decoder (
input [3:0] A,
//output reg [9:0] Y_L
output [9:0] Y_L
);
/* always @ (*)
case(A)
4'd0:Y_L=10'b11_1111_1110;
4'd1:Y_L=10'b11_1111_1101;
4'd2:Y_L=10'b11_1111_1011;
4'd3:Y_L=10'b11_1111_0111;
4'd4:Y_L=10'b11_1110_1111;
4'd5:Y_L=10'b11_1101_1111;
4'd6:Y_L=10'b11_1011_1111;
4'd7:Y_L=10'b11_0111_1111;
4'd8:Y_L=10'b10_1111_1111;
4'd9:Y_L=10'b01_1111_1111;
default:Y_L=10'b11_1111_1111;
endcase */
assign Y_L[0] = ~(~A[3] & ~A[2] & ~A[1] & ~A[0]);
assign Y_L[1] = ~(~A[3] & ~A[2] & ~A[1] & A[0]);
assign Y_L[2] = ~(~A[3] & ~A[2] & A[1] & ~A[0]);
assign Y_L[3] = ~(~A[3] & ~A[2] & A[1] & A[0]);
assign Y_L[4] = ~(~A[3] & A[2] & ~A[1] & ~A[0]);
assign Y_L[5] = ~(~A[3] & A[2] & ~A[1] & A[0]);
assign Y_L[6] = ~(~A[3] & A[2] & A[1] & ~A[0]);
assign Y_L[7] = ~(~A[3] & A[2] & A[1] & A[0]);
assign Y_L[8] = ~(A[3] & ~A[2] & ~A[1] & ~A[0]);
assign Y_L[9] = ~(A[3] & ~A[2] & ~A[1] & A[0]);
endmodule
| 6.675526 |
module test19 (
input [ 7:0] i_a,
input [ 7:0] i_b,
output [15:0] o_y
);
assign o_y = i_a * i_b;
endmodule
| 7.249686 |
module test19 (
input signed [ 7:0] i_a,
input signed [ 7:0] i_b,
output signed [14:0] o_y
);
assign o_y = i_a * i_b;
endmodule
| 7.249686 |
module test19 (
input signed [ 7:0] i_a,
input [ 7:0] i_b,
output signed [15:0] o_y
);
/* wire signed [8:0] b_r;
assign b_r = {1'b0,i_b}; */
// assign o_y = i_a * b_r;
assign o_y = i_a * $signed({1'b0, i_b});
endmodule
| 7.249686 |
module bus_top #(
parameter N = 2
) (
input [8:0] inp[N-1:0],
output status,
output [7:0] out,
input rst
);
reg status;
wire [7:0] value = 1, cur, p = 8'b00000000;
assign value = 8'b11111111;
genvar i;
generate
for (i = 0; i < N; i = i + 1) begin
if (inp[i][8] == 1) begin
assign cur = inp[i][7:0];
assign value = value & cur;
assign p = (value < cur) ? cur : p;
end
end
endgenerate
endmodule
| 6.904175 |
module test1_mips32;
reg clk1,clk2;
integer k;
pipe_MIPS32 mips(clk1,clk2);
initial
begin
clk1=0;clk1=0;
repeat(20)
begin
#5clk1=1 ; #5clk1=0; //2 phase clock
#5clk2=1 ; #5clk2=0;
end
end
initial
begin
for(k=0;k<=31;k=k+1)
mips.Reg[k]=k; //Load register file from values 0 to 31 for register R0 to R31 respectively.
mips.Mem[0]=32'h2801000A;
mips.Mem[1]=32'h28020014;
mips.Mem[2]=32'h28030019;
mips.Mem[3]=32'h0CE77800; //OR R7,R7,R7 --dummy instruction
mips.Mem[4]=32'h0CE77800; //OR R7,R7,R7 --dummy instruction
mips.Mem[5]=32'h00222000;
mips.Mem[6]=32'h0CE77800; //OR R7,R7,R7 --dummy instruction
mips.Mem[7]=32'h00832800;
mips.Mem[8]=32'hFC000000;
mips.HALTED=0;
mips.TAKEN_BRANCH=0;
mips.PC=0;
#280;
for(k=0;k<6;k=k+1)
$display("R%1d - %2d",k , mips.Reg[k]); //Print value of registers
end
initial
begin
$dumpfile("mips32_1.vcd");
$dumpvars(0,test1_mips32);
#300 $finish;
end
endmodule
| 6.656412 |
module test1_showpic (
input CLK100MHZ,
input SW0, //display_ena
input SW1, //movement_ena
input BTNU, //reset
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
output VGA_HS,
output VGA_VS
);
wire [10:0] h_cnt;
wire [9:0] v_cnt;
wire inplace;
wire vga_clk;
vga vga_ctrl (
CLK100MHZ,
BTNU,
vga_clk,
VGA_HS,
VGA_VS,
h_cnt,
v_cnt,
inplace
);
test_img_control imgctrl (
vga_clk,
h_cnt,
v_cnt,
VGA_VS,
inplace,
SW0,
SW1,
VGA_R,
VGA_G,
VGA_B
);
endmodule
| 7.26657 |
module Test2 (
input clock,
input reset,
input [4:0] io_in_val,
output [3:0] io_out_head,
output [2:0] io_out_extractS,
output [2:0] io_out_extractI,
output [2:0] io_out_extractE
);
assign io_out_head = io_in_val[4:1]; // @[Test2.scala 38:32]
assign io_out_extractS = io_in_val[3:1]; // @[Test2.scala 41:31]
assign io_out_extractI = io_in_val[3:1]; // @[Test2.scala 44:18]
assign io_out_extractE = io_in_val[3:1]; // @[Test2.scala 48:18]
endmodule
| 7.268316 |
module addroundkey (
state,
state_out,
key
);
input wire [127:0] key;
input wire [127:0] state;
output [127:0] state_out;
assign state_out = key ^ state;
endmodule
| 8.744472 |
module test20 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q);
generate
reg [width-1:0] int [depth-1:0];
genvar w, d;
for (d = 0; d < depth; d=d+1) begin
for (w = 0; w < width; w=w+1) begin
initial int[d][w] <= ~((d+w) % 2);
if (d == 0) begin
always @(negedge clk) if (e) int[d][w] <= i[w];
end
else begin
always @(negedge clk) if (e) int[d][w] <= int[d-1][w];
end
end
end
assign z = int[depth-1];
endgenerate
endmodule
| 6.99028 |
module test21 (
input signed [3:0] a,
b,
c,
output reg [3:0] max
);
always @(*) begin
if (a >= b && a >= c) max = a;
else if (b >= a && b >= c) max = b;
else if (c >= b && c >= a) max = c;
else max = max;
end
endmodule
| 6.682703 |
module DFF (
input clk,
input rst_n,
input i_D,
output reg o_Q,
output o_Qn
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
o_Q <= 1'b1;
end else begin
o_Q <= i_D;
end
end
assign o_Qn = ~o_Q;
endmodule
| 7.464833 |
module test21a #(parameter width=130, depth=4) (input clk, input [width-1:0] i, output q);
genvar d;
wire [depth:0] int;
assign int[0] = ^i[width-1:0];
generate
for (d = 0; d < depth; d=d+1) begin
\$_DFFE_PP_ r(.C(clk), .D(int[d]), .E(1'b1), .Q(int[d+1]));
end
endgenerate
assign q = int[depth];
endmodule
| 6.916088 |
module test21b #(parameter width=130, depth=4) (input clk, input [width-1:0] i, input e, output q);
reg [depth-1:0] int;
genvar d;
for (d = 0; d < depth; d=d+1)
initial int[d] <= ~(d % 2);
if (depth == 1) begin
always @(negedge clk) if (e) int <= ~^i[width-1:0];
assign q = int;
end
else begin
always @(negedge clk) if (e) int <= { int[depth-2:0], ~^i[width-1:0] };
assign q = int[depth-1];
end
endmodule
| 6.899926 |
module latch_ff (
input clk,
input enable,
input data,
input clr,
output latch_q,
output ff_q
);
LDCE #(
.INIT(1'b0) // Initial value of latch (1'b0 or 1'b1)
) LDCE_inst (
.Q (latch_q), // Data output
.CLR(clr), // Asynchronous clear/reset input
.D (data), // Data input
.G (clk), // Gate input
.GE (enable) // Gate enable input
);
FDCE #(
.INIT (1'b0), // Initial value of register, 1'b0, 1'b1
// Programmable Inversion Attributes: Specifies the use of the built-in programmable inversion
.IS_CLR_INVERTED(1'b0), // Optional inversion for CLR
.IS_C_INVERTED (1'b0), // Optional inversion for C
.IS_D_INVERTED (1'b0) // Optional inversion for D
) FDCE_inst (
.Q (ff_q), // 1-bit output: Data
.C (clk), // 1-bit input: Clock
.CE (enable), // 1-bit input: Clock enable
.CLR(clr), // 1-bit input: Asynchronous clear
.D (data) // 1-bit input: Data
);
endmodule
| 6.981437 |
module test29 (
input clk,
rst_n,
data,
output reg flag_101
);
parameter ST0 = 4'b0001, ST1 = 4'b0010, ST2 = 4'b0100, ST3 = 4'b1000;
reg [3:0] c_st;
reg [3:0] n_st;
//FSM-1
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
c_st <= ST0;
end else begin
c_st <= n_st;
end
end
//FSM-2
always @(*) begin
case (c_st)
ST0: n_st = data ? ST1 : ST0;
ST1: n_st = data ? ST1 : ST2;
ST2: n_st = data ? ST3 : ST0;
ST3: n_st = data ? ST1 : ST2;
default: n_st = ST0;
endcase
end
//FSM-3
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
flag_101 <= 1'b0;
end else begin
case (n_st)
ST3: flag_101 <= 1'b1;
ST0, ST1, ST2: flag_101 <= 1'b0;
default: flag_101 <= 1'b0;
endcase
end
end
endmodule
| 7.886915 |
module Test2GuitarHero (
KEY,
LEDR,
CLOCK_50,
SW
);
input [3:0] KEY;
input CLOCK_50;
input [12:0] SW;
output [7:0] LEDR;
//PLACEBO FOR DATASELECTION COUNTER
wire [3:0] empty_data;
assign empty_data = 4'b0000;
//DEFAULT FOR NEVER ON WIRE
wire never_write;
assign never_write = 1'b0;
//EASE OF ACCESS WIRING
wire RESET_GAME;
assign RESET_GAME = SW[12];
//NEED TO CHANGE THE GAME CLOCK SPEED/GO MANUAL? CLICK HERE!
wire CLOCK_LINE;
assign CLOCK_LINE = KEY[0];
/*RAM DATA TRACK #1, PRELOADED FROM .mif*/
wire [3:0] track1_out;
ram32x4_track1 track1 (
.address(5'b00000),
.clock(CLOCK_50),
.data(empty_data),
.wren(never_write),
.q(track1_out)
);
/***** 4bit counter that keeps track of when the next memory load should be *****/
wire shouldLoad;
wire [1:0] counter;
counter_4bit(
.INPUTCLOCK(CLOCK_LINE), .reset_n(RESET_GAME), .counter(counter), .shouldLoad(shouldLoad)
);
wire [3:0] loadShiftOut;
shifterbit loadShift3 (
.OUT(loadShiftOut[3]),
.IN(never_write),
.LOAD(track1_out[3]),
.SHIFT(CLOCK_LINE),
.LOAD_N(shouldLoad),
.CLK(CLOCK_LINE),
.RESET_N(RESET_GAME)
);
shifterbit loadShift2 (
.OUT(loadShiftOut[2]),
.IN(loadShiftOut[3]),
.LOAD(track1_out[2]),
.SHIFT(CLOCK_LINE),
.LOAD_N(shouldLoad),
.CLK(CLOCK_LINE),
.RESET_N(RESET_GAME)
);
shifterbit loadShift1 (
.OUT(loadShiftOut[1]),
.IN(loadShiftOut[2]),
.LOAD(track1_out[1]),
.SHIFT(CLOCK_LINE),
.LOAD_N(shouldLoad),
.CLK(CLOCK_LINE),
.RESET_N(RESET_GAME)
);
shifterbit loadShift0 (
.OUT(loadShiftOut[0]),
.IN(loadShiftOut[1]),
.LOAD(track1_out[0]),
.SHIFT(CLOCK_LINE),
.LOAD_N(shouldLoad),
.CLK(CLOCK_LINE),
.RESET_N(RESET_GAME)
);
assign LEDR[7:4] = loadShiftOut;
endmodule
| 7.636753 |
module keyexpansion (
keyInput,
keyNum,
keyOutput
);
input [127:0] keyInput;
input [3:0] keyNum;
output reg [127:0] keyOutput;
wire [31:0] stp1, stp2, Rcon;
wire [3:0] num;
rcon uut1 (
.r(num),
.rcon(Rcon)
);
subbyte uut2 (
.sbox_in (stp1),
.sbox_out(stp2)
);
assign stp1 = {keyInput[23:0], keyInput[31:24]};
assign num = keyNum + 4'd1;
always @(*) begin
keyOutput[127:96] = keyInput[127:96] ^ stp2 ^ Rcon;
keyOutput[95:64] = keyInput[95:64] ^ keyOutput[127:96];
keyOutput[63:32] = keyInput[63:32] ^ keyOutput[95:64];
keyOutput[31:0] = keyInput[31:0] ^ keyOutput[63:32];
end
endmodule
| 7.303995 |
module t1 (N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15);
input N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11;
output N12,N13,N14,N15;
N16 = NAND(N1, N2)
N19 = NOR(N3, N16)
N21 = NAND(N4, N5)
N23 = NOR(N6, N7)
N26 = NAND(N7, N9)
N25 = NOR(N3, N8)
N18 = NAND(N19, N17)
N17 = NOR(N16, N21)
N22 = NOR(N21, N25)
N20 = NAND(N19, N22)
N12 = NOR(N18, N20)
N27 = NOR(N10, N11)
N24 = NAND(N23, N27)
N13 = NOR(N22, N24)
N28 = NAND(N25, N26)
N29 = NAND(N22, N28)
N14 = NAND(N29, N11)
N15 = NAND(N26, N27)
endmodule
| 7.526928 |
module test2port (
address_a,
address_b,
clock,
q_a,
q_b);
input [15:0] address_a;
input [15:0] address_b;
input clock;
output [9:0] q_a;
output [9:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0 = 10'h0;
wire sub_wire1 = 1'h0;
wire [9:0] sub_wire2;
wire [9:0] sub_wire3;
wire [9:0] q_a = sub_wire2[9:0];
wire [9:0] q_b = sub_wire3[9:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (sub_wire0),
.data_b (sub_wire0),
.wren_a (sub_wire1),
.wren_b (sub_wire1),
.q_a (sub_wire2),
.q_b (sub_wire3)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clock1 (),
.clocken0 (),
.clocken1 (),
.clocken2 (),
.clocken3 (),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1)
// synopsys translate_on
);
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.init_file = "./picture/meow2_290x160_convert.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 46400,
altsyncram_component.numwords_b = 46400,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M9K",
altsyncram_component.widthad_a = 16,
altsyncram_component.widthad_b = 16,
altsyncram_component.width_a = 10,
altsyncram_component.width_b = 10,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
| 6.511903 |
module rcon (
input [3:0] r,
output reg [31:0] rcon
);
always @(*) begin
case (r)
4'h1: rcon = 32'h01000000;
4'h2: rcon = 32'h02000000;
4'h3: rcon = 32'h04000000;
4'h4: rcon = 32'h08000000;
4'h5: rcon = 32'h10000000;
4'h6: rcon = 32'h20000000;
4'h7: rcon = 32'h40000000;
4'h8: rcon = 32'h80000000;
4'h9: rcon = 32'h1b000000;
4'ha: rcon = 32'h36000000;
default: rcon = 32'h00000000;
endcase
end
endmodule
| 6.802543 |
module test2_mips32;
reg clk1,clk2;
integer k;
pipe_MIPS32 mips(clk1,clk2);
initial
begin
clk1=0;clk1=0;
repeat(20)
begin
#5clk1=1 ; #5clk1=0; //2 phase clock
#5clk2=1 ; #5clk2=0;
end
end
initial
begin
for(k=0;k<=31;k=k+1)
mips.Reg[k]=k; //Load register file from values 0 to 31 for register R0 to R31 respectively.
mips.Mem[0]=32'h00222000;
mips.HALTED=0;
mips.TAKEN_BRANCH=0;
mips.PC=0;
#280;
for(k=0;k<6;k=k+1)
$display("R%1d - %2d",k , mips.Reg[k]); //Print value of registers
end
initial
begin
$dumpfile("mips32_2.vcd");
$dumpvars(0,test2_mips32);
#300 $finish;
end
endmodule
| 6.627676 |
module: Test2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Test2_sim;
// Inputs
reg clk;
reg [2:0] a;
reg [2:0] b;
// Outputs
wire [3:0] c;
// Instantiate the Unit Under Test (UUT)
Test2 uut (
.clk(clk),
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
clk = 0;
a = 0;
b = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.587093 |
module Test3 (
input clock,
input reset,
input [11:0] io_inp,
output [15:0] io_out_pad
);
assign io_out_pad = {{4'd0}, io_inp}; // @[Test3.scala 18:27]
endmodule
| 7.002654 |
module Unit_fd (
clk_in,
reset,
clk_out
); // Time Frequency Divider
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `UnitTime) begin
count <= 0;
clk_out <= ~clk_out;
end else begin
count = count + 1; //Is the notation between count and count+1 '=' or '<='?
end
end
end
endmodule
| 7.014406 |
module fd (
clk_in,
reset,
clk_out
); // Time Frequency Divider
input clk_in, reset;
output reg clk_out;
reg [31:0] count;
always @(posedge clk_in) begin
if (!reset) begin
count <= 32'd0;
clk_out <= 1'b0;
end else begin
if (count == `Time) begin
count <= 0;
clk_out <= ~clk_out;
end else begin
count = count + 1; //Is the notation between count and count+1 '=' or '<='?
end
end
end
endmodule
| 7.187406 |
module test30 (
input clk,
input rst_n,
input sel_x,
input [ 7:0] da_x,
input [ 7:0] da_y,
input [ 7:0] db_x,
input [ 7:0] db_y,
output reg [15:0] dout_x_y
);
wire [ 7:0] da;
wire [ 7:0] db;
wire [15:0] dout;
assign da = sel_x ? da_x : da_y;
assign db = sel_x ? db_y : db_x;
assign dout = da * db;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
dout_x_y <= 16'd0;
end else begin
dout_x_y <= dout;
end
end
endmodule
| 6.971441 |
module test32 #(
parameter WD = 4'd8, //数据位宽
parameter DP = 5'd16, //深度
parameter ADDR_WD = clogb2(DP) //地址位宽
) (
input i_en ,
input [ADDR_WD-1:0] i_addr ,
output [WD-1:0] o_data
);
reg [WD-1:0] buffer[DP-1:0];
integer i;
initial begin
for (i = 0; i < DP; i = i + 1) begin
buffer[i] <= i + 8'hA0;
end
end
assign o_data = i_en ? buffer[i_addr] : 'hz;
function integer clogb2(input integer depth);
begin
for (clogb2 = 0; depth > 1; clogb2 = clogb2 + 1) depth = depth >> 1;
end
endfunction
endmodule
| 7.2946 |
module spram #(
parameter WD = 8, //数据位宽
parameter AD = 4 //地址位宽
) (
input clk,
input cs_n,
input w_r_n,
input [AD-1:0] addr,
input [WD-1:0] din,
output reg [WD-1:0] dout
);
localparam DP = 1 << AD;
reg [WD-1:0] buffer[DP-1:0];
always @(posedge clk) begin
casex ({
cs_n, w_r_n
})
2'b1x: dout <= 'hx;
2'b01: buffer[addr] <= din;
2'b00: dout <= buffer[addr];
default: ;
endcase
end
endmodule
| 8.813407 |
module single_port_ram (
input [7:0] data,
input [5:0] addr,
input we,
clk,
output [7:0] q
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Variable to hold the registered read address
reg [5:0] addr_reg;
always @(posedge clk) begin
// Write
if (we) ram[addr] <= data;
addr_reg <= addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];
endmodule
| 8.023817 |
module sy_dpram #(
parameter WD = 8, //位宽
parameter DP = 16, //深度
parameter AD = clogb2(DP)
) (
input clk,
input cs_n,
input wr_n,
input rd_n,
input [WD-1:0] din_b, //B口写入
input [AD-1:0] addr_b,
input [AD-1:0] addr_a, //A口读出
output reg [WD-1:0] dout_a
);
reg [WD-1:0] buffer[DP-1:0];
/* always @(posedge clk) begin
if (!cs_n && !rd_n) begin
dout_a <= buffer[addr_a];
end
end
always @(posedge clk) begin
if (!cs_n && !wr_n) begin
buffer[addr_b] <= din_b;
end
end */
always @(posedge clk) begin
casex ({
cs_n, wr_n, rd_n
})
3'b1xx: dout_a <= 'hx;
3'b000: begin
dout_a <= buffer[addr_a];
buffer[addr_b] <= din_b;
end
3'b001: buffer[addr_b] <= din_b;
3'b010: dout_a <= buffer[addr_a];
default: ;
endcase
end
function integer clogb2(input integer depth);
begin
for (clogb2 = 0; depth > 1; clogb2 = clogb2 + 1) depth = depth >> 1;
end
endfunction
endmodule
| 7.356674 |
module as_dpram #(
parameter WD = 8, //数据位宽
parameter AD = 4 //地址位宽
) (
input clk_a,
input rda_n,
input [AD-1:0] addr_a,
output reg [WD-1:0] dout_a,
input clk_b,
input wrb_n,
input [WD-1:0] din_b,
input [AD-1:0] addr_b,
input cs_n
);
localparam DP = 1 << AD;
reg [WD-1:0] buffer[DP-1:0];
/* always @(posedge clk_a) begin
if (!cs_n && !rda_n) begin
dout_a <= buffer[addr_a];
end
end */
always @(posedge clk_a) begin
casex ({
cs_n, rda_n
})
2'b1x: dout_a <= 'hx;
2'b00: dout_a <= buffer[addr_a];
default: ;
endcase
end
always @(posedge clk_b) begin
if (!cs_n && !wrb_n) begin
buffer[addr_b] <= din_b;
end
end
endmodule
| 8.282806 |
module sy_ture_dpram #(
parameter WD = 8, //数据位宽
parameter AD = 4 //地址位宽
) (
input clk,
input cs_n,
input aw_r_n,
input [AD-1:0] addr_a,
input [WD-1:0] din_a,
output reg [WD-1:0] dout_a,
input bw_r_n,
input [AD-1:0] addr_b,
input [WD-1:0] din_b,
output reg [WD-1:0] dout_b
);
localparam DP = 2 ** AD;
reg [WD-1:0] buffer[DP-1:0];
always @(posedge clk) begin
casex ({
cs_n, aw_r_n
})
2'b1x: dout_a <= 'hx;
2'b01: buffer[addr_a] <= din_a;
2'b00: dout_a <= buffer[addr_a];
default: ;
endcase
end
always @(posedge clk) begin
casex ({
cs_n, bw_r_n
})
2'b1x: dout_b <= 'hx;
2'b01: buffer[addr_b] <= din_b;
2'b00: dout_b <= buffer[addr_b];
default: ;
endcase
end
/* always @(posedge clk) begin
casex ({cs_n,aw_r_n,bw_r_n})
3'b1xx: begin dout_a <= 'hx; dout_b <= 'hx; end
3'b000: begin dout_a <= buffer[addr_a]; dout_b <= buffer[addr_b]; end //A读B读
3'b001: begin dout_a <= buffer[addr_a]; buffer[addr_b] <= din_b; end //A读B写
3'b010: begin buffer[addr_a] <= din_a; dout_b <= buffer[addr_b]; end //A写B读
3'b011: begin //A写B写
if (addr_a == addr_b) begin
buffer[addr_a] <= din_a;
end else begin
buffer[addr_a] <= din_a;
buffer[addr_b] <= din_b;
end
end
default: ;
endcase
end */
endmodule
| 8.114928 |
module fir
#(
parameter DIN_WIDTH = 8 , //输入数据位宽
FIR_TAP = 4 , //滤波器阶数
COEF_WIDTH = 8 , //系数位宽
DOUT_WIDTH = 8 //输出数据位宽
)
(
input clk ,
input rst_n ,
input load_sw , // load/run switch
input [ DIN_WIDTH-1:0] data_in , //数据
input [COEF_WIDTH-1:0] coff_in , //系数
output [DOUT_WIDTH-1:0] data_out //输出
);
localparam PROD_WIDTH = DIN_WIDTH + COEF_WIDTH, //乘积位宽
ADD_WIDTH = PROD_WIDTH + clogb2(FIR_TAP) ;//乘积和位宽
reg [DIN_WIDTH-1:0] data_in_r;
wire [ADD_WIDTH-1:0] data_out_w;
reg [COEF_WIDTH-1:0] coff [FIR_TAP-1:0]; //系数
wire [PROD_WIDTH-1:0] prod [FIR_TAP-1:0]; //乘积
reg [ADD_WIDTH-1:0] sum [FIR_TAP-1:0]; //乘积和
//----> Load Data or Coefficient
always @(posedge clk or negedge rst_n) begin: LOAD
integer i;
if (!rst_n) begin
for (i = 0; i <= FIR_TAP-1; i = i +1) begin
coff[i] <= 'd0;
end
data_in_r <= 'd0;
end else if(!load_sw) begin //缓存系数
coff[FIR_TAP-1] <= coff_in;
for (i = FIR_TAP-1; i > 0; i = i -1) begin
coff[i-1] <= coff[i];
end
end else begin
data_in_r <= data_in; //缓存数据
end
end
//----> Compute productss
genvar k;
generate
for (k = 0; k < FIR_TAP; k = k + 1) begin
assign prod[k] = data_in_r * coff[k];
end
endgenerate
//----> Compute sum-of-products
always @(posedge clk or negedge rst_n) begin: SOP
integer m;
if (!rst_n) begin
for (m = 0; m < FIR_TAP; m = m + 1) begin
sum[m] <= 'd0;
end
end else begin
sum[FIR_TAP-1] <= prod[FIR_TAP-1];
for (m = FIR_TAP-1; m > 0; m = m - 1) begin
sum[m-1] <= prod[m-1] + sum[m];
end
/* for (m = 0; m < FIR_TAP - 1; m = m + 1) begin
sum[m] <= prod[m] + sum[m+1];
end
sum[FIR_TAP-1] <= prod[FIR_TAP-1]; */
end
end
assign data_out_w = sum[0];
assign data_out = data_out_w[ADD_WIDTH-1:ADD_WIDTH-DOUT_WIDTH];
function integer clogb2 (input integer depth);
begin
for(clogb2=0; depth>1; clogb2=clogb2+1)
depth = depth >> 1;
end
endfunction
endmodule
| 8.024664 |
module TEST43SLAVE (
input clk,
input reset
);
integer tTMT4Main_V_0;
wire [31:0] ktop12;
reg [31:0] KiKiwi_old_pausemode_value;
wire [31:0] ktop10;
integer mpc10;
reg [1:0] xpc10nz;
always @(posedge clk) begin
//Start structure HPR test43.exe
if (reset) begin
KiKiwi_old_pausemode_value <= 32'd0;
tTMT4Main_V_0 <= 32'd0;
xpc10nz <= 2'd0;
end else begin
case (xpc10nz)
0 /*0:US*/: begin
$display("test43 start");
KiKiwi_old_pausemode_value <= 32'd2;
tTMT4Main_V_0 <= 32'd1;
xpc10nz <= 2'd2 /*2:xpc10nz*/;
end
1'd1 /*1:US*/: begin
$display("The value of the integer: %1d", tTMT4Main_V_0);
tTMT4Main_V_0 <= 32'd1001 * tTMT4Main_V_0;
xpc10nz <= 2'd2 /*2:xpc10nz*/;
end
endcase
if ((xpc10nz == 2'd2 /*2:US*/)) xpc10nz <= 1'd1 /*1:xpc10nz*/;
end
//End structure HPR test43.exe
end
// 1 vectors of width 2
// 1 vectors of width 32
// 32 bits in scalar variables
// Total state bits in module = 66 bits.
// 96 continuously assigned (wire/non-state) bits
// Total number of leaf cells = 0
endmodule
| 7.055169 |
module reset_gen (
input clk,
input rst_async_n,
output rst_sync_n
);
reg rst_s1, rst_s2;
always @(posedge clk or negedge rst_async_n)
if (!rst_async_n) begin
rst_s1 <= 1'b0;
rst_s2 <= 1'b0;
end else begin
rst_s1 <= 1'b1;
rst_s2 <= rst_s1;
end
assign rst_sync_n = rst_s2; //rst_sync_n才是我们真正对系统输出的复位信号
endmodule
| 7.242271 |
module cnt_ring (
input clk,
rst_n,
output [3:0] o_cnt
);
reg [3:0] cnt;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cnt <= 4'b0001;
end else begin
cnt <= {cnt[0], cnt[3:1]};
end
end
assign o_cnt = cnt;
endmodule
| 7.462111 |
module debounce #(
parameter DELAY_TIME = 18'h3ffff
) (
input clk,
input rst_n,
input key_in,
output reg key_vld
);
localparam IDLE = 4'b0001, PRESS_DELAY = 4'b0010, WAIT_RELEASE = 4'b0100, RELEASE_DELA = 4'b1000;
reg [1:0] key_in_r;
wire key_press_edge;
wire key_release_edge;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
key_in_r <= 2'b11;
end else begin
key_in_r <= {key_in_r[0], key_in};
end
end
assign key_press_edge = key_in_r[1] & (~key_in_r[0]);
assign key_release_edge = (~key_in_r[1]) & key_in_r[0];
reg [17:0] cnt;
reg [3:0] cstate, nstate;
//FSM-1
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cstate <= IDLE;
end else begin
cstate <= nstate;
end
end
//FSM-2
always @(*) begin
case (cstate)
IDLE: nstate = key_press_edge ? PRESS_DELAY : IDLE;
PRESS_DELAY: begin
if (cnt == DELAY_TIME && key_in_r[0] == 0) begin
nstate = WAIT_RELEASE; //按下完成
end else if (cnt < DELAY_TIME && key_in_r[0] == 1) begin
nstate = IDLE; //抖动
end else begin
nstate = PRESS_DELAY; //计数未完成
end
end
WAIT_RELEASE: nstate = key_release_edge ? RELEASE_DELA : WAIT_RELEASE;
RELEASE_DELA: begin
if (cnt == DELAY_TIME && key_in_r[0] == 1) begin
nstate = IDLE; //松开完成
end else if (cnt < DELAY_TIME && key_in_r[0] == 0) begin
nstate = WAIT_RELEASE; //抖动
end else begin
nstate = RELEASE_DELA; //计数未完成
end
end
default: nstate = IDLE;
endcase
end
//FSM-3
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
key_vld <= 1'b1;
end else begin
case (nstate)
IDLE, PRESS_DELAY: key_vld <= 1'b1;
WAIT_RELEASE, RELEASE_DELA: key_vld <= 1'b0;
default: key_vld <= 1'b1;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) cnt <= 18'd0;
else if (cstate == PRESS_DELAY || cstate == RELEASE_DELA) begin
if (cnt == DELAY_TIME) begin
cnt <= 18'd0;
end else begin
cnt <= cnt + 1'b1;
end
end else begin
cnt <= 18'd0;
end
end
endmodule
| 8.549926 |
module Test6 (
input clock,
input reset,
input [15:0] io_in_0,
input [15:0] io_in_1,
input [15:0] io_in_2,
input [ 4:0] io_addr,
output [15:0] io_out
);
wire [15:0] _GEN_1 = 2'h1 == io_addr[1:0] ? io_in_1 : io_in_0; // @[Test6.scala 17:10 Test6.scala 17:10]
assign io_out = 2'h2 == io_addr[1:0] ? io_in_2 : _GEN_1; // @[Test6.scala 17:10 Test6.scala 17:10]
endmodule
| 7.028449 |
module flip_flop_vl (
input d,
clk,
reset,
output reg q
);
always @(posedge clk or posedge reset) begin
if (reset == 1) q = 1'b0;
else q = d;
end
endmodule
| 6.918617 |
module RAM (
CLK,
nCS,
nWE,
ADDR,
DI,
DO
);
// Port definition
input CLK, nCS, nWE;
input [11:0] ADDR;
input [15:0] DI;
output [15:0] DO;
wire CLK, nCS, nWE;
wire [11:0] ADDR;
wire [15:0] DI;
reg [15:0] DO;
// Implementation
reg [15:0] mem [0:4095];
always @(posedge CLK) begin
if (!nCS) begin
if (!nWE) mem[ADDR[11:0]] <= DI;
end
end
always @(posedge CLK) begin
if (!nCS) begin
DO <= mem[ADDR[11:0]];
end
end
`ifdef __ICARUS__
initial begin : prefill
integer i;
for (i = 0; i < 4096; i = i + 1) mem[i] = 0;
mem[3] = 16'h0008;
mem[4] = 16'h4e71;
mem[5] = 16'h31c0;
mem[6] = 16'h1234;
mem[7] = 16'h60f8;
end
`endif
endmodule
| 6.625533 |
module test68 (
input clk_25mhz,
output [7:0] leds
);
// ===============================================================
// 68000 CPU
// ===============================================================
reg fx68_phi1 = 0;
wire fx68_phi2 = !fx68_phi1;
always @(posedge clk_25mhz) begin
fx68_phi1 <= ~fx68_phi1;
end
reg [15:0] pwr_up_reset_counter = 0;
wire pwr_up_reset_n = &pwr_up_reset_counter;
always @(posedge clk_25mhz) begin
if (!pwr_up_reset_n) pwr_up_reset_counter <= pwr_up_reset_counter + 1;
end
// CPU outputs
wire cpu_rw; // Read = 1, Write = 0
wire cpu_as_n; // Address strobe
wire cpu_lds_n; // Lower byte
wire cpu_uds_n; // Upper byte
wire cpu_E; // Peripheral enable
wire vma_n; // Valid memory address
wire [ 2:0] cpu_fc; // Processor state
wire cpu_reset_n_o; // Reset output signal
wire cpu_halted_n;
wire bg_n; // Bus grant
// CPU busses
wire [15:0] cpu_dout; // Data from CPU
wire [23:0] cpu_a; // Address
wire [15:0] cpu_din; // Data to CPU
// CPU inputs
wire berr_n = 1'b1; // Bus error (never error)
wire dtack_n = 1'b0; // Data transfer ack (always ready)
wire vpa_n; // Valid peripheral address
reg mcu_br_n; // Bus request
reg bgack_n = 1'b1; // Bus grant ack
reg ipl0_n = 1'b1; // Interrupt request signals
reg ipl1_n = 1'b1;
reg ipl2_n = 1'b1;
assign cpu_a[0] = 0; // to make gtk wave easy
fx68k fx68k (
// input
.clk(clk_25mhz),
.enPhi1(fx68_phi1),
.enPhi2(fx68_phi2),
.extReset(!pwr_up_reset_n),
.pwrUp(!pwr_up_reset_n),
.HALTn(pwr_up_reset_n),
// output
.eRWn(cpu_rw),
.ASn(cpu_as_n),
.LDSn(cpu_lds_n),
.UDSn(cpu_uds_n),
.E(cpu_E),
.VMAn(vma_n),
.VPAn(1'b1),
.FC0(cpu_fc[0]),
.FC1(cpu_fc[1]),
.FC2(cpu_fc[2]),
.BGn(bg_n),
.oRESETn(cpu_reset_n_o),
.oHALTEDn(cpu_halted_n),
// input
.DTACKn(dtack_n),
.BERRn (berr_n),
.BRn (1'b1), // No bus requests
.BGACKn(1'b1),
.IPL0n (ipl0_n),
.IPL1n (ipl1_n),
.IPL2n (ipl2_n),
// busses
.iEdb(cpu_din),
.oEdb(cpu_dout),
.eab (cpu_a[23:1])
);
RAM ram (
.CLK (clk_25mhz),
.nCS (cpu_as_n),
.nWE (cpu_rw),
.ADDR(cpu_a[12:1]),
.DI (cpu_dout),
.DO (cpu_din)
);
assign leds = cpu_dout;
endmodule
| 7.035199 |
module test_dff_v (
clk,
d,
q
);
parameter g_count = 1;
input [g_count-1:0] d;
input clk;
output reg [g_count-1:0] q;
genvar i;
generate
for (i = 0; i <= g_count - 1; i = i + 1) begin : REG
always @(posedge clk) q[i] <= d[i];
end
endgenerate
endmodule
| 6.993199 |
module FullTB;
reg clk, ena, rst;
integer i;
integer cycles;
wire [31:0] alpha, k, error, model;
wire done;
reg [31:0] acf;
wire valid;
wire [3:0] m;
wire signed [31:0] quant_c;
wire q_valid;
Durbinator db (
.iClock (clk),
.iEnable(ena),
.iReset (rst),
.iACF(acf),
.alpha(alpha),
.error(error),
.k(k),
.oM(m),
.oModel(model),
.oValid(valid),
.oDone(done)
);
Quantizer q (
.iClock(clk),
.iEnable(ena),
.iReset(rst),
.iValid(valid),
.iFloatCoeff(model),
.oQuantizedCoeff(quant_c),
.oValid(q_valid)
);
always begin
#0 clk = 0;
#10 clk = 1;
#10 cycles = cycles + 1;
end
initial begin
cycles = 0;
ena = 0;
rst = 1;
#30;
#20;
ena = 1;
rst = 0;
acf = 32'h0x3f800000;
#20;
acf = 32'h0x3f7f7bb8;
#20;
acf = 32'h0x3f7e0430;
#20;
acf = 32'h0x3f7b9f88;
#20;
acf = 32'h0x3f784f5a;
#20;
acf = 32'h0x3f742267;
#20;
acf = 32'h0x3f6f2663;
#20;
acf = 32'h0x3f696ae8;
#20;
acf = 32'h0x3f63029e;
#20;
acf = 32'h0x3f5bfe6b;
#20;
acf = 32'h0x3f54715b;
#20;
acf = 32'h0x3f4c6cdf;
#20;
acf = 32'h0x3f4401d3;
#20;
for (i = 0; i < 1200; i = i + 1) begin
if (valid) begin
$display(" %d MODEL: %f", m, `DFP(model));
end
if (q_valid) begin
$display("Q: %d Model: %d", m, quant_c);
end
#20;
end
$stop;
end
endmodule
| 6.790235 |
module TestADDA (
originalClock,
clockAD,
clockDA,
nCS,
SDATA,
nSYNC,
DIN,
led
);
input originalClock;
output nCS;
input SDATA;
output nSYNC;
output DIN;
output clockAD;
output clockDA;
output [7:0] led;
wire [7:0] tempLevel;
AD(
.clock(originalClock), .level(tempLevel), .SDATA(SDATA), .nCS(nCS)
); DA(
.clock(originalClock), .level(tempLevel), .nSYNC(nSYNC), .DIN(DIN)
);
assign clockAD = originalClock;
assign clockDA = originalClock;
assign led = ~tempLevel;
endmodule
| 7.039959 |
module of the EX stage of the pipeline.
`include "ALU_CONTROL.v"
module test ( ) ;
// Wire Ports
wire [ 2 : 0 ] select;
// Register Declarations
reg [ 1 : 0 ] alu_op ;
reg [ 5 : 0 ] funct ;
ALU_CONTROL alucontrol1 ( alu_op, funct, select ) ;
initial begin
alu_op = 2'b00 ;
funct = 6'b100000 ;
$monitor ( "ALUOp = %b \ tfunct = %b\ tselect = %b ", alu_op , funct , select) ;
#10
alu_op = 2'b01 ;
funct = 6'b100000 ;
#10
alu_op = 2'b10 ;
funct = 6'b100000 ;
#10
funct = 6'b100010 ;
#10
funct = 6'b100100 ;
#10
funct = 6'b100101 ;
#10
funct = 6'b101010 ;
#10
alu_op = 2'b11;
funct = 6'b101100 ;
#10
$finish ;
end
endmodule
| 7.294112 |
module and3gate (
output s,
input a,
input b,
input c
);
assign s = (a & b & c);
endmodule
| 8.641841 |
module testand3entgate;
// ---------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
and3gate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
a = 0;
b = 0;
c = 0;
end
// ------------------------- parte principal
initial begin
$display("Exercicio 4 - Afonso Spinelli - 266304");
$display("Tabela Verdade para porta AND com 3 entradas - v1.0\n");
$display("(a & b & c) = s\n");
#1 $display("(%b & %b & %b) = %b", a, b, c, s);
a = 0;
b = 0;
c = 1;
#1 $display("(%b & %b & %b) = %b", a, b, c, s);
a = 0;
b = 1;
c = 0;
#1 $display("(%b & %b & %b) = %b", a, b, c, s);
a = 0;
b = 1;
c = 1;
#1 $display("(%b & %b & %b) = %b", a, b, c, s);
a = 1;
b = 0;
c = 0;
#1 $display("(%b & %b & %b) = %b", a, b, c, s);
a = 1;
b = 0;
c = 1;
#1 $display("(%b & %b & %b) = %b", a, b, c, s);
a = 1;
b = 1;
c = 0;
#1 $display("(%b & %b & %b) = %b", a, b, c, s);
a = 1;
b = 1;
c = 1;
#1 $display("(%b & %b & %b) = %b", a, b, c, s);
end
endmodule
| 7.188672 |
module testandgate;
reg [2:0] a, b;
wire [2:0] s;
// instancia
andgate AND1 (
s,
a,
b
);
// parte principal
initial begin
$display("Exemplo 04_01 - xxx yyy zzz - 999999");
$display("Test AND gate");
$display("\na & b = s\n");
a = 3'b000;
b = 3'b000;
#1 $display("%3b & %3b = %3b", a, b, s);
a = 3'b001;
b = 3'b111;
#1 $display("%3b & %3b = %3b", a, b, s);
a = 3'b111;
b = 3'b101;
#1 $display("%3b & %3b = %3b", a, b, s);
a = 3'b101;
b = 3'b010;
#1 $display("%3b & %3b = %3b", a, b, s);
end
endmodule
| 6.553783 |
module testando_cont_pc (
input clock,
output [31:0] PC
);
wire [31:0] PC_mais_1;
Program_Counter test_PC (
.clock(clock),
.PC_in(PC_mais_1),
.PC(PC),
.PC_mais_1(PC_mais_1)
);
endmodule
| 7.070834 |
module testAnythingProtocol
#( parameter TAP_FOLDER = "",
parameter TAP_FILE = "",
parameter MAX_STRING_LENGTH = 80 );
integer hTap; //File handle for tap file
integer hTemp; //File handle for temporary file
integer testCaseIdx = 0; //Current testcase index
reg[ 7: 0 ] character;
initial begin
if ( TAP_FILE == 0 || TAP_FOLDER == 0 ) begin
$display( "No TAP_FOLDER or TAP_FILE specified" );
end
else begin
hTemp = $fopen( { TAP_FOLDER, "/tap.tmp" }, "w" );
end
end
task assert (
input sucess,
input [ MAX_STRING_LENGTH * 8 - 1: 0 ] message
);
begin
// add test case to temp file
testCaseIdx = testCaseIdx + 1;
if ( sucess ) begin
$fwrite( hTemp, "ok %0d - %0s\n", testCaseIdx, message );
end
else begin
$fwrite( hTemp, "not ok %0d - %0s\n", testCaseIdx, message );
end
end
endtask
task finish;
begin
$fclose( hTemp );
hTemp = $fopen( { TAP_FOLDER, "/tap.tmp" }, "r" );
hTap = $fopen( { TAP_FOLDER, "/", TAP_FILE }, "w" );
// Copy content to tap file including header
$fwrite( hTap, "1..%0d\n", testCaseIdx );
character = $fgetc( hTemp );
while ( character <= 126 ) begin
$fwrite( hTap, "%c", character );
character = $fgetc( hTemp );
end
$fclose( hTap );
$fclose( hTemp );
$finish;
end
endtask
endmodule
| 7.339826 |
module TestBench ();
localparam w = 16;
localparam n = 8;
localparam T = 200;
reg read_enable, wirte_enable, rst, clk;
reg [2:0] read_addr, write_addr;
wire [w-1:0] read_data, read_data_1;
reg [w-1:0] write_data;
MemoryRegisters #(w, n) RegistersTest (
read_enable,
wirte_enable,
read_data,
write_data,
clk,
rst,
read_addr,
write_addr
);
memoryArray #(n, w) ArrayTest (
read_enable,
wirte_enable,
read_data_1,
write_data,
clk,
rst,
read_addr,
write_addr
);
initial begin
$monitor(
"the data read_enable=%b write_enable=%b read_data=%b write_data=%b read_addr=%b write_addr=%b for Registers ",
read_enable, wirte_enable, read_data, write_data, read_addr, write_addr);
$monitor(
" the data read_enable=%b write_enable=%b read_data=%b write_data=%b read_addr=%b write_addr=%b for Arrays ",
read_enable, wirte_enable, read_data_1, write_data, read_addr, write_addr);
end
initial begin
$display(" test 1 case write data in position 000");
wirte_enable = 1;
read_enable = 0;
write_addr = 3'b000;
write_data = 16'b0000111100001111;
#T;
$display(" test 2 case read data in position 000");
read_enable = 1;
wirte_enable = 0;
read_addr = 3'b000;
#T;
#T;
if (read_data == 16'b0000111100001111 && read_data_1 == 16'b0000111100001111)
$display("test case one and two success");
$display(" test 3 case write data in position 011");
wirte_enable = 1;
read_enable = 0;
write_addr = 3'b011;
write_data = 16'b0000111111111111;
#T;
$display(" test 4 case read data in position 011");
read_enable = 1;
wirte_enable = 0;
read_addr = 3'b011;
#T;
#T;
if (read_data == 16'b0000111111111111 && read_data_1 == 16'b0000111111111111)
$display("test case 3 and 4 success");
$display(" test 5 case write data in position 111");
wirte_enable = 1;
read_enable = 0;
write_addr = 3'b111;
write_data = 16'b0000111111111111;
#T;
$display(" test 6 case read data in position 111");
read_enable = 1;
wirte_enable = 0;
read_addr = 3'b111;
#T;
#T;
if (read_data == 16'b0000111111111111 && read_data_1 == 16'b0000111111111111)
$display("test case 5 and 6 success");
$display(" test 7 case write data in position 111 and enable the write and read");
wirte_enable = 1;
read_enable = 1;
write_addr = 3'b111;
write_data = 16'b1100111111111111;
#T;
#T;
$display(" test 8 case check the read data of test 7");
read_enable = 1;
wirte_enable = 0;
read_addr = 3'b111;
#T;
#T;
if (read_data == 16'b1100111111111111 && read_data_1 == 16'b1100111111111111)
$display("test case 8 success");
$display(" test 9 case check the reset with the enables");
rst = 1;
#50;
read_enable = 1;
read_addr = 3'b111;
#T;
#T;
if (read_data == 16'b0000000000000000 && read_data_1 == 16'b0000000000000000)
$display("test case 9 success");
end
endmodule
| 7.747207 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [15:0] duration;
reg finish;
reg [1:0] curstate;
reg [1:0] nxtstate;
reg [5:0] curaddr;
reg [5:0] nxtaddr;
reg [15:0] nxtduration;
reg [7:0] nxt_error_num;
reg state, state_next;
parameter state_idle = 2'b00;
parameter state_pass = 2'b01;
always@( posedge clk or negedge rst ) // State-DFF
begin
if (~rst) begin
curstate <= state_idle;
curaddr <= 0;
duration <= 0;
state <= 0;
end else begin
curstate <= nxtstate;
curaddr <= nxtaddr;
duration <= nxtduration;
state <= state_next;
end
end
always@( curstate or curaddr or addr or data or wen or duration ) // FSM for test
begin
finish = 1'b0;
case (curstate)
state_idle: begin
nxtaddr = 0;
nxtduration = 0;
if (addr == `TestPort && data == `answer && wen) begin
nxtstate = state_pass;
end else nxtstate = state_idle;
end
state_pass: begin
finish = 1'b1;
nxtaddr = curaddr;
nxtstate = curstate;
nxtduration = duration;
end
endcase
end
always @(*) begin //sub-FSM (avoid the Dcache stall condition)
case (state)
1'b0: begin
if (wen) state_next = 1;
else state_next = state;
end
1'b1: begin
if (!wen) state_next = 0;
else state_next = state;
end
endcase
end
always @(negedge clk) begin
if (curstate == state_pass) begin
$display("============================================================================");
$display("\n \\(^o^)/ CONGRATULATIONS!! The simulation result is PASS!!!\n");
$display("============================================================================");
end
end
endmodule
| 8.489904 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [15:0] duration;
reg finish;
reg [1:0] curstate;
reg [1:0] nxtstate;
reg [5:0] curaddr;
reg [5:0] nxtaddr;
reg [15:0] nxtduration;
reg [7:0] nxt_error_num;
reg state, state_next;
parameter state_idle = 2'b00;
parameter state_pass = 2'b01;
always@( posedge clk or negedge rst ) // State-DFF
begin
if (~rst) begin
curstate <= state_idle;
curaddr <= 0;
duration <= 0;
state <= 0;
end else begin
curstate <= nxtstate;
curaddr <= nxtaddr;
duration <= nxtduration;
state <= state_next;
end
end
always@( curstate or curaddr or addr or data or wen or duration ) // FSM for test
begin
finish = 1'b0;
case (curstate)
state_idle: begin
nxtaddr = 0;
nxtduration = 0;
if (addr == `TestPort && data == `answer && wen) begin
nxtstate = state_pass;
end else nxtstate = state_idle;
end
state_pass: begin
finish = 1'b1;
nxtaddr = curaddr;
nxtstate = curstate;
nxtduration = duration;
end
endcase
end
always @(*) begin //sub-FSM (avoid the Dcache stall condition)
case (state)
1'b0: begin
if (wen) state_next = 1;
else state_next = state;
end
1'b1: begin
if (!wen) state_next = 0;
else state_next = state;
end
endcase
end
always @(negedge clk) begin
if (curstate == state_pass) begin
$display("============================================================================");
$display("\n \\(^o^)/ CONGRATULATIONS!! The simulation result is PASS!!!\n");
$display("============================================================================");
end
end
endmodule
| 8.489904 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish,
br,
wrong
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg finish;
reg [1:0] curstate;
reg [1:0] nxtstate;
reg [7:0] error_num, nxt_error_num;
reg state, state_next;
input br, wrong;
integer f, br_times, wrong_times, dur;
parameter state_A = 2'b00;
parameter state_B = 2'b01;
parameter state_C = 2'b10;
parameter state_end = 2'b11;
assign duration = 0;
initial begin
f = $fopen("output.txt", "a");
@(posedge rst);
@(posedge clk);
if (f) $display("File open suceessfully: %0d", f);
else $display("File open error: %0d", f);
@(curstate == state_end) begin
$display("write result to output.txt");
$fwrite(f, "duration: %d\n", dur);
$fwrite(f, "br_times: %d\n", br_times);
$fwrite(f, "wrong_times: %d\n", wrong_times);
end
$fclose(f);
end
always @(posedge clk) begin
if (~rst) begin
br_times = 0;
wrong_times = 0;
dur = 0;
end else begin
dur = dur + 1;
if (curstate == state_A | curstate == state_B | curstate == state_C) begin
if (br) begin
br_times = br_times + 1;
if (wrong) begin
wrong_times = wrong_times + 1;
end
end
end
end
end
always@( posedge clk or negedge rst ) // State-DFF
begin
if (~rst) begin
curstate <= state_A;
error_num <= 8'd0;
state <= 0;
end else begin
curstate <= nxtstate;
error_num <= nxt_error_num;
state <= state_next;
end
end
always@(*) // FSM for test
begin
finish = 1'b0;
case (curstate)
state_A: begin
nxt_error_num = error_num;
nxtstate = curstate;
if (addr == 0 && wen && !state) begin
if (data == 0) begin
$display("\nBranch Part A is complete.");
nxtstate = state_B;
end else begin
nxt_error_num = error_num + 1;
end
end
end
state_B: begin
nxt_error_num = error_num;
nxtstate = curstate;
if (addr == 0 && wen && !state) begin
if (data == 0) begin
$display("\nBranch Part B is complete.");
nxtstate = state_C;
end else begin
nxt_error_num = error_num + 1;
end
end
end
state_C: begin
nxt_error_num = error_num;
nxtstate = curstate;
if (addr == 0 && wen && !state) begin
if (data == 0) begin
$display("\nBranch Part C is complete.\n");
nxtstate = state_end;
end else begin
nxt_error_num = error_num + 1;
end
end
end
state_end: begin
finish = 1'b1;
nxtstate = curstate;
nxt_error_num = error_num;
end
endcase
end
always @(*) begin //sub-FSM (avoid the Dcache stall condition)
case (state)
1'b0: begin
if (wen) state_next = 1;
else state_next = state;
end
1'b1: begin
if (!wen) state_next = 0;
else state_next = state;
end
endcase
end
always @(negedge clk) begin
if (curstate == state_end) begin
$display("--------------------------- Simulation FINISH !!---------------------------");
if (error_num) begin
$display("============================================================================");
$display("\n (T_T) FAIL!! The simulation result is FAIL!!!\n");
$display("============================================================================");
end else begin
$display("============================================================================");
$display("\n \\(^o^)/ CONGRATULATIONS!! The simulation result is PASS!!!\n");
$display("============================================================================");
end
end
end
endmodule
| 8.489904 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [7:0] error_num;
reg [15:0] duration;
reg finish;
reg [31:0] answer;
reg [1:0] curstate;
reg [1:0] nxtstate;
reg [4:0] curaddr;
reg [4:0] nxtaddr;
reg [7:0] nxt_error_num;
reg [15:0] nxtduration;
reg state, state_next;
wire [31:0] data_modify;
parameter state_idle = 2'b00;
parameter state_check = 2'b01;
parameter state_report = 2'b10;
assign data_modify = {
data[7:0], data[15:8], data[23:16], data[31:24]
}; // convert little-endian format to readable format
always@( posedge clk or negedge rst ) // State-DFF
begin
if (~rst) begin
curstate <= state_idle;
curaddr <= 0;
duration <= 0;
error_num <= 8'd255;
state <= 0;
end else begin
curstate <= nxtstate;
curaddr <= nxtaddr;
duration <= nxtduration;
error_num <= nxt_error_num;
state <= state_next;
end
end
always@(*) // FSM for test
begin
finish = 1'b0;
case (curstate)
state_idle: begin
nxtaddr = 0;
nxtduration = 0;
nxt_error_num = 255;
if (addr == `TestPort && data_modify == `BeginSymbol && wen) begin
nxt_error_num = 0;
nxtstate = state_check;
end else nxtstate = state_idle;
end
state_check: begin
nxtduration = duration + 1;
nxtaddr = curaddr;
nxt_error_num = error_num;
if (addr == `TestPort && wen && state == 0) begin
nxtaddr = curaddr + 1;
if (data_modify != answer) nxt_error_num = error_num + 8'd1;
end
nxtstate = curstate;
if (curaddr == `CheckNum) nxtstate = state_report;
end
state_report: begin
finish = 1'b1;
nxtaddr = curaddr;
nxtstate = curstate;
nxtduration = duration;
nxt_error_num = error_num;
end
endcase
end
always @(negedge clk) begin
if (curstate == state_report) begin
$display("--------------------------- Simulation FINISH !!---------------------------");
if (error_num) begin
$display("============================================================================");
$display("\n (T_T) FAIL!! The simulation result is FAIL!!! there were %d errors at all.\n",
error_num);
$display("============================================================================");
end else begin
$display("============================================================================");
$display("\n \\(^o^)/ CONGRATULATIONS!! The simulation result is PASS!!!\n");
$display("============================================================================");
end
end
end
always @(*) begin //sub-FSM (avoid the Dcache stall condition)
case (state)
1'b0: begin
if (wen) state_next = 1;
else state_next = state;
end
1'b1: begin
if (!wen) state_next = 0;
else state_next = state;
end
endcase
end
always@(*) // ROM for correct result
begin
answer = 0;
case (curaddr)
5'd0: answer = 32'h0000DEAD;
5'd1: answer = 32'h0000F625;
5'd2: answer = 32'h6F568000;
5'd3: answer = 32'h37AB4000;
5'd4: answer = 32'h8B2C2000;
5'd5: answer = 32'h45961000;
5'd6: answer = 32'h22CB0800;
5'd7: answer = 32'h80BC0400;
5'd8: answer = 32'h405E0200;
5'd9: answer = 32'h202F0100;
5'd10: answer = 32'h10178080;
5'd11: answer = 32'h77624040;
5'd12: answer = 32'hAB07A020;
5'd13: answer = 32'h5583D010;
5'd14: answer = 32'h9A186808;
5'd15: answer = 32'hBC62B404;
5'd16: answer = 32'hCD87DA02;
5'd17: answer = 32'hD61A6D01;
5'd18: answer = `EndSymbol;
endcase
end
endmodule
| 8.489904 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [7:0] error_num;
reg [15:0] duration;
reg finish;
reg [31:0] answer;
reg [1:0] curstate;
reg [1:0] nxtstate;
reg [6:0] curaddr;
reg [6:0] nxtaddr;
reg [7:0] nxt_error_num;
reg [15:0] nxtduration;
reg state, state_next;
wire [31:0] data_modify;
parameter state_idle = 2'b00;
parameter state_check = 2'b01;
parameter state_report = 2'b10;
assign data_modify = {
data[7:0], data[15:8], data[23:16], data[31:24]
}; // convert little-endian format to readable format
always@( posedge clk or negedge rst ) // State-DFF
begin
if (~rst) begin
curstate <= state_idle;
curaddr <= 0;
duration <= 0;
error_num <= 8'd255;
state <= 0;
end else begin
curstate <= nxtstate;
curaddr <= nxtaddr;
duration <= nxtduration;
error_num <= nxt_error_num;
state <= state_next;
end
end
always@(*) // FSM for test
begin
finish = 1'b0;
case (curstate)
state_idle: begin
nxtaddr = 0;
nxtduration = 0;
nxt_error_num = 255;
if (addr == `TestPort && data_modify == `BeginSymbol && wen) begin
nxt_error_num = 0;
nxtstate = state_check;
end else nxtstate = state_idle;
end
state_check: begin
nxtduration = duration + 1;
nxtaddr = curaddr;
nxt_error_num = error_num;
if (addr == `TestPort && wen && state == 0) begin
nxtaddr = curaddr + 1;
if (data_modify != answer) nxt_error_num = error_num + 8'd1;
end
nxtstate = curstate;
if (curaddr == `CheckNum) nxtstate = state_report;
end
state_report: begin
finish = 1'b1;
nxtaddr = curaddr;
nxtstate = curstate;
nxtduration = duration;
nxt_error_num = error_num;
end
endcase
end
always @(negedge clk) begin
if (curstate == state_report) begin
$display("--------------------------- Simulation FINISH !!---------------------------");
if (error_num) begin
$display("============================================================================");
$display("\n (T_T) FAIL!! The simulation result is FAIL!!! there were %d errors at all.\n",
error_num);
$display("============================================================================");
end else begin
$display("============================================================================");
$display("\n \\(^o^)/ CONGRATULATIONS!! The simulation result is PASS!!!\n");
$display("============================================================================");
end
end
end
always @(*) begin //sub-FSM (avoid the Dcache stall condition)
case (state)
1'b0: begin
if (wen) state_next = 1;
else state_next = state;
end
1'b1: begin
if (!wen) state_next = 0;
else state_next = state;
end
endcase
end
always@(*) // ROM for correct result
begin
answer = 0;
case (curaddr)
7'd0: answer = 32'd0;
7'd1: answer = 32'd1;
7'd2: answer = 32'd1;
7'd3: answer = 32'd1;
7'd4: answer = 32'd1;
7'd5: answer = 32'd0;
7'd6: answer = `EndSymbol;
endcase
end
endmodule
| 8.489904 |
module TESTBED;
parameter WIDTH_DATA = 256, WIDTH_RESULT = 1;
//Connection wires
wire [ (WIDTH_DATA-1):0] data;
wire [(WIDTH_RESULT-1):0] result;
wire clk, rst_n;
wire in_valid, out_valid;
initial begin
`ifdef RTL
$fsdbDumpfile("CS_IP_Demo.fsdb");
$fsdbDumpvars(0, "+mda");
`endif
`ifdef GATE
$sdf_annotate("CS_IP_Demo_SYN.sdf", My_IP);
$fsdbDumpfile("CS_IP_Demo_SYN.fsdb");
$fsdbDumpvars(0, "+mda");
`endif
end
`ifdef RTL
CS_IP_Demo #(
.WIDTH_DATA (WIDTH_DATA),
.WIDTH_RESULT(WIDTH_RESULT)
) My_IP (
.data(data),
.in_valid(in_valid),
.clk(clk),
.rst_n(rst_n),
.result(result),
.out_valid(out_valid)
);
PATTERN_IP #(
.WIDTH_DATA (WIDTH_DATA),
.WIDTH_RESULT(WIDTH_RESULT)
) My_PATTERN (
.data(data),
.in_valid(in_valid),
.clk(clk),
.rst_n(rst_n),
.result(result),
.out_valid(out_valid)
);
`elsif GATE
CS_IP_Demo My_IP (
.data(data),
.in_valid(in_valid),
.clk(clk),
.rst_n(rst_n),
.result(result),
.out_valid(out_valid)
);
PATTERN_IP #(
.WIDTH_DATA (WIDTH_DATA),
.WIDTH_RESULT(WIDTH_RESULT)
) My_PATTERN (
.data(data),
.in_valid(in_valid),
.clk(clk),
.rst_n(rst_n),
.result(result),
.out_valid(out_valid)
);
`endif
endmodule
| 6.55282 |
module TestBed (
clk,
rst,
addr,
data,
wen,
error_num,
duration,
finish
);
input clk, rst;
input [29:0] addr;
input [31:0] data;
input wen;
output [7:0] error_num;
output [15:0] duration;
output finish;
reg [7:0] error_num;
reg [15:0] duration;
reg finish;
reg [1:0] curstate;
reg [1:0] nxtstate;
reg [5:0] curaddr;
reg [5:0] nxtaddr;
reg [15:0] nxtduration;
reg [7:0] nxt_error_num;
reg state, state_next;
parameter state_idle = 2'b00;
parameter state_check = 2'b01;
parameter state_report = 2'b10;
always@( posedge clk or negedge rst ) // State-DFF
begin
if (~rst) begin
curstate <= state_idle;
curaddr <= 0;
duration <= 0;
error_num <= 8'd255;
state <= 0;
end else begin
curstate <= nxtstate;
curaddr <= nxtaddr;
duration <= nxtduration;
error_num <= nxt_error_num;
state <= state_next;
end
end
always@( curstate or curaddr or addr or data or wen or duration or error_num ) // FSM for test
begin
finish = 1'b0;
case (curstate)
state_idle: begin
nxtaddr = 0;
nxtduration = 0;
nxt_error_num = 255;
if (addr == `TestPort1 && data == `answer1 && wen) begin
nxt_error_num = 0;
nxtstate = state_check;
end else nxtstate = state_idle;
end
state_check: begin
nxtduration = duration + 1;
nxtaddr = curaddr;
nxt_error_num = error_num;
if (addr == `TestPort2 && wen && state == 0) begin
nxtaddr = curaddr + 1;
if (data != `answer2) nxt_error_num = error_num + 8'd1;
end else if (addr == `TestPort3 && wen && state == 0) begin
nxtaddr = curaddr + 1;
if (data != `answer3) nxt_error_num = error_num + 8'd1;
end else if (addr == `TestPort4 && wen && state == 0) begin
nxtaddr = curaddr + 1;
if (data != `answer4) nxt_error_num = error_num + 8'd1;
end
nxtstate = curstate;
if (curaddr == `CheckNum) nxtstate = state_report;
end
state_report: begin
finish = 1'b1;
nxtaddr = curaddr;
nxtstate = curstate;
nxtduration = duration;
nxt_error_num = error_num;
end
endcase
end
always @(*) begin //sub-FSM (avoid the Dcache stall condition)
case (state)
1'b0: begin
if (wen) state_next = 1;
else state_next = state;
end
1'b1: begin
if (!wen) state_next = 0;
else state_next = state;
end
endcase
end
always @(negedge clk) begin
if (curstate == state_report) begin
$display("--------------------------- Simulation FINISH !!---------------------------");
if (error_num) begin
$display("============================================================================");
$display("\n (T_T) FAIL!! The simulation result is FAIL!!! there were %d errors at all.\n",
error_num);
$display("============================================================================");
end else begin
$display("============================================================================");
$display("\n \\(^o^)/ CONGRATULATIONS!! The simulation result is PASS!!!\n");
$display("============================================================================");
end
end
end
endmodule
| 8.489904 |
module TESTBED;
wire clk, rst_n, in_valid;
wire [1:0] init;
wire [1:0] in0, in1, in2, in3;
wire out_valid;
wire [1:0] out;
initial begin
`ifdef RTL
$fsdbDumpfile("SUBWAY.fsdb");
$fsdbDumpvars(0, "+mda");
`endif
`ifdef GATE
$sdf_annotate("SUBWAY_SYN.sdf", u_SUBWAY);
$fsdbDumpfile("SUBWAY_SYN.fsdb");
$fsdbDumpvars(0, "+mda");
`endif
end
SUBWAY u_SUBWAY (
.clk(clk),
.rst_n(rst_n),
.in_valid(in_valid),
.init(init),
.in0(in0),
.in1(in1),
.in2(in2),
.in3(in3),
.out_valid(out_valid),
.out(out)
);
PATTERN u_PATTERN (
.clk(clk),
.rst_n(rst_n),
.in_valid(in_valid),
.init(init),
.in0(in0),
.in1(in1),
.in2(in2),
.in3(in3),
.out_valid(out_valid),
.out(out)
);
endmodule
| 6.764775 |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (1000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
picorv32_wrapper #(
.AXI_TEST(AXI_TEST),
.VERBOSE (VERBOSE)
) top (
.clk(clk),
.resetn(resetn),
.trap(trap),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule
| 6.640835 |
module testbench_CLA();
parameter bits = 8;
reg [bits-1:0] operand1;
reg [bits-1:0] operand2;
reg carryIn;
wire [bits-1:0] result;
wire carryOut;
wire p;
wire g;
integer i;
integer j;
integer k;
reg errorFlag = 0;
reg expectG;
reg expectP;
reg expectCOut;
reg [bits-1:0] expectResult;
initial begin
carryIn = 0;
for(k = 0;k < 2;k = k+1) begin
carryIn = ~carryIn;
for(i = 0;i < (1 << bits);i = i+1) begin
operand1 = i;
for(j = 0;j < (1 << bits);j = j+1) begin
operand2 = j;
{expectG,expectResult[bits-1:0]} = operand1 + operand2;
{expectCOut,expectResult[bits-1:0]} = operand1 + operand2 + carryIn;
expectP = &(operand1|operand2);
#1;
if (expectG !== g) begin
errorFlag = 1;
$display("singal G fail: %d+%d = %d, P = %d, G = %d, CIn = %d, COut = %d",operand1,operand2,result,p,g,carryIn,carryOut);
end
if(expectP !== p) begin
errorFlag = 1;
$display("singal P fail: %d+%d = %d, P = %d, G = %d, CIn = %d, COut = %d",operand1,operand2,result,p,g,carryIn,carryOut);
end
if(expectResult !== result) begin
errorFlag = 1;
$display("result fail: %d+%d = %d, P = %d, G = %d, CIn = %d, COut = %d",operand1,operand2,result,p,g,carryIn,carryOut);
end
if(expectCOut !== carryOut) begin
errorFlag = 1;
$display("carry out fail: %d+%d = %d, P = %d, G = %d, CIn = %d, COut = %d",operand1,operand2,result,p,g,carryIn,carryOut);
end
end
end
end
if(errorFlag == 0) begin
$display("Result test pass");
end
else begin
$display("Result test fail");
end
end
CLA #bits cla(.operand1(operand1), .operand2(operand2), .carryIn(carryIn), .carryOut(carryOut), .result(result), .p(p), .g(g));
endmodule
| 6.707837 |
module testbench_CLA_Array ();
localparam bits = 64;
reg [bits-1:0] a;
reg [bits-1:0] b;
reg cin;
wire [bits-1:0] result;
wire cout;
wire [bits:0] expectOutput;
reg errorFlag = 0;
integer i;
assign expectOutput = a + b + cin;
initial begin
a = 64'h1111111111111111;
b = 64'hffffffffffffffff;
cin = 1;
#10;
if ({cout, result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout, result}, expectOutput);
end
a = 64'h0000000000000000;
b = 64'hffffffffffffffff;
cin = 1;
#10;
if ({cout, result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout, result}, expectOutput);
end
a = 64'h1111111111111111;
b = 64'heeeeeeeeeeeeeeee;
cin = 1;
#10;
if ({cout, result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout, result}, expectOutput);
end
for (i = 0; i < 32'hffff; i = i + 1) begin
a = {$random(), $random()};
b = {$random(), $random()};
cin = ($random() & 1);
#10;
if ({cout, result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, {cout, result}, expectOutput);
end
end
if (errorFlag === 0) begin
$display("Test passed");
end else begin
$display("Test failed");
end
end
CLA_Array #16 cla (
.a(a),
.b(b),
.cin(cin),
.result(result),
.cout(cout)
);
endmodule
| 6.707837 |
module testbench_CLA_Array_32 ();
reg [31:0] a;
reg [31:0] b;
reg cin;
wire [31:0] result;
wire cout;
wire [32:0] expectOutput;
reg errorFlag = 0;
integer i;
assign expectOutput = a + b + cin;
initial begin
a = 32'h11111111;
b = 32'hffffffff;
cin = 1;
#10;
if ({cout, result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, expectOutput, {cout, result});
end
a = 32'h00000000;
b = 32'hffffffff;
cin = 1;
#10;
if ({cout, result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, expectOutput, {cout, result});
end
a = 32'h11111111;
b = 32'heeeeeeee;
cin = 1;
#10;
if ({cout, result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, expectOutput, {cout, result});
end
for (i = 0; i < 32'hffff; i = i + 1) begin
a = $random();
b = $random();
cin = ($random() & 1);
#10;
if ({cout, result} !== expectOutput) begin
errorFlag = 1;
$display("test fail: expect %x + %x = %x, actual %x", a, b, expectOutput, {cout, result});
end
end
if (errorFlag === 0) begin
$display("Test passed");
end else begin
$display("Test failed");
end
end
CLA_Array_32 cla (
.a(a),
.b(b),
.cin(cin),
.result(result),
.cout(cout)
);
endmodule
| 6.707837 |
module testbench_CSA();
parameter bits = 4;
reg [bits-1:0] a;
reg [bits-1:0] b;
reg [bits-1:0] cin;
wire [bits-1:0] sum;
wire [bits-1:0] cout;
integer i;
integer j;
integer k;
integer errorFlag = 0;
reg [bits-1:0] expectSum;
reg [bits-1:0] expectCout;
initial begin
for(i = 0;i < (1<<bits-1); i = i+1) begin
a = i;
for(i = 0;i < (1<<bits-1); i = i+1) begin
b = j;
for(i = 0;i < (1<<bits-1); i = i+1) begin
cin = k;
#1;
expectSum = (i^j^k);
expectCout = (i&j)|(i&k)|(j&k);
if( ( sum !== expectSum ) || ( cout !== expectCout ) ) begin
$display("%x + %x + %x, expect: sum = %x, cout = %x; actual sum = %x, cout = %x", i, j, k, expectSum, expectCout, sum, cout);
errorFlag = 1;
end
end
end
end
if (errorFlag === 0) begin
$display("Test passed.");
end
else begin
$display("Test failed.");
end
end
CSA #bits csa(.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));
endmodule
| 6.68794 |
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