code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module TemperatureMonitor_tb ();
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam time PER1 = 20 * ONE_NS;
// Declare the input clock signals
reg DCLK_TB = 1;
wire [ 6:0] DADDR_TB;
wire DEN_TB;
wire DWE_TB;
wire [15:0] DI_TB;
wire [15:0] DO_TB;
wire DRDY_TB;
wire [ 2:0] ALM_unused;
wire FLOAT_VCCAUX_ALARM;
wire FLOAT_VCCINT_ALARM;
wire FLOAT_USER_TEMP_ALARM;
// Input clock generation
always begin
DCLK_TB = #(PER1 / 2) ~DCLK_TB;
end
// Start of the testbench
initial begin
$display("Single channel avereraging is enabled");
$display("This TB does not verify averaging");
$display("Please increase the simulation duration to see complete waveform");
//// Single Channel setup
/////////////////////////////////////////////////////////////
//// Single Channel Mode - Temperature channel selected ////
/////////////////////////////////////////////////////////////
/// Channel selected is Temp. channel
$display("No status signals are pulled out to monitor the test status");
$display("Simulation Stopped.");
$finish;
end
// Instantiation of the example design
//---------------------------------------------------------
TemperatureMonitor_exdes dut (
.DADDR_IN(DADDR_TB[6:0]),
.DCLK_IN(DCLK_TB),
.DEN_IN(DEN_TB),
.DI_IN(DI_TB[15:0]),
.DWE_IN(DWE_TB),
.DO_OUT(DO_TB[15:0]),
.DRDY_OUT(DRDY_TB),
.VP_IN(1'b0),
.VN_IN(1'b0)
);
endmodule
| 8.35573 |
module RW_DATA_MODULE (
input CLK,
input RW,
input [79:0] DATA_TO_SEND,
input [7:0] COUNTER,
input ENABLE,
input INIT,
inout ONE_WIRE_LINE,
output reg [79:0] DATA_RECEIVED,
output READY,
output reg test_pin
);
wire ONE_WIRE_ENABLE;
reg DATA_TO_DRIVER = 0;
reg ONE_WIRE_ENABLE_reg = 0;
wire ONE_WIRE_READY;
reg [7:0] DATA_LENGTH = 0;
reg WORKING_reg = 0;
reg [3:0] machine_state = 0;
reg [3:0] next_machine_state = 0;
parameter ready_state = 0, write_data = 2, read_data = 3, read_data_catch = 4;
assign ONE_WIRE_RW = RW;
assign READY = (INIT) ? ONE_WIRE_READY : !(WORKING_reg | ENABLE);
assign ONE_WIRE_ENABLE = (INIT) ? ENABLE : ONE_WIRE_ENABLE_reg;
// always @(DATA_LENGTH)
// begin
// if(DATA_LENGTH == 0) WORKING_reg = 1'b0;
// else WORKING_reg = 1'b1;
//end
always @(ENABLE, DATA_LENGTH) begin
if (ENABLE) WORKING_reg = 1'b1;
else if (DATA_LENGTH == 0) WORKING_reg = 1'b0;
end
always @(posedge CLK) begin
case (machine_state)
ready_state: begin
if (ENABLE) begin
DATA_LENGTH <= 0;
test_pin <= 1'b1;
end
end
write_data: begin
if (DATA_LENGTH < COUNTER) begin
if (ONE_WIRE_READY) begin
DATA_TO_DRIVER <= DATA_TO_SEND[DATA_LENGTH];
ONE_WIRE_ENABLE_reg <= 1'b1;
DATA_LENGTH <= DATA_LENGTH + 1;
end else begin
ONE_WIRE_ENABLE_reg <= 1'b0;
end
end else begin
ONE_WIRE_ENABLE_reg <= 1'b0;
DATA_LENGTH <= 0;
end
end
read_data: begin
if (DATA_LENGTH < COUNTER) begin
if (ONE_WIRE_READY) begin
if (DATA_LENGTH > 0) DATA_RECEIVED[DATA_LENGTH-1] <= DATA_FROM_DRIVER;
ONE_WIRE_ENABLE_reg <= 1'b1;
DATA_LENGTH <= DATA_LENGTH + 1;
end else begin
ONE_WIRE_ENABLE_reg <= 1'b0;
end
end else begin
if (ONE_WIRE_READY) DATA_RECEIVED[DATA_LENGTH-1] <= DATA_FROM_DRIVER;
ONE_WIRE_ENABLE_reg <= 1'b0;
DATA_LENGTH <= 0;
end
end
read_data_catch: begin
if (ONE_WIRE_READY) begin
//DATA_RECEIVED[DATA_LENGTH] <= DATA_FROM_DRIVER;
//DATA_LENGTH++;
end
end
default: ;
endcase
end
always @(machine_state, INIT, RW, ENABLE, DATA_LENGTH) begin
case (machine_state)
ready_state: begin
if (INIT == 0 && ENABLE == 1) begin
if (RW == 1) begin
next_machine_state <= read_data;
end else begin
next_machine_state <= write_data;
end
end else begin
next_machine_state <= ready_state;
end
end
write_data: if (DATA_LENGTH == COUNTER) next_machine_state <= ready_state;
read_data: if (DATA_LENGTH == COUNTER) next_machine_state <= ready_state;
default: next_machine_state <= ready_state;
endcase
end
always @(posedge CLK) begin
machine_state <= next_machine_state;
end
ONE_WIRE_DRIVER ONE_WIRE_MOD (
.CLK(CLK),
.RW(ONE_WIRE_RW),
.DATA_IN(DATA_TO_DRIVER),
.ENABLE(ONE_WIRE_ENABLE),
.INIT(INIT),
.ONE_WIRE_LINE(ONE_WIRE_LINE),
.DATA_OUT(DATA_FROM_DRIVER),
.READY(ONE_WIRE_READY),
.test_pin()
);
endmodule
| 7.169553 |
module CLK_DIVIDER_3P3MHz (
input CLK_3P3MHz,
output UPDATE_COUNTER,
output BTN_SAMPLE,
output ONE_WIRE_CLK,
output READ_OUT_TIMER
);
reg [19:0] COUNTER = 20'b0;
always @(posedge CLK_3P3MHz) COUNTER <= COUNTER + 1;
assign UPDATE_COUNTER = COUNTER[19];
assign READ_OUT_TIMER = COUNTER[13];
assign BTN_SAMPLE = COUNTER[17];
assign ONE_WIRE_CLK = COUNTER[1];
endmodule
| 8.139274 |
module Digilent_IOX (
// -- Connections to Digilent Parallel Port (DPP) interface
// -- Controlled by Digilent ADEPT 2 software and USB controller
input ASTB, // Address strobe
input DSTB, // Data strobe
input WRITE, // Read/Write control
inout [ 7:0] DB, // Data bus, byte-wide
output WAIT, // Wait control
// --- Virtual I/O signals
input [31:0] FromFPGA, // 32-bit value (From FPGA on GUI)
output reg [31:0] ToFPGA // 32-bit value (To FPGA on GUI)
);
reg [7:0] AddressRegister; // Epp address
reg [7:0] CommValidRegister ; // Communitation link confirmed by reading complement of value written to FPGA
reg [7:0] busIOXinternal; // Internal data bus
// Assert WAIT signal whenever ASTB or DSTB are Low. Maximum port speed.
assign WAIT = (!ASTB | !DSTB);
// Control data direction to/from IOX interface
// If WRITE = 1, then read value on busIOXinternal. If WRITE = 0, set outputs to three-state (Hi-Z)
assign DB = ((WRITE) ? busIOXinternal : 8'bZZZZZZZZ);
// Read values from inside FPGA application and display on GUI
always @(*) begin
if (!ASTB) // When ASTB is Low
busIOXinternal <= AddressRegister; // ... Read address register
else if (AddressRegister == 8'h00) // When address is 0x00
busIOXinternal <= CommValidRegister ; // ... return the complement value written value to CommValidRegister
else if (AddressRegister == 8'h0d) // When address is 0x0D
busIOXinternal <= FromFPGA[7:0] ; // ... read value to be presented in "From FPGA" text box, bits 7:0
else if (AddressRegister == 8'h0e) // When address is 0x0E
busIOXinternal <= FromFPGA[15:8] ; // ... read value to be presented in "From FPGA" text box, bits 15:8
else if (AddressRegister == 8'h0f) // When address is 0x0F
busIOXinternal <= FromFPGA[23:16] ; // ... read value to be presented in "From FPGA" text box, bits 23:16
else if (AddressRegister == 8'h10) // When address is 0x10
busIOXinternal <= FromFPGA[31:24] ; // ... read value to be presented in "From FPGA" text box, bits 31:24
else
busIOXinternal <= 8'b11111111 ; // Otherwise, read all ones (or any value that looks like non data)
end
// EPP Address Register
// If WRITE = 0, load Address Register at rising-edge of ASTB
always @(posedge ASTB) if (!WRITE) AddressRegister <= DB;
// Write Various Registers based on settings from GUI controls
// If WRITE = 0, load register selected by Address Register at rising-edge of DSTB
always @(posedge DSTB)
if (!WRITE) begin
if (AddressRegister == 8'h00) // When address is 0x00
CommValidRegister <= ~DB ; // ... Load Verification register with complement of value written
// ... The GUI writes to this register to verify proper communication with target
else if (AddressRegister == 8'h09) // When address is 0x09
ToFPGA[7:0] <= DB; // ... Load value from "To FPGA" in GUI, bits 7:0
else if (AddressRegister == 8'h0a) // When address is 0x0A
ToFPGA[15:8] <= DB; // ... Load value from "To FPGA" in GUI, bits 15:8
else if (AddressRegister == 8'h0b) // When address is 0x0B
ToFPGA[23:16] <= DB; // ... Load value from "To FPGA" in GUI, bits 23:16
else if (AddressRegister == 8'h0c) // When address is 0x0C
ToFPGA[31:24] <= DB; // ... Load value from "To FPGA" in GUI, bits 31:24
end
endmodule
| 7.604002 |
module CLK_DIVIDER_3P3MHz (
input CLK_3P3MHz,
output UPDATE_COUNTER,
output BTN_SAMPLE,
output ONE_WIRE_CLK,
output READ_OUT_TIMER
);
reg [19:0] COUNTER = 20'b0;
always @(posedge CLK_3P3MHz) COUNTER <= COUNTER + 1;
assign UPDATE_COUNTER = COUNTER[19];
assign READ_OUT_TIMER = COUNTER[13];
assign BTN_SAMPLE = COUNTER[17];
assign ONE_WIRE_CLK = COUNTER[1];
endmodule
| 8.139274 |
module Digilent_IOX (
// -- Connections to Digilent Parallel Port (DPP) interface
// -- Controlled by Digilent ADEPT 2 software and USB controller
input ASTB, // Address strobe
input DSTB, // Data strobe
input WRITE, // Read/Write control
inout [ 7:0] DB, // Data bus, byte-wide
output WAIT, // Wait control
// --- Virtual I/O signals
input [31:0] FromFPGA, // 32-bit value (From FPGA on GUI)
output reg [31:0] ToFPGA // 32-bit value (To FPGA on GUI)
);
reg [7:0] AddressRegister; // Epp address
reg [7:0] CommValidRegister ; // Communitation link confirmed by reading complement of value written to FPGA
reg [7:0] busIOXinternal; // Internal data bus
// Assert WAIT signal whenever ASTB or DSTB are Low. Maximum port speed.
assign WAIT = (!ASTB | !DSTB);
// Control data direction to/from IOX interface
// If WRITE = 1, then read value on busIOXinternal. If WRITE = 0, set outputs to three-state (Hi-Z)
assign DB = ((WRITE) ? busIOXinternal : 8'bZZZZZZZZ);
// Read values from inside FPGA application and display on GUI
always @(*) begin
if (!ASTB) // When ASTB is Low
busIOXinternal <= AddressRegister; // ... Read address register
else if (AddressRegister == 8'h00) // When address is 0x00
busIOXinternal <= CommValidRegister ; // ... return the complement value written value to CommValidRegister
else if (AddressRegister == 8'h0d) // When address is 0x0D
busIOXinternal <= FromFPGA[7:0] ; // ... read value to be presented in "From FPGA" text box, bits 7:0
else if (AddressRegister == 8'h0e) // When address is 0x0E
busIOXinternal <= FromFPGA[15:8] ; // ... read value to be presented in "From FPGA" text box, bits 15:8
else if (AddressRegister == 8'h0f) // When address is 0x0F
busIOXinternal <= FromFPGA[23:16] ; // ... read value to be presented in "From FPGA" text box, bits 23:16
else if (AddressRegister == 8'h10) // When address is 0x10
busIOXinternal <= FromFPGA[31:24] ; // ... read value to be presented in "From FPGA" text box, bits 31:24
else
busIOXinternal <= 8'b11111111 ; // Otherwise, read all ones (or any value that looks like non data)
end
// EPP Address Register
// If WRITE = 0, load Address Register at rising-edge of ASTB
always @(posedge ASTB) if (!WRITE) AddressRegister <= DB;
// Write Various Registers based on settings from GUI controls
// If WRITE = 0, load register selected by Address Register at rising-edge of DSTB
always @(posedge DSTB)
if (!WRITE) begin
if (AddressRegister == 8'h00) // When address is 0x00
CommValidRegister <= ~DB ; // ... Load Verification register with complement of value written
// ... The GUI writes to this register to verify proper communication with target
else if (AddressRegister == 8'h09) // When address is 0x09
ToFPGA[7:0] <= DB; // ... Load value from "To FPGA" in GUI, bits 7:0
else if (AddressRegister == 8'h0a) // When address is 0x0A
ToFPGA[15:8] <= DB; // ... Load value from "To FPGA" in GUI, bits 15:8
else if (AddressRegister == 8'h0b) // When address is 0x0B
ToFPGA[23:16] <= DB; // ... Load value from "To FPGA" in GUI, bits 23:16
else if (AddressRegister == 8'h0c) // When address is 0x0C
ToFPGA[31:24] <= DB; // ... Load value from "To FPGA" in GUI, bits 31:24
end
endmodule
| 7.604002 |
module RW_DATA_MODULE (
input CLK,
input RW,
inout [71:0] DATA,
inout [7:0] COUNTER,
input ENABLE,
input INIT,
inout ONE_WIRE_LINE,
output READY,
output OK
);
wire ONE_WIRE_DATA;
wire ONE_WIRE_ENABLE;
reg ONE_WIRE_DATA_reg = 0;
reg ONE_WIRE_ENABLE_reg = 0;
wire ONE_WIRE_READY;
wire ONE_WIRE_OK;
reg ONE_WIRE_READY_reg = 1;
reg ONE_WIRE_OK_reg = 1;
reg [7:0] DATA_LENGTH = 0;
reg WORKING_reg;
reg [3:0] machine_state = 0;
reg [3:0] next_machine_state = 0;
reg [8:0] BIT_TIMEOUT = 0;
reg [71:0] DATA_reg;
parameter ready_state = 0, write_data = 2, read_data = 3;
localparam init_low_timer = 450;
assign ONE_WIRE_RW = RW;
// assign READY = !(WORKING_reg | ENABLE);//ONE_WIRE_READY;//
assign READY = (INIT) ? ONE_WIRE_READY : !(WORKING_reg | ENABLE);
assign OK = (INIT) ? ONE_WIRE_OK : ONE_WIRE_OK_reg;
assign ONE_WIRE_DATA = (RW) ? 1'bz : ONE_WIRE_DATA_reg;
assign ONE_WIRE_ENABLE = (INIT) ? ENABLE : ONE_WIRE_ENABLE_reg;
assign DATA = (RW) ? DATA_reg : 1'hzzzzzzzzzzzzzzzzzz;
always @(DATA_LENGTH) begin
if (DATA_LENGTH == 0) WORKING_reg = 1'b0;
else WORKING_reg = 1'b1;
end
//assign ONE_WIRE_READY_reg = WORKING_reg | ENABLE;
always @(posedge CLK) begin
case (machine_state)
ready_state: begin
if (ENABLE == 1) DATA_LENGTH = COUNTER;
end
write_data: begin
if (DATA_LENGTH > 0) begin
if (ONE_WIRE_READY) begin
ONE_WIRE_DATA_reg = DATA[DATA_LENGTH-1];
ONE_WIRE_ENABLE_reg = 1'b1;
DATA_LENGTH--;
end else begin
ONE_WIRE_ENABLE_reg = 1'b0;
end
end else begin
//ONE_WIRE_READY_reg = 1'b1;
ONE_WIRE_ENABLE_reg = 1'b0;
end
end
read_data: begin
if (DATA_LENGTH > 0) begin
if (ONE_WIRE_READY) begin
DATA_reg[DATA_LENGTH-1] = 1'b1; //DATA_LENGTH[0];
//ONE_WIRE_DATA_reg = DATA[DATA_LENGTH-1];
ONE_WIRE_ENABLE_reg = 1'b1;
DATA_LENGTH--;
end else begin
ONE_WIRE_ENABLE_reg = 1'b0;
end
end else begin
//ONE_WIRE_READY_reg = 1'b1;
ONE_WIRE_ENABLE_reg = 1'b0;
end
end
default: ;
endcase
end
always @(machine_state, ENABLE, DATA_LENGTH) begin
case (machine_state)
ready_state: begin
if (INIT == 0 && ENABLE == 1) begin
if (RW == 1) begin
next_machine_state = read_data;
end else begin
next_machine_state = write_data;
end
end else begin
next_machine_state = ready_state;
end
end
write_data: if (DATA_LENGTH == 0) next_machine_state = ready_state;
read_data: if (DATA_LENGTH == 0) next_machine_state = ready_state;
default: next_machine_state = ready_state;
endcase
end
always @(posedge CLK) begin
machine_state <= #1 next_machine_state;
end
ONE_WIRE_DRIVER ONE_WIRE_MOD (
.CLK(CLK),
.RW(ONE_WIRE_RW),
.DATA(ONE_WIRE_DATA),
.ENABLE(ONE_WIRE_ENABLE),
.INIT(INIT),
.ONE_WIRE_LINE(ONE_WIRE_LINE),
.READY(ONE_WIRE_READY),
.OK(ONE_WIRE_OK)
);
endmodule
| 7.169553 |
module CLK_DIVIDER_3P3MHz (
input CLK_3P3MHz,
output BTN_SAMPLE,
output ONE_WIRE_CLK
);
reg [19:0] COUNTER = 20'b0;
always @(posedge CLK_3P3MHz) COUNTER <= COUNTER + 1;
assign BTN_SAMPLE = COUNTER[17];
assign ONE_WIRE_CLK = COUNTER[1];
endmodule
| 8.139274 |
module Digilent_IOX (
// -- Connections to Digilent Parallel Port (DPP) interface
// -- Controlled by Digilent ADEPT 2 software and USB controller
input ASTB, // Address strobe
input DSTB, // Data strobe
input WRITE, // Read/Write control
inout [ 7:0] DB, // Data bus, byte-wide
output WAIT, // Wait control
// --- Virtual I/O signals
input [31:0] FromFPGA, // 32-bit value (From FPGA on GUI)
output reg [31:0] ToFPGA // 32-bit value (To FPGA on GUI)
);
reg [7:0] AddressRegister; // Epp address
reg [7:0] CommValidRegister ; // Communitation link confirmed by reading complement of value written to FPGA
reg [7:0] busIOXinternal; // Internal data bus
// Assert WAIT signal whenever ASTB or DSTB are Low. Maximum port speed.
assign WAIT = (!ASTB | !DSTB);
// Control data direction to/from IOX interface
// If WRITE = 1, then read value on busIOXinternal. If WRITE = 0, set outputs to three-state (Hi-Z)
assign DB = ((WRITE) ? busIOXinternal : 8'bZZZZZZZZ);
// Read values from inside FPGA application and display on GUI
always @(*) begin
if (!ASTB) // When ASTB is Low
busIOXinternal <= AddressRegister; // ... Read address register
else if (AddressRegister == 8'h00) // When address is 0x00
busIOXinternal <= CommValidRegister ; // ... return the complement value written value to CommValidRegister
else if (AddressRegister == 8'h0d) // When address is 0x0D
busIOXinternal <= FromFPGA[7:0] ; // ... read value to be presented in "From FPGA" text box, bits 7:0
else if (AddressRegister == 8'h0e) // When address is 0x0E
busIOXinternal <= FromFPGA[15:8] ; // ... read value to be presented in "From FPGA" text box, bits 15:8
else if (AddressRegister == 8'h0f) // When address is 0x0F
busIOXinternal <= FromFPGA[23:16] ; // ... read value to be presented in "From FPGA" text box, bits 23:16
else if (AddressRegister == 8'h10) // When address is 0x10
busIOXinternal <= FromFPGA[31:24] ; // ... read value to be presented in "From FPGA" text box, bits 31:24
else
busIOXinternal <= 8'b11111111 ; // Otherwise, read all ones (or any value that looks like non data)
end
// EPP Address Register
// If WRITE = 0, load Address Register at rising-edge of ASTB
always @(posedge ASTB) if (!WRITE) AddressRegister <= DB;
// Write Various Registers based on settings from GUI controls
// If WRITE = 0, load register selected by Address Register at rising-edge of DSTB
always @(posedge DSTB)
if (!WRITE) begin
if (AddressRegister == 8'h00) // When address is 0x00
CommValidRegister <= ~DB ; // ... Load Verification register with complement of value written
// ... The GUI writes to this register to verify proper communication with target
else if (AddressRegister == 8'h09) // When address is 0x09
ToFPGA[7:0] <= DB; // ... Load value from "To FPGA" in GUI, bits 7:0
else if (AddressRegister == 8'h0a) // When address is 0x0A
ToFPGA[15:8] <= DB; // ... Load value from "To FPGA" in GUI, bits 15:8
else if (AddressRegister == 8'h0b) // When address is 0x0B
ToFPGA[23:16] <= DB; // ... Load value from "To FPGA" in GUI, bits 23:16
else if (AddressRegister == 8'h0c) // When address is 0x0C
ToFPGA[31:24] <= DB; // ... Load value from "To FPGA" in GUI, bits 31:24
end
endmodule
| 7.604002 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// A generic module template for autocounters
// This is an upcounter, with wrapping
// OVALID maintained for consistency with AXI-STREAM, but it is always "valid"
// Creates an output trigger when wrapping, to allow creation of nested counters
// =============================================================================
module <module_name>
#(
parameter COUNTERW = <counterw>
, parameter STARTAT = <startat>
, parameter WRAPAT = <wrapat>
)
(
// =============================================================================
// ** Ports
// =============================================================================
input clk
, input rst
, input trig_count
, output ovalid
, output reg [COUNTERW-1:0] counter_value_s0
, output trig_wrap
);
assign ovalid = 1'b1;
//generate trigger if reached wrap (max) value
assign trig_wrap = (counter_value_s0 == WRAPAT);
always @(posedge clk) begin
if(rst)
counter_value_s0 <= STARTAT;
else if (trig_count)
if(trig_wrap)
counter_value_s0 <= STARTAT;
else
counter_value_s0 <= counter_value_s0+1;
else
counter_value_s0 <= counter_value_s0;
end
endmodule
| 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// A generic module template for leaf map nodes for use by Tytra Back-End Compile
// (TyBEC)
//
// NOTE ON AXI STREAM PROTOCOL:
//I am working on a IREADY **before** IVALID mechanism
//That is, the consimer indicates it is READY when it is ready, irrespetive of the
//IVALID state.
//Typiclaly, a node will look at OREADY downstream and
//assert IREADY accordingly, but since this is a (decoupling) FIFO buffer,
//it simply asserts IREADY when it is not empty
//In such a situation, write happens as soon as IVALID
//is asserted
//Read happens as soon as OREADY and OVALID are asserted
// =============================================================================
module <module_name>
#(
parameter STREAMW = <streamw>
)
(
// =============================================================================
// ** Ports
// =============================================================================
input clk
, input rst
, output reg ovalid
, input oready
, output iready
, input ivalid_in1_s0
, input [STREAMW-1:0] in1_s0
, output [STREAMW-1:0] out1_s0
);
wire empty;
//ovalid should follow ~empty with a single cycle delay
always @(posedge clk)
ovalid <= ~empty;
//always @(*)
// ovalid = ~empty;
//not full = iready
wire full;
assign iready = ~full;
//read and write
wire write = ivalid_in1_s0 & (~full);
wire read = oready & ovalid;
//instantiate buffer
<instFifoBuff>
endmodule
| 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// Template for axi4 stencil buffer (no "smart" caching)
// =============================================================================
module <module_name>
#(
parameter STREAMW = <streamw>
, parameter SIZE = <size>
)
(
// =============================================================================
// ** Ports
// =============================================================================
input clk
, input rst
, output iready
, input ivalid_in1_s0
, input [STREAMW-1:0] in1_s0
<ovalids>
<oreadys>
<outputs>
);
//shift register bank for data, and ovalid(s)
reg [STREAMW-1:0] offsetRegBank [0:SIZE-1];
reg valid_shifter [0:SIZE-1];
//local oready only asserted when *all* outputs are ready
<oreadysAnd>
//iready when all oready's asserted
assign iready = oready;
//tap at relevant delays
//the valid shifter takes care of the initial latency of filling up the buffer
//if ivalid is negated anytime during operation, we simply freeze the stream buffer
//so the valid shifter never gets a "0" in there (and the data shift register never reads
//invalid data). This contiguity of *valid* data ensures that data of a certain "offset" is
//always available at a fixed location
<assign_ovalids>
<assign_dataouts>
//SHIFT write
always @(posedge clk) begin
if(ivalid_in1_s0) begin
offsetRegBank[0] <= in1_s0;
valid_shifter[0] <= ivalid_in1_s0;
<shift_data_and_valid>
end else begin
offsetRegBank[0] <= offsetRegBank[0];
valid_shifter[0] <= valid_shifter[0];
<dont_shift_data_and_valid>
end
end
endmodule
| 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// Template for axi4 stream compatible buffer used in TyBEC synchronize parallel
// paths with mismatched latencies.
// Can be used to generate buffer with multiple "taps" for the same data
// =============================================================================
module <module_name>
#(
parameter STREAMW = <streamw>
, parameter SIZE = <size>
)
(
// =============================================================================
// ** Ports
// =============================================================================
input clk
, input rst
, output iready
, input ivalid_in1_s0
, input [STREAMW-1:0] in1_s0
<ovalids>
<oreadys>
<outputs>
);
//shift register bank for data, and ovalid(s)
reg [STREAMW-1:0] offsetRegBank [0:SIZE-1];
reg valid_shifter [0:SIZE-1];
//local oready only asserted when *all* outputs are ready
<oreadysAnd>
//iready when all oready's asserted
assign iready = oready;
//tap at relevant delays
//the valid shifter takes care of the initial latency of filling up the buffer
//if ivalid is negated anytime during operation, we simply freeze the stream buffer
//so the valid shifter never gets a "0" in there (and the data shift register never reads
//invalid data). This contiguity of *valid* data ensures that data of a certain "offset" is
//always available at a fixed location
<assign_ovalids>
<assign_dataouts>
//SHIFT write
always @(posedge clk) begin
if(ivalid_in1_s0) begin
offsetRegBank[0] <= in1_s0;
valid_shifter[0] <= ivalid_in1_s0;
<shift_data_and_valid>
end else begin
offsetRegBank[0] <= offsetRegBank[0];
valid_shifter[0] <= valid_shifter[0];
<dont_shift_data_and_valid>
end
end
endmodule
| 7.09244 |
module func_hdl_top
#(
parameter DATAW = <dataw>
,parameter STREAMW = <streamw>
)
(
input clock
,input resetn
,input ivalid
,input iready
,output ovalid
,output oready
<ports>
);
//statically synchronized, no handshaking
assign ovalid = 1'b1;
assign oready = 1'b1;
// ivalid, iready, resetn are ignored
wire rst = !resetn;
wire ovalidDut;
//child instantiation
<localOutputWires>
<concatOutputs>
main main_i(
.clk (clock)
,.rst (rst)
,.stall (!ivalid)
,.ovalid (ovalidDut)
<childPortConnections>
);
endmodule
| 7.616956 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// template for main (top-level synthesized module)
// (TyBEC)
//
//=============================================================================
module <module_name>
#(
parameter STREAMW = <streamw>
)
(
// =============================================================================
// ** Ports
// =============================================================================
input clk
, input rst
, output iready
, input ivalid
, output ovalid
, input oready
<ports>
);
// ============================================================================
// ** Instantiations
// ============================================================================
<connections>
//glue logic for output control signals
assign ovalid =
<ovalids>
1'b1;
assign iready =
<ireadysAnd>
1'b1;
<excFieldFlopoco>
// if input data to kernel_top module is flopoco floats (with 2 control bits)
// those two bits will be appended here during instantiation
//if output data from kernel_top module is flopoco floats (with 2 control bits)
//they will be connected to narrower data signals here, so as to truncate the top-most
//2 bits
<instantiations>
endmodule
| 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// A generic module template for leaf map nodes for use by Tytra Back-End Compile
// (TyBEC)
//
// =============================================================================
module <module_name>
#(
parameter STREAMW = <streamw>
)
(
// -----------------------------------------------------------------------------
// ** Ports
// -----------------------------------------------------------------------------
input clk
, input rst
, output iready
, output ovalid
<ivalids>
<oreadys>
<ports>
);
<connections>
//And input valids and output readys
<ivalidsAnd>
<oreadysAnd>
//glue logic for output control signals
assign ovalid =
<ovalids>
1'b1;
assign iready =
<ireadysAnd>
oready &
1'b1;
//single iready from a successor node may connect to multiple
//predecssor nodes; make those connections here
<ireadyConns>
<instantiations>
endmodule
| 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// A generic module template for leaf map nodes for use by Tytra Back-End Compile
// (TyBEC)
//
// =============================================================================
module <module_name>
#(
parameter DATAW = <dataw>
)
(
// =============================================================================
// ** Ports
// =============================================================================
input clk
, input rst
, input stall
<ports>
);
<connections>
<instantiations>
endmodule
| 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// A generic module template for leaf map nodes for use by Tytra Back-End Compile
// (TyBEC)
//
// =============================================================================
module <module_name>
#(
parameter STREAMW = <streamw>
)
(
// =============================================================================
// ** Ports
// =============================================================================
input clk
, input rst
, output ovalid
, output reg <oStrWidth> out1_s0
, input oready
, output iready
//<inputReadys> <-- deprecated
<inputIvalids>
<firstOpInputPort>
<secondOpInputPort>
<thirdOpInputPort>
);
//if FP, then I need to attend this constant 2 bits for flopoco units
<fpcEF>
//unregistered output
wire <oStrWidth> out1_pre_s0;
//And input valids and output readys
<inputIvalidsAnded>
//If any input operands are constants, assign them their value here
<assignConstants>
//dont stall if input valid and slave ready
wire dontStall = ivalid & oready;
//perform datapath operation, or instantiate module
<datapath>
//if I'm not stalling, I am ready
//assign iready = dontStall;
//if output is ready (and no locally generated stall), I am ready
//assign iready = oready & local_stall;
assign iready = oready;
//fanout iready to all inputs <-- deprecated
//<ireadysFanout>
//registered output
always @(posedge clk) begin
if(rst)
out1_s0 <= 0;
else if (dontStall)
out1_s0 <= out1_pre_s0;
else
out1_s0 <= out1_s0;
end
<ovalidLogic>
endmodule
| 7.09244 |
module_name>
// Generator Version : <gen_ver>
// Generator TimeStamp : <timeStamp>
//
// Dependencies : <dependencies>
//
//
// =============================================================================
// =============================================================================
// General Description
// -----------------------------------------------------------------------------
// A generic module template for leaf map nodes for use by Tytra Back-End Compile
// (TyBEC)
//
// =============================================================================
module <module_name>
#(
parameter DATAW = <dataw>
)
(
// =============================================================================
// ** Ports
// =============================================================================
input clk
, input rst
, input stall
, output reg[DATAW-1:0] out1_s0
, output reg[DATAW-1:0] out1_s1
, input [DATAW-1:0] in1_s0
, input [DATAW-1:0] in1_s1
, input [DATAW-1:0] in2_s0
, input [DATAW-1:0] in2_s1
);
//unregistered output
wire [DATAW-1:0] out1_pre_s0;
wire [DATAW-1:0] out1_pre_s1;
//perform datapath operation, or instantiate module
<datapath>
//registered output
always @(posedge clk) begin
if(rst) begin
out1_s0 <= 0;
out1_s1 <= 0;
end
else if (stall) begin
out1_s0 <= out1_s0;
out1_s1 <= out1_s1;
end
else begin
out1_s0 <= out1_pre_s0;
out1_s1 <= out1_pre_s1;
end
end
endmodule
| 7.09244 |
module: GasDetectorSensor
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TemplateTB;
// Inputs
reg arst;
reg clk;
reg din;
// Outputs
wire [2:0] dout;
// Instantiate the Unit Under Test (UUT)
GasDetectorSensor uut (
.arst(arst),
.clk(clk),
.din(din),
.dout(dout)
);
initial begin
clk = 0;
# 5
repeat (20)
# 10 clk = ~clk;
end
initial begin
// Initialize Inputs
arst = 1'b1;
# 2
arst = 1'b0;
din = 1'b0;
#10
din = 1'b1;
# 10
din = 1'b0;
# 40
din = 1'b0;
# 10
din = 1'b1;
# 10
din = 1'b0;
# 40
din = 1'b0;
# 10
din = 1'b1;
# 10
din = 1'b0;
# 40
din = 1'b0;
end
endmodule
| 7.168269 |
module conv3d_kernel_{{n_channel}}_channel_size_3 #(
parameter DATA_WIDTH = 32,
parameter IMG_WIDTH = 56,
parameter IMG_HEIGHT = 56,
parameter CHANNEL = {{n_channel}},
// Cx_Wy = CHANNELx_WEIGHTy
{{param_weight_bias}}
)
(
{{port}}
);
localparam NUM_OPERANDs = CHANNEL;
localparam NUM_DELAY = {{n_delay}};
reg [31:0] counter;
wire [31:0] data_out_conv_kernel [0:CHANNEL-1];
wire [CHANNEL-1:0] valid_out_conv_kernel;
wire [CHANNEL-1:0] done_conv;
wire [NUM_OPERANDs-2:0] valid_in_add;
wire [NUM_OPERANDs-2:0] valid_out_add;
wire [31:0] output_add [0:NUM_OPERANDs-2];
wire [31:0] op_1 [0:NUM_OPERANDs-2];
wire [31:0] op_2 [0:NUM_OPERANDs-2];
wire [31:0] in_delay [0:NUM_DELAY-1];
wire [31:0] out_delay [0:NUM_DELAY-1];
{{instances}}
{{content_assign_add}}
// Tao ra (NUM_OPERANDs - 1) bo fp add
genvar i;
generate
for (i = 0; i < NUM_OPERANDs-1; i=i+1)
begin :initial_adders // needs (NUM_OPERANDs - 1) adders
FP_Top_AddSub fp_adders(clk,resetn,valid_in_add[i],op_1[i],op_2[i],output_add[i],valid_out_add[i]);
end
endgenerate
// Delay input cho bo fp add
generate
for (i = 0; i < NUM_DELAY; i=i+1)
begin :delay_clocksssss
// ------------ Thay doi do delay theo mach cong ------------
delay_clock #(.DATA_WIDTH(32),.N_CLOCKs(1)) delay_xxx(clk,resetn,1'b1,in_delay[i],out_delay[i]);
end
endgenerate
wire valid_temp;
wire [31:0] data_temp;
assign valid_temp = valid_out_add[NUM_OPERANDs-2];
assign data_temp = output_add[NUM_OPERANDs-2];
wire temp_valid;
FP_Top_AddSub add_bias(clk, resetn, valid_temp, data_temp, BIAS, data_out, temp_valid);
assign valid_out_pixel = temp_valid;
always @ (posedge clk or negedge resetn)
begin
if(resetn == 1'b0)
counter <= 0;
else
if (done == 1'b1)
counter <= 0;
else
if(valid_out_pixel == 1'b1)
begin
if(counter == (IMG_WIDTH)*(IMG_HEIGHT) -1 )
counter <= 0;
else
counter <= counter + 1;
end
else
counter <= counter;
end
assign done = (counter == (IMG_WIDTH)*(IMG_HEIGHT) -1) & valid_out_pixel;
endmodule
| 7.186689 |
module conv3d_{{n_kernel}}_kernel_{{n_channel}}_channel_size_3 #(
parameter DATA_WIDTH = 32,
parameter IMG_WIDTH = 56,
parameter IMG_HEIGHT = 56,
parameter CHANNEL = {{n_channel}},
parameter NUM_KERNEL = {{n_kernel}},
// Kx_Cy_Wz = KERNELx_CHANNELy_WEIGHTz
{{param_weight_bias}}
)
(
{{port}}
);
wire [NUM_KERNEL-1:0] valid_out_conv;
wire [NUM_KERNEL-1:0] done_conv;
{{instances}}
endmodule
| 6.915441 |
module {{module_name}} #(
parameter DATA_WIDTH = 32,
parameter WIDTH = 56,
parameter HEIGHT = 56,
parameter CHANNEL_OUT = {{n_kernel}}
)
(
{{port}}
);
// testbench cho mach conv3d_8kernel_3channel
wire [DATA_WIDTH-1:0] conv_out [0: CHANNEL_OUT -1];
wire conv_valid_out;
wire done_conv;
assign valid_out = conv_valid_out;
assign done = done_conv;
// gan output cho block1_conv1-relu-maxpool
// wire [DATA_WIDTH-1:0] relu_out [0: CHANNEL_OUT -1];
// wire [DATA_WIDTH-1:0] data_out_pool [0: CHANNEL_OUT -1];
// wire [CHANNEL_OUT -1 : 0] valid_out_pool;
// wire [CHANNEL_OUT -1 : 0] done_pool;
// assign data_out_0 = data_out_pool[0];
// assign data_out_1 = data_out_pool[1];
// assign data_out_2 = data_out_pool[2];
// assign data_out_3 = data_out_pool[3];
// assign data_out_4 = data_out_pool[4];
// assign data_out_5 = data_out_pool[5];
// assign data_out_6 = data_out_pool[6];
// assign data_out_7 = data_out_pool[7];
// assign valid_out = valid_out_pool[CHANNEL_OUT -1];
// assign done = done_pool[CHANNEL_OUT -1];
// gan output cho block1_conv1
{{instances}}
// genvar i;
// generate
// for (i = 0; i < CHANNEL_OUT; i=i+1)
// begin :initial_relu_and_max_pool // needs CHANNEL_OUT relu
// // FP_Top_AddSub fp_adders(clk,resetn,valid_in_add[i],op_1[i],op_2[i],output_add[i],valid_out_add[i]);
// activate #(
// .DATA_WIDTH(32)
// )
// relu (
// .in(conv_out[i]),
// .out(relu_out[i])
// );
// max_pooling #(
// .DATA_WIDTH(32),
// .WIDTH(WIDTH),
// .HEIGHT(HEIGHT)
// )
// max_pool(
// .clk(clk),
// .resetn(resetn),
// .valid_in(conv_valid_out),
// .data_in(relu_out[i]),
// .data_out(data_out_pool[i]),
// .valid_out(valid_out_pool[i]),
// .done(done_pool[i])
// );
// end
// endgenerate
endmodule
| 7.532924 |
module TempLoader
/*
*/
(
//input clock
input wire MCLK,
//time(sec)
output reg [13:0] TEMPDATA,
//control
input wire nLOAD,
output reg nCOMPLETE,
output reg nCS = 1'b1,
inout wire SIO,
output reg CLK = 1'b0
);
/*
TC77 DATA LOADER
*/
//TC77 fmax = 7MHz, 48MHz / 8 = 6MHz
localparam TEMP_RESET = 4'b0000; //리셋
localparam TEMP_RD_S0 = 4'b0001; //CS내리기
localparam TEMP_RD_S1 = 4'b0010; //CLK 0
localparam TEMP_RD_S2 = 4'b0011; //nop
localparam TEMP_RD_S3 = 4'b0100; //nop
localparam TEMP_RD_S4 = 4'b0101; //nop
localparam TEMP_RD_S5 = 4'b0110; //nop
localparam TEMP_RD_S6 = 4'b0111; //nop
localparam TEMP_RD_S7 = 4'b1000; //nop
localparam TEMP_RD_S8 = 4'b1001; //CLK 1, 데이터 샘플링
localparam TEMP_RD_S9 = 4'b1010; //nop
localparam TEMP_RD_S10 = 4'b1011; //nop
localparam TEMP_RD_S11 = 4'b1100; //nop
localparam TEMP_RD_S12 = 4'b1101; //nop
localparam TEMP_RD_S13 = 4'b1110; //nop, S1로 branch할건지 S13으로 갈건지 결정
localparam TEMP_RD_S14 = 4'b1111; //CS올리기
reg [3:0] spi_state = TEMP_RESET;
reg [3:0] spi_counter = 4'd0;
//branch control
always @(posedge MCLK) begin
case (spi_state)
TEMP_RESET:
case (nLOAD)
1'b0: spi_state <= TEMP_RD_S0;
1'b1: spi_state <= TEMP_RESET;
endcase
TEMP_RD_S0: spi_state <= TEMP_RD_S1;
TEMP_RD_S1: spi_state <= TEMP_RD_S2;
TEMP_RD_S2: spi_state <= TEMP_RD_S3;
TEMP_RD_S3: spi_state <= TEMP_RD_S4;
TEMP_RD_S4: spi_state <= TEMP_RD_S5;
TEMP_RD_S5: spi_state <= TEMP_RD_S6;
TEMP_RD_S6: spi_state <= TEMP_RD_S7;
TEMP_RD_S7: spi_state <= TEMP_RD_S8;
TEMP_RD_S8: spi_state <= TEMP_RD_S9;
TEMP_RD_S9: spi_state <= TEMP_RD_S10;
TEMP_RD_S10: spi_state <= TEMP_RD_S11;
TEMP_RD_S11: spi_state <= TEMP_RD_S12;
TEMP_RD_S12: spi_state <= TEMP_RD_S13;
TEMP_RD_S13:
if (spi_counter < 4'd14) begin
spi_state <= TEMP_RD_S1;
end else begin
spi_state <= TEMP_RD_S14;
end
TEMP_RD_S14: spi_state <= TEMP_RESET;
default: spi_state <= TEMP_RESET;
endcase
end
//output control
always @(posedge MCLK) begin
case (spi_state)
TEMP_RESET: begin
nCOMPLETE <= 1'b1;
nCS <= 1'b1;
CLK <= 1'b0;
spi_counter <= 4'd0;
end
TEMP_RD_S0: begin
nCS <= 1'b0;
CLK <= 1'b0;
end
TEMP_RD_S1: begin
CLK <= 1'b0;
end
TEMP_RD_S2: begin
end //nop
TEMP_RD_S3: begin
end //nop
TEMP_RD_S4: begin
end //nop
TEMP_RD_S5: begin
end //nop
TEMP_RD_S6: begin
end //nop
TEMP_RD_S7: begin
end //nop
TEMP_RD_S8: begin
CLK <= 1'b1;
spi_counter <= spi_counter + 4'd1;
TEMPDATA[13:1] <= TEMPDATA[12:0];
TEMPDATA[0] <= SIO;
end
TEMP_RD_S9: begin
end //nop
TEMP_RD_S10: begin
end //nop
TEMP_RD_S11: begin
end //nop
TEMP_RD_S12: begin
end //nop
TEMP_RD_S13: begin
end //nop
TEMP_RD_S14: begin
nCOMPLETE <= 1'b0;
nCS <= 1'b1;
CLK <= 1'b0;
end
default: begin
nCOMPLETE <= 1'b1;
nCS <= 1'b1;
CLK <= 1'b1;
spi_counter <= 4'd0;
end
endcase
end
endmodule
| 6.54294 |
module tempo #(
parameter BPM = 60,
parameter GENERATE_CLOCK = 1,
)(
input wire clock_in,
output reg clock_out,
output reg whole,
output reg half,
output reg quarter,
output reg eighth,
output reg sixteenth,
output reg thirtysecond,
output reg sixtyfourth,
);
localparam COUNTER_BPM = $rtoi(60.0/((32*BPM)*0.0002));
wire internal_clock;
reg osc_10kz;
// assign internal_clock = (GENERATE_CLOCK == 1) ? osc_10kz : clock_in;
// // assign clock_out = internal_clock;
// if ( GENERATE_CLOCK == 1) begin
SB_LFOSC OSC10KHZ (
.CLKLFEN(1'b1),
.CLKLFPU(1'b1),
.CLKLF(osc_10kz)
);
// end
reg [21:0] counter = 0;
reg [21:0] ref = COUNTER_BPM;
reg [7:0] tempo_counter = 0;
always @( posedge osc_10kz ) begin
if (counter == ref) begin
counter <= 0;
tempo_counter <= tempo_counter + 1;
end else begin
counter <= counter + 1;
end
end
// always @( negedge tempo_counter[0] ) begin
// whole <= (tempo_counter[7:0] == 8'b10000000) ? 1'b1 : 1'b0;
// half <= (tempo_counter[6:0] == 7'b1000000) ? 1'b1 : 1'b0;
// quarter <= tempo_counter[5];
// eighth <= (tempo_counter[4:0] == 5'b10000) ? 1'b1 : 1'b0;
// sixteenth <= (tempo_counter[3:0] == 4'b1000) ? 1'b1 : 1'b0;
// thirtysecond <= (tempo_counter[2:0] == 3'b100) ? 1'b1 : 1'b0;
// sixtyfourth <= (tempo_counter[1:0] == 2'b10) ? 1'b1 : 1'b0;
// end
// assign whole = (tempo_counter[7:0] == 8'b10000000) ? 1'b1 : 1'b0;
// assign half = (tempo_counter[6:0] == 7'b1000000) ? 1'b1 : 1'b0;
assign quarter = tempo_counter[5];
// assign eighth = (tempo_counter[4:0] == 5'b10000) ? 1'b1 : 1'b0;
// assign sixteenth = (tempo_counter[3:0] == 4'b1000) ? 1'b1 : 1'b0;
// assign thirtysecond = (tempo_counter[2:0] == 3'b100) ? 1'b1 : 1'b0;
// assign sixtyfourth = (tempo_counter[1:0] == 2'b10) ? 1'b1 : 1'b0;
endmodule
| 6.778752 |
module TemporaryWord(
input clk,
input start,
input [31:0] e,
input [31:0] f,
input [31:0] g,
input [31:0] h,
input [31:0] const,
input [31:0] word,
input [31:0] a,
input [31:0] b,
input [31:0] c,
output [31:0] outputFirst,
output [31:0] outputSecond,
output [31:0] outputBoth
);
TemporaryWordOne first(clk,start,e,f,g,h,const,word,outputFirst);
TemporaryWordTwo second(clk,start,a,b,c,outputSecond);
assign outputBoth = outputFirst+outputSecond;
endmodule
| 6.551848 |
module TemporaryWordOne(
input clk,
input rst,
input [31:0]e,
input [31:0]f,
input [31:0]g,
input [31:0]h,
input [31:0] const,
input [31:0]word,
output [31:0] outputData
);
wire [31:0] func5Out;
wire [31:0] func4Out;
Function4 rotrE(clk,rst,e,func4Out);
Function5 choice(clk,e,f,g,func5Out);
assign outputData = func4Out+func5Out+h+const+word;
endmodule
| 6.551848 |
module TemporaryWordTwo (
input clk,
input rst,
input [31:0] a,
input [31:0] b,
input [31:0] c,
output [31:0] outputData
);
wire [31:0] func6Output;
wire [31:0] func4Output;
Function3 func3 (
clk,
rst,
a,
func4Output
);
Function6 maj (
rst,
a,
b,
c,
func6Output
);
assign outputData = func4Output + func6Output;
endmodule
| 6.551848 |
module: temporizador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module temporizadorSim;
// Inputs
reg clk_100MHz;
reg [1:0] value;
reg start_timer;
// Outputs
wire t_expired;
wire on;
wire counting;
wire [1:0] counter;
wire clk_1Hz;
wire add_one;
wire add_one_last;
// Instantiate the Unit Under Test (UUT)
temporizador uut (
.clk_100MHz(clk_100MHz),
.value(value),
.start_timer(start_timer),
.t_expired(t_expired),
.on(on),
.counting(counting),
.counter(counter),
.clk_1Hz(clk_1Hz),
.add_one(add_one),
.add_one_last(add_one_last)
);
initial begin
// Initialize Inputs
clk_100MHz = 0;
value = 0;
start_timer = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10 value = 1;
#10 start_timer = 1;
#10 start_timer = 0;
end
always
#1 clk_100MHz = ! clk_100MHz;
endmodule
| 7.383646 |
module TemporizadorTest (
input clk,
input btnl,
input btnd,
input btnr,
input btnp,
input [3:0] speed,
output [7:3] led,
output [6:0] seg,
output [3:0] an
);
wire out;
wire on;
Debouncer started (
.clk(clk),
.signal(btnp),
.signal_state(out)
);
temporizador temp (
.clk_100MHz(clk),
.value(speed[1:0]),
.start_timer(out),
.t_expired(led[7]),
.on(on)
);
clock_divisor clk_1Hz (
.clk_100MHz(clk),
.clk_1Hz(led[6]),
.on(on)
);
endmodule
| 7.722977 |
module: temporizador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module temporizador_test;
// Inputs
reg clk_100MHz;
reg value;
reg start_timer;
// Outputs
wire t_expired;
// Instantiate the Unit Under Test (UUT)
temporizador uut (
.clk_100MHz(clk_100MHz),
.value(value),
.texpired(texpired),
.start_timer(start_timer)
);
initial begin
// Initialize Inputs
clk_100MHz = 0;
value = 0;
start_timer = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#10 start_timer=1 ;
#10 value=1 ;
end
always
#1 clk_100MHz = ! clk_100MHz;
endmodule
| 7.383646 |
module tempo_selector (
input [ 2:0] val,
output [31:0] beat_cycles
);
reg [31:0] cycles;
always @* //NOTE: You are describing combo logic, since there is no clock signal
case (val)
3'b000: cycles = 32'd100000000;
3'b001: cycles = 32'd80000000;
3'b010: cycles = 32'd66666666;
3'b011: cycles = 32'd60000000;
3'b100: cycles = 32'd50000000;
3'b101: cycles = 32'd42857142;
3'b110: cycles = 32'd30000000;
3'b111: cycles = 32'd25000000;
endcase
assign beat_cycles = cycles;
endmodule
| 7.626886 |
module TempReg (
input CLK,
input [31:0] IData,
output reg [31:0] OData
);
initial begin
OData = 0;
end
always @(posedge CLK) begin
OData <= IData;
end
endmodule
| 8.830372 |
module Tempreture (
clk,
rst,
ds,
led,
cs,
key1,
key2,
key3,
key_p,
key_i,
key_d,
static_p1,
static_p2,
work_status,
show_flag_wire,
heater_status,
fan_status,
heater_control,
loopfin
);
input key1, key2, key3, key_p, key_i, key_d;
input rst;
input clk;
inout ds;
output [3:0] cs;
output [7:0] led;
output [7:0] static_p1;
output [7:0] static_p2;
output work_status;
output show_flag_wire;
output heater_status;
output fan_status;
output heater_control;
output loopfin;
wire clk_1ms_wire;
wire clk_1s_wire;
wire clk_1us_wire;
wire [11:0] temp_data;
wire [11:0] data_warn_wire;
wire [2:0] flash_flag_wire;
wire key1_wire;
wire key2_wire;
wire key3_wire;
wire [15:0] mid_point;
wire [6:0] P_PARA;
wire [6:0] I_PARA;
wire [6:0] D_PARA;
wire [1:0] pid_show_wire;
wire pid_lock_wire;
clk_1s U0 (
.clk(clk),
.rst(rst),
.CP (clk_1s_wire)
);
clk_1us U1 (
.clk(clk),
.rst(rst),
.CP (clk_1us_wire) //clk_1us_wire
);
clk_1ms U2 (
.clk(clk),
.rst(rst),
.CP (clk_1ms_wire) //clk_1ms_wire
);
ds18b20_test U3 (
//.nReset(rst),
.clk(clk_1us_wire),
.icdata(ds),
.data(temp_data),
.Flag_CmdSET(loopfin)
);
key_rc U4 (
.clk(clk_1ms_wire),
.key1(key1),
.key2(key2),
.key3(key3),
.key1_out(key1_wire),
.key2_out(key2_wire),
.key3_out(key3_wire)
);
data_change U5 (
.key1_in(key1_wire),
.key2_in(key2_wire),
.key3_in(key3_wire),
.data_warn(data_warn_wire),
.show_flag(show_flag_wire),
.flash_flag(flash_flag_wire)
);
led_show U6 (
.flash_flag(flash_flag_wire),
.show_flag(show_flag_wire),
.clk_1ms(clk_1ms_wire),
.cs(cs),
.data_warn(data_warn_wire),
.data_show(temp_data),
.data(led),
.sta_p1(static_p1),
.sta_p2(static_p2),
.p_data(P_PARA),
.i_data(I_PARA),
.d_data(D_PARA),
.pid_show(pid_show_wire),
.pid_lock(pid_lock_wire)
);
work_unity U7 (
.data_changing(show_flag_wire),
.data_warn(data_warn_wire),
.ds_data(temp_data),
.data_get_complete(loopfin),
.p_para(P_PARA),
.i_para(I_PARA),
.d_para(D_PARA),
.heater_open(heater_status),
.fan_open(fan_status),
.work_c(work_status),
.high_len(mid_point)
);
heatercontrol U8 (
.clk(clk_1us_wire),
.heater_open(heater_status),
.high_len(mid_point),
.heater_con(heater_control)
);
pid_parameter U9 (
.clk(clk_1ms_wire),
.change_p(show_flag_wire),
.k_p(key_p),
.k_i(key_i),
.k_d(key_d),
.p_pa(P_PARA),
.i_pa(I_PARA),
.d_pa(D_PARA),
.pid_show(pid_show_wire)
);
endmodule
| 7.907516 |
module: TemperatureCalculator
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tempretureCalculatorTest;
// Inputs
reg [7:0] factoryBaseTemp;
reg [3:0] factoryTempCoef;
reg [3:0] tempSensorValue;
// Outputs
wire [7:0] temperature;
// Instantiate the Unit Under Test (UUT)
TemperatureCalculator uut (
.factoryBaseTemp(factoryBaseTemp),
.factoryTempCoef(factoryTempCoef),
.tempSensorValue(tempSensorValue),
.temperature(temperature)
);
initial begin
// Initialize Inputs
factoryBaseTemp = 8'b00011110;
factoryTempCoef = 4'b0100;
tempSensorValue = 4'b0010;
// Wait 100 ns for global reset to finish
#100;
factoryBaseTemp = 8'b00100011;
factoryTempCoef = 4'b0100;
tempSensorValue = 4'b0010;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 8.396779 |
module tempsense #(
parameter DAC_RESOLUTION = 6,
parameter COUNTER_BITWIDTH = 12
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire clk,
input wire rst_n,
input wire start_conv_in,
output wire [DAC_RESOLUTION-1:0] vdac_result_out,
output wire [COUNTER_BITWIDTH-1:0] tick_result_out,
output wire conversion_finished_out
);
// Digital core with SAR-algoritm
tempsense_sar_ctrl #(
.DAC_RESOLUTION (DAC_RESOLUTION),
.COUNTER_BITWIDTH(COUNTER_BITWIDTH)
) sar (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.clk(clk),
.rst_n(rst_n),
.start_conv_in(start_conv_in),
.dac_result_out(vdac_result_out),
.ticks_out(tick_result_out),
.conv_finished_out(conversion_finished_out),
.vdac_data_out(dac_data_w),
.vdac_enable_out(dac_enable_w),
.dcdc_dat_out(dcdc_data_w),
.time_trigd_n_in(dcdc_trigd_n_w)
);
// Voltage-mode Digital to Analog Converter (VDAC)
wire [DAC_RESOLUTION-1:0] dac_data_w;
wire dac_enable_w;
wire dcdc_data_w;
wire dcdc_enable_analog_w;
tempsense_vdac #(
.BITWIDTH(DAC_RESOLUTION)
) dac (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.data(dac_data_w),
.enable(dac_enable_w),
.vout_analog(dcdc_enable_analog_w)
);
// Digitally-Controled Delay Cell
wire dcdc_trig_n_analog_w;
wire dcdc_trigd_w;
wire dcdc_trigd_n_w;
sky130_fd_sc_hd__einvp_1 dcdc (
`ifdef USE_POWER_PINS
.VPWR(vccd1),
.VPB(vccd1),
.VNB(vssd1),
.VGND(vssd1),
`endif
.A(dcdc_data_w),
.TE(dcdc_enable_analog_w),
.Z(dcdc_trig_n_analog_w)
);
sky130_fd_sc_hd__inv_4 inv1 (
`ifdef USE_POWER_PINS
.VPWR(vccd1),
.VPB(vccd1),
.VNB(vssd1),
.VGND(vssd1),
`endif
.A(dcdc_trig_n_analog_w),
.Y(dcdc_trigd_w)
);
sky130_fd_sc_hd__inv_12 inv2 (
`ifdef USE_POWER_PINS
.VPWR(vccd1),
.VPB(vccd1),
.VNB(vssd1),
.VGND(vssd1),
`endif
.A(dcdc_trigd_w),
.Y(dcdc_trigd_n_w)
);
endmodule
| 8.085909 |
module tempsense_vdac #(
parameter BITWIDTH = 6
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire [BITWIDTH-1:0] data,
input wire enable,
output wire vout_analog
);
genvar i;
generate
for (i = 0; i < BITWIDTH - 1; i = i + 1) begin : parallel_cells
tempsense_vdac_cell #(
.PARALLEL_CELLS(2 ** i)
) vdac_batch (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.sign(data[BITWIDTH-1]),
.data(data[i]),
.enable(enable),
.vout_analog(vout_analog)
);
end
endgenerate
// Single cell for transition from 011..11 to 100..00
tempsense_vdac_cell #(
.PARALLEL_CELLS(1)
) vdac_single (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.sign(1'b0),
.data(1'b0),
.enable(enable & (~data[BITWIDTH-1])),
.vout_analog(vout_analog)
);
endmodule
| 7.359722 |
module tempsense_vdac_cell #(
parameter PARALLEL_CELLS = 4
) (
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
input wire sign,
input wire data,
input wire enable,
output wire vout_analog
);
wire en_vref, en_pupd, npu_pd;
// Control logic
assign npu_pd = ~data;
assign en_pupd = enable & (~(sign ^ data));
assign en_vref = enable & (sign ^ data);
genvar i;
generate
for (i = 0; i < PARALLEL_CELLS; i = i + 1) begin : einvp_batch
sky130_fd_sc_hd__einvp_1 pupd (
`ifdef USE_POWER_PINS
.VPWR(vccd1),
.VPB(vccd1),
.VNB(vssd1),
.VGND(vssd1),
`endif
.A(npu_pd),
.TE(en_pupd),
.Z(vout_analog)
);
sky130_fd_sc_hd__einvp_1 vref (
`ifdef USE_POWER_PINS
.VPWR(vccd1),
.VPB(vccd1),
.VNB(vssd1),
.VGND(vssd1),
`endif
.A(vout_analog),
.TE(en_vref),
.Z(vout_analog)
);
end
endgenerate
endmodule
| 7.359722 |
module temperature_top (
output [7:0] led_output_o, //iesire pentru aprinderea fiecarui led
output alert_o, //semnalul de alerta(este 1 daca iesirea este aprox in exteriorul 19:26)
input [39:0] sensors_data_i, // val de temperatura
input [4:0] sensors_en_i
); //bit de enable, daca este 1 atunci este pregatit de citire
wire [15:0] temp;
wire [7:0] activesensors;
wire [15:0] q;
wire [15:0] r;
wire [7:0] coded_out;
reg [15:0] activesensors16bit;
integer i;
sensors_input s (
temp,
activesensors,
sensors_data_i,
sensors_en_i
); //instantierea primului modul
always @(*) begin //trecem activesensors pe 16 biti ca sa poata fi utilizat de division
for (i = 0; i <= 15; i = i + 1) begin
activesensors16bit[i] = 0; //il umplem cu 0
end
activesensors16bit = activesensors; //si inscriem valoarea vechiului activesensors
end
division d (
q,
r,
temp,
activesensors16bit
); //instantierea modului de division
output_display o (
led_output_o,
alert_o,
q,
r,
activesensors
); //instantierea modulului de output display
endmodule
| 7.039424 |
module temp_decoder_encoder (
clock,
clock_4x,
reset,
rxtx,
rx_byte,
rx_valid,
tx_bytes,
tx_num_bytes,
tx_valid,
tx_switch
);
parameter MAX_BYTES = 5;
input clock;
input clock_4x;
input reset;
inout rxtx;
input [MAX_BYTES*8-1:0] tx_bytes;
input [3:0] tx_num_bytes;
input tx_valid;
output reg [7:0] rx_byte;
output reg rx_valid;
output reg tx_switch;
reg [9:0] incoming_data;
reg [3:0] rx_count;
reg [1:0] rx_reg;
wire rx;
reg tx;
assign rx = (tx_switch) ? 1'b1 : rxtx;
assign rxtx = (tx_switch) ? tx : 1'bz;
always @(posedge clock or posedge reset) begin
if (reset) begin
rx_reg <= 2'b00;
rx_byte <= 8'h00;
rx_valid <= 1'b0;
incoming_data <= 10'h000;
rx_count <= 4'h0;
end else begin
rx_reg <= {rx_reg[0], rx};
incoming_data[9:0] <= {rx_reg[0], incoming_data[9:1]};
if ((incoming_data[9] == 1'b0) && (incoming_data[8] == 1'b1) && (rx_count == 0)) begin
rx_count <= 1;
rx_valid <= 1'b0;
end else if (rx_count == 9) begin
rx_count <= 0;
rx_byte <= incoming_data[8:1];
rx_valid <= 1'b1;
end else if (rx_count > 0) begin
rx_count <= rx_count + 1;
rx_valid <= 1'b0;
end else rx_valid <= 0;
end
end
reg [ 9:0] outgoing_data;
reg [ 3:0] tx_count;
reg [MAX_BYTES*8-1:0] tx_bytes_reg;
reg [ 3:0] tx_byte_count;
reg tx_start;
always @(posedge clock or posedge reset) begin
if (reset) begin
tx <= 1'b1;
outgoing_data <= 10'h3FF;
tx_count <= 4'h0;
tx_bytes_reg <= 0;
tx_byte_count <= 0;
tx_start <= 0;
tx_switch <= 1'b0;
end else begin
tx <= outgoing_data[0];
if ((tx_count == 0) && (tx_start == 0)) begin
if ((tx_valid == 1) && (tx_byte_count == 0)) begin
tx_bytes_reg <= tx_bytes;
tx_start <= 1;
tx_byte_count <= 1;
end else if (tx_byte_count == tx_num_bytes) begin
tx_byte_count <= 0;
tx_start <= 0;
end else if (tx_byte_count > 0) begin
tx_bytes_reg[MAX_BYTES*8-1:0] <= {tx_bytes_reg[(MAX_BYTES-1)*8-1:0], 8'hFF};
tx_start <= 1;
tx_byte_count <= tx_byte_count + 1;
end else tx_start <= 0;
end else tx_start <= 0;
if ((tx_start == 1'b1) && (tx_count == 0)) begin
outgoing_data <= {1'b1, tx_bytes_reg[MAX_BYTES*8-1:(MAX_BYTES-1)*8], 1'b0};
tx_count <= 1;
tx_switch <= 1'b1;
end else if (tx_count == 10) begin
outgoing_data <= 10'h3FF;
tx_count <= 0;
tx_switch <= 1'b0;
end else if (tx_count > 0) begin
outgoing_data <= {1'b1, outgoing_data[9:1]};
tx_count <= tx_count + 1;
tx_switch <= 1'b1;
end
end
end
endmodule
| 6.67617 |
module temp_demo (
input wire clk_in,
input wire rst_n,
inout wire dq,
output wire [4:0] temp
);
wire clk;
//clk_div
clk_div clk_div_inst (
.clk_in (clk_in),
.rst_n (rst_n),
.clk_out(clk)
);
//temp_rd
temp_rd temp_rd_inst (
.clk_in(clk), //1.024M
.rst_n(rst_n),
.dq(dq), //单总线
.temp(temp) //温度值，单位℃
);
endmodule
| 7.076962 |
module HPR_HEAPMANGER_T0 (
input clk,
input reset,
output reg [63:0] RESULT,
input [63:0] SIZE_IN_BYTES,
input REQ,
output reg ACK,
output reg FAIL
);
reg [32:0] base;
always @(posedge clk)
if (reset) begin
ACK <= 0;
FAIL <= 0;
base <= 4096; // Do not start at zero, since null must be reserved.
RESULT <= 1;
end else begin
ACK <= REQ;
if (REQ) begin
RESULT <= base;
$display("%1t, %m: Alloc at %1d at 0x%1h", $time, SIZE_IN_BYTES, base);
base <= base + ((SIZE_IN_BYTES + 7) / 8) * 8;
end
end
endmodule
| 6.619502 |
module temp_read_driver (
input clk, // 100 MHz clock
input rst, // Asynchronous reset, tied to dip switch 0
output reg iocs, // chip select
output reg read,
input rda, // received data available
input [ 7:0] data_in,
input [ 1:0] addr,
output [15:0] data_out,
output reg dav
);
reg [7:0] first_status, second_status, next_first_status, next_second_status;
reg [7:0] first_x_loc, second_x_loc, next_first_x_loc, next_second_x_loc;
reg [7:0] first_y_loc, second_y_loc, next_first_y_loc, next_second_y_loc;
reg [2:0] state, next_state; // state and next state
reg next_dav;
// state variables
localparam WAIT_STATUS_1 = 3'h0;
localparam WAIT_STATUS_2 = 3'h1;
localparam WAIT_X_1 = 3'h2;
localparam WAIT_X_2 = 3'h3;
localparam WAIT_Y_1 = 3'h4;
localparam WAIT_Y_2 = 3'h5;
assign data_out = (addr == 2'b00) ? {first_status, second_status} :
(addr == 2'b01) ? {first_x_loc, second_x_loc} :
(addr == 2'b10) ? {first_y_loc, second_y_loc} : 16'd0;
// sequential logic
always @(posedge clk, posedge rst) begin
if (rst) begin
state <= WAIT_STATUS_1;
first_status <= 8'd0;
second_status <= 8'd0;
first_x_loc <= 8'd0;
second_x_loc <= 8'd0;
first_y_loc <= 8'd0;
second_y_loc <= 8'd0;
end else begin
state <= next_state;
first_status <= next_first_status;
second_status <= next_second_status;
first_x_loc <= next_first_x_loc;
second_x_loc <= next_second_x_loc;
first_y_loc <= next_first_y_loc;
second_y_loc <= next_second_y_loc;
dav <= next_dav;
end
end
// next state and combinational logic
// determine next state and output signals
always @(*) begin
iocs = 1'b1;
next_state = state;
next_first_status = first_status;
next_second_status = second_status;
next_first_x_loc = first_x_loc;
next_second_x_loc = second_x_loc;
next_first_y_loc = first_y_loc;
next_second_y_loc = second_y_loc;
read = 1'b0;
next_dav = 1'b0;
case (state)
WAIT_STATUS_1: begin
iocs = 1'b1;
if (rda) begin
read = 1'b1;
next_first_status = data_in;
next_state = WAIT_STATUS_2;
end else begin
next_state = WAIT_STATUS_1;
end
end
WAIT_STATUS_2: begin
iocs = 1'b1;
if (rda) begin
read = 1'b1;
next_second_status = data_in;
next_state = WAIT_X_1;
end else begin
next_state = WAIT_STATUS_2;
end
end
WAIT_X_1: begin
iocs = 1'b1;
if (rda) begin
read = 1'b1;
next_first_x_loc = data_in;
next_state = WAIT_X_2;
end else begin
next_state = WAIT_X_1;
end
end
WAIT_X_2: begin
iocs = 1'b1;
if (rda) begin
read = 1'b1;
next_second_x_loc = data_in;
next_state = WAIT_Y_1;
end else begin
next_state = WAIT_X_2;
end
end
WAIT_Y_1: begin
iocs = 1'b1;
if (rda) begin
read = 1'b1;
next_first_y_loc = data_in;
next_state = WAIT_Y_2;
end else begin
next_state = WAIT_Y_1;
end
end
WAIT_Y_2: begin
iocs = 1'b1;
if (rda) begin
read = 1'b1;
next_second_y_loc = data_in;
next_state = WAIT_STATUS_1;
end else begin
next_state = WAIT_Y_2;
end
end
endcase
end
endmodule
| 7.688327 |
module temp_register (
input clk,
reset_n,
load,
increment,
decrement,
input [7:0] data,
output negative,
positive,
zero
);
endmodule
| 7.226009 |
module Temp_Reg_A (
input clk,
input [31:0] data_in,
output reg [31:0] data_out
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 7.133229 |
module Temp_Reg_ALU (
input clk,
input [31:0] data_in,
output reg [31:0] data_out
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 7.525206 |
module Temp_Reg_B (
input clk,
input [31:0] data_in,
output reg [31:0] data_out
);
always @(posedge clk) begin
data_out <= data_in;
end
endmodule
| 7.162564 |
module Temp_Reg_DM (
input clk,
input lb_sign,
input [31:0] data_in,
output reg [31:0] data_out
);
reg lb_pos;
always @(posedge clk) begin
if (!lb_sign) data_out <= data_in;
else data_out <= {{24{data_in[7]}}, data_in[7:0]};
end
endmodule
| 7.577336 |
module temp_result_calc (
clk,
rst,
ldresult,
one_bit_mult_x,
powercnt,
init_result,
temp_result
);
input clk, rst, init_result, ldresult;
input [11:0] one_bit_mult_x;
input [5:0] powercnt;
output reg [11:0] temp_result;
always @(posedge clk, posedge rst) begin
if (rst) temp_result <= 12'b0;
else if (init_result) temp_result <= 12'b0;
else if (ldresult) begin
$display("%d%d%d%d", one_bit_mult_x * powercnt, one_bit_mult_x, powercnt, temp_result);
temp_result <= (temp_result + (one_bit_mult_x * powercnt));
end
end
endmodule
| 6.545635 |
module temp_sense (
input clk,
arst, // < 80 MHz
output reg [7:0] degrees_c,
output reg [7:0] degrees_f,
output reg [11:0] degrees_f_bcd,
output reg fresh_sample,
failed_sample
);
parameter OFFSET_DEGREES = 8'd133;
/////////////////////////////////////
// slow down the clock by 2 for the TSD block
/////////////////////////////////////
reg half_clk;
always @(posedge clk or posedge arst) begin
if (arst) begin
half_clk <= 1'b0;
end else begin
half_clk <= ~half_clk;
end
end
/////////////////////////////////////
// temp sense block
/////////////////////////////////////
reg tsd_clr;
wire [7:0] tsd_out;
wire tsd_done;
stratixiv_tsdblock tsd (
.clk(half_clk),
.ce(1'b1),
.clr(tsd_clr),
.tsdcalo(tsd_out),
.tsdcaldone(tsd_done)
// Temp sense is still kind of an "engineering only"
// feature - the sim model appears to be a little out of sync.
//
// synthesis translate off
, .offset(),
.testin(),
.fdbkctrlfromcore(),
.compouttest(),
.tsdcompout(),
.offsetout()
// synthesis translate on
);
/////////////////////////////////////
// sampling schedule
/////////////////////////////////////
reg [19:0] timer;
reg timer_max;
reg [7:0] raw_degrees_c;
always @(posedge clk or posedge arst) begin
if (arst) begin
timer <= 0;
timer_max <= 1'b0;
fresh_sample <= 1'b0;
failed_sample <= 1'b0;
raw_degrees_c <= 0;
end else begin
fresh_sample <= 1'b0;
failed_sample <= 1'b0;
timer_max <= (timer == 20'hffffe);
tsd_clr <= (timer[19:4] == 16'h0000);
if (timer_max) timer <= 0;
else timer <= timer + 1'b1;
if (timer_max) begin
if (tsd_done) begin
raw_degrees_c <= tsd_out;
fresh_sample <= 1'b1;
end else failed_sample <= 1'b1;
end
degrees_c <= raw_degrees_c - OFFSET_DEGREES;
end
end
wire [8:0] degc_x2 = {degrees_c, 1'b0};
wire [8:0] degc_x14 = {2'b0, degrees_c[7:2]};
always @(posedge clk or posedge arst) begin
if (arst) begin
degrees_f <= 0;
end else begin
// rough C to F convert
degrees_f <= degc_x2 - degc_x14 + 9'd32;
end
end
localparam ST_START = 2'h0, ST_HUND = 2'h1, ST_TENS = 2'h2, ST_ONES = 2'h3;
reg [1:0] bcd_state /* synthesis preserve */;
reg [7:0] working;
reg [3:0] working_hund, working_tens;
always @(posedge clk or posedge arst) begin
if (arst) begin
degrees_f_bcd <= 0;
bcd_state <= ST_START;
end else begin
case (bcd_state)
ST_START: begin
working <= degrees_f;
working_hund <= 0;
working_tens <= 0;
bcd_state <= ST_HUND;
end
ST_HUND: begin
if (working >= 8'd100) begin
working <= working - 8'd100;
working_hund <= working_hund + 1'b1;
end else bcd_state <= ST_TENS;
end
ST_TENS: begin
if (working >= 8'd10) begin
working <= working - 8'd10;
working_tens <= working_tens + 1'b1;
end else bcd_state <= ST_ONES;
end
ST_ONES: begin
degrees_f_bcd <= {working_hund, working_tens, working[3:0]};
bcd_state <= ST_START;
end
endcase
end
end
endmodule
| 8.244752 |
module temp_sense_s5 (
input clk, // ~50-100 MHz
output reg [7:0] degrees_c,
output reg [7:0] degrees_f
);
//////////////////////////////////////////////
wire [7:0] tsd_out;
wire tsd_done;
reg tsd_clr = 1'b0;
reg tsd_clr_inv = 1'b0 /* synthesis preserve */;
wire tsd_clk;
reg tsd_ce = 1'b0 /* synthesis preserve */;
reg [7:0] raw_c = 8'd133;
// little clock divider
reg [11:0]
tsd_cntr = 0 /* synthesis preserve */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"create_clock -name {temp_sense_clock} -period 40.0 [get_keepers {*temp_sense*tsd_cntr\[11\]}]\" " */;
assign tsd_clk = tsd_cntr[11];
always @(posedge clk) tsd_cntr <= tsd_cntr + 1'b1;
reg [7:0] tsd_sched = 0 /* synthesis preserve */;
always @(posedge tsd_clk) begin
tsd_sched <= tsd_sched + 1'b1;
tsd_clr <= (tsd_sched == 8'h01) ^ tsd_clr_inv;
if (&tsd_sched) begin
if (tsd_done && (~&tsd_out)) begin
raw_c <= tsd_out ^ {1'b0, tsd_out[7:1]}; // grey code for crossing
end else begin
// sampling error - call it very cold
raw_c <= 8'd133;
// muck with the control polarity - it is programmable
// and not super clear in the docs
{tsd_ce, tsd_clr_inv} <= {tsd_ce, tsd_clr_inv} + 1'b1;
end
end
end
// WYS connection to sense diode ADC
stratixv_tsdblock tsd (
.clk(tsd_clk),
.ce(tsd_ce),
.clr(tsd_clr),
.tsdcalo(tsd_out),
.tsdcaldone(tsd_done)
);
// this is ridiculous overkill, but better safe than unstable
reg [7:0]
raw_c_meta = 8'h0 /* synthesis preserve */
/* synthesis ALTERA_ATTRIBUTE = "-name SDC_STATEMENT \"set_false_path -to [get_keepers {*temp_sense*raw_c_meta\[*\]}]\" " */;
reg [7:0] raw_c_sync = 8'h0 /* synthesis preserve */;
always @(posedge clk) begin
raw_c_meta <= raw_c;
raw_c_sync <= raw_c_meta;
end
// convert back to decimal
reg [7:0] raw_c_dec = 0;
genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin : gry
always @(posedge clk) begin
raw_c_dec[i] <= ^raw_c_sync[7:i];
end
end
endgenerate
// convert valid samples to better format
initial degrees_c = 0;
initial degrees_f = 0;
always @(posedge clk) begin
degrees_c <= raw_c_dec - 8'd133; // offset
// F = C * 1.8 + 32
// rounding off the fraction a little bit
degrees_f <= {degrees_c, 1'b0} - {2'b0, degrees_c[7:2]} + {4'b0, degrees_c[7:4]} + 8'd32;
end
endmodule
| 7.32193 |
module temp_test (
input wire [31:0] test,
output reg [31:0] boop
);
always @(*) begin
boop = test;
end
endmodule
| 6.623247 |
module JK (
clk,
j,
k,
q,
qn
);
input clk, j, k;
output q, qn;
reg q;
wire qn;
always @(posedge clk) begin
case ({
j, k
})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
default: q <= q;
endcase
end
assign qn = ~q;
endmodule
| 6.897092 |
module TENBASET_TxD (
clk20,
SendingPacket,
pkt_data,
rdaddress,
ShiftData,
ShiftCount,
CRCflush,
CRC,
readram,
Ethernet_TDp,
Ethernet_TDm
);
input clk20; // a 20MHz clock (this code won't work with a different frequency)
input [7:0] pkt_data;
output [10:0] rdaddress;
input SendingPacket;
output ShiftData;
output [3:0] ShiftCount;
input CRCflush;
input CRC;
output readram;
output Ethernet_TDp, Ethernet_TDm; // the two differential 10BASE-T outputs
reg [10:0] rdaddress = 0;
reg [3:0] ShiftCount = 0;
wire readram = (ShiftCount == 15);
reg [7:0] ShiftData = 0;
reg [17:0] LinkPulseCount = 0;
reg LinkPulse = 0;
reg SendingPacketData = 0;
reg [2:0] idlecount = 0;
reg qo = 0;
reg qoe = 0;
reg Ethernet_TDp = 0;
reg Ethernet_TDm = 0;
//////////////////////////////////////////////////////////////////////
// 10BASE-T's magic
always @(posedge clk20) begin
ShiftCount <= SendingPacket ? ShiftCount + 1 : 15;
if (ShiftCount == 15) rdaddress <= SendingPacket ? rdaddress + 1 : 0;
if (ShiftCount[0]) ShiftData <= readram ? pkt_data : {1'b0, ShiftData[7:1]};
end
// generate the NLP
always @(posedge clk20) begin
LinkPulseCount <= SendingPacket ? 0 : LinkPulseCount + 1;
LinkPulse <= &LinkPulseCount[17:1];
end
wire dataout = CRCflush ? CRC : ShiftData[0];
// TP_IDL, shift-register and manchester encoder
always @(posedge clk20) begin
SendingPacketData <= SendingPacket;
if (SendingPacketData) idlecount <= 0;
else if (~&idlecount) idlecount <= idlecount + 1;
qo <= SendingPacketData ? ~dataout ^ ShiftCount[0] : 1;
qoe <= SendingPacketData | LinkPulse | (idlecount < 6);
Ethernet_TDp <= (qoe ? qo : 1'b0);
Ethernet_TDm <= (qoe ? ~qo : 1'b0);
end
endmodule
| 7.086672 |
module TensorReg ( // tensor register , read data from it on negedge, send data to it on posedge
input iClk,
input ena, // high volt active , enable signal
input wEna, // high volt active, write enable signal
input [4:0] addrIn,
input [255:0] dataIn,
output reg [255:0] dataOut
);
reg [255:0] memories[31:0];
always @(posedge iClk) begin
if (ena) begin // active
if (wEna) begin
dataOut = memories[addrIn];
end else begin
memories[addrIn] = dataIn;
end
end else dataOut = {255{1'bz}};
end
endmodule
| 6.663223 |
module FPAddSub_single_32 (
clk,
rst,
a,
b,
operation,
result,
flags
);
// Clock and reset
input clk; // Clock signal
input rst; // Reset (active high, resets pipeline registers)
// Input ports
input [31:0] a; // Input A, a 32-bit floating point number
input [31:0] b; // Input B, a 32-bit floating point number
input operation; // Operation select signal
// Output ports
output [31:0] result; // Result of the operation
output [4:0] flags; // Flags indicating exceptions according to IEEE754
reg [68:0] pipe_1;
reg [54:0] pipe_2;
reg [45:0] pipe_3;
//internal module wires
//output ports
wire Opout;
wire Sa;
wire Sb;
wire MaxAB;
wire [ 7:0] CExp;
wire [ 4:0] Shift;
wire [22:0] Mmax;
wire [ 4:0] InputExc;
wire [23:0] Mmin_3;
wire [32:0] SumS_5;
wire [ 4:0] Shift_1;
wire PSgn;
wire Opr;
wire [22:0] NormM; // Normalized mantissa
wire [ 8:0] NormE; // Adjusted exponent
wire ZeroSum; // Zero flag
wire NegE; // Flag indicating negative exponent
wire R; // Round bit
wire S; // Final sticky bit
wire FG;
FPAddSub_a_32 M1 (
a,
b,
operation,
Opout,
Sa,
Sb,
MaxAB,
CExp,
Shift,
Mmax,
InputExc,
Mmin_3
);
FpAddSub_b_32 M2 (
pipe_1[51:29],
pipe_1[23:0],
pipe_1[67],
pipe_1[66],
pipe_1[65],
pipe_1[68],
SumS_5,
Shift_1,
PSgn,
Opr
);
FPAddSub_c_32 M3 (
pipe_2[54:22],
pipe_2[21:17],
pipe_2[16:9],
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
FPAddSub_d_32 M4 (
pipe_3[13],
pipe_3[22:14],
pipe_3[45:23],
pipe_3[11],
pipe_3[10],
pipe_3[9],
pipe_3[8],
pipe_3[7],
pipe_3[6],
pipe_3[5],
pipe_3[12],
pipe_3[4:0],
result,
flags
);
always @(posedge clk) begin
if (rst) begin
pipe_1 <= 0;
pipe_2 <= 0;
pipe_3 <= 0;
end else begin
/*
pipe_1:
[68] Opout;
[67] Sa;
[66] Sb;
[65] MaxAB;
[64:57] CExp;
[56:52] Shift;
[51:29] Mmax;
[28:24] InputExc;
[23:0] Mmin_3;
*/
pipe_1 <= {Opout, Sa, Sb, MaxAB, CExp, Shift, Mmax, InputExc, Mmin_3};
/*
pipe_2:
[54:22]SumS_5;
[21:17]Shift;
[16:9]CExp;
[8]Sa;
[7]Sb;
[6]operation;
[5]MaxAB;
[4:0]InputExc
*/
pipe_2 <= {
SumS_5,
Shift_1,
pipe_1[64:57],
pipe_1[67],
pipe_1[66],
pipe_1[68],
pipe_1[65],
pipe_1[28:24]
};
/*
pipe_3:
[45:23] NormM ;
[22:14] NormE ;
[13]ZeroSum ;
[12]NegE ;
[11]R ;
[10]S ;
[9]FG ;
[8]Sa;
[7]Sb;
[6]operation;
[5]MaxAB;
[4:0]InputExc
*/
pipe_3 <= {
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG,
pipe_2[8],
pipe_2[7],
pipe_2[6],
pipe_2[5],
pipe_2[4:0]
};
end
end
endmodule
| 6.626859 |
module FpAddSub_b_32 (
Mmax,
Mmin,
Sa,
Sb,
MaxAB,
OpMode,
SumS_5,
Shift,
PSgn,
Opr
);
input [22:0] Mmax; // The larger mantissa
input [23:0] Mmin; // The smaller mantissa
input Sa; // Sign bit of larger number
input Sb; // Sign bit of smaller number
input MaxAB; // Indicates the larger number (0/A, 1/B)
input OpMode; // Operation to be performed (0/Add, 1/Sub)
// Output ports
wire [32:0] Sum;
// Output ports
output [32:0] SumS_5; // Mantissa after 16|0 shift
output [4:0] Shift; // Shift amount // The result of the operation
output PSgn; // The sign for the result
output Opr; // The effective (performed) operation
assign Opr = (OpMode ^ Sa ^ Sb); // Resolve sign to determine operation
// Perform effective operation
assign Sum = (OpMode^Sa^Sb) ? ({1'b1, Mmax, 8'b00000000} - {Mmin, 8'b00000000}) : ({1'b1, Mmax, 8'b00000000} + {Mmin, 8'b00000000}) ;
// Assign result sign
assign PSgn = (MaxAB ? Sb : Sa);
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Determine normalization shift amount by finding leading nought
assign Shift = (
Sum[32] ? 5'b00000 :
Sum[31] ? 5'b00001 :
Sum[30] ? 5'b00010 :
Sum[29] ? 5'b00011 :
Sum[28] ? 5'b00100 :
Sum[27] ? 5'b00101 :
Sum[26] ? 5'b00110 :
Sum[25] ? 5'b00111 :
Sum[24] ? 5'b01000 :
Sum[23] ? 5'b01001 :
Sum[22] ? 5'b01010 :
Sum[21] ? 5'b01011 :
Sum[20] ? 5'b01100 :
Sum[19] ? 5'b01101 :
Sum[18] ? 5'b01110 :
Sum[17] ? 5'b01111 :
Sum[16] ? 5'b10000 :
Sum[15] ? 5'b10001 :
Sum[14] ? 5'b10010 :
Sum[13] ? 5'b10011 :
Sum[12] ? 5'b10100 :
Sum[11] ? 5'b10101 :
Sum[10] ? 5'b10110 :
Sum[9] ? 5'b10111 :
Sum[8] ? 5'b11000 :
Sum[7] ? 5'b11001 : 5'b11010
);
reg [32:0] Lvl1;
always @(*) begin
// Rotate by 16?
Lvl1 <= Shift[4] ? {Sum[16:0], 16'b0000000000000000} : Sum;
end
// Assign outputs
assign SumS_5 = Lvl1;
endmodule
| 6.675503 |
module FPAddSub_c_32 (
SumS_5,
Shift,
CExp,
NormM,
NormE,
ZeroSum,
NegE,
R,
S,
FG
);
// Input ports
input [32:0] SumS_5; // Smaller mantissa after 16|12|8|4 shift
input [4:0] Shift; // Shift amount
// Input ports
input [7:0] CExp;
// Output ports
output [22:0] NormM; // Normalized mantissa
output [8:0] NormE; // Adjusted exponent
output ZeroSum; // Zero flag
output NegE; // Flag indicating negative exponent
output R; // Round bit
output S; // Final sticky bit
output FG;
wire [3:0] Shift_1;
assign Shift_1 = Shift[3:0];
// Output ports
wire [32:0] SumS_7; // The smaller mantissa
reg [32:0] Lvl2;
wire [65:0] Stage1;
reg [32:0] Lvl3;
wire [65:0] Stage2;
integer i; // Loop variable
assign Stage1 = {SumS_5, SumS_5};
always @(*) begin // Rotate {0 | 4 | 8 | 12} bits
case (Shift[3:2])
// Rotate by 0
2'b00: Lvl2 <= Stage1[32:0];
// Rotate by 4
2'b01: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-4];
end
Lvl2[3:0] <= 0;
end
// Rotate by 8
2'b10: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-8];
end
Lvl2[7:0] <= 0;
end
// Rotate by 12
2'b11: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl2[i-33] <= Stage1[i-12];
end
Lvl2[11:0] <= 0;
end
endcase
end
assign Stage2 = {Lvl2, Lvl2};
always @(*) begin // Rotate {0 | 1 | 2 | 3} bits
case (Shift_1[1:0])
// Rotate by 0
2'b00: Lvl3 <= Stage2[32:0];
// Rotate by 1
2'b01: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl3[i-33] <= Stage2[i-1];
end
Lvl3[0] <= 0;
end
// Rotate by 2
2'b10: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl3[i-33] <= Stage2[i-2];
end
Lvl3[1:0] <= 0;
end
// Rotate by 3
2'b11: begin
for (i = 65; i >= 33; i = i - 1) begin
Lvl3[i-33] <= Stage2[i-3];
end
Lvl3[2:0] <= 0;
end
endcase
end
// Assign outputs
assign SumS_7 = Lvl3; // Take out smaller mantissa
// Internal signals
wire MSBShift; // Flag indicating that a second shift is needed
wire [8:0] ExpOF; // MSB set in sum indicates overflow
wire [8:0] ExpOK; // MSB not set, no adjustment
// Calculate normalized exponent and mantissa, check for all-zero sum
assign MSBShift = SumS_7[32]; // Check MSB in unnormalized sum
assign ZeroSum = ~|SumS_7; // Check for all zero sum
assign ExpOK = CExp - Shift; // Adjust exponent for new normalized mantissa
assign NegE = ExpOK[8]; // Check for exponent overflow
assign ExpOF = CExp - Shift + 1'b1; // If MSB set, add one to exponent(x2)
assign NormE = MSBShift ? ExpOF : ExpOK; // Check for exponent overflow
assign NormM = SumS_7[31:9]; // The new, normalized mantissa
// Also need to compute sticky and round bits for the rounding stage
assign FG = SumS_7[8];
assign R = SumS_7[7];
assign S = |SumS_7[6:0];
endmodule
| 6.891648 |
module FPAddSub_d_32 (
ZeroSum,
NormE,
NormM,
R,
S,
G,
Sa,
Sb,
Ctrl,
MaxAB,
NegE,
InputExc,
P,
Flags
);
// Input ports
input ZeroSum; // Sum is zero
input [8:0] NormE; // Normalized exponent
input [22:0] NormM; // Normalized mantissa
input R; // Round bit
input S; // Sticky bit
input G;
input Sa; // A's sign bit
input Sb; // B's sign bit
input Ctrl; // Control bit (operation)
input MaxAB;
input NegE; // Negative exponent?
input [4:0] InputExc; // Exceptions in inputs A and B
// Output ports
output [31:0] P; // Final result
output [4:0] Flags; // Exception flags
//
wire [31:0] Z; // Final result
wire EOF;
// Internal signals
wire [23:0] RoundUpM; // Rounded up sum with room for overflow
wire [22:0] RoundM; // The final rounded sum
wire [ 8:0] RoundE; // Rounded exponent (note extra bit due to poential overflow )
wire RoundUp; // Flag indicating that the sum should be rounded up
wire ExpAdd; // May have to add 1 to compensate for overflow
wire RoundOF; // Rounding overflow
wire FSgn;
// The cases where we need to round upwards (= adding one) in Round to nearest, tie to even
assign RoundUp = (G & ((R | S) | NormM[0]));
// Note that in the other cases (rounding down), the sum is already 'rounded'
assign RoundUpM = (NormM + 1); // The sum, rounded up by 1
assign RoundM = (RoundUp ? RoundUpM[22:0] : NormM); // Compute final mantissa
assign RoundOF = RoundUp & RoundUpM[23]; // Check for overflow when rounding up
// Calculate post-rounding exponent
assign ExpAdd = (RoundOF ? 1'b1 : 1'b0); // Add 1 to exponent to compensate for overflow
assign RoundE = ZeroSum ? 8'b00000000 : (NormE + ExpAdd); // Final exponent
// If zero, need to determine sign according to rounding
assign FSgn = (ZeroSum & (Sa ^ Sb)) | (ZeroSum ? (Sa & Sb & ~Ctrl) : ((~MaxAB & Sa) | ((Ctrl ^ Sb) & (MaxAB | Sa)))) ;
// Assign final result
assign Z = {FSgn, RoundE[7:0], RoundM[22:0]};
// Indicate exponent overflow
assign EOF = RoundE[8];
/////////////////////////////////////////////////////////////////////////////////////////////////////////
// Internal signals
wire Overflow; // Overflow flag
wire Underflow; // Underflow flag
wire DivideByZero; // Divide-by-Zero flag (always 0 in Add/Sub)
wire Invalid; // Invalid inputs or result
wire Inexact; // Result is inexact because of rounding
// Exception flags
// Result is too big to be represented
assign Overflow = EOF | InputExc[1] | InputExc[0];
// Result is too small to be represented
assign Underflow = NegE & (R | S);
// Infinite result computed exactly from finite operands
assign DivideByZero = &(Z[30:23]) & ~|(Z[30:23]) & ~InputExc[1] & ~InputExc[0];
// Invalid inputs or operation
assign Invalid = |(InputExc[4:2]);
// Inexact answer due to rounding, overflow or underflow
assign Inexact = (R | S) | Overflow | Underflow;
// Put pieces together to form final result
assign P = Z;
// Collect exception flags
assign Flags = {Overflow, Underflow, DivideByZero, Invalid, Inexact};
endmodule
| 7.959097 |
module FPMult_PrepModule (
clk,
rst,
a,
b,
Sa,
Sb,
Ea,
Eb,
Mp,
InputExc
);
// Input ports
input clk;
input rst;
input [16-1:0] a; // Input A, a 32-bit floating point number
input [16-1:0] b; // Input B, a 32-bit floating point number
// Output ports
output Sa; // A's sign
output Sb; // B's sign
output [8-1:0] Ea; // A's exponent
output [8-1:0] Eb; // B's exponent
output [2*7+1:0] Mp; // 7 product
output [4:0] InputExc; // Input numbers are exceptions
// Internal signals // If signal is high...
wire ANaN; // A is a signalling NaN
wire BNaN; // B is a signalling NaN
wire AInf; // A is infinity
wire BInf; // B is infinity
wire [7-1:0] Ma;
wire [7-1:0] Mb;
assign ANaN = &(a[16-2:7]) & |(a[16-2:7]); // All one 8and not all zero 7 - NaN
assign BNaN = &(b[16-2:7]) & |(b[7-1:0]); // All one 8and not all zero 7 - NaN
assign AInf = &(a[16-2:7]) & ~|(a[16-2:7]); // All one 8and all zero 7 - Infinity
assign BInf = &(b[16-2:7]) & ~|(b[16-2:7]); // All one 8and all zero 7 - Infinity
// Check for any exceptions and put all flags into exception vector
assign InputExc = {(ANaN | BNaN | AInf | BInf), ANaN, BNaN, AInf, BInf};
//assign InputExc = {(ANaN | ANaN | BNaN |BNaN), ANaN, ANaN, BNaN,BNaN} ;
// Take input numbers apart
assign Sa = a[16-1]; // A's sign
assign Sb = b[16-1]; // B's sign
assign Ea = a[16-2:7]; // Store A's 8in Ea, unless A is an exception
assign Eb = b[16-2:7]; // Store B's 8in Eb, unless B is an exception
// assign Ma = a[7_MSB:7_LSB];
// assign Mb = b[7_MSB:7_LSB];
// Actual 7 multiplication occurs here
//assign Mp = ({4'b0001, a[7-1:0]}*{4'b0001, b[7-1:9]}) ;
assign Mp = ({1'b1, a[7-1:0]} * {1'b1, b[7-1:0]});
//We multiply part of the 7 here
//Full 7 of A
//Bits 7_MUL_SPLIT_MSB:7_MUL_SPLIT_LSB of B
// wire [`ACTUAL_7-1:0] inp_A;
// wire [`ACTUAL_7-1:0] inp_B;
// assign inp_A = {1'b1, Ma};
// assign inp_B = {{(7-(7_MUL_SPLIT_MSB-7_MUL_SPLIT_LSB+1)){1'b0}}, 1'b1, Mb[7_MUL_SPLIT_MSB:7_MUL_SPLIT_LSB]};
// DW02_mult #(`ACTUAL_7,`ACTUAL_7) u_mult(.A(inp_A), .B(inp_B), .TC(1'b0), .PRODUCT(Mp));
endmodule
| 7.427166 |
module FPMult_NormalizeModule (
NormM,
NormE,
RoundE,
RoundEP,
RoundM,
RoundMP
);
// Input Ports
input [23-1:0] NormM; // Normalized 7
input [8:0] NormE; // Normalized exponent
// Output Ports
output [8:0] RoundE;
output [8:0] RoundEP;
output [23:0] RoundM;
output [23:0] RoundMP;
// 8= 5
// 8-1 = 4
// NEED to subtract 2^4 -1 = 15
//wire [8-1 : 0] bias;
//assign bias = ((1<< (8-1)) -1);
assign RoundE = NormE - 9'd127;
assign RoundEP = NormE - 9'd127 - 1;
assign RoundM = NormM;
assign RoundMP = NormM;
endmodule
| 7.947312 |
module FPMult_RoundModule (
RoundM,
RoundMP,
RoundE,
RoundEP,
Sp,
GRS,
InputExc,
Z,
Flags
);
// Input Ports
input [23:0] RoundM; // Normalized 7
input [23:0] RoundMP; // Normalized exponent
input [8:0] RoundE; // Normalized 7 + 1
input [8:0] RoundEP; // Normalized 8+ 1
input Sp; // Product sign
input GRS;
input [4:0] InputExc;
// Output Ports
output [32-1:0] Z; // Final product
output [4:0] Flags;
// Internal Signals
wire [ 8:0] FinalE; // Rounded exponent
wire [23:0] FinalM;
wire [23:0] PreShiftM;
assign PreShiftM = GRS ? RoundMP : RoundM; // Round up if R and (G or S)
// Post rounding normalization (potential one bit shift> use shifted 7 if there is overflow)
assign FinalM = (PreShiftM[23] ? {1'b0, PreShiftM[23:1]} : PreShiftM[23:0]);
assign FinalE = (PreShiftM[23] ? RoundEP : RoundE); // Increment 8if a shift was done
assign Z = {Sp, FinalE[8-1:0], FinalM[14-1:0], 9'b0}; // Putting the pieces together
assign Flags = InputExc[4:0];
endmodule
| 7.570448 |
module tensor_weight_y1_bkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 144;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 7.058897 |
module tensor_weight_y1_bkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd144;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
tensor_weight_y1_bkb_ram tensor_weight_y1_bkb_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0)
);
endmodule
| 7.058897 |
module tensor_weight_y2_bkb_ram (
addr0,
ce0,
d0,
we0,
q0,
clk
);
parameter DWIDTH = 144;
parameter AWIDTH = 10;
parameter MEM_SIZE = 1024;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input clk;
(* ram_style = "block" *) reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
always @(posedge clk) begin
if (ce0) begin
if (we0) begin
ram[addr0] <= d0;
q0 <= d0;
end else q0 <= ram[addr0];
end
end
endmodule
| 7.058897 |
module tensor_weight_y2_bkb (
reset,
clk,
address0,
ce0,
we0,
d0,
q0
);
parameter DataWidth = 32'd144;
parameter AddressRange = 32'd1024;
parameter AddressWidth = 32'd10;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
tensor_weight_y2_bkb_ram tensor_weight_y2_bkb_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0)
);
endmodule
| 7.058897 |
module TensTimer (
input wire clk, //250Hz
input wire rst_n,
input wire [1:0] state,
output reg slake
);
parameter ZERO = 2'b01;
reg [11:0] cnt = 0;
always @(posedge clk, negedge rst_n) begin
if (!rst_n) begin
slake <= 0;
cnt <= 0;
end else if (state != ZERO) begin
slake <= 0;
cnt <= 0;
end else if (cnt >= 2499) slake <= 1;
else cnt <= cnt + 1;
end
endmodule
| 6.827799 |
module tens_comp (
x,
y
);
input [3:0] x;
output reg [3:0] y;
//case statement used to find 10's complement of input
always @(x) begin
case (x)
4'b0000: y = 4'b1010;
4'b0001: y = 4'b1001;
4'b0010: y = 4'b1000;
4'b0011: y = 4'b0111;
4'b0100: y = 4'b0110;
4'b0101: y = 4'b0101;
4'b0110: y = 4'b0100;
4'b0111: y = 4'b0011;
4'b1000: y = 4'b0010;
4'b1001: y = 4'b0001;
endcase
end
endmodule
| 6.655538 |
module tenth_sec_clk (
input wire clk, // 100MHz
output clock_divide_tenth_sec // 101Hz
);
localparam div_val = 9999999;
integer counter = 0;
reg hold = 0;
assign clock_divide_tenth_sec = hold;
always @(posedge clk) begin
if (counter == div_val) begin
counter = 0; //resets counter
hold = !hold;
end else begin
counter = counter + 1; //iterates clock
end
end
endmodule
| 7.185516 |
module ten_gige_phy_clk_gen (
input areset,
input refclk_p,
input refclk_n,
output refclk,
output clk156,
output dclk
);
wire clk156_buf;
wire dclk_buf;
wire clkfbout;
IBUFDS_GTE2 ibufds_inst (
.O (refclk),
.ODIV2(),
.CEB (1'b0),
.I (refclk_p),
.IB (refclk_n)
);
BUFG clk156_bufg_inst (
.I(refclk),
.O(clk156)
);
// Divding independent clock by 2 as source for DRP clock
BUFR #(
.BUFR_DIVIDE("2")
) dclk_divide_by_2_buf (
.I (clk156),
.O (dclk_buf),
.CE (1'b1),
.CLR(1'b0)
);
BUFG dclk_bufg_i (
.I(dclk_buf),
.O(dclk)
);
endmodule
| 6.893508 |
module ten_gig_eth_mac (
input reset,
//Transmit user I/F
input tx_clk0,
input tx_dcm_lock,
input tx_underrun,
input [63:0] tx_data,
input [ 7:0] tx_data_valid,
input tx_start,
output tx_ack,
input [ 7:0] tx_ifg_delay,
output [24:0] tx_statistics_vector,
output tx_statistics_valid,
//Receive user I/F
input rx_clk0,
input rx_dcm_lock,
output [63:0] rx_data,
output [ 7:0] rx_data_valid,
output rx_good_frame,
output rx_bad_frame,
output [28:0] rx_statistics_vector,
output [ 7:0] rx_statistics_valid,
// Misc
input [15:0] pause_val,
input pause_req,
input [66:0] configuration_vector,
//XGMII I/Fs
output [63:0] xgmii_txd,
output [ 7:0] xgmii_txc,
input [63:0] xgmii_rxd,
input [ 7:0] xgmii_rxc
);
mac_tx #(
.USE_HARD_CRC(1)
) mac_tx_inst (
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.reset (reset),
.tx_clk (tx_clk0),
.tx_dcm_lock (tx_dcm_lock),
.tx_underrun (tx_underrun),
.tx_data (tx_data),
.tx_data_valid (tx_data_valid),
.tx_start (tx_start),
.tx_ack (tx_ack),
.tx_ifg_delay (tx_ifg_delay),
.tx_statistics_vector(tx_statistics_vector),
.tx_statistics_valid (tx_statistics_valid)
);
mac_rx #(
.USE_HARD_CRC(1)
) mac_rx_inst (
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.reset (reset),
.rx_clk (rx_clk0),
.rx_dcm_lock (rx_dcm_lock),
.rx_data (rx_data),
.rx_data_valid (rx_data_valid),
.rx_good_frame (rx_good_frame),
.rx_bad_frame (rx_bad_frame),
.rx_statistics_vector(rx_statistics_vector),
.rx_statistics_valid (rx_statistics_valid)
);
endmodule
| 6.594556 |
module ten_gig_eth_mac_0 (
// Port declarations
input tx_clk0,
input reset,
input wire tx_axis_aresetn,
input wire [63 : 0] tx_axis_tdata,
input wire [ 7:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
input wire [ 7:0] tx_ifg_delay,
output wire tx_axis_tready,
output wire [25 : 0] tx_statistics_vector,
output wire tx_statistics_valid,
input [15 : 0] pause_val,
input pause_req,
input wire rx_axis_aresetn,
output wire [63 : 0] rx_axis_tdata,
output wire [ 7 : 0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tuser,
output wire rx_axis_tlast,
output wire [29 : 0] rx_statistics_vector,
output wire rx_statistics_valid,
input [ 79:0] tx_configuration_vector,
input [79 : 0] rx_configuration_vector,
output [ 2 : 0] status_vector,
input tx_dcm_locked,
output [63 : 0] xgmii_txd,
output [ 7 : 0] xgmii_txc,
input rx_clk0,
input rx_dcm_locked,
input [63 : 0] xgmii_rxd,
input [ 7 : 0] xgmii_rxc
);
ten_gig_eth_mac_0_block inst (
.tx_clk0 (tx_clk0),
.reset (reset),
.tx_axis_aresetn (tx_axis_aresetn),
.tx_axis_tdata (tx_axis_tdata),
.tx_axis_tvalid (tx_axis_tvalid),
.tx_axis_tlast (tx_axis_tlast),
.tx_axis_tuser (tx_axis_tuser),
.tx_ifg_delay (tx_ifg_delay),
.tx_axis_tkeep (tx_axis_tkeep),
.tx_axis_tready (tx_axis_tready),
.tx_statistics_vector (tx_statistics_vector),
.tx_statistics_valid (tx_statistics_valid),
.pause_val (pause_val),
.pause_req (pause_req),
.rx_axis_aresetn (rx_axis_aresetn),
.rx_axis_tdata (rx_axis_tdata),
.rx_axis_tkeep (rx_axis_tkeep),
.rx_axis_tvalid (rx_axis_tvalid),
.rx_axis_tuser (rx_axis_tuser),
.rx_axis_tlast (rx_axis_tlast),
.rx_statistics_vector (rx_statistics_vector),
.rx_statistics_valid (rx_statistics_valid),
.tx_configuration_vector(tx_configuration_vector),
.rx_configuration_vector(rx_configuration_vector),
.status_vector (status_vector),
.tx_dcm_locked (tx_dcm_locked),
.xgmii_txd (xgmii_txd),
.xgmii_txc (xgmii_txc),
.rx_clk0 (rx_clk0),
.rx_dcm_locked (rx_dcm_locked),
.xgmii_rxd (xgmii_rxd),
.xgmii_rxc (xgmii_rxc)
);
endmodule
| 6.594556 |
module ten_gig_eth_mac_0_sync_resetn (
input clk, // clock to be sync'ed to
input resetn_in, // Reset to be 'synced'
output resetn_out // synced reset
);
// Internal Signals
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async0 = 1'b0;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async1 = 1'b0;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async2 = 1'b0;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async3 = 1'b0;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_async4 = 1'b0;
(* ASYNC_REG = "TRUE", SHREG_EXTRACT = "NO" *)
reg reset_sync0 = 1'b0;
reg reset_sync1 = 1'b0;
// Synchroniser process.
// first five flops are asynchronously reset
always @(posedge clk or negedge resetn_in) begin
if (!resetn_in) begin
reset_async0 <= 1'b0;
reset_async1 <= 1'b0;
reset_async2 <= 1'b0;
reset_async3 <= 1'b0;
reset_async4 <= 1'b0;
end else begin
reset_async0 <= 1'b1;
reset_async1 <= reset_async0;
reset_async2 <= reset_async1;
reset_async3 <= reset_async2;
reset_async4 <= reset_async3;
end
end
// second two flops are synchronously reset - this is used for all later flops
// and should ensure the reset is fully synchronous
always @(posedge clk) begin
if (!reset_async4) begin
reset_sync0 <= 1'b0;
reset_sync1 <= 1'b0;
end else begin
reset_sync0 <= 1'b1;
reset_sync1 <= reset_sync0;
end
end
assign resetn_out = reset_sync1;
endmodule
| 6.594556 |
module ten_gig_eth_mac_0_xgmii_if (
// Port declarations
input reset,
input rx_axis_rstn,
input tx_clk0,
input tx_clk90,
input [63:0] xgmii_txd_core,
input [ 7:0] xgmii_txc_core,
output [31:0] xgmii_txd,
output [ 3:0] xgmii_txc,
output xgmii_tx_clk, (* KEEP = "true" *)
output wire rx_clk0,
output wire rx_dcm_locked,
input xgmii_rx_clk,
input [31:0] xgmii_rxd,
input [ 3:0] xgmii_rxc,
output wire [63:0] xgmii_rxd_core,
output wire [ 7:0] xgmii_rxc_core
);
reg rx_dcm_locked_reg;
wire xgmii_rx_clk_dcm;
wire rx_dcm_clk0;
wire clkfbout_buf;
wire clkfbout;
wire rx_mmcm_locked;
// Receiver clock management
IBUF xgmii_rx_clk_ibuf (
.I(xgmii_rx_clk),
.O(xgmii_rx_clk_dcm)
);
MMCME2_BASE #(
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6.000),
.CLKOUT0_DIVIDE_F (6.000),
.CLKIN1_PERIOD (6.400),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_PHASE (180.000),
.CLKOUT0_DUTY_CYCLE(0.5),
.REF_JITTER1 (0.010)
) rx_mmcm
// Output clocks
(
.CLKFBOUT (clkfbout),
.CLKOUT0 (rx_dcm_clk0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (xgmii_rx_clk_dcm),
// Other control and status signals
.LOCKED (rx_mmcm_locked),
.PWRDWN (1'b0),
.RST (reset),
.CLKFBOUTB(),
.CLKOUT0B (),
.CLKOUT1 (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 ()
);
BUFG clkf_buf (
.O(clkfbout_buf),
.I(clkfbout)
);
assign rx_dcm_locked = rx_mmcm_locked;
BUFG rx_bufg (
.I(rx_dcm_clk0),
.O(rx_clk0)
);
// register the dcm_locked signal into the system clock domain
always @(posedge rx_clk0) begin
rx_dcm_locked_reg <= rx_dcm_locked;
end
// Input Double Data Rate registers
generate
genvar i, j;
for (i = 0; i < 32; i = i + 1) begin : rxd_loop
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE")
) rxd_ddr (
.Q1(xgmii_rxd_core[i+32]),
.Q2(xgmii_rxd_core[i]),
.C (rx_clk0),
.CE(1'b1),
.D (xgmii_rxd[i]),
.R (1'b0),
.S (1'b0)
);
end
for (j = 0; j < 4; j = j + 1) begin : rxc_loop
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE")
) rxc_ddr (
.Q1(xgmii_rxc_core[j+4]),
.Q2(xgmii_rxc_core[j]),
.C (rx_clk0),
.CE(1'b1),
.D (xgmii_rxc[j]),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
// Transmit output clock logic
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE")
) tx_clk_ddr (
.Q (xgmii_tx_clk),
.D1(1'b1),
.D2(1'b0),
.C (tx_clk90),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
generate
genvar k, l;
// Transmit output registers
for (k = 0; k < 32; k = k + 1) begin : txd_loop
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0)
) txd_ddr (
.Q (xgmii_txd[k]),
.D1(xgmii_txd_core[k]),
.D2(xgmii_txd_core[k+32]),
.C (tx_clk0),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
end
for (l = 0; l < 4; l = l + 1) begin : txc_loop
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b1)
) txc_ddr (
.Q (xgmii_txc[l]),
.D1(xgmii_txc_core[l]),
.D2(xgmii_txc_core[l+4]),
.C (tx_clk0),
.CE(1'b1),
.R (1'b0),
.S (1'b0)
);
end
endgenerate
endmodule
| 6.594556 |
module ten_gig_eth_mac_UCB (
input reset,
input tx_clk0,
input tx_dcm_lock,
input rx_clk0,
input rx_dcm_lock,
// transmit interface
output tx_underrun,
input [63:0] tx_data,
input [7:0] tx_data_valid,
input tx_start,
output tx_ack,
output tx_ifg_delay,
output tx_statistics_vector,
output tx_statistics_valid,
// receive interface
output [63:0] rx_data,
output [7:0] rx_data_valid,
output rx_good_frame,
output rx_bad_frame,
output rx_statistics_vector,
output rx_statistics_valid,
// flow_control interface
output pause_val,
output pause_req,
// configuration
output configuration_vector,
// phy interface
output [63:0] xgmii_txd,
output [7:0] xgmii_txc,
input [63:0] xgmii_rxd,
input [7:0] xgmii_rxc
);
reg start;
assign tx_ack = 1'b1;
always @(posedge tx_clk0) begin
if (reset) begin
start <= 0;
end else begin
if (tx_start) begin
start <= 1'b1;
`ifdef DEBUG
$display("mac: got start of frame");
`endif
end
if (start) begin
if (tx_data_valid != 8'b1111_1111) begin
start <= 1'b0;
`ifdef DEBUG
$display("mac: got end of frame - %b", tx_data_valid);
`endif
end
end
end
end
assign xgmii_txc = start ? {8{1'b0}} : {8{1'b1}};
assign xgmii_txd = tx_data;
endmodule
| 6.594556 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module ten_gig_eth_pcs_pma_ip_ff_synchronizer #(
parameter C_NUM_SYNC_REGS = 3
)
(
input wire clk,
input wire data_in,
output reg data_out = 1'b0
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{1'b0}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk) begin
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
always @(posedge clk) begin
data_out = sync1_r[C_NUM_SYNC_REGS-1];
end
endmodule
| 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module ten_gig_eth_pcs_pma_ip_ff_synchronizer_rst #(
parameter C_NUM_SYNC_REGS = 3,
parameter C_RVAL = 1'b0
)
(
input wire clk,
input wire rst,
input wire data_in,
output reg data_out = 1'b0
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{C_RVAL}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk or posedge rst) begin
if(rst)
sync1_r <= {C_NUM_SYNC_REGS{C_RVAL}};
else
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
always @(posedge clk)
begin
data_out <= sync1_r[C_NUM_SYNC_REGS-1];
end
endmodule
| 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module ten_gig_eth_pcs_pma_ip_shared_logic_in_core_ff_synchronizer #(
parameter C_NUM_SYNC_REGS = 3
)
(
input wire clk,
input wire data_in,
output reg data_out = 1'b0
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{1'b0}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk) begin
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
always @(posedge clk) begin
data_out = sync1_r[C_NUM_SYNC_REGS-1];
end
endmodule
| 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module ten_gig_eth_pcs_pma_ip_shared_logic_in_core_ff_synchronizer_rst #(
parameter C_NUM_SYNC_REGS = 3,
parameter C_RVAL = 1'b0
)
(
input wire clk,
input wire rst,
input wire data_in,
output reg data_out = 1'b0
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{C_RVAL}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk or posedge rst) begin
if(rst)
sync1_r <= {C_NUM_SYNC_REGS{C_RVAL}};
else
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
always @(posedge clk)
begin
data_out <= sync1_r[C_NUM_SYNC_REGS-1];
end
endmodule
| 9.028271 |
module provides a parameterizable multi stage
// FF Synchronizer with appropriate synth attributes
// to mark ASYNC_REG and prevent SRL inference
// An active high reset is included with a parameterized reset
// value
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
`timescale 1ps / 1ps
module ten_gig_eth_pcs_pma_ip_shared_logic_in_core_ff_synchronizer_rst2 #(
parameter C_NUM_SYNC_REGS = 3,
parameter C_RVAL = 1'b0
)
(
input wire clk,
input wire rst,
input wire data_in,
output reg data_out = 1'b0
);
(* shreg_extract = "no", ASYNC_REG = "TRUE" *) reg [C_NUM_SYNC_REGS-1:0] sync1_r = {C_NUM_SYNC_REGS{C_RVAL}};
//----------------------------------------------------------------------------
// Synchronizer
//----------------------------------------------------------------------------
always @(posedge clk or posedge rst) begin
if(rst)
sync1_r <= {C_NUM_SYNC_REGS{C_RVAL}};
else
sync1_r <= {sync1_r[C_NUM_SYNC_REGS-2:0], data_in};
end
always @(posedge clk)
begin
data_out <= sync1_r[C_NUM_SYNC_REGS-1];
end
endmodule
| 9.028271 |
module holds the top level component declaration for the
// 10Gb/E PCS/PMA core.
//---------------------------------------------------------------------------
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
module ten_gig_eth_pcs_pma
(
input reset,
input txreset322,
input rxreset322,
input dclk_reset,
output pma_resetout,
output pcs_resetout,
input clk156,
input txusrclk2,
input rxusrclk2,
input dclk,
input [63 : 0] xgmii_txd,
input [7 : 0] xgmii_txc,
output [63 : 0] xgmii_rxd,
output [7 : 0] xgmii_rxc,
input mdc,
input mdio_in,
output mdio_out,
output mdio_tri,
input [4 : 0] prtad,
output [7 : 0] core_status,
input [2 : 0] pma_pmd_type,
output drp_req,
input drp_gnt,
output drp_den,
output drp_dwe,
output [15:0] drp_daddr,
input drp_drdy,
input [15:0] drp_drpdo,
output [15:0] drp_di,
output [31 : 0] gt_txd,
output [7 : 0] gt_txc,
input [31 : 0] gt_rxd,
input [7 : 0] gt_rxc,
output gt_slip,
input resetdone,
output tx_prbs31_en,
output rx_prbs31_en,
output clear_rx_prbs_err_count,
output [2 : 0] loopback_ctrl,
input signal_detect,
input tx_fault,
output tx_disable);
endmodule
| 7.541523 |
module ten_mhz_clock (
clock_in,
reset,
clock_out
);
input clock_in, reset;
output reg clock_out;
reg [11:0] counter;
always @(posedge clock_in or negedge reset) begin
if (!reset) begin
counter <= 0;
clock_out <= 0;
end else begin
if (counter == 12'h004) begin
counter <= 0;
clock_out <= ~clock_out;
end else begin
counter <= counter + 1;
clock_out <= clock_out;
end
end
end
endmodule
| 6.734305 |
module fibonacci_lfsr2(
input clk, [5:0]seedz,
input rst_n,
output [3:0] data
);
wire feedback = data[3] ^ data[1] ;
reg [3:0] out1 = 0 , out2 = 0;
always @(posedge clk)
if (~rst_n)
out1 <= 3'hf;
else
out1 <= {out1[2:0], feedback} ;
always @(negedge clk)
if (~rst_n)
out2 <= 3'hf;
else
out2 <= {out2[2:0], feedback} ;
assign data = (out1 | out2 != 0)?(out1 | out2):seedz[5:2];
endmodule
| 6.969171 |
module ten_sec_clk (
input wire clk, // 100MHz
output clock_divide_ten_sec // 1Hz
);
localparam div_val = 499999999;
integer counter = 0;
reg hold = 0;
assign clock_divide_ten_sec = hold;
always @(posedge clk) begin
if (counter == div_val) begin
counter = 0; //resets counter
hold = !hold;
end else begin
counter = counter + 1; //iterates clock
end
end
endmodule
| 7.157244 |
module TERAISC_AB_DECODER (
DI_SYSCLK,
DI_PHASE_A,
DI_PHASE_B,
DO_PULSE,
DO_DIRECT
);
// input
//
input DI_SYSCLK;
input DI_PHASE_A;
input DI_PHASE_B;
// output
//
output DO_PULSE;
output DO_DIRECT;
// register
//
reg DO_PULSE;
reg PULSE_DOUBLE;
reg PULSE_DOUBLE_LAST;
reg DIRECT;
reg DIRECT_PATCH;
// decode direct from phase A and B
//
always @(posedge DI_PHASE_A) DIRECT = DI_PHASE_B;
always @(posedge DI_PHASE_B) DIRECT_PATCH = ~(DIRECT ^ DI_PHASE_A);
assign DO_DIRECT = DIRECT | DIRECT_PATCH;
// decode pulse from phase A and B
//
always PULSE_DOUBLE = DI_PHASE_A ^ DI_PHASE_B;
always @(posedge DI_SYSCLK) begin
if (PULSE_DOUBLE != PULSE_DOUBLE_LAST) begin
DO_PULSE = 1'b1;
PULSE_DOUBLE_LAST = PULSE_DOUBLE;
end else begin
DO_PULSE = 1'b0;
end
end
endmodule
| 6.860234 |
module TERAISC_PWM_EX (
clk,
reset_n,
//
s_cs,
s_address,
s_write,
s_writedata,
s_read,
s_readdata,
//
PWM
);
`define REG_TOTAL_DUR 0
`define REG_HIGH_DUR 1
`define REG_ADJ_SPEED 2
`define REG_ABORT 3
`define REG_STATUS 2
input clk;
input reset_n;
input s_cs;
input [1:0] s_address;
input s_read;
output reg [31:0] s_readdata;
input s_write;
input [31:0] s_writedata;
output reg PWM;
reg [31:0] total_dur;
reg [31:0] high_dur;
reg [31:0] high_dur_temp;
reg [31:0] tick;
reg [31:0] dividir;
reg done;
wire trigger;
reg init;
reg abort;
PWM_Delay p1 (
.iclk(clk),
.ireset_n(reset_n),
.idivider(dividir),
.idone(done),
.otrigger(trigger)
);
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
high_dur <= 0;
total_dur <= 0;
dividir <= 0;
abort <= 0;
end else if (s_cs & s_write) begin
if (s_address == `REG_TOTAL_DUR) total_dur <= s_writedata;
else if (s_address == `REG_HIGH_DUR) high_dur <= s_writedata;
else if (s_address == `REG_ADJ_SPEED) dividir <= s_writedata;
else if (s_address == `REG_ABORT) abort <= s_writedata;
else high_dur <= high_dur;
end else if (s_cs & s_read) begin
if (s_address == `REG_TOTAL_DUR) s_readdata <= total_dur;
else if (s_address == `REG_HIGH_DUR) s_readdata <= high_dur_temp;
else if (s_address == `REG_STATUS) s_readdata <= done;
else s_readdata <= s_readdata;
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
high_dur_temp <= 0;
done <= 1'b0;
init <= 1'b0;
end else begin
if (high_dur != high_dur_temp) begin
if (trigger == 1'b1 && high_dur > high_dur_temp && init == 1'b1) begin
high_dur_temp <= high_dur_temp + 1'b1;
done <= 1'b0;
end else if (trigger == 1'b1 && high_dur < high_dur_temp && init == 1'b1) begin
high_dur_temp <= high_dur_temp - 1'b1;
done <= 1'b0;
end else if (trigger == 1'b1 && high_dur == high_dur_temp && init == 1'b1) begin
high_dur_temp <= high_dur;
done <= 1'b1;
end else if (high_dur == 32'd75000 && init == 1'b0) begin
init <= 1'b1;
high_dur_temp <= 32'd75000;
end else done <= 1'b0;
end else begin
done <= 1'b1;
end
end
end
reg PwmEnd;
reg AbortEnable;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
tick <= 0;
end else if (tick >= total_dur) begin
tick <= 0;
PwmEnd = ~PwmEnd;
end else tick <= tick + 1;
end
always @(PwmEnd) begin
if (abort) AbortEnable <= 1;
else AbortEnable <= 0;
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) PWM <= 0;
else
PWM <= (tick < high_dur_temp && AbortEnable == 0) ? 1'b1 : 1'b0; //duck die width(5us)250
end
endmodule
| 7.608025 |
module TERASIC_ADC_READ (
clk,
reset_n,
// avalon slave
s_chipselect,
s_read,
s_readdata,
s_write,
s_writedata,
// export interface
SPI_CLK,
SPI_CS_n,
SPI_IN,
SPI_OUT
);
input clk;
input reset_n;
input s_chipselect;
input s_read;
output reg [15:0] s_readdata;
input s_write;
input [15:0] s_writedata;
output SPI_CLK;
output SPI_CS_n;
input SPI_IN;
output SPI_OUT;
////////////////////////////////////////////
reg Start;
wire Done;
wire [11:0] Data;
reg [2:0] Channel;
////////////////////////////////////////////
// avalon read
always @(posedge clk or negedge reset_n) begin
if (~reset_n) s_readdata <= 0;
else if (s_chipselect & s_read) s_readdata <= {Done, 3'b000, Data}; // 1 + 3 + 12 = 16
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) Start <= 1'b0;
else if (s_chipselect & s_write) begin
Start <= s_writedata[15];
if (s_writedata[15]) Channel <= s_writedata[2:0];
end
end
////////////////////////////////////////////
ADC_READ ADC_READ_Inst (
.clk(clk),
.reset_n(reset_n),
.Channel(Channel),
.Data(Data),
.Start(Start),
.Done(Done),
.oDIN (SPI_OUT),
.oCS_n(SPI_CS_n),
.oSCLK(SPI_CLK),
.iDOUT(SPI_IN)
);
endmodule
| 8.29736 |
module TERASIC_CAMERA (
clk,
reset_n,
// streaming source interface
st_data,
st_valid,
st_sop,
st_eop,
st_ready,
// export
CAMERA_D,
CAMERA_FVAL,
CAMERA_LVAL,
CAMERA_PIXCLK
);
input clk;
input reset_n;
output [23:0] st_data;
output st_valid;
output st_sop;
output st_eop;
input st_ready;
input [11:0] CAMERA_D;
input CAMERA_FVAL;
input CAMERA_LVAL;
input CAMERA_PIXCLK;
////////////////////////////////////////////////
/* ##lou mod
parameter VIDEO_W = 800;
parameter VIDEO_H = 600;
*/
parameter VIDEO_W = 1280;
parameter VIDEO_H = 720;
`define VIDEO_PIX_NUM (VIDEO_W * VIDEO_H)
////////////////////////////////////////////////
wire [11:0] RGB_R, RGB_G, RGB_B;
wire [11:0] RGB_X, RGB_Y;
wire RGB_VALID;
CAMERA_RGB CAMERA_RGB_inst (
.reset_n(reset_n),
// Bayer Input
.CAMERA_D(CAMERA_D),
.CAMERA_FVAL(CAMERA_FVAL),
.CAMERA_LVAL(CAMERA_LVAL),
.CAMERA_PIXCLK(CAMERA_PIXCLK),
// RGB Output
.RGB_R(RGB_R),
.RGB_G(RGB_G),
.RGB_B(RGB_B),
.RGB_X(RGB_X),
.RGB_Y(RGB_Y),
.RGB_VALID(RGB_VALID)
);
defparam CAMERA_RGB_inst.VIDEO_W = VIDEO_W; defparam CAMERA_RGB_inst.VIDEO_H = VIDEO_H;
/////////////////////////////
// write rgb to fifo
reg [25:0] fifo_w_data; // 1-bit sop + 1-bit eop + 24-bits data
wire fifo_w_full;
wire sop;
wire eop;
wire in_active_area;
assign sop = (RGB_X == 0 && RGB_Y == 0) ? 1'b1 : 1'b0;
assign eop = (((RGB_X + 1) == VIDEO_W) && ((RGB_Y + 1) == VIDEO_H)) ? 1'b1 : 1'b0;
assign in_active_area = ((RGB_X < VIDEO_W) && (RGB_Y < VIDEO_H)) ? 1'b1 : 1'b0;
reg fifo_w_write;
always @(posedge CAMERA_PIXCLK or negedge reset_n) begin
if (~reset_n) begin
fifo_w_write <= 1'b0;
//push_fail <= 1'b0;
end else if (RGB_VALID & in_active_area) begin
if (!fifo_w_full) begin
fifo_w_data <= {sop, eop, RGB_B[11:4], RGB_G[11:4], RGB_R[11:4]};
fifo_w_write <= 1'b1;
end else begin
fifo_w_write <= 1'b0;
// push_fail <= 1'b1; // fifo full !!!!!
end
end else fifo_w_write <= 1'b0;
end
/////////////////////////////
// read from fifo
wire fifo_r_empty;
wire [25:0] fifo_r_q;
wire fifo_r_rdreq_ack;
/////////////////////////////
// FIFO
rgb_fifo rgb_fifo_inst (
// write
.data (fifo_w_data),
.wrclk (~CAMERA_PIXCLK),
.wrreq (fifo_w_write),
.wrfull(fifo_w_full),
// read
.rdclk(clk),
.rdreq(fifo_r_rdreq_ack),
.q(fifo_r_q),
.rdempty(fifo_r_empty),
//
.aclr(~reset_n)
);
///////////////////////////////
wire frame_start;
assign frame_start = fifo_r_q[25] & ~fifo_r_empty;
reg first_pix;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) first_pix <= 1'b0;
else if (send_packet_id) first_pix <= 1'b1;
else first_pix <= 1'b0;
end
wire send_packet_id;
assign send_packet_id = frame_start & ~first_pix;
/////////////////////////////
// flag for ready_latency=1
reg pre_ready;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) pre_ready <= 0;
else pre_ready <= st_ready;
end
////////////////////////////////////
assign {st_sop, st_eop, st_data} = (send_packet_id)?{1'b1,1'b0, 24'h000000}:{1'b0, fifo_r_q[24:0]};
assign st_valid = ~fifo_r_empty & pre_ready;
assign fifo_r_rdreq_ack = st_valid & (~send_packet_id);
endmodule
| 7.909958 |
module TERASIC_CLOCK_COUNT (
// avalon bus
s_clk_in,
s_reset_in,
s_address_in,
s_read_in,
s_readdata_out,
s_write_in,
s_writedata_in,
// clock bus
CLK_1,
CLK_2
);
`define REG_START 2'b00
`define REG_READ_CLK1 2'b01
`define REG_READ_CLK2 2'b10
input s_clk_in;
input s_reset_in;
input [1:0] s_address_in;
input s_read_in;
output [31:0] s_readdata_out;
input s_write_in;
input [31:0] s_writedata_in;
input CLK_1;
input CLK_2;
reg [31:0] s_readdata_out;
reg counting_now;
reg [15:0] cnt_down;
reg [15:0] clk1_cnt_latched;
reg [15:0] clk2_cnt_latched;
//===== control
// avalon write
always @(posedge s_clk_in or posedge s_reset_in) begin
if (s_reset_in) cnt_down <= 0;
else if (s_write_in && s_address_in == `REG_START) begin
cnt_down <= s_writedata_in[15:0];
counting_now <= (s_writedata_in == 0) ? 1'b0 : 1'b1;
end else if (cnt_down > 1) cnt_down <= cnt_down - 1;
else counting_now <= 1'b0;
end
// avalon read
always @(posedge s_clk_in or posedge s_reset_in) begin
if (s_reset_in) s_readdata_out <= 0;
else if (s_read_in && s_address_in == `REG_START) s_readdata_out <= {31'h0, counting_now};
else if (s_read_in && s_address_in == `REG_READ_CLK1)
s_readdata_out <= {16'h0000, clk1_cnt_latched};
else if (s_read_in && s_address_in == `REG_READ_CLK2)
s_readdata_out <= {16'h0000, clk2_cnt_latched};
end
//===== count
reg [15:0] clk1_cnt;
reg [15:0] clk2_cnt;
//assign counting_now = (cnt_down == 32'b0)?1'b0:1'b1;
always @(posedge CLK_1) begin
if (counting_now) begin
clk1_cnt <= clk1_cnt + 1;
clk1_cnt_latched <= 0;
end else if (clk1_cnt != 0) begin
clk1_cnt_latched <= clk1_cnt;
clk1_cnt <= 0;
end
end
always @(posedge CLK_2) begin
if (counting_now) begin
clk2_cnt <= clk2_cnt + 1;
clk2_cnt_latched <= 0;
end else if (clk2_cnt != 0) begin
clk2_cnt_latched <= clk2_cnt;
clk2_cnt <= 0;
end
end
endmodule
| 7.507823 |
module TERASIC_DC_MOTOR_PWM (
input clk,
input reset_n,
//
input s_cs,
input [ 1:0] s_address,
input s_write,
input [31:0] s_writedata,
input s_read,
output reg [31:0] s_readdata,
//
output reg PWM,
output reg DC_MOTOR_IN1,
output reg DC_MOTOR_IN2
);
`define REG_TOTAL_DUR 2'd0
`define REG_HIGH_DUR 2'd1
`define REG_CONTROL 2'd2
////////////////////////////////////////
// MM Port
reg motor_go;
reg motor_forward;
reg motor_fast_decay;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
// PWM
high_dur <= 0;
total_dur <= 0;
// MOTOR
motor_go <= 1'b0;
motor_forward <= 1'b1;
motor_fast_decay <= 1'b1;
end else if (s_cs && (s_address == `REG_CONTROL)) begin
if (s_write) {motor_fast_decay, motor_forward, motor_go} <= s_writedata[2:0];
else if (s_read) s_readdata <= {29'b0, motor_fast_decay, motor_forward, motor_go};
end else if (s_cs & s_write) begin
if (s_address == `REG_TOTAL_DUR) total_dur <= s_writedata;
else if (s_address == `REG_HIGH_DUR) high_dur <= s_writedata;
end else if (s_cs & s_read) begin
if (s_address == `REG_TOTAL_DUR) s_readdata <= total_dur;
else if (s_address == `REG_HIGH_DUR) s_readdata <= high_dur;
end
end
////////////////////////////////////////
always @(*) begin
if (motor_fast_decay) begin
// fast decay
if (motor_go) begin
if (motor_forward) {DC_MOTOR_IN2, DC_MOTOR_IN1, PWM} <= {1'b1, 1'b0, PWM_OUT}; // forward
else {DC_MOTOR_IN2, DC_MOTOR_IN1, PWM} <= {1'b0, 1'b1, PWM_OUT}; // reverse
end else {DC_MOTOR_IN2, DC_MOTOR_IN1, PWM} <= {1'b1, 1'b1, 1'b0};
end else begin
// slow decay
if (motor_go) begin
if (motor_forward) {DC_MOTOR_IN2, DC_MOTOR_IN1, PWM} <= {1'b1, 1'b0, PWM_OUT}; // forward
else {DC_MOTOR_IN2, DC_MOTOR_IN1, PWM} <= {1'b0, 1'b1, PWM_OUT}; // reverse
end else {DC_MOTOR_IN2, DC_MOTOR_IN1, PWM} <= {1'b0, 1'b0, 1'b0};
end
end
////////////////////////////////////////
// PWM
reg PWM_OUT;
reg [31:0] total_dur;
reg [31:0] high_dur;
reg [31:0] tick;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
tick <= 1;
end else if (tick >= total_dur) begin
tick <= 1;
end else tick <= tick + 1;
end
always @(posedge clk) begin
PWM_OUT <= (tick <= high_dur) ? 1'b1 : 1'b0;
end
endmodule
| 6.59791 |
module Terasic_IrDA_0 (
input wire s_read, // avalon_slave.read
input wire s_cs_n, // .chipselect_n
output wire [31:0] s_readdata, // .readdata
input wire s_write, // .write
input wire [31:0] s_writedata, // .writedata
input wire clk, // clock_sink.clk
input wire reset_n, // clock_sink_reset.reset_n
input wire ir, // conduit_end.export
output wire irq // interrupt_sender.irq
);
TERASIC_IRM terasic_irda_0 (
.s_read (s_read), // avalon_slave.read
.s_cs_n (s_cs_n), // .chipselect_n
.s_readdata (s_readdata), // .readdata
.s_write (s_write), // .write
.s_writedata(s_writedata), // .writedata
.clk (clk), // clock_sink.clk
.reset_n (reset_n), // clock_sink_reset.reset_n
.ir (ir), // conduit_end.export
.irq (irq) // interrupt_sender.irq
);
endmodule
| 7.328238 |
module TERASIC_IRM (
clk, // must be 50 MHZ
reset_n,
// interrrupt
irq,
// avalon slave
s_cs_n,
s_read,
s_readdata,
s_write,
s_writedata,
// export
ir
);
input clk;
input reset_n;
output reg irq;
input s_cs_n;
input s_read;
output [31:0] s_readdata;
input s_write;
input [31:0] s_writedata;
input ir;
// write to clear interrupt
wire data_ready;
//always @ (posedge clk or posedge data_ready or negedge reset_n)
reg pre_data_ready;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) pre_data_ready <= 1'b0;
else pre_data_ready <= data_ready;
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) irq <= 1'b0;
else if (~pre_data_ready & data_ready) irq <= 1'b1;
else if (~s_cs_n & s_write) irq <= 1'b0; // write any valud to clear interrupt flga
end
wire [31:0] fifo_data;
assign s_readdata = data_ready ? fifo_data : 32'hdeadbeef;
IRDA_RECEIVE_Terasic IRDA_RECEIVE_Terasic_inst (
.iCLK (clk), //clk 50MHz
.iRST_n(reset_n), //reset
.iIRDA(ir), //IRDA code input
.iREAD(~s_cs_n & s_read), //read command
.oDATA_REAY(data_ready), //data ready
.oDATA (fifo_data) //decode data output
);
endmodule
| 7.674776 |
module TERASIC_IR_RX_FIFO (
clk, // must be 50 MHZ
reset_n,
// interrrupt
irq,
// avalon slave
s_address,
s_cs_n,
s_read,
s_readdata,
s_write,
s_writedata,
// export
ir
);
`define IR_RX_DATA_REG 0
`define IR_RX_CS_REG 1
input s_address;
input clk;
input reset_n;
output reg irq;
input s_cs_n;
input s_read;
output [31:0] s_readdata;
input s_write;
input [31:0] s_writedata;
input ir;
reg [31:0] s_readdata;
reg fifo_clear;
wire [ 7:0] use_dw;
wire [31:0] writedata;
wire [31:0] readdata;
// write to clear interrupt
wire data_ready;
//always @ (posedge clk or posedge data_ready or negedge reset_n)
reg pre_data_ready;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) pre_data_ready <= 1'b0;
else pre_data_ready <= data_ready;
end
///////// interupt
always @(posedge clk or negedge reset_n) begin
if (~reset_n) irq <= 1'b0;
else if (~pre_data_ready & data_ready) irq <= 1'b1;
else if (s_write && (s_address == `IR_RX_CS_REG)) irq <= ~s_writedata[1];
end
////////// fifo clear
always @(clk) begin
if (~reset_n) fifo_clear <= 1'b0;
else if (s_write && (s_address == `IR_RX_CS_REG)) fifo_clear <= s_writedata[0];
else if (fifo_clear) fifo_clear <= 1'b0;
end
assign read = (s_read && (s_address == `IR_RX_DATA_REG)) ? 1 : 0;
always @(clk) begin
if (~reset_n) s_readdata <= 32'b0;
else if (s_read && (s_address == `IR_RX_CS_REG)) s_readdata <= use_dw;
else if (read && (s_address == `IR_RX_DATA_REG)) s_readdata <= readdata;
else s_readdata <= 32'b0;
end
reg write;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) write <= 1'b0;
else if (~pre_data_ready & data_ready) write <= 1'b1;
else if (write) write <= 0;
end
ir_fifo ir_fifo_inst (
.aclr(fifo_clear),
.data (writedata),
.wrclk(clk),
.wrreq(write),
.rdclk(clk),
.rdreq(read),
.q(readdata),
.rdusedw(use_dw),
.rdempty()
);
IRDA_RECEIVE_Terasic IRDA_RECEIVE_Terasic_inst (
.iCLK (clk), //clk 50MHz
.iRST_n(reset_n), //reset
.iIRDA(ir), //IRDA code input
.oDATA_REAY(data_ready), //data ready
.oDATA (writedata) //decode data output
);
endmodule
| 8.14762 |
module TERASIC_LOOPBACK (
clk,
reset_n,
// avalon mm slave
s_cs,
s_read,
s_readdata,
s_write,
s_writedata,
//
lb_in,
lb_out
);
parameter PAIR_NUM = 32;
parameter PAIR_BIR = 1;
input clk;
input reset_n;
//
input s_cs;
input s_read;
input s_write;
output reg [(PAIR_NUM-1):0] s_readdata;
input [(PAIR_NUM-1):0] s_writedata;
//
inout [(PAIR_NUM-1):0] lb_in;
inout [(PAIR_NUM-1):0] lb_out;
//============================================
always @(posedge clk) begin
if (s_cs & s_write) test_reset_n <= s_writedata[0];
else if (s_cs & s_read) s_readdata <= lb_error;
end
//============================================
// combin logic
//============================================
reg [(PAIR_NUM-1):0] test_mask;
wire [(PAIR_NUM-1):0] test_in;
wire [(PAIR_NUM-1):0] test_out;
reg test_reset_n;
reg test_done;
wire test_value_invert;
wire test_dir_invert;
reg [(PAIR_NUM-1):0] lb_error;
reg [ 1:0] test_case;
assign test_in = (test_value_invert)?(test_dir_invert?~lb_out:~lb_in):(test_dir_invert?lb_out:lb_in);
assign lb_out = (test_dir_invert) ? {PAIR_NUM{1'bz}} : (test_value_invert ? ~test_out : test_out);
assign lb_in = (test_dir_invert) ? (test_value_invert ? ~test_out : test_out) : {PAIR_NUM{1'bz}};
assign test_out = test_mask;
assign {test_dir_invert, test_value_invert} = {PAIR_BIR ? test_case[1] : 1'b0, test_case[0]};
always @(posedge clk or negedge test_reset_n) begin
if (~test_reset_n) begin
lb_error <= 'b0;
test_mask <= 'b1;
test_case <= 2'b00;
end else begin
// update mask
if (test_mask == (1 << (PAIR_NUM - 1))) begin
test_mask <= 'b1;
test_case <= test_case + 1;
end else test_mask <= (test_mask << 1);
// check loopback
if ((test_in & test_mask) != test_out) lb_error <= lb_error | test_mask;
end
end
endmodule
| 8.584522 |
module TERASIC_PWM_EX (
clk,
reset_n,
//
s_cs,
s_address,
s_write,
s_writedata,
s_read,
s_readdata,
//
PWM
);
`define REG_TOTAL_DUR 0
`define REG_HIGH_DUR 1
`define REG_ADJ_SPEED 2
`define REG_ABORT 3
`define REG_STATUS 2
input clk;
input reset_n;
input s_cs;
input [1:0] s_address;
input s_read;
output reg [31:0] s_readdata;
input s_write;
input [31:0] s_writedata;
output reg PWM;
reg [31:0] total_dur;
reg [31:0] high_dur;
reg [31:0] high_dur_temp;
reg [31:0] tick;
reg [31:0] dividir;
reg done;
wire trigger;
reg init;
reg abort;
PWM_Delay p1 (
.iclk(clk),
.ireset_n(reset_n),
.idivider(dividir),
.idone(done),
.otrigger(trigger)
);
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
high_dur <= 0;
total_dur <= 0;
dividir <= 0;
abort <= 0;
end else if (s_cs & s_write) begin
if (s_address == `REG_TOTAL_DUR) total_dur <= s_writedata;
else if (s_address == `REG_HIGH_DUR) high_dur <= s_writedata;
else if (s_address == `REG_ADJ_SPEED) dividir <= s_writedata;
else if (s_address == `REG_ABORT) abort <= s_writedata;
else high_dur <= high_dur;
end else if (s_cs & s_read) begin
if (s_address == `REG_TOTAL_DUR) s_readdata <= total_dur;
else if (s_address == `REG_HIGH_DUR) s_readdata <= high_dur_temp;
else if (s_address == `REG_STATUS) s_readdata <= done;
else s_readdata <= s_readdata;
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
high_dur_temp <= 0;
done <= 1'b0;
init <= 1'b0;
end else begin
if (high_dur != high_dur_temp) begin
if (trigger == 1'b1 && high_dur > high_dur_temp && init == 1'b1) begin
high_dur_temp <= high_dur_temp + 1'b1;
done <= 1'b0;
end else if (trigger == 1'b1 && high_dur < high_dur_temp && init == 1'b1) begin
high_dur_temp <= high_dur_temp - 1'b1;
done <= 1'b0;
end else if (trigger == 1'b1 && high_dur == high_dur_temp && init == 1'b1) begin
high_dur_temp <= high_dur;
done <= 1'b1;
end else if (high_dur == 32'd75000 && init == 1'b0) begin
init <= 1'b1;
high_dur_temp <= 32'd75000;
end else done <= 1'b0;
end else begin
done <= 1'b1;
end
end
end
reg PwmEnd;
reg AbortEnable;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
tick <= 0;
end else if (tick >= total_dur) begin
tick <= 0;
PwmEnd = ~PwmEnd;
end else tick <= tick + 1;
end
always @(PwmEnd) begin
if (abort) AbortEnable <= 1;
else AbortEnable <= 0;
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) PWM <= 0;
else
PWM <= (tick < high_dur_temp && AbortEnable == 0) ? 1'b1 : 1'b0; //duck die width(5us)250
end
endmodule
| 7.700539 |
module board_regs (
input wire clk,
input wire rst,
input wire cs,
input wire we,
input wire [ 7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
// API addresses.
localparam ADDR_CORE_NAME0 = 8'h00;
localparam ADDR_CORE_NAME1 = 8'h01;
localparam ADDR_CORE_VERSION = 8'h02;
localparam ADDR_DUMMY_REG = 8'hFF; // general-purpose register
// Core ID constants.
localparam CORE_NAME0 = 32'h54433547; // "TC5G"
localparam CORE_NAME1 = 32'h20202020; // " "
localparam CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31:0] tmp_read_data;
// dummy register to check that you can actually write something
reg [31:0] reg_dummy;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign read_data = tmp_read_data;
//----------------------------------------------------------------
// Access Handler
//----------------------------------------------------------------
always @(posedge clk)
//
if (rst)
reg_dummy <= {32{1'b0}};
else if (cs) begin
//
if (we) begin
//
// WRITE handler
//
case (address)
ADDR_DUMMY_REG: reg_dummy <= write_data;
endcase
//
end else begin
//
// READ handler
//
case (address)
ADDR_CORE_NAME0: tmp_read_data <= CORE_NAME0;
ADDR_CORE_NAME1: tmp_read_data <= CORE_NAME1;
ADDR_CORE_VERSION: tmp_read_data <= CORE_VERSION;
ADDR_DUMMY_REG: tmp_read_data <= reg_dummy;
//
default: tmp_read_data <= {32{1'b0}}; // read non-existent locations as zeroes
endcase
//
end
//
end
endmodule
| 7.886152 |
module TERASIC_SPI_3WIRE (
clk,
reset_n,
//
s_chipselect,
s_address,
s_write,
s_writedata,
s_read,
s_readdata,
// condui
SPI_CS_n,
SPI_SCLK,
SPI_SDIO
);
input clk;
input reset_n;
// avalon slave
input s_chipselect;
input [3:0] s_address;
input s_write;
input [7:0] s_writedata;
input s_read;
output reg [7:0] s_readdata;
output SPI_CS_n;
output SPI_SCLK;
inout SPI_SDIO;
//////////////////////////////////////
`define REG_DATA 0 // r/w
`define REG_CTRL_STATUS 1 // r/w
`define REG_INDEX 2 // w
`define REG_READ_NUM 3 // w
/////////////////////////////////////
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
CMD_START <= 1'b0;
FIFO_CLEAR <= 1'b0;
end else if (s_chipselect & s_read) begin
if (s_address == `REG_DATA) s_readdata <= FIFO_READDATA;
else if (s_address == `REG_CTRL_STATUS) s_readdata <= {7'h00, CMD_DONE};
end else if (s_chipselect & s_write) begin
if (s_address == `REG_DATA) FIFO_WRITEDATA <= s_writedata;
else if (s_address == `REG_CTRL_STATUS) {FIFO_CLEAR, REG_RW, CMD_START} <= s_writedata[2:0];
else if (s_address == `REG_INDEX) REG_ADDR <= s_writedata;
else if (s_address == `REG_READ_NUM) REG_RX_NUM <= s_writedata;
end
end
always @(posedge clk or negedge reset_n) begin
if (~reset_n) FIFO_WRITE <= 1'b0;
else if (s_chipselect && s_write && (s_address == `REG_DATA)) FIFO_WRITE <= 1'b1;
else FIFO_WRITE <= 1'b0;
end
/////////////////////////////////////
reg CMD_START;
wire CMD_DONE;
reg [7:0] REG_ADDR;
reg [7:0] REG_RX_NUM;
reg REG_RW;
reg FIFO_CLEAR;
reg FIFO_WRITE;
reg [7:0] FIFO_WRITEDATA;
wire FIFO_READ_ACK;
wire [7:0] FIFO_READDATA;
assign FIFO_READ_ACK = (s_chipselect && s_read && (s_address == `REG_DATA)) ? 1'b1 : 1'b0;
//assign FIFO_WRITE = (s_chipselect && s_write && (s_address == `REG_DATA))?1'b1:1'b0;
SPI_3WIRE SPI_3WIRE_inst (
.clk(clk),
.reset_n(reset_n),
//
.CMD_START(CMD_START),
.CMD_DONE(CMD_DONE),
.REG_ADDR(REG_ADDR),
.REG_RW(REG_RW),
.REG_RX_NUM(REG_RX_NUM),
.FIFO_CLEAR(FIFO_CLEAR),
.FIFO_WRITE(FIFO_WRITE),
.FIFO_WRITEDATA(FIFO_WRITEDATA),
.FIFO_READ_ACK(FIFO_READ_ACK),
.FIFO_READDATA(FIFO_READDATA),
//
.SPI_CS_n(SPI_CS_n),
.SPI_SCLK(SPI_SCLK),
.SPI_SDIO(SPI_SDIO)
);
endmodule
| 8.216858 |
module TERASIC_SRAM (
// global clk/reset
clk,
reset_n,
// avalon slave
s_chipselect_n,
s_byteenable_n,
s_write_n,
s_read_n,
s_address,
s_writedata,
s_readdata,
// SRAM interface
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_n,
SRAM_LB_n,
SRAM_WE_n,
SRAM_CE_n,
SRAM_OE_n
);
parameter DATA_BITS = 16;
parameter ADDR_BITS = 20;
input clk;
input reset_n;
input s_chipselect_n;
input [(DATA_BITS/8-1):0] s_byteenable_n;
input s_write_n;
input s_read_n;
input [(ADDR_BITS-1):0] s_address;
input [(DATA_BITS-1):0] s_writedata;
output [(DATA_BITS-1):0] s_readdata;
output SRAM_CE_n;
output SRAM_OE_n;
output SRAM_LB_n;
output SRAM_UB_n;
output SRAM_WE_n;
output [(ADDR_BITS-1):0] SRAM_ADDR;
inout [(DATA_BITS-1):0] SRAM_DQ;
assign SRAM_DQ = SRAM_WE_n ? 'hz : s_writedata;
assign s_readdata = SRAM_DQ;
assign SRAM_ADDR = s_address;
assign SRAM_WE_n = s_write_n;
assign SRAM_OE_n = s_read_n;
assign SRAM_CE_n = s_chipselect_n;
assign {SRAM_UB_n, SRAM_LB_n} = s_byteenable_n;
/*
// Host Side
input [15:0] iDATA;
output [15:0] oDATA;
input [17:0] iADDR;
input iWE_N,iOE_N;
input iCE_N,iCLK;
input [1:0] iBE_N;
// SRAM Side
inout [15:0] SRAM_DQ;
output [17:0] SRAM_ADDR;
output SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N;
assign SRAM_DQ = SRAM_WE_N ? 16'hzzzz : iDATA;
assign oDATA = SRAM_DQ;
assign SRAM_ADDR = iADDR;
assign SRAM_WE_N = iWE_N;
assign SRAM_OE_N = iOE_N;
assign SRAM_CE_N = iCE_N;
assign SRAM_UB_N = iBE_N[1];
assign SRAM_LB_N = iBE_N[0];
*/
endmodule
| 7.627867 |
module TERASIC_STREAM_SOURCE (
// clock
clk,
reset_n,
// mm slave
s_cs,
s_read,
s_write,
s_readdata,
s_writedata,
// streaming source
src_ready,
src_valid,
src_data,
src_sop,
src_eop,
user_mode
);
parameter VIDEO_W = 800;
parameter VIDEO_H = 600;
// clock
input clk;
input reset_n;
// mm slave
input s_cs;
input s_read;
input s_write;
output reg [7:0] s_readdata;
input [7:0] s_writedata;
// streaming source
input src_ready;
output reg src_valid;
output reg [23:0] src_data;
output reg src_sop;
output reg src_eop;
// mode
input [7:0] user_mode;
`define PAT_SCALE 7'd0
`define PAT_RED 7'd1
`define PAT_GREEN 7'd2
`define PAT_BLUE 7'd3
`define PAT_WHITE 7'd4
`define PAT_BLACK 7'd5
`define PAT_RED_SCALE 7'd6
`define PAT_GREEN_SCALE 7'd7
`define PAT_BLUE_SCALE 7'd8
//////////////////////////////////
// mm slave
// bit0: 1 start streaming, 0 stop streaming
// bit1~7: pattern mode
reg stream_active;
reg [6:0] pat_id;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
pat_id <= 0;
stream_active <= 1'b1; // defautl active for testing
end else if (s_cs & s_write) {pat_id, stream_active} <= s_writedata;
else if (s_cs & s_read) s_readdata <= {pat_id, stream_active};
end
//////////////////////////////////
// generate x & y
reg [9:0] x;
reg [9:0] y;
wire next_xy;
assign next_xy = src_ready & is_send_video_data;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
x <= 0;
y <= 0;
end else if (next_xy) begin
if (x + 1 < VIDEO_W) x <= x + 1;
else if (y + 1 < VIDEO_H) begin
y <= y + 1;
x <= 0;
end else begin
x <= 0;
y <= 0;
end
end
end
///////////////////////////////////
// pat id
wire [6:0] disp_pat;
assign disp_pat = user_mode[0] ? user_mode[7:1] : pat_id;
///////////////////////////////////
// generate src_data, src_eop, src_valid according to x & y;
//
reg is_send_video_data;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) src_valid <= 1'b0;
else src_valid <= src_ready;
end
wire is_last_pixel;
assign is_last_pixel = (((x + 1) == VIDEO_W) && ((y + 1) == VIDEO_H)) ? 1'b1 : 1'b0;
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
is_send_video_data <= 1'b0; // need to send packet id first
src_sop <= 1'b0;
src_eop <= 1'b0;
src_data <= 0;
end else if (src_ready) begin
if (~is_send_video_data) begin // send packet id
is_send_video_data <= 1'b1;
src_sop <= 1'b1;
src_eop <= 1'b0;
src_data <= 0; // 0: presents 'Video data packet'
end else begin
src_sop <= 1'b0; //(x==0 && y ==0)?1'b1:1'b0;
src_eop <= is_last_pixel;
if (is_last_pixel) is_send_video_data <= 1'b0; // no more send video data
if (disp_pat == `PAT_SCALE) begin
if (y < VIDEO_H / 4) src_data <= {8'h00, 8'h00, x[7:0]};
else if (y < VIDEO_H / 2) src_data <= {8'h00, x[7:0], 8'h00};
else if (y < VIDEO_H * 3 / 4) src_data <= {x[7:0], 8'h00, 8'h00};
else src_data <= {x[7:0], x[7:0], x[7:0]};
end else if (disp_pat == `PAT_RED) src_data <= {8'h00, 8'h00, 8'hff};
else if (disp_pat == `PAT_GREEN) src_data <= {8'h00, 8'hff, 8'h00};
else if (disp_pat == `PAT_BLUE) src_data <= {8'hff, 8'h00, 8'h00};
else if (disp_pat == `PAT_WHITE) src_data <= {8'hff, 8'hff, 8'hff};
else if (disp_pat == `PAT_BLACK) src_data <= {8'h00, 8'h00, 8'h00};
else if (disp_pat == `PAT_RED_SCALE) src_data <= {8'h00, 8'h00, x[7:0]};
else if (disp_pat == `PAT_GREEN_SCALE) src_data <= {8'h00, x[7:0], 8'h00};
else if (disp_pat == `PAT_BLUE_SCALE) src_data <= {x[7:0], 8'h00, 8'h00};
end
end
end
endmodule
| 7.054555 |
module terminal (
`include "fifo_define.v"
input wire wr_en,
input wire rd_en,
input wire [`width-1:0] wr_data,
input wire terminal_valid,
input wire rstn,
input wire clk,
output reg [`width-1:0] rd_data, // APB read data
output wire terminal_ready,
output wire fifo_full, // Watchdog interrupt
output wire fifo_empty
); // Watchdog timeout reset
integer i;
reg [`width-1:0] fifo[`depth-1:0];
reg [`addr-1:0] rd_addr, wr_addr;
reg [`addr-1:0] cnt;
always @(posedge clk or negedge rstn) begin : cnt_judge
// process p_LockSeq
if (rstn == 1'b0) begin
// asynchronous reset (active low)
cnt <= 'b0;
end else if (wr_en && terminal_valid && rd_en && (cnt == `depth - 1)) begin
cnt <= cnt - 1;
end else if (wr_en && terminal_valid && rd_en && (cnt == 0)) begin
cnt <= cnt + 1;
end else if (wr_en && terminal_valid && !rd_en && (cnt != `depth - 1)) begin
cnt <= cnt + 1;
end else if (!wr_en && rd_en && (cnt != 0)) begin
cnt <= cnt - 1;
end else begin
cnt <= cnt;
end
end //cnt shows the margin of the fifo
always @(posedge clk or negedge rstn) begin : write
// asynchronous reset (active low)
if (rstn == 1'b0) begin
for (i = 0; i < `depth; i = i + 1) fifo[i] <= 'b0;
wr_addr <= 1'b0;
end else if (wr_en && terminal_valid && !fifo_full) begin
fifo[wr_addr] <= wr_data;
wr_addr <= wr_addr + 1;
end else begin
wr_addr <= wr_addr;
fifo[wr_addr] <= fifo[wr_addr];
end
end
always @(posedge clk or negedge rstn) begin : read
// asynchronous reset (active low)
if (rstn == 1'b0) begin
rd_addr <= 1'b0;
end else if (rd_en && !fifo_empty) begin
rd_data <= fifo[rd_addr];
rd_addr <= rd_addr + 1;
end else begin
rd_addr <= rd_addr;
end
end
assign fifo_full = (cnt == `depth - 1) ? 1 : 0;
assign terminal_ready = !fifo_full && wr_en;
assign fifo_empty = (cnt == 0) ? 1 : 0;
endmodule
| 8.692363 |
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