code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module td_fused_top_fifo_w4_d8_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 4'd1;
if (mOutPtr == 4'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 4'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 4'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d8_S_shiftReg U_td_fused_top_fifo_w4_d8_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d8_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 4'd8;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
sr_2 <= sr_1;
sr_3 <= sr_2;
sr_4 <= sr_3;
sr_5 <= sr_4;
sr_6 <= sr_5;
sr_7 <= sr_6;
end
end
always @(sr_0, sr_1, sr_2, sr_3, sr_4, sr_5, sr_6, sr_7, a) begin
case (a)
3'd0: q = sr_0;
3'd1: q = sr_1;
3'd2: q = sr_2;
3'd3: q = sr_3;
3'd4: q = sr_4;
3'd5: q = sr_5;
3'd6: q = sr_6;
3'd7: q = sr_7;
default: q = sr_7;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d2_S (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din
);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output [DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input [DATA_WIDTH - 1:0] if_din;
wire [ADDR_WIDTH - 1:0] shiftReg_addr;
wire [DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg [ADDR_WIDTH:0] mOutPtr = ~{(ADDR_WIDTH + 1) {1'b0}};
reg internal_empty_n = 0;
reg internal_full_n = 1;
assign if_full_n = internal_full_n;
assign if_empty_n = internal_empty_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @(posedge clk) begin
if (reset == 1'b1) begin
mOutPtr <= ~{ADDR_WIDTH + 1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 2'd1;
if (mOutPtr == 2'd0) internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 2'd1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2'd2) internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0] : {ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
td_fused_top_fifo_w4_d2_S_shiftReg U_td_fused_top_fifo_w4_d2_S_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q)
);
endmodule
| 6.827284 |
module td_fused_top_fifo_w4_d2_S_shiftReg (
clk,
data,
ce,
a,
q
);
parameter DATA_WIDTH = 32'd4;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 2'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg [DATA_WIDTH-1:0] sr_0, sr_1;
integer i;
always @(posedge clk) begin
if (ce) begin
sr_0 <= data;
sr_1 <= sr_0;
end
end
always @(sr_0, sr_1, a) begin
case (a)
1'd0: q = sr_0;
1'd1: q = sr_1;
default: q = sr_1;
endcase
end
endmodule
| 6.827284 |
module td_fused_top_Block_entry_proc_proc (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
tmp,
ap_return
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [15:0] tmp;
output [15:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg[15:0] ap_return;
reg ap_done_reg;
reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_block_state1;
reg [15:0] ap_return_preg;
reg [0:0] ap_NS_fsm;
wire ap_ce_reg;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
#0 ap_return_preg = 16'd0;
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @(posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_return_preg <= 16'd0;
end else begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return_preg <= tmp;
end
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @(*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @(*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_return = tmp;
end else begin
ap_return = ap_return_preg;
end
end
always @(*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1: begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default: begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @(*) begin
ap_block_state1 = ((ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0 #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 3,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input wire i_ce,
input wire i_write,
output wire i_full_n,
input wire i_ce0,
input wire i_we0,
input wire [AddressWidth-1:0] i_address0,
input wire [ DataWidth-1:0] i_d0,
output wire [ DataWidth-1:0] i_q0,
// target
input wire t_ce,
input wire t_read,
output wire t_empty_n,
input wire t_ce0,
input wire t_we0,
input wire [AddressWidth-1:0] t_address0,
input wire [ DataWidth-1:0] t_d0,
output wire [ DataWidth-1:0] t_q0
);
//------------------------Local signal-------------------
// control/status
reg [ IndexWidth-1:0] iptr = 1'b0; // initiator index
reg [ IndexWidth-1:0] tptr = 1'b0; // target index
reg [ IndexWidth:0] count = 1'b0; // count of written buffers
reg full_n = 1'b1; // whether all buffers are written
reg empty_n = 1'b0; // whether none of the buffers is written
wire push_buf; // finish writing a buffer
wire write_buf; // write a buffer
wire pop_buf; // finish reading a buffer
wire [AddressWidth+IndexWidth-1:0] memcore_iaddr;
wire [AddressWidth+IndexWidth-1:0] memcore_taddr;
//------------------------Instantiation------------------
assign memcore_iaddr = {i_address0, iptr};
assign memcore_taddr = {t_address0, tptr};
td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_U (
.reset (reset),
.clk (clk),
.address0(memcore_iaddr),
.ce0 (i_ce0),
.we0 (i_we0),
.d0 (i_d0),
.q0 (i_q0),
.address1(memcore_taddr),
.ce1 (t_ce0),
.we1 (t_we0),
.d1 (t_d0),
.q1 (t_q0)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++output+++++++++++++++++++++++++
assign i_full_n = full_n;
assign t_empty_n = empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++control/status+++++++++++++++++
assign push_buf = i_ce & i_write & full_n;
assign write_buf = i_ce & i_write;
assign pop_buf = t_ce & t_read & empty_n;
// iptr
always @(posedge clk) begin
if (reset == 1'b1) iptr <= 1'b0;
else if (push_buf) begin
if (iptr == BufferCount - 1'b1) iptr <= 1'b0;
else iptr <= iptr + 1'b1;
end
end
// tptr
always @(posedge clk) begin
if (reset == 1'b1) tptr <= 1'b0;
else if (pop_buf) begin
if (tptr == BufferCount - 1'b1) tptr <= 1'b0;
else tptr <= tptr + 1'b1;
end
end
// count
always @(posedge clk) begin
if (reset == 1'b1) count <= 1'b0;
else if (push_buf && !pop_buf) count <= count + 1'b1;
else if (!push_buf && pop_buf) count <= count - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1) full_n <= 1'b1;
else if (push_buf && !pop_buf && count == BufferCount - 2'd2) full_n <= 1'b0;
else if (!push_buf && pop_buf) full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1) empty_n <= 1'b0;
else if ((!write_buf && pop_buf && count == 1'b1) || (pop_buf && count == 1'b0))
empty_n <= 1'b0;
else if (write_buf && !pop_buf) empty_n <= 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd14;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum2_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 14;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd14;
parameter AddressWidth = 32'd4;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_accum1_out_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 4;
parameter MEM_SIZE = 14;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd27;
parameter AddressWidth = 32'd5;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_products_0_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 5;
parameter MEM_SIZE = 27;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec #(
parameter
DataWidth = 16,
AddressRange = 32,
AddressWidth = 5,
BufferCount = 2,
IndexWidth = 1
) (
// system signals
input wire clk,
input wire reset,
// initiator
input wire i_ce,
input wire i_write,
output wire i_full_n,
input wire i_ce0,
input wire i_we0,
input wire [AddressWidth-1:0] i_address0,
input wire [ DataWidth-1:0] i_d0,
output wire [ DataWidth-1:0] i_q0,
// target
input wire t_ce,
input wire t_read,
output wire t_empty_n,
input wire t_ce0,
input wire t_we0,
input wire [AddressWidth-1:0] t_address0,
input wire [ DataWidth-1:0] t_d0,
output wire [ DataWidth-1:0] t_q0
);
//------------------------Local signal-------------------
// control/status
reg [ IndexWidth-1:0] iptr = 1'b0; // initiator index
reg [ IndexWidth-1:0] tptr = 1'b0; // target index
reg [ IndexWidth:0] count = 1'b0; // count of written buffers
reg full_n = 1'b1; // whether all buffers are written
reg empty_n = 1'b0; // whether none of the buffers is written
wire push_buf; // finish writing a buffer
wire write_buf; // write a buffer
wire pop_buf; // finish reading a buffer
wire [AddressWidth+IndexWidth-1:0] memcore_iaddr;
wire [AddressWidth+IndexWidth-1:0] memcore_taddr;
//------------------------Instantiation------------------
assign memcore_iaddr = {i_address0, iptr};
assign memcore_taddr = {t_address0, tptr};
td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_U (
.reset (reset),
.clk (clk),
.address0(memcore_iaddr),
.ce0 (i_ce0),
.we0 (i_we0),
.d0 (i_d0),
.q0 (i_q0),
.address1(memcore_taddr),
.ce1 (t_ce0),
.we1 (t_we0),
.d1 (t_d0),
.q1 (t_q0)
);
//------------------------Body---------------------------
//++++++++++++++++++++++++output+++++++++++++++++++++++++
assign i_full_n = full_n;
assign t_empty_n = empty_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++control/status+++++++++++++++++
assign push_buf = i_ce & i_write & full_n;
assign write_buf = i_ce & i_write;
assign pop_buf = t_ce & t_read & empty_n;
// iptr
always @(posedge clk) begin
if (reset == 1'b1) iptr <= 1'b0;
else if (push_buf) begin
if (iptr == BufferCount - 1'b1) iptr <= 1'b0;
else iptr <= iptr + 1'b1;
end
end
// tptr
always @(posedge clk) begin
if (reset == 1'b1) tptr <= 1'b0;
else if (pop_buf) begin
if (tptr == BufferCount - 1'b1) tptr <= 1'b0;
else tptr <= tptr + 1'b1;
end
end
// count
always @(posedge clk) begin
if (reset == 1'b1) count <= 1'b0;
else if (push_buf && !pop_buf) count <= count + 1'b1;
else if (!push_buf && pop_buf) count <= count - 1'b1;
end
// full_n
always @(posedge clk) begin
if (reset == 1'b1) full_n <= 1'b1;
else if (push_buf && !pop_buf && count == BufferCount - 2'd2) full_n <= 1'b0;
else if (!push_buf && pop_buf) full_n <= 1'b1;
end
// empty_n
always @(posedge clk) begin
if (reset == 1'b1) empty_n <= 1'b0;
else if ((!write_buf && pop_buf && count == 1'b1) || (pop_buf && count == 1'b0))
empty_n <= 1'b0;
else if (write_buf && !pop_buf) empty_n <= 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore (
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
we1,
d1,
q1
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd54;
parameter AddressWidth = 32'd6;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
output [DataWidth - 1:0] q1;
td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_ram td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_ram_U(
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1),
.q1(q1)
);
endmodule
| 6.827284 |
module td_fused_top_dataflow_in_loop_TOP_LOOP38116_ifmap_vec_memcore_ram (
addr0,
ce0,
d0,
we0,
q0,
addr1,
ce1,
d1,
we1,
q1,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 6;
parameter MEM_SIZE = 54;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
output reg [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
output reg [DWIDTH-1:0] q1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram[addr0] <= d0;
q0 <= ram[addr0];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1) ram[addr1] <= d1;
q1 <= ram[addr1];
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = 32'd2;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
input [AddressWidth - 1:0] address2;
input ce2;
output [DataWidth - 1:0] q2;
input [AddressWidth - 1:0] address3;
input ce3;
output [DataWidth - 1:0] q3;
input [AddressWidth - 1:0] address4;
input ce4;
output [DataWidth - 1:0] q4;
td_fused_top_td_fused_axi_in_p_ram td_fused_top_td_fused_axi_in_p_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1),
.addr2(address2),
.ce2(ce2),
.q2(q2),
.addr3(address3),
.ce3(ce3),
.q3(q3),
.addr4(address4),
.ce4(ce4),
.q4(q4)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input clk;
reg [DWIDTH-1:0] ram0[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram1[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram2[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram3[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram0[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram1[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram2[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram2[addr3];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram3[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram3[addr4];
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd49000;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_final_fmaps_memcore_ram td_fused_top_td_fused_final_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd6272;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf7_fmaps_memcore_ram td_fused_top_td_fused_tdf7_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd3136;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf10_fmaps_memcore_ram td_fused_top_td_fused_tdf10_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd12544;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf4_fmaps_memcore_ram td_fused_top_td_fused_tdf4_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd25088;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf3_fmaps_memcore_ram td_fused_top_td_fused_tdf3_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd50176;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf1_fmaps_memcore_ram td_fused_top_td_fused_tdf1_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = 32'd2;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
input [AddressWidth - 1:0] address2;
input ce2;
output [DataWidth - 1:0] q2;
input [AddressWidth - 1:0] address3;
input ce3;
output [DataWidth - 1:0] q3;
input [AddressWidth - 1:0] address4;
input ce4;
output [DataWidth - 1:0] q4;
td_fused_top_td_fused_axi_in_p_ram td_fused_top_td_fused_axi_in_p_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1),
.addr2(address2),
.ce2(ce2),
.q2(q2),
.addr3(address3),
.ce3(ce3),
.q3(q3),
.addr4(address4),
.ce4(ce4),
.q4(q4)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input clk;
reg [DWIDTH-1:0] ram0[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram1[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram2[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram3[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram0[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram1[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram2[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram2[addr3];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram3[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram3[addr4];
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p (
reset,
clk,
address0,
ce0,
we0,
d0,
address1,
ce1,
q1,
address2,
ce2,
q2,
address3,
ce3,
q3,
address4,
ce4,
q4
);
parameter DataWidth = 32'd16;
parameter AddressRange = 32'd4;
parameter AddressWidth = 32'd2;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
input we0;
input [DataWidth - 1:0] d0;
input [AddressWidth - 1:0] address1;
input ce1;
output [DataWidth - 1:0] q1;
input [AddressWidth - 1:0] address2;
input ce2;
output [DataWidth - 1:0] q2;
input [AddressWidth - 1:0] address3;
input ce3;
output [DataWidth - 1:0] q3;
input [AddressWidth - 1:0] address4;
input ce4;
output [DataWidth - 1:0] q4;
td_fused_top_td_fused_axi_in_p_ram td_fused_top_td_fused_axi_in_p_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.we0(we0),
.d0(d0),
.addr1(address1),
.ce1(ce1),
.q1(q1),
.addr2(address2),
.ce2(ce2),
.q2(q2),
.addr3(address3),
.ce3(ce3),
.q3(q3),
.addr4(address4),
.ce4(ce4),
.q4(q4)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input clk;
reg [DWIDTH-1:0] ram0[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram1[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram2[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram3[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram0[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram1[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram2[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram2[addr3];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram3[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram3[addr4];
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_axi_in_p_ram (
addr0,
ce0,
d0,
we0,
addr1,
ce1,
q1,
addr2,
ce2,
q2,
addr3,
ce3,
q3,
addr4,
ce4,
q4,
clk
);
parameter DWIDTH = 16;
parameter AWIDTH = 2;
parameter MEM_SIZE = 4;
input [AWIDTH-1:0] addr0;
input ce0;
input [DWIDTH-1:0] d0;
input we0;
input [AWIDTH-1:0] addr1;
input ce1;
output reg [DWIDTH-1:0] q1;
input [AWIDTH-1:0] addr2;
input ce2;
output reg [DWIDTH-1:0] q2;
input [AWIDTH-1:0] addr3;
input ce3;
output reg [DWIDTH-1:0] q3;
input [AWIDTH-1:0] addr4;
input ce4;
output reg [DWIDTH-1:0] q4;
input clk;
reg [DWIDTH-1:0] ram0[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram1[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram2[MEM_SIZE-1:0];
reg [DWIDTH-1:0] ram3[MEM_SIZE-1:0];
always @(posedge clk) begin
if (ce0) begin
if (we0) ram0[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce1) begin
q1 <= ram0[addr1];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram1[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce2) begin
q2 <= ram1[addr2];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram2[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce3) begin
q3 <= ram2[addr3];
end
end
always @(posedge clk) begin
if (ce0) begin
if (we0) ram3[addr0] <= d0;
end
end
always @(posedge clk) begin
if (ce4) begin
q4 <= ram3[addr4];
end
end
endmodule
| 6.827284 |
module td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1 (
clk,
reset,
ce,
din0,
din1,
din2,
dout
);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input [din0_WIDTH - 1:0] din0;
input [din1_WIDTH - 1:0] din1;
input [din2_WIDTH - 1:0] din2;
output [dout_WIDTH - 1:0] dout;
td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1_DSP48_0 td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1_DSP48_0_U(
.clk (clk),
.rst (reset),
.ce (ce),
.in0 (din0),
.in1 (din1),
.in2 (din2),
.dout(dout)
);
endmodule
| 6.827284 |
module td_fused_top_mac_muladd_10s_9ns_8ns_16_4_1_DSP48_0 (
input clk,
input rst,
input ce,
input [10 - 1:0] in0,
input [9 - 1:0] in1,
input [8 - 1:0] in2,
output [16 - 1:0] dout
);
wire [27 - 1:0] a;
wire [18 - 1:0] b;
wire [48 - 1:0] c;
wire [45 - 1:0] m;
wire [48 - 1:0] p;
reg [45 - 1:0] m_reg;
reg [27 - 1:0] a_reg;
reg [18 - 1:0] b_reg;
reg [48 - 1:0] p_reg;
assign a = (in0);
assign b = (in1);
assign c = (in2);
assign m = a_reg * b_reg;
assign p = m_reg + c;
always @(posedge clk) begin
if (ce) begin
m_reg <= m;
a_reg <= a;
b_reg <= b;
p_reg <= p;
end
end
assign dout = p_reg;
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd49000;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_final_fmaps_memcore_ram td_fused_top_td_fused_final_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd49000;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_final_fmaps_memcore_ram td_fused_top_td_fused_final_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_final_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 49000;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd3136;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf10_fmaps_memcore_ram td_fused_top_td_fused_tdf10_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd3136;
parameter AddressWidth = 32'd12;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf10_fmaps_memcore_ram td_fused_top_td_fused_tdf10_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf10_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 12;
parameter MEM_SIZE = 3136;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd50176;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf1_fmaps_memcore_ram td_fused_top_td_fused_tdf1_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd50176;
parameter AddressWidth = 32'd16;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf1_fmaps_memcore_ram td_fused_top_td_fused_tdf1_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf1_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 16;
parameter MEM_SIZE = 50176;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd25088;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf3_fmaps_memcore_ram td_fused_top_td_fused_tdf3_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd25088;
parameter AddressWidth = 32'd15;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf3_fmaps_memcore_ram td_fused_top_td_fused_tdf3_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf3_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 15;
parameter MEM_SIZE = 25088;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd12544;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf4_fmaps_memcore_ram td_fused_top_td_fused_tdf4_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd12544;
parameter AddressWidth = 32'd14;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf4_fmaps_memcore_ram td_fused_top_td_fused_tdf4_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf4_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 14;
parameter MEM_SIZE = 12544;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd6272;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf7_fmaps_memcore_ram td_fused_top_td_fused_tdf7_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore (
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
we1,
d1
);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd6272;
parameter AddressWidth = 32'd13;
input reset;
input clk;
input [AddressWidth - 1:0] address0;
input ce0;
output [DataWidth - 1:0] q0;
input [AddressWidth - 1:0] address1;
input ce1;
input we1;
input [DataWidth - 1:0] d1;
td_fused_top_td_fused_tdf7_fmaps_memcore_ram td_fused_top_td_fused_tdf7_fmaps_memcore_ram_U (
.clk(clk),
.addr0(address0),
.ce0(ce0),
.q0(q0),
.addr1(address1),
.ce1(ce1),
.we1(we1),
.d1(d1)
);
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module td_fused_top_td_fused_tdf7_fmaps_memcore_ram (
addr0,
ce0,
q0,
addr1,
ce1,
d1,
we1,
clk
);
parameter DWIDTH = 64;
parameter AWIDTH = 13;
parameter MEM_SIZE = 6272;
input [AWIDTH-1:0] addr0;
input ce0;
output wire [DWIDTH-1:0] q0;
input [AWIDTH-1:0] addr1;
input ce1;
input [DWIDTH-1:0] d1;
input we1;
input clk;
reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
wire [AWIDTH-1:0] addr0_t0;
reg [AWIDTH-1:0] addr0_t1;
reg [DWIDTH-1:0] q0_t0;
reg [DWIDTH-1:0] q0_t1;
wire [AWIDTH-1:0] addr1_t0;
reg [AWIDTH-1:0] addr1_t1;
wire [DWIDTH-1:0] d1_t0;
wire we1_t0;
reg [DWIDTH-1:0] d1_t1;
reg we1_t1;
assign addr0_t0 = addr0;
assign q0 = q0_t1;
assign addr1_t0 = addr1;
assign d1_t0 = d1;
assign we1_t0 = we1;
always @(posedge clk) begin
if (ce0) begin
addr0_t1 <= addr0_t0;
q0_t1 <= q0_t0;
end
if (ce1) begin
addr1_t1 <= addr1_t0;
d1_t1 <= d1_t0;
we1_t1 <= we1_t0;
end
end
always @(posedge clk) begin
if (ce0) begin
q0_t0 <= ram[addr0_t1];
end
end
always @(posedge clk) begin
if (ce1) begin
if (we1_t1) ram[addr1_t1] <= d1_t1;
end
end
endmodule
| 6.827284 |
module teater ();
reg clock, nreset, d;
DFlipFlop D1 (
q,
clock,
nreset,
d
);
always #10 clock = ~clock;
initial begin
//$dumpfile("testDFlipFlop.dump");
//$dumpvars(1,D1);
#0 d = 0;
clock = 0;
nreset = 0;
#50 nreset = 1;
#1000 $finish;
end
always #8 d = ~d;
endmodule
| 7.39571 |
module tea_decryptor_core #(
parameter DELTA = 32'h9E3779B9
) (
input wire resetn
, input wire clk
, input wire [127:0] key
, input wire [ 63:0] textI
, input wire textI_vld
, output wire [ 63:0] textO
, output wire textO_vld
);
//-----------------------------------------------------
wire [31:0] key0 = key[ 31: 0];
wire [31:0] key1 = key[ 63:32];
wire [31:0] key2 = key[ 95:64];
wire [31:0] key3 = key[127:96];
reg [63:0] vld;
reg [31:0] sum [0:63];
reg [31:0] textOy[0:63];
reg [31:0] textOz[0:63];
integer idx;
//-----------------------------------------------------
always @(posedge clk or negedge resetn) begin
if (~resetn) begin
for (idx = 0; idx < 64; idx = idx + 1) begin
vld [idx] <= 1'b0;
textOy[idx] <= 32'h0;
textOz[idx] <= 32'h0;
sum [idx] <= 32'h0;
end
end else begin
vld[0] <= textI_vld;
textOz[0] <= textI[63:32]
- ( ((textI[31:0] << 4)+key2)
^ ( textI[31:0]+(DELTA<<5))
^ ((textI[31:0] >> 5)+key3));
textOy[0] <= textI[31:0];
sum[0] <= DELTA << 5;
for (idx = 1; idx < 64; idx = idx + 1) begin
vld[idx] <= vld[idx-1];
if (idx[0] == 1'b1) begin
textOy[idx] <= textOy[idx-1]
- ( ((textOz[idx-1] << 4)+key0)
^ ( textOz[idx-1]+sum[idx-1])
^ ((textOz[idx-1] >> 5)+key1));
textOz[idx] <= textOz[idx-1];
sum[idx] <= sum[idx-1] - DELTA;
end else begin
textOy[idx] <= textOy[idx-1];
textOz[idx] <= textOz[idx-1]
- ( ((textOy[idx-1] << 4)+key2)
^ ( textOy[idx-1]+sum[idx-1])
^ ((textOy[idx-1] >> 5)+key3));
sum[idx] <= sum[idx-1];
end
end
end // if
end // always
//-----------------------------------------------------
assign textO_vld = vld[63];
assign textO = {textOz[63], textOy[63]};
endmodule
| 6.93617 |
module tea_decryptor_stream
#(parameter STREAM_WIDTH_DATA=64
, STREAM_WIDTH_DS=(STREAM_WIDTH_DATA/8)
, STREAM_WIDTH_TID=8
, STREAM_WIDTH_TDEST=3
, STREAM_WIDTH_TUSER=1
, TEA_KEY=128'hABAB_ABAB_ABAB_ABAB_ABAB_ABAB_ABAB_ABAB
, DELTA=32'h9E3779B9
)
(
input wire ARESETn
, input wire ACLK
//--------------------------------------------------
, output wire S_TREADY
, input wire S_TVALID
, input wire [STREAM_WIDTH_DATA-1:0] S_TDATA
, input wire [STREAM_WIDTH_DS-1:0] S_TSTRB
, input wire [STREAM_WIDTH_DS-1:0] S_TKEEP
, input wire S_TLAST
, input wire [STREAM_WIDTH_TID-1:0] S_TID
, input wire [STREAM_WIDTH_TDEST-1:0] S_TDEST
`ifdef AMBA_AXI_TUSER
, input wire [STREAM_WIDTH_TUSER-1:0] S_TUSER
`endif
//----------------------------------------------------
, input wire M_TREADY
, output wire M_TVALID
, output wire [STREAM_WIDTH_DATA-1:0] M_TDATA
, output wire [STREAM_WIDTH_DS-1:0] M_TSTRB
, output wire [STREAM_WIDTH_DS-1:0] M_TKEEP
, output wire M_TLAST
, output wire [STREAM_WIDTH_TID-1:0] M_TID
, output wire [STREAM_WIDTH_TDEST-1:0] M_TDEST
`ifdef AMBA_AXI_TUSER
, output wire [STREAM_WIDTH_TUSER-1:0] M_TUSER
`endif
//--------------------------------------------------
);
//-----------------------------------------------------
.....
//-----------------------------------------------------
endmodule
| 6.93617 |
module tea_encryptor_core #(
parameter DELTA = 32'h9E3779B9
) (
input resetn
, input clk
, input wire [127:0] key
, input wire [ 63:0] textI
, input wire textI_vld
, output wire [ 63:0] textO
, output wire textO_vld
);
//-----------------------------------------------------
wire [31:0] key0 = key[ 31: 0];
wire [31:0] key1 = key[ 63:32];
wire [31:0] key2 = key[ 95:64];
wire [31:0] key3 = key[127:96];
reg [63:0] vld;
reg [31:0] sum [0:63];
reg [31:0] textOy[0:63];
reg [31:0] textOz[0:63];
integer idx;
//-----------------------------------------------------
always @(posedge clk or negedge resetn) begin
if (~resetn) begin
for (idx = 0; idx < 64; idx = idx + 1) begin
vld [idx] <= 1'b0;
textOy[idx] <= 32'h0;
textOz[idx] <= 32'h0;
sum [idx] <= 32'h0;
end
end else begin
vld[0] <= textI_vld;
textOy[0] <= textI[31:0]
+ ( ((textI[63:32]<<4)+key0)
^ ( textI[63:32]+DELTA)
^ ((textI[63:32]>>5)+key1));
textOz[0] <= textI[63:32];
sum[0] <= DELTA;
for (idx = 1; idx < 64; idx = idx + 1) begin
vld[idx] <= vld[idx-1];
if (idx[0] == 1'b1) begin
textOz[idx] <= textOz[idx-1]
+ ( ((textOy[idx-1]<<4)+key2)
^ ( textOy[idx-1]+sum[idx-1])
^ ((textOy[idx-1] >> 5)+key3));
textOy[idx] <= textOy[idx-1];
sum[idx] <= sum[idx-1] + DELTA;
end else begin
textOz[idx] <= textOz[idx-1];
textOy[idx] <= textOy[idx-1]
+ ( ((textOz[idx-1]<<4)+key0)
^ ( textOz[idx-1]+sum[idx-1])
^ ((textOz[idx-1]>>5)+key1));
sum[idx] <= sum[idx-1];
end
end
end // if
end // always
//-----------------------------------------------------
assign textO_vld = vld[63];
assign textO = {textOz[63], textOy[63]};
//-----------------------------------------------------
endmodule
| 6.740986 |
module tea_encryptor_stream
#(parameter STREAM_WIDTH_DATA=64
, STREAM_WIDTH_DS=(STREAM_WIDTH_DATA/8)
, STREAM_WIDTH_TID=8
, STREAM_WIDTH_TDEST=3
, STREAM_WIDTH_TUSER=1
, TEA_KEY=128'hABAB_ABAB_ABAB_ABAB_ABAB_ABAB_ABAB_ABAB
, DELTA=32'h9E3779B9
)
(
input wire ARESETn
, input wire ACLK
//--------------------------------------------------
, output wire S_TREADY
, input wire S_TVALID
, input wire [STREAM_WIDTH_DATA-1:0] S_TDATA
, input wire [STREAM_WIDTH_DS-1:0] S_TSTRB
, input wire [STREAM_WIDTH_DS-1:0] S_TKEEP
, input wire S_TLAST
, input wire [STREAM_WIDTH_TID-1:0] S_TID
, input wire [STREAM_WIDTH_TDEST-1:0] S_TDEST
`ifdef AMBA_AXI_TUSER
, input wire [STREAM_WIDTH_TUSER-1:0] S_TUSER
`endif
//----------------------------------------------------
, input wire M_TREADY
, output wire M_TVALID
, output wire [STREAM_WIDTH_DATA-1:0] M_TDATA
, output wire [STREAM_WIDTH_DS-1:0] M_TSTRB
, output wire [STREAM_WIDTH_DS-1:0] M_TKEEP
, output wire M_TLAST
, output wire [STREAM_WIDTH_TID-1:0] M_TID
, output wire [STREAM_WIDTH_TDEST-1:0] M_TDEST
`ifdef AMBA_AXI_TUSER
, output wire [STREAM_WIDTH_TUSER-1:0] M_TUSER
`endif
//--------------------------------------------------
);
//-----------------------------------------------------
...
//-----------------------------------------------------
endmodule
| 6.740986 |
module _90_fa (
A,
B,
C,
X,
Y
);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B, C;
output [WIDTH-1:0] X, Y;
wire [WIDTH-1:0] t1, t2, t3;
assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
assign Y = t1 ^ C, X = t2 | t3;
endmodule
| 7.517837 |
module _90_lcu (
P,
G,
CI,
CO
);
parameter WIDTH = 2;
input [WIDTH-1:0] P, G;
input CI;
output [WIDTH-1:0] CO;
integer i, j;
reg [WIDTH-1:0] p, g;
wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
always @* begin
p = P;
g = G;
// in almost all cases CI will be constant zero
g[0] = g[0] | (p[0] & CI);
// [[CITE]] Brent Kung Adder
// R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders",
// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
// Main tree
for (i = 1; i <= $clog2(WIDTH); i = i + 1) begin
for (j = 2 ** i - 1; j < WIDTH; j = j + 2 ** i) begin
g[j] = g[j] | p[j] & g[j-2**(i-1)];
p[j] = p[j] & p[j-2**(i-1)];
end
end
// Inverse tree
for (i = $clog2(WIDTH); i > 0; i = i - 1) begin
for (j = 2 ** i + 2 ** (i - 1) - 1; j < WIDTH; j = j + 2 ** i) begin
g[j] = g[j] | p[j] & g[j-2**(i-1)];
p[j] = p[j] & p[j-2**(i-1)];
end
end
end
assign CO = g;
endmodule
| 7.065403 |
module _90_alu (
A,
B,
CI,
BI,
X,
Y,
CO
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH-1:0] CO;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(
.A_SIGNED(A_SIGNED),
.A_WIDTH (A_WIDTH),
.Y_WIDTH (Y_WIDTH)
) A_conv (
.A(A),
.Y(A_buf)
);
\$pos #(
.A_SIGNED(B_SIGNED),
.A_WIDTH (B_WIDTH),
.Y_WIDTH (Y_WIDTH)
) B_conv (
.A(B),
.Y(B_buf)
);
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
\$lcu #(
.WIDTH(Y_WIDTH)
) lcu (
.P (X),
.G (AA & BB),
.CI(CI),
.CO(CO)
);
assign X = AA ^ BB;
assign Y = X ^ {CO, CI};
endmodule
| 7.174058 |
module \$__div_mod_u (
A,
B,
Y,
R
);
parameter WIDTH = 1;
input [WIDTH-1:0] A, B;
output [WIDTH-1:0] Y, R;
wire [WIDTH*WIDTH-1:0] chaindata;
assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
genvar i;
generate
begin
for (i = 0; i < WIDTH; i = i + 1) begin : stage
wire [WIDTH-1:0] stage_in;
if (i == 0) begin : cp
assign stage_in = A;
end else begin : cp
assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
end
assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH - (i + 1) {1'b0}}};
assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
end
end
endgenerate
endmodule
| 7.101288 |
module \$__div_mod (
A,
B,
Y,
R
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
localparam WIDTH =
A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y, R;
wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(
.A_SIGNED(A_SIGNED),
.A_WIDTH (A_WIDTH),
.Y_WIDTH (WIDTH)
) A_conv (
.A(A),
.Y(A_buf)
);
\$pos #(
.A_SIGNED(B_SIGNED),
.A_WIDTH (B_WIDTH),
.Y_WIDTH (WIDTH)
) B_conv (
.A(B),
.Y(B_buf)
);
wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
\$__div_mod_u #(
.WIDTH(WIDTH)
) div_mod_u (
.A(A_buf_u),
.B(B_buf_u),
.Y(Y_u),
.R(R_u)
);
assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
endmodule
| 6.657259 |
module _90_pow (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
wire _TECHMAP_FAIL_ = 1;
endmodule
| 6.825399 |
module _90_pmux (
A,
B,
S,
Y
);
parameter WIDTH = 1;
parameter S_WIDTH = 1;
input [WIDTH-1:0] A;
input [WIDTH*S_WIDTH-1:0] B;
input [S_WIDTH-1:0] S;
output [WIDTH-1:0] Y;
wire [WIDTH-1:0] Y_B;
genvar i, j;
generate
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
for (i = 0; i < S_WIDTH; i = i + 1) begin : B_AND
assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
end : B_AND
for (i = 0; i < WIDTH; i = i + 1) begin : B_OR
wire [S_WIDTH-1:0] B_AND_BITS;
for (j = 0; j < S_WIDTH; j = j + 1) begin : B_AND_BITS_COLLECT
assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
end : B_AND_BITS_COLLECT
assign Y_B[i] = |B_AND_BITS;
end : B_OR
endgenerate
assign Y = |S ? Y_B : A;
endmodule
| 7.254615 |
module \$add (
A,
B,
Y
);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if ((A_WIDTH == 32) && (B_WIDTH == 32)) begin
wire [16:0] S1 = A[15:0] + B[15:0];
wire [15:0] S2 = A[31:16] + B[31:16] + S1[16];
assign Y = {S2[15:0], S1[15:0]};
end else wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
| 7.120414 |
module TecladoPS2_Interface (
input iCLK,
input iCLK_50,
input Reset,
inout PS2_KBCLK,
inout PS2_KBDAT,
// Barramento de IO
input wReadEnable,
wWriteEnable,
input [ 3:0] wByteEnable,
input [31:0] wAddress,
wWriteData,
output [31:0] wReadData,
// Para o Coprocessador 0 - Interrupcao
output reg ps2_scan_ready_clock,
output reg keyboard_interrupt
);
wire [7:0] PS2scan_code;
reg [7:0] PS2history[7:0]; // buffer de 8 bytes
wire PS2read, PS2scan_ready;
oneshot pulser (
.pulse_out(PS2read),
.trigger_in(PS2scan_ready),
.clk(iCLK_50)
);
keyboard kbd (
.keyboard_clk(PS2_KBCLK),
.keyboard_data(PS2_KBDAT),
.clock50(iCLK_50),
.reset(Reset),
.read(PS2read),
.scan_ready(PS2scan_ready),
.scan_code(PS2scan_code)
);
//reg ps2_scan_ready_clock;
//reg keyboard_interrupt;
always @(posedge PS2scan_ready) ps2_scan_ready_clock <= ~ps2_scan_ready_clock;
always @(posedge iCLK) keyboard_interrupt <= ps2_scan_ready_clock;
always @(posedge PS2scan_ready, posedge Reset) begin
if (Reset) begin
PS2history[7] <= 8'b0;
PS2history[6] <= 8'b0;
PS2history[5] <= 8'b0;
PS2history[4] <= 8'b0;
PS2history[3] <= 8'b0;
PS2history[2] <= 8'b0;
PS2history[1] <= 8'b0;
PS2history[0] <= 8'b0;
end else begin
PS2history[7] <= PS2history[6];
PS2history[6] <= PS2history[5];
PS2history[5] <= PS2history[4];
PS2history[4] <= PS2history[3];
PS2history[3] <= PS2history[2];
PS2history[2] <= PS2history[1];
PS2history[1] <= PS2history[0];
PS2history[0] <= PS2scan_code;
end
end
always @(*)
if (wReadEnable) begin
if (wAddress == BUFFER0_TECLADO_ADDRESS)
wReadData = {PS2history[3], PS2history[2], PS2history[1], PS2history[0]};
else if (wAddress == BUFFER1_TECLADO_ADDRESS)
wReadData = {PS2history[7], PS2history[6], PS2history[5], PS2history[4]};
else wReadData = 32'hzzzzzzzz;
end else wReadData = 32'hzzzzzzzz;
endmodule
| 6.778261 |
module teclado_conta (
lin,
col,
bot_press,
s
);
/*Tratando o teclado como uma matriz 4x4, como abaixo
1 2 3 A
4 5 6 B
7 8 9 C
* 0 # D
Cada botao pode ser representado por duas "coordenadas",
no caso, linha e coluna da matriz*/
input [3:0] lin, col;
input bot_press;
output [11:0] s;
reg [11:0] s;
reg [3:0] uni, dez, cent;
reg [1:0] aux = 2'b00;
always @(posedge bot_press) begin
aux = aux + 1;
if (lin == 1 && col == 2) //"Enter" (lin = 0001 e col = 0010)
begin
aux = 0;
s = {cent, dez, uni}; //Concatena os numeros
uni = 0;
dez = 0; //Retorna os valores a 0 para que outro numero possa ser digitado
cent = 0;
end
if (lin == 1 && col == 4) //Zero (lin = 0001 e col = 0100)
begin
if (aux == 1) begin
uni = 0;
end
if (aux == 2) begin
dez = 0;
end
if (aux == 3) begin
cent = 0;
end
end
if (lin == 8 && col == 8) //Um (lin = 1000 e col = 1000)
begin
if (aux == 1) begin
uni = 1;
end
if (aux == 2) begin
dez = 1;
end
if (aux == 3) begin
cent = 1;
end
end
if (lin == 8 && col == 4) //Dois (lin = 1000 e col = 0100)
begin
if (aux == 1) begin
uni = 2;
end
if (aux == 2) begin
dez = 2;
end
if (aux == 3) begin
cent = 2;
end
end
if (lin == 8 && col == 2) //Tres (lin = 1000 e col = 0010)
begin
if (aux == 1) begin
uni = 3;
end
if (aux == 2) begin
dez = 3;
end
if (aux == 3) begin
cent = 3;
end
end
if (lin == 4 && col == 8) //Quatro (lin = 0100 e col = 1000)
begin
if (aux == 1) begin
uni = 4;
end
if (aux == 2) begin
dez = 4;
end
if (aux == 3) begin
cent = 4;
end
end
if (lin == 4 && col == 4) //Cinco (lin = 0100 e col = 0100)
begin
if (aux == 1) begin
uni = 5;
end
if (aux == 2) begin
dez = 5;
end
if (aux == 3) begin
cent = 5;
end
end
if (lin == 4 && col == 2) //Seis (lin = 0100 e col = 0010)
begin
if (aux == 1) begin
uni = 6;
end
if (aux == 2) begin
dez = 6;
end
if (aux == 3) begin
cent = 6;
end
end
if (lin == 2 && col == 8) //Sete (lin = 0010 e col = 1000)
begin
if (aux == 1) begin
uni = 7;
end
if (aux == 2) begin
dez = 7;
end
if (aux == 3) begin
cent = 7;
end
end
if (lin == 2 && col == 4) //Oito (lin = 0010 e col = 0100)
begin
if (aux == 1) begin
uni = 8;
end
if (aux == 2) begin
dez = 8;
end
if (aux == 3) begin
cent = 8;
end
end
if (lin == 2 && col == 2) //Nove (lin = 0010 e col = 0010)
begin
if (aux == 1) begin
uni = 9;
end
if (aux == 2) begin
dez = 9;
end
if (aux == 3) begin
cent = 9;
end
end
end
endmodule
| 6.829625 |
module Teller (
teller,
tcount
);
input [2:0] teller;
output wire [1:0] tcount;
// Sum is tcount[0]
// S = A ^ B ^ C
assign tcount[0] = teller[0] ^ teller[1] ^ teller[2];
// Carry is the tcount[1]
// Carry = AB + ACin + BCin
assign tcount[1] = (teller[0] & teller[1]) + (teller[2] & teller[1]) + (teller[0] & teller[2]);
endmodule
| 7.39674 |
module holds the Verilog component declaration for temac1
* (the Tri-Mode MAC core).
* Copyright 2003 Xilinx Inc.
*/
/****************************************************************************
* Component Declaration for trimac (the Tri-Mode MAC core).
****************************************************************************/
module temac1
( reset,
emacphytxd,
emacphytxen,
emacphytxer,
phyemaccrs,
phyemaccol,
phyemacrxd,
phyemacrxdv,
phyemacrxer,
clientemactxd,
clientemactxdvld,
emacclienttxack,
clientemactxunderrun,
emacclienttxcollision,
emacclienttxretransmit,
clientemactxifgdelay,
clientemacpausereq,
clientemacpauseval,
emacclientrxd,
emacclientrxdvld,
emacclientrxgoodframe,
emacclientrxbadframe,
tieemacconfigvec,
txcoreclk,
rxcoreclk,
txgmiimiiclk,
rxgmiimiiclk,
speedis100,
speedis10100,
corehassgmii
);
// Port declarations
input reset;
output [7:0] emacphytxd;
output emacphytxen;
output emacphytxer;
input phyemaccrs;
input phyemaccol;
input [7:0] phyemacrxd;
input phyemacrxdv;
input phyemacrxer;
input [7:0] clientemactxd;
input clientemactxdvld;
output emacclienttxack;
input clientemactxunderrun;
output emacclienttxcollision;
output emacclienttxretransmit;
input [7:0] clientemactxifgdelay;
input clientemacpausereq;
input [15:0] clientemacpauseval;
output [7:0] emacclientrxd;
output emacclientrxdvld;
output emacclientrxgoodframe;
output emacclientrxbadframe;
input [66:0] tieemacconfigvec;
input txcoreclk;
input rxcoreclk;
input txgmiimiiclk;
input rxgmiimiiclk;
output speedis100;
output speedis10100;
input corehassgmii;
endmodule
| 7.998157 |
module iiitb_cps (
input clk,
reset_n,
input sensor_entrance,
sensor_exit,
input [1:0] password_1,
password_2,
output wire GREEN_LED,
RED_LED,
output reg [6:0] HEX_1,
HEX_2
);
parameter IDLE = 3'b000, WAIT_PASSWORD = 3'b001, WRONG_PASS = 3'b010, RIGHT_PASS = 3'b011,STOP = 3'b100;
// Moore FSM : output just depends on the current state
reg [2:0] current_state, next_state;
reg [31:0] counter_wait;
reg red_tmp, green_tmp;
// Next state
always @(posedge clk or negedge reset_n) begin
if (~reset_n) current_state = IDLE;
else current_state = next_state;
end
// counter_wait
always @(posedge clk or negedge reset_n) begin
if (~reset_n) counter_wait <= 0;
else if (current_state == WAIT_PASSWORD) counter_wait <= counter_wait + 1;
else counter_wait <= 0;
end
// change state
// fpga4student.com FPGA projects, Verilog projects, VHDL projects
always @(*) begin
case (current_state)
IDLE: begin
if (sensor_entrance == 1) next_state = WAIT_PASSWORD;
else next_state = IDLE;
end
WAIT_PASSWORD: begin
if (counter_wait <= 3) next_state = WAIT_PASSWORD;
else begin
if ((password_1 == 2'b01) && (password_2 == 2'b10)) next_state = RIGHT_PASS;
else next_state = WRONG_PASS;
end
end
WRONG_PASS: begin
if ((password_1 == 2'b01) && (password_2 == 2'b10)) next_state = RIGHT_PASS;
else next_state = WRONG_PASS;
end
RIGHT_PASS: begin
if (sensor_entrance == 1 && sensor_exit == 1) next_state = STOP;
else if (sensor_exit == 1) next_state = IDLE;
else next_state = RIGHT_PASS;
end
STOP: begin
if ((password_1 == 2'b01) && (password_2 == 2'b10)) next_state = RIGHT_PASS;
else next_state = STOP;
end
default: next_state = IDLE;
endcase
end
// LEDs and output, change the period of blinking LEDs here
always @(posedge clk) begin
case (current_state)
IDLE: begin
green_tmp = 1'b0;
red_tmp = 1'b0;
HEX_1 = 7'b1111111; // off
HEX_2 = 7'b1111111; // off
end
WAIT_PASSWORD: begin
green_tmp = 1'b0;
red_tmp = 1'b1;
HEX_1 = 7'b000_0110; // E
HEX_2 = 7'b010_1011; // n
end
WRONG_PASS: begin
green_tmp = 1'b0;
red_tmp = ~red_tmp;
HEX_1 = 7'b000_0110; // E
HEX_2 = 7'b000_0110; // E
end
RIGHT_PASS: begin
green_tmp = ~green_tmp;
red_tmp = 1'b0;
HEX_1 = 7'b000_0010; // 6
HEX_2 = 7'b100_0000; // 0
end
STOP: begin
green_tmp = 1'b0;
red_tmp = ~red_tmp;
HEX_1 = 7'b001_0010; // 5
HEX_2 = 7'b000_1100; // P
end
endcase
end
assign RED_LED = red_tmp;
assign GREEN_LED = green_tmp;
endmodule
| 8.117646 |
module: TemperatureAnalyzer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tempAnalizerTest;
// Inputs
reg [7:0] temperature;
// Outputs
wire temperatureAbnormality;
// Instantiate the Unit Under Test (UUT)
TemperatureAnalyzer uut (
.temperature(temperature),
.temperatureAbnormality(temperatureAbnormality)
);
initial begin
// Initialize Inputs
temperature = 8'b00011111;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
temperature = 8'b00100100;
#100;
end
endmodule
| 9.080435 |
module tempCont (
input clk_i, //@100 MHz
input rst_i,
input [7:0] temp_i,
input [2:0] tempCase_i, //40, 70, 100, 127, 150
output PWM_o //30-120 Hz.
);
reg [19:0] div = 20'b0;
reg [19:0] maxCount = 20'b0;
reg [1:0] statePulse = 2'b0;
reg rst = 1'b0;
always @(posedge clk_i) begin //Detect crossover FSM
case (statePulse)
2'b0: begin
rst <= 1'b0;
if (!rst_i) statePulse <= 2'b1;
else statePulse <= 2'b0;
end
2'b1: begin
rst <= 1'b1;
statePulse <= 2'b10;
end
2'b10: begin
rst <= 1'b0;
if (!rst_i) statePulse <= 2'b10;
else statePulse <= 2'b0;
end
default: begin
rst <= 1'b0;
statePulse <= 2'b00;
end
endcase
end
always @(posedge clk_i, posedge rst) begin
if (rst) div <= 20'h0;
else if (!div[19]) div <= div + 1'b1;
end
assign PWM_o = (div < maxCount);
reg [7:0] tempS = 8'b0; //Desired temperatures
always @(tempCase_i) begin
case (tempCase_i)
3'h1: tempS <= 8'h28; //40°C
3'h2: tempS <= 8'h46; //70°C
3'h3: tempS <= 8'h64; //100°C
3'h4: tempS <= 8'h7F; //127°C
3'h5: tempS <= 8'h96; //150°C
default: tempS <= 8'h00;
endcase
end
reg [25:0] masterDiv = 26'b0;
always @(posedge clk_i) masterDiv <= masterDiv + 1'b1;
always @(posedge masterDiv[17]) begin //On/Off control with small Duty Cycle.
if ((tempS == 8'h00) || (tempS <= temp_i)) maxCount <= 20'b0;
else maxCount <= 20'h1000;
end
endmodule
| 8.711436 |
module NextStateAddressSelector (
output reg [1:0] M,
input [2:0] N,
input Sts
);
always @(N, Sts) begin
case (N)
3'b000: M = 2'b00; // Encoder
3'b001: if (Sts == 0) M = 2'b01; // 1
else M = 2'b10; // Control Register
3'b010: M = 2'b10; // Control Register
3'b011: M = 2'b11; // Incrementer
3'b100: if (Sts == 1) M = 2'b00; // Encoder
else M = 2'b10; // Control Register
3'b101: if (Sts == 1) M = 2'b10; // Control Register
else M = 2'b11; // Incrementer
3'b110: if (Sts == 1) M = 2'b00; // Encoder
else M = 2'b11; // Incrementer
3'b111: M = 2'b00; //Encoder
endcase
end
endmodule
| 7.265287 |
module Adder (
output reg [5:0] Out,
input [5:0] In
);
always @(In) begin
Out = In + 6'b000001;
end
endmodule
| 6.893856 |
module IncrementRegister (
output reg [5:0] Out,
input [5:0] In,
input Clk
);
always @(posedge Clk) begin
Out = In;
end
endmodule
| 6.680637 |
module Inverter (
output reg InvOut,
input In,
VarInv
);
always @(In, VarInv)
case (VarInv)
1'b0: if (In == 0) InvOut = 0;
else InvOut = 1;
1'b1: if (In == 1) InvOut = 0;
else InvOut = 1;
endcase
endmodule
| 7.198219 |
module InverterMux (
output reg InvIn,
input MOC,
Cond,
unsignee,
double,
load,
EntrySix,
Entryseven,
Entryeight,
input [2:0] S
);
always @(S, MOC, Cond) begin
case (S)
3'b000: InvIn = MOC;
3'b001: InvIn = Cond;
3'b010: InvIn = unsignee;
3'b011: InvIn = double;
3'b100: InvIn = load;
3'b101: InvIn = EntrySix;
3'b110: InvIn = Entryseven;
3'b111: InvIn = Entryeight;
endcase
end
endmodule
| 7.278959 |
module ControlRegister (
output reg [5:0] state,
output reg FR,
RF,
IR,
MAR,
MDR,
ReadWrite,
MOV,
MD,
ME,
Inv,
output reg [1:0] MA,
output reg [1:0] MB,
output reg [1:0] MC,
output reg [4:0] OP,
output reg [5:0] CR,
output reg [2:0] N,
output reg [2:0] S,
input FR_IN,
RF_IN,
IR_IN,
MAR_IN,
MDR_IN,
ReadWrite_IN,
MOV_IN,
MD_IN,
ME_IN,
Inv_IN,
input [1:0] MA_IN,
input [1:0] MB_IN,
input [1:0] MC_IN,
input [4:0] OP_IN,
input [5:0] CR_IN,
input [2:0] N_IN,
input [2:0] S_IN,
input Clk,
input [5:0] state_in
);
always @(posedge Clk) begin
FR = FR_IN;
RF = RF_IN;
IR = IR_IN;
MAR = MAR_IN;
MDR = MDR_IN;
ReadWrite = ReadWrite_IN;
MOV = MOV_IN;
MA = MA_IN;
MB = MB_IN;
MC = MC_IN;
MD = MD_IN;
ME = ME_IN;
OP = OP_IN;
Inv = Inv_IN;
CR = CR_IN;
N = N_IN;
S = S_IN;
state = state_in;
end
endmodule
| 6.822423 |
module temperature #(
parameter WIDTH = 32,
parameter S_WIDTH_A = 1
) (
input clk, // Must be less than 80 MHz, should be greater than 20 MHz
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH-1:0] slave_writedata,
input slave_read,
input slave_write,
input [WIDTH/8-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH-1:0] slave_readdata,
output slave_readdatavalid
);
localparam DIVIDER = 80;
wire tsdcaldone;
wire [7:0] tsdcalo;
temp_sense temp (
.ce(slave_read),
.clk(clk),
.clr(!slave_read),
.tsdcaldone(tsdcaldone),
.tsdcalo(tsdcalo)
);
assign slave_waitrequest = slave_read && !tsdcaldone;
assign slave_readdata = {{WIDTH - 8{1'b0}}, tsdcalo} - 32'h080; // Convert to Celsius
assign slave_readdatavalid = slave_read && tsdcaldone;
endmodule
| 8.072365 |
module tb_temperatureAbnormalityDetector ();
reg [4:0] factoryBaseTemp;
reg [3:0] factoryTempCoef;
reg [3:0] tempSensorValue;
wire hightemprature;
wire lowtemprature;
temperatureAbnormalityDetector tad (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
lowtemprature,
hightemprature
);
initial begin
factoryBaseTemp <= 5'b11111;
factoryTempCoef <= 4'b1000;
tempSensorValue <= 4'b0000;
#10;
tempSensorValue <= 4'b0001;
#10;
tempSensorValue <= 4'b0010;
#10;
tempSensorValue <= 4'b0011;
#10;
tempSensorValue <= 4'b0100;
#10;
tempSensorValue <= 4'b0101;
#10;
tempSensorValue <= 4'b0110;
#10;
tempSensorValue <= 4'b0111;
#10;
tempSensorValue <= 4'b1000;
#10;
tempSensorValue <= 4'b1001;
#10;
tempSensorValue <= 4'b1010;
#10;
tempSensorValue <= 4'b1011;
#10;
tempSensorValue <= 4'b1100;
#10;
tempSensorValue <= 4'b1101;
#10;
tempSensorValue <= 4'b1110;
#10;
tempSensorValue <= 4'b1111;
#10;
$finish;
end
endmodule
| 7.590233 |
module temperatureAbnormalityDetector (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
lowTempAbnormality,
highTempAbnormality
);
input [4:0] factoryBaseTemp;
input [3:0] factoryTempCoef;
input [3:0] tempSensorValue;
output lowTempAbnormality;
output highTempAbnormality;
wire [7:0] tmp;
temperatureCalculator c (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
tmp
);
temperatureAnalyzer z (
tmp,
highTempAbnormality,
lowTempAbnormality
);
endmodule
| 7.663437 |
module tb_temperatureAnalyzer ();
reg [7:0] t;
wire ht;
wire lt;
temperatureAnalyzer a (
t,
ht,
lt
);
initial begin
t = 7'b0000000;
#10;
t = 7'b0000001;
#10;
t = 7'b0000010;
#10;
t = 7'b0000011;
#10;
t = 7'b0000100;
#10;
t = 7'b0000101;
#10;
t = 7'b0000110;
#10;
t = 7'b0000111;
#10;
t = 7'b0001000;
#10;
t = 7'b0001001;
#10;
t = 7'b0001010;
#10;
t = 7'b0001011;
#10;
t = 7'b0001100;
#10;
t = 7'b0001101;
#10;
t = 7'b0001110;
#10;
t = 7'b0001111;
#10;
t = 7'b0010000;
#10;
t = 7'b0010001;
#10;
t = 7'b0010010;
#10;
t = 7'b0010011;
#10;
t = 7'b0010100;
#10;
t = 7'b0010101;
#10;
t = 7'b0010110;
#10;
t = 7'b0010111;
#10;
t = 7'b0011000;
#10;
t = 7'b0011001;
#10;
t = 7'b0011010;
#10;
t = 7'b0011011;
#10;
t = 7'b0011100;
#10;
t = 7'b0011101;
#10;
t = 7'b0011110;
#10;
t = 7'b0011111;
#10;
t = 7'b0100000;
#10;
t = 7'b0100001;
#10;
t = 7'b0100010;
#10;
t = 7'b0100011;
#10;
t = 7'b0100100;
#10;
t = 7'b0100101;
#10;
t = 7'b0100110;
#10;
t = 7'b0100111;
#10;
t = 7'b0101000;
#10;
t = 7'b0101001;
#10;
t = 7'b0101010;
#10;
t = 7'b0101011;
#10;
t = 7'b0101100;
#10;
t = 7'b0101101;
#10;
t = 7'b0101110;
#10;
t = 7'b0101111;
#10;
t = 7'b0110000;
#10;
t = 7'b0110001;
#10;
t = 7'b0110010;
#10;
t = 7'b0110011;
#10;
t = 7'b0110100;
#10;
t = 7'b0110101;
#10;
t = 7'b0110110;
#10;
t = 7'b0110111;
#10;
t = 7'b0111000;
#10;
t = 7'b0111001;
#10;
t = 7'b0111010;
#10;
t = 7'b0111011;
#10;
t = 7'b0111100;
#10;
t = 7'b0111101;
#10;
t = 7'b0111110;
#10;
t = 7'b0111111;
#10;
t = 7'b1000000;
#10;
t = 7'b1000001;
#10;
t = 7'b1000010;
#10;
t = 7'b1000011;
#10;
t = 7'b1000100;
#10;
t = 7'b1000101;
#10;
t = 7'b1000110;
#10;
t = 7'b1000111;
#10;
t = 7'b1001000;
#10;
t = 7'b1001001;
#10;
t = 7'b1001010;
#10;
t = 7'b1001011;
#10;
t = 7'b1001100;
#10;
t = 7'b1001101;
#10;
t = 7'b1001110;
#10;
t = 7'b1001111;
#10;
t = 7'b1010000;
#10;
t = 7'b1010001;
#10;
t = 7'b1010010;
#10;
t = 7'b1010011;
#10;
t = 7'b1010100;
#10;
t = 7'b1010101;
#10;
t = 7'b1010110;
#10;
t = 7'b1010111;
#10;
t = 7'b1011000;
#10;
t = 7'b1011001;
#10;
t = 7'b1011010;
#10;
t = 7'b1011011;
#10;
t = 7'b1011100;
#10;
t = 7'b1011101;
#10;
t = 7'b1011110;
#10;
t = 7'b1011111;
#10;
t = 7'b1100000;
#10;
t = 7'b1100001;
#10;
t = 7'b1100010;
#10;
t = 7'b1100011;
#10;
t = 7'b1100100;
#10;
t = 7'b1100101;
#10;
t = 7'b1100110;
#10;
t = 7'b1100111;
#10;
t = 7'b1101000;
#10;
t = 7'b1101001;
#10;
t = 7'b1101010;
#10;
t = 7'b1101011;
#10;
t = 7'b1101100;
#10;
t = 7'b1101101;
#10;
t = 7'b1101110;
#10;
t = 7'b1101111;
#10;
t = 7'b1110000;
#10;
t = 7'b1110001;
#10;
t = 7'b1110010;
#10;
t = 7'b1110011;
#10;
t = 7'b1110100;
#10;
t = 7'b1110101;
#10;
t = 7'b1110110;
#10;
t = 7'b1110111;
#10;
t = 7'b1111000;
#10;
t = 7'b1111001;
#10;
t = 7'b1111010;
#10;
t = 7'b1111011;
#10;
t = 7'b1111100;
#10;
t = 7'b1111101;
#10;
t = 7'b1111110;
#10;
t = 7'b1111111;
end
endmodule
| 7.590233 |
module temperatureAnalyzer (
temperature,
highTempAbnormality,
lowTempAbnormality
);
input [7:0] temperature;
output lowTempAbnormality;
output highTempAbnormality;
assign lowTempAbnormality = (temperature < 35);
assign highTempAbnormality = (temperature > 39);
endmodule
| 6.911668 |
module tb_temperatureCalculator ();
reg [4:0] factoryBaseTemp;
reg [3:0] factoryTempCoef;
reg [3:0] tempSensorValue;
wire [7:0] temperature;
temperatureCalculator tc (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
temperature
);
initial begin
factoryTempCoef <= 4'b0010;
factoryBaseTemp <= 5'b00111;
tempSensorValue <= 4'b00000;
#5;
tempSensorValue <= 4'b00001;
#5;
tempSensorValue <= 4'b00010;
#5;
tempSensorValue <= 4'b00011;
#5;
tempSensorValue <= 4'b00100;
#5;
tempSensorValue <= 4'b00101;
#5;
tempSensorValue <= 4'b00110;
#5;
tempSensorValue <= 4'b00111;
#5;
tempSensorValue <= 4'b01000;
#5;
tempSensorValue <= 4'b01001;
#5;
tempSensorValue <= 4'b01010;
#5;
tempSensorValue <= 4'b01011;
#5;
tempSensorValue <= 4'b01100;
#5;
tempSensorValue <= 4'b01101;
#5;
tempSensorValue <= 4'b01110;
#5;
tempSensorValue <= 4'b01111;
#10;
$finish;
end
endmodule
| 7.590233 |
module temperatureCalculator (
factoryBaseTemp,
factoryTempCoef,
tempSensorValue,
temperature
);
input [4:0] factoryBaseTemp;
input [3:0] factoryTempCoef;
input [3:0] tempSensorValue;
output [7:0] temperature;
wire [7:0] mpo;
wire cout;
Multiplier4x4 m (
mpo,
factoryTempCoef,
tempSensorValue
);
Adder8bit a (
temperature
,,
{3'b000, factoryBaseTemp},
{3'b000, mpo[7:3]},
0
);
endmodule
| 7.291612 |
module TemperatureMonitor_exdes (
DADDR_IN, // Address bus for the dynamic reconfiguration port
DCLK_IN, // Clock input for the dynamic reconfiguration port
DEN_IN, // Enable Signal for the dynamic reconfiguration port
DI_IN, // Input data bus for the dynamic reconfiguration port
DWE_IN, // Write Enable for the dynamic reconfiguration port
DO_OUT, // Output data bus for dynamic reconfiguration port
DRDY_OUT, // Data ready signal for the dynamic reconfiguration port
VP_IN, // Dedicated Analog Input Pair
VN_IN
);
input VP_IN;
input VN_IN;
input [6:0] DADDR_IN;
input DCLK_IN;
input DEN_IN;
input [15:0] DI_IN;
input DWE_IN;
output [15:0] DO_OUT;
output DRDY_OUT;
wire GND_BIT;
wire [2:0] GND_BUS3;
wire FLOAT_VCCAUX;
wire FLOAT_VCCINT;
wire FLOAT_USER_TEMP_ALARM;
assign GND_BIT = 0;
TemperatureMonitor sysmon_wiz_inst (
.DADDR_IN(DADDR_IN[6:0]),
.DCLK_IN(DCLK_IN),
.DEN_IN(DEN_IN),
.DI_IN(DI_IN[15:0]),
.DWE_IN(DWE_IN),
.DO_OUT(DO_OUT[15:0]),
.DRDY_OUT(DRDY_OUT),
.VP_IN(VP_IN),
.VN_IN(VN_IN)
);
endmodule
| 8.35573 |
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