code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module vsdmemsoc_tb;
// Inputs
reg CLK, reset;
reg init_en;
reg [7:0] init_addr;
reg [31:0] init_data;
// Outputs
wire [9:0] OUT;
// Other Signals
integer i;
wire [31:0] ROM =
i == 32'h0 ? {12'b1, 5'd0, 3'b000, 5'd9, 7'b0010011} :
i == 32'h1 ? {12'b101011, 5'd0, 3'b000, 5'd10, 7'b0010011} :
i == 32'h2 ? {12'b0, 5'd0, 3'b000, 5'd11, 7'b0010011} :
i == 32'h3 ? {12'b0, 5'd0, 3'b000, 5'd17, 7'b0010011} :
i == 32'h4 ? {7'b0000000, 5'd11, 5'd17, 3'b000, 5'd17, 7'b0110011} :
i == 32'h5 ? {12'b1, 5'd11, 3'b000, 5'd11, 7'b0010011} :
i == 32'h6 ? {1'b1, 6'b111111, 5'd10, 5'd11, 3'b001, 4'b1100, 1'b1, 7'b1100011} :
i == 32'h7 ? {7'b0000000, 5'd11, 5'd17, 3'b000, 5'd17, 7'b0110011} :
i == 32'h8 ? {7'b0100000, 5'd11, 5'd17, 3'b000, 5'd17, 7'b0110011} :
i == 32'h9 ? {7'b0100000, 5'd9, 5'd11, 3'b000, 5'd11, 7'b0110011} :
i == 32'hA ? {1'b1, 6'b111111, 5'd9, 5'd11, 3'b001, 4'b1100, 1'b1, 7'b1100011} :
i == 32'hB ? {7'b0100000, 5'd11, 5'd17, 3'b000, 5'd17, 7'b0110011} :
i == 32'hC ? {1'b1, 6'b111111, 5'd0, 5'd0, 3'b000, 4'b0000, 1'b1, 7'b1100011} :
32'd0 ;
// Instantiate the Unit Under Test (UUT)
vsdmemsoc uut (
.OUT(OUT),
.CLK(CLK),
.reset(reset),
.init_en(init_en),
.init_addr(init_addr),
.init_data(init_data)
);
always @(posedge CLK) begin
if (i < 32'd16) begin
i <= i + 32'd1;
reset <= 1'b1;
init_en <= 1'b1;
init_addr <= i;
init_data <= ROM;
end else if (i < 32'd20) begin
i <= i + 32'd1;
init_en <= 1'b0;
end else begin
reset <= 1'b0;
end
end
initial begin
`ifdef PRE_SYNTH_SIM
$dumpfile("pre_synth_sim.vcd");
`elsif POST_SYNTH_SIM
$dumpfile("post_synth_sim.vcd");
`endif
$dumpvars(0, vsdmemsoc_tb);
i = 0;
CLK = 0;
reset = 0;
#5000 $finish;
end
always #5 CLK = ~CLK;
endmodule
| 7.032941 |
module testbench05;
reg [3:0] A, B;
reg Select;
wire [3:0] Sum;
wire Carry, Overflow;
_4bit_Adder_Sub_gate mod (
Sum,
Carry,
Overflow,
A,
B,
Select
);
initial begin
$monitor($time, " A=%4b, B=%4b, Select=%b, Carry=%b, Sum=%4b, Overflow=%b.", A, B, Select,
Carry, Sum, Overflow);
#0 A = 4'b0000;
B = 4'b0000;
Select = 1'b0;
#10 A = 4'b1000;
B = 4'b0101;
Select = 1'b1;
#10 A = 4'b1111;
B = 4'b1000;
Select = 1'b1;
#10 $finish;
end
endmodule
| 6.538107 |
module testbench06;
reg [3:0] A, B;
reg Select;
wire [3:0] Sum;
wire Carry;
_4bit_Adder_Sub_df mod (
Sum,
Carry,
A,
B,
Select
);
initial begin
$monitor($time, " A=%4b, B=%4b, Select=%b, Carry=%b, Sum=%4b.", A, B, Select, Carry, Sum);
#0 A = 4'b0000;
B = 4'b0000;
Select = 1'b0;
#10 A = 4'b1000;
B = 4'b0101;
Select = 1'b1;
#10 A = 4'b1111;
B = 4'b1000;
Select = 1'b1;
#10 $finish;
end
endmodule
| 6.677562 |
module testbench11;
`include "params.v"
parameter DIM = WIDTH * HEIGHT;
parameter t = 10;
reg clk, reset;
reg [ 23:0] RGB;
wire [ 7:0] L;
reg [ 23:0] rom [0:DIM-1];
// Output ram
reg [ 7:0] out_ram[0:DIM-1];
wire [ 7:0] din;
reg [$clog2(DIM)-1:0] addr;
reg w1, w2;
reg [7:0] out;
initial begin
$readmemb("RGB.txt", rom);
end
always @clk #(t / 2) clk <= ~clk;
Convert dut (
.clk(clk),
.rst(reset),
.RGB(RGB),
.L (L)
);
//Addr RAM
always @(posedge clk or posedge reset) begin
if (reset) w2 <= 1'b0;
else w2 <= w1;
end
always @(posedge clk or posedge reset) begin
if (reset) addr <= 0;
else if (w2) addr <= (addr == (DIM - 1)) ? 0 : (addr + 1);
end
//Value RAM
assign din = L;
always @(posedge clk) begin
if (w2) out_ram[addr] <= din;
end
integer i;
initial begin
reset <= 1'b1;
clk <= 1'b1;
w1 <= 1'b0;
#(t * 5);
reset <= 1'b0;
#2;
for (i = 0; i < WIDTH * HEIGHT; i = i + 1) begin
RGB <= rom[i];
if (i == 4) w1 <= 1'b1;
#t;
end
#(t * 5);
w1 <= 1'b0;
#(t * 5);
$writememb("Gray.txt", out_ram);
$finish;
end
endmodule
| 7.353884 |
module counter_tb ();
// Make a register for the clock you're going to generate.
reg clk;
// Make a wire for the output of the module you're testbenching for.
wire [31:0] count;
// Instantiate the module we're testbenching.
counter tb (
.clk (clk),
.count(count)
);
// Initialize the clock to 0.
initial clk = 0;
// At every half cycle, the clock signal oscillates. We want it to do that
// every half cycle because a whole cycle is the time it takes for two
// oscillations.
always #5 clk = ~clk;
endmodule
| 7.107233 |
module encoderTestBench;
reg [3:0] D;
wire A, B, V;
encoderGates4x1 e1 (
D,
A,
B,
V
);
integer i;
initial begin
for (i = 0; i < 16; i = i + 1) begin
D = i;
#50;
end
end
endmodule
| 6.713618 |
module clk_div_tb ();
// Make a register for the clock you're going to generate and the reset.
reg clk, rst;
// Generally, you make registers for inputs because you usually want to
// make procedural changes to them to see how the output is affected. In
// this case, we could get away with using wires if we also made appropriate
// changes to the assignments so they were continuous assignments instead
// of procedural assignments.
reg [31:0] scale = 1000;
// Make a wire for your output.
wire out;
// Instantiate the module we're testbenching.
clk_div test (
.clk(clk),
.reset(rst),
.scale(scale),
.clk_out(out)
);
// Initialize the clock and reset to 0.
initial begin
clk = 0;
rst = 0;
end
// Clock is 100 MHz
always #5 clk = !clk;
endmodule
| 6.724979 |
module. To see the results, run the simulation for a
// little while longer until the freq_counter's counter has reached the
// localparam max.
module freq_count_tb();
wire [19:0] freq;
reg clk, in, enable;
wire done;
initial begin
clk = 0;
in = 0;
enable = 1;
// Test frequency is 250 kHz
forever #2000 in = !in;
end
// Clock is 100 MHz
always #5 clk = !clk;
freq_counterdiv16 tb1(
.CLK(clk),
.enable(enable),
.IN(in),
.freq(freq),
.done(done)
);
endmodule
| 8.236286 |
module testbench_AS;
reg [3:0] A, B;
reg Select;
wire [3:0] Sum;
wire Carry, Overflow;
ADDSUB mod (
Sum,
Carry,
Overflow,
A,
B,
Select
);
initial begin
$monitor($time, " A=%4b, B=%4b, Select=%b, Carry=%b, Sum=%4b, Overflow=%b.", A, B, Select,
Carry, Sum, Overflow);
#0 A = 4'b0000;
B = 4'b0000;
Select = 1'b0;
#10 A = 4'b1000;
B = 4'b0101;
Select = 1'b1;
#10 A = 4'b1111;
B = 4'b1000;
Select = 1'b1;
#10 $finish;
end
endmodule
| 6.516317 |
module tbCompressor ();
reg x1, x2, x3, x4, Cin;
wire Sum, Carry, Cout;
compressor4to2 inst (
x1,
x2,
x3,
x4,
Cin,
Sum,
Carry,
Cout
);
initial begin
{x2, x3, x4, Cin} = 4'b0000;
x1 = 1'b1;
#1 x2 = ~x2;
#1 x3 = ~x3;
#1 x4 = ~x4;
#1 Cin = ~Cin;
#1 x1 = ~x1;
//step 1
#1 x2 = ~x2;
#1 x3 = ~x3;
#1 x4 = ~x4;
#1 Cin = ~Cin;
#1 x1 = ~x1;
//step 2
#1 x2 = ~x2;
#1 x3 = ~x3;
#1 x4 = ~x4;
#1 Cin = ~Cin;
#1 x1 = ~x1;
//step 3
#1 x2 = ~x2;
#1 x3 = ~x3;
#1 x4 = ~x4;
#1 Cin = ~Cin;
#1 x1 = ~x1;
//step 4
#1 x2 = ~x2;
#1 x3 = ~x3;
#1 x4 = ~x4;
#1 Cin = ~Cin;
#1 x1 = ~x1;
//step 5
#1 x2 = ~x2;
#1 x3 = ~x3;
#1 x4 = ~x4;
#1 Cin = ~Cin;
#1 x1 = ~x1;
end
endmodule
| 6.65134 |
module Testbench;
reg in;
reg [1:0] sel;
wire [3:0] f;
integer i;
defparam demux2x4.sel_width = 2;
Demux demux2x4 (
in,
sel,
f
);
initial begin
$dumpfile("demux.vcd");
$dumpvars(0, Testbench);
in = 1;
for (i = 0; i < 4; i = i + 1) begin
sel = i;
#1;
end
$finish;
end
endmodule
| 7.128264 |
module eightToOneMUXTest;
wire out_t;
reg [0:7] in_t;
reg sl1_t, sl2_t, sl3_t;
eightToOneMUX loki (
out_t,
in_t,
sl1_t,
sl2_t,
sl3_t
);
initial begin
sl1_t <= 0;
sl2_t <= 0;
sl3_t <= 0;
in_t <= 8'b11010101;
#1 $display("input = %b ", in_t, "Output = %b ", out_t);
end
endmodule
| 7.166107 |
module m21Test;
reg D0_t, D1_t, s_t;
wire y_t;
m21 thor (
D0_t,
D1_t,
s_t,
y_t
);
initial begin
D0_t <= 0;
D1_t <= 1;
s_t <= 0;
#1 $display("Input = %b ", D0_t, D1_t, "Output = %b ", y_t);
end
endmodule
| 6.669187 |
module mainComparatorTest;
reg [0:7] in1_t, in2_t;
wire CO_t;
mainComparator Odin (
in1_t,
in2_t,
CO_t
);
initial begin
in1_t <= 8'b00110010;
in2_t <= 8'b11100110;
#1 $display("Input1 = %b ", in1_t, "Input2 = %b ", in2_t, "CO = %b ", CO_t);
end
endmodule
| 6.859464 |
module TestBenchForEightToThirteen (
clk_AD,
sysclk,
clk16,
datain,
dataout,
pcmlinear,
rpcmlinear,
logPCM,
rLogPCM,
fskdata
);
output reg [7:0] datain;
output [7:0] dataout;
output wire [7:0] logPCM, rLogPCM;
wire [8:0] checked, rfskdata;
output reg sysclk, clk16;
output reg clk_AD;
output wire fskdata;
output wire [12:0] pcmlinear, rpcmlinear;
reg reset;
EightToThirteen module6 (
.clk_AD (clk_AD),
.reset (reset),
.datain (datain),
.dataout(pcmlinear)
);
LinToLogPCM module0 (
.pcmlinear(pcmlinear),
.pcmlog(logPCM)
);
CheckCode module1 (
.datain (logPCM),
.dataout(checked)
);
FSK module2 (
.clk(sysclk),
.reset(reset),
.datain(checked),
.dataout(fskdata)
);
rFSK module3 (
.clk(clk16),
.reset(reset),
.datain(fskdata),
.dataout(rfskdata)
);
rCheckCode module4 (
.datain (rfskdata),
.dataout(rLogPCM)
);
rLinToLogPCM module5 (
.pcmlog(rLogPCM),
.pcmlinear(rpcmlinear)
);
rEightToThirteen module7 (
.datain (rpcmlinear),
.dataout(dataout)
);
initial begin
reset = 1;
sysclk = 0;
#5 clk16 = 1;
forever #80 clk16 = ~clk16;
end
initial begin
datain = 13'b0000000000000;
#5 datain = 13'b0000000000000;
forever #1440 datain = datain + 1;
end
initial begin
#5 clk_AD = 1;
forever #720 clk_AD = ~clk_AD;
end
initial
fork
forever #5 sysclk = ~sysclk;
#1 reset = 0;
#2 reset = 1;
join
always @(datain) begin
if (datain == 13'b1111111111111) datain <= 13'b0000000000000;
end
endmodule
| 6.557231 |
module testbenchReg;
reg clk = 0;
reg rst = 0;
reg l = 0;
reg [15:0] in = 16'b1111111111111111;
wire [15:0] out;
register reg_0 (
clk,
rst,
l,
in,
out
);
initial begin
$dumpvars;
#1 clk <= 1;
#5 clk <= 0;
l <= 1;
#2 clk <= 1;
#2 clk <= 0;
l <= 0;
#1 in <= 16'b1011000111100111;
#2 l <= 1;
#2 clk <= 1;
#5 rst <= 1;
#1 rst <= 0;
$finish;
end
endmodule
| 7.075364 |
module testbench;
wire CLOCK, RESET, PUSHDATOENTRADA, POPffg/*Viene del probador*/, SET_INIT/*Viene del probador*/, POPDATOCF;
wire [1:0] IDINPUT, SEL, WEIGHT;
wire [ 3:0] DATO_IN;
wire [31:0] TABLE;
wire [6:0] TL_IN, TH_IN;
wire IDLE;
wire [3:0] PAUSE_STB, CONTINUE_STB, ERROR_FULL;
wire [3:0] DATO_OUTffg;
TransactionProb GeneradorSenales (
CLOCK,
RESET,
PUSHDATOENTRADA,
IDINPUT,
DATO_IN,
TL_IN,
TH_IN,
SEL,
TABLE,
WEIGHT,
POPDATOCF,
POPffg,
SET_INIT,
IDLE,
PAUSE_STB,
CONTINUE_STB,
ERROR_FULL
);
TRANSACTIONLAYER conductual (
CLOCK,
RESET,
PUSHDATOENTRADA,
IDINPUT,
DATO_IN,
TL_IN,
TH_IN,
SEL,
TABLE,
WEIGHT,
POPDATOCF,
POPffg,
SET_INIT,
IDLE,
PAUSE_STB,
CONTINUE_STB,
ERROR_FULL,
DATO_OUTffg
);
endmodule
| 7.015571 |
modules, 16 bit crc *
* ------------------------------------------------ */
`include "Sources/crc.v"
`include "Common/parallel_to_serial.v"
module tb(); // CRC-16/CCITT-FALSE
localparam CRC_SIZE = 16, //Size of CRC value, all following parameters should have this size
INITAL_VAL = 16'hFFFF, //Initial value for CRC reg
CRC_POLY = 16'h1021, //Polynomial for crc calculation
FINAL_XOR = 16'h0;
reg clk, rst, start;
reg [127:0] data;
wire enable, serial;
wire [CRC_SIZE-1:0] crc_s, crc_d;
integer f, i;
reg dummy;
parallel_to_serial #(128,1) data_conv(clk,rst,start,data,serial,enable);
crc_static #(CRC_SIZE,INITAL_VAL,CRC_POLY,FINAL_XOR) uut_s(clk,rst,serial,enable,crc_s);
crc_dynamic #(CRC_SIZE) uut_d(clk,rst,serial,enable,crc_d,INITAL_VAL,CRC_POLY, FINAL_XOR);
//Generate clock
always begin
clk = 0;
forever #5 clk = ~clk;
end
//Send reset
initial begin
rst <= 0;
#3
rst <= 1;
#10
rst <= 0;
end
initial begin
$dumpfile("sim.vcd");
$dumpvars(0, clk);
$dumpvars(1, rst);
$dumpvars(2, start);
$dumpvars(3, serial);
$dumpvars(4, enable);
$dumpvars(5, crc_s);
$dumpvars(6, crc_d);
$dumpvars(7, data);
end
initial begin
f = $fopen("output.tmp.txt","w");
start = 0;
data = {128{1'b1}};
#10
start = 1;
$fwrite(f,"%h\n",data);
#10
start = 0;
while (enable == 1) begin
#10 dummy = 1;
end
#30
data = 128'h0;
rst = 1;
#10
rst = 0;
start = 1;
$fwrite(f,"%h\n",data);
#10
start = 0;
while (enable == 1) begin
#10 dummy = 1;
end
for(i = 0; i < 5; i=i+1)
begin
#30
data = {$random,$random,$random,$random};
rst = 1;
#10
rst = 0;
start = 1;
$fwrite(f,"%h\n",data);
#10
start = 0;
while (enable == 1) begin
#10 dummy = 1;
end
end
#30
$fclose(f);
$finish;
end
endmodule
| 8.564951 |
module testbench;
reg [15:0] in_a, in_b;
reg CLK;
reg reset;
reg [15:0] correct_ans;
wire [15:0] s;
reg [5:0] counter;
reg [5:0] ct;
reg error;
reg cin;
reg [4:0] successful_count;
wire cout;
initial cin = 0;
initial ct = 0;
initial in_a = 0;
initial in_b = 0;
initial successful_count = 0;
cla_16bit DDLab6 (
in_a,
in_b,
cin,
s
);
/////// initial ///////
initial begin
$dumpfile("lab6_16bit.fsdb");
$dumpvars;
CLK = 1'b0;
#10 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 $finish;
end
always #10 CLK = ~CLK;
always @(posedge CLK or posedge reset) begin
if (reset) begin
counter <= 0;
in_a <= {$random};
in_b <= {$random} % 32767;
cin <= {$random} % 2;
correct_ans <= 0;
error <= 0;
ct <= ct + 1'b1;
end else begin
correct_ans <= in_a + in_b + cin;
counter <= counter + 1;
if (counter == 4)
//if({cout,s} == correct_ans)
if (s == correct_ans) begin
successful_count = successful_count + 1;
$display("Test %d ", ct);
$display("//////////////////");
$display("// Successful %d//", successful_count);
$display("//////////////////");
$display("%d + %d + %d= ?", in_a, in_b, cin);
$display("sum = %d\n", s);
$display();
end else begin
$display();
$display("Test %d ", ct);
$display("//////////");
$display("// Fail //");
$display("//////////");
$display("%d + %d + %d= ?", in_a, in_b, cin);
$display("your s=%d", s);
$display("correct:");
$display("sum =%d", correct_ans[15:0]);
$display();
end
end
end
endmodule
| 7.015571 |
module testbench_card_write; //testbench y probador de DAT
reg [3:0] card_in = 0;
reg [31:0] buffer_in = 0;
wire [31:0] buffer_out;
wire [3:0] card_out;
reg clock;
reg new_trans;
reg enable_write, enable_read, Clear_in, reset;
parameter n = 32;
parameter vector_width = 10; //reg_vector has inputs with information coming from registers
reg [vector_width - 1 : 0] reg_vector = 10'b1101111111;
reg fifo_ack_i = 0;
reg card_ack_i = 0;
reg fifo_full = 0;
reg fifo_empty = 0;
reg mode = 1;
reg [10:0] block_amount = 8;
reg direction = 0;
DAT data_module (
buffer_in,
buffer_out,
card_in,
card_out,
clock,
fifo_ack_i,
fifo_ack_o,
fifo_enable_o,
card_ack_i,
card_ack_o,
fifo_full,
fifo_empty,
block_amount,
fifo_ready,
new_trans,
reset,
mode,
direction
);
initial begin
Clear_in = 1;
enable_write = 1;
enable_read = 1;
reset = 0;
clock = 0;
#2 new_trans = 1;
#40 buffer_in = 32'hCAFECAFE;
#50 buffer_in = 32'h0A0BF10A;
#40 buffer_in = 32'hFCB01AF0;
#40 buffer_in = 32'hABBA01FF;
#60 buffer_in = 32'hAFA016F0;
#30 buffer_in = 32'h01AF001A;
mode = 0;
#40 buffer_in = 32'hABBACAFE;
#50 buffer_in = 32'hFF001ABA;
#30 buffer_in = 32'hCAFECAFE;
#50 buffer_in = 32'h110FCBAF;
#60 buffer_in = 32'hFF001FF0;
#50 buffer_in = 32'h11FFABBA;
#200 $finish;
end
initial begin
$dumpfile("testbench_card_write.vcd");
$dumpvars(0, testbench_card_write);
end
always #2 clock = !clock;
endmodule
| 7.061901 |
modules, 32 bit crc *
* ------------------------------------------------ */
`include "Sources/crc.v"
`include "Common/parallel_to_serial.v"
module tb(); // CRC-32/POSIX
localparam CRC_SIZE = 32, //Size of CRC value, all following parameters should have this size
INITAL_VAL = 32'h00000000, //Initial value for CRC reg
CRC_POLY = 32'h04C11DB7 , //Polynomial for crc calculation
FINAL_XOR = 32'hFFFFFFFF;
reg clk, rst, start;
reg [127:0] data;
wire enable, serial;
wire [CRC_SIZE-1:0] crc_s, crc_d;
integer f, i;
reg dummy;
parallel_to_serial #(128,1) data_conv(clk,rst,start,data,serial,enable);
crc_static #(CRC_SIZE,INITAL_VAL,CRC_POLY,FINAL_XOR) uut_s(clk,rst,serial,enable,crc_s);
crc_dynamic #(CRC_SIZE) uut_d(clk,rst,serial,enable,crc_d,INITAL_VAL,CRC_POLY, FINAL_XOR);
//Generate clock
always begin
clk = 0;
forever #5 clk = ~clk;
end
//Send reset
initial begin
rst <= 0;
#3
rst <= 1;
#10
rst <= 0;
end
initial begin
$dumpfile("sim.vcd");
$dumpvars(0, clk);
$dumpvars(1, rst);
$dumpvars(2, start);
$dumpvars(3, serial);
$dumpvars(4, enable);
$dumpvars(5, crc_s);
$dumpvars(6, crc_d);
$dumpvars(7, data);
end
initial begin
f = $fopen("output.tmp.txt","w");
start = 0;
data = {128{1'b1}};
#10
start = 1;
$fwrite(f,"%h\n",data);
#10
start = 0;
while (enable == 1) begin
#10 dummy = 1;
end
#30
data = 128'h0;
rst = 1;
#10
rst = 0;
start = 1;
$fwrite(f,"%h\n",data);
#10
start = 0;
while (enable == 1) begin
#10 dummy = 1;
end
for(i = 0; i < 5; i=i+1)
begin
#30
data = {$random,$random,$random,$random};
rst = 1;
#10
rst = 0;
start = 1;
$fwrite(f,"%h\n",data);
#10
start = 0;
while (enable == 1) begin
#10 dummy = 1;
end
end
#30
$fclose(f);
$finish;
end
endmodule
| 9.179462 |
module tb ();
reg [3:0]
zero,
one,
two,
three,
four,
five,
six,
seven,
eight,
nine,
ten,
eleven,
twelve,
thirtn,
fourtn,
fiftn,
dummy;
wire [8:0] v1_1, v1_2, v1_3, v1_4, fbc_1, fbc_2, fbc_3, fbc_4, v1_5, fbc_5, fbc_6, fbc_7, fbc_8, v1_6, v1_7, v1_8;
reg [15:0] binary_result;
multiCS4_v1 uut0_0 (
three,
four,
v1_1
);
multiCS4_v1 uut0_1 (
ten,
seven,
v1_2
);
multiCS4_v1 uut0_2 (
nine,
fourtn,
v1_3
);
multiCS4_v1 uut0_3 (
six,
six,
v1_4
);
multiCS4_v1 uut0_4 (
fiftn,
fiftn,
v1_5
);
multiCS4_v1 uut0_5 (
zero,
twelve,
v1_6
);
multiCS4_v1 uut0_6 (
five,
thirtn,
v1_7
);
multiCS4_v1 uut0_7 (
eleven,
eleven,
v1_8
);
multiCS4_fullbasecell uut1_0 (
three,
four,
fbc_1[7:0]
);
multiCS4_fullbasecell uut1_1 (
ten,
seven,
fbc_2[7:0]
);
multiCS4_fullbasecell uut1_2 (
nine,
fourtn,
fbc_3[7:0]
);
multiCS4_fullbasecell uut1_3 (
six,
six,
fbc_4[7:0]
);
multiCS4_fullbasecell uut1_4 (
fiftn,
fiftn,
fbc_5[7:0]
);
multiCS4_fullbasecell uut1_5 (
zero,
twelve,
fbc_6[7:0]
);
multiCS4_fullbasecell uut1_6 (
five,
thirtn,
fbc_7[7:0]
);
multiCS4_fullbasecell uut1_7 (
eleven,
eleven,
fbc_8[7:0]
);
assign fbc_1[8] = 1'b0;
assign fbc_2[8] = 1'b0;
assign fbc_3[8] = 1'b0;
assign fbc_4[8] = 1'b0;
assign fbc_5[8] = 1'b0;
assign fbc_6[8] = 1'b0;
assign fbc_7[8] = 1'b0;
assign fbc_8[8] = 1'b0;
initial //test cases here
begin
zero <= 4'd0;
one <= 4'd1;
two <= 4'd2;
three <= 4'd3;
four <= 4'd4;
five <= 4'd5;
six <= 4'd6;
seven <= 4'd7;
eight <= 4'd8;
nine <= 4'd9;
ten <= 4'd10;
eleven <= 4'd11;
twelve <= 4'd12;
thirtn <= 4'd13;
fourtn <= 4'd14;
fiftn <= 4'd15;
#100 binary_result[0] <= (v1_1 == 9'd12);
binary_result[1] <= (v1_2 == 9'd70);
binary_result[2] <= (v1_3 == 9'd126);
binary_result[3] <= (v1_4 == 9'd36);
binary_result[4] <= (v1_5 == 9'd225);
binary_result[5] <= (v1_6 == 9'd0);
binary_result[6] <= (v1_7 == 9'd65);
binary_result[7] <= (v1_8 == 9'd121);
binary_result[8] <= (fbc_1 == 9'd12);
binary_result[9] <= (fbc_2 == 9'd70);
binary_result[10] <= (fbc_3 == 9'd126);
binary_result[11] <= (fbc_4 == 9'd36);
binary_result[12] <= (fbc_5 == 9'd225);
binary_result[13] <= (fbc_6 == 9'd0);
binary_result[14] <= (fbc_7 == 9'd65);
binary_result[15] <= (fbc_8 == 9'd121);
#100 dummy = 0;
end
endmodule
| 7.002324 |
module testbench;
reg [63:0] in_a, in_b;
reg CLK;
reg reset;
reg [64:0] correct_ans;
wire [63:0] sum;
reg [5:0] counter;
reg [5:0] ct;
reg error;
reg cin;
wire cout;
initial cin = 0;
initial ct = 0;
initial in_a = 0;
initial in_b = 0;
cla_64bit DDLab6 (
in_a,
in_b,
cin,
sum
);
/////// initial ///////
initial begin
$dumpfile("lab6_64bit.fsdb");
$dumpvars;
CLK = 1'b0;
#10 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 reset = 1;
#20 reset = 0;
#500 $finish;
end
always #10 CLK = ~CLK;
always @(posedge CLK or posedge reset) begin
if (reset) begin
counter <= 0;
in_a <= {$random} * {$random} * {$random} * {$random};
in_b <= {$random} * {$random} * {$random} * {$random};
//in_b <= 64'd9223372036854775808+{$random};
cin <= {$random} % 2;
correct_ans <= 0;
error <= 0;
ct <= ct + 1'b1;
end else begin
correct_ans <= in_a + in_b + cin;
counter <= counter + 1;
if (counter == 4)
if (sum == correct_ans[63:0]) begin
$display(" Test %d ", ct);
$display(" ////////////////");
$display(" // Successful //");
$display(" ////////////////");
$display(" %d + %d + %d = ?", in_a, in_b, cin);
$display(" sum = %d\n", sum);
$display();
end else begin
$display();
$display("Test %d ", ct);
$display("//////////");
$display("// Fail //");
$display("//////////");
$display("%d + %d + %d = ?", in_a, in_b, cin);
$display("your sum = %d", sum);
$display("correct:");
$display(" sum=%d", correct_ans[63:0]);
$display();
end
end
end
endmodule
| 7.015571 |
module tb_comparator8 ();
reg [7:0] A;
reg [7:0] B;
reg l;
reg e;
reg g;
wire lt;
wire eq;
wire gt;
comparator8 test_comparator8 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(eq),
.gt(gt)
);
initial begin
A = 8'b00000001;
B = 8'b00000001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
A = 8'b00000010;
B = 8'b00000001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
//////////////////
A = 8'b00000001;
B = 8'b00000010;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
$finish;
end
endmodule
| 6.843472 |
module usr_testbench;
reg [7:0] inp;
reg clk;
reg clr;
reg [1:0] op;
reg sinr;
reg sinl;
wire [7:0] pout;
wire soutl;
wire soutr;
eightbit_usr usr (
clk,
sinr,
sinl,
clr,
op,
inp,
pout,
soutr,
soutl
);
always #50 clk = ~clk;
initial begin
clk = 1'b1;
clr = 1'b0;
sinr = 1'b0;
sinl = 1'b0;
op = 2'b11;
#100;
inp = 8'b11110101;
#100;
op = 2'b01;
#500;
op = 2'b10;
#200;
op = 2'b00;
#50;
clr = 1'b1;
#100;
clr = 1'b0;
op = 2'b11;
inp = 8'b01100110;
#100;
op = 2'b01;
#200;
op = 2'b10;
#200;
op = 2'b00;
end
initial
$monitor(
$time, " clk = %b; clr = %b; next op = %d; pin = %b; pout = %b ", clk, clr, op, inp, pout
);
initial #1500 $finish;
endmodule
| 6.67584 |
module testbench_add32 ();
reg [31:0] A;
reg [31:0] B;
wire Overflow; //溢出判定
wire [31:0] result; //输出结果
reg isSub; //运算判定
reg isSign;
Add32 testadd32 (
Overflow,
result,
A,
B,
isSub,
isSign
);
initial begin
isSub = 1'b0;
isSign = 1'b0;
A = 100;
B = 100;
end
initial begin
repeat (100) #10 A = {$random} % 4294967295;
end
initial begin
repeat (100) #10 B = {$random} % 4294967295;
end
integer out_file;
initial begin
out_file = $fopen("unsigned_result.txt", "w");
end
always @(A or B) begin
//$display("1:A 2:B 3:A+B 4:result 5:overflow");
//$monitor("%d%d%d%d%d",A,B,A+B,result,Overflow);
$fwrite(out_file, "A:%d B:%d fact:%d cal:%d overflow:%d err:%d\n", A, B, A + B, result,
Overflow, result - A - B);
end
endmodule
| 7.504399 |
module testbench_adder_32bit;
reg [31:0] num1, num2;
wire [31:0] sum;
wire cfinal;
wire cin;
assign cin = 0;
adder_32bit add1 (
cfinal,
sum,
num1,
num2,
cin
);
initial
$monitor(
, $time, "sum=%b, cfinal = %b, num1=%b, num2=%b, cin = %b", sum, cfinal, num1, num2, cin
);
initial begin
#0 num1 = 32'b00000001000000010000000100000001;
num2 = 32'b11111111111111111111111111111111;
#10 num1 = 32'b00000000000000000000000000000000;
num2 = 32'b11111110111111101111111011111110;
#20 num1 = 32'b00000000000000000000000000000000;
num2 = 32'b11111101111111011111110111111101;
#30 num1 = 32'b00000000000000000000000000000000;
num2 = 32'b11111011111110111111101111111011;
#40 num1 = 32'b00000000000000000000000000000000;
num2 = 32'b11110111111101111111011111110111;
end
endmodule
| 7.504399 |
module testbench_adder_8bit;
reg [7:0] num1, num2;
wire [7:0] sum;
wire cfinal;
wire cin;
assign cin = 0;
ADDER_8bit fl (
cfinal,
sum,
num1,
num2,
cin
);
initial
$monitor(
, $time, "sum=%b, cfinal = %b, num1=%b, num2=%b, cin = %b", sum, cfinal, num1, num2, cin
);
initial begin
#0 num1 = 8'b00000001;
num2 = 8'b11111111;
#10 num1 = 8'b00000000;
num2 = 8'b11111110;
#20 num1 = 8'b00000000;
num2 = 8'b11111101;
#30 num1 = 8'b00000000;
num2 = 8'b11111011;
#40 num1 = 8'b00000000;
num2 = 8'b11110111;
end
endmodule
| 7.504399 |
module: ADSR_mngt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_ADSR;
// Inputs
reg clk;
reg rst;
reg new_sample;
reg new_note_pulse;
reg release_note_pulse;
reg [6:0] attack_rate;
reg [6:0] decay_rate;
reg [6:0] release_rate;
reg [6:0] sustain_value;
wire [17:0] volume;
wire [4:0] state;
reg [7:0] count;
// Instantiate the Unit Under Test (UUT)
adsr_mngt uut (
.clk(clk),
.rst(rst),
.new_sample(new_sample),
.new_note_pulse(new_note_pulse),
.release_note_pulse(release_note_pulse),
.attack_rate(attack_rate),
.decay_rate(decay_rate),
.release_rate(release_rate),
.sustain_value(sustain_value),
.volume(volume),
.state(state)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
new_sample = 0;
new_note_pulse = 0;
release_note_pulse = 0;
attack_rate = 7'hFF;
decay_rate = 7'hFF;
release_rate = 7'hFF;
sustain_value = 7'b0100000;
count = 0;
// Wait 10 ns for global reset to finish
#20;
rst = 1;
#60
rst = 0;
// Add stimulus here
#4000
new_note_pulse = 1;
#20
new_note_pulse = 0;
// // release in sustain state
// #80000
// release_note_pulse = 1;
// #20
// release_note_pulse = 0;
// release in sustain state
#70000
release_note_pulse = 1;
#20
release_note_pulse = 0;
end
always begin
#10
clk <= ~clk;
end
always @(posedge clk) begin
count <= count +1;
if (count == 127)
new_sample <= 1'b1;
else
new_sample <= 1'b0;
end
endmodule
| 6.550976 |
module testbench_all (
output wire completed
);
wire [5:0] completion;
assign completed = &completion;
testbench_arith p_arith (completion[0]);
testbench_cpu p_cpu (completion[1]);
testbench_extcall p_extcall (completion[2]);
testbench_ram p_ram (completion[3]);
testbench_top p_top (completion[4]);
testbench_utils p_utils (completion[5]);
initial begin
#10;
while (!completed) #10;
$info("[all] Test group completed.");
end
endmodule
| 7.451523 |
module TestBench ();
reg [1:0] x;
wire y;
and_behavioral_level behavioral_level_module (
y,
x
);
reg [1:0] index;
initial begin
$dumpfile("TimingDiagram.vcd");
$dumpvars(0, y, x);
index = 0;
repeat (6) begin
x = index;
index = index + 1;
#20;
end
$finish;
end
endmodule
| 7.747207 |
module testbench_tricomp0_sync (
output reg completed
);
`include "../utils.h"
integer ii;
reg [17:0] in;
wire p;
wire z;
wire n;
wire [2:0] pzn = {p, z, n};
tricomp0_sync comp0 (
.in (in),
.pos (p),
.zero(z),
.neg (n)
);
initial begin
completed = 0;
for (ii = -9841; ii <= 9841; ii = ii + 1) begin
in = util_int_to_tryte(ii);
#10;
if (ii < 0) if (pzn !== 3'b001) $error("[tricomp0_sync] %d", ii);
if (ii === 0) if (pzn !== 3'b010) $error("[tricomp0_sync] %d", ii);
if (ii > 0) if (pzn !== 3'b100) $error("[tricomp0_sync] %d", ii);
end
completed = 1;
$display("[tricomp0_sync] Test completed.");
end
endmodule
| 7.180779 |
module testbench_trisfcomp_sync (
output reg completed
);
`include "../utils.h"
integer ii;
reg [17:0] in;
wire signed [1:0] sf;
trisfcomp_sync sfcomp (
.in(in),
.sf(sf)
);
initial begin
completed = 0;
for (ii = -9841; ii <= 9841; ii = ii + 1) begin
in = util_int_to_tryte(ii);
#10;
if (ii < 0) if (sf !== 2'b11) $error("[trisfcomp_sync] %d", ii);
if (ii === 0) if (sf !== 2'b00) $error("[trisfcomp_sync] %d", ii);
if (ii > 0) if (sf !== 2'b01) $error("[trisfcomp_sync] %d", ii);
end
completed = 1;
$display("[trisfcomp_sync] Test completed.");
end
endmodule
| 7.180779 |
module testbench_tricomp_sync (
output reg completed
);
`include "../utils.h"
integer ii;
integer ij;
reg [17:0] lhs;
reg neg_rhs;
reg [17:0] rhs;
wire gt;
wire eq;
wire lt;
wire [2:0] gel = {gt, eq, lt};
tricomp_sync comp (
.lhs(lhs),
.neg_rhs(neg_rhs),
.rhs(rhs),
.gt(gt),
.eq(eq),
.lt(lt)
);
initial begin
completed = 0;
neg_rhs = 1'b0;
for (ii = -10; ii <= 10; ii = ii + 1)
for (ij = -9841; ij <= 9841; ij = ij + 1) begin
lhs = util_int_to_tryte(ii);
rhs = util_int_to_tryte(ij);
#10;
if (ii < ij) if (gel !== 3'b001) $error("[tricomp_sync] ~neg %d %d", ii, ij);
if (ii === ij) if (gel !== 3'b010) $error("[tricomp_sync] ~neg %d %d", ii, ij);
if (ii > ij) if (gel !== 3'b100) $error("[tricomp_sync] ~neg %d %d", ii, ij);
end
neg_rhs = 1'b1;
for (ii = -10; ii <= 10; ii = ii + 1)
for (ij = -9841; ij <= 9841; ij = ij + 1) begin
lhs = util_int_to_tryte(ii);
rhs = util_int_to_tryte(ij);
#10;
if (ii < -ij) if (gel !== 3'b001) $error("[tricomp_sync] neg %d %d", ii, ij);
if (ii === -ij) if (gel !== 3'b010) $error("[tricomp_sync] neg %d %d", ii, ij);
if (ii > -ij) if (gel !== 3'b100) $error("[tricomp_sync] neg %d %d", ii, ij);
end
completed = 1;
$display("[tricomp_sync] Test completed.");
end
endmodule
| 7.180779 |
module testbench_triinc_sync (
output reg completed
);
`include "../utils.h"
integer ii;
integer ires;
reg [17:0] inc_in;
wire [17:0] inc_res;
wire signed [1:0] inc_cf;
wire signed [1:0] inc_sf;
triinc_sync inc (
.in(inc_in),
.res(inc_res),
.cf (inc_cf),
.sf (inc_sf)
);
initial begin
completed = 0;
for (ii = -9841; ii < -1; ii = ii + 1) begin
inc_in = util_int_to_tryte(ii);
ires = ii + 1;
#10;
if (inc_res !== util_int_to_tryte(ires) || inc_cf !== 2'b00 || inc_sf !== 2'b11) begin
$error("[triinc_sync] %d", ii);
end
end
ii = -1;
inc_in = util_int_to_tryte(ii);
ires = ii + 1;
#10;
if (inc_res !== util_int_to_tryte(ires) || inc_cf !== 2'b00 || inc_sf !== 2'b00) begin
$error("[triinc_sync] %d", ii);
end
for (ii = 0; ii < 9841; ii = ii + 1) begin
inc_in = util_int_to_tryte(ii);
ires = ii + 1;
#10;
if (inc_res !== util_int_to_tryte(ires) || inc_cf !== 2'b00 || inc_sf !== 2'b01) begin
$error("[triinc_sync] %d", ii);
end
end
ii = 9841;
inc_in = util_int_to_tryte(ii);
ires = -9841;
#10;
if (inc_res !== util_int_to_tryte(ires) || inc_cf !== 2'b01 || inc_sf !== 2'b01) begin
$error("[triinc_sync] %d", ii);
end
completed = 1;
$display("[triinc_sync] Test completed.");
end
endmodule
| 7.180779 |
module testbench_tridec_sync (
output reg completed
);
`include "../utils.h"
integer ii;
integer ires;
reg [17:0] dec_in;
wire [17:0] dec_res;
wire signed [1:0] dec_cf;
wire signed [1:0] dec_sf;
tridec_sync dec (
.in(dec_in),
.res(dec_res),
.cf (dec_cf),
.sf (dec_sf)
);
initial begin
completed = 0;
ii = -9841;
dec_in = util_int_to_tryte(ii);
ires = 9841;
#10;
if (dec_res !== util_int_to_tryte(ires) || dec_cf !== 2'b11 || dec_sf !== 2'b11) begin
$error("[tridec_sync] %d", ii);
end
for (ii = -9840; ii < 1; ii = ii + 1) begin
dec_in = util_int_to_tryte(ii);
ires = ii - 1;
#10;
if (dec_res !== util_int_to_tryte(ires) || dec_cf !== 2'b00 || dec_sf !== 2'b11) begin
$error("[tridec_sync] %d", ii);
end
end
ii = 1;
dec_in = util_int_to_tryte(ii);
ires = ii - 1;
#10;
if (dec_res !== util_int_to_tryte(ires) || dec_cf !== 2'b00 || dec_sf !== 2'b00) begin
$error("[tridec_sync] %d", ii);
end
for (ii = 2; ii <= 9841; ii = ii + 1) begin
dec_in = util_int_to_tryte(ii);
ires = ii - 1;
#10;
if (dec_res !== util_int_to_tryte(ires) || dec_cf !== 2'b00 || dec_sf !== 2'b01) begin
$error("[tridec_sync] %d", ii);
end
end
completed = 1;
$display("[tridec_sync] Test completed.");
end
endmodule
| 7.180779 |
module testbench_triaddtri_sync (
output reg completed
);
`include "../utils.h"
`include "numbers.h"
integer ils;
integer ilhsi;
integer ilhs;
integer ims;
integer imhsi;
integer imhs;
integer irs;
integer irhsi;
integer irhs;
integer ires;
reg lsub;
reg [17:0] lhs;
reg msub;
reg [17:0] mhs;
reg rsub;
reg [17:0] rhs;
wire [17:0] res;
wire signed [1:0] cf;
wire signed [1:0] sf;
triaddtri_sync add (
.lsub(lsub),
.lhs (lhs),
.msub(msub),
.mhs (mhs),
.rsub(rsub),
.rhs (rhs),
.res(res),
.cf (cf),
.sf (sf)
);
initial begin
completed = 0;
for (ils = -1; ils <= 1; ils = ils + 2)
for (ims = -1; ims <= 1; ims = ims + 2)
for (irs = -1; irs <= 1; irs = irs + 2)
for (ilhsi = 0; ilhsi <= 24; ilhsi = ilhsi + 1)
for (imhsi = 0; imhsi <= 24; imhsi = imhsi + 1)
for (irhsi = 0; irhsi <= 24; irhsi = irhsi + 1) begin
lsub = ils == -1;
msub = ims == -1;
rsub = irs == -1;
ilhs = util_test_numbers(ilhsi);
imhs = util_test_numbers(imhsi);
irhs = util_test_numbers(irhsi);
lhs = util_int_to_tryte(ilhs);
mhs = util_int_to_tryte(imhs);
rhs = util_int_to_tryte(irhs);
ires = ils * ilhs + ims * imhs + irs * irhs;
#10;
if ({cf, res} !== util_int_to_trits10(
ires
) || (ires < 0 && sf !== 2'b11) || (ires === 0 && sf !== 2'b00) ||
(ires > 0 && sf !== 2'b01)) begin
$error("[triaddtri_sync] %d %d %d %d %d %d", ils, ims, irs, ilhs, imhs, irhs);
end
end
completed = 1;
$display("[triaddtri_sync] Test completed.");
end
endmodule
| 7.180779 |
module testbench_triaddtri (
output reg completed
);
`include "../utils.h"
`include "numbers.h"
integer ils;
integer ilhsi;
integer ilhs;
integer ims;
integer imhsi;
integer imhs;
integer irs;
integer irhsi;
integer irhs;
integer ires;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
reg enable;
reg lsub;
reg [17:0] lhs;
reg msub;
reg [17:0] mhs;
reg rsub;
reg [17:0] rhs;
wire ready;
wire [17:0] res;
wire signed [1:0] cf;
wire signed [1:0] sf;
triaddtri add (
.clk(clk),
.rst(rst),
.e(enable),
.lsub(lsub),
.lhs(lhs),
.msub(msub),
.mhs(mhs),
.rsub(rsub),
.rhs(rhs),
.o (ready),
.res(res),
.cf (cf),
.sf (sf)
);
initial begin
completed = 0;
enable = 0;
rst = 1;
#160;
rst = 0;
for (ils = -1; ils <= 1; ils = ils + 2)
for (ims = -1; ims <= 1; ims = ims + 2)
for (irs = -1; irs <= 1; irs = irs + 2)
for (ilhsi = 0; ilhsi <= 24; ilhsi = ilhsi + 1)
for (imhsi = 0; imhsi <= 24; imhsi = imhsi + 1)
for (irhsi = 0; irhsi <= 24; irhsi = irhsi + 1) begin
lsub = ils == -1;
msub = ims == -1;
rsub = irs == -1;
ilhs = util_test_numbers(ilhsi);
imhs = util_test_numbers(imhsi);
irhs = util_test_numbers(irhsi);
lhs = util_int_to_tryte(ilhs);
mhs = util_int_to_tryte(imhs);
rhs = util_int_to_tryte(irhs);
ires = ils * ilhs + ims * imhs + irs * irhs;
enable = 1;
#10;
enable = 0;
while (!ready) #10;
if ({cf, res} !== util_int_to_trits10(
ires
) || (ires < 0 && sf !== 2'b11) || (ires === 0 && sf !== 2'b00) ||
(ires > 0 && sf !== 2'b01)) begin
$error("[triaddtri] %d %d %d %d %d %d", ils, ims, irs, ilhs, imhs, irhs);
end
end
enable = 1;
lsub = 1;
msub = 0;
rsub = 0;
lhs = util_int_to_tryte(2);
mhs = util_int_to_tryte(1);
rhs = util_int_to_tryte(1);
ires = 0;
#10;
enable = 0;
while (!ready) #10;
if ({cf, res} !== util_int_to_trits10(ires) || sf !== 2'b00) $error("[triaddtri] mem 0");
#100;
if ({cf, res} !== util_int_to_trits10(ires) || sf !== 2'b00) $error("[triaddtri] mem 1");
mhs = util_int_to_tryte(-2);
#100;
if ({cf, res} !== util_int_to_trits10(ires) || sf !== 2'b00) $error("[triaddtri] mem 2");
enable = 1;
ires = -3;
#10;
enable = 0;
while (!ready) #10;
if ({cf, res} !== util_int_to_trits10(ires) || sf !== 2'b11) $error("[triaddtri] mem 3");
#100;
if ({cf, res} !== util_int_to_trits10(ires) || sf !== 2'b11) $error("[triaddtri] mem 4");
lsub = 0;
#100;
if ({cf, res} !== util_int_to_trits10(ires) || sf !== 2'b11) $error("[triaddtri] mem 5");
enable = 1;
ires = 1;
#10;
enable = 0;
while (!ready) #10;
if ({cf, res} !== util_int_to_trits10(ires) || sf !== 2'b01) $error("[triaddtri] mem 6");
#100;
if ({cf, res} !== util_int_to_trits10(ires) || sf !== 2'b01) $error("[triaddtri] mem 7");
completed = 1;
$display("[triaddtri] Test completed.");
end
endmodule
| 7.180779 |
module testbench_trimul (
output reg completed
);
`include "../utils.h"
`include "numbers.h"
integer ilhsi;
integer ilhs;
integer irhsi;
integer irhs;
integer ires;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
reg enable;
reg [17:0] lhs;
reg [17:0] rhs;
wire [17:0] res;
wire ready;
wire signed [1:0] cf;
wire signed [1:0] sf;
trimul mul (
.clk(clk),
.rst(rst),
.e (enable),
.lhs(lhs),
.rhs(rhs),
.o (ready),
.res(res),
.cf (cf),
.sf (sf)
);
initial begin
completed = 0;
enable = 0;
rst = 1;
#160;
rst = 0;
for (ilhsi = 0; ilhsi <= 24; ilhsi = ilhsi + 1)
for (irhsi = 0; irhsi <= 24; irhsi = irhsi + 1) begin
ilhs = util_test_numbers(ilhsi);
irhs = util_test_numbers(irhsi);
lhs = util_int_to_tryte(ilhs);
rhs = util_int_to_tryte(irhs);
ires = ilhs * irhs;
enable = 1;
#10;
enable = 0;
while (!ready) #10;
if (res !== util_int_to_tryte(
ires
) || cf !== 2'b00 || (ires < 0 && sf !== 2'b11) || (ires == 0 && sf !== 2'b00) ||
(ires > 0 && sf !== 2'b01)) begin
$error("[trimul] %d %d", ilhs, irhs);
end
end
enable = 1;
lhs = util_int_to_tryte(2);
rhs = util_int_to_tryte(3);
ires = 6;
#10;
enable = 0;
while (!ready) #10;
if (res !== util_int_to_tryte(ires) || cf !== 2'b00 || sf !== 2'b01) $error("[trimul] mem 0");
#100;
if (res !== util_int_to_tryte(ires) || cf !== 2'b00 || sf !== 2'b01) $error("[trimul] mem 1");
rhs = util_int_to_tryte(-5);
#100;
if (res !== util_int_to_tryte(ires) || cf !== 2'b00 || sf !== 2'b01) $error("[trimul] mem 2");
enable = 1;
ires = -10;
#10;
enable = 0;
while (!ready) #10;
if (res !== util_int_to_tryte(ires) || cf !== 2'b00 || sf !== 2'b11) $error("[trimul] mem 3");
#100;
if (res !== util_int_to_tryte(ires) || cf !== 2'b00 || sf !== 2'b11) $error("[trimul] mem 4");
lhs = util_int_to_tryte(0);
#100;
if (res !== util_int_to_tryte(ires) || cf !== 2'b00 || sf !== 2'b11) $error("[trimul] mem 5");
enable = 1;
ires = 0;
#10;
enable = 0;
while (!ready) #10;
if (res !== util_int_to_tryte(ires) || cf !== 2'b00 || sf !== 2'b00) $error("[trimul] mem 6");
#100;
if (res !== util_int_to_tryte(ires) || cf !== 2'b00 || sf !== 2'b00) $error("[trimul] mem 7");
completed = 1;
$display("[trimul] Test completed.");
end
endmodule
| 7.180779 |
module testbench_trishl_sync (
output reg completed
);
`include "../utils.h"
`include "numbers.h"
integer ilhsi;
integer ilhs;
integer irs;
integer irhs;
reg [17:0] exp_res;
reg [17:0] lhs;
reg neg_rhs;
reg [5:0] rhs;
wire [17:0] res;
wire signed [1:0] cf;
wire signed [1:0] sf;
trishl_sync shl (
.lhs(lhs),
.neg_rhs(neg_rhs),
.rhs(rhs),
.res(res),
.cf (cf),
.sf (sf)
);
initial begin
completed = 0;
for (irs = -1; irs <= 1; irs = irs + 2)
for (ilhsi = 0; ilhsi <= 24; ilhsi = ilhsi + 1)
for (irhs = -13; irhs <= 13; irhs = irhs + 1) begin
neg_rhs = irs == -1;
ilhs = util_test_numbers(ilhsi);
lhs = util_int_to_tryte(ilhs);
rhs = util_int_to_tryte(irhs);
if (neg_rhs) begin
if (irhs < 0) exp_res = lhs << (2 * (-irhs));
else exp_res = lhs >> (2 * irhs);
end else begin
if (irhs < 0) exp_res = lhs >> (2 * (-irhs));
else exp_res = lhs << (2 * irhs);
end
#10;
// XXX: Not testing sf.
if (res !== exp_res || cf !== 0) $error("[trishl_sync] %d %d %d", irs, ilhs, irhs);
end
completed = 1;
$display("[trishl_sync] Test completed.");
end
endmodule
| 7.180779 |
module testbench_arith (
output wire completed
);
wire [10:0] completion;
assign completed = &completion;
testbench_tricomp0_sync p_tricomp0_sync (completion[0]);
testbench_trisfcomp_sync p_trisfcomp_sync (completion[1]);
testbench_tricomp_sync p_tricomp_sync (completion[2]);
testbench_triadd_sync p_triadd_sync (completion[3]);
testbench_triadd p_triadd (completion[4]);
testbench_triinc_sync p_triinc_sync (completion[5]);
testbench_tridec_sync p_tridec_sync (completion[6]);
testbench_triaddtri_sync p_triaddtri_sync (completion[7]);
testbench_triaddtri p_triaddtri (completion[8]);
testbench_trimul p_trimul (completion[9]);
testbench_trishl_sync p_trishl_sync (completion[10]);
initial begin
#10;
while (!completed) #10;
$display("[arith] Test group completed.");
end
endmodule
| 7.212422 |
module Testbench_Barrel_Shifter ();
parameter PERIOD = 10;
parameter EW = 8;
parameter SW = 26;
//inputs
reg clk;
reg rst;
reg ctrl_a_i;
reg [EW-1:0] Shift_Value_0_i;
reg [EW-1:0] Shift_Value_1_i;
reg [SW-1:0] Shift_Data_0_i;
reg [SW-1:0] Shift_Data_1_i;
reg FSM_left_right_i;
reg FSM_select_C_i;
/////////////////////////////////////////////7
wire [SW-1:0] N_mant_o;
Barrel_Shifter #(
.SW(SW),
.EW(EW)
) uut (
.clk(clk),
.rst(rst),
.ctrl_a_i(ctrl_a_i),
.Shift_Value_0_i(Shift_Value_0_i),
.Shift_Value_1_i(Shift_Value_1_i),
.Shift_Data_0_i(Shift_Data_0_i),
.Shift_Data_1_i(Shift_Data_1_i),
.FSM_left_right_i(FSM_left_right_i),
.FSM_select_C_i(FSM_select_C_i),
.N_mant_o(N_mant_o)
);
/* reg [31:0] Array_IN [0:((2**width)-1)];
reg [31:0] Array_IN_2 [0:((2**width)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;*/
initial begin
// Initialize Input
rst = 1;
ctrl_a_i = 1;
Shift_Value_0_i = 8'b00001001;
Shift_Value_1_i = 0;
Shift_Data_0_i = 26'b11101010001011101100010000;
Shift_Data_1_i = 0;
FSM_left_right_i = 0;
FSM_select_C_i = 0;
// Wait 100 ns for global reset to finish
#100 rst = 0;
//Add stimulus here
end
initial begin
clk = 1'b0;
#(PERIOD / 2);
forever #(PERIOD / 2) clk = ~clk;
end
endmodule
| 7.839439 |
module bcd_tb ();
reg [3:0] tb_A;
reg [3:0] tb_B;
reg tb_cin;
wire [3:0] tb_sum;
wire tb_cout;
reg [7:0] tb_E = 8'b00000000;
wire [2:0] tb_F;
reg clk;
initial clk = 0;
always #10 clk = ~clk;
reg [31:0] tb_mem[0:13];
lab6_2circuits bcd_ins (
.A(tb_A),
.B(tb_B),
.cin(tb_cin),
.sum(tb_sum),
.cout(tb_cout),
.E(tb_E),
.F(tb_F),
.clock(clk)
);
initial begin
$readmemh("configure_bcd_adder.mem", tb_mem);
bcd_ins.ins1.mem[31:0] = tb_mem[0];
bcd_ins.ins1.mem[32] = tb_mem[1];
bcd_ins.ins2.mem[31:0] = tb_mem[2];
bcd_ins.ins2.mem[32] = tb_mem[3];
bcd_ins.ins3.mem[31:0] = tb_mem[0];
bcd_ins.ins3.mem[32] = tb_mem[1];
bcd_ins.ins4.mem[31:0] = tb_mem[2];
bcd_ins.ins4.mem[32] = tb_mem[3];
bcd_ins.ins5.mem[31:0] = tb_mem[0];
bcd_ins.ins5.mem[32] = tb_mem[1];
bcd_ins.ins6.mem[31:0] = tb_mem[2];
bcd_ins.ins6.mem[32] = tb_mem[3];
bcd_ins.ins7.mem[31:0] = tb_mem[0];
bcd_ins.ins7.mem[32] = tb_mem[1];
bcd_ins.ins8.mem[31:0] = tb_mem[2];
bcd_ins.ins8.mem[32] = tb_mem[3];
bcd_ins.ins9.mem[31:0] = tb_mem[4];
bcd_ins.ins9.mem[32] = tb_mem[5];
bcd_ins.ins10.mem[31:0] = tb_mem[6];
bcd_ins.ins10.mem[32] = tb_mem[7];
bcd_ins.ins11.mem[31:0] = tb_mem[8];
bcd_ins.ins11.mem[32] = tb_mem[9];
bcd_ins.ins12.mem[31:0] = tb_mem[10];
bcd_ins.ins12.mem[32] = tb_mem[11];
bcd_ins.ins13.mem[31:0] = tb_mem[12];
bcd_ins.ins13.mem[32] = tb_mem[13];
tb_A = 4'b0101;
tb_B = 4'b0001;
tb_cin = 1'b0;
#20
$display(
"BCD adder:: A= %b ,B= %b ,cin= %b, sum= %b ,cout=%b", tb_A, tb_B, tb_cin, tb_sum, tb_cout
);
tb_A = 4'b0101;
tb_B = 4'b0001;
tb_cin = 1;
#20
$display(
"BCD adder:: A= %b ,B= %b ,cin= %b, sum= %b ,cout=%b", tb_A, tb_B, tb_cin, tb_sum, tb_cout
);
tb_A = 4'b0111;
tb_B = 4'b0001;
tb_cin = 1;
#20
$display(
"BCD adder:: A= %b ,B= %b ,cin= %b, sum= %b ,cout=%b", tb_A, tb_B, tb_cin, tb_sum, tb_cout
);
tb_A = 4'b1111;
tb_B = 4'b0001;
tb_cin = 1;
#20
$display(
"BCD adder:: A= %b ,B= %b ,cin= %b, sum= %b ,cout=%b", tb_A, tb_B, tb_cin, tb_sum, tb_cout
);
end
initial #1000 $finish;
initial begin
$dumpfile("2019csb1100_bcd.vcd");
$dumpvars;
end
endmodule
| 6.696849 |
module TestBench_BF_Dec;
wire [7:0] D;
reg [3:0] I;
reg [1:0] E;
BF_decoder_3_bit D0 (
D,
I,
E[0]
);
initial begin
for (E = 2'b00; E <= 2'b01; E = E + 2'b01) for (I = 4'b0000; I <= 4'b0111; I = I + 4'b0001) #50;
end
initial $monitor($time, "\t I=%b D=%b E=%b", I, D, E);
endmodule
| 7.106562 |
module testbench_bintogray ();
parameter CLK_PERIOD = 10;
reg clk;
reg rst;
reg [3:0] data;
wire [3:0] gray_data;
// Ӳģ
bin_to_Gray bin_to_Gray_test (
.clk (clk),
.rst (rst),
.data (data),
.gray_data(gray_data)
);
// ʼʱӺλ
initial begin
clk <= 0;
rst <= 0;
data <= 0;
#1000;
rst <= 1;
end
always begin
#(CLK_PERIOD / 2) clk = ~clk;
end
// Լ
integer i;
initial begin
@(posedge rst);
@(posedge clk) begin
for (i = 0; i < 50; i = i + 1) begin
#500;
data <= {$random} % 15;
#300 data <= 0;
end
end
data <= 0;
#10000;
$stop;
end
endmodule
| 6.718156 |
module TB_booth;
parameter multiplier_width = 8;
parameter multiplicand_width = 8;
wire [multiplicand_width-1 : 0] AC;
wire [ multiplier_width-1 : 0] QR;
reg [multiplicand_width-1 : 0] multiplicand;
reg [ multiplier_width-1 : 0] multiplier;
booth_algo booth (
AC,
QR,
multiplicand,
multiplier
);
initial begin
multiplicand = 8'd16;
multiplier = 8'd32;
#40 multiplicand = 8'd100;
multiplier = 8'd15;
#40 $finish;
end
endmodule
| 6.612465 |
module TestBench_brush ();
parameter SLOWNESS = 8, //number of position of counter clock divider
RESOLUTION_H = 640, RESOLUTION_V = 480, HPOS_WIDTH = 0, //coordinate wires width
VPOS_WIDTH=0,
V_TOP = 10,
V_SYNC = 2,
V_BOTTOM =33,
H_FRONT = 16,
H_SYNC = 96,
H_BACK = 48,
BRUSH_SIZE=10,
BRUSH_COLOR=3'b101;
localparam X_WIRE_WIDTH = $clog2(
RESOLUTION_H + H_FRONT + H_SYNC + H_BACK
), Y_WIRE_WIDTH = $clog2(
RESOLUTION_V + V_BOTTOM + V_SYNC + V_TOP
), TESTSQUARE_LEFTSIDE = 0, TESTSQUARE_RIGHTSIDE = 20, TESTSQUARE_TOPSIDE = 0,
TESTSQUARE_DOWNSIDE = 30;
reg clk, reset_n, enable;
reg [3:0] BTN; // [2:0]key_sw;
reg [X_WIRE_WIDTH - 1:0] hpos;
reg [Y_WIRE_WIDTH - 1:0] vpos;
reg [2:0] FB_RGB;
brush #(
.SLOWNESS (SLOWNESS),
.RESOLUTION_H(RESOLUTION_H),
.RESOLUTION_V(RESOLUTION_V),
.HPOS_WIDTH (X_WIRE_WIDTH),
.VPOS_WIDTH (Y_WIRE_WIDTH),
.BRUSH_SIZE (BRUSH_SIZE),
.BRUSH_COLOR (BRUSH_COLOR),
.INIT_XPOS ('d10),
.INIT_YPOS ('d12)
) Painting_Brush (
.clk (clk),
.reset (~reset_n),
.BTN (BTN), // [2:0]movedirection=[2:0]key_sw
.enable(enable),
.hpos (hpos),
.vpos (vpos),
.FB_RGB(FB_RGB)
);
always #5 clk = ~clk;
initial begin
clk = 0;
reset_n = 0;
BTN = 0;
enable = 0;
hpos = TESTSQUARE_LEFTSIDE;
vpos = TESTSQUARE_TOPSIDE;
FB_RGB = 0;
#10 reset_n = 1;
#10 enable = 1;
FB_RGB = 'b111;
end
always @(posedge clk) begin
if (enable) begin
if (hpos != TESTSQUARE_RIGHTSIDE) hpos = hpos + 1;
else hpos = TESTSQUARE_LEFTSIDE;
end
end
always @(posedge clk) begin
if (hpos == TESTSQUARE_RIGHTSIDE) begin
if (vpos != TESTSQUARE_DOWNSIDE) vpos = vpos + 1;
else vpos = TESTSQUARE_TOPSIDE;
end
end
endmodule
| 6.842661 |
module TestBench_BtoG;
wire [3:0] Y;
reg [4:0] I;
Bin2Gray B (
Y[3:0],
I[3:0]
);
initial begin
for (I = 5'b00000; I <= 5'b01111; I = I + 5'b00001) #50;
end
initial $monitor($time, "\t I = %b, Y = %b", I, Y);
endmodule
| 6.695215 |
module testbench_carry_select_adder ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
carry_select_adder uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 0 && of == 0) begin
$display("Test case 1 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 1 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve with overflow
a = 32'h8fffffff;
b = 32'h8fffffff;
Cin = 0;
#100
if (sum == 32'h1ffffffe && Cout == 1 && of == 0) begin
$display("Test case 2 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 2 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + -ve
a = 32'h7AA;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'h000007a9 && Cout == 1 && of == 0) begin
$display("Test case 3 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 3 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + +ve without overflow
a = 32'hAF;
b = 32'hAF;
Cin = 1;
#100
if (sum == 32'h0000015f && Cout == 0 && of == 0) begin
$display("Test case 4 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 4 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve without overflow
a = 32'hffffffff;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 1 && of == 0) begin
$display("Test case 5 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 5 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case1
a = 32'h123;
b = 32'hfffff123;
Cin = 0;
#100
if (sum == 32'hfffff246 && Cout == 0 && of == 0) begin
$display("Test case 6 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 6 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case2
a = 32'hfffff999;
b = 32'h111;
Cin = 0;
#100
if (sum == 32'hfffffaaa && Cout == 0 && of == 0) begin
$display("Test case 7 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 7 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case3
a = 32'h0;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hffffffff && Cout == 0 && of == 0) begin
$display("Test case 8 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 8 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
end
endmodule
| 7.061901 |
module testbench_cbpa ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
cbpa uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 0 && of == 0) begin
$display("Test case 1 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 1 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve with overflow
a = 32'h8fffffff;
b = 32'h8fffffff;
Cin = 0;
#100
if (sum == 32'h1ffffffe && Cout == 1 && of == 0) begin
$display("Test case 2 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 2 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + -ve
a = 32'h7AA;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'h000007a9 && Cout == 1 && of == 0) begin
$display("Test case 3 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 3 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + +ve without overflow
a = 32'hAF;
b = 32'hAF;
Cin = 1;
#100
if (sum == 32'h0000015f && Cout == 0 && of == 0) begin
$display("Test case 4 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 4 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve without overflow
a = 32'hffffffff;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 1 && of == 0) begin
$display("Test case 5 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 5 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case1
a = 32'h123;
b = 32'hfffff123;
Cin = 0;
#100
if (sum == 32'hfffff246 && Cout == 0 && of == 0) begin
$display("Test case 6 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 6 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case2
a = 32'hfffff999;
b = 32'h111;
Cin = 0;
#100
if (sum == 32'hfffffaaa && Cout == 0 && of == 0) begin
$display("Test case 7 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 7 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case3
a = 32'h0;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hffffffff && Cout == 0 && of == 0) begin
$display("Test case 8 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 8 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
end
endmodule
| 6.888891 |
module tb_channel;
logic [0:0] clk;
logic [1:0] count;
logic [0:0] reset;
logic [0:0] recv__en;
CGRAData_32_1_1 recv__msg;
logic [0:0] recv__rdy;
logic [0:0] send__en;
CGRAData_32_1_1 send__msg;
logic [0:0] send__rdy;
ChannelRTL__DataType_CGRAData_32_1_1__latency_1 dut (
.clk(clk),
.count(count),
.reset(reset),
.recv__en(recv__en),
.recv__msg(recv__msg),
.recv__rdy(recv__rdy),
.send__en(send__en),
.send__msg(send__msg),
.send__rdy(send__rdy)
);
initial begin
reset <= 1;
#10;
reset <= 0;
#10;
reset <= 1;
recv__en = 1'd1;
recv__msg = {32'hECEBECEB, 1'd1, 1'd1};
send__rdy = 1'd1;
#10;
recv__en = 1'd1;
recv__msg = {32'hAAAAAAAA, 1'd1, 1'd1};
send__rdy = 1'd1;
end
always begin
clk <= 1;
#5;
clk <= 0;
#5;
end
endmodule
| 6.532607 |
module testbench_CIA ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
CarryIncrementAdder uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 0 && of == 0) begin
$display("Test case 1 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 1 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve with overflow
a = 32'h8fffffff;
b = 32'h8fffffff;
Cin = 0;
#100
if (sum == 32'h1ffffffe && Cout == 1 && of == 0) begin
$display("Test case 2 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 2 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + -ve
a = 32'h7AA;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'h000007a9 && Cout == 1 && of == 0) begin
$display("Test case 3 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 3 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + +ve without overflow
a = 32'hAF;
b = 32'hAF;
Cin = 1;
#100
if (sum == 32'h0000015f && Cout == 0 && of == 0) begin
$display("Test case 4 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 4 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve without overflow
a = 32'hffffffff;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 1 && of == 0) begin
$display("Test case 5 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 5 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case1
a = 32'h123;
b = 32'hfffff123;
Cin = 0;
#100
if (sum == 32'hfffff246 && Cout == 0 && of == 0) begin
$display("Test case 6 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 6 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case2
a = 32'hfffff999;
b = 32'h111;
Cin = 0;
#100
if (sum == 32'hfffffaaa && Cout == 0 && of == 0) begin
$display("Test case 7 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 7 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case3
a = 32'h0;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hffffffff && Cout == 0 && of == 0) begin
$display("Test case 8 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 8 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
end
endmodule
| 6.771059 |
module TestBench_CLA;
wire [3:0] S;
wire C;
reg [4:0] A, B;
reg [1:0] K;
carryLookaheadAdder_4_bit CLA (
S,
C,
A[3:0],
B[3:0],
K[0]
);
initial begin
for (A = 5'b00000; A <= 5'b01111; A = A + 5'b00001)
for (B = 5'b00000; B <= 5'b01111; B = B + 5'b00001)
for (K = 2'b00; K <= 2'b01; K = K + 2'b01) #50;
end
initial $monitor($time, "\t A=%d B=%d K=%d S=%d C=%d", A, B, K, S, C);
endmodule
| 6.648325 |
module testbench_CLA_adder ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
CLA_adder uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 0 && of == 0) begin
$display("Test case 1 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 1 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve with overflow
a = 32'h8fffffff;
b = 32'h8fffffff;
Cin = 0;
#100
if (sum == 32'h1ffffffe && Cout == 1 && of == 0) begin
$display("Test case 2 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 2 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + -ve
a = 32'h7AA;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'h000007a9 && Cout == 1 && of == 0) begin
$display("Test case 3 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 3 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + +ve without overflow
a = 32'hAF;
b = 32'hAF;
Cin = 1;
#100
if (sum == 32'h0000015f && Cout == 0 && of == 0) begin
$display("Test case 4 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 4 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve without overflow
a = 32'hffffffff;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 1 && of == 0) begin
$display("Test case 5 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 5 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case1
a = 32'h123;
b = 32'hfffff123;
Cin = 0;
#100
if (sum == 32'hfffff246 && Cout == 0 && of == 0) begin
$display("Test case 6 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 6 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case2
a = 32'hfffff999;
b = 32'h111;
Cin = 0;
#100
if (sum == 32'hfffffaaa && Cout == 0 && of == 0) begin
$display("Test case 7 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 7 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case3
a = 32'h0;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hffffffff && Cout == 0 && of == 0) begin
$display("Test case 8 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 8 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
end
endmodule
| 6.707837 |
module: Clock_screen_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TestBench_Clock_screen_top;
// Inputs
reg clk;
reg reset;
// Outputs
wire hsync;
wire vsync;
wire [11:0] RGB;
// Instantiate the Unit Under Test (UUT)
Clock_screen_top uut (
.clk(clk),
.reset(reset),
.hsync(hsync),
.vsync(vsync),
.RGB(RGB),
.pixel_tick(pixel_tick)
);
//Para generar clock de 100 MHz
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial
begin
// Initialize Inputs
reset = 1;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
#50000000$stop;
end
initial begin
$timeformat(-5,1,"ns",4);
$display("hsync vsync RGB[0] RGB[1] RGB[2] RGB[3] RGB[4] RGB[5] RGB[6] RGB[7] RGB[8] RGB[9] RGB[10] RGB[11]");
$monitor("%t: %b %b %b %b %b %b %b %b %b %b %b %b %b %b", $realtime,
hsync, vsync, RGB[0],RGB[1],RGB[2],RGB[3],RGB[4],RGB[5],RGB[6],RGB[7],RGB[8],RGB[9],RGB[10],RGB[11]);
end
endmodule
| 7.868932 |
module testbench_color;
parameter size = 110592, rows = 192, cols = 192;
color #(
.infile("rahul_in_hex.hex"),
.outfile("rahul_out_3_hex.hex"),
.size(size),
.rows(rows),
.cols(cols),
.ksize(3)
) k3 (); //instantiating module color which will give output hex file for kernel size 3x3
color #(
.infile("rahul_in_hex.hex"),
.outfile("rahul_out_5_hex.hex"),
.size(size),
.rows(rows),
.cols(cols),
.ksize(5)
) k5 (); //instantiating module color which will give output hex file for kernel size 5x5
color #(
.infile("rahul_in_hex.hex"),
.outfile("rahul_out_7_hex.hex"),
.size(size),
.rows(rows),
.cols(cols),
.ksize(7)
) k7 (); //instantiating module color which will give output hex file for kernel size 7x7
endmodule
| 8.065258 |
module Testbench;
reg reset, clk;
wire rw;
wire [15:0] data_proc, data_mem;
wire [15:0] mem_addr;
Processor mARC ( //marcee
data_mem, //data or instructions coming from the main memory
mem_addr, //Data comming from the bus A of the datapath
data_proc, //Data comming from the bus B of the datapath to the main mem
rw, //signal indicating whether the main memory is to be written or not
reset, //signal reseting the processor
clk //clock signal
);
Memory mem (
data_proc, //Data input coming from the bus b of the datapath
data_mem, //Data output, it is read when rw = 1, otherwise it is disconnected
mem_addr[7:0], //a 16-bit address coming from the bus a of the datapath
rw, //read/write mode operation of the memory
clk //the clock signal
);
always begin
#1 clk = ~clk;
end
initial begin
$dumpfile("marcee.vcd");
$dumpvars(0, Testbench);
clk = 0;
reset = 0;
#0.5;
reset = 1;
#3;
reset = 0;
#1.5;
//While the %ir doesn't store st %r3, %r1
while (mARC.datapath_unit.instruction != 16'b0_0111_011_001_0_0_000) #1.0;
#10 $finish;
end
endmodule
| 7.339781 |
module: Contol_RTC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_contro_RTC;
// Inputs
reg clk;
reg reset;
reg sw0;
reg sw1;
reg sw2;
reg enUP;
reg enDOWN;
reg enRIGHT;
reg enLEFT;
reg desactivar_alarma;
reg formato_hora;
// Outputs
wire a_d;
wire cs;
wire rd;
wire wr;
wire [7:0] out_seg_hora;
wire [7:0] out_min_hora;
wire [7:0] out_hora_hora;
wire [7:0] out_dia_fecha;
wire [7:0] out_mes_fecha;
wire [7:0] out_jahr_fecha;
wire [7:0] out_dia_semana;
wire [7:0] out_seg_timer;
wire [7:0] out_min_timer;
wire [7:0] out_hora_timer;
wire estado_alarma;
wire [1:0] cursor_location;
wire AM_PM;
// Bidirs
wire [7:0] dato;
// Instantiate the Unit Under Test (UUT)
Contol_RTC uut (
.clk(clk),
.reset(reset),
.sw0(sw0),
.sw1(sw1),
.sw2(sw2),
.enUP(enUP),
.enDOWN(enDOWN),
.enRIGHT(enRIGHT),
.enLEFT(enLEFT),
.desactivar_alarma(desactivar_alarma),
.formato_hora(formato_hora),
.dato(dato),
.a_d(a_d),
.cs(cs),
.rd(rd),
.wr(wr),
.out_seg_hora(out_seg_hora),
.out_min_hora(out_min_hora),
.out_hora_hora(out_hora_hora),
.out_dia_fecha(out_dia_fecha),
.out_mes_fecha(out_mes_fecha),
.out_jahr_fecha(out_jahr_fecha),
.out_dia_semana(out_dia_semana),
.out_seg_timer(out_seg_timer),
.out_min_timer(out_min_timer),
.out_hora_timer(out_hora_timer),
.estado_alarma(estado_alarma),
.cursor_location(cursor_location),
.AM_PM(AM_PM)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
sw0 = 0;
sw1 = 0;
sw2 = 0;
enUP = 0;
enDOWN = 0;
enRIGHT = 0;
enLEFT = 0;
desactivar_alarma = 0;
formato_hora = 0;
// Wait 100 ns for global reset to finish
#10 reset = 0;
//#40 dato = 8'd12;
#10000 sw2 = 01;
#5000 sw2 = 0;
#1000000 $stop;
// Add stimulus here
end
endmodule
| 8.101144 |
module testbench_first_instrs (
output reg completed
);
`include "../utils.h"
integer ii;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
tricpu #(
.P_LOGLEVEL(-1)
) cpu (
.clk(clk),
.rst(rst),
.stepping(1'b0),
.s_axis_tvalid(1'b0),
.m_axis_tready(1'b1)
);
initial begin
completed = 0;
rst = 1;
#160;
rst = 0;
while (!cpu.ram.e) #10;
// J 18'b000000000001111111
if (cpu.ram.write !== 0) $error("[first_instrs] 0.0 write");
if (cpu.ram.pt !== 2'b11) $error("[first_instrs] 0.0 pt");
if (cpu.ram.addr !== 18'h0) $error("[first_instrs] 0.0 addr");
#10;
while (!cpu.ram.e) #10;
if (cpu.ram.write !== 0) $error("[first_instrs] 0.1 write");
if (cpu.ram.pt !== 2'b11) $error("[first_instrs] 0.1 pt");
if (cpu.ram.addr !== 18'h1) $error("[first_instrs] 0.1 addr");
#10;
while (!cpu.ram.e) #10;
// MOV @1 18'b000101110101010011
if (cpu.ram.write !== 0) $error("[first_instrs] 1.0 write");
if (cpu.ram.pt !== 2'b11) $error("[first_instrs] 1.0 pt");
if (cpu.ram.addr !== 18'b000000000001111111) $error("[first_instrs] 1.0 addr");
#10;
while (!cpu.ram.e) #10;
if (cpu.ram.write !== 0) $error("[first_instrs] 1.1 write");
if (cpu.ram.pt !== 2'b11) $error("[first_instrs] 1.1 pt");
if (cpu.ram.addr !== 18'b000000000001111100) $error("[first_instrs] 1.1 addr");
#10;
while (!cpu.ram.e) #10;
if (cpu.regs[1] !== 18'b000101110101010011) $error("[first_instrs] 1.1 r1");
// MOV @2 18'b0000000000000000011
if (cpu.ram.write !== 0) $error("[first_instrs] 2.0 write");
if (cpu.ram.pt !== 2'b11) $error("[first_instrs] 2.0 pt");
if (cpu.ram.addr !== 18'b000000000001111101) $error("[first_instrs] 2.0 addr");
#10;
while (!cpu.ram.e) #10;
if (cpu.regs[1] !== 18'b000101110101010011) $error("[first_instrs] 2.0 r1");
if (cpu.ram.write !== 0) $error("[first_instrs] 2.1 write");
if (cpu.ram.pt !== 2'b11) $error("[first_instrs] 2.1 pt");
if (cpu.ram.addr !== 18'b000000000001110011) $error("[first_instrs] 2.1 addr");
#10;
while (!cpu.ram.e) #10;
if (cpu.regs[1] !== 18'b000101110101010011) $error("[first_instrs] 2.1 r1");
if (cpu.regs[2] !== 18'b000000000000000011) $error("[first_instrs] 2.1 r2");
// HVC 1 (hypercall_log)
if (cpu.ram.write !== 0) $error("[first_instrs] 3.0 write");
if (cpu.ram.pt !== 2'b11) $error("[first_instrs] 3.0 pt");
if (cpu.ram.addr !== 18'b000000000001110000) $error("[first_instrs] 3.0 addr");
while (!cpu.p_extcall_ctrl.i_enable) #10;
if (cpu.p_extcall_ctrl.i_type !== 1'b1 || cpu.p_extcall_ctrl.i_code !== 6'b000001)
$error("[first_instrs] 3.0 extcall");
while (!cpu.ram.e) #10;
// reads first character of string
if (cpu.ram.write !== 0) $error("[first_instrs] 3.1 write", ii);
if (cpu.ram.pt !== 2'b01) $error("[first_instrs] 3.1 pt", ii);
if (cpu.ram.addr !== 18'b000101110101010011) $error("[first_instrs] 3.1 addr", ii);
completed = 1;
$display("[first_instrs] Test completed.");
end
endmodule
| 6.516488 |
module testbench_cpu_calls_hypercall_log (
output reg completed
);
`include "../utils.h"
integer ii;
integer msg[0:32] = "";
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
wire [31:0] m_axis_tdata;
wire m_axis_tlast;
reg m_axis_tready;
wire m_axis_tvalid;
tricpu #(
.P_LOGLEVEL(-1)
) cpu (
.clk(clk),
.rst(rst),
.stepping(1'b0),
.s_axis_tvalid(1'b0),
.m_axis_tdata (m_axis_tdata),
.m_axis_tlast (m_axis_tlast),
.m_axis_tready(m_axis_tready),
.m_axis_tvalid(m_axis_tvalid)
);
initial begin
completed = 0;
m_axis_tready = 1;
rst = 1;
#160;
rst = 0;
msg[0] = "I";
msg[1] = "n";
msg[2] = "i";
msg[3] = "t";
msg[4] = "i";
msg[5] = "a";
msg[6] = "l";
msg[7] = "i";
msg[8] = "z";
msg[9] = "i";
msg[10] = "n";
msg[11] = "g";
msg[12] = " ";
msg[13] = "o";
msg[14] = "p";
msg[15] = "e";
msg[16] = "r";
msg[17] = "a";
msg[18] = "t";
msg[19] = "i";
msg[20] = "n";
msg[21] = "g";
msg[22] = " ";
msg[23] = "s";
msg[24] = "y";
msg[25] = "s";
msg[26] = "t";
msg[27] = "e";
msg[28] = "m";
msg[29] = ".";
msg[30] = ".";
msg[31] = ".";
msg[32] = 0;
while (!m_axis_tvalid) #10;
if (m_axis_tlast !== 1 || m_axis_tdata !== {25'h0, 7'b1000001})
$error("[cpu_calls_hypercall_log] header");
#10;
while (!m_axis_tvalid) #10;
if (m_axis_tlast !== 1 || m_axis_tdata !== {14'h0, 18'b11})
$error("[cpu_calls_hypercall_log] level");
for (ii = 0; ii <= 32; ii = ii + 1) begin
#10;
while (!m_axis_tvalid) #10;
if (m_axis_tlast !== 1 || m_axis_tdata !== {14'h0, util_int_to_tryte(msg[ii])})
$error("[cpu_calls_hypercall_log] msg %d", ii);
end
while (!cpu.p_extcall_ctrl.o_ready) #10;
if (cpu.p_extcall_ctrl.o_pagefault !== 0 || cpu.p_extcall_ctrl.o_exit !== 0)
$error("[cpu_calls_hypercall_log] extres %d", ii);
completed = 1;
$display("[cpu_calls_hypercall_log] Test completed.");
end
endmodule
| 7.776549 |
module testbench_inf_loop (
output reg completed
);
`include "../utils.h"
integer ii;
reg clk;
initial clk = 0;
always #5 if (!completed) clk = ~clk;
reg rst;
tricpu #(
.BIN_FILENAME("zzz_test_inf_loop.bin")
) cpu (
.clk(clk),
.rst(rst),
.stepping(1'b0),
.s_axis_tvalid(1'b0),
.m_axis_tready(1'b1)
);
initial begin
completed = 0;
rst = 1;
#160;
rst = 0;
while (!cpu.ram.e) #10;
for (ii = 0; ii < 27; ii = ii + 1) begin
// J 18'b000000000000000000
if (cpu.ram.write !== 0) $error("[inf_loop] %d.0 write", ii);
if (cpu.ram.pt !== 2'b11) $error("[inf_loop] %d.0 pt", ii);
if (cpu.ram.addr !== 18'h0) $error("[inf_loop] %d.0 addr", ii);
#10;
while (!cpu.ram.e) #10;
if (cpu.ram.write !== 0) $error("[inf_loop] %d.1 write", ii);
if (cpu.ram.pt !== 2'b11) $error("[inf_loop] %d.1 pt", ii);
if (cpu.ram.addr !== 18'h1) $error("[inf_loop] %d.1 addr", ii);
#10;
while (!cpu.ram.e) #10;
end
completed = 1;
$display("[inf_loop] Test completed.");
end
endmodule
| 6.547391 |
module testbench_cpu (
output wire completed
);
wire [2:0] completion;
assign completed = &completion;
testbench_first_instrs p_first_instrs (completion[0]);
testbench_cpu_calls_hypercall_log p_cpu_calls_hypercall_log (completion[1]);
testbench_inf_loop p_inf_loop (completion[2]);
initial begin
#10;
while (!completed) #10;
$display("[cpu] Test group completed.");
end
endmodule
| 7.776549 |
module tb_crossbar;
logic [0:0] clk;
logic [0:0] reset;
logic [0:0] recv_data__en[0:5];
CGRAData_32_1_1 recv_data__msg[0:5];
logic [0:0] recv_data__rdy[0:5];
logic [0:0] recv_opt__en;
CGRAConfig_6_4_6_8 recv_opt__msg;
logic [0:0] recv_opt__rdy;
logic [0:0] send_data__en[0:7];
CGRAData_32_1_1 send_data__msg[0:7];
logic [0:0] send_data__rdy[0:7];
logic [0:0] send_predicate__en;
CGRAData_1_1 send_predicate__msg;
logic [0:0] send_predicate__rdy;
CrossbarRTL__20918f721d5f331c dut (
.clk(clk),
.reset(reset),
.recv_data__en(recv_data__en),
.recv_data__msg(recv_data__msg),
.recv_data__rdy(recv_data__rdy),
.recv_opt__en(recv_opt__en),
.recv_opt__msg(recv_opt__msg),
.recv_opt__rdy(recv_opt__rdy),
.send_data__en(send_data__en),
.send_data__msg(send_data__msg),
.send_data__rdy(send_data__rdy),
.send_predicate__en(send_predicate__en),
.send_predicate__msg(send_predicate__msg),
.send_predicate__rdy(send_predicate__rdy)
);
initial begin
reset <= 1;
#10;
reset <= 0;
#10;
reset <= 1;
recv_data__en = {1'd0, 1'd0, 1'd0, 1'd0, 1'd1, 1'd0};
recv_data__msg = {
{32'haaaaaaaa, 1'd1, 1'd1},
{32'hbbbbbbbb, 1'd1, 1'd1},
{32'hcccccccc, 1'd1, 1'd1},
{32'hdddddddd, 1'd1, 1'd1},
{32'heeeeeeee, 1'd1, 1'd1},
{32'hffffffff, 1'd1, 1'd1}
};
recv_opt__msg.ctrl = 6'h20;
recv_opt__msg.predicate = 1'd1;
recv_opt__msg.fu_in[0] = 3'd1;
recv_opt__msg.fu_in[1] = 3'd2;
recv_opt__msg.fu_in[2] = 3'd0;
recv_opt__msg.fu_in[3] = 3'd0;
recv_opt__msg.outport[0] = 3'd0;
recv_opt__msg.outport[1] = 3'd0;
recv_opt__msg.outport[2] = 3'd5;
recv_opt__msg.outport[3] = 3'd0;
recv_opt__msg.outport[4] = 3'd5;
recv_opt__msg.outport[5] = 3'd0;
recv_opt__msg.outport[6] = 3'd0;
recv_opt__msg.outport[7] = 3'd0;
recv_opt__msg.predicate_in = 6'd0;
recv_opt__en = 1'b1;
send_data__rdy = {1'd0, 1'd0, 1'd1, 1'd0, 1'd1, 1'd0, 1'd0, 1'd0};
send_predicate__rdy = 1'b1;
end
always begin
clk <= 1;
#5;
clk <= 0;
#5;
end
endmodule
| 6.866425 |
module testbench_CSA ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
CSA uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 0 && of == 0) begin
$display("Test case 1 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 1 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve with overflow
a = 32'h8fffffff;
b = 32'h8fffffff;
Cin = 0;
#100
if (sum == 32'h1ffffffe && Cout == 1 && of == 0) begin
$display("Test case 2 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 2 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + -ve
a = 32'h7AA;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'h000007a9 && Cout == 1 && of == 0) begin
$display("Test case 3 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 3 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + +ve without overflow
a = 32'hAF;
b = 32'hAF;
Cin = 1;
#100
if (sum == 32'h0000015f && Cout == 0 && of == 0) begin
$display("Test case 4 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 4 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve without overflow
a = 32'hffffffff;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 1 && of == 0) begin
$display("Test case 5 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 5 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case1
a = 32'h123;
b = 32'hfffff123;
Cin = 0;
#100
if (sum == 32'hfffff246 && Cout == 0 && of == 0) begin
$display("Test case 6 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 6 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case2
a = 32'hfffff999;
b = 32'h111;
Cin = 0;
#100
if (sum == 32'hfffffaaa && Cout == 0 && of == 0) begin
$display("Test case 7 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 7 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case3
a = 32'h0;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hffffffff && Cout == 0 && of == 0) begin
$display("Test case 8 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 8 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
end
endmodule
| 6.68794 |
module testbench_csa32 ();
reg [31:0] a;
reg [31:0] b;
reg Cin;
wire [31:0] sum;
wire Cout;
wire of;
csa32 uut (
a,
b,
Cin,
sum,
Cout,
of
);
initial begin
//+ve + +ve with over flow
a = 32'h7fffffff;
b = 32'h7fffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 0 && of == 0) begin
$display("Test case 1 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 1 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve with overflow
a = 32'h8fffffff;
b = 32'h8fffffff;
Cin = 0;
#100
if (sum == 32'h1ffffffe && Cout == 1 && of == 0) begin
$display("Test case 2 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 2 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + -ve
a = 32'h7AA;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'h000007a9 && Cout == 1 && of == 0) begin
$display("Test case 3 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 3 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//+ve + +ve without overflow
a = 32'hAF;
b = 32'hAF;
Cin = 1;
#100
if (sum == 32'h0000015f && Cout == 0 && of == 0) begin
$display("Test case 4 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 4 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//-ve + -ve without overflow
a = 32'hffffffff;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hfffffffe && Cout == 1 && of == 0) begin
$display("Test case 5 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 5 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case1
a = 32'h123;
b = 32'hfffff123;
Cin = 0;
#100
if (sum == 32'hfffff246 && Cout == 0 && of == 0) begin
$display("Test case 6 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 6 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case2
a = 32'hfffff999;
b = 32'h111;
Cin = 0;
#100
if (sum == 32'hfffffaaa && Cout == 0 && of == 0) begin
$display("Test case 7 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 7 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
//random case3
a = 32'h0;
b = 32'hffffffff;
Cin = 0;
#100
if (sum == 32'hffffffff && Cout == 0 && of == 0) begin
$display("Test case 8 PASSED SUCCESSFULY!\n");
end else begin
$display("Test case 8 FAILED\n");
$display("A = %d\tB = %d\tSum = %d\tCout =%b\tOverFlow = %b\n\n", $signed(a), $signed(b),
$signed(sum), Cout, of);
end
end
endmodule
| 6.605262 |
module TestBench_debouncer #(
parameter DEBOUNCE_TIMER = 3
) ();
reg clk, reset;
reg [3:0] RAW_BTN;
button_debouncer #(
.DEBOUNCE_TIMER(DEBOUNCE_TIMER)
) DUT (
.clk(clk),
.reset(reset),
.RAW_BTN(RAW_BTN)
);
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 0;
RAW_BTN = 0;
#10;
reset = 1;
#10;
reset = 0;
#20;
RAW_BTN = 'b0000;
//#10;
//RAW_BTN='b0000;
//#10;
//RAW_BTN='b0001;
//#10;
//RAW_BTN='b0000;
//#10;
//RAW_BTN='b0001;
//$stop;
end
endmodule
| 6.923197 |
module test_decoder;
reg [1:0] in;
wire [3:0] out;
decoder_dataflow U0 (
out,
in
);
// test할 module (decoder_dataflow, decoder_structural, decoder_behavioral)
initial begin
#100 // 딜레이
in = 2'b00; // 입력 00
#100 in = 2'b01; // 입력 01
#100 in = 2'b10; // 입력 10
#100 in = 2'b11; // 입력 11
#100 $finish; // 종료
end
endmodule
| 6.703022 |
module TestBench ();
reg [1:0] X;
wire [3:0] Y;
decoder_2_4 decoder_2_4_test (
Y,
X
);
initial begin
$dumpfile("TimingDiagram.vcd");
$dumpvars(0, Y, X);
X = 2'b00;
#20;
X = 2'b01;
#20;
X = 2'b10;
#20;
X = 2'b11;
#20;
X = 2'b11;
#20;
$finish;
end
endmodule
| 7.747207 |
module TestBench_decoder_4_bit;
wire [15:0] Y;
reg [ 4:0] D;
Decoder_4_bit D0 (
Y,
D[3:0]
);
initial begin
for (D = 5'b00000; D <= 5'b01111; D = D + 5'b00001) #100;
end
initial $monitor($time, "\t D=%b Y=%b", D[3:0], Y);
endmodule
| 7.299579 |
module testbench_dtrig ();
parameter CLK_PERIOD = 10;
reg clk;
reg rst;
reg [3:0] d;
wire [3:0] q;
// Ӳģ
dtrig dtrig_test (
.clk(clk),
.rst(rst),
.d (d),
.q (q)
);
// ʼʱӡλź
initial begin
clk <= 0;
rst <= 0;
#1000;
rst <= 1;
@(posedge clk);
#2;
d <= 4'd1;
@(posedge clk);
#2;
d <= 4'd2;
@(posedge clk);
#2;
d <= 4'd3;
@(posedge clk);
#2;
d <= 4'd4;
end
always #(CLK_PERIOD / 2) clk <= ~clk;
initial begin
@(posedge rst); // ȴһ initial ĸλ
@(posedge clk); // ڸλɵĻϵȴʱ
repeat (10) begin
@(posedge clk);
end
#10_000;
$stop;
end
endmodule
| 7.255235 |
module testbench_sumfour ();
parameter CLK_PERIORD = 10;
reg clk;
reg rst;
wire [3:0] o_cnt_1;
wire [3:0] o_cnt_2;
// ģ
sumfour sumfour_test (
.clk (clk),
.rst (rst),
.o_cnt_1(o_cnt_1),
.o_cnt_2(o_cnt_2)
);
// ʼʱ
initial begin
clk <= 0;
rst <= 0;
#1000;
rst <= 1;
end
always #(CLK_PERIORD / 2) clk = ~clk;
// ź
initial begin
@(posedge rst); // ȴλ
@(posedge clk); // ȴʱ
repeat (10) begin
@(posedge clk); // ظ 10 ʱжϣôҲDz 10 ηƵź
end
#10_000; // ʱΪ 10000 ʱ䵥λҲ 10000*1ns=10000ns
$stop;
end
endmodule
| 7.503826 |
module testbench_edge_detector ( /*AUTOARG*/);
//---------------------------------------------------------------------------
//
// Free Running Clock
//
//---------------------------------------------------------------------------
wire CLK;
free_running_clk CLK_50MHZ (.CLK(CLK));
//---------------------------------------------------------------------------
//
// System Reset
//
//---------------------------------------------------------------------------
reg RESET;
initial begin
RESET <= 1'b0;
repeat (2) @(posedge CLK);
#3 RESET <= 1'b1;
repeat (20) @(posedge CLK);
#2 RESET <= 1'b0;
end
//---------------------------------------------------------------------------
//
// DUT
//
//---------------------------------------------------------------------------
wire RISING_EDGE;
wire FALLING_EDGE;
reg SIGNAL;
reg ENABLE;
edged_detector dut (
// Outputs
.RISING_EDGE(RISING_EDGE),
.FALLING_EDGE(FALLING_EDGE),
// Inputs
.CLK(CLK),
.ENABLE(ENABLE),
.RESET(RESET),
.SIGNAL(SIGNAL)
);
//---------------------------------------------------------------------------
//
// TEST CASES
//
//---------------------------------------------------------------------------
initial begin
SIGNAL <= 1'b0;
ENABLE <= 1'b0;
#5 @(negedge RESET);
$display("RESET RELEASED @ %d", $time);
//
// TEST 1: Rising Edge detection
//
ENABLE <= 1'b1;
@(posedge CLK);
#2 SIGNAL <= 1'b1;
@(posedge RISING_EDGE);
if (!RISING_EDGE) begin
$display("RISING EDGE = 0x%h FAIL @ %d", RISING_EDGE, $time);
$finish;
end
repeat (10) @(posedge CLK);
//
// TEST 2: Falling Edge detection
//
@(posedge CLK);
#2 SIGNAL <= 1'b0;
@(posedge FALLING_EDGE);
if (!FALLING_EDGE) begin
$display("FALLING EDGE = 0x%h FAIL @ %d", FALLING_EDGE, $time);
$finish;
end
//
// TEST 3: Enable signal operation
//
ENABLE <= 1'b0;
@(posedge CLK);
#2 SIGNAL <= 1'b1;
@(posedge CLK);
@(posedge CLK);
if (RISING_EDGE) begin
$display("ENABLE RISING EDGE = 0x%h FAIL @ %d", RISING_EDGE, $time);
$finish;
end
repeat (10) @(posedge CLK);
@(posedge CLK);
#2 SIGNAL <= 1'b0;
@(posedge CLK);
@(posedge CLK);
if (FALLING_EDGE) begin
$display("ENABLE FALLING EDGE = 0x%h FAIL @ %d", FALLING_EDGE, $time);
$finish;
end
repeat (10) @(posedge CLK);
$display("SIM COMPLETE @ %d", $time);
$finish;
end
endmodule
| 6.866457 |
module enc_tb ();
reg [3:0] tb_A = 4'b0000;
reg [3:0] tb_B = 4'b0000;
reg tb_cin = 1'b0;
wire [3:0] tb_sum = 4'b0000;
wire tb_cout = 4'b0000;
reg [7:0] tb_E;
wire [2:0] tb_F;
reg clk;
initial clk = 0;
always #10 clk = ~clk;
reg [31:0] tb_mem[0:2];
lab6_2circuits enc_ins (
.A(tb_A),
.B(tb_B),
.cin(tb_cin),
.sum(tb_sum),
.cout(tb_cout),
.E(tb_E),
.F(tb_F),
.clock(clk)
);
initial begin
$readmemh("configure8_to_3encoder.mem", tb_mem);
enc_ins.inst1.mem[31:0] = tb_mem[0];
enc_ins.inst1.mem[32] = tb_mem[1];
enc_ins.inst2.mem[31:0] = tb_mem[0];
enc_ins.inst2.mem[32] = tb_mem[1];
enc_ins.inst3.mem[31:0] = tb_mem[0];
enc_ins.inst3.mem[32] = tb_mem[1];
tb_E = 8'b00010000;
#20 $display("8 to 3 encoder:: E= %b ,F= %b", tb_E, tb_F);
tb_E = 8'b00001000;
#20 $display("8 to 3 encoder:: E= %b ,F= %b", tb_E, tb_F);
tb_E = 8'b00000010;
#20 $display("8 to 3 encoder:: E= %b ,F= %b", tb_E, tb_F);
tb_E = 8'b00000001;
#20 $display("8 to 3 encoder:: E= %b ,F= %b", tb_E, tb_F);
end
initial #1000 $finish;
initial begin
$dumpfile("2019csb1100_enc.vcd");
$dumpvars;
end
endmodule
| 7.185917 |
module testbench_encender_lucesLED;
//Entradas
reg [3:0] bin = 0;
//Salidas
wire [3:0] led;
//Unidad Bajo Prueba (UUT)
encender_lucesLED uut (
.bin(bin),
.led(led)
);
//Variable para hacer las pruebas
reg [4:0] k = 0;
initial begin
bin = 0;
for (k = 0; k < 16; k = k + 1) #10 bin = k;
#10 $finish;
end
endmodule
| 6.783584 |
module testbench_exemplo ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping para analisar via gtkwave
initial begin
//arquivo de dump para o gtkwave. Deve ser sempre
//o nome do modulo de testbench seguido de .vcd
$dumpfile("testbench_exemplo.vcd");
$dumpvars;
end
//bloco utilizado para controlar o sinal de clock.
//crie outras sequencias de forma a testar o seu codigo
initial begin
clk = 1'b0;
for (i = 0; i < 20; i = i + 1) begin
#1 clk = clk ^ 1'b1;
end
#1 $finish; //finalizando a simulacao
end
//bloco utilizado para controlar o sinal do botao.
//crie outras sequencias de forma a testar o seu codigo
initial begin
bt = 1'b0; //comece zerado
//botao acionado no instante 1
#1 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 2
//botao acionado no instante 7
#5 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 8
end
//bloco utilizado para controlar o sinal de reset.
//crie outras sequencias de forma a testar o seu codigo
initial begin
rst = 1'b1;
#1 rst = 1'b0; //reset apos o primeiro ciclo
end
endmodule
| 7.476841 |
module testbench_exemplo1 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping para analisar via gtkwave
initial begin
//arquivo de dump para o gtkwave. Deve ser sempre
//o nome do modulo de testbench seguido de .vcd
$dumpfile("testbench_exemplo1.vcd");
$dumpvars;
end
//bloco utilizado para controlar o sinal de clock.
//crie outras sequencias de forma a testar o seu codigo
initial begin
clk = 1'b0;
for (i = 0; i < 20; i = i + 1) begin
#1 clk = clk ^ 1'b1;
end
#1 $finish; //finalizando a simulacao
end
//bloco utilizado para controlar o sinal do botao.
//crie outras sequencias de forma a testar o seu codigo
initial begin
bt = 1'b0; //comece zerado
//botao acionado no instante 2
#2 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 3
//botao acionado no instante 8
#5 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 9
end
//bloco utilizado para controlar o sinal de reset.
//crie outras sequencias de forma a testar o seu codigo
initial begin
rst = 1'b1;
#1 rst = 1'b0; //reset apos o primeiro ciclo
end
endmodule
| 7.476841 |
module testbench_exemplo2 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping para analisar via gtkwave
initial begin
//arquivo de dump para o gtkwave. Deve ser sempre
//o nome do modulo de testbench seguido de .vcd
$dumpfile("testbench_exemplo2.vcd");
$dumpvars;
end
//bloco utilizado para controlar o sinal de clock.
//crie outras sequencias de forma a testar o seu codigo
initial begin
clk = 1'b0;
for (i = 0; i < 20; i = i + 1) begin
#1 clk = clk ^ 1'b1;
end
#1 $finish; //finalizando a simulacao
end
//bloco utilizado para controlar o sinal do botao.
//crie outras sequencias de forma a testar o seu codigo
initial begin
bt = 1'b0; //comece zerado
//botao acionado no instante 2
#2 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 3
//botao acionado no instante 14
#11 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 15
end
//bloco utilizado para controlar o sinal de reset.
//crie outras sequencias de forma a testar o seu codigo
initial begin
rst = 1'b1;
#1 rst = 1'b0; //reset apos o primeiro ciclo
end
endmodule
| 7.476841 |
module testbench_exemplo3 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping para analisar via gtkwave
initial begin
//arquivo de dump para o gtkwave. Deve ser sempre
//o nome do modulo de testbench seguido de .vcd
$dumpfile("testbench_exemplo3.vcd");
$dumpvars;
end
//bloco utilizado para controlar o sinal de clock.
//crie outras sequencias de forma a testar o seu codigo
initial begin
clk = 1'b0;
for (i = 0; i < 30; i = i + 1) begin
#1 clk = clk ^ 1'b1;
end
#1 $finish; //finalizando a simulacao
end
//bloco utilizado para controlar o sinal do botao.
//crie outras sequencias de forma a testar o seu codigo
initial begin
bt = 1'b0; //comece zerado
//botao acionado no instante 1
#1 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 2
//botao acionado no instante 7
#5 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 8
end
//bloco utilizado para controlar o sinal de reset.
//crie outras sequencias de forma a testar o seu codigo
initial begin
rst = 1'b1;
#1 rst = 1'b0; //reset apos o primeiro ciclo
end
endmodule
| 7.476841 |
module testbench_exemplo4 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping para analisar via gtkwave
initial begin
//arquivo de dump para o gtkwave. Deve ser sempre
//o nome do modulo de testbench seguido de .vcd
$dumpfile("testbench_exemplo4.vcd");
$dumpvars;
end
//bloco utilizado para controlar o sinal de clock.
//crie outras sequencias de forma a testar o seu codigo
initial begin
clk = 1'b0;
for (i = 0; i < 30; i = i + 1) begin
#1 clk = clk ^ 1'b1;
end
#1 $finish; //finalizando a simulacao
end
//bloco utilizado para controlar o sinal do botao.
//crie outras sequencias de forma a testar o seu codigo
initial begin
bt = 1'b0; //comece zerado
#5 bt = 1'b1;
#1 bt = 1'b0;
#10 bt = 1'b1;
#1 bt = 1'b0;
end
//bloco utilizado para controlar o sinal de reset.
//crie outras sequencias de forma a testar o seu codigo
initial begin
rst = 1'b1;
#1 rst = 1'b0; //reset apos o primeiro ciclo
end
endmodule
| 7.476841 |
module testbench_exemplo5 ();
reg clk, bt, rst; //1 bit, sinais de entrada
wire [2:0] As; //estado do semaforo A
wire [2:0] Bs; //estado do semaforo B
integer i; //para as iteracoes do for
semaforo s (
.clk(clk),
.rst(rst),
.bt (bt),
.A (As),
.B (Bs)
);
//dumping para analisar via gtkwave
initial begin
//arquivo de dump para o gtkwave. Deve ser sempre
//o nome do modulo de testbench seguido de .vcd
$dumpfile("testbench_exemplo5.vcd");
$dumpvars;
end
//bloco utilizado para controlar o sinal de clock.
//crie outras sequencias de forma a testar o seu codigo
initial begin
clk = 1'b0;
for (i = 0; i < 100; i = i + 1) begin
#1 clk = clk ^ 1'b1;
end
#1 $finish; //finalizando a simulacao
end
//bloco utilizado para controlar o sinal do botao.
//crie outras sequencias de forma a testar o seu codigo
initial begin
bt = 1'b0; //comece zerado
//botao acionado no instante 1
#10 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 2
//botao acionado no instante 7
#16 bt = 1'b1;
#1 bt = 1'b0; //solto no instante 8
end
//bloco utilizado para controlar o sinal de reset.
//crie outras sequencias de forma a testar o seu codigo
initial begin
rst = 1'b1;
#1 rst = 1'b0; //reset apos o primeiro ciclo
end
endmodule
| 7.476841 |
module testbench_extcall (
output wire completed
);
wire [3:0] completion;
assign completed = &completion;
testbench_termcall_beep p_termcall_beep (completion[0]);
testbench_termcall_putc p_termcall_putc (completion[1]);
testbench_hypercall_exit p_hypercall_exit (completion[2]);
testbench_hypercall_log p_hypercall_log (completion[3]);
initial begin
#10;
while (!completed) #10;
$display("[extcall] Test group completed.");
end
endmodule
| 7.606883 |
module TB;
wire ss, cy;
reg aa, bb, cc;
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end
gate newGate (
.a (aa),
.b (bb),
.c (cc),
.s (ss),
.ca(cy)
);
initial begin
aa = 1'b0;
bb = 1'b0;
#5 aa = 1'b0;
bb = 1'b1;
#5 aa = 1'b1;
bb = 1'b0;
#5 aa = 1'b1;
bb = 1'b1;
#5 aa = 1'b0;
bb = 1'b0;
end
endmodule
| 6.522363 |
module testbench_fetcher #(
parameter DATA_WIDTH = 8,
parameter ARRAY_W = 4, //j
parameter ARRAY_L = 4
); //i
localparam ARRAY_SIZE = ARRAY_L * ARRAY_W;
reg [ DATA_WIDTH*ARRAY_W*ARRAY_L-1:0] parameters_test;
reg [DATA_WIDTH*ARRAY_W*ARRAY_L - 1:0] inputs_test;
wire [2*DATA_WIDTH*ARRAY_W*ARRAY_W-1:0] outputs_test;
reg clk, reset_n, param_load, start_comp;
wire ready;
sys_array_fetcher #(
.DATA_WIDTH(DATA_WIDTH),
.ARRAY_W(ARRAY_W),
.ARRAY_L(ARRAY_L)
) fetching_unit (
.clock(clk),
.reset_n(reset_n),
.load_params(param_load),
.start_comp(start_comp),
.input_data_b(parameters_test),
.input_data_a(inputs_test),
.ready(ready),
.out_data(outputs_test)
);
initial $dumpvars;
initial begin
clk = 0;
forever #10 clk = !clk;
end
integer ii;
initial begin
reset_n = 0;
param_load = 0;
start_comp = 0;
#80;
reset_n = 1;
#20;
for (ii = 0; ii < ARRAY_SIZE; ii = ii + 1) begin
parameters_test[DATA_WIDTH*ii+:DATA_WIDTH] = ii + 1;
inputs_test[DATA_WIDTH*ii+:DATA_WIDTH] = ii + 1;
end
param_load = 1;
#20;
param_load = 0;
#10;
start_comp = 1;
#20;
start_comp = 0;
#100;
end
endmodule
| 8.040859 |
module address_mux_tb #(
parameter WIDTH = 5
) ();
reg [WIDTH - 1 : 0] in0, in1;
reg sel;
wire [WIDTH - 1 : 0] out;
initial begin
in0 = {WIDTH{1'b0}};
in1 = {WIDTH{1'b0}};
sel = 0;
end
// DUT
address_mux adm0 (
.in0(in0),
.in1(in1),
.sel(sel),
.out(out)
);
initial begin
$dumpfile("adm.vcd");
$dumpvars(1, address_mux_tb);
#10 sel = 0;
in0 = 5'b11111;
in1 = 5'b10101;
#10 sel = 1;
in0 = 5'b00010;
in1 = 5'b00111;
#30 $finish;
end
endmodule
| 7.411159 |
module tss_tb;
reg CLK, BUS_CON, STROBE_DATA, STROBE_MODE, RESET;
wire [7:0] IN_VAL;
wire [7:0] BUS;
reg [7:0] OUT_VAL;
reg OUT_VALID;
test_just_2 T1 (
.clk(CLK),
.bus(BUS),
.bus_con(BUS_CON),
.strobe_data(STROBE_DATA),
.strobe_mode(STROBE_MODE),
.reset(RESET)
);
assign IN_VAL = BUS;
assign BUS = (OUT_VALID == 1'b1) ? OUT_VAL : 8'hZZ;
initial begin
CLK = 0;
forever #5 CLK = ~CLK;
end
initial begin
RESET = 0;
#10 RESET = 1;
//Take auto generated testbench
// The output generated from the Python File responsible for converting Raw Image into Pixel Data
$finish;
end
endmodule
| 6.649286 |
module test_for_P2RV ();
reg clk = 1;
reg resetn = 0;
/** clk */
always #5 clk = ~clk;
/** reset */
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
`ifdef MODELSIM
reg [1023:0] firmware_file, instr_file, data_file;
initial begin
// instr_file = "instr.hex";
// $readmemh(instr_file, multicore.picoCore_top.sim.sim_reg);
data_file = "firmware.hex";
$readmemh(data_file, genData.memory);
end
`endif
wire data_in_valid, data_out_valid;
wire [133:0] data_in, data_out;
iCore_top iCore (
.clk(clk),
.resetn(resetn),
// FAST packets from CPU (ARM A8) or Physical ports, the format is according to fast
// project (www.http://www.fastswitch.org/)
.dataIn_valid_i(data_in_valid),
.dataIn_i(data_in), // 2'b01 is head, 2'b00 is body, and 2'b10 is tail;
.dataOut_valid_o(data_out_valid),
.dataOut_o(data_out)
);
gen_data genData (
.clk(clk),
.resetn(resetn),
.data_in_valid(data_in_valid),
.data_in(data_in),
.data_out_valid(data_out_valid),
.data_out(data_out)
);
endmodule
| 6.964132 |
module tb;
// logic [0:0] clk;
// logic [1:0] count;
// logic [0:0] reset;
// logic [0:0] recv__en;
// CGRAData_32_1_1 recv__msg;
// logic [0:0] recv__rdy;
// logic [0:0] send__en;
// CGRAData_32_1_1 send__msg;
// logic [0:0] send__rdy;
// ChannelRTL__DataType_CGRAData_32_1_1__latency_1 dut (
// .clk(clk),
// .count(count),
// .reset(reset),
// .recv__en(recv__en),
// .recv__msg(recv__msg),
// .recv__rdy(recv__rdy),
// .send__en(send__en),
// .send__msg(send__msg),
// .send__rdy(send__rdy)
// );
// initial begin
// reset <= 1; #10;
// reset <= 0; #10;
// reset <= 1;
// recv__en = 1'd1;
// recv__msg = {32'hECEBECEB, 1'd1,1'd1};
// send__rdy = 1'd1;
// #10;
// recv__en = 1'd1;
// recv__msg = {32'hAAAAAAAA, 1'd1,1'd1};
// send__rdy = 1'd1;
// end
// always
// begin
// clk <= 1; #5;
// clk <= 0; #5;
// end
// endmodule
| 6.640745 |
module TestBench_FullRangeFFFF ();
reg CLK;
reg Reset;
reg [7:0] A;
reg [15:0] B;
wire [7:0] Q;
wire [7:0] R;
wire Done;
integer j;
reg [7:0] tempQ, tempR;
Top UUT (
.CLK(CLK),
.Reset(Reset),
.A(A),
.B(B),
.Q(Q),
.R(R),
.Done(Done)
);
always #10 CLK <= ~CLK;
reg [15:0] x;
initial begin
$display("Test at time = ", $time);
CLK <= 0;
for (j = 16'hffff; j >= 0; j = j - 1) begin
Reset <= 1;
x <= j;
A <= 8'hff;
B <= x;
#25 Reset <= 0;
#5000;
tempQ = B / A;
tempR = R % A;
$display("From UUT --- > Dividend = %h , Divisor = %h , Quotient = %h , Remainder = %h",
B, A, Q, R);
$display("From TestBench --- > Dividend = %h , Divisor = %h , Quotient = %h , Remainder = %h",
B, A, tempQ, tempR);
if (Q != tempQ) $display("ERROR : Q was not obtained correctly");
if (R != tempR) $display("ERROR : R was not obtained correctly");
end
$display("Test end at time = ", $time);
end
endmodule
| 6.602917 |
module TestBench_GL_Dec;
wire [7:0] D;
reg [3:0] I;
reg [1:0] E;
GL_decoder_3_bit D0 (
D,
I[2:0],
E[0]
);
initial begin
for (E = 2'b00; E <= 2'b01; E = E + 2'b01) for (I = 4'b0000; I <= 4'b0111; I = I + 4'b0001) #50;
end
initial $monitor($time, "\t I=%b D=%b E=%b", I, D, E);
endmodule
| 6.515183 |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (1000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
`ifdef DEBUGREGS
wire [31:0] dbg_reg_x0;
wire [31:0] dbg_reg_x1;
wire [31:0] dbg_reg_x2;
wire [31:0] dbg_reg_x3;
wire [31:0] dbg_reg_x4;
wire [31:0] dbg_reg_x5;
wire [31:0] dbg_reg_x6;
wire [31:0] dbg_reg_x7;
wire [31:0] dbg_reg_x8;
wire [31:0] dbg_reg_x9;
wire [31:0] dbg_reg_x10;
wire [31:0] dbg_reg_x11;
wire [31:0] dbg_reg_x12;
wire [31:0] dbg_reg_x13;
wire [31:0] dbg_reg_x14;
wire [31:0] dbg_reg_x15;
wire [31:0] dbg_reg_x16;
wire [31:0] dbg_reg_x17;
wire [31:0] dbg_reg_x18;
wire [31:0] dbg_reg_x19;
wire [31:0] dbg_reg_x20;
wire [31:0] dbg_reg_x21;
wire [31:0] dbg_reg_x22;
wire [31:0] dbg_reg_x23;
wire [31:0] dbg_reg_x24;
wire [31:0] dbg_reg_x25;
wire [31:0] dbg_reg_x26;
wire [31:0] dbg_reg_x27;
wire [31:0] dbg_reg_x28;
wire [31:0] dbg_reg_x29;
wire [31:0] dbg_reg_x30;
wire [31:0] dbg_reg_x31;
`endif
`WRAPPER top (
.clk(clk),
.resetn(resetn),
.trap(trap),
`ifdef DEBUGREGS
.dbg_reg_x0,
.dbg_reg_x1,
.dbg_reg_x2,
.dbg_reg_x3,
.dbg_reg_x4,
.dbg_reg_x5,
.dbg_reg_x6,
.dbg_reg_x7,
.dbg_reg_x8,
.dbg_reg_x9,
.dbg_reg_x10,
.dbg_reg_x11,
.dbg_reg_x12,
.dbg_reg_x13,
.dbg_reg_x14,
.dbg_reg_x15,
.dbg_reg_x16,
.dbg_reg_x17,
.dbg_reg_x18,
.dbg_reg_x19,
.dbg_reg_x20,
.dbg_reg_x21,
.dbg_reg_x22,
.dbg_reg_x23,
.dbg_reg_x24,
.dbg_reg_x25,
.dbg_reg_x26,
.dbg_reg_x27,
.dbg_reg_x28,
.dbg_reg_x29,
.dbg_reg_x30,
.dbg_reg_x31,
`endif
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule
| 6.640835 |
module TB;
wire ss, cc;
reg aa, bb;
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, TB);
end
gate newGate (
.a(aa),
.b(bb),
.s(ss),
.c(cc)
);
initial begin
aa = 1'b0;
bb = 1'b0;
#5 aa = 1'b0;
bb = 1'b1;
#5 aa = 1'b1;
bb = 1'b0;
#5 aa = 1'b1;
bb = 1'b1;
end
endmodule
| 6.522363 |
module testbench_int; //testbench y probador de DAT
reg [ 3:0] card_in = 0;
reg [31:0] buffer_in = 0;
wire [31:0] buffer_out;
wire [ 3:0] card_out;
reg clock, host_clk;
reg new_trans;
reg enable_write, enable_read, Clear_in, reset;
parameter n = 32;
parameter vector_width = 10; //reg_vector has inputs with information coming from registers
reg [vector_width - 1 : 0] reg_vector = 10'b1101111111;
reg fifo_ack_i = 0;
reg card_ack_i = 0;
wire fifo_full;
wire [31:0] Data_out;
reg fifo_empty = 0;
reg mode = 1;
reg [10:0] block_amount = 8;
reg direction = 1;
DAT data_module (
buffer_in, //list
buffer_out, //listo
card_in, //listo
card_out, //listo
clock,
fifo_ack_i,
fifo_ack_o,
fifo_enable_o,
card_ack_i,
card_ack_o,
fifo_full,
fifo_empty,
block_amount,
fifo_ready,
new_trans,
reset,
mode,
direction
);
asynchronous_fifo FIFO
//Reading port
(
Data_out,
Empty_out, //almost empty signal
fifo_enable_o,
host_clk,
//Writing port.
buffer_out,
fifo_full, //almost full signal
fifo_enable_o,
clock,
fifo_ack_in, // FIXME falta definir esta bandera
fifo_ready
);
initial begin
Clear_in = 1;
enable_write = 1;
enable_read = 1;
reset = 0;
host_clk = 0;
clock = 0;
#2 new_trans = 1;
#4 card_in = 4'hF;
#5 card_in = 4'hC;
#4 card_in = 4'h1;
#4 card_in = 4'h0;
#6 card_in = 4'hB;
#3 card_in = 4'h0;
#4 card_in = 4'b1011;
#5 card_in = 4'b0000;
#3 card_in = 4'b1110;
#5 card_in = 4'b0111;
#6 card_in = 4'b1101;
#5 card_in = 4'b0000;
#4 card_in = 4'hF;
#5 card_in = 4'hC;
#4 card_in = 4'h1;
#4 card_in = 4'h0;
#6 card_in = 4'hB;
#3 card_in = 4'h0;
#4 card_in = 4'b1011;
#5 card_in = 4'b0000;
#3 card_in = 4'b1110;
#5 card_in = 4'b0111;
#6 card_in = 4'b1101;
#5 card_in = 4'b0000;
#5 mode = 0;
#4 card_in = 4'hF;
#5 card_in = 4'hC;
#4 card_in = 4'h1;
#4 card_in = 4'h0;
#6 card_in = 4'hB;
#3 card_in = 4'h0;
#4 card_in = 4'b1011;
#5 card_in = 4'b0000;
#3 card_in = 4'b1110;
#5 card_in = 4'b0111;
#6 card_in = 4'b1101;
#5 card_in = 4'b0000;
#5 enable_read = 0;
#30 enable_read = 1;
#400 $finish;
end
initial begin
$dumpfile("testbench_int.vcd");
$dumpvars(0, testbench_int);
end
always #2 clock = !clock;
always #6 host_clk = !host_clk;
endmodule
| 6.68599 |
module: logica_para_Escribir_Leer_Mux
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_IO_datos;
// Inputs
reg clk;
reg reset;
reg in_flag_dato;
reg in_direccion_dato;
reg [7:0] in_dato_inicio;
reg in_flag_inicio;
reg in_wr;
reg [7:0] in_dato;
reg [7:0] addr_RAM;
reg controlador_dato;
// Outputs
wire [7:0] out_reg_dato;
// Bidirs
wire [7:0] dato;
// Instantiate the Unit Under Test (UUT)
logica_para_Escribir_Leer_Mux uut (
.clk(clk),
.reset(reset),
.in_flag_dato(in_flag_dato),
.in_direccion_dato(in_direccion_dato),
.in_dato_inicio(in_dato_inicio),
.in_flag_inicio(in_flag_inicio),
.in_wr(in_wr),
.in_dato(in_dato),
.out_reg_dato(out_reg_dato),
.addr_RAM(addr_RAM),
.dato(dato),
.controlador_dato(controlador_dato)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
in_flag_dato = 0;
in_direccion_dato = 0;
in_dato_inicio = 0;
in_flag_inicio = 0;
in_wr = 0;
in_dato = 0;
addr_RAM = 0;
controlador_dato = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.901575 |
module testbench_lectura_codigoGray;
//Entradas
reg [3:0] a = 0;
//Salidas
wire [3:0] bin;
//Unidad Bajo Prueba (UUT)
lectura_codigoGray uut (
.a (a),
.bin(bin)
);
//Variable para hacer las pruebas
reg [4:0] k = 0;
initial begin
a = 0;
for (k = 0; k < 16; k = k + 1) #10 a = k;
#10 $finish;
end
endmodule
| 6.506838 |
module: logica_generador_pulsos_RTC
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testbench_logica_generador_pulsos_rtc;
// Inputs
reg clk;
reg rst;
reg [1:0] funcion;
reg [7:0] cuenta;
// Outputs
wire a_d_out;
wire cs_out;
wire wr_out;
wire rd_out;
wire [3:0] addr_logica_escribir_leer_out;
wire [7:0] addr_RAM_out;
wire funcion_r_w_out;
// Instantiate the Unit Under Test (UUT)
logica_generador_pulsos_RTC uut (
.clk(clk),
.rst(rst),
.funcion(funcion),
.cuenta(cuenta),
.a_d_out(a_d_out),
.cs_out(cs_out),
.wr_out(wr_out),
.rd_out(rd_out),
.addr_logica_escribir_leer_out(addr_logica_escribir_leer_out),
.addr_RAM_out(addr_RAM_out),
.funcion_r_w_out(funcion_r_w_out)
);
always #10 clk = ~clk;
always@(negedge clk) begin
if (cuenta == 255 || rst) begin
cuenta = 0;
$finish;
end
else cuenta = cuenta + 1;
end
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
funcion = 0;
cuenta = 0;
// Wait 100 ns for global reset to finish
#10;
rst=1;
#10;
rst=0;
funcion = 2'b00;
// Add stimulus here
end
endmodule
| 6.693355 |
module Testbench_logic ();
reg [31:0] tb_mem[0:2];
reg [ 3:0] sbin;
reg rin1, rin2, rin3, rin4, rin5, clk;
wire wout;
wire [3:0] sbout;
initial clk = 0;
always #10 clk = ~clk;
logic_tile inst_logic_tile (
.in1 (rin1),
.in2 (rin2),
.in3 (rin3),
.in4 (rin4),
.in5 (rin5),
.out (wout),
.clock(clk)
);
switch_box_4x4 switch_box_inst (
.out(sbout),
.in (sbin)
);
initial begin
$readmemh("a.bin", tb_mem);
inst_logic_tile.mem[31:0] = tb_mem[0];
inst_logic_tile.mem[32] = tb_mem[1][0];
switch_box_inst.configure[15:0] = tb_mem[2][15:0];
end
initial begin
rin1 = 1'b0;
rin2 = 1'b0;
rin3 = 1'b0;
rin4 = 1'b0;
rin5 = 1'b0;
sbin = 4'b0000;
#15
$display(
"logic tile : in1 = %b, in2 = %b, in3 = %b, in4 = %b, in5 = %b, out = %b, switch box : in = %b, out = %b",
rin1,
rin2,
rin3,
rin4,
rin5,
wout,
sbin,
sbout
);
rin1 = 1'b1;
rin2 = 1'b1;
rin3 = 1'b1;
rin4 = 1'b1;
rin5 = 1'b1;
sbin = 4'b0001;
#15
$display(
"logic tile : in1 = %b, in2 = %b, in3 = %b, in4 = %b, in5 = %b, out = %b, switch box : in = %b, out = %b",
rin1,
rin2,
rin3,
rin4,
rin5,
wout,
sbin,
sbout
);
rin1 = 1'b1;
rin2 = 1'b1;
rin3 = 1'b0;
rin4 = 1'b0;
rin5 = 1'b0;
sbin = 4'b1111;
#15
$display(
"logic tile : in1 = %b, in2 = %b, in3 = %b, in4 = %b, in5 = %b, out = %b, switch box : in = %b, out = %b",
rin1,
rin2,
rin3,
rin4,
rin5,
wout,
sbin,
sbout
);
rin1 = 1'b0;
rin2 = 1'b1;
rin3 = 1'b0;
rin4 = 1'b0;
rin5 = 1'b1;
sbin = 4'b0101;
#15
$display(
"logic tile : in1 = %b, in2 = %b, in3 = %b, in4 = %b, in5 = %b, out = %b, switch box : in = %b, out = %b",
rin1,
rin2,
rin3,
rin4,
rin5,
wout,
sbin,
sbout
);
end
initial begin
#100 $finish;
end
initial begin
$dumpfile("lab4.vcd");
$dumpvars;
end
endmodule
| 8.338779 |
module testbench;
//outputs
wire [15:0] busA, busB;
wire rw;
//inputs
reg [15:0] dataIn;
reg reset, clk;
Processor mARC ( //marcee
dataIn, //data or instructions comming from the main memory
busA, //Data comming from the bus A of the datapath
busB, //Data comming from the bus B of the datapath
rw, //signal indicating whether the main memory is to be written or not
reset, //signal reseting the processor
clk //clock signal
);
always begin
#1 clk = ~clk;
end
initial begin
$dumpfile("max.vcd");
$dumpvars(0, testbench);
clk = 0;
reset = 0;
dataIn = 16'b1_000001000000000; //call 1024 to initialize the PC register
#0.5;
reset = 1;
#1;
reset = 0;
#9.5;
dataIn = 16'b0101000101000000; //setlow 64, %r1
#10;
dataIn = 16'b0101101000000001; //sethi 1, %r2
#10;
dataIn = 16'b1111100000000010; //call 0xF004 (61444)
#10;
dataIn = 16'b0010100000101010; //subcc %r1, %r2, %r0
#10;
dataIn = 16'b0100110100000110; //ble 3 !%pc <-- %pc + 6
#10;
if (busA == 16'hF008) begin
dataIn = 16'b0000101100100000; //mov %r1, %r3
#10;
dataIn = 16'b0100100100000100; //ba 2 !%pc <-- %pc + 4
#10;
end else begin
dataIn = 16'b0000101101000000; //mov %r2, %r3
#10;
end
dataIn = 16'b0100100000000111; //jmp %r7
#10;
dataIn = 16'b0101111000001000; //sethi 8, %r6 !%r6 <-- 2048
#10;
dataIn = 16'b0011101111000000; //st %r3, %r6
#10 $finish;
end
endmodule
| 7.015571 |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (10000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
picorv32_wrapper #(
.AXI_TEST(AXI_TEST),
.VERBOSE (VERBOSE)
) top (
.clk(clk),
.resetn(resetn),
.trap(trap),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule
| 6.640835 |
module picorv32_wrapper #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
) (
input clk,
input resetn,
output trap,
output trace_valid,
output [35:0] trace_data
);
wire tests_passed;
reg [31:0] irq = 0;
reg [15:0] count_cycle = 0;
always @(posedge clk) count_cycle <= resetn ? count_cycle + 1 : 0;
always @* begin
irq = 0;
irq[4] = &count_cycle[12:0];
irq[5] = &count_cycle[15:0];
end
wire mem_axi_awvalid;
wire mem_axi_awready;
wire [31:0] mem_axi_awaddr;
wire [ 2:0] mem_axi_awprot;
wire mem_axi_wvalid;
wire mem_axi_wready;
wire [31:0] mem_axi_wdata;
wire [ 3:0] mem_axi_wstrb;
wire mem_axi_bvalid;
wire mem_axi_bready;
wire mem_axi_arvalid;
wire mem_axi_arready;
wire [31:0] mem_axi_araddr;
wire [ 2:0] mem_axi_arprot;
wire mem_axi_rvalid;
wire mem_axi_rready;
wire [31:0] mem_axi_rdata;
axi4_mem_periph #(
.AXI_TEST(AXI_TEST),
.VERBOSE (VERBOSE)
) mem (
.clk (clk),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr),
.mem_axi_awprot (mem_axi_awprot),
.mem_axi_wvalid(mem_axi_wvalid),
.mem_axi_wready(mem_axi_wready),
.mem_axi_wdata (mem_axi_wdata),
.mem_axi_wstrb (mem_axi_wstrb),
.mem_axi_bvalid(mem_axi_bvalid),
.mem_axi_bready(mem_axi_bready),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr),
.mem_axi_arprot (mem_axi_arprot),
.mem_axi_rvalid(mem_axi_rvalid),
.mem_axi_rready(mem_axi_rready),
.mem_axi_rdata (mem_axi_rdata),
.tests_passed(tests_passed)
);
picorv32_axi #(
`ifndef SYNTH_TEST
`ifdef SP_TEST
.ENABLE_REGS_DUALPORT(0),
`endif
`ifdef COMPRESSED_ISA
.COMPRESSED_ISA(1),
`endif
.ENABLE_MUL(1),
.ENABLE_DIV(1),
.ENABLE_IRQ(1),
.ENABLE_TRACE(1)
`endif
) uut (
.clk (clk),
.resetn (resetn),
.trap (trap),
.mem_axi_awvalid(mem_axi_awvalid),
.mem_axi_awready(mem_axi_awready),
.mem_axi_awaddr (mem_axi_awaddr),
.mem_axi_awprot (mem_axi_awprot),
.mem_axi_wvalid (mem_axi_wvalid),
.mem_axi_wready (mem_axi_wready),
.mem_axi_wdata (mem_axi_wdata),
.mem_axi_wstrb (mem_axi_wstrb),
.mem_axi_bvalid (mem_axi_bvalid),
.mem_axi_bready (mem_axi_bready),
.mem_axi_arvalid(mem_axi_arvalid),
.mem_axi_arready(mem_axi_arready),
.mem_axi_araddr (mem_axi_araddr),
.mem_axi_arprot (mem_axi_arprot),
.mem_axi_rvalid (mem_axi_rvalid),
.mem_axi_rready (mem_axi_rready),
.mem_axi_rdata (mem_axi_rdata),
.irq (irq),
.trace_valid (trace_valid),
.trace_data (trace_data)
);
reg [1023:0] firmware_file;
initial begin
if (!$value$plusargs("firmware=%s", firmware_file)) firmware_file = "firmware/firmware.hex";
$readmemh(firmware_file, mem.memory);
end
integer cycle_counter;
always @(posedge clk) begin
cycle_counter <= resetn ? cycle_counter + 1 : 0;
if (resetn && trap) begin
`ifndef VERILATOR
repeat (10) @(posedge clk);
`endif
$display("TRAP after %1d clock cycles", cycle_counter);
if (tests_passed) begin
$display("ALL TESTS PASSED.");
$finish;
end else begin
$display("ERROR!");
if ($test$plusargs("noerror")) $finish;
$stop;
end
end
end
endmodule
| 6.647596 |
module testbench #(
parameter AXI_TEST = 0,
parameter VERBOSE = 0
);
reg clk = 1;
reg resetn = 0;
wire trap;
always #5 clk = ~clk;
initial begin
repeat (100) @(posedge clk);
resetn <= 1;
end
initial begin
if ($test$plusargs("vcd")) begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
repeat (10000000000) @(posedge clk);
$display("TIMEOUT");
$finish;
end
wire trace_valid;
wire [35:0] trace_data;
integer trace_file;
initial begin
if ($test$plusargs("trace")) begin
trace_file = $fopen("testbench.trace", "w");
repeat (10) @(posedge clk);
while (!trap) begin
@(posedge clk);
if (trace_valid) $fwrite(trace_file, "%x\n", trace_data);
end
$fclose(trace_file);
$display("Finished writing testbench.trace.");
end
end
picorv32_wrapper #(
.AXI_TEST(AXI_TEST),
.VERBOSE (VERBOSE)
) top (
.clk(clk),
.resetn(resetn),
.trap(trap),
.trace_valid(trace_valid),
.trace_data(trace_data)
);
endmodule
| 6.640835 |
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