code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_logical_operator (
clk,
G1,
G2
);
input G1, G2;
output G3;
assign G3 = G1 && G2;
endmodule
| 6.608267 |
module TOP;
//ALU inputs
reg [31:0] a;
wire [31:0] out;
//wire [31:0] flags;
wire carry_out;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 32'hffff_ffff;
#`cycle //1
if(out != (a + 1))
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 32'ha47ba47b;
#`cycle //3
if(out != (a + 1))
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 32'hbcdabcda;
#`cycle //5
if(out != (a + 1))
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 32'h96579657;
#`cycle //7
if(out != (a + 1))
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("inc_by_1.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(*)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, recieved out = %x, correct out = %x",
$time, a, out, (a + 1));
else
$strobe ("correct: time: %0d: a = %x, out = %x",
$time, a, out);
inc_by_1 u_inc_by_1 (out, carry_out, a);
endmodule
| 7.259416 |
module mux_test_inlab(
// input [9:0] SW,
// input CLOCK_50,
// input [3:0] KEY,
// output [9:0] LEDR,
// output VGA_CLK, // VGA Clock
// output VGA_HS, // VGA H_SYNC
// output VGA_VS, // VGA V_SYNC
// output VGA_BLANK_N, // VGA BLANK
// output VGA_SYNC_N, // VGA SYNC
// output [9:0] VGA_R, // VGA Red[9:0]
// output [9:0] VGA_G, // VGA Green[9:0]
// output [9:0] VGA_B // VGA Blue[9:0]
// );
// wire reset_n;
// assign reset_n = KEY[0];
// vga_adapter VGA(
// .resetn(reset_n),
// .clock(CLOCK_50),
// .colour(color),
// .x(x),
// .y(y),
// .plot(writeEn),
// .VGA_R(VGA_R),
// .VGA_G(VGA_G),
// .VGA_B(VGA_B),
// .VGA_HS(VGA_HS),
// .VGA_VS(VGA_VS),
// .VGA_BLANK(VGA_BLANK_N),
// .VGA_SYNC(VGA_SYNC_N),
// .VGA_CLK(VGA_CLK));
// defparam VGA.RESOLUTION = "160x120";
// defparam VGA.MONOCHROME = "FALSE";
// defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
// defparam VGA.BACKGROUND_IMAGE = "black.mif";
// wire [2:0] color;
// wire [7:0] x;
// wire [6:0] y;
// wire writeEn;
// mux_ui_ff c1(SW[0],reset_n, CLOCK_50, SW[1], color, x, y, LEDR[0], writeEn, LEDR[9:7]);
// endmodule
| 7.765303 |
module mux_ui_ff ( // clear_instruction need to be set with high change_instruction;
// reset to change instruction, no reset for clear
input change_instruction,
input reset_n,
input clk,
input clear_instruction,
output [2:0] color,
output [7:0] x,
output [6:0] y,
output done_signal,
output writeEn,
output [2:0] instruction
);
wire [3:0] control_instructions;
wire reset_instructions, done;
wire [2:0] current_instruction;
instruction_shift i1 (
change_instruction,
clk,
reset_n,
current_instruction
);
assign instruction = current_instruction;
mux_instructions i2 (
change_instruction,
control_instructions,
clk,
reset_instructions,
done,
writeEn,
x,
y
);
assign done_signal = done;
mux_control i3 (
clear_instruction,
change_instruction,
current_instruction,
reset_n,
done,
clk,
reset_instructions,
control_instructions,
color
);
endmodule
| 7.567331 |
module mux_instructions (
input enable,
input [3:0] instruction, // input instruction with 4 bit, [3] clear when 1
// [2:0] instruction
input clk,
input reset_n,
output reg done,
output reg writeEn,
output reg [7:0] x,
output reg [6:0] y
);
reg en_u1, en_u2, en_u3, en_u4, en_u5, en_u6;
reg reset_1, reset_2, reset_3, reset_4, reset_5, reset_6;
wire done1, done2, done3, done4, done5, done6;
wire writeEn1, writeEn2, writeEn3, writeEn4, writeEn5, writeEn6;
reg [3:0] CURRRENT_INSTRUCTION;
localparam UP = 3'b000,
DOWN = 3'b001,
RIGHT = 3'b010,
LEFT = 3'b011,
R = 3'b100,
L = 3'b101,
NULL = 3'b110;
wire [7:0] x1, x2, x3, x4, x5, x6;
wire [6:0] y1, y2, y3, y4, y5, y6;
always @(*) begin : FFFF
en_u1 = 0;
reset_1 = 0;
en_u2 = 0;
reset_2 = 0;
en_u3 = 0;
reset_3 = 0;
en_u4 = 0;
reset_4 = 0;
en_u5 = 0;
reset_5 = 0;
en_u6 = 0;
reset_6 = 0;
case (CURRRENT_INSTRUCTION[2:0])
UP: begin
en_u1 = 1;
x = x1;
y = y1;
done = done1;
writeEn = writeEn1;
reset_1 = 1;
end
DOWN: begin
en_u2 = 1;
x = x2;
y = y2;
done = done2;
writeEn = writeEn2;
reset_2 = 1;
end
RIGHT: begin
en_u3 = 1;
x = x3;
y = y3;
done = done3;
writeEn = writeEn3;
reset_3 = 1;
end
LEFT: begin
en_u4 = 1;
x = x4;
y = y4;
done = done4;
writeEn = writeEn4;
reset_4 = 1;
end
R: begin
en_u5 = 1;
x = x5;
y = y5;
done = done5;
writeEn = writeEn5;
reset_5 = 1;
end
L: begin
en_u6 = 1;
x = x6;
y = y6;
done = done6;
writeEn = writeEn6;
reset_6 = 1;
end
endcase
end
ui_UP u1 (
clk,
reset_1,
en_u1,
x1,
y1,
done1,
writeEn1
);
ui_DOWN u2 (
clk,
reset_2,
en_u2,
x2,
y2,
done2,
writeEn2
);
ui_RIGHT u3 (
clk,
reset_3,
en_u3,
x3,
y3,
done3,
writeEn3
);
ui_LEFT u4 (
clk,
reset_4,
en_u4,
x4,
y4,
done4,
writeEn4
);
ui_R u5 (
clk,
reset_5,
en_u5,
x5,
y5,
done5,
writeEn5
);
ui_L u6 (
clk,
reset_6,
en_u6,
x6,
y6,
done6,
writeEn6
);
always @(posedge clk) begin
if (!reset_n) begin
CURRRENT_INSTRUCTION[2:0] <= NULL;
end else if (enable) begin
CURRRENT_INSTRUCTION <= instruction; // update instruction if enabled
end
end
endmodule
| 7.710431 |
module mux_control (
input clear,
input enable, // corresponding to change_instruction flag, flip
input [2:0] instruction,
input reset_n,
input done,
input clk,
output reg reset_instructions,
output reg [3:0] control_instructions,
output reg [2:0] color
);
reg [5:0] CURRENT_STATE;
localparam UP = 6'b000000,
UP_WAIT = 6'b000001,
DOWN = 6'b000100,
DOWN_WAIT = 6'b000101,
LEFT = 6'b001000,
LEFT_WAIT = 6'b001001,
RIGHT = 6'b001100 ,
RIGHT_WAIT = 6'b001101,
L = 6'b010000 ,
L_WAIT = 6'b010001,
R = 6'b010100 ,
R_WAIT = 6'b010101,
ON_HOLD = 6'b011000,
PREPARE_INSTRUCTION = 6'b011001,
ON_HOLD_WAIT = 6'b011101;
reg [5:0] NEXT_STATE;
always @(*) begin : proc_
case (CURRENT_STATE)
ON_HOLD : NEXT_STATE = ON_HOLD_WAIT;
ON_HOLD_WAIT : NEXT_STATE = (enable) ? PREPARE_INSTRUCTION: ON_HOLD_WAIT;
PREPARE_INSTRUCTION :
if (!enable)
begin
case (instruction)
3'b000: NEXT_STATE = UP; // UP
3'b001: NEXT_STATE = DOWN; // DOWN
3'b010: NEXT_STATE = LEFT; // LEFT
3'b011: NEXT_STATE = RIGHT; // RIGHT
3'b100: NEXT_STATE = L; // L
3'b101: NEXT_STATE = R; // R
endcase
end
else
begin
NEXT_STATE = PREPARE_INSTRUCTION;
end
UP: NEXT_STATE = done ? UP_WAIT : UP;
UP_WAIT: NEXT_STATE = done ? UP_WAIT : ON_HOLD_WAIT;
DOWN: NEXT_STATE = done ? DOWN_WAIT : DOWN;
DOWN_WAIT: NEXT_STATE = done ? DOWN_WAIT : ON_HOLD_WAIT;
RIGHT: NEXT_STATE = done ? RIGHT_WAIT : RIGHT;
RIGHT_WAIT: NEXT_STATE = done ? RIGHT_WAIT : ON_HOLD_WAIT;
LEFT: NEXT_STATE = done ? LEFT_WAIT : LEFT;
LEFT_WAIT: NEXT_STATE = done ? LEFT_WAIT : ON_HOLD_WAIT;
L: NEXT_STATE = done ? L_WAIT : L;
L_WAIT: NEXT_STATE = done ? L_WAIT : ON_HOLD_WAIT;
R: NEXT_STATE = done ? R_WAIT : R;
R_WAIT: NEXT_STATE = done ? R_WAIT : ON_HOLD_WAIT;
default: /* default */;
endcase
end
always @(*) begin : FSM_ASS
reset_instructions <= 1'b1;
case (CURRENT_STATE)
ON_HOLD: begin
reset_instructions <= 0;
color <= 3'b000;
end
UP: begin
control_instructions <= 4'b0000;
color <= (clear) ? 3'b000 : 3'b001;
end
DOWN: begin
control_instructions <= 4'b0001;
color <= (clear) ? 3'b000 : 3'b010;
end
RIGHT: begin
control_instructions <= 4'b0010;
color <= (clear) ? 3'b000 : 3'b011;
end
LEFT: begin
control_instructions <= 4'b0011;
color <= (clear) ? 3'b000 : 3'b100;
end
R: begin
control_instructions <= 4'b0100;
color <= (clear) ? 3'b000 : 3'b101;
end
L: begin
control_instructions <= 4'b0101;
color <= (clear) ? 3'b000 : 3'b110;
end
ON_HOLD_WAIT: begin
if (clear) color <= 3'b000;
end
endcase
end
always @(posedge clk) begin : FF
if (!reset_n) begin
CURRENT_STATE <= ON_HOLD;
end else begin
CURRENT_STATE <= NEXT_STATE;
end
end
endmodule
| 9.509437 |
module instruction_shift_control (
input clk,
input reset_n,
output reg reset_random
);
// random need to be initialized with reset, but only once, we need control
reg [1:0] CURRENT_STATE, NEXT_STATE;
localparam START = 2'b01, RESET = 2'b10, DONE = 2'b11;
always @(*) begin
case (CURRENT_STATE)
START: NEXT_STATE = (reset_n) ? RESET : START;
RESET: NEXT_STATE = DONE;
DONE: NEXT_STATE = DONE;
endcase
end
always @(*) begin
reset_random = 1;
case (CURRENT_STATE)
RESET: reset_random = 0;
endcase
end
always @(posedge clk) begin
if (!reset_n) begin
CURRENT_STATE <= START;
end else begin
CURRENT_STATE <= NEXT_STATE;
end
end
endmodule
| 8.258005 |
module instruction_shift (
input change_instruction,
input clk,
input reset_n, // reset only the control, only once by FSM
output reg [2:0] instruction
);
wire [3:0] random;
wire rst_n;
reg [3:0] ran;
wire enable_control;
// reset this machine automatically in first 2 clk
instruction_shift_control c0 (
clk,
reset_n,
rst_n
);
random r1 (
clk,
rst_n,
random
);
always @(posedge change_instruction) begin : proc_
ran <= random;
if (ran < 4'b0011) instruction <= 3'b000; // UP
else if (ran < 4'b0110) instruction <= 3'b001; // DOWN
else if (ran < 4'b1001) instruction <= 3'b010; // LEFT
else if (ran < 4'b1011) instruction <= 3'b011; // RIGHT
else if (ran < 4'b1101) instruction <= 3'b100; // L
else instruction <= 3'b101; // R
end
endmodule
| 8.258005 |
module
module dff_0(clock,reset_n,data_in,q);
input clock,reset_n,data_in;
output reg q;
always@(posedge clock)
begin
if(reset_n == 0)
q <= 1'b0;
else
q<= data_in;
end
endmodule
| 6.870045 |
module dff_1 (
clock,
reset_n,
data_in,
q
);
input clock, reset_n, data_in;
output reg q;
always @(posedge clock) begin
if (reset_n == 0) q <= 1'b1;
else q <= data_in;
end
endmodule
| 6.721609 |
module ui_UP (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
writeEn,
reset_datapath
);
datapath_up d0 (
clk,
reset_datapath,
enable,
x,
y,
done
);
endmodule
| 7.14537 |
module control_UI (
input clk,
input reset_n,
input enable_unit,
output reg enable,
output reg writeEn,
output reg reset_datapath
);
localparam ENABLE_STATE = 4'b0000, ENABLE_WAIT = 4'b0001, DRAW = 4'b0010, DISABLE = 4'b0011;
reg [1:0] current_state, next_state;
always @(*) begin
case (current_state)
DISABLE: next_state = (enable_unit) ? DRAW : DISABLE;
// ENABLE_STATE : next_state = (enable_unit) ? ENABLE_STATE : ENABLE_WAIT;
// ENABLE_WAIT : next_state = DRAW;
DRAW: next_state = (reset_n) ? DRAW : DISABLE;
endcase
end
always @(*) begin
enable = 1'b0;
writeEn = 1'b0;
reset_datapath = 1'b0;
case (current_state)
DRAW: begin
enable = 1'b1;
writeEn = 1'b1;
reset_datapath = 1'b1;
end
endcase
end
always @(posedge clk) begin
if (!reset_n) begin
current_state <= DISABLE;
end else begin
current_state <= next_state;
end
end
endmodule
| 6.660162 |
module datapath_up (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done, frame enabled
wire [24:0] rate_out;
wire frame_enable;
// when frame division done, x enabled
wire [4:0] frame_out;
wire enable1, enable2, enable3;
always @(posedge clk) begin : proc_
if (!reset_n) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (done) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (enable3) begin
x <= 8'd79 - increment3;
y <= 7'd63 + increment3;
end else if (enable2) begin
x <= 8'd79 + increment2;
y <= 7'd63 + increment2;
end else if (enable1) begin
x <= 8'd79;
y <= 7'd63 + increment1;
end
end
// rate divider
rate_divider rate (
clk,
reset_n,
enable,
rate_out
);
assign frame_enable = (rate_out == 25'd0) ? 1 : 0;
// frame counter
frame_counter frame (
clk,
frame_enable,
reset_n,
frame_out
);
assign enable1 = (frame_out == 4'd4) ? 1 : 0; // DRAW IN 4 FRAME
counter_8 c1 (
clk,
enable1,
reset_n,
increment1
);
// assign y_enable = 1 when x goes through 1 row
assign enable2 = (increment1 == 3'b111) ? 1 : 0;
counter_4 c2 (
clk,
enable2,
reset_n,
increment2
);
assign enable3 = (increment2 == 3'b011) ? 1 : 0;
counter_4 c3 (
clk,
enable3,
reset_n,
increment3
);
assign done = (frame_out == 5'd15) ? 1 : 0;
// start done in 17 frame
endmodule
| 6.800186 |
module test_rate_divider (
input clk,
input reset_n,
input enable,
output [3:0] frame_out
);
wire [24:0] rate_out;
rate_divider rate (
clk,
reset_n,
enable,
rate_out
);
assign frame_enable = (rate_out == 25'd0) ? 1 : 0;
frame_counter frame (
clk,
frame_enable,
reset_n,
frame_out
);
endmodule
| 6.95378 |
module ui_DOWN (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
writeEn,
reset_datapath
);
datapath_down d0 (
clk,
reset_datapath,
enable,
x,
y,
done
);
endmodule
| 7.03474 |
module datapath_down (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done, frame enabled
wire [24:0] rate_out;
wire frame_enable;
// when frame division done, x enabled
wire [4:0] frame_out;
wire enable1, enable2, enable3;
always @(posedge clk) begin : proc_
if (!reset_n) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (done) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (enable3) begin
x <= 8'd79 - increment3;
y <= 7'd63 - increment3;
end else if (enable2) begin
x <= 8'd79 + increment2;
y <= 7'd63 - increment2;
end else if (enable1) begin
x <= 8'd79;
y <= 7'd63 - increment1;
end
end
// rate divider
rate_divider rate (
clk,
reset_n,
enable,
rate_out
);
assign frame_enable = (rate_out == 25'd0) ? 1 : 0;
// frame counter
frame_counter frame (
clk,
frame_enable,
reset_n,
frame_out
);
assign enable1 = (frame_out == 4'd5) ? 1 : 0; // DRAW IN 5 FRAME
counter_8 c1 (
clk,
enable1,
reset_n,
increment1
);
// assign y_enable = 1 when x goes through 1 row
assign enable2 = (increment1 == 3'b111) ? 1 : 0;
counter_4 c2 (
clk,
enable2,
reset_n,
increment2
);
assign enable3 = (increment2 == 3'b011) ? 1 : 0;
counter_4 c3 (
clk,
enable3,
reset_n,
increment3
);
assign done = (frame_out == 5'd15) ? 1 : 0;
// start done in 17 frame
endmodule
| 6.790293 |
module ui_RIGHT (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
writeEn,
reset_datapath
);
datapath_right d0 (
clk,
reset_datapath,
enable,
x,
y,
done
);
endmodule
| 6.687216 |
module datapath_right (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done, frame enabled
wire [24:0] rate_out;
wire frame_enable;
// when frame division done, x enabled
wire [4:0] frame_out;
wire enable1, enable2, enable3;
always @(posedge clk) begin : proc_
if (!reset_n) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (done) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (enable3) begin
x <= 8'd79 - increment3;
y <= 7'd63 + increment3;
end else if (enable2) begin
x <= 8'd79 - increment2;
y <= 7'd63 - increment2;
end else if (enable1) begin
x <= 8'd79 - increment1;
y <= 7'd63;
end
end
// rate divider
rate_divider rate (
clk,
reset_n,
enable,
rate_out
);
assign frame_enable = (rate_out == 25'd0) ? 1 : 0;
// frame counter
frame_counter frame (
clk,
frame_enable,
reset_n,
frame_out
);
assign enable1 = (frame_out == 4'd6) ? 1 : 0; // DRAW IN 6 FRAME
counter_8 c1 (
clk,
enable1,
reset_n,
increment1
);
// assign y_enable = 1 when x goes through 1 row
assign enable2 = (increment1 == 3'b111) ? 1 : 0;
counter_4 c2 (
clk,
enable2,
reset_n,
increment2
);
assign enable3 = (increment2 == 3'b011) ? 1 : 0;
counter_4 c3 (
clk,
enable3,
reset_n,
increment3
);
assign done = (frame_out == 5'd15) ? 1 : 0;
// start done in 17 frame
endmodule
| 6.744548 |
module ui_LEFT (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
writeEn,
reset_datapath
);
datapath_left d0 (
clk,
reset_datapath,
enable,
x,
y,
done
);
endmodule
| 6.847954 |
module datapath_left (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done, frame enabled
wire [24:0] rate_out;
wire frame_enable;
// when frame division done, x enabled
wire [4:0] frame_out;
wire enable1, enable2, enable3;
always @(posedge clk) begin : proc_
if (!reset_n) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (done) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (enable3) begin
x <= 8'd79 + increment3;
y <= 7'd63 + increment3;
end else if (enable2) begin
x <= 8'd79 + increment2;
y <= 7'd63 - increment2;
end else if (enable1) begin
x <= 8'd79 + increment1;
y <= 7'd63;
end
end
// rate divider
rate_divider rate (
clk,
reset_n,
enable,
rate_out
);
assign frame_enable = (rate_out == 25'd0) ? 1 : 0;
// frame counter
frame_counter frame (
clk,
frame_enable,
reset_n,
frame_out
);
assign enable1 = (frame_out == 4'd7) ? 1 : 0; // DRAW IN 7 FRAME
counter_8 c1 (
clk,
enable1,
reset_n,
increment1
);
// assign y_enable = 1 when x goes through 1 row
assign enable2 = (increment1 == 3'b111) ? 1 : 0;
counter_4 c2 (
clk,
enable2,
reset_n,
increment2
);
assign enable3 = (increment2 == 3'b011) ? 1 : 0;
counter_4 c3 (
clk,
enable3,
reset_n,
increment3
);
assign done = (frame_out == 5'd15) ? 1 : 0;
// start done in 17 frame
endmodule
| 6.965497 |
module ui_L (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
writeEn,
reset_datapath
);
datapath_L d0 (
clk,
reset_datapath,
enable,
x,
y,
done
);
endmodule
| 7.193055 |
module datapath_L (input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3;
// when rate division done, frame enabled
wire [24:0] rate_out;
wire frame_enable;
// when frame division done, x enabled
wire [4:0] frame_out;
wire enable1, enable2, enable3;
always @(posedge clk) begin : proc_
if (!reset_n)
begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end
else if (done)
begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end
// else if (enable3)
// begin
// x <= 8'd79 - increment3;
// y <= 7'd63 + increment3;
// end
else if (enable2)
begin
x <= 8'd79 + increment2;
y <= 7'd63;
end
else if (enable1)
begin
x <= 8'd79;
y <= 7'd63 - increment1;
end
end
// rate divider
rate_divider rate(clk, reset_n, enable, rate_out);
assign frame_enable = (rate_out == 25'd0) ? 1 : 0;
// frame counter
frame_counter frame(clk, frame_enable, reset_n, frame_out);
assign enable1 = (frame_out == 4'd8) ? 1 : 0; // DRAW IN 8 FRAME
counter_8 c1(clk, enable1, reset_n, increment1);
// assign y_enable = 1 when x goes through 1 row
assign enable2 = (increment1 == 3'b111) ? 1 : 0;
counter_4 c2(clk, enable2, reset_n, increment2);
// assign enable3 = (increment2 == 3'b011) ? 1 : 0;
// counter_4 c3(clk, enable3 & frame_enable, reset_n, increment3);
assign done = (frame_out == 5'd15) ? 1 : 0;
// start done in 17 frame
endmodule
| 6.685861 |
module ui_R (
input clk,
input reset_vga, // reset controller
input enable_control, // enable the control
output [7:0] x,
output [6:0] y,
output done,
output writeEn
);
wire enable, reset_datapath;
control_UI c0 (
clk,
reset_vga,
enable_control,
enable,
writeEn,
reset_datapath
);
datapath_R d0 (
clk,
reset_datapath,
enable,
x,
y,
done
);
endmodule
| 7.546963 |
module datapath_R (
input clk,
input reset_n,
input enable,
output reg [7:0] x,
output reg [6:0] y,
output done // signal for all ui drawing is done
);
// could vary according to shape
wire [2:0] increment1;
wire [2:0] increment2;
wire [2:0] increment3, increment4, increment5, increment6, increment7, increment8;
// when rate division done, frame enabled
wire [24:0] rate_out;
wire frame_enable;
// when frame division done, x enabled
wire [4:0] frame_out;
wire enable1, enable2, enable3, enable4, enable5, enable6, enable7, enable8;
always @(posedge clk) begin : proc_
if (!reset_n) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (done) begin
x <= 8'd79; // from middle
y <= 7'd63; // from top
end else if (enable8) begin
x <= 8'd79 + increment8;
y <= 7'd67 + increment8;
end else if (enable7) begin
x <= 8'd79;
y <= 7'd67 + increment7;
end else if (enable6) begin
x <= 8'd79;
y <= 7'd63 + increment6;
end else if (enable5) begin
x <= 8'd81 - increment5;
y <= 7'd67;
end else if (enable4) begin
x <= 8'd82 - increment4;
y <= 7'd66 + increment4;
end else if (enable3) begin
x <= 8'd82;
y <= 7'd64 + increment3;
end else if (enable2) begin
x <= 8'd81 + increment2;
y <= 7'd63 + increment2;
end else if (enable1) begin
x <= 8'd79 + increment1;
y <= 7'd63;
end
end
// rate divider
rate_divider rate (
clk,
reset_n,
enable,
rate_out
);
assign frame_enable = (rate_out == 25'd0) ? 1 : 0;
// frame counter
frame_counter frame (
clk,
frame_enable,
reset_n,
frame_out
);
assign enable1 = (frame_out == 4'd9) ? 1 : 0; // DRAW IN 9 FRAME
counter_4 c1 (
clk,
enable1,
reset_n,
increment1
); // --
// assign y_enable = 1 when x goes through 1 row
assign enable2 = (increment1 == 3'b011) ? 1 : 0;
counter_3 c2 (
clk,
enable2,
reset_n,
increment2
);
assign enable3 = (frame_out == 4'd10) ? 1 : 0; // DRAW IN 10 FRAME
counter_4 c3 (
clk,
enable3,
reset_n,
increment3
);
assign enable4 = (increment3 == 3'b011) ? 1 : 0;
counter_3 c4 (
clk,
enable4,
reset_n,
increment4
);
assign enable5 = (frame_out == 4'd11) ? 1 : 0; // DRAW IN 11 FRAME
counter_4 c5 (
clk,
enable5,
reset_n,
increment5
);
assign enable6 = (increment5 == 3'b011) ? 1 : 0;
counter_5 c6 (
clk,
enable6,
reset_n,
increment6
);
assign enable7 = (frame_out == 4'd12) ? 1 : 0; // DRAW IN 12 FRAME
counter_5 c7 (
clk,
enable7,
reset_n,
increment7
);
assign enable8 = (increment7 == 3'b100) ? 1 : 0;
counter_5 c8 (
clk,
enable8,
reset_n,
increment8
);
assign done = (frame_out == 5'd15) ? 1 : 0;
// start done in 17 frame
endmodule
| 6.777345 |
module counter_5 (
clk,
enable,
reset_n,
increment
);
input clk, enable, reset_n;
// could vary according to shape
output reg [2:0] increment;
always @(posedge clk) begin
if (!reset_n) begin
increment <= 3'b0;
end else if (enable) begin
if (increment == 3'b100) increment <= 3'b000;
else increment <= increment + 1'b1;
end
end
endmodule
| 6.894743 |
module counter_6 (
clk,
enable,
reset_n,
increment
);
input clk, enable, reset_n;
// could vary according to shape
output reg [2:0] increment;
always @(posedge clk) begin
if (!reset_n) begin
increment <= 3'b0;
end else if (enable) begin
if (increment == 3'b101) increment <= 3'b000;
else increment <= increment + 1'b1;
end
end
endmodule
| 6.768667 |
module counter_4 (
clk,
enable,
reset_n,
increment
);
input clk, enable, reset_n;
// could vary according to shape
output reg [2:0] increment;
always @(posedge clk) begin
if (!reset_n) begin
increment <= 3'b0;
end else if (enable) begin
if (increment == 3'b011) increment <= 3'b000;
else increment <= increment + 1'b1;
end
end
endmodule
| 6.562775 |
module counter_8 (
clk,
enable,
reset_n,
increment
);
input clk, enable, reset_n;
// could vary according to shape
output reg [2:0] increment;
always @(posedge clk) begin
if (!reset_n) begin
increment <= 3'b0;
end else if (enable) begin
if (increment == 3'b111) increment <= 3'b000;
else increment <= increment + 1'b1;
end
end
endmodule
| 7.065173 |
module frame_counter (
clk,
enable,
reset_n,
out
);
input clk, enable, reset_n;
output reg [4:0] out;
always @(posedge clk) begin
if (!reset_n) begin
out <= 5'b0;
end else if (enable) begin
if (out == 5'd15) out <= 5'b0;
else out <= out + 1'b1;
end
end
endmodule
| 6.859338 |
module rate_divider (
clk,
reset_n,
enable,
out
);
input clk;
input reset_n;
input enable;
output reg [24:0] out;
always @(posedge clk) begin
if (!reset_n) begin
out <= 25'd0;
end else if (enable) begin
if (out == 25'd3125000) begin
out <= 25'd0;
end else begin
out <= out + 1'b1;
end
end
end
endmodule
| 7.346866 |
module test_inputs (
input loop_rst,
input LVBL,
output reg [6:0] game_joystick1,
output reg button_1p,
output reg coin_left
);
localparam FIRE = 4;
localparam DOWN = 2;
integer framecnt = 0;
always @(negedge loop_rst) $display("INFO: loop_rst over.");
always @(negedge LVBL)
if (loop_rst) begin
game_joystick1 <= ~7'd0;
button_1p <= 1'b1;
coin_left <= 1'b0;
end else begin
framecnt <= framecnt + 1;
case (framecnt >> 3)
0: coin_left <= 1'b0; // enable all test modes
4: begin
coin_left <= 1'b1;
game_joystick1[DOWN] <= 1'b0;
end
8: begin
game_joystick1[DOWN] <= 1'b1;
game_joystick1[FIRE] <= 1'b0;
end
9: game_joystick1[FIRE] <= 1'b1;
endcase // framecnt
end
endmodule
| 7.415876 |
module test_input_2;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 1;
parameter SIGNED = 1;
parameter ASCENDING = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire y_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, x_0, x_1, x_label_0, x_label_1, x_valid);
$to_myhdl(y_0, y_1, y_label_0, y_label_1, y_valid);
// dump file
$dumpfile("test_input_2.lxt");
$dumpvars(0, test_input_2);
end
input_2 #(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
) UUT (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x_0),
.x_1(x_1),
.x_label_0(x_label_0),
.x_label_1(x_label_1),
.y_0(y_0),
.y_1(y_1),
.y_label_0(y_label_0),
.y_label_1(y_label_1),
.y_valid(y_valid)
);
endmodule
| 7.387447 |
module test_input_4;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 2;
parameter SIGNED = 1;
parameter ASCENDING = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DATA_WIDTH-1 : 0] x_3 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_2 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_3 = 0;
// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [DATA_WIDTH-1 : 0] y_2;
wire [DATA_WIDTH-1 : 0] y_3;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire [LABEL_WIDTH-1 : 0] y_label_2;
wire [LABEL_WIDTH-1 : 0] y_label_3;
wire y_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, x_0, x_1, x_2, x_3, x_label_0, x_label_1, x_label_2, x_label_3, x_valid);
$to_myhdl(y_0, y_1, y_2, y_3, y_label_0, y_label_1, y_label_2, y_label_3, y_valid);
// dump file
$dumpfile("test_input_4.lxt");
$dumpvars(0, test_input_4);
end
input_4 #(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
) UUT (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x_0),
.x_1(x_1),
.x_2(x_2),
.x_3(x_3),
.x_label_0(x_label_0),
.x_label_1(x_label_1),
.x_label_2(x_label_2),
.x_label_3(x_label_3),
.y_0(y_0),
.y_1(y_1),
.y_2(y_2),
.y_3(y_3),
.y_label_0(y_label_0),
.y_label_1(y_label_1),
.y_label_2(y_label_2),
.y_label_3(y_label_3),
.y_valid(y_valid)
);
endmodule
| 7.241409 |
module test_input_8;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 3;
parameter SIGNED = 1;
parameter ASCENDING = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DATA_WIDTH-1 : 0] x_3 = 0;
reg [DATA_WIDTH-1 : 0] x_4 = 0;
reg [DATA_WIDTH-1 : 0] x_5 = 0;
reg [DATA_WIDTH-1 : 0] x_6 = 0;
reg [DATA_WIDTH-1 : 0] x_7 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_2 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_3 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_4 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_5 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_6 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_7 = 0;
// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [DATA_WIDTH-1 : 0] y_2;
wire [DATA_WIDTH-1 : 0] y_3;
wire [DATA_WIDTH-1 : 0] y_4;
wire [DATA_WIDTH-1 : 0] y_5;
wire [DATA_WIDTH-1 : 0] y_6;
wire [DATA_WIDTH-1 : 0] y_7;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire [LABEL_WIDTH-1 : 0] y_label_2;
wire [LABEL_WIDTH-1 : 0] y_label_3;
wire [LABEL_WIDTH-1 : 0] y_label_4;
wire [LABEL_WIDTH-1 : 0] y_label_5;
wire [LABEL_WIDTH-1 : 0] y_label_6;
wire [LABEL_WIDTH-1 : 0] y_label_7;
wire y_valid;
initial begin
// myhdl integration
$from_myhdl(clk, rst, x_0, x_1, x_2, x_3, x_4, x_5, x_6, x_7, x_label_0, x_label_1, x_label_2,
x_label_3, x_label_4, x_label_5, x_label_6, x_label_7, x_valid);
$to_myhdl(y_0, y_1, y_2, y_3, y_4, y_5, y_6, y_7, y_label_0, y_label_1, y_label_2, y_label_3,
y_label_4, y_label_5, y_label_6, y_label_7, y_valid);
// dump file
$dumpfile("test_input_8.lxt");
$dumpvars(0, test_input_8);
end
input_8 #(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
) UUT (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x({x_7, x_6, x_5, x_4, x_3, x_2, x_1, x_0}),
.x_label({
x_label_7, x_label_6, x_label_5, x_label_4, x_label_3, x_label_2, x_label_1, x_label_0
}),
.y({y_7, y_6, y_5, y_4, y_3, y_2, y_1, y_0}),
.y_label({
y_label_7, y_label_6, y_label_5, y_label_4, y_label_3, y_label_2, y_label_1, y_label_0
}),
.y_valid(y_valid)
);
endmodule
| 7.425543 |
module test;
// Clock period, ns
parameter CLOCK_PERIOD = 500;
// Pulse width, gap and break delay
parameter PWID = 500;
parameter PGAP = 500;
parameter BREAK = 25000; // 25us
// time constants
localparam USEC = 1000;
localparam MSEC = 1000000;
// Output waveform file for this test
initial begin
$dumpfile("tests/test_input_chained.lxt2");
$dumpvars(0, test);
end
// 2MHz reference clock
reg refclk;
initial refclk = 1'b0;
always #(CLOCK_PERIOD / 2) refclk = !refclk;
// POST port interface
reg testreq;
wire testack;
initial testreq = 1'b0;
// LCD interface
wire [3:0] lcd_data;
wire lcd_rs, lcd_e;
// Transmit interface
reg [7:0] txin;
reg txpend;
initial txpend = 1'b0;
initial txin = 8'd0;
// Transmit interface is omitted, display adapters always tx 0x00
// Instantiate the module we're testing
postcode p (
.refclk (refclk),
.testreq(testreq),
.testack(testack),
.lcd_data(lcd_data),
.lcd_rs(lcd_rs),
.lcd_e(lcd_e),
.txin(txin), // always transmit 0x00, display interface
.tx_pending(txpend)
);
`include "tasks.v"
// Testbench
// Shift register, receives data sent in response to an INPUT req
reg [7:0] sr;
initial sr = 0;
always @(posedge testreq) #5 sr <= {sr[6:0], testack};
initial begin
// Startup delay
#(25 * USEC)
// Four pulses to initialise the FSM to a known state
pulsebreak(
4);
// Four pulses for INPUT, lastAck will NACK because txpend = 0
pulse(4);
if (lastAck != 1'b0) begin
$display("*** DUT ERROR at t=%d. DUT Acked an INPUT when txpend = 0", $time);
$finish;
end
// Send five chained bytes
reqcount = 0;
repeat (5) begin
txin = 8'h5A;
txpend = 1;
repeat (9) begin
// 8 data bit clocks plus the ack
pulse(1);
end
if (sr != 8'h5A) begin
$display("*** DUT ERROR at t=%d. INPUT phase, data mismatch. Got 0x%02X, wanted 0x%02X",
$time, sr, txin);
$finish;
end
end
#BREAK; // break to clear the FSM down
if (reqcount != (9 * 5)) begin
$display("*** DUT ERROR at t=%d. Request clock count mismatch. Got %d", $time, reqcount);
$finish;
end
$display("<OK> Chained input test completed. reqcount=%d, time=%d", reqcount, $time);
#(5 * USEC);
$finish;
end
endmodule
| 7.816888 |
module.v"
`include "../src/rate_divider.v"
module test_input_module(
CLOCK_50,
KEY,
LEDR,
LEDG);
input CLOCK_50;
input [1:0] KEY;
output [2:0] LEDR;
output [3:0] LEDG;
wire [27:0] one_hz = 28'b0010111110101111000010000000;
wire clock;
rate_divider rate0(
.clock_in(CLOCK_50),
.clock_out(clock),
.rate(one_hz)
);
reg [6:0] input_mem;
assign LEDG = input_mem;
input_module input0(
.clock(clock),
.input_in(KEY[0]),
.resetn(1'b1),
.ld_dot(LEDR[0]),
.ld_line(LEDR[1])
);
always @(posedge clock) begin
if (KEY[0])
input_mem <= 0;
else
input_mem <= { input_mem[3:0], 1'b1 };
end
endmodule
| 7.259509 |
module test;
// Clock period, ns
parameter CLOCK_PERIOD = 500;
// Pulse width, gap and break delay
parameter PWID = 500;
parameter PGAP = 500;
parameter BREAK = 25000; // 25us
// time constants
localparam USEC = 1000;
localparam MSEC = 1000000;
// Output waveform file for this test
initial begin
$dumpfile("tests/test_input.lxt2");
$dumpvars(0, test);
end
// 2MHz reference clock
reg refclk;
initial refclk = 1'b0;
always #(CLOCK_PERIOD / 2) refclk = !refclk;
// POST port interface
reg testreq;
wire testack;
initial testreq = 1'b0;
// LCD interface
wire [3:0] lcd_data;
wire lcd_rs, lcd_e;
// Transmit interface
reg [7:0] txin;
reg txpend;
initial txpend = 1'b0;
initial txin = 8'd0;
// Transmit interface is omitted, display adapters always tx 0x00
// Instantiate the module we're testing
postcode p (
.refclk (refclk),
.testreq(testreq),
.testack(testack),
.lcd_data(lcd_data),
.lcd_rs(lcd_rs),
.lcd_e(lcd_e),
.txin(txin), // always transmit 0x00, display interface
.tx_pending(txpend)
);
`include "tasks.v"
// Testbench
integer x;
localparam WS = 3; // number of wait states
// Shift register, receives data sent in response to an INPUT req
reg [7:0] sr;
initial sr = 0;
always @(posedge testreq) #5 sr <= {sr[6:0], testack};
initial begin
// Startup delay
#(25 * USEC)
// Four pulses to initialise the FSM to a known state
pulsebreak(
4);
// Four pulses for INPUT, lastAck will NACK because txpend=0
pulse(4);
if (lastAck != 1'b0) begin
$display("*** DUT ERROR at t=%d. DUT Acked an INPUT with txpend = 0", $time);
$finish;
end
// Send <WS> waitstates followed by an ACK and 8 data bits
x = 0;
txin = 8'h5A;
while (x < 8 + WS) begin // 8 data bit clocks plus wait states
//$display("lastAck = %d, x = %d", lastAck, x);
pulse(1);
x += 1;
if (x == WS - 1) begin
txpend = 1'b1;
end else if (x >= WS) begin
txpend = 1'b0;
end
end
#BREAK; // break to clear the FSM down
//$display("lastAck = %d, x = %d", lastAck, x);
if (sr != 8'h5A) begin
$display("*** DUT ERROR at t=%d. INPUT phase, data mismatch. Got 0x%02X, wanted 0x%02X",
$time, sr, txin);
$finish;
end
$display("<OK> Chained input test completed. time=%d", $time);
#(5 * USEC);
$finish;
end
endmodule
| 7.816888 |
module test_instruction;
// Inputs
reg [31:0] pc;
// Outputs
wire [31:0] instruction;
// Instantiate the Unit Under Test (UUT)
InstructionMemory_32 uut (
.pc(pc),
.instruction(instruction)
);
initial begin
// Initialize Inputs
pc = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.204418 |
module test_instruction_decoder ();
reg clk, rst;
reg [31:0] instruction;
reg [31:0] men_data;
reg [31:0] alu_result;
wire jal = instruction[31:26] == 6'b000011;
wire reg_write = (
instruction[31:29] == 3'b001 ||
instruction[31:26] == 6'b100011 ||
jal ||
instruction[31:26] == 6'b000000
) && !(instruction[31:26] == 6'b000000 && instruction[5:0] == 6'b001000);
wire mem_to_reg = instruction[31:26] == 6'b100011;
wire reg_dst = instruction[31:26] == 6'b000000;
reg [31:0] opcplus4;
wire [31:0] read_data_1;
wire [31:0] read_data_2;
wire [31:0] sign_extend;
instruction_decoder inst1 (
clk,
rst,
instruction,
men_data,
alu_result,
jal,
reg_write,
mem_to_reg,
reg_dst,
opcplus4,
read_data_1,
read_data_2,
sign_extend
);
initial begin
rst = 1;
instruction = 32'b0;
men_data = 32'b0;
alu_result = 32'b0;
opcplus4 = 32'b0;
#200 instruction = 32'b000000_00010_00011_00111_100000;
alu_result = 5;
end
endmodule
| 7.204418 |
module test_instruction_fetch ();
// input
reg [31:0] Add_result = 32'h00000000;
reg [31:0] Read_data_1 = 32'h00000000;
reg Branch = 1'b0;
reg nBranch = 1'b0;
reg Jmp = 1'b0;
reg Jal = 1'b0;
reg Jrn = 1'b0;
reg Zero = 1'b0;
reg clock = 1'b0, reset = 1'b1;
// output
wire [31:0] Instruction; // ���ָ�?
wire [31:0] PC_plus_4_out;
wire [31:0] opcplus4;
instruction_fetch Uifetch (
clock,
reset,
Instruction,
PC_plus_4_out,
opcplus4,
Add_result,
Read_data_1,
Branch,
nBranch,
Jmp,
Jal,
Jrn,
Zero
);
initial begin
#99 reset = 1'b0;
#100 Jal = 1;
#100 begin
Jrn = 1;
Jal = 0;
Read_data_1 = 32'h0000019c;
end
#100 begin
Jrn = 0;
Branch = 1'b1;
Zero = 1'b1;
Add_result = 32'h00000002;
end
#100 begin
Branch = 1'b0;
Zero = 1'b0;
end
end
always #50 clock = ~clock;
endmodule
| 7.204418 |
module: interleave_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_interleave_top_v;
// Inputs
reg clk;
reg clk_bit;
reg rst_n;
reg [7:0] din;
reg syn_in;
// Outputs
wire [7:0] dout_byte;
wire syn_out;
// Instantiate the Unit Under Test (UUT)
interleave_top uut (
.clk(clk),
.clk_bit(clk_bit),
.rst_n(rst_n),
.din(din),
.syn_in(syn_in),
.dout_byte(dout_byte),
.syn_out(syn_out)
);
initial begin
// Initialize Inputs
clk = 0;
clk_bit = 0;
rst_n = 0;
din = 0;
syn_in = 0;
#80 rst_n = 1'd1;
#100 rst_n = 1'd0;
#36000 rst_n = 1'd1;
// Wait 100 ns for global reset to finish
#500000 $stop;
// Add stimulus here
end
always #10 clk_bit = ~clk_bit;
always #80 clk = ~clk;
////stop counter
//reg [3:0] counter;
//always @ (posedge clk or negedge rst_n)
//begin
// if(!rst_n)
// begin
// counter <= 4'd0;
// end
// else if(counter == 4'd15)
// begin
// counter <= counter;
// end
// else if(syn_in == 1'd1)
// begin
// counter <= counter + 4'd1;
// end
//end
//take the counter as din
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
din <= 8'd66;
// else if(counter == 4'd15)
// din <= 8'dx;
else if (din == 8'd203)
din <= 8'd0;
else din <= din + 8'd1;
end
//
always @ (posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
syn_in <= 1'd0;
end
// else if(counter == 4'd15)
// begin
// syn_in <= 1'd0;
// end
else if (din == 8'd203)
begin
syn_in <= 1'd1;
end
else
begin
syn_in <= 1'd0;
end
end
endmodule
| 6.629 |
module f2_test (
in1,
in2,
out
);
input in1, in2;
output reg out;
always @(in1 or in2)
if (in1 > in2) out = in1;
else out = in2;
endmodule
| 6.539927 |
module f10_MyCounter (
clock,
preset,
updown,
presetdata,
counter
);
input clock, preset, updown;
input [1:0] presetdata;
output reg [1:0] counter;
always @(posedge clock)
if (preset) counter <= presetdata;
else if (updown) counter <= counter + 1;
else counter <= counter - 1;
endmodule
| 6.992385 |
module f12_test (
input in,
output out
);
//no buffer removal
assign out = in;
endmodule
| 7.136143 |
module f14_test (
in,
out
);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign w4 = w3;
assign out = w4;
f14_mybuf _f14_mybuf (
w2,
w3
);
endmodule
| 6.860461 |
module f14_mybuf (
in,
out
);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
| 7.333671 |
module f15_mybuf (
in,
out
);
input in;
output out;
wire w1, w2, w3, w4;
assign w1 = in;
assign w2 = w1;
assign out = w2;
endmodule
| 7.102453 |
module f16_test (
out,
in1,
in2,
vin1,
vin2,
vout1
);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 + in2;
assign vout1 = vin1 + vin2;
endmodule
| 6.8974 |
module f17_test (
in1,
in2,
vin1,
vin2,
out,
vout,
vin3,
vin4,
vout1
);
input in1, in2;
input [1:0] vin1;
input [3:0] vin2;
input [1:0] vin3;
input [3:0] vin4;
output vout, vout1;
output out;
assign out = in1 && in2;
assign vout = vin1 && vin2;
assign vout1 = vin3 || vin4;
endmodule
| 6.503725 |
module f18_test (
output out,
input in,
output [1:0] vout,
input [1:0] vin
);
assign out = ~in;
assign vout = ~vin;
endmodule
| 7.063564 |
module f20_test (
in1,
in2,
out,
vin1,
vin2,
vin3,
vin4,
vout1,
vout2,
en1,
ven1,
ven2
);
input in1, in2, en1, ven1;
input [1:0] ven2;
output out;
input [1:0] vin1, vin2, vin3, vin4;
output [1:0] vout1, vout2;
assign out = en1 ? in1 : in2;
assign vout1 = ven1 ? vin1 : vin2;
assign vout2 = ven2 ? vin3 : vin4;
endmodule
| 6.798931 |
module f21_test (
in,
out,
en,
vin1,
vout1,
en1
);
input in, en, en1;
output out;
input [1:0] vin1;
output [1:0] vout1;
assign out = en ? in : 1'bz;
assign vout1 = en1 ? vin1 : 2'bzz;
endmodule
| 6.873326 |
module f22_test (
in,
out,
vin,
vout,
vin1,
vout1,
vin2,
vout2
);
input in;
input [3:0] vin, vin1, vin2;
output [3:0] vout, vout1, vout2;
output out;
assign out = in << 1;
assign vout = vin << 2;
assign vout1 = vin1 >> 2;
assign vout2 = vin2 >>> 2;
endmodule
| 7.049654 |
module f24_test (
out,
in1,
in2,
vin1,
vin2,
vout1
);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 / in2;
assign vout1 = vin1 / vin2;
endmodule
| 6.651305 |
module f25_test (
out,
vout,
in,
vin
);
output out, vout;
input in;
input [3:0] vin;
assign out = !in;
assign vout = !vin;
endmodule
| 6.687032 |
module f28_test (
output out,
input [1:0] vin,
output out1,
input [3:0] vin1
);
assign out = &vin;
assign out1 = &vin1;
endmodule
| 6.751069 |
module f29_Reduction (
A1,
A2,
A3,
A4,
A5,
A6,
Y1,
Y2,
Y3,
Y4,
Y5,
Y6
);
input [1:0] A1;
input [1:0] A2;
input [1:0] A3;
input [1:0] A4;
input [1:0] A5;
input [1:0] A6;
output Y1, Y2, Y3, Y4, Y5, Y6;
//reg Y1, Y2, Y3, Y4, Y5, Y6;
assign Y1 = &A1; //reduction AND
assign Y2 = |A2; //reduction OR
assign Y3 = ~&A3; //reduction NAND
assign Y4 = ~|A4; //reduction NOR
assign Y5 = ^A5; //reduction XOR
assign Y6 = ~^A6; //reduction XNOR
endmodule
| 6.565295 |
module f30_test (
out,
in1,
in2,
vin1,
vin2,
vout1
);
output out;
input in1, in2;
input [1:0] vin1;
input [2:0] vin2;
output [3:0] vout1;
assign out = in1 - in2;
assign vout1 = vin1 - vin2;
endmodule
| 6.813864 |
module f31_test (
output out,
input in,
output [31:0] vout,
input [31:0] vin
);
assign out = -in;
assign vout = -vin;
endmodule
| 7.053981 |
module f32_test (
output out,
input in
);
assign out = +in;
endmodule
| 7.000614 |
module f33_test (
vin0,
vout0
);
input [2:0] vin0;
output reg [7:0] vout0;
wire [7:0] myreg0, myreg1, myreg2;
integer i;
assign myreg0 = vout0 << vin0;
assign myreg1 = myreg2 >> i;
endmodule
| 6.579599 |
module testbench
SXP Processor
Sam Gladstone
*/
`timescale 1ns / 1ns
`include "../src/int_cont.v"
module test_int_cont();
reg clk;
reg reset_b;
reg halt;
reg int_req;
reg [15:0] int_num;
reg safe_switch;
reg nop_detect;
wire int_rdy;
wire idle;
wire int_srv_req;
wire jal_req;
wire [15:0] int_srv_num;
integer i;
integer clk_cnt;
initial
begin
clk = 1'b 0;
clk_cnt = 0;
#10 forever
begin
#2.5 clk = ~clk;
if (clk)
begin
clk_cnt = clk_cnt + 1;
$display ("R Clk");
end
end
end
int_cont i_int_cont(
.clk(clk), // system clock
.reset_b(reset_b), // system reset
.halt(halt), // processor halt signal
.int_req(int_req), // signal that an interupt is requested
.int_num(int_num), // interupt number that is being requested
.safe_switch(safe_switch), // signal that processor is safe to switch
.nop_detect(nop_detect), // signal that the processor just executed a NOP instruction
.int_rdy(int_rdy), // 1 when int req will be serviced when requested
.idle(idle), // signal to idle processor;
.jal_req(jal_req), // signal to fetch to insert the JAL instruction
.int_srv_req(int_srv_req), // signal that the interupt was serviced
.int_srv_num(int_srv_num)); // interupt number that was serviced
initial
begin
$dumpfile("./icarus.vcd");
$dumpvars(1,i_int_cont);
end
initial
begin
halt = 1'b 0;
int_req = 1'b 0;
int_num = 1'b 0;
safe_switch = 1'b 0;
nop_detect = 1'b 0;
reset_b = 1'b 1;
@(negedge clk);
reset_b = 1'b 0;
@(negedge clk);
reset_b = 1'b 1;
@(negedge clk);
@(negedge clk);
@(negedge clk);
// Start with interupt request
$display ("Asserting request line");
int_req = 1'b 1;
int_num = 16'd 16;
@(negedge clk);
int_num = 16'b 0;
int_req = 1'b 0;
// Next rdy line should drop and idle goes high
@(negedge clk);
$display ("nop_cnt = %d",i_int_cont.nop_cnt);
@(negedge clk);
$display ("nop_cnt = %d",i_int_cont.nop_cnt);
@(negedge clk);
$display ("nop_cnt = %d",i_int_cont.nop_cnt);
safe_switch = 1'b 1;
$display ("Bringing safe switch high");
@(negedge clk);
$display ("nop_cnt = %d",i_int_cont.nop_cnt);
nop_detect = 1'b 1;
$display ("Bringing nop_detect high");
@(negedge clk);
$display ("nop_cnt = %d",i_int_cont.nop_cnt);
@(negedge clk);
$display ("nop_cnt = %d",i_int_cont.nop_cnt);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
$finish;
end
always @(negedge clk)
begin
$display ("state = %d, idle = %b, jal_req = %b, int_rdy = %b",i_int_cont.state,idle,jal_req,int_rdy);
end
endmodule
| 7.336453 |
module INV (
input I,
output O
);
wire GP_INV_inst0_OUT;
GP_INV GP_INV_inst0 (
.IN (I),
.OUT(GP_INV_inst0_OUT)
);
assign O = GP_INV_inst0_OUT;
endmodule
| 7.585108 |
module test_inv2;
wire out;
reg in, inv;
inverter Inverter (
out,
in,
inv
);
initial begin
in <= 0;
inv <= 0;
#10 inv <= 1;
end
initial $monitor("%b %b %b", inv, in, out);
endmodule
| 6.73782 |
module
// Project Name: GVISION200
// Target Devices: Spartan-6 xc6slx150-3fg900
// Tool versions: ISE13.1
// Description:
// Revision:
// V1.0-First created
//////////////////////////////////////////////////////////////////////////////////
module test_io_module( test_in_0, test_in_1, test_in_2, test_in_3, test_in_4, test_in_5, test_in_6, test_in_7, test_out
);
input test_in_0;
input test_in_1;
input test_in_2;
input test_in_3;
input test_in_4;
input test_in_5;
input test_in_6;
input test_in_7;
output [7:0] test_out;
assign test_out[0] = test_in_0;
assign test_out[1] = test_in_1;
//assign test_out[2] = test_in_2;
gclk_2_gpio gclk_2_gpio_2(
.gclk_in(test_in_2),
.clk_out(test_out[2]),
.ce(1'b1)
);
assign test_out[3] = test_in_3;
assign test_out[4] = test_in_4;
assign test_out[5] = test_in_5;
// gclk_2_gpio gclk_2_gpio_5(
// .gclk_in(test_in_5),
// .clk_out(test_out[5]),
// .ce(1'b1)
// );
assign test_out[6] = test_in_6;
//assign test_out[7] = test_in_7;
gclk_2_gpio gclk_2_gpio(
.gclk_in(test_in_7),
.clk_out(test_out[7]),
.ce(1'b1)
);
endmodule
| 7.088073 |
module test_is_sign ();
reg [31:0] result = 32'bz;
reg [31:0] a = 1, b = -1;
reg clk = 0;
reg [31:0] rrr = 0;
wire [31:0] www;
assign www = rrr;
initial begin
#0.1
rrr = 1;
#0.1
rrr = 2;
end
always
fork
//是无符号数比?
#1 result = a < b;
#11 result = a > b;
//可行
#3
forever begin
clk = ~clk;
#5;
end
join
endmodule
| 6.723615 |
module test_jbimu;
// Inputs
reg clks;
reg clock;
reg reset;
reg start;
wire miso;
// Outputs
wire [15:0] roll;
83
wire [15:0] pitch;
wire [15:0] yaw;
wire [15:0] roll_rate;
wire [15:0] pitch_rate;
wire [15:0] yaw_rate;
wire [15:0] accel_x;
wire [15:0] accel_y;
wire [15:0] accel_z;
wire done;
wire mosi;
wire sck;
wire ss;
// Instantiate the Unit Under Test (UUT)
jb_imu uut (
.clock(clock),
.reset(reset),
.start(start),
.roll(roll),
.pitch(pitch),
.yaw(yaw),
.roll_rate(roll_rate),
.pitch_rate(pitch_rate),
.yaw_rate(yaw_rate),
.accel_x(accel_x),
.accel_y(accel_y),
.accel_z(accel_z),
.done(done),
.miso(miso),
.mosi(mosi),
.sck(sck),
.ss(ss)
);
wire slave_done;
reg [7:0] din;
wire [7:0] slave_dout;
spi_slave slave(
.clk(clks),
.rst(reset),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sck(sck),
.done(slave_done),
.din(din),
.dout(slave_dout)
);
84
always #10 clock = ~clock; //50Mhz = 20 ns period
always #20 clks = ~clks; //25 Mhz slave clock
always @(slave_done) begin
if(slave_done) begin
din = din + 1'b1;
end
end
initial begin
// Initialize Inputs
clock = 0;
clks=0;
reset = 0;
start = 0;
din = 0;
// Wait 100 ns for global reset to finish
reset = 1;
#100;
reset = 0;
// Add stimulus here
din = 8'h00;
#20;
start = 1;
#20;
start = 0;
#10000;
end
endmodule
| 6.632599 |
module test_JK;
// Inputs
reg J;
reg K;
reg clk;
reg clear;
// Outputs
wire Q;
wire Qbar;
// Instantiate the Unit Under Test (UUT)
myJK uut (
.J(J),
.K(K),
.clk(clk),
.Q(Q),
.Qbar(Qbar)
);
initial begin
// Initialize Inputs
clear = 1;
J = 0;
K = 0;
clk = 0;
#100 clear = 0;
J = 0;
K = 0;
#100 J = 0;
K = 1;
#100 J = 1;
K = 0;
#100 J = 1;
K = 1;
#200;
$finish;
end
always #10 clk = ~clk;
endmodule
| 6.645279 |
module _test_JKlatchUP_rst;
reg j, k, clk, reset;
wire s1, s2;
supply1 power;
integer i;
JKlatchUP_rst test_JKlatchUP_rst (
j,
k,
clk,
reset,
s1,
s2
);
initial begin
reset = 1;
j = 1;
k = 1;
clk = 0;
i = 0;
$dumpfile("signal_JKlatchUP.vcd");
$dumpvars;
$display("\t\ttime, \tj, \tk, \tclk, \treset, \ts1, \ts2");
$monitor("%d \t%b \t%b \t%b \t%b \t%b \t%b", $time, j, k, clk, reset, s1, s2);
end
always begin
if (reset && clk == 1) begin
reset = 0;
end
if (i >= 10 && !clk) begin
$finish;
end
clk = ~clk;
#5;
end
always @(posedge clk) begin
i++;
end
endmodule
| 6.52092 |
module test_jmp (
input wire dummy
);
reg clk, reset;
localparam IL = 17;
localparam PRG = "/mnt/data/nand2tetris/Verilog/nand2tetris/src/test/test_jmp.mif";
wire signed [15:0] regD;
wire [15:0] regA;
wire writeM;
wire [15:0] data_in, data_out;
wire [ 14:0] addressM;
wire [IL-1:0] instruction;
wire [IL-2:0] addressI;
wire loadPC, stall;
single_port_ram cpu_ram (
.a_clk (clk),
.a_wr (writeM),
.a_addr(addressM),
.a_din (data_in),
.a_dout(data_out)
);
CPU #(
.IL (IL),
.PRG(PRG)
) CPU (
.clk(clk),
.reset(reset),
.writeM(writeM),
.outM(data_in),
.addressM(addressM),
.inM(data_out),
.D(regD),
.A(regA)
);
reg signed [15:0] regDExpected;
integer i, j;
always #1 clk = ~clk;
initial begin
clk = 1'b0;
regDExpected = -10;
#200
if (regD != regDExpected)
$display("[ERROR AT %t]! expected: %d, actual: %d", 0, regDExpected, regD);
else $display("[%t OK] expected: %d, actual: %d", 0, regDExpected, regD);
end
endmodule
| 6.722315 |
module TEST_KANADE32 ();
parameter CLK = 10;
reg reset_n;
reg clk;
always begin
#(CLK) clk <= ~clk;
end
initial begin
$dumpvars(0, TEST_KANADE32);
#0;
reset_n <= 1;
clk <= 0;
#1 reset_n <= 0;
#(CLK * 4) reset_n <= 1;
#1000000 $finish;
end
KANADE32 kanade (
.reset_n(reset_n),
.clk(clk)
);
endmodule
| 6.983331 |
module Test_Keyboard;
reg clk;
reg rst;
reg clr;
reg ps2_clk;
reg ps2_data;
wire [7:0] data;
wire cs;
wire ready;
assign cs = 1;
Keyboard keyboard (
.clk(clk),
.rst(rst),
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.data(data),
.cs(cs),
.clr(clr),
.ready(ready)
);
task RESET;
begin
rst = 0;
clk = 0;
ps2_clk = 0;
ps2_data = 0;
clr = 0;
#5 rst = 1;
#5 rst = 0;
end
endtask
;
task CLOCK;
input [31:0] count;
integer k;
begin
for (k = 0; k < count; k = k + 1) begin
#5 clk = 1;
#5 clk = 0;
end
end
endtask
reg [10:0] payload;
task PS2_TRANSMIT;
input [7:0] send;
integer k;
begin
payload = {
1'b1, ~^send, send[7], send[6], send[5], send[4], send[3], send[2], send[1], send[0], 1'b0
};
$display("payload = 0b%b", payload);
for (k = 0; k < 11; k = k + 1) begin
ps2_data = payload[k];
ps2_clk = 1;
$display("payload = 0b%b :: send = 0b%b :: ps2_data = 0b%b :: k = %d", payload, send,
ps2_data, k);
CLOCK(1);
ps2_clk = 0;
CLOCK(1);
end
ps2_clk = 1;
CLOCK(1);
end
endtask
parameter FULL_CYCLE = 32'd10_000_000;
initial begin
#10 #10 RESET;
PS2_TRANSMIT(8'h1C);
CLOCK(10);
#10 $stop;
#5 $finish;
end
endmodule
| 6.595034 |
module TOP;
//ALU inputs
reg [31:0] a, b;
wire [31:0] p;
wire [31:0] g;
wire [31:0] c;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 32'hffffffff;
b = 32'h00000000;
#`cycle //1
if(c != 32'b00000000)
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 32'ha47ba47b;
b = 32'h5c915c91;
#`cycle //3
if(c != 32'hfcf3fcf3)
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 32'hbcdabcda;
b = 32'h79867986;
#`cycle //5
if(c != 32'hf99ef99e)
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 32'h96579657;
b = 32'h34563456;
#`cycle //7
if(c != 32'h34563456)
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! %3.2F ns cycle time ***\n", `cycle);
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("kogge_stone_lookahead.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(*)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, carry = %x",
$time, a, b, c);
// else
// $strobe ("correct: time: %0d: a = %x, b = %x, carry = %x",
// $time, a, b, c);
generate32 generate32_test(g, a, b);
propagate32 propagate32_test(p, a, b);
gp_group32 (c, g, p);
endmodule
| 7.259416 |
module test_KSA;
reg [15:0] x, y; // input x, y
reg c0; // carry in
wire [15:0] sum; // output sum
wire c16; // carry out
reg [16:0] check; // KoggeStoneAdder로 구한 값이 맞는지 확인
integer i, j, k;
integer num_correct; // 값이 맞을 경우 증가
integer num_wrong; // 값이 틀릴 경우 증가
KoggeStoneAdder ksa (
c16,
sum,
x,
y,
c0
); // Kogge Stone Adder
initial begin
num_correct = 0;
num_wrong = 0;
for (i = 0; i < 65536; i = i + 1000) begin
x = i; // X값은 0에서 ~ 65535까지 1000씩 증가한다.
for (j = 0; j < 65536; j = j + 1000) begin
y = j; // Y값 0에서 ~ 65535까지 1000씩 증가한다.
for (k = 0; k < 2; k = k + 1) begin
c0 = k; // carry in 0 또는 1
check = x + y + c0; // Kogge Stone Adder로 계산한 값이 실제 계산 값과 일치하는지 확인
#10
if ({c16, sum} == check) // Kogge Stone Adder로 계산한 값이 맞으면
num_correct = num_correct + 1; // num_correct 증가
else num_wrong = num_wrong + 1;
$display($time, ": %d + %d + %d = %d (%d)", x, y, c0, {c16, sum}, check);
// Kogge Stone Adder로 계산한 결과와 실제 계산 값을 출력하여 제대로 계산되었는지 확인
end
end
end
$display("num_correct = %d, num_wrong = %d", num_correct, num_wrong);
// 맞은 개수, 틀린 개수 출력
end
endmodule
| 6.733552 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
| 7.868877 |
module coreir_mem #(
parameter has_init = 1'b0,
parameter sync_read = 1'b0,
parameter depth = 1,
parameter width = 1,
parameter [(width * depth) - 1:0] init = 0
) (
input clk,
input [width-1:0] wdata,
input [$clog2(depth)-1:0] waddr,
input wen,
output [width-1:0] rdata,
input [$clog2(depth)-1:0] raddr
);
reg [width-1:0] data[depth-1:0];
generate
if (has_init) begin
genvar j;
for (j = 0; j < depth; j = j + 1) begin
initial begin
data[j] = init[(j+1)*width-1:j*width];
end
end
end
endgenerate
always @(posedge clk) begin
if (wen) begin
data[waddr] <= wdata;
end
end
generate
if (sync_read) begin
reg [width-1:0] rdata_reg;
always @(posedge clk) begin
rdata_reg <= data[raddr];
end
assign rdata = rdata_reg;
end else begin
assign rdata = data[raddr];
end
endgenerate
endmodule
| 7.482949 |
module RAM256x16 (
input [7:0] RADDR,
output [15:0] RDATA,
input [7:0] WADDR,
input [15:0] WDATA,
input CLK,
input WE
);
wire [15:0] coreir_mem256x16_inst0_rdata;
wire [15:0] reg_P_inst0_out;
coreir_mem #(
.depth(256),
.has_init(1'b0),
.sync_read(1'b0),
.width(16)
) coreir_mem256x16_inst0 (
.clk (CLK),
.wdata(WDATA),
.waddr(WADDR),
.wen (WE),
.rdata(coreir_mem256x16_inst0_rdata),
.raddr(RADDR)
);
coreir_reg #(
.clk_posedge(1'b1),
.init(16'h0000),
.width(16)
) reg_P_inst0 (
.clk(CLK),
.in (coreir_mem256x16_inst0_rdata),
.out(reg_P_inst0_out)
);
assign RDATA = reg_P_inst0_out;
endmodule
| 6.532367 |
module test_lcd (
input wire CLK_IN,
input wire RST_N,
output wire [0:7] R,
output wire [0:7] G,
output wire [0:7] B,
output wire LCD_CLK,
output wire LCD_HSYNC,
output wire LCD_VSYNC,
output wire LCD_DEN,
output wire LCD_PWM //backlight,set to high
);
wire clk_lcd;
wire clklock;
wire [10:0] hsync;
wire [10:0] vsync;
ip_pll pll (
.refclk(CLK_IN),
.reset(~RST_N),
.extlock(clklock),
.clk0_out(clk_lcd)
);
//lcd display
wire [10:0] hsync_cnt;
wire [10:0] vsync_cnt;
wire lcd_rden;
wire [15:0] lcd_rddat; //lcd read
wire [15:0] lcd_rdaddr;
lcd_sync #(
.IMG_W(800),
.IMG_H(480),
.IMG_X(0),
.IMG_Y(0)
) u_lcd_sync (
.clk (clk_lcd),
.rest_n (RST_N),
.lcd_clk (LCD_CLK),
.lcd_pwm (LCD_PWM),
.lcd_hsync (LCD_HSYNC),
.lcd_vsync (LCD_VSYNC),
.lcd_de (LCD_DEN),
.hsync_cnt (hsync_cnt),
.vsync_cnt (vsync_cnt),
.img_ack (lcd_rden),
.addr (lcd_rdaddr)
);
data_out datout (
.clk_lcd (clk_lcd),
.R (R),
.G (G),
.B (B),
.den (lcd_rden),
.hsync (hsync_cnt),
.vsync (vsync_cnt)
);
endmodule
| 7.337433 |
module test_lecture4;
// inputs (use regs)
reg [2:0] swt;
// Outputs use wires
wire D;
integer i;
reg e_output;
// Instantiate the Device/Module Under Test (DUT)
lecture4 ttul (
.A(swt[2]),
.B(swt[1]),
.C(swt[0]),
.D(D)
);
// Define the same module functionality for the expected value computation
function expected_led;
input [2:0] switch;
begin
expected_led = (switch[2] | switch[1]) & switch[0];
end
endfunction
// Define the stimuli generation and compare with expected output
// Initial blocks occurs only once at time zero
initial begin
for (i = 0; i < 8; i = i + 1) begin
#50 swt = i;
#10 e_output = expected_led(swt);
// the $display task will print message in simulator console window when run
if (D == e_output) $display("LED output matched at %t\n", $time);
else $display("LED output mis-matched at %t, expected %b, actual %b\n", $time, e_output, D);
end
end
endmodule
| 7.332089 |
module test_level;
wire [3:0] level;
reg up;
reg down;
reg clk;
reg rst_n;
level U0 (
level,
up,
down,
clk,
rst_n
);
always #5 clk = ~clk;
initial begin
clk = 0;
rst_n = 1;
up = 0;
down = 0;
#10 rst_n = 0;
#10 rst_n = 1;
#10 up = 1;
#100 up = 0;
#10 down = 1;
#50 down = 0;
end
endmodule
| 6.73827 |
module: model_lexer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_lexer;
// Inputs
reg clk_25mhz;
reg reset;
reg [7:0] data_in;
reg [7:0] data_step;
// Outputs
wire [31:0] data_out;
// Instantiate the Unit Under Test (UUT)
model_lexer uut (
.clk_25mhz(clk_25mhz),
.reset(reset),
.data_in(data_in),
.data_step(data_step),
.data_out(data_out)
);
initial begin
// Initialize Inputs
clk_25mhz = 0;
reset = 1;
data_step = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 0;
data_step = 1;
end
always begin
clk_25mhz<=~clk_25mhz;
#50;
end
reg [7:0] counter;
initial begin
counter <= 8'b0;
end
wire [7:0] token;
assign token = data_out[7:0]<8 ? data_out[7:0]+48 : data_out[7:0];
// let str=" (\\xxx.xxx) yyy" in sequence_ $ map putStr $ ["parameter max_size = ",(show (length str)),";\nwire [7:0] string [0:max_size-1];\n/*",str,"*/\n"] ++ ([("assign string[" ++ show (fst t) ++ "] = " ++ "8'd" ++ show (ord (snd t)) ++ ";\n") | t<-zip [0..] str])
parameter max_size = 8;
wire [7:0] string [0:max_size-1];
/* id=\x.x*/
assign string[0] = 8'd32;
assign string[1] = 8'd105;
assign string[2] = 8'd100;
assign string[3] = 8'd61;
assign string[4] = 8'd92;
assign string[5] = 8'd120;
assign string[6] = 8'd46;
assign string[7] = 8'd120;
always @(posedge clk_25mhz or posedge reset) begin
if(reset) begin
counter <= 8'b0;
end else begin
if(counter<max_size) begin
data_in<=string[counter];
counter<=counter+1;
end else begin
data_in<=0;
end
end
end
endmodule
| 6.972625 |
module testLibrary (
input signed [15:0] signedInput,
input [15:0] unsignedInput,
output signed [ 7:0] signedSRange,
output [ 7:0] unsignedSPositive,
output [ 7:0] unsignedUPositive,
output signed [15:0] signedRountToZeroExM1
);
clampSRange #(
.INW (16),
.OUTW(8)
) myClampSRange (
.valueIn (signedInput),
.valueOut(signedSRange)
);
clampSPositive #(
.INW (16),
.OUTW(8)
) myClampSPositive (
.valueIn (signedInput),
.valueOut(unsignedSPositive)
);
clampUPositive #(
.INW (16),
.OUTW(8)
) myClampUPositive (
.valueIn (unsignedInput),
.valueOut(unsignedUPositive)
);
roundTowardZeroExceptM1 #(
.WIDTH(16)
) myRTZEM1 (
.valueIn (signedInput),
.valueOut(signedRountToZeroExM1)
);
endmodule
| 6.999229 |
module test ( //input
pulse_clk,
sys_rst_l,
Xe,
Ye,
change_readyH,
//output
X_acc,
Y_acc,
X_dec,
Y_dec,
draw_overH
);
parameter LO = 1'b0, HI = 1'b1, X = 1'bx;
parameter r_IDLE = 3'b001, r_INIT = 3'b010, r_WORK = 3'b011, r_JUDGE = 3'b100, r_0VER = 3'b101;
reg [2:0] state;
reg [2:0] next_state;
input pulse_clk;
input sys_rst_l;
input signed [15:0] Xe;
input signed [15:0] Ye;
input change_readyH;
output X_acc; //x+
output Y_acc; //y+
output X_dec; //x-
output Y_dec; //y-
output draw_overH; //岹
reg X_acc;
reg Y_acc;
reg X_dec;
reg Y_dec;
reg draw_overH;
integer i_Xe; //յ
integer i_Ye;
reg [15:0] Xe_abs; //յֵ
reg [15:0] Ye_abs;
integer i_Xe_sign; //
integer i_Ye_sign;
reg r_e; //x=0ʱ
integer error; //ƫ
integer steps; //ܲ
always @(posedge pulse_clk or negedge sys_rst_l) begin //첽λ
if (~sys_rst_l) state <= r_IDLE;
else state <= next_state;
end
always @(state or change_readyH or steps) begin
next_state = X;
case (state)
r_IDLE: begin
if (change_readyH) next_state = r_INIT;
else next_state = r_IDLE;
end
r_INIT: begin
next_state = r_WORK;
end
r_WORK: begin
next_state = r_JUDGE;
end
r_JUDGE: begin
if (steps == 0) next_state = r_0VER;
else next_state = r_WORK;
end
r_0VER: begin
next_state = r_IDLE;
end
endcase
end
always @(posedge pulse_clk) begin
case (state)
r_IDLE: begin
draw_overH = LO;
X_acc = 0;
Y_acc = 0;
X_dec = 0;
Y_dec = 0;
error = 0;
steps = 0;
end
r_INIT: begin
r_e = 0;
if (Xe > 0) begin
i_Xe_sign = 1;
Xe_abs = Xe;
end else if (Xe < 0) begin
i_Xe_sign = -1;
Xe_abs = -Xe;
end else begin
i_Xe_sign = 0;
Xe_abs = 0;
r_e = 1;
end
if (Ye > 0) begin
i_Ye_sign = 1;
Ye_abs = Ye;
end else if (Ye < 0) begin
i_Ye_sign = -1;
Ye_abs = -Ye;
end else begin
i_Ye_sign = 0;
Ye_abs = 0;
end
steps = Xe_abs + Ye_abs + r_e;
end
r_WORK: begin
if (pulse_clk) begin
if (error >= 0) begin
if (i_Xe_sign > 0) begin
X_acc = 1;
X_dec = 0;
Y_acc = 0;
Y_dec = 0;
end else if (i_Xe_sign < 0) begin
X_acc = 0;
X_dec = 1;
Y_acc = 0;
Y_dec = 0;
end
error = error - Ye_abs;
end else begin
if (i_Ye_sign > 0) begin
X_acc = 0;
X_dec = 0;
Y_acc = 1;
Y_dec = 0;
end else if (i_Ye_sign < 0) begin
X_acc = 0;
X_dec = 0;
Y_acc = 0;
Y_dec = 1;
end
error = error + Xe_abs;
end
steps = steps - 1;
end
end
r_JUDGE: begin
X_acc = 0;
X_dec = 0;
Y_acc = 0;
Y_dec = 0;
end
r_0VER: begin
draw_overH = HI;
X_acc = 0;
X_dec = 0;
Y_acc = 0;
Y_dec = 0;
end
default: begin
draw_overH = X;
X_acc = X;
Y_acc = X;
X_dec = X;
Y_dec = X;
error = X;
steps = X;
end
endcase
end
endmodule
| 7.204801 |
module test_ll_axis_bridge;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] ll_data_in = 0;
reg ll_sof_in_n = 1;
reg ll_eof_in_n = 1;
reg ll_src_rdy_in_n = 1;
reg m_axis_tready = 0;
// Outputs
wire ll_dst_rdy_out_n;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, ll_data_in, ll_sof_in_n, ll_eof_in_n, ll_src_rdy_in_n,
m_axis_tready);
$to_myhdl(m_axis_tdata, m_axis_tvalid, m_axis_tlast, ll_dst_rdy_out_n);
// dump file
$dumpfile("test_ll_axis_bridge.lxt");
$dumpvars(0, test_ll_axis_bridge);
end
ll_axis_bridge #(
.DATA_WIDTH(DATA_WIDTH)
) UUT (
.clk(clk),
.rst(rst),
// locallink input
.ll_data_in(ll_data_in),
.ll_sof_in_n(ll_sof_in_n),
.ll_eof_in_n(ll_eof_in_n),
.ll_src_rdy_in_n(ll_src_rdy_in_n),
.ll_dst_rdy_out_n(ll_dst_rdy_out_n),
// axi output
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast)
);
endmodule
| 8.891994 |
module test_logic_shift ();
parameter CLOCK_CYCLE = 100;
parameter BIT_NUM = 8;
parameter SHIFT_BIT_NUM = 3;
parameter COUNTER_BIT_NUM = BIT_NUM + SHIFT_BIT_NUM + 1;
parameter SIMULATION_PERIOD = 500;
// signal defenition
reg clk;
reg reset;
reg [COUNTER_BIT_NUM -1:0] counter;
wire [ BIT_NUM-1:0] data_in;
wire [ SHIFT_BIT_NUM-1:0] shift_bit_num;
wire is_right_shift;
wire [ BIT_NUM-1:0] data_out;
assign data_in = counter[BIT_NUM+SHIFT_BIT_NUM+1-1:SHIFT_BIT_NUM+1];
assign shift_bit_num = counter[SHIFT_BIT_NUM-1:1];
assign is_right_shift = counter[0];
// dump wave file
initial begin
$dumpfile("tmp/dump.vcd");
$dumpvars(0, test_logic_shift);
end
// monitor
initial begin
$monitor("[%t] data=%b, shift_bit_num=%d, is_right_shift=%b => data_out=%b", $time,
logic_shift_1.data_in, logic_shift_1.shift_bit_num, logic_shift_1.is_right_shift,
logic_shift_1.data_out);
end
// simulation end
initial begin
#(CLOCK_CYCLE * SIMULATION_PERIOD) $finish;
end
// clock
initial begin
#10 clk <= 1'b0;
forever begin
#(CLOCK_CYCLE / 2) clk <= ~clk;
end
end
// reset
initial begin
#10 reset <= 1'b0;
#300 reset <= 1'b1;
end
// counter
always @(posedge clk or negedge reset) begin
if (~reset) begin
counter <= {COUNTER_BIT_NUM{1'b0}};
end else begin
counter <= counter + {{COUNTER_BIT_NUM - 1{1'b0}}, 1'b1};
end
end
logic_shift #(
.BIT_NUM (BIT_NUM),
.SHIFT_BIT_NUM(SHIFT_BIT_NUM)
) logic_shift_1 (
.data_in (data_in),
.shift_bit_num (shift_bit_num),
.is_right_shift(is_right_shift),
.data_out (data_out)
);
endmodule
| 7.541332 |
module test_logic_tb ();
reg [7:0] a;
reg [7:0] b;
wire out, out_a, out_b;
wire [7:0] data;
reg clk, load, rst;
test_logic TL (
a,
b,
data,
out_a,
out_b,
out,
clk,
rst,
load
);
initial begin
rst = 0;
clk = 0;
load = 0;
#20 rst = 1;
#20 rst = 0;
#20 a = 8'b11100110;
b = 8'b11000111;
#20 load = 1;
#20 load = 0;
//#100 a=8'b10010010;b=8'b10011010;
#170 rst = 1;
#20 rst = 0;
#20 a = 8'b11101110;
b = 8'b11110011;
#20 load = 1;
#20 load = 0;
#170 $finish;
end
always #10 clk = ~clk;
endmodule
| 6.999757 |
module LUT2 (
input I0,
input I1,
output O
);
wire GP_2LUT_inst0_OUT;
GP_2LUT #(
.INIT(4'h8)
) GP_2LUT_inst0 (
.IN0(I0),
.IN1(I1),
.OUT(GP_2LUT_inst0_OUT)
);
assign O = GP_2LUT_inst0_OUT;
endmodule
| 6.567004 |
module LUT3 (
input I0,
input I1,
input I2,
output O
);
wire GP_3LUT_inst0_OUT;
GP_3LUT #(
.INIT(8'h80)
) GP_3LUT_inst0 (
.IN0(I0),
.IN1(I1),
.IN2(I2),
.OUT(GP_3LUT_inst0_OUT)
);
assign O = GP_3LUT_inst0_OUT;
endmodule
| 6.707736 |
module LUT4 (
input I0,
input I1,
input I2,
input I3,
output O
);
wire GP_4LUT_inst0_OUT;
GP_4LUT #(
.INIT(16'h8000)
) GP_4LUT_inst0 (
.IN0(I0),
.IN1(I1),
.IN2(I2),
.IN3(I3),
.OUT(GP_4LUT_inst0_OUT)
);
assign O = GP_4LUT_inst0_OUT;
endmodule
| 6.884042 |
module stream_gen (
input i_clk,
input i_enable,
input i_ready,
output [7:0] o_data,
output o_valid
);
reg [9:0] test_vector_idx = 0;
reg [7:0] test_vector[0:1023];
integer i;
initial begin
i = 0;
// Zero bytes
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'h00;
// Garbage
test_vector[i++] = 8'h23;
test_vector[i++] = 8'hE0;
test_vector[i++] = 8'h01;
test_vector[i++] = 8'h00;
test_vector[i++] = 8'hFA;
test_vector[i++] = 8'h77;
// Command 1 - READ MAGIC
test_vector[i++] = 8'hA2; // CMD
test_vector[i++] = 8'd00; // CNT0
test_vector[i++] = 8'd00; // ADDR0
// Command 2 - READ EVERYTHING
test_vector[i++] = 8'hA4; // CMD
test_vector[i++] = 8'hFF; // CNT
test_vector[i++] = 8'h00; // ADDR
//
for (i = i; i < 1024; i = i + 1) begin
test_vector[i] = 8'b0;
end
end
assign o_valid = i_enable;
assign o_data = test_vector[test_vector_idx];
always @(posedge i_clk) begin
if (o_valid && i_ready) begin
// Transaction happens, increment idx
test_vector_idx <= test_vector_idx + 10'd1;
end
end
endmodule
| 6.890266 |
module test_ly_2257_4 ();
reg clk_in; //输入
reg rst;
reg sel;
wire clk_out; //输出
initial //初始化
begin
clk_in = 1'b0;
sel = 1'b0;
rst = 1'b0;
#100 rst = 1'b1;
#200000 sel = 1'b1;
end
always #1 clk_in = ~clk_in; //设置clk_in频率
ly_2257_4 divider (
.clk_in (clk_in),
.rst (rst),
.sel (sel),
.clk_out(clk_out)
);
endmodule
| 7.423298 |
module test_ly_2257_5 ();
// 输入
reg clk;
reg reset_n;
reg key;
// 输出
wire key_state;
wire [3:0] Q;
wire [6:0] codeout;
wire CO;
ly_2257_5 test (
.clk(clk),
.reset_n(reset_n),
.key(key),
.key_state(key_state),
.Q(Q),
.codeout(codeout),
.CO(CO)
);
always #1 clk = ~clk;
initial begin
//初始化
clk = 1'b0;
reset_n = 1'b0;
key = 1'b1;
#200;
reset_n = 1'b1; //拉高reset_n，结束复位
end
always begin
//抖动
#100000;
key = 1'b1;
#100000;
key = 1'b0;
#100000;
key = 1'b1;
#100000;
key = 1'b0;
#100000;
key = 1'b1;
#100000;
key = 1'b0;
#100000;
key = 1'b1;
#100000;
key = 1'b0;
#100000;
key = 1'b1;
#100000;
key = 1'b0;
//稳定
#(40 * 100000);
key = 1'b1;
//抖动
#100000;
key = 1'b0;
#100000;
key = 1'b1;
#100000;
key = 1'b0;
#100000;
key = 1'b1;
#100000;
key = 1'b0;
#100000;
key = 1'b1;
#100000;
key = 1'b0;
#100000;
key = 1'b1;
#100000;
key = 1'b0;
#100000;
key = 1'b1;
//稳定
#(40 * 100000);
key = 1'b0;
end
endmodule
| 7.423298 |
module test_ly_2257_6;
reg Ain, Bin, rst, clkin;
wire [3:0] cnt;
wire [6:0] codeout;
wire A;
wire B;
initial begin
Ain = 0;
Bin = 0;
rst = 0;
clkin = 0;
#10 rst = 1;
end
always #5 clkin <= ~clkin;
always begin
#400 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#200 Ain = 1;
#200 Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#600 Ain = 0;
#400 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#200 Ain = 1;
#200 Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#600 Ain = 0;
//减计数
#600 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#10 Ain = 0;
#10 Ain = 1;
#200 Ain = 1;
#200 Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#10 Ain = 1;
#10;
Ain = 0;
#400 Ain = 0;
end
always begin
#600 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#200 Bin = 1;
#200 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#400 Bin = 0;
#600 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#200 Bin = 1;
#200 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#400 Bin = 0;
//减计数
#400 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#200 Bin = 1;
#200 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#10 Bin = 1;
#10 Bin = 0;
#600 Bin = 0;
end
ly_2257_6 test (
.Ain(Ain),
.Bin(Bin),
.clkin(clkin),
.rst(rst),
.cnt(cnt),
.codeout(codeout),
.A(A),
.B(B)
);
endmodule
| 7.423298 |
module test_ly_2257_7 ();
reg clk_in;
reg rst;
reg auto;
reg [13:0] Key;
wire clk_out;
wire clk_out2;
wire [ 7:0] codeout;
wire [ 6:0] low;
wire [ 6:0] middle;
ly_2257_7_3 play (
.clk_in(clk_in),
.rst(rst),
.auto(auto),
.Key(Key),
.clk_out(clk_out),
.clk_out2(clk_out2),
.codeout(codeout),
.low(low),
.middle(middle)
);
initial clk_in = 1;
always #500 clk_in = ~clk_in; //时钟频率1MHZ
initial begin
rst = 0;
auto = 0;
Key = 14'b0;
#(1000) rst = 1;
#(10000 * 1000);
repeat(3) //每次按下按键10ms
begin
#(10000 * 1000) auto = 1;
Key = 14'b000_0000_000_0001;
#(10000 * 1000) Key = 14'b000_0000_000_0010;
#(10000 * 1000) Key = 14'b000_0000_000_0100;
#(10000 * 1000) Key = 14'b000_0000_000_1000;
#(10000 * 1000) Key = 14'b000_0000_001_0000;
#(10000 * 1000) Key = 14'b000_0000_010_0000;
#(10000 * 1000) Key = 14'b000_0000_100_0000;
#(10000 * 1000) Key = 14'b000_0001_000_0000;
#(10000 * 1000) Key = 14'b000_0010_000_0000;
#(10000 * 1000) Key = 14'b000_0100_000_0000;
#(10000 * 1000) Key = 14'b000_1000_000_0000;
#(10000 * 1000) Key = 14'b001_0000_000_0000;
#(10000 * 1000) Key = 14'b010_0000_000_0000;
#(10000 * 1000) Key = 14'b100_0000_000_0000;
end
end
endmodule
| 7.423298 |
module test_mac18x25x20;
// Inputs
reg [24:0] cin;
reg [17:0] din;
reg first;
reg last;
reg clk;
reg rst;
// Outputs
wire [19:0] dout;
wire ov;
wire ovf;
// Instantiate the Unit Under Test (UUT)
mac18x25x20 uut (
.cin(cin),
.din(din),
.first(first),
.last(last),
.dout(dout),
.ov(ov),
.ovf(ovf),
.clk(clk),
.rst(rst)
);
initial begin
// Initialize Inputs
cin = 0;
din = 0;
first = 0;
last = 0;
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// reset
#5 clk = 0;
rst = 1;
#5 clk = 1;
repeat (15) begin
#5 clk = 0;
rst = 0;
#5 clk = 1;
end
// Test 1
#5 clk = 0;
first = 1;
last = 0;
cin = 262144;
din = 1; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 262144;
din = 10; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 262144;
din = 100; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 262144;
din = 1000; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 262144;
din = 10000; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 1;
cin = 262144;
din = 100000; //
#5 clk = 1;
#5 clk = 0;
first = 1;
last = 0;
cin = 262144;
din = -1; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 262144;
din = -10; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 262144;
din = -100; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 262144;
din = -1000; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 262144;
din = -10000; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 1;
cin = 262144;
din = -100000; //
#5 clk = 1;
#5 clk = 0;
first = 1;
last = 0;
cin = 131072;
din = 1; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 131072;
din = 10; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 131072;
din = 100; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 131072;
din = 1000; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 131072;
din = 10000; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 1;
cin = 131072;
din = 100000; //
#5 clk = 1;
#5 clk = 0;
first = 1;
last = 0;
cin = 65536;
din = -1; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 65536;
din = -10; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 65536;
din = -100; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 65536;
din = -1000; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 0;
cin = 65536;
din = -10000; //
#5 clk = 1;
#5 clk = 0;
first = 0;
last = 1;
cin = 65536;
din = -100000; //
#5 clk = 1;
#5 clk = 0;
first = 1;
last = 1;
cin = 25'h0800000;
din = 18'h10000; // 1/2 x1/2 = 1/4
#5 clk = 1;
#5 clk = 0;
first = 1;
last = 1;
cin = 25'h0FFFFFF;
din = 18'h1FFFF; // 1 x1 = 1
#5 clk = 1;
#5 clk = 0;
first = 1;
last = 1;
cin = 0;
din = 0;
#5 clk = 1;
// clock out results
repeat (16) begin
#5 clk = 0;
first = 0;
last = 0;
#5 clk = 1;
end
end
endmodule
| 6.76066 |
module: main
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_main;
// Inputs
reg Clk;
reg rst;
// Outputs
wire [7:0] data_RED;
wire [7:0] data_BLUE;
wire [7:0] data_GREEN;
wire DISP;
wire TFT_en;
wire DE_clk;
wire clk_lcd;
wire startclk;
wire backlight;
wire de_en,disp_en,led_en,rgb_en,pixel_en,flagh,flagv;
wire [9:0]hcount_reg;
wire[8:0]Vcount_reg;
// Instantiate the Unit Under Test (UUT)
main uut (
.Clk(Clk),
.rst(rst),
.data_RED(data_RED),
.data_BLUE(data_BLUE),
.data_GREEN(data_GREEN),
.DISP(DISP),
.TFT_en(TFT_en),
.DE_clk(DE_clk),
.clk_lcd(clk_lcd),
.startclk(startclk),
.backlight(backlight),
.de_en(de_en),
.disp_en(disp_en),
.led_en(led_en),
.rgb_en(rgb_en),
.pixel_en(pixel_en),
.flagh(flagh),
.flagv(flagv),
.hcount_reg(hcount_reg),
.Vcount_reg(Vcount_reg)
);
initial begin
Clk = 0;
rst = 0;
forever
begin
#10 Clk= ~Clk;
end
end
// Add stimulus here
endmodule
| 7.089523 |
module test_main_ctrl #(
parameter CTRL_ADDR_WIDTH = 28,
parameter MEM_DQ_WIDTH = 16,
parameter MEM_SPACE_AW = 18
) (
output [CTRL_ADDR_WIDTH-1:0] random_rw_addr,
output [3:0] random_axi_id,
output [3:0] random_axi_len,
input clk,
input rst_n,
input ddrc_init_done,
output reg init_start,
input init_done,
output reg write_en,
input write_done_p,
output reg read_en,
input read_done_p
);
wire [127:0] prbs_dout;
wire random_write_en;
localparam E_IDLE = 0;
localparam E_INIT = 1;
localparam E_WR = 2;
localparam E_RD = 3;
localparam E_END = 4;
reg [3:0] state;
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
state <= E_IDLE;
write_en <= 1'b0;
read_en <= 1'b0;
init_start <= 1'b0;
end else begin
case (state)
E_IDLE: begin
if (ddrc_init_done) state <= E_INIT;
else state <= E_IDLE;
end
E_INIT: begin
init_start <= 1'b1;
if (init_done) begin
state <= E_WR;
init_start <= 1'b0;
end
end
E_WR: begin
if (write_done_p) begin
write_en <= 1'b0;
state <= E_END;
end else write_en <= 1'b1;
end
E_RD: begin
if (read_done_p) begin
read_en <= 1'b0;
state <= E_END;
end else read_en <= 1'b1;
end
E_END: begin
if (random_write_en) state <= E_WR;
else state <= E_RD;
end
default: begin
state <= E_IDLE;
end
endcase
end
assign prbs_clk_en = write_done_p | read_done_p;
prbs31_128bit #(
.PRBS_INIT (128'h1234_5678_9abc_def0_8686_2016_0707_336a),
.PRBS_GEN_EN(1'b1)
) I_prbs31_128bit (
.clk (clk),
.rstn (rst_n),
.clk_en(prbs_clk_en),
.cnt_mode (1'b0),
.din (128'd0),
.dout (prbs_dout),
.insert_er(1'b0),
.error ()
);
wire [CTRL_ADDR_WIDTH-1:0] random_rw_addr_mask = {CTRL_ADDR_WIDTH{1'b0}} + {MEM_SPACE_AW{1'b1}};
assign random_rw_addr = {prbs_dout[96+CTRL_ADDR_WIDTH-8:96], 7'd0} & random_rw_addr_mask;
assign random_axi_id = prbs_dout[39:36];
assign random_axi_len = prbs_dout[35:32];
assign random_write_en = prbs_dout[0];
endmodule
| 6.802479 |
module Mux2 (
input [1:0] I,
input S,
output O
);
wire SB_LUT4_inst0_O;
SB_LUT4 #(
.LUT_INIT(16'hCACA)
) SB_LUT4_inst0 (
.I0(I[0]),
.I1(I[1]),
.I2(S),
.I3(1'b0),
.O (SB_LUT4_inst0_O)
);
assign O = SB_LUT4_inst0_O;
endmodule
| 7.615389 |
module Mux2x10 (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire Mux2_inst0_O;
wire Mux2_inst1_O;
wire Mux2_inst2_O;
wire Mux2_inst3_O;
wire Mux2_inst4_O;
wire Mux2_inst5_O;
wire Mux2_inst6_O;
wire Mux2_inst7_O;
wire Mux2_inst8_O;
wire Mux2_inst9_O;
Mux2 Mux2_inst0 (
.I({I1[0], I0[0]}),
.S(S),
.O(Mux2_inst0_O)
);
Mux2 Mux2_inst1 (
.I({I1[1], I0[1]}),
.S(S),
.O(Mux2_inst1_O)
);
Mux2 Mux2_inst2 (
.I({I1[2], I0[2]}),
.S(S),
.O(Mux2_inst2_O)
);
Mux2 Mux2_inst3 (
.I({I1[3], I0[3]}),
.S(S),
.O(Mux2_inst3_O)
);
Mux2 Mux2_inst4 (
.I({I1[4], I0[4]}),
.S(S),
.O(Mux2_inst4_O)
);
Mux2 Mux2_inst5 (
.I({I1[5], I0[5]}),
.S(S),
.O(Mux2_inst5_O)
);
Mux2 Mux2_inst6 (
.I({I1[6], I0[6]}),
.S(S),
.O(Mux2_inst6_O)
);
Mux2 Mux2_inst7 (
.I({I1[7], I0[7]}),
.S(S),
.O(Mux2_inst7_O)
);
Mux2 Mux2_inst8 (
.I({I1[8], I0[8]}),
.S(S),
.O(Mux2_inst8_O)
);
Mux2 Mux2_inst9 (
.I({I1[9], I0[9]}),
.S(S),
.O(Mux2_inst9_O)
);
assign O = {
Mux2_inst9_O,
Mux2_inst8_O,
Mux2_inst7_O,
Mux2_inst6_O,
Mux2_inst5_O,
Mux2_inst4_O,
Mux2_inst3_O,
Mux2_inst2_O,
Mux2_inst1_O,
Mux2_inst0_O
};
endmodule
| 6.548523 |
module Test (
input [9:0] I0,
input [9:0] I1,
input S,
output [9:0] O
);
wire [9:0] my_mux_O;
Mux2x10 my_mux (
.I0(I0),
.I1(I1),
.S (S),
.O (my_mux_O)
);
assign O = my_mux_O;
endmodule
| 7.402791 |
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