code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module test_pipeline_propagation_core;
reg clk;
reg arst;
localparam data_width = 32;
localparam pstage = 3;
initial clk = 1'b0;
always begin
#(`CLOCK_PERIOD / 2) clk = ~clk;
end
initial begin
arst = 1'b1;
#(10.5 * `CLOCK_PERIOD);
arst = 1'b0;
end
reg [data_width-1:0] data_in;
wire [data_width-1:0] data_o;
initial begin
data_in <= 0;
#(11 * `CLOCK_PERIOD);
repeat (10) begin
@(posedge clk);
data_in <= data_in + 1;
end
end
initial begin
$display("TIME\tDATA_IN\tDATA_O");
$monitor("%t\t%x\t%x", $time, data_in, data_o);
end
pipeline_propagation_core #(
.DATA_WIDTH(data_width),
.PSTAGE(pstage)
) u_test (
.clk(clk),
.ce(1'b1),
.arst(arst),
.data_in(data_in),
.data_o(data_o)
);
endmodule
| 6.631713 |
module test_player2 (
CLOCK_50,
KEY,
LEDR,
LEDG
);
input CLOCK_50;
input [3:0] KEY;
output [17:0] LEDR;
output [7:0] LEDG;
wire [27:0] one_hz = 28'b0010111110101111000010000000;
reg [19:0] p1_value = 6'b101110;
wire clock;
rate_divider rate0 (
.clock_in(CLOCK_50),
.clock_out(clock),
.rate(one_hz)
);
player2 player2_0 (
.clock(clock),
.user_input(KEY[0]),
.next_input(KEY[2]),
.done_input(KEY[3]),
.resetn(KEY[1]),
.player1_value(p1_value),
.correct(LEDG[7]),
.q(LEDR)
);
// visual on LEDG
reg [2:0] input_mem;
assign LEDG[2:0] = input_mem;
always @(posedge clock) begin
if (KEY[0]) input_mem <= 0;
else if (input_mem == 3'b111) input_mem <= 1'b1;
else input_mem <= {input_mem[1:0], 1'b1};
end
endmodule
| 6.642622 |
module test_pmod_top (
//switch
input wire [15:0] switch,
//led
output wire [15:0] led,
//pmod
output wire [7:0] Ja,
output wire [7:0] Jb,
output wire [7:0] Jc,
output wire [7:0] Jd
);
assign led = switch;
assign Ja = 8'h80;
assign Jb = switch[15:8];
assign Jc = 8'b0;
assign Jd = switch[7 : 0];
endmodule
| 7.543842 |
module mux2_32 (
D_EXT1,
negative,
Z_ena,
D_negative,
carry,
D_carry,
EXT1_n_c
);
output [0:0] D_EXT1;
input negative;
input Z_ena;
input D_negative;
input carry;
input D_carry;
input EXT1_n_c;
wire [0:0] D_EXT1;
wire D_carry;
wire D_negative;
wire EXT1_n_c;
wire Z_ena;
wire carry;
wire negative;
LUT6 #(
.INIT(64'hFF33CC00B8B8B8B8)
) c (
.I0(negative),
.I1(Z_ena),
.I2(D_negative),
.I3(carry),
.I4(D_carry),
.I5(EXT1_n_c),
.O (D_EXT1)
);
endmodule
| 6.85623 |
module test_ppcm_nexys3 (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// PPCM interfaces
output wire pcm_ce_n,
output wire pcm_rst_n,
output wire pcm_oe_n,
output wire pcm_we_n,
output wire [ADDR_BITS-1:1] pcm_addr,
input wire [15:0] pcm_din,
output wire [15:0] pcm_dout
);
parameter CLK_FREQ = 100, ADDR_BITS = 24;
wire busy, ack;
wire [31:0] dout;
reg [31:0] data_buf;
reg cs_prev;
always @(posedge clk_bus) begin
if (rst) cs_prev <= 0;
else cs_prev <= cs;
end
reg cs_buf;
always @(posedge clk_bus) begin
if (rst) cs_buf <= 0;
else if (cs & ~cs_prev) cs_buf <= 1;
else if (ack) cs_buf <= 0;
end
/*ppcm_core_nexys3 #(
.CLK_FREQ(CLK_FREQ),
.ADDR_BITS(ADDR_BITS)
) PPCM_CORE (
.clk(clk),
.rst(rst),
.cs(~cs_prev & cs),
.addr({14'b0, addr}),
.burst(1'b0),
.dout(dout),
.busy(busy),
.ack(ack),
.pcm_ce_n(pcm_ce_n),
.pcm_rst_n(pcm_rst_n),
.pcm_oe_n(pcm_oe_n),
.pcm_we_n(pcm_we_n),
.pcm_addr(pcm_addr),
.pcm_din(pcm_din),
.pcm_dout(pcm_dout)
);*/
wb_ppcm_nexys3 #(
.CLK_FREQ(CLK_FREQ),
.ADDR_BITS(ADDR_BITS),
.HIGH_ADDR(0),
.BUF_ADDR_BITS(4)
) WB_PPCM (
.clk(clk),
.rst(rst),
.pcm_busy(busy),
.pcm_ce_n(pcm_ce_n),
.pcm_rst_n(pcm_rst_n),
.pcm_oe_n(pcm_oe_n),
.pcm_we_n(pcm_we_n),
.pcm_addr(pcm_addr),
.pcm_din(pcm_din),
.pcm_dout(pcm_dout),
.wbs_clk_i(clk_bus),
.wbs_cyc_i(cs_buf),
.wbs_stb_i(cs_buf),
.wbs_addr_i({22'b0, addr}),
.wbs_cti_i(3'b0),
.wbs_bte_i(2'b0),
.wbs_sel_i(4'b1111),
.wbs_we_i(1'b0),
.wbs_data_i(32'b0),
.wbs_data_o(dout),
.wbs_ack_o(ack)
);
always @(posedge clk_bus) begin
if (rst) data_buf <= 0;
else if (ack) data_buf <= dout;
end
assign data = data_buf;
assign state = {busy, pcm_ce_n, pcm_rst_n, pcm_oe_n, pcm_we_n, 2'b0, ack};
endmodule
| 8.436736 |
module test_priority_encoder;
// Parameters
localparam WIDTH = 32;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_unencoded = 0;
// Outputs
wire output_valid;
wire [$clog2(WIDTH)-1:0] output_encoded;
wire [WIDTH-1:0] output_unencoded;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, input_unencoded);
$to_myhdl(output_valid, output_encoded, output_unencoded);
// dump file
$dumpfile("test_priority_encoder.lxt");
$dumpvars(0, test_priority_encoder);
end
priority_encoder #(
.WIDTH(WIDTH)
) UUT (
.input_unencoded(input_unencoded),
.output_valid(output_valid),
.output_encoded(output_encoded),
.output_unencoded(output_unencoded)
);
endmodule
| 7.096955 |
module alu (
out,
Data1,
Data2,
Select
);
input [7:0] Data1, Data2;
input [2:0] Select;
output reg [7:0] out;
always @(Data1, Data2, Select) begin
case (Select)
3'b000: out <= Data1;
3'b001: out <= Data1 + Data2;
3'b010: out <= Data1 & Data2;
3'b011: out <= Data1 | Data2;
endcase
end
endmodule
| 7.812586 |
module CU (
OUT1addr,
OUT2addr,
INaddr,
immediate,
Select,
imm_signal,
comp_signal,
instruction
);
input [31:0] instruction;
output reg [7:0] immediate;
output reg imm_signal;
output reg [2:0] Select;
output reg [2:0] OUT1addr;
output reg [2:0] OUT2addr;
output reg [2:0] INaddr;
output reg comp_signal;
always @(instruction) begin
immediate = instruction[7:0];
//opcode=instruction[31:24];
Select = instruction[26:24];
INaddr = instruction[18:16];
OUT2addr = instruction[2:0];
OUT1addr = instruction[10:8];
imm_signal = 1'b0;
comp_signal = 1'b0;
case (instruction[31:24])
8'b00001000: imm_signal = 1'b1;
8'b00001001: comp_signal = 1'b1;
default: ;
endcase
end
endmodule
| 7.902187 |
module mux (
out,
select,
input1,
input2
);
input select;
input [7:0] input1, input2;
output reg [7:0] out;
always @* begin
if (select == 1) out = input1;
else out = input2;
end
endmodule
| 7.812393 |
module compliment (
out,
in
);
input [7:0] in;
output [7:0] out;
reg [7:0] comp = 8'b11111111;
assign out = (comp - in) + 8'b00000001;
endmodule
| 6.612524 |
module regInstructions (
instruction,
clk,
Read_Addr
);
input clk;
input [2:0] Read_Addr;
output reg [31:0] instruction;
reg [31:0] addr1 = 32'b00001000000001000000000011111111; // loadi 4, X, 0xFF
reg [31:0] addr2 = 32'b00001000000001100000000010101010; // loadi 6, X, 0xAA
reg [31:0] addr3 = 32'b00001000000000110000000010111011; // loadi 3, X, 0xBB
reg [31:0] addr4 = 32'b00000001000001010000011000000011; // add 5, 6, 3
reg [31:0] addr5 = 32'b00000010000000010000010000000101; // and 1, 4, 5
reg [31:0] addr6 = 32'b00000011000000100000000100000110; // or 2, 1, 6
reg [31:0] addr7 = 32'b00000000000001110000000000000010; // mov 7, x, 2
reg [31:0] addr8 = 32'b00001001000001000000011100000011; // sub 4, 7, 3
always @(negedge clk) begin
case (Read_Addr)
3'd0: instruction = addr1;
3'd1: instruction = addr2;
3'd2: instruction = addr3;
3'd3: instruction = addr4;
3'd4: instruction = addr5;
3'd5: instruction = addr6;
3'd6: instruction = addr7;
3'd7: instruction = addr8;
default: ;
endcase
end
endmodule
| 7.583668 |
module test_Processing_Unit ();
parameter word_size = 10;
parameter data_size = 8;
parameter op_size = 4;
parameter Sel1_size = 3;
parameter Sel2_size = 3;
reg [6:0] address_decoded;
reg [7:0] constant_decoded;
reg [word_size-1:0] mem_word;
reg Load_R0, Load_R1, Load_R2, Load_R3, Load_PC, Inc_PC;
reg [Sel1_size-1:0] Sel_Bus_1a_Mux, Sel_Bus_1b_Mux;
reg [Sel2_size-1:0] Sel_Bus_2_Mux;
reg Load_IR, Load_Add_R, Load_Reg_Z;
reg clk, rst;
wire [word_size-1:0] instruction;
wire [6:0] address;
wire [data_size-1:0] Bus_1a, Bus_1b;
wire Zflag;
wire [data_size-1:0] R0_out, R1_out, R2_out, R3_out, PC_count;
initial begin
clk = 0;
end
always #5 clk = ~clk;
//begin test signal
wire [7:0] r0 = process1.R0.data_out[7:0];
wire [7:0] r1 = process1.R1.data_out[7:0];
wire [7:0] r2 = process1.R2.data_out[7:0];
wire [7:0] r3 = process1.R3.data_out[7:0];
wire [9:0] bus2 = process1.Bus_2[9:0];
//end test signal
Processing_Unit process1 (
instruction,
Zflag,
address,
address_decoded,
constant_decoded,
Bus_1a,
Bus_1b,
mem_word,
Load_R0,
Load_R1,
Load_R2,
Load_R3,
Load_PC,
Inc_PC,
Sel_Bus_1a_Mux,
Sel_Bus_1b_Mux,
Load_IR,
Load_Add_R,
Load_Reg_Z,
Sel_Bus_2_Mux,
clk,
rst,
R0_out,
R1_out,
R2_out,
R3_out,
PC_count
);
initial begin
address_decoded[6:0] = 0;
constant_decoded[7:0] = 0;
mem_word[word_size-1:0] = 0;
Load_R0 = 0;
Load_R1 = 0;
Load_R2 = 0;
Load_R3 = 0;
Load_PC = 0;
Inc_PC = 0;
Sel_Bus_1a_Mux[2:0] = 0;
Sel_Bus_1b_Mux[2:0] = 0;
Sel_Bus_2_Mux[2:0] = 0;
Load_IR = 0;
Load_Add_R = 0;
Load_Reg_Z = 0;
//r0 = r1 + r2 =>> r2 = r1 + r2
#10 begin
mem_word[9:0] = 10'b0000100110;
process1.R0.data_out = 0;
process1.R1.data_out = 1;
process1.R2.data_out = 2;
process1.R3.data_out = 3;
Sel_Bus_1a_Mux[2:0] = 4; //sel_PCa = 1
Sel_Bus_2_Mux[2:0] = 1;
Load_Add_R = 1;
end
// S_fet2
#10 begin
Sel_Bus_2_Mux[2:0] = 2; //Sel_Mem = 1;
Load_IR = 1;
Inc_PC = 1;
end
//S_dec
#10 begin
Sel_Bus_1a_Mux[2:0] = 1; //Sel_R1a = 1;
Sel_Bus_1b_Mux[2:0] = 2; //Sel_R2b = 1;
end
//ex1
#10 begin
Load_Reg_Z = 1;
Sel_Bus_2_Mux[2:0] = 0; //Sel_ALU = 1;
Load_R0 = 1;
end
//r0 = r3-r1 =>> r0 = 3-1 = 2
end
endmodule
| 6.763534 |
module TOP;
//ALU inputs
reg a, b;
wire p;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 0;
b = 0;
#`cycle //1
if(p != (a | b))
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 1;
b = 0;
#`cycle //3
if(p != (a | b))
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 0;
b = 1;
#`cycle //5
if(p != (a | b))
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 1;
b = 1;
#`cycle //7
if(p != (a | b))
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("propagate1.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(error)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, propagate1 = %x",
$time, a, b, p);
propagate1 propagate1_test(p, a, b);
endmodule
| 7.259416 |
module TOP;
//ALU inputs
reg [31:0] a, b;
wire [31:0] p;
reg error;
reg error_free;
initial
begin
error_free = 1;
error = 0;
a = 32'hffffffff;
b = 32'h00000000;
#`cycle //1
if(p != (a | b))
begin
error_free = 0;
error = 1;
end
#`error_time //2
error = 0;
a = 32'ha47ba47b;
b = 32'h5c915c91;
#`cycle //3
if(p != (a | b))
begin
error_free = 0;
error = 1;
end
#`error_time //4
error = 0;
a = 32'hbcdabcda;
b = 32'h79867986;
#`cycle //5
if(p != (a | b))
begin
error_free = 0;
error = 1;
end
#`error_time //6
error = 0;
a = 32'h96579657;
b = 32'h34563456;
#`cycle //7
if(p != (a | b))
begin
error_free = 0;
error = 1;
end
if(error_free == 1)
$display("\n*** WOOT! TEST PASS! ***\n");
end
initial `runtime $finish;
// Dump all waveforms to d_latch.dump.vpd
initial
begin
//$dumpfile ("d_latch.dump");
//$dumpvars (0, TOP);
$vcdplusfile("propagate32.dump.vpd");
$vcdpluson(0, TOP);
end // initial begin
always @(error)
if(error == 1)
$strobe ("time: %0d found error at: a = %x, b = %x, propagate1 = %x, correct propagate1 = %x",
$time, a, b, p, (a | b));
propagate32 propagate32_test(p, a, b);
endmodule
| 7.259416 |
module Test_Proyect;
// Entradas
reg Clock_Nexys;
reg Reset;
reg reset_Clck;
reg data_ADC;
reg start;
reg [11:0] Entrada_referencia;
// Salidas
wire CS;
wire Clock_Muestreo;
wire [3:0] data_basura;
wire pwm_out;
wire [17:0] IPD;
// Unit Under Test (UUT)
Servo_Top uut (
.Clock_Nexys(Clock_Nexys),
.Reset(Reset),
.reset_Clck(reset_Clck),
.data_ADC(data_ADC),
.start(start),
.Entrada_referencia(Entrada_referencia),
.CS(CS),
.Clock_Muestreo(Clock_Muestreo),
.data_basura(data_basura),
.pwm_out(pwm_out),
.IPD(IPD)
);
integer I_PD, k;
reg [11:0] mem1[90:0];
reg [11:0]mem2[90:0];//Se genera una memoria para abir el fichero .txt, donde la primera parametrizacion (los primeros parentesis cuadrados
//leyendo de izquierda a derecha) son para determinar el tamao de los bits en el arreglo, mientras que los segundos es para
//indicar cuantos datos existen en el fichero .txt
reg [11:0] VariableAux;
initial
forever
#20 Clock_Nexys = ~Clock_Nexys; //Generacion de senal de reloj principal para simulacion
initial begin
// Initialize Inputs
Clock_Nexys = 0;
Reset = 0;
reset_Clck = 0;
data_ADC = 0;
start = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Initialize Inputs
Clock_Nexys = 0;
Reset = 1;
reset_Clck = 1;
data_ADC = 0;
start = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Initialize Inputs
Reset = 0;
reset_Clck = 0;
data_ADC = 0;
start = 0;
// Wait 100 ns for global reset to finish
#100;
I_PD = $fopen("Salida_I_PD.txt"); // Abre fichero para escritura
$readmemb("Referencia_Binario.txt",
mem1); // Carga en mem los datos del fichero Referencia_Binario.txt para lectura
$readmemb("y_Binario.txt",
mem2); // Carga en mem2 los datos del fichero y_Binario.txt para lectura
for (
k = 0; k < 89; k = k + 1
) // Ciclo for para recorrer el fichero cargado
begin
//
Entrada_referencia = mem1[k];
VariableAux = mem2[k];
@(negedge Clock_Muestreo) start = 1;
repeat (4)
@(posedge Clock_Muestreo); // Se esperan 4 ciclos de reloj, esto equivale a los primeros 4 datos del ADC que son para estabilizar
// la senal
@(negedge Clock_Muestreo) data_ADC = VariableAux[11]; // bit numero 1 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[10]; // bit numero 2 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[9]; // bit numero 3 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[8]; // bit numero 4 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[7]; // bit numero 5 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[6]; // bit numero 6 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[5]; // bit numero 7 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[4]; // bit numero 8 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[3]; // bit numero 9 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[2]; // bit numero 10 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[1]; // bit numero 11 del dato
@(negedge Clock_Muestreo) data_ADC = VariableAux[0]; // bit numero 12 del dato
start = 0;
repeat (18) @(posedge Clock_Muestreo);
$fdisplayb(I_PD, IPD);
end
$fclose(I_PD); //Se cierra el fichero Salida_I_PD.txt
$stop;
end
endmodule
| 7.763372 |
module test_ps2 (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] cmd,
output wire [31:0] data,
output wire [7:0] state,
// PS2 interfaces
inout wire ps2_clk,
inout wire ps2_dat
);
parameter CLK_FREQ = 100;
wire [ 7:0] dout;
reg [31:0] data_buf;
wire tx_busy, rx_busy;
wire tx_ack, rx_ack;
wire tx_err, rx_err;
reg cs_prev;
always @(posedge clk) begin
if (rst) cs_prev <= 0;
else cs_prev <= cs;
end
reg cs_buf;
always @(posedge clk) begin
if (rst) cs_buf <= 0;
else if (cs & ~cs_prev) cs_buf <= 1;
else if (tx_ack || rx_ack || tx_err || rx_err) cs_buf <= 0;
end
ps2_host #(
.CLK_FREQ(CLK_FREQ)
) PS2_HOST (
.clk(clk),
.rst(rst),
.tx_en(cs & we),
.tx_data(cmd),
.rx_en(cs),
.rx_data(dout),
.tx_busy(tx_busy),
.rx_busy(rx_busy),
.tx_ack(tx_ack),
.rx_ack(rx_ack),
.tx_err(tx_err),
.rx_err(rx_err),
.ps2_clk(ps2_clk),
.ps2_dat(ps2_dat)
);
always @(posedge clk) begin
if (rst) data_buf <= 0;
else if (rx_ack || rx_err) data_buf <= {data_buf[23:0], dout};
end
reg tx_err_buf, rx_err_buf;
always @(posedge clk) begin
if (rst) begin
tx_err_buf <= 0;
rx_err_buf <= 0;
end else begin
tx_err_buf <= tx_err_buf | tx_err;
rx_err_buf <= rx_err_buf | rx_err;
end
end
assign data = data_buf;
assign state = {tx_busy, rx_busy, 2'b0, tx_err_buf, rx_err_buf, tx_ack, rx_ack};
endmodule
| 7.837163 |
module test_ps2_keyboard (
/* PS/2 inputs */
PS2_CLK,
PS2_DAT,
HEX0,
HEX1
);
input PS2_CLK;
input PS2_DAT;
output [6:0] HEX0, HEX1;
wire [7:0] data_out;
wire data_complete;
reg [3:0] hex0_val, hex1_val;
ps2_keyboard keyboard_input (
.ps2_clock(PS2_CLK),
.ps2_data(PS2_DAT),
.data_out(data_out),
.data_complete(data_complete)
);
hex_decoder hex0 (
.hex_digit(hex0_val),
.segments (HEX0)
);
hex_decoder hex1 (
.hex_digit(hex1_val),
.segments (HEX1)
);
always @(posedge data_complete) begin
hex0_val = data_out[3:0];
hex1_val = data_out[7:4];
end
endmodule
| 7.581791 |
module test_psram_nexys3 (
input wire clk,
input wire clk_bus,
input wire rst,
input wire cs,
input wire we,
input wire [7:0] addr,
output wire [31:0] data,
output wire [7:0] state,
// PSRAM interfaces
output wire ram_ce_n,
output wire ram_clk,
output wire ram_oe_n,
output wire ram_we_n,
output wire ram_adv_n,
output wire ram_cre,
output wire ram_lb_n,
output wire ram_ub_n,
input wire ram_wait,
output wire [ADDR_BITS-1:1] ram_addr,
input wire [15:0] ram_din,
output wire [15:0] ram_dout
);
parameter CLK_FREQ = 100, ADDR_BITS = 24;
wire busy, ack;
wire [31:0] dout;
reg [31:0] data_buf;
reg cs_prev;
always @(posedge clk_bus) begin
if (rst) cs_prev <= 0;
else cs_prev <= cs;
end
reg cs_buf;
always @(posedge clk_bus) begin
if (rst) cs_buf <= 0;
else if (cs & ~cs_prev) cs_buf <= 1;
else if (ack) cs_buf <= 0;
end
/*psram_core_nexys3 #(
.CLK_FREQ(CLK_FREQ),
.ADDR_BITS(ADDR_BITS)
) PSRAM_CORE (
.clk(clk),
.rst(rst),
.cs(cs & ~cs_prev),
.we(we),
.addr({14'b0, addr}),
.sel(4'b1111),
.burst(1'b0),
.din(32'h12345678),
.dout(dout),
.busy(busy),
.ack(ack),
.ram_clk(ram_clk),
.ram_ce_n(ram_ce_n),
.ram_oe_n(ram_oe_n),
.ram_we_n(ram_we_n),
.ram_adv_n(ram_adv_n),
.ram_cre(ram_cre),
.ram_lb_n(ram_lb_n),
.ram_ub_n(ram_ub_n),
.ram_wait(ram_wait),
.ram_addr(ram_addr),
.ram_din(ram_din),
.ram_dout(ram_dout)
);*/
wb_psram_nexys3 #(
.CLK_FREQ(CLK_FREQ),
.ADDR_BITS(ADDR_BITS),
.HIGH_ADDR(0),
.BUF_ADDR_BITS(4)
) WB_PSRAM (
.clk(clk),
.rst(rst),
.ram_busy(busy),
.ram_clk(ram_clk),
.ram_ce_n(ram_ce_n),
.ram_oe_n(ram_oe_n),
.ram_we_n(ram_we_n),
.ram_adv_n(ram_adv_n),
.ram_cre(ram_cre),
.ram_lb_n(ram_lb_n),
.ram_ub_n(ram_ub_n),
.ram_wait(ram_wait),
.ram_addr(ram_addr),
.ram_din(ram_din),
.ram_dout(ram_dout),
.wbs_clk_i(clk_bus),
.wbs_cyc_i(cs_buf),
.wbs_stb_i(cs_buf),
.wbs_addr_i({22'b0, addr}),
.wbs_cti_i(3'b0),
.wbs_bte_i(2'b0),
.wbs_sel_i(4'b1111),
.wbs_we_i(we),
.wbs_data_i(32'h12345678),
.wbs_data_o(dout),
.wbs_ack_o(ack)
);
always @(posedge clk_bus) begin
if (rst) data_buf <= 0;
else if (ack) data_buf <= dout;
end
assign data = data_buf;
assign state = {busy, ram_ce_n, ram_oe_n, ram_we_n, ram_adv_n, ram_wait, 1'b0, ack};
endmodule
| 8.926065 |
module test_ptp_clock (
input wire clk,
input wire rst,
inout wire [95:0] ts_96,
inout wire [63:0] ts_64,
inout wire ts_step,
inout wire pps
);
endmodule
| 7.202445 |
module test_ptp_clock_cdc_64;
// Parameters
parameter TS_WIDTH = 64;
parameter NS_WIDTH = 4;
parameter FNS_WIDTH = 16;
parameter INPUT_PERIOD_NS = 4'h6;
parameter INPUT_PERIOD_FNS = 16'h6666;
parameter OUTPUT_PERIOD_NS = 4'h6;
parameter OUTPUT_PERIOD_FNS = 16'h6666;
parameter USE_SAMPLE_CLOCK = 1;
parameter LOG_FIFO_DEPTH = 3;
parameter LOG_RATE = 3;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_clk = 0;
reg input_rst = 0;
reg output_clk = 0;
reg output_rst = 0;
reg sample_clk = 0;
reg [TS_WIDTH-1:0] input_ts = 0;
// Outputs
wire [TS_WIDTH-1:0] output_ts;
wire output_ts_step;
wire output_pps;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, input_clk, input_rst, output_clk, output_rst, sample_clk,
input_ts);
$to_myhdl(output_ts, output_ts_step, output_pps);
// dump file
$dumpfile("test_ptp_clock_cdc_64.lxt");
$dumpvars(0, test_ptp_clock_cdc_64);
end
ptp_clock_cdc #(
.TS_WIDTH(TS_WIDTH),
.NS_WIDTH(NS_WIDTH),
.FNS_WIDTH(FNS_WIDTH),
.INPUT_PERIOD_NS(INPUT_PERIOD_NS),
.INPUT_PERIOD_FNS(INPUT_PERIOD_FNS),
.OUTPUT_PERIOD_NS(OUTPUT_PERIOD_NS),
.OUTPUT_PERIOD_FNS(OUTPUT_PERIOD_FNS),
.USE_SAMPLE_CLOCK(USE_SAMPLE_CLOCK),
.LOG_FIFO_DEPTH(LOG_FIFO_DEPTH),
.LOG_RATE(LOG_RATE)
) UUT (
.input_clk(input_clk),
.input_rst(input_rst),
.output_clk(output_clk),
.output_rst(output_rst),
.sample_clk(sample_clk),
.input_ts(input_ts),
.output_ts(output_ts),
.output_ts_step(output_ts_step),
.output_pps(output_pps)
);
endmodule
| 7.202445 |
module test_ptp_clock_cdc_96;
// Parameters
parameter TS_WIDTH = 96;
parameter NS_WIDTH = 4;
parameter FNS_WIDTH = 16;
parameter INPUT_PERIOD_NS = 4'h6;
parameter INPUT_PERIOD_FNS = 16'h6666;
parameter OUTPUT_PERIOD_NS = 4'h6;
parameter OUTPUT_PERIOD_FNS = 16'h6666;
parameter USE_SAMPLE_CLOCK = 1;
parameter LOG_FIFO_DEPTH = 3;
parameter LOG_RATE = 3;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_clk = 0;
reg input_rst = 0;
reg output_clk = 0;
reg output_rst = 0;
reg sample_clk = 0;
reg [TS_WIDTH-1:0] input_ts = 0;
// Outputs
wire [TS_WIDTH-1:0] output_ts;
wire output_ts_step;
wire output_pps;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, input_clk, input_rst, output_clk, output_rst, sample_clk,
input_ts);
$to_myhdl(output_ts, output_ts_step, output_pps);
// dump file
$dumpfile("test_ptp_clock_cdc_96.lxt");
$dumpvars(0, test_ptp_clock_cdc_96);
end
ptp_clock_cdc #(
.TS_WIDTH(TS_WIDTH),
.NS_WIDTH(NS_WIDTH),
.FNS_WIDTH(FNS_WIDTH),
.INPUT_PERIOD_NS(INPUT_PERIOD_NS),
.INPUT_PERIOD_FNS(INPUT_PERIOD_FNS),
.OUTPUT_PERIOD_NS(OUTPUT_PERIOD_NS),
.OUTPUT_PERIOD_FNS(OUTPUT_PERIOD_FNS),
.USE_SAMPLE_CLOCK(USE_SAMPLE_CLOCK),
.LOG_FIFO_DEPTH(LOG_FIFO_DEPTH),
.LOG_RATE(LOG_RATE)
) UUT (
.input_clk(input_clk),
.input_rst(input_rst),
.output_clk(output_clk),
.output_rst(output_rst),
.sample_clk(sample_clk),
.input_ts(input_ts),
.output_ts(output_ts),
.output_ts_step(output_ts_step),
.output_pps(output_pps)
);
endmodule
| 7.202445 |
module test_ptp_clock_sim_time (
input wire clk,
inout wire [95:0] ts_96,
inout wire [63:0] ts_64,
inout wire pps
);
endmodule
| 7.202445 |
module test_ptp_perout;
// Parameters
parameter FNS_ENABLE = 1;
parameter OUT_START_S = 48'h0;
parameter OUT_START_NS = 30'h0;
parameter OUT_START_FNS = 16'h0000;
parameter OUT_PERIOD_S = 48'd1;
parameter OUT_PERIOD_NS = 30'd0;
parameter OUT_PERIOD_FNS = 16'h0000;
parameter OUT_WIDTH_S = 48'h0;
parameter OUT_WIDTH_NS = 30'd1000;
parameter OUT_WIDTH_FNS = 16'h0000;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [95:0] input_ts_96 = 0;
reg input_ts_step = 0;
reg enable = 0;
reg [95:0] input_start = 0;
reg input_start_valid = 0;
reg [95:0] input_period = 0;
reg input_period_valid = 0;
reg [95:0] input_width = 0;
reg input_width_valid = 0;
// Outputs
wire locked;
wire error;
wire output_pulse;
initial begin
// myhdl integration
$from_myhdl(clk, rst, current_test, input_ts_96, input_ts_step, enable, input_start,
input_start_valid, input_period, input_period_valid, input_width,
input_width_valid);
$to_myhdl(locked, error, output_pulse);
// dump file
$dumpfile("test_ptp_perout.lxt");
$dumpvars(0, test_ptp_perout);
end
ptp_perout #(
.FNS_ENABLE(FNS_ENABLE),
.OUT_START_S(OUT_START_S),
.OUT_START_NS(OUT_START_NS),
.OUT_START_FNS(OUT_START_FNS),
.OUT_PERIOD_S(OUT_PERIOD_S),
.OUT_PERIOD_NS(OUT_PERIOD_NS),
.OUT_PERIOD_FNS(OUT_PERIOD_FNS),
.OUT_WIDTH_S(OUT_WIDTH_S),
.OUT_WIDTH_NS(OUT_WIDTH_NS),
.OUT_WIDTH_FNS(OUT_WIDTH_FNS)
) UUT (
.clk(clk),
.rst(rst),
.input_ts_96(input_ts_96),
.input_ts_step(input_ts_step),
.enable(enable),
.input_start(input_start),
.input_start_valid(input_start_valid),
.input_period(input_period),
.input_period_valid(input_period_valid),
.input_width(input_width),
.input_width_valid(input_width_valid),
.locked(locked),
.error(error),
.output_pulse(output_pulse)
);
endmodule
| 7.793635 |
module pulse_detect_tb ();
reg clk_fast;
reg clk_slow;
reg rst_n;
reg data_in;
wire dataout;
pulse_detect dut (
.clk_fast(clk_fast),
.clk_slow(clk_slow),
.rst_n(rst_n),
.data_in(data_in),
.dataout(dataout)
);
initial begin
clk_fast = 0;
clk_slow = 0;
rst_n = 0;
data_in = 0;
#10 rst_n = 1;
end
// generate clock
always begin
#5 clk_fast = ~clk_fast;
end
always begin
#50 clk_slow = ~clk_slow;
end
// apply input pulses
initial begin
#60 data_in = 1;
#10 data_in = 0;
#300;
end
always @(posedge clk_slow) begin
$monitor("data_in = %b, dataout = %b", data_in, dataout);
end
endmodule
| 6.636089 |
module Test_PulseCapture;
reg success_flag;
reg clk, rst;
reg oe, clr;
reg ext_pulse;
reg trigger;
reg int_clr;
wire [31:0] data;
wire int;
integer i;
pulseCapture U0 (
.clk(clk),
.rst(rst),
.oe(oe), // output enable
.clr(clr), // clear
.trigger(trigger), // start a capture
.ext_pulse(ext_pulse), // external pulse signal
.int_clr(int_clr), // interrupt flag clear signal
.int(int), // interrupt flag when capture event occurs
.data(data)
);
task STROBE_TRIGGER; // task definition starts here
begin
trigger = 0;
#1000
trigger = 1;
CLOCK(1);
#1000
trigger = 0;
end
endtask
task CHECK_OUTPUT;
input [31:0] value;
begin
oe = 1;
#1000
if(data != value)
begin
success_flag = 0;
$display("!!ERROR!! @ %d 0x%X !== 0x%X", $time, data, value);
end
#1
oe = 0;
end
endtask;
task CHECK_INTERRUPT;
input bit_value;
begin
#1
if(int != bit_value)
begin
success_flag = 0;
$display("!!ERROR!! @ %d INTERRUPT FLAG %d !== %d", $time, int, bit_value);
end
#1
oe = 0;
end
endtask;
task CLOCK;
input [31:0] count;
integer k;
begin
for (k=0; k < count; k = k+1)
begin
#5
clk = 1;
#5
clk = 0;
end
end
endtask
initial
begin
success_flag = 1;
rst = 0;
clk = 0;
oe = 0;
trigger = 0;
#5
rst = 1;
#5
rst = 0;
#5
ext_pulse = 0;
STROBE_TRIGGER;
ext_pulse = 1;
CLOCK(1000);
ext_pulse = 0;
CLOCK(1);
CHECK_OUTPUT(1000);
CHECK_INTERRUPT(1);
CLOCK(1000);
ext_pulse = 0;
STROBE_TRIGGER;
CHECK_INTERRUPT(0);
ext_pulse = 1;
CLOCK(2000);
CHECK_INTERRUPT(0);
CLOCK(5000);
ext_pulse = 0;
CLOCK(1);
CHECK_OUTPUT(7000);
CHECK_INTERRUPT(1);
// Print out Success/Failure message
if (success_flag == 0) begin
$display("*FAILED* TEST!");
end
else begin
$display("**PASSED** TEST!");
end
#10 $stop;
#5 $finish;
end
endmodule
| 7.006226 |
module test_pwm_generator;
// pwm_generator module testbench
`timescale 1ns/1ns
/*
* Tested:
* Basic functionality
*
* To test:
* Mid-period input value change
* 0 input value
* >250 input value
*/
reg [7:0] m_1_rate, m_2_rate, m_3_rate, m_4_rate;
wire m_1_pwm, m_2_pwm, m_3_pwm, m_4_pwm;
reg rst, clk;
// TODO: Fix these tests because the parameters don't match up
pwm_generator
#(.INPUT_WIDTH(8),
.CLK_CONVERSION_HIGH(2),
.CLK_CONVERSION_LOW(4))
pwm_dut
(.motor_1_pwm(m_1_pwm),
.motor_2_pwm(m_2_pwm),
.motor_3_pwm(m_3_pwm),
.motor_4_pwm(m_4_pwm),
.motor_1_rate(m_1_rate),
.motor_2_rate(m_2_rate),
.motor_3_rate(m_3_rate),
.motor_4_rate(m_4_rate),
.rst(rst),
.sys_clk(clk));
initial begin
m_1_rate <= 0;
m_2_rate <= 0;
m_3_rate <= 0;
m_4_rate <= 0;
end
initial begin
clk <= 0;
forever begin
#1 clk <= ~clk;
end
end
initial begin
repeat (2) @(posedge clk);
rst <= 1'b0;
m_1_rate <= 8'b00011110;
repeat (2) @(posedge clk);
rst <= 1'b1;
repeat (100) @(posedge clk);
m_2_rate <= 8'b01010101;
repeat (160000) @(posedge clk);
$finish;
end
endmodule
| 6.640256 |
module test_pwm_reader;
localparam SUCCESS = 1'b0;
localparam FAIL = 1'b1;
localparam [10:0] INITIAL_PULSE_HIGH_US = 1500;
wire sys_clk;
wire us_clk;
wire [10:0] pwm_pulse_length_us;
reg pwm = 0;
reg resetn = 1;
reg result = SUCCESS;
defparam OSCH_inst.NOM_FREQ = "38.00";
OSCH OSCH_inst (
.STDBY(1'b0),
.OSC(sys_clk),
.SEDSTDBY()
);
us_clk us_clk_divider (
.us_clk (us_clk),
.sys_clk(sys_clk),
.resetn (1)
); // TODO: Change this to the top level reset signal (.resetn(resetn))
pwm_reader DUT (
.pwm_pulse_length_us(pwm_pulse_length_us),
.pwm(pwm),
.us_clk(us_clk),
.resetn(resetn)
);
initial begin
// Test 1: Test initial reset
resetn = 0;
#5000;
if (pwm_pulse_length_us != INITIAL_PULSE_HIGH_US) begin
result = FAIL;
display_fail(resetn, pwm_pulse_length_us);
#10 $finish;
end
// Test 2: Make sure that if we don't see any signal (constant 0 pwm) we output the default value
#10 resetn = 1;
#5000;
if (pwm_pulse_length_us != INITIAL_PULSE_HIGH_US) begin
result = FAIL;
display_fail(resetn, pwm_pulse_length_us);
#10 $finish;
end
// Test 3: Staying high for only 900us (1ms is min) should output the minimum pwm_pulse_length_us value
#1000 pwm = 1;
#900000 pwm = 0;
#5000; // wait ~5 clock cycles to check the result
if (pwm_pulse_length_us != `MIN_PWM_TIME_HIGH_US) begin
result = FAIL;
display_fail(resetn, pwm_pulse_length_us);
#10 $finish;
end
// Test 4: Staying high for over 2000us should output 2000us
#200000
pwm = 1; // Stay at 0 for a while before raising to increase readability in the waveform
#2100000 pwm = 0;
#5000;
if (pwm_pulse_length_us != 2000) begin
result = FAIL;
display_fail(resetn, pwm_pulse_length_us);
#10 $finish;
end
// Test 5: Staying high for around 1500us should output a time with +/- 5us of 1500us
#200000
pwm = 1; // Stay at 0 for a while before raising to increase readability in the waveform
#1500000 pwm = 0;
#5000;
if (pwm_pulse_length_us <= 1450 || pwm_pulse_length_us >= 1550) begin
result = FAIL;
display_fail(resetn, pwm_pulse_length_us);
#10 $finish;
end
// Test 6: Staying high for over 800us should output the initial pwm_pulse_length_us value
#200000
pwm = 1; // Stay at 0 for a while before raising to increase readability in the waveform
#800000 pwm = 0;
#5000;
if (pwm_pulse_length_us != 1000) begin
result = FAIL;
display_fail(resetn, pwm_pulse_length_us);
#10 $finish;
end
if (result == SUCCESS) display_success();
#10 $finish;
end
task display_fail(input result_in, input resetn, input [10:0] pwm_pulse_length_us);
begin
#1 $display("########################################################################");
#1 $display("########################################################################");
#1
$display(
"########## TEST FAILED: resetn=%d pwm_pulse_length_us=%d ##########",
resetn,
pwm_pulse_length_us
);
#1 $display("########################################################################");
#1 $display("########################################################################");
end
endtask
task display_success();
begin
#1 $display("########################################################################");
#1 $display("########################################################################");
#1 $display("########################### ALL TESTS PASSED ###########################");
#1 $display("########################################################################");
#1 $display("########################################################################");
end
endtask
endmodule
| 7.567604 |
module test_ram32x20(
/* clock input */
CLOCK_50,
/* inputs */
KEY,
SW,
LEDR,
);
input CLOCK_50;
input [17:0] SW;
input [2:0] KEY;
output [17:0] LEDR;
wire [3:0] data_out;
reg [4:0] counter;
ram32x20 ram0(
.data(SW[16:0]),
.address(counter),
.wren(SW[17]),
.clock(KEY[0]),
.q(data_out)
);
always @(negedge KEY[0]) begin
if (!KEY[1])
counter <= 0;
else
counter <= counter + 1'b1;
end
assign LEDR = data_out;
endmodule
| 6.810588 |
module test_ram_256;
reg [31:0] DataIn; //Las entradas del módulo deben ser tipo reg
reg [7:0] Address;
wire [31:0] DataOut;
wire MFC;
reg RW, Enable;
reg [1:0] DataSize;
reg [2:0] counter;
parameter sim_time = 15;
ram_256 ram_module (
DataOut,
MFC,
Enable,
RW,
Address,
DataIn,
DataSize
);
initial #sim_time $finish; // Especifica cuando termina simulación
initial begin
counter = 0;
DataIn = 0;
DataSize = 0;
RW = 0;
Enable = 0;
repeat (8) #2 counter = counter + 1;
end
always @(counter) begin
case (counter)
3'd0: begin
//Case ~Enable Write
Enable = 1'b0;
RW = 1'b0;
Address = 8'h00;
DataSize = 2'b00;
DataIn = 32'hFFFFFFFF;
end
3'd1: begin
//Case ~Enable Read
Enable = 1'b0;
RW = 1'b1;
Address = 8'h00;
DataSize = 2'b00;
end
3'd2: begin
//Case Write Enable Byte
Enable = 1'b1;
RW = 1'b0;
Address = 8'h00;
DataSize = 2'b00;
DataIn = 32'hFFFFFF0B;
end
3'd3: begin
//Case Read Enable Byte
RW = 1'b1;
Address = 8'h00;
DataSize = 2'b00;
end
3'd4: begin
//Case Write Enable Half Word
RW = 1'b0;
Address = 8'hF0;
DataSize = 2'b01;
DataIn = 32'hABCDEF1A;
end
3'd5: begin
//Case Read Enable Half Word
RW = 1'b1;
Address = 8'hF0;
DataSize = 2'b01;
end
3'd6: begin
//Case Write Enable Word
RW = 1'b0;
Address = 8'hFC;
DataSize = 2'b10;
DataIn = 32'hABCDEF1C;
end
3'd7: begin
//Case Read Enable Word
RW = 1'b1;
Address = 8'hFC;
DataSize = 2'b10;
end
endcase
end
initial begin
$display("EN\tRW\tAddress MFC\tDSize\tDI\t\tDOut"); //imprime header
$monitor("%h\t%h\t%h\t%h\t%h\t%h\t%h", Enable, RW, Address, MFC, DataSize, DataIn,
DataOut); //imprime las señales
end
endmodule
| 6.545766 |
module test_RAM_rn (
clk,
rst
);
//------------------------------------------------------------------
// -- Input/Output Declarations --
//------------------------------------------------------------------
input clk, rst;
//------------------------------------------------------------------
// -- State & Reg Declarations --
//------------------------------------------------------------------
parameter START = 3'd0, SET_ADDR = 3'd1, SET_RN = 3'd2, CHECK_RN = 3'd3, DONE = 3'd4;
reg [2:0] STATE, NEXT_STATE;
//------------------------------------------------------------------
// -- Module Instantiations --
//------------------------------------------------------------------
reg [8:0] rn_addr;
reg rn_clk;
reg [31:0] rn_write_data;
wire [31:0] ram_out;
RAM_autocorrelate_Rn ram1_rn (
rn_addr,
rn_clk,
rn_write_data,
0,
1,
ram_out
);
//------------------------------------------------------------------
// -- Begin Declarations & Coding --
//------------------------------------------------------------------
always@(posedge clk or negedge rst) // Determine STATE
begin
if (rst == 1'b0) STATE <= START;
else STATE <= NEXT_STATE;
end
always@(*) // Determine NEXT_STATE
begin
case (STATE)
START: begin
NEXT_STATE = SET_ADDR;
end
SET_ADDR: begin
NEXT_STATE = SET_RN;
end
SET_RN: begin
NEXT_STATE = CHECK_RN;
end
CHECK_RN: begin
NEXT_STATE = DONE;
end
DONE: begin
NEXT_STATE = DONE;
end
endcase
end
always@(posedge clk or negedge rst) // Determine outputs
begin
if (rst == 1'b0) begin
end else begin
case (STATE)
START: begin
end
SET_ADDR: begin
rn_addr <= 4'b0;
rn_clk <= clk;
end
SET_RN: begin
rn_write_data <= 4'b1111;
end
CHECK_RN: begin
end
DONE: begin
end
endcase
end
end
endmodule
| 6.740844 |
module test_rconst;
// Inputs
reg [23:0] i;
// Outputs
wire [63:0] rc;
// Instantiate the Unit Under Test (UUT)
rconst uut (
.i (i),
.rc(rc)
);
initial begin
// Initialize Inputs
i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
i = 0;
i[0] = 1;
#(`P);
if (rc !== 64'h1) begin
$display("E");
$finish;
end
i = 0;
i[1] = 1;
#(`P);
if (rc !== 64'h8082) begin
$display("E");
$finish;
end
i = 0;
i[2] = 1;
#(`P);
if (rc !== 64'h800000000000808a) begin
$display("E");
$finish;
end
i = 0;
i[3] = 1;
#(`P);
if (rc !== 64'h8000000080008000) begin
$display("E");
$finish;
end
i = 0;
i[4] = 1;
#(`P);
if (rc !== 64'h808b) begin
$display("E");
$finish;
end
i = 0;
i[5] = 1;
#(`P);
if (rc !== 64'h80000001) begin
$display("E");
$finish;
end
i = 0;
i[6] = 1;
#(`P);
if (rc !== 64'h8000000080008081) begin
$display("E");
$finish;
end
i = 0;
i[7] = 1;
#(`P);
if (rc !== 64'h8000000000008009) begin
$display("E");
$finish;
end
i = 0;
i[8] = 1;
#(`P);
if (rc !== 64'h8a) begin
$display("E");
$finish;
end
i = 0;
i[9] = 1;
#(`P);
if (rc !== 64'h88) begin
$display("E");
$finish;
end
i = 0;
i[10] = 1;
#(`P);
if (rc !== 64'h80008009) begin
$display("E");
$finish;
end
i = 0;
i[11] = 1;
#(`P);
if (rc !== 64'h8000000a) begin
$display("E");
$finish;
end
i = 0;
i[12] = 1;
#(`P);
if (rc !== 64'h8000808b) begin
$display("E");
$finish;
end
i = 0;
i[13] = 1;
#(`P);
if (rc !== 64'h800000000000008b) begin
$display("E");
$finish;
end
i = 0;
i[14] = 1;
#(`P);
if (rc !== 64'h8000000000008089) begin
$display("E");
$finish;
end
i = 0;
i[15] = 1;
#(`P);
if (rc !== 64'h8000000000008003) begin
$display("E");
$finish;
end
i = 0;
i[16] = 1;
#(`P);
if (rc !== 64'h8000000000008002) begin
$display("E");
$finish;
end
i = 0;
i[17] = 1;
#(`P);
if (rc !== 64'h8000000000000080) begin
$display("E");
$finish;
end
i = 0;
i[18] = 1;
#(`P);
if (rc !== 64'h800a) begin
$display("E");
$finish;
end
i = 0;
i[19] = 1;
#(`P);
if (rc !== 64'h800000008000000a) begin
$display("E");
$finish;
end
i = 0;
i[20] = 1;
#(`P);
if (rc !== 64'h8000000080008081) begin
$display("E");
$finish;
end
i = 0;
i[21] = 1;
#(`P);
if (rc !== 64'h8000000000008080) begin
$display("E");
$finish;
end
i = 0;
i[22] = 1;
#(`P);
if (rc !== 64'h80000001) begin
$display("E");
$finish;
end
i = 0;
i[23] = 1;
#(`P);
if (rc !== 64'h8000000080008008) begin
$display("E");
$finish;
end
$display("Good!");
$finish;
end
endmodule
| 6.567675 |
module test_rdyackin_rdyackout ();
//Interfaccia ingresso MMU
reg lineaRdyIn;
reg lineaAckIn;
reg betaRdyIn; //per resettare RdyIn
reg betaAckIn; //per resettare AckIn
reg betaRdyOut; //per settare RdyOut
reg betaAckOut; //per settare AckOut
wire rdyIn;
wire ackIn;
wire rdyOut;
wire ackOut;
reg clock;
//module(output rdyackin, input linea_rdyackin, input beta, input clock);
rdyack_in RDYIN (
rdyIn,
lineaRdyIn,
betaRdyIn,
clock
);
rdyack_in ACKIN (
ackIn,
lineaAckIn,
betaAckIn,
clock
);
//module rdyack_out(output rdyackout, input beta, input clock);
rdyack_out RDYOUT (
rdyOut,
betaRdyOut,
clock
);
rdyack_out ACKOUT (
ackOut,
betaAckOut,
clock
);
always begin
if (clock) #1 clock = ~clock;
else #4 clock = ~clock;
end
initial begin
$dumpfile("prova_rdyack_inout.vcd");
$dumpvars;
clock = 0;
#10 lineaRdyIn = 1; //ricevo qualcosa in ingresso e lo uso
#5 betaAckOut <= 1; //Set Ackout
betaRdyIn <= 1; //Reset RdyIn
#30 lineaAckIn = 1; //ricevo qualcosa dall'altra unita' e lo uso
#5 betaRdyOut <= 1; //Set RdyOut
betaAckIn <= 1; //Reset AckIn
#30 $finish;
end
endmodule
| 7.613287 |
module test ();
localparam verbose = 0;
// 33 exclamation mark
tri [7:0] BUS;
logic [7:0] Dtx;
logic WR;
logic _RD;
wire _TXE;
wire _RXF;
reg [7:0] RECEIVED;
`include "timings.v"
assign BUS = Dtx;
reg [12*8:0] expected;
integer countTx = 0;
integer countRx = 0;
integer MAX_RX = -1;
reg [7:0] charA = "a";
reg [7:0] charB = "b";
reg [7:0] charC = "c";
reg [7:0] charD = "d";
initial begin
$dumpfile("dumpfile.vcd");
$dumpvars(0, test);
$display("init value %8b", BUS);
if (BUS !== 8'bxxxxxxxx) begin
$error("wrong init value %8b", BUS);
$finish();
end
Dtx = 8'bzzzzzzzz;
$display("[%9t] START", $time);
WR = 1;
_RD = 1;
#100 $display("[%9t] ======= ENABLE READ", $time);
`Equals(BUS, 8'bzzzzzzzz);
_RD = 0;
#11000 $display("[%9t] ======= CHECK BUS FOR A", $time);
`Equals(BUS, charA);
$display("BUS hex:%x chr=%c dec:%d bin:%b", BUS, uart.printable(BUS), BUS, BUS);
$display("[%9t] ======= DISABLE READ", $time);
_RD = 1;
#100 $display("[%9t] ======= ENABLE READ", $time);
_RD = 0;
#100 $display("[%9t] ======= CHECK BUS FOR B", $time);
$display("BUS hex:%x chr=%c dec:%d bin:%b", BUS, uart.printable(BUS), BUS, BUS);
`Equals(BUS, charB);
$display("BUS=", BUS);
$display("[%9t] ======= DISABLE READ", $time);
_RD = 1;
#100 $display("[%9t] ======= ENABLE READ", $time);
_RD = 0;
#100 $display("[%9t] ======= CHECK BUS FOR C", $time);
$display("BUS hex:%x chr=%c dec:%d bin:%b", BUS, uart.printable(BUS), BUS, BUS);
`Equals(BUS, charC);
$display("BUS=", BUS);
#50000
$display(
"[%9t] ======= CHECK BUS FOR C AGAIN - NEW DATA OUGHT TO HAVE ARRIVED BY NOW", $time
);
$display("BUS hex:%x chr=%c dec:%d bin:%b", BUS, uart.printable(BUS), BUS, BUS);
`Equals(BUS, charC);
$display("BUS=", BUS);
$display("[%9t] ======= DISABLE READ", $time);
_RD = 1;
#100 $display("[%9t] ======= ENABLE READ", $time);
_RD = 0;
#100 $display("[%9t] ======= CHECK BUS FOR D", $time);
$display("BUS hex:%x chr=%c dec:%d bin:%b", BUS, uart.printable(BUS), BUS, BUS);
`Equals(BUS, charD);
$display("BUS=", BUS);
#10000 $display("DONE");
end
um245r #(
.LOG(2),
.CONTROL_FILE("test_read.control")
) uart (
.D(BUS), // Input data
.WR, // Writes data on -ve edge
._RD, // When goes from high to low then the FIFO data is placed onto D (equates to _OE)
._TXE, // When high do NOT write data using WR, when low write data by strobing WR
._RXF // When high to NOT read from D, when low then data is available to read by strobing RD low
);
always @(*)
if (verbose)
$display(
"[%9t] TEST: ",
$time,
"BUS=%8b",
BUS,
"RECEIVED=%8b",
RECEIVED,
", WR=%1b",
WR,
",_RD=%1b",
_RD,
" _RXF=%1b",
_RXF,
" _TXE=%1b",
_TXE,
" Dtx=%8b",
Dtx
);
endmodule
| 7.528945 |
module Test_Read_MUX;
// Inputs
reg CLK;
reg RST;
reg [31:0] HRDATA_1;
reg [31:0] HRDATA_2;
reg [31:0] HRDATA_3;
reg [1:0] SEL;
// Outputs
wire [31:0] HRDATA;
// Instantiate the Unit Under Test (UUT)
Read_MUX uut (
.CLK(CLK),
.RST(RST),
.HRDATA(HRDATA),
.HRDATA_1(HRDATA_1),
.HRDATA_2(HRDATA_2),
.HRDATA_3(HRDATA_3),
.SEL(SEL)
);
always #15 CLK = !CLK;
initial begin
#500 RST = 1; // Random reset stimuli
#50 RST = 0;
end
initial begin
// Initialize Inputs
CLK = 0;
RST = 0;
HRDATA_1 = 0;
HRDATA_2 = 0;
HRDATA_3 = 0;
SEL = 0;
// Wait 100 ns for global reset to finish
#15;
// Add stimulus here
#200 HRDATA_1 = $random;
HRDATA_2 = $random;
HRDATA_3 = $random;
SEL = 2'b00;
RST = 0;
#200 /*HRDATA_1 = $random; HRDATA_2 = $random; HRDATA_3 = $random;*/ SEL = 2'b01;
RST = 0;
#200 /*HRDATA_1 = $random; HRDATA_2 = $random; HRDATA_3 = $random;*/ SEL = 2'b10;
RST = 0;
#200 /*HRDATA_1 = $random; HRDATA_2 = $random; HRDATA_3 = $random;*/ SEL = 2'b11;
RST = 0;
#200 /*HRDATA_1 = $random; HRDATA_2 = $random; HRDATA_3 = $random;*/ SEL = 2'b00;
RST = 0;
end
endmodule
| 7.370382 |
module test_receiver;
localparam SUCCESS = 1'b1;
localparam FAIL = 1'b0;
reg result = SUCCESS;
// scaled output values corresponding to their pwm input counterpart
wire [`PWM_VALUE_BIT_WIDTH - 1:0] throttle_val;
wire [`PWM_VALUE_BIT_WIDTH - 1:0] yaw_val;
wire [`PWM_VALUE_BIT_WIDTH - 1:0] roll_val;
wire [`PWM_VALUE_BIT_WIDTH - 1:0] pitch_val;
reg [`PWM_VALUE_BIT_WIDTH - 1:0] expected_val;
// pwm inputs modeling the hardware receiver
reg throttle_pwm = 0;
reg yaw_pwm = 0;
reg roll_pwm = 0;
reg pitch_pwm = 0;
reg resetn = 1;
wire sys_clk = 0;
defparam OSCH_inst.NOM_FREQ = "38.00";
OSCH OSCH_inst (
.STDBY(1'b0),
.OSC(sys_clk),
.SEDSTDBY()
);
wire us_clk;
us_clk us_clk_divider (
.us_clk (us_clk),
.sys_clk(sys_clk),
.resetn (1)
); // TODO: Change this to the top level reset signal (.resetn(resetn))
// line up the parameters here to the ones internal to the receiver module
receiver DUT (
.throttle_val(throttle_val),
.yaw_val(yaw_val),
.roll_val(roll_val),
.pitch_val(pitch_val),
.throttle_pwm(throttle_pwm),
.yaw_pwm(yaw_pwm),
.roll_pwm(roll_pwm),
.pitch_pwm(pitch_pwm),
.us_clk(us_clk),
.resetn(resetn)
);
initial begin
// Test 1: reset all submodules and make sure they output their default values
resetn = 0;
#5000 resetn = 1;
#5000;
expected_val = map_pwm_to_value(`THROTTLE_DEFAULT_PULSE_TIME_HIGH_US);
if (throttle_val != expected_val) begin
display_fail("throttle", throttle_val, expected_val);
result = FAIL;
end
expected_val = map_pwm_to_value(`YAW_DEFAULT_PULSE_TIME_HIGH_US);
if (yaw_val != expected_val) begin
display_fail("yaw", yaw_val, expected_val);
result = FAIL;
end
expected_val = map_pwm_to_value(`ROLL_DEFAULT_PULSE_TIME_HIGH_US);
if (roll_val != expected_val) begin
display_fail("roll", roll_val, expected_val);
result = FAIL;
end
expected_val = map_pwm_to_value(`PITCH_DEFAULT_PULSE_TIME_HIGH_US);
if (pitch_val != expected_val) begin
display_fail("pitch", pitch_val, expected_val);
result = FAIL;
end
if (result == FAIL) #10 $finish;
display_success();
#10 $finish;
end
function [`PWM_VALUE_BIT_WIDTH - 1:0] map_pwm_to_value(
input [`PWM_TIME_BIT_WIDTH - 1:0] pwm_time_high_us);
begin
pwm_time_high_us = pwm_time_high_us - `MIN_PWM_TIME_HIGH_US;
map_pwm_to_value = pwm_time_high_us[9:2];
end
endfunction
task display_fail(input [63:0] val_name, input [`PWM_VALUE_BIT_WIDTH - 1:0] actual_val,
input [`PWM_VALUE_BIT_WIDTH - 1:0] expected_val);
begin
#1 $display("########################################################################");
#1 $display("\tTEST FAILED(%s):", val_name);
#1 $display("\t\tactual=%d expected=%d", actual_val, expected_val);
#1 $display("########################################################################");
end
endtask
task display_success();
begin
#1 $display("########################################################################");
#1 $display("########################################################################");
#1 $display("########################### ALL TESTS PASSED ###########################");
#1 $display("########################################################################");
#1 $display("########################################################################");
end
endtask
endmodule
| 8.90121 |
module regf_test ();
parameter AWIDTH = 4;
parameter DSIZE = 32;
reg clk;
reg reset_b;
reg halt;
reg [AWIDTH-1:0] addra;
reg a_en;
reg [AWIDTH-1:0] addrb;
reg b_en;
reg [AWIDTH-1:0] addrc;
reg [DSIZE-1:0] dc;
reg wec;
wire [DSIZE-1:0] qra;
wire a_en_out;
wire [DSIZE-1:0] qrb;
wire b_en_out;
integer i;
integer clk_cnt;
integer errors;
mem_regf #(AWIDTH, DSIZE) i_regf (
.clk(clk),
.reset_b(reset_b),
.halt(halt),
.addra(addra), // reg a addr
.a_en(a_en), // valid reg a read
.addrb(addrb), // reg b addr
.b_en(b_en), // valid reg b read
.addrc(addrc), // reg c addr
.wec(wec), // write enable reg c
.dc(dc), // data input reg c
.qra(qra), // data output a
.qrb(qrb)
); // data output b
initial begin
clk = 1'b0;
clk_cnt = 0;
#10
forever begin
#2.5 clk = ~clk;
if (clk) clk_cnt = clk_cnt + 1;
end
end
initial begin
errors = 0;
addra = 'b0;
a_en = 1'b0;
addrb = 'b0;
b_en = 1'b0;
halt = 1'b0;
@(negedge clk);
reset_b = 1'b1;
@(negedge clk);
reset_b = 1'b0;
@(negedge clk);
reset_b = 1'b1;
@(negedge clk);
@(negedge clk);
@(negedge clk);
// Test out port C write functionality
wec = 1'b1;
for (i = 0; i < (1 << AWIDTH); i = i + 1) begin
addrc = i;
dc = i;
@(negedge clk);
end
wec = 1'b0;
for (i = 0; i < (1 << AWIDTH); i = i + 1) begin
addra = i;
a_en = 1'b1;
addrb = (1 << AWIDTH) - (i + 1);
b_en = 1'b1;
if (i == 5) begin
addrc = 'd5;
dc = 32'd1234;
wec = 1'b1;
end else wec = 1'b0;
if (i == 7) begin
halt = 1'b1;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
halt = 1'b0;
end
@(negedge clk);
end
a_en = 1'b0;
b_en = 1'b0;
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
@(negedge clk);
$finish;
end
always @(posedge clk) begin
if (!halt) $display("after rising edge clk # %d, regf output a = %d", clk_cnt, qra);
if (!halt) $display("after rising edge clk # %d, regf output b = %d", clk_cnt, qrb);
end
endmodule
| 6.799711 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
| 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
.in1(muxN_1_out),
.sel(in_sel[1]),
.out(_join_out)
);
wire [3:0] muxN_0_in_data[1:0];
assign muxN_0_in_data[1] = in_data[1];
assign muxN_0_in_data[0] = in_data[0];
commonlib_muxn__N2__width4 muxN_0 (
.in_data(muxN_0_in_data),
.in_sel(sel_slice0_out),
.out(muxN_0_out)
);
wire [3:0] muxN_1_in_data[1:0];
assign muxN_1_in_data[1] = in_data[3];
assign muxN_1_in_data[0] = in_data[2];
commonlib_muxn__N2__width4 muxN_1 (
.in_data(muxN_1_in_data),
.in_sel(sel_slice1_out),
.out(muxN_1_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice0 (
.in (in_sel),
.out(sel_slice0_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice1 (
.in (in_sel),
.out(sel_slice1_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input ASYNCRESET
);
wire [3:0] reg_PR4_inst0_out;
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_PR4_inst0 (
.clk (CLK),
.arst(ASYNCRESET),
.in (I),
.out (reg_PR4_inst0_out)
);
assign O = reg_PR4_inst0_out;
endmodule
| 7.117303 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign coreir_commonlib_mux4x4_inst0_in_data[2] = I2;
assign coreir_commonlib_mux4x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux4x4_inst0_in_data[0] = I0;
commonlib_muxn__N4__width4 coreir_commonlib_mux4x4_inst0 (
.in_data(coreir_commonlib_mux4x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux4x4_inst0_out)
);
assign O = coreir_commonlib_mux4x4_inst0_out;
endmodule
| 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 (
.in_data(coreir_commonlib_mux2x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x4_inst0_out)
);
assign O = coreir_commonlib_mux2x4_inst0_out;
endmodule
| 8.559964 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] Mux2xBits4_inst1_O;
wire [3:0] Mux2xBits4_inst2_O;
wire [3:0] Mux2xBits4_inst3_O;
wire [3:0] Mux4xBits4_inst0_O;
wire [3:0] Register_inst0_O;
wire [3:0] Register_inst1_O;
wire [3:0] Register_inst2_O;
wire [3:0] Register_inst3_O;
wire [1:0] const_0_2_out;
wire [1:0] const_1_2_out;
wire [1:0] const_2_2_out;
wire [1:0] const_3_2_out;
wire magma_Bits_2_eq_inst0_out;
wire magma_Bits_2_eq_inst1_out;
wire magma_Bits_2_eq_inst2_out;
wire magma_Bits_2_eq_inst3_out;
Mux2xBits4 Mux2xBits4_inst0 (
.I0(Register_inst0_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst0_out),
.O (Mux2xBits4_inst0_O)
);
Mux2xBits4 Mux2xBits4_inst1 (
.I0(Register_inst1_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst1_out),
.O (Mux2xBits4_inst1_O)
);
Mux2xBits4 Mux2xBits4_inst2 (
.I0(Register_inst2_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst2_out),
.O (Mux2xBits4_inst2_O)
);
Mux2xBits4 Mux2xBits4_inst3 (
.I0(Register_inst3_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst3_out),
.O (Mux2xBits4_inst3_O)
);
Mux4xBits4 Mux4xBits4_inst0 (
.I0(Register_inst0_O),
.I1(Register_inst1_O),
.I2(Register_inst2_O),
.I3(Register_inst3_O),
.S (read_0_addr),
.O (Mux4xBits4_inst0_O)
);
Register Register_inst0 (
.I(Mux2xBits4_inst0_O),
.O(Register_inst0_O),
.CLK(CLK),
.ASYNCRESET(ASYNCRESET)
);
Register Register_inst1 (
.I(Mux2xBits4_inst1_O),
.O(Register_inst1_O),
.CLK(CLK),
.ASYNCRESET(ASYNCRESET)
);
Register Register_inst2 (
.I(Mux2xBits4_inst2_O),
.O(Register_inst2_O),
.CLK(CLK),
.ASYNCRESET(ASYNCRESET)
);
Register Register_inst3 (
.I(Mux2xBits4_inst3_O),
.O(Register_inst3_O),
.CLK(CLK),
.ASYNCRESET(ASYNCRESET)
);
coreir_const #(
.value(2'h0),
.width(2)
) const_0_2 (
.out(const_0_2_out)
);
coreir_const #(
.value(2'h1),
.width(2)
) const_1_2 (
.out(const_1_2_out)
);
coreir_const #(
.value(2'h2),
.width(2)
) const_2_2 (
.out(const_2_2_out)
);
coreir_const #(
.value(2'h3),
.width(2)
) const_3_2 (
.out(const_3_2_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst0 (
.in0(write_0_addr),
.in1(const_0_2_out),
.out(magma_Bits_2_eq_inst0_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst1 (
.in0(write_0_addr),
.in1(const_1_2_out),
.out(magma_Bits_2_eq_inst1_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst2 (
.in0(write_0_addr),
.in1(const_2_2_out),
.out(magma_Bits_2_eq_inst2_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst3 (
.in0(write_0_addr),
.in1(const_3_2_out),
.out(magma_Bits_2_eq_inst3_out)
);
assign read_0_data = Mux4xBits4_inst0_O;
endmodule
| 7.958996 |
module test_regfile_basic_magma_False_AsyncReset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
| 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
.in1(muxN_1_out),
.sel(in_sel[1]),
.out(_join_out)
);
wire [3:0] muxN_0_in_data[1:0];
assign muxN_0_in_data[1] = in_data[1];
assign muxN_0_in_data[0] = in_data[0];
commonlib_muxn__N2__width4 muxN_0 (
.in_data(muxN_0_in_data),
.in_sel(sel_slice0_out),
.out(muxN_0_out)
);
wire [3:0] muxN_1_in_data[1:0];
assign muxN_1_in_data[1] = in_data[3];
assign muxN_1_in_data[0] = in_data[2];
commonlib_muxn__N2__width4 muxN_1 (
.in_data(muxN_1_in_data),
.in_sel(sel_slice1_out),
.out(muxN_1_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice0 (
.in (in_sel),
.out(sel_slice0_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice1 (
.in (in_sel),
.out(sel_slice1_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign coreir_commonlib_mux4x4_inst0_in_data[2] = I2;
assign coreir_commonlib_mux4x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux4x4_inst0_in_data[0] = I0;
commonlib_muxn__N4__width4 coreir_commonlib_mux4x4_inst0 (
.in_data(coreir_commonlib_mux4x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux4x4_inst0_out)
);
assign O = coreir_commonlib_mux4x4_inst0_out;
endmodule
| 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 (
.in_data(coreir_commonlib_mux2x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x4_inst0_out)
);
assign O = coreir_commonlib_mux2x4_inst0_out;
endmodule
| 8.559964 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] const_0_4_out;
wire [3:0] reg_P4_inst0_out;
Mux2xBits4 Mux2xBits4_inst0 (
.I0(I),
.I1(const_0_4_out),
.S (RESET),
.O (Mux2xBits4_inst0_O)
);
coreir_const #(
.value(4'h0),
.width(4)
) const_0_4 (
.out(const_0_4_out)
);
coreir_reg #(
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_P4_inst0 (
.clk(CLK),
.in (Mux2xBits4_inst0_O),
.out(reg_P4_inst0_out)
);
assign O = reg_P4_inst0_out;
endmodule
| 7.117303 |
module my_regfile (
input CLK,
input RESET,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] Mux2xBits4_inst1_O;
wire [3:0] Mux2xBits4_inst2_O;
wire [3:0] Mux2xBits4_inst3_O;
wire [3:0] Mux4xBits4_inst0_O;
wire [3:0] Register_inst0_O;
wire [3:0] Register_inst1_O;
wire [3:0] Register_inst2_O;
wire [3:0] Register_inst3_O;
wire [1:0] const_0_2_out;
wire [1:0] const_1_2_out;
wire [1:0] const_2_2_out;
wire [1:0] const_3_2_out;
wire magma_Bits_2_eq_inst0_out;
wire magma_Bits_2_eq_inst1_out;
wire magma_Bits_2_eq_inst2_out;
wire magma_Bits_2_eq_inst3_out;
Mux2xBits4 Mux2xBits4_inst0 (
.I0(Register_inst0_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst0_out),
.O (Mux2xBits4_inst0_O)
);
Mux2xBits4 Mux2xBits4_inst1 (
.I0(Register_inst1_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst1_out),
.O (Mux2xBits4_inst1_O)
);
Mux2xBits4 Mux2xBits4_inst2 (
.I0(Register_inst2_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst2_out),
.O (Mux2xBits4_inst2_O)
);
Mux2xBits4 Mux2xBits4_inst3 (
.I0(Register_inst3_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst3_out),
.O (Mux2xBits4_inst3_O)
);
Mux4xBits4 Mux4xBits4_inst0 (
.I0(Register_inst0_O),
.I1(Register_inst1_O),
.I2(Register_inst2_O),
.I3(Register_inst3_O),
.S (read_0_addr),
.O (Mux4xBits4_inst0_O)
);
Register Register_inst0 (
.I(Mux2xBits4_inst0_O),
.O(Register_inst0_O),
.CLK(CLK),
.RESET(RESET)
);
Register Register_inst1 (
.I(Mux2xBits4_inst1_O),
.O(Register_inst1_O),
.CLK(CLK),
.RESET(RESET)
);
Register Register_inst2 (
.I(Mux2xBits4_inst2_O),
.O(Register_inst2_O),
.CLK(CLK),
.RESET(RESET)
);
Register Register_inst3 (
.I(Mux2xBits4_inst3_O),
.O(Register_inst3_O),
.CLK(CLK),
.RESET(RESET)
);
coreir_const #(
.value(2'h0),
.width(2)
) const_0_2 (
.out(const_0_2_out)
);
coreir_const #(
.value(2'h1),
.width(2)
) const_1_2 (
.out(const_1_2_out)
);
coreir_const #(
.value(2'h2),
.width(2)
) const_2_2 (
.out(const_2_2_out)
);
coreir_const #(
.value(2'h3),
.width(2)
) const_3_2 (
.out(const_3_2_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst0 (
.in0(write_0_addr),
.in1(const_0_2_out),
.out(magma_Bits_2_eq_inst0_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst1 (
.in0(write_0_addr),
.in1(const_1_2_out),
.out(magma_Bits_2_eq_inst1_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst2 (
.in0(write_0_addr),
.in1(const_2_2_out),
.out(magma_Bits_2_eq_inst2_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst3 (
.in0(write_0_addr),
.in1(const_3_2_out),
.out(magma_Bits_2_eq_inst3_out)
);
assign read_0_data = Mux4xBits4_inst0_O;
endmodule
| 7.958996 |
module test_regfile_basic_magma_False_Reset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input RESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.CLK(CLK),
.RESET(RESET),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
| 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
.in1(muxN_1_out),
.sel(in_sel[1]),
.out(_join_out)
);
wire [3:0] muxN_0_in_data[1:0];
assign muxN_0_in_data[1] = in_data[1];
assign muxN_0_in_data[0] = in_data[0];
commonlib_muxn__N2__width4 muxN_0 (
.in_data(muxN_0_in_data),
.in_sel(sel_slice0_out),
.out(muxN_0_out)
);
wire [3:0] muxN_1_in_data[1:0];
assign muxN_1_in_data[1] = in_data[3];
assign muxN_1_in_data[0] = in_data[2];
commonlib_muxn__N2__width4 muxN_1 (
.in_data(muxN_1_in_data),
.in_sel(sel_slice1_out),
.out(muxN_1_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice0 (
.in (in_sel),
.out(sel_slice0_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice1 (
.in (in_sel),
.out(sel_slice1_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input ASYNCRESET
);
wire [3:0] reg_PR4_inst0_out;
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_PR4_inst0 (
.clk (CLK),
.arst(ASYNCRESET),
.in (I),
.out (reg_PR4_inst0_out)
);
assign O = reg_PR4_inst0_out;
endmodule
| 7.117303 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign coreir_commonlib_mux4x4_inst0_in_data[2] = I2;
assign coreir_commonlib_mux4x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux4x4_inst0_in_data[0] = I0;
commonlib_muxn__N4__width4 coreir_commonlib_mux4x4_inst0 (
.in_data(coreir_commonlib_mux4x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux4x4_inst0_out)
);
assign O = coreir_commonlib_mux4x4_inst0_out;
endmodule
| 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 (
.in_data(coreir_commonlib_mux2x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x4_inst0_out)
);
assign O = coreir_commonlib_mux2x4_inst0_out;
endmodule
| 8.559964 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] Mux2xBits4_inst1_O;
wire [3:0] Mux2xBits4_inst2_O;
wire [3:0] Mux2xBits4_inst3_O;
wire [3:0] Mux2xBits4_inst4_O;
wire [3:0] Mux4xBits4_inst0_O;
wire [3:0] Register_inst0_O;
wire [3:0] Register_inst1_O;
wire [3:0] Register_inst2_O;
wire [3:0] Register_inst3_O;
wire [1:0] const_0_2_out;
wire [1:0] const_1_2_out;
wire [1:0] const_2_2_out;
wire [1:0] const_3_2_out;
wire magma_Bits_2_eq_inst0_out;
wire magma_Bits_2_eq_inst1_out;
wire magma_Bits_2_eq_inst2_out;
wire magma_Bits_2_eq_inst3_out;
wire magma_Bits_2_eq_inst4_out;
Mux2xBits4 Mux2xBits4_inst0 (
.I0(Register_inst0_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst0_out),
.O (Mux2xBits4_inst0_O)
);
Mux2xBits4 Mux2xBits4_inst1 (
.I0(Register_inst1_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst1_out),
.O (Mux2xBits4_inst1_O)
);
Mux2xBits4 Mux2xBits4_inst2 (
.I0(Register_inst2_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst2_out),
.O (Mux2xBits4_inst2_O)
);
Mux2xBits4 Mux2xBits4_inst3 (
.I0(Register_inst3_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst3_out),
.O (Mux2xBits4_inst3_O)
);
Mux2xBits4 Mux2xBits4_inst4 (
.I0(Mux4xBits4_inst0_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst4_out),
.O (Mux2xBits4_inst4_O)
);
Mux4xBits4 Mux4xBits4_inst0 (
.I0(Register_inst0_O),
.I1(Register_inst1_O),
.I2(Register_inst2_O),
.I3(Register_inst3_O),
.S (read_0_addr),
.O (Mux4xBits4_inst0_O)
);
Register Register_inst0 (
.I(Mux2xBits4_inst0_O),
.O(Register_inst0_O),
.CLK(CLK),
.ASYNCRESET(ASYNCRESET)
);
Register Register_inst1 (
.I(Mux2xBits4_inst1_O),
.O(Register_inst1_O),
.CLK(CLK),
.ASYNCRESET(ASYNCRESET)
);
Register Register_inst2 (
.I(Mux2xBits4_inst2_O),
.O(Register_inst2_O),
.CLK(CLK),
.ASYNCRESET(ASYNCRESET)
);
Register Register_inst3 (
.I(Mux2xBits4_inst3_O),
.O(Register_inst3_O),
.CLK(CLK),
.ASYNCRESET(ASYNCRESET)
);
coreir_const #(
.value(2'h0),
.width(2)
) const_0_2 (
.out(const_0_2_out)
);
coreir_const #(
.value(2'h1),
.width(2)
) const_1_2 (
.out(const_1_2_out)
);
coreir_const #(
.value(2'h2),
.width(2)
) const_2_2 (
.out(const_2_2_out)
);
coreir_const #(
.value(2'h3),
.width(2)
) const_3_2 (
.out(const_3_2_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst0 (
.in0(write_0_addr),
.in1(const_0_2_out),
.out(magma_Bits_2_eq_inst0_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst1 (
.in0(write_0_addr),
.in1(const_1_2_out),
.out(magma_Bits_2_eq_inst1_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst2 (
.in0(write_0_addr),
.in1(const_2_2_out),
.out(magma_Bits_2_eq_inst2_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst3 (
.in0(write_0_addr),
.in1(const_3_2_out),
.out(magma_Bits_2_eq_inst3_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst4 (
.in0(write_0_addr),
.in1(read_0_addr),
.out(magma_Bits_2_eq_inst4_out)
);
assign read_0_data = Mux2xBits4_inst4_O;
endmodule
| 7.958996 |
module test_regfile_basic_magma_True_AsyncReset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg #(
parameter width = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg = init;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk) begin
outReg <= in;
end
assign out = outReg;
endmodule
| 7.868877 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
.in1(muxN_1_out),
.sel(in_sel[1]),
.out(_join_out)
);
wire [3:0] muxN_0_in_data[1:0];
assign muxN_0_in_data[1] = in_data[1];
assign muxN_0_in_data[0] = in_data[0];
commonlib_muxn__N2__width4 muxN_0 (
.in_data(muxN_0_in_data),
.in_sel(sel_slice0_out),
.out(muxN_0_out)
);
wire [3:0] muxN_1_in_data[1:0];
assign muxN_1_in_data[1] = in_data[3];
assign muxN_1_in_data[0] = in_data[2];
commonlib_muxn__N2__width4 muxN_1 (
.in_data(muxN_1_in_data),
.in_sel(sel_slice1_out),
.out(muxN_1_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice0 (
.in (in_sel),
.out(sel_slice0_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice1 (
.in (in_sel),
.out(sel_slice1_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module Mux4xBits4 (
input [3:0] I0,
input [3:0] I1,
input [3:0] I2,
input [3:0] I3,
input [1:0] S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux4x4_inst0_out;
wire [3:0] coreir_commonlib_mux4x4_inst0_in_data[3:0];
assign coreir_commonlib_mux4x4_inst0_in_data[3] = I3;
assign coreir_commonlib_mux4x4_inst0_in_data[2] = I2;
assign coreir_commonlib_mux4x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux4x4_inst0_in_data[0] = I0;
commonlib_muxn__N4__width4 coreir_commonlib_mux4x4_inst0 (
.in_data(coreir_commonlib_mux4x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux4x4_inst0_out)
);
assign O = coreir_commonlib_mux4x4_inst0_out;
endmodule
| 8.824384 |
module Mux2xBits4 (
input [3:0] I0,
input [3:0] I1,
input S,
output [3:0] O
);
wire [3:0] coreir_commonlib_mux2x4_inst0_out;
wire [3:0] coreir_commonlib_mux2x4_inst0_in_data[1:0];
assign coreir_commonlib_mux2x4_inst0_in_data[1] = I1;
assign coreir_commonlib_mux2x4_inst0_in_data[0] = I0;
commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0 (
.in_data(coreir_commonlib_mux2x4_inst0_in_data),
.in_sel(S),
.out(coreir_commonlib_mux2x4_inst0_out)
);
assign O = coreir_commonlib_mux2x4_inst0_out;
endmodule
| 8.559964 |
module Register (
input [3:0] I,
output [3:0] O,
input CLK,
input RESET
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] const_0_4_out;
wire [3:0] reg_P4_inst0_out;
Mux2xBits4 Mux2xBits4_inst0 (
.I0(I),
.I1(const_0_4_out),
.S (RESET),
.O (Mux2xBits4_inst0_O)
);
coreir_const #(
.value(4'h0),
.width(4)
) const_0_4 (
.out(const_0_4_out)
);
coreir_reg #(
.clk_posedge(1'b1),
.init(4'h0),
.width(4)
) reg_P4_inst0 (
.clk(CLK),
.in (Mux2xBits4_inst0_O),
.out(reg_P4_inst0_out)
);
assign O = reg_P4_inst0_out;
endmodule
| 7.117303 |
module my_regfile (
input CLK,
input RESET,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
wire [3:0] Mux2xBits4_inst0_O;
wire [3:0] Mux2xBits4_inst1_O;
wire [3:0] Mux2xBits4_inst2_O;
wire [3:0] Mux2xBits4_inst3_O;
wire [3:0] Mux2xBits4_inst4_O;
wire [3:0] Mux4xBits4_inst0_O;
wire [3:0] Register_inst0_O;
wire [3:0] Register_inst1_O;
wire [3:0] Register_inst2_O;
wire [3:0] Register_inst3_O;
wire [1:0] const_0_2_out;
wire [1:0] const_1_2_out;
wire [1:0] const_2_2_out;
wire [1:0] const_3_2_out;
wire magma_Bits_2_eq_inst0_out;
wire magma_Bits_2_eq_inst1_out;
wire magma_Bits_2_eq_inst2_out;
wire magma_Bits_2_eq_inst3_out;
wire magma_Bits_2_eq_inst4_out;
Mux2xBits4 Mux2xBits4_inst0 (
.I0(Register_inst0_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst0_out),
.O (Mux2xBits4_inst0_O)
);
Mux2xBits4 Mux2xBits4_inst1 (
.I0(Register_inst1_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst1_out),
.O (Mux2xBits4_inst1_O)
);
Mux2xBits4 Mux2xBits4_inst2 (
.I0(Register_inst2_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst2_out),
.O (Mux2xBits4_inst2_O)
);
Mux2xBits4 Mux2xBits4_inst3 (
.I0(Register_inst3_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst3_out),
.O (Mux2xBits4_inst3_O)
);
Mux2xBits4 Mux2xBits4_inst4 (
.I0(Mux4xBits4_inst0_O),
.I1(write_0_data),
.S (magma_Bits_2_eq_inst4_out),
.O (Mux2xBits4_inst4_O)
);
Mux4xBits4 Mux4xBits4_inst0 (
.I0(Register_inst0_O),
.I1(Register_inst1_O),
.I2(Register_inst2_O),
.I3(Register_inst3_O),
.S (read_0_addr),
.O (Mux4xBits4_inst0_O)
);
Register Register_inst0 (
.I(Mux2xBits4_inst0_O),
.O(Register_inst0_O),
.CLK(CLK),
.RESET(RESET)
);
Register Register_inst1 (
.I(Mux2xBits4_inst1_O),
.O(Register_inst1_O),
.CLK(CLK),
.RESET(RESET)
);
Register Register_inst2 (
.I(Mux2xBits4_inst2_O),
.O(Register_inst2_O),
.CLK(CLK),
.RESET(RESET)
);
Register Register_inst3 (
.I(Mux2xBits4_inst3_O),
.O(Register_inst3_O),
.CLK(CLK),
.RESET(RESET)
);
coreir_const #(
.value(2'h0),
.width(2)
) const_0_2 (
.out(const_0_2_out)
);
coreir_const #(
.value(2'h1),
.width(2)
) const_1_2 (
.out(const_1_2_out)
);
coreir_const #(
.value(2'h2),
.width(2)
) const_2_2 (
.out(const_2_2_out)
);
coreir_const #(
.value(2'h3),
.width(2)
) const_3_2 (
.out(const_3_2_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst0 (
.in0(write_0_addr),
.in1(const_0_2_out),
.out(magma_Bits_2_eq_inst0_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst1 (
.in0(write_0_addr),
.in1(const_1_2_out),
.out(magma_Bits_2_eq_inst1_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst2 (
.in0(write_0_addr),
.in1(const_2_2_out),
.out(magma_Bits_2_eq_inst2_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst3 (
.in0(write_0_addr),
.in1(const_3_2_out),
.out(magma_Bits_2_eq_inst3_out)
);
coreir_eq #(
.width(2)
) magma_Bits_2_eq_inst4 (
.in0(write_0_addr),
.in1(read_0_addr),
.out(magma_Bits_2_eq_inst4_out)
);
assign read_0_data = Mux2xBits4_inst4_O;
endmodule
| 7.958996 |
module test_regfile_basic_magma_True_Reset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input RESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.CLK(CLK),
.RESET(RESET),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
end
assign read_0_data = data[read_0_addr];
endmodule
| 7.958996 |
module test_regfile_basic_verilog_False_AsyncReset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module my_regfile (
input CLK,
input RESET,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
end
assign read_0_data = data[read_0_addr];
endmodule
| 7.958996 |
module test_regfile_basic_verilog_False_Reset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input RESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.CLK(CLK),
.RESET(RESET),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module my_regfile (
input ASYNCRESET,
input CLK,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
end
assign read_0_data = write_0_addr == read_0_addr ? write_0_data : data[read_0_addr];
endmodule
| 7.958996 |
module test_regfile_basic_verilog_True_AsyncReset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input ASYNCRESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.ASYNCRESET(ASYNCRESET),
.CLK(CLK),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module my_regfile (
input CLK,
input RESET,
input [1:0] read_0_addr,
output [3:0] read_0_data,
input [1:0] write_0_addr,
input [3:0] write_0_data
);
reg [3:0] data[3:0];
always @(posedge CLK) begin
data[write_0_addr] <= write_0_data;
end
assign read_0_data = write_0_addr == read_0_addr ? write_0_data : data[read_0_addr];
endmodule
| 7.958996 |
module test_regfile_basic_verilog_True_Reset (
input [1:0] write_addr,
input [3:0] write_data,
input [1:0] read_addr,
output [3:0] read_data,
input CLK,
input RESET
);
wire [3:0] my_regfile_read_0_data;
my_regfile my_regfile (
.CLK(CLK),
.RESET(RESET),
.read_0_addr(read_addr),
.read_0_data(my_regfile_read_0_data),
.write_0_addr(write_addr),
.write_0_data(write_data)
);
assign read_data = my_regfile_read_0_data;
endmodule
| 6.909877 |
module coreir_slice #(
parameter hi = 1,
parameter lo = 0,
parameter width = 1
) (
input [width-1:0] in,
output [hi-lo-1:0] out
);
assign out = in[hi-1:lo];
endmodule
| 8.799926 |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
| 8.40589 |
module coreir_mux #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
input sel,
output [width-1:0] out
);
assign out = sel ? in1 : in0;
endmodule
| 8.809699 |
module coreir_eq #(
parameter width = 1
) (
input [width-1:0] in0,
input [width-1:0] in1,
output out
);
assign out = in0 == in1;
endmodule
| 7.939296 |
module coreir_const #(
parameter width = 1,
parameter value = 1
) (
output [width-1:0] out
);
assign out = value;
endmodule
| 8.127638 |
module corebit_and (
input in0,
input in1,
output out
);
assign out = in0 & in1;
endmodule
| 8.125026 |
module commonlib_muxn__N2__width4 (
input [3:0] in_data[1:0],
input [0:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
coreir_mux #(
.width(4)
) _join (
.in0(in_data[0]),
.in1(in_data[1]),
.sel(in_sel[0]),
.out(_join_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
module commonlib_muxn__N4__width4 (
input [3:0] in_data[3:0],
input [1:0] in_sel,
output [3:0] out
);
wire [3:0] _join_out;
wire [3:0] muxN_0_out;
wire [3:0] muxN_1_out;
wire [0:0] sel_slice0_out;
wire [0:0] sel_slice1_out;
coreir_mux #(
.width(4)
) _join (
.in0(muxN_0_out),
.in1(muxN_1_out),
.sel(in_sel[1]),
.out(_join_out)
);
wire [3:0] muxN_0_in_data[1:0];
assign muxN_0_in_data[1] = in_data[1];
assign muxN_0_in_data[0] = in_data[0];
commonlib_muxn__N2__width4 muxN_0 (
.in_data(muxN_0_in_data),
.in_sel(sel_slice0_out),
.out(muxN_0_out)
);
wire [3:0] muxN_1_in_data[1:0];
assign muxN_1_in_data[1] = in_data[3];
assign muxN_1_in_data[0] = in_data[2];
commonlib_muxn__N2__width4 muxN_1 (
.in_data(muxN_1_in_data),
.in_sel(sel_slice1_out),
.out(muxN_1_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice0 (
.in (in_sel),
.out(sel_slice0_out)
);
coreir_slice #(
.hi(1),
.lo(0),
.width(2)
) sel_slice1 (
.in (in_sel),
.out(sel_slice1_out)
);
assign out = _join_out;
endmodule
| 7.978522 |
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