code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module tg_prbs_gen #(
parameter PRBS_WIDTH = 64, // // "SEQUENTIAL_BURST"
parameter START_ADDR = 32'h00000000,
parameter DMODE = "READ",
parameter PRBS_OFFSET = 0,
parameter [PRBS_WIDTH-1:0] TAPS= 32'h80200003 //32'b10000000_00100000_00000000_00000011// [31,21,1,0]
// 16 taps: [15,14,12,3] : 16'b11010000_00001000
// 64 taps: [63,62,60,59]: {{8'b11011000}, {56'b0}}
) (
input clk_i,
input clk_en,
input rst,
// input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH-1:0] prbs_seed_i,
output initialize_done,
output [PRBS_WIDTH-1:0] prbs_o, // generated address
output reg [ 3:0] prbs_shift_value,
output [ 31:0] ReSeedcounter_o
);
wire prbs_seed_ld;
reg [PRBS_WIDTH - 1:0] Next_LFSR_Reg;
reg [PRBS_WIDTH - 1:0] LFSR_Reg;
reg [PRBS_WIDTH-1:0] counterA;
reg Bits0_9_zero, Feedback;
integer i;
reg [PRBS_WIDTH - 1:0] ReSeedcounter;
reg [10:0] freerun_counters;
reg init_setup;
wire prbs_clk_en1;
wire prbs_clk_en2;
always @(posedge clk_i) begin
if (rst) freerun_counters <= 'b0;
else if (freerun_counters <= 128 || init_setup) freerun_counters <= freerun_counters + 1'b1;
end
always @(posedge clk_i) begin
if (rst) counterA <= 'b0;
// else if (clk_en || init_setup || )
else if (prbs_clk_en1) counterA <= counterA + 1'b1;
end
assign initialize_done = ~init_setup;
always @(posedge clk_i) begin
if (rst) init_setup <= 'b0;
else if (freerun_counters <= PRBS_OFFSET + 255) init_setup <= 1'b1;
else init_setup <= 1'b0;
end
/*always @ (posedge clk_i)
begin
if (rst)
prbs_shift_value <= 'b0;
else if (freerun_counters == PRBS_OFFSET + 4 )
prbs_shift_value <= LFSR_Reg[3:0];
end
*/
assign ReSeedcounter_o = {{(32 - PRBS_WIDTH) {1'b0}}, ReSeedcounter};
always @(posedge clk_i) begin
if (rst) ReSeedcounter <= 'b0;
else if (prbs_clk_en1)
if (ReSeedcounter == {PRBS_WIDTH{1'b1}}) ReSeedcounter <= 'b0;
else ReSeedcounter <= ReSeedcounter + 1'b1;
end
assign prbs_clk_en1 = clk_en | init_setup;
assign prbs_clk_en2 = clk_en | init_setup;
always @(posedge clk_i) begin
if (rst) begin
// add a fixed non zero value to prevent to load a zero value to the LFSR.
LFSR_Reg[3:0] <= prbs_seed_i[3:0] | 4'h5;
LFSR_Reg[PRBS_WIDTH-1:4] <= prbs_seed_i[PRBS_WIDTH-1:4];
// LFSR_Reg <= prbs_seed_i;
end else if (prbs_clk_en2) begin
// if ( PRBS_OFFSET == 0)
// $display("prbs_value = 0x%h",LFSR_Reg);
LFSR_Reg <= Next_LFSR_Reg;
prbs_shift_value <= {prbs_shift_value[2:0], LFSR_Reg[PRBS_WIDTH-1]};
end
end
always @(LFSR_Reg) begin : LFSR_Feedback
Bits0_9_zero = ~|LFSR_Reg[PRBS_WIDTH-2:0];
Feedback = LFSR_Reg[PRBS_WIDTH-1] ^ Bits0_9_zero;
// Feedback = LFSR_Reg[PRBS_WIDTH-1] ;
// for (i = 1; i <= PRBS_WIDTH - 1; i = i+1)
for (i = PRBS_WIDTH - 1; i >= 1; i = i - 1)
if (TAPS[i-1] == 1) Next_LFSR_Reg[i] = LFSR_Reg[i-1] ^ Feedback;
else Next_LFSR_Reg[i] = LFSR_Reg[i-1];
Next_LFSR_Reg[0] = Feedback; //LFSR_Reg[PRBS_WIDTH-1];// always use the last stage for feedback
end
assign prbs_o = LFSR_Reg;
endmodule
| 7.599107 |
module compare the memory read data agaisnt compare data that generated from data_gen module.
// Error signal will be asserted if the comparsion is not equal.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module tg_status #(
parameter TCQ = 100,
parameter DWIDTH = 32
)
(
input clk_i ,
input rst_i ,
input manual_clear_error,
input data_error_i ,
input [DWIDTH-1:0] cmp_data_i,
input [DWIDTH-1:0] rd_data_i ,
input [31:0] cmp_addr_i ,
input [5:0] cmp_bl_i ,
input mcb_cmd_full_i ,
input mcb_wr_full_i,
input mcb_rd_empty_i,
output reg [64 + (2*DWIDTH - 1):0] error_status,
output error
);
reg data_error_r;
reg error_set;
assign error = error_set;
always @ (posedge clk_i)
data_error_r <= #TCQ data_error_i;
always @ (posedge clk_i)
begin
if (rst_i || manual_clear_error) begin
error_status <= #TCQ 'b0;
error_set <= #TCQ 1'b0;
end
else begin
// latch the first error only
if (data_error_i && ~data_error_r && ~error_set ) begin
error_status[31:0] <= #TCQ cmp_addr_i;
error_status[37:32] <= #TCQ cmp_bl_i;
error_status[40] <= #TCQ mcb_cmd_full_i;
error_status[41] <= #TCQ mcb_wr_full_i;
error_status[42] <= #TCQ mcb_rd_empty_i;
error_set <= #TCQ 1'b1;
error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i;
error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i;
end
error_status[39:38] <= #TCQ 'b0; // reserved
error_status[63:43] <= #TCQ 'b0; // reserved
end end
endmodule
| 7.544807 |
module thcomp ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Parameters------------------------------
parameter IDLE = 1'b0, CMP = 1'b1;
//-------------Input Ports-----------------------------
input clk;
input rst_n;
input thcomptop_thcomp_start;
input [MSB:0] thcompregs_thcomp_reg_data_out0;
input [MSB:0] thcompregs_thcomp_reg_data_out1;
//-------------Output Ports----------------------------
output reg thcomp_thcomptop_finish;
output reg thcomp_thcomptop_data;
//-------------Wires-----------------------------------
wire thcomptop_thcomp_start;
//-------------Registers-------------------------------
reg state_r;
reg state_nxt;
always @* begin
state_nxt = state_r;
thcomp_thcomptop_finish = 1'b0;
thcomp_thcomptop_data = 1'b0;
case (state_r)
IDLE: begin
if (thcomptop_thcomp_start) state_nxt = CMP;
end
CMP: begin
if (thcompregs_thcomp_reg_data_out0 > thcompregs_thcomp_reg_data_out1) begin
thcomp_thcomptop_data = 1'b1;
end else begin
thcomp_thcomptop_data = 1'b0;
end
thcomp_thcomptop_finish = 1'b1;
state_nxt = IDLE;
end
endcase
end
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
state_r <= IDLE;
end else begin
state_r <= state_nxt;
end
endmodule
| 6.861777 |
module thcompregs ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Input Ports-----------------------------
input clk;
input rst_n;
input cfg_we;
input [MSB_REGS_ADDRESS:0] cfg_addr;
input [MSB:0] cfg_data_in;
input thcomptop_thcompregs_we0;
input [MSB:0] thcomptop_thcompregs_reg_data_in0;
//-------------Output Ports----------------------------
output [MSB:0] thcompregs_ctrltop_cfg_data_out0;
output [MSB:0] thcompregs_ctrltop_cfg_data_out1;
output [MSB:0] thcompregs_thcomp_reg_data_out0;
output [MSB:0] thcompregs_thcomp_reg_data_out1;
/* reg1regw2r AUTO_TEMPLATE (
.reg_data_in(thcomptop_thcompregs_reg_data_in0[MSB:0]),
.cfg_data_out(thcompregs_ctrltop_cfg_data_out0[MSB:0]),
.reg_we(thcomptop_thcompregs_we0),
.reg_data_out(thcompregs_thcomp_reg_data_out0[MSB:0]),
); */
reg1regw2r #(.MY_ADDR(THCOMPREG)) THCOMPR0 ( /*AUTOINST*/);
/* reg1cfgw2r AUTO_TEMPLATE (
.cfg_data_out(thcompregs_ctrltop_cfg_data_out1[MSB:0]),
.reg_data_out(thcompregs_thcomp_reg_data_out1[MSB:0]),
); */
reg1cfgw2r #(.MY_ADDR(THRESHOLDREG)) THCOMPR1 ( /*AUTOINST*/);
endmodule
| 6.626007 |
module thcomptop ( /*AUTOARG*/);
`include "sync_params.v"
//-------------Parameters------------------------------
parameter IDLE = 2'b00, START = 2'b01, CMP = 2'b10;
parameter MSB_STATE = 1;
//-------------Input Ports-----------------------------
input clk;
input rst_n;
input ematop_thcomptop_start;
input [MSB:0] ematop_thcomptop_data;
input cfg_we;
input [MSB:0] cfg_data_in;
input [MSB_REGS_ADDRESS:0] cfg_addr;
//-------------Output Ports----------------------------
output reg thcomptop_ctrltop_data;
output reg thcomptop_ctrltop_finish;
output [MSB:0] thcompregs_ctrltop_cfg_data_out0;
output [MSB:0] thcompregs_ctrltop_cfg_data_out1;
//-------------Registers-------------------------------
reg thcomptop_thcompregs_we0;
reg [ MSB:0] thcomptop_thcompregs_reg_data_in0;
reg thcomptop_thcomp_start;
reg [MSB_STATE:0] state_r;
reg [MSB_STATE:0] state_nxt;
/*AUTOWIRE*/
thcomp thcomp ( /*AUTOINST*/);
thcompregs THCOMPREGS ( /*AUTOINST*/);
// Sequential logic
always @(posedge clk or negedge rst_n)
if (!rst_n) begin
state_r <= IDLE;
end else begin
state_r <= state_nxt;
end
// FSM Combinatorial logic
always @* begin
state_nxt = state_r;
thcomptop_thcompregs_we0 = 1'b0;
thcomptop_thcompregs_reg_data_in0 = 0;
thcomptop_thcomp_start = 1'b0;
thcomptop_ctrltop_finish = 1'b0;
thcomptop_ctrltop_data = 0;
case (state_r)
IDLE: begin
if (ematop_thcomptop_start) begin
thcomptop_thcompregs_we0 = 1'b1;
thcomptop_thcompregs_reg_data_in0 = ematop_thcomptop_data;
state_nxt = START;
end
end
START: begin
thcomptop_thcomp_start = 1'b1;
state_nxt = CMP;
end
CMP: begin
if (thcomp_thcomptop_finish) begin
thcomptop_ctrltop_data = thcomp_thcomptop_data;
thcomptop_ctrltop_finish = 1'b1;
state_nxt = IDLE;
end
end
endcase
end
endmodule
| 6.892987 |
module regFile (
rs_address,
rt_address,
dest_address,
writeBack_data,
reg_write,
clk,
rs_data,
rt_data,
reg_file_address,
reg_file_data
); // 6 i/p , 2 o/p
input [4:0] rs_address, rt_address, reg_file_address; //address '5 bits
input [4:0] dest_address;
input [31:0] writeBack_data; // data to be saved '32 bits
input reg_write;
input clk;
output reg [31:0] rs_data,rt_data,reg_file_data; //output data from rs_address,rt_address '32 bits
reg [31:0] index[0:31]; // first is number of reg size , second is number of regs
always @(negedge clk) begin
if (reg_write) index[dest_address] <= writeBack_data;
rs_data <= index[rs_address];
rt_data <= index[rt_address];
end
integer i;
integer line = 0;
always @(reg_file_address) begin
reg_file_data <= index[reg_file_address];
end
initial begin
for (i = 0; i < 32; i = i + 1) index[i] <= 0;
end
endmodule
| 7.797802 |
module ForwardUnit (
ID_EX_RS,
ID_EX_RT,
EX_MEM_RD,
MEM_WB_RD,
ForwardA,
ForwardB,
MEM_RegWrite,
WB_RegWrite
);
input wire [4:0] ID_EX_RS, ID_EX_RT, EX_MEM_RD, MEM_WB_RD;
input wire MEM_RegWrite, WB_RegWrite;
output reg [1:0] ForwardA, ForwardB;
always @* begin
if ((MEM_RegWrite == 1) && (EX_MEM_RD != 0) && (EX_MEM_RD == ID_EX_RS)) ForwardA <= 10;
else begin
ForwardA <= 0;
end
if ((MEM_RegWrite == 1) && (EX_MEM_RD != 0) && (EX_MEM_RD == ID_EX_RT)) ForwardB <= 10;
else begin
ForwardB <= 0;
end
///////////////////////////////////////////////////////////////
//MemForwardUnit
if((WB_RegWrite == 1)&&
(MEM_WB_RD != 0)&&
(EX_MEM_RD!= ID_EX_RS)&&
(MEM_WB_RD == ID_EX_RS))
ForwardA <= 01;
else begin
ForwardA <= 0;
end
if((WB_RegWrite == 1)&&
(MEM_WB_RD != 0)&&
(EX_MEM_RD != ID_EX_RT)&&
(MEM_WB_RD == ID_EX_RT))
ForwardB <= 01;
else begin
ForwardB <= 0;
end
end
endmodule
| 6.879476 |
module testbench;
wire [31:0] pc_output, ALU_Result, Mem_out, Instr_32;
wire [31:0] reg_file_data;
reg [ 4:0] reg_file_address;
reg [31:0] read_address, write_address; //address '32 bits
reg [7:0] write_data;
reg We, clk;
wire [31:0] read_data;
reg [7:0] index[0:256];
always #100 clk = ~clk;
integer i, j, line;
integer file;
reg pc_enable = 0;
initial begin
clk = 0;
We = 1;
#5 We = 0;
#900000 file = $fopen("show.txt");
for (line = 16; line < 24; line = line + 1) begin
#1 reg_file_address = line;
#5 $fdisplay(file, "%d", reg_file_data);
end
end
processor MIPS (
write_data,
write_address,
We,
pc_output,
ALU_Result,
Mem_out,
pc_enable,
clk,
reg_file_address,
reg_file_data
); //module processor(write_data,write_address,We,pc_output,ALU_Result,Mem_out,clk);
endmodule
| 7.015571 |
module dataMem (
R1,
D1,
We,
Re,
clk,
O1
); // 5 i/p , 1 o/p
input [31:0] R1; //address '32 bits
input [31:0] D1; // data to be saved '32 bits
input We, Re;
input clk;
output reg [31:0] O1; //output data from R1 '32 bits
reg [7:0] index[0:255]; // first is number of mem size , second is number of memvalues
always @* begin
if (Re) begin
O1 <= {index[R1], index[R1+1], index[R1+2], index[R1+3]};
end else if (We) begin
index[R1] <= D1[31:24];
index[R1+1] <= D1[23:16];
index[R1+2] <= D1[15:8];
index[R1+3] <= D1[7:0];
end
end
integer i;
initial begin
for (i = 0; i < 256; i = i + 1) #5 index[i] = 0;
end
endmodule
| 6.754704 |
module InstMem (
read_address,
write_address,
write_data,
We,
clk,
read_data
); // 5 i/p , 1 o/p
input [31:0] read_address, write_address; //address '32 bits
input [7:0] write_data;
input clk, We;
output reg [31:0] read_data; //output data from R1'32 bits
reg [7:0] index[0:255]; // first is number of mem size , second is number of memvalues
initial begin
$readmemb("output.txt", index);
end
always @(posedge clk) begin
//#1 ///4eeeel el delay daaaaaaaaaaaaaaaaaaa
read_data <= {
index[read_address[7:0]],
index[read_address[7:0]+1],
index[read_address[7:0]+2],
index[read_address[7:0]+3]
};
$display("blaaaaaaaaaaaaaaa");
end
endmodule
| 6.646235 |
module signext (
ip,
op
);
input [15:0] ip;
output [31:0] op;
reg [31:0] ext;
always @(*) begin
ext[15:0] = ip;
ext[31:16] = {16{ip[15]}};
end
assign op = ext;
endmodule
| 7.970829 |
module mux_2x1_5 (
ip0,
ip1,
sel,
out
);
input sel;
input [4:0] ip1;
input [4:0] ip0;
output reg [4:0] out;
always @(*) begin
if (sel == 1'b1) begin
out <= ip1;
end else begin
out <= ip0;
end
end
endmodule
| 6.663991 |
module mux_2x1_32 (
ip0,
ip1,
sel,
out
);
input sel;
input [31:0] ip1;
input [31:0] ip0;
output reg [31:0] out;
always @(*) begin
if (sel == 1'b1) begin
out <= ip1;
end else begin
out <= ip0;
end
end
endmodule
| 7.462987 |
module mux_3x1_32 (
ip0,
ip1,
ip2,
sel,
out
);
input [1:0] sel;
input [31:0] ip1;
input [31:0] ip0;
input [31:0] ip2;
output reg [31:0] out;
always @(*) begin
if (sel == 2'b0) out <= ip0;
else if (sel == 2'b1) begin
out <= ip1;
end else if (sel == 2'b10) begin
out <= ip2;
end
end
endmodule
| 6.941975 |
module IF_ID (
clk,
input_pc,
output_pc,
input_Inst,
output_Inst
);
input wire [31:0] input_pc, input_Inst;
input clk;
output reg [31:0] output_pc, output_Inst;
always @(posedge clk) begin
output_pc <= input_pc;
output_Inst <= input_Inst;
end
endmodule
| 7.397718 |
module andg (
out,
a,
b
);
input a, b;
output reg out;
always @(*) begin
out <= a & b;
end
endmodule
| 6.551197 |
module pro_counter (
in,
clk,
reset,
out
);
input [7:0] in;
input clk;
input reset;
output reg [7:0] out;
always @(posedge clk) begin
if (reset) out <= 8'b00000000;
else out <= in;
end
endmodule
| 6.693721 |
module CONTROL_UNIT (
input [3:0] opcode,
output reg reg_sel,
output reg alu_src,
output reg reg_w_enbl,
output reg br,
output reg jump,
output reg m_r_enbl,
output reg m_w_enbl,
output reg mem_mux,
output reg [3:0] to_alu_ctrl
);
always @(opcode) begin
to_alu_ctrl <= opcode;
if (opcode == 4'b0000) begin
reg_sel <= 1'b1;
alu_src <= 1'b0;
reg_w_enbl <= 1'b1;
br <= 1'b0;
jump <= 1'b0;
m_r_enbl <= 1'b0;
m_w_enbl <= 1'b0;
mem_mux <= 1'b0;
end else if (opcode == 4'b0100) begin
reg_sel <= 1'b1;
alu_src <= 1'b1;
reg_w_enbl <= 1'b1;
br <= 1'b0;
jump <= 1'b0;
m_r_enbl <= 1'b0;
m_w_enbl <= 1'b0;
mem_mux <= 1'b0;
end else if (opcode == 4'b1011) begin
reg_sel <= 1'b1;
alu_src <= 1'b1;
reg_w_enbl <= 1'b1;
br <= 1'b0;
jump <= 1'b0;
m_r_enbl <= 1'b1;
m_w_enbl <= 1'b0;
mem_mux <= 1'b1;
end else if (opcode == 4'b1111) begin
reg_sel <= 1'b0;
alu_src <= 1'b1;
reg_w_enbl <= 1'b0;
br <= 1'b0;
jump <= 1'b0;
m_r_enbl <= 1'b0;
m_w_enbl <= 1'b1;
mem_mux <= 1'b0;
end else if (opcode == 4'b1000) begin
reg_sel <= 1'b0;
alu_src <= 1'b0;
reg_w_enbl <= 1'b0;
br <= 1'b1;
jump <= 1'b0;
m_r_enbl <= 1'b0;
m_w_enbl <= 1'b0;
mem_mux <= 1'b0;
end else if (opcode == 4'b0010) begin
reg_sel <= 1'b1;
alu_src <= 1'b0;
reg_w_enbl <= 1'b0;
br <= 1'b0;
jump <= 1'b1;
m_r_enbl <= 1'b0;
m_w_enbl <= 1'b0;
mem_mux <= 1'b0;
end else begin
reg_sel <= 1'b0;
alu_src <= 1'b0;
reg_w_enbl <= 1'b0;
br <= 1'b0;
jump <= 1'b0;
m_r_enbl <= 1'b0;
m_w_enbl <= 1'b0;
mem_mux <= 1'b0;
end
end
endmodule
| 6.766875 |
module dmem (
input [7:0] addr,
input [7:0] in,
input read,
input write,
input clk,
output [7:0] out
);
reg [7:0] out;
reg [7:0] DATA[255:0];
always @(posedge clk) begin
#1;
if (read == 1) begin
out <= DATA[addr];
end else if (write == 1) DATA[addr] <= in;
end
endmodule
| 7.276583 |
module imem (
input [ 7:0] Addr,
output [15:0] rd
);
reg [15:0] RAM[256:0];
initial begin
RAM[8'b00000000] = 16'b0100110000000101;
RAM[8'b00000001] = 16'b0100111000001010;
RAM[8'b00000010] = 16'b1111110000000000;
RAM[8'b00000011] = 16'b1111111000000001;
RAM[8'b00000100] = 16'b1011001000000000;
RAM[8'b00000101] = 16'b1011010000000001;
RAM[8'b00000110] = 16'b0000011011010000;
RAM[8'b00000111] = 16'b0100001001111111;
RAM[8'b00001000] = 16'b1000001000001010;
RAM[8'b00001001] = 16'b0010000000000110;
end
assign rd = RAM[Addr];
endmodule
| 6.860817 |
module reg_file (
input clk,
input rst,
// write port
input reg_write_en,
input [2:0] reg_write_dest,
input [7:0] reg_write_data,
//read port 1
input [2:0] reg_read_addr_1,
output [7:0] reg_read_data_1,
//read port 2
input [2:0] reg_read_addr_2,
output [7:0] reg_read_data_2
);
reg [7:0] reg_array[7:0];
always @(posedge clk)
if (rst) begin
reg_array[0] <= 8'b00000000;
reg_array[1] <= 8'b00000000;
reg_array[2] <= 8'b00000000;
reg_array[3] <= 8'b00000000;
reg_array[4] <= 8'b00000000;
reg_array[5] <= 8'b00000000;
reg_array[6] <= 8'b00000000;
reg_array[7] <= 8'b00000000;
end
always @(negedge clk) begin
if (reg_write_en) begin
reg_array[reg_write_dest] <= reg_write_data;
end
end
assign reg_read_data_1 = (reg_read_addr_1 == 0) ? 8'b0 : reg_array[reg_read_addr_1];
assign reg_read_data_2 = (reg_read_addr_2 == 0) ? 8'b0 : reg_array[reg_read_addr_2];
endmodule
| 7.294051 |
module cpu ();
reg clk = 1'b0;
reg pc_rst, reg_rst;
wire [7:0] pc_in, pc_out, inc_pc;
wire reg_sel, alu_src, reg_w_enbl, br, jump, m_r_enbl, m_w_enbl, mem_mux_sel;
wire [ 3:0] to_alu_ctrl;
wire [15:0] inst;
wire [2:0] mx_t_reg, alu_ctrl_t_alu;
wire [7:0] reg_w_data, reg_a_data, reg_b_data, alu_out, mem_out;
wire [7:0] ext_imm, mx_t_alu, imm_mux_out;
wire zero, and_t_mx;
pro_counter PC (
pc_in,
clk,
pc_rst,
pc_out
);
imem I_MEM (
pc_out,
inst
);
CONTROL_UNIT CU (
inst[15:12],
reg_sel,
alu_src,
reg_w_enbl,
br,
jump,
m_r_enbl,
m_w_enbl,
mem_mux_sel,
to_alu_ctrl
);
mux_3_bit REG_MUX (
inst[5:3],
inst[11:9],
reg_sel,
mx_t_reg
);
reg_file REG_FILE (
clk,
reg_rst,
reg_w_enbl,
inst[11:9],
reg_w_data,
inst[8:6],
reg_a_data,
mx_t_reg,
reg_b_data
);
sign_ext SIGNEXT (
inst[5:0],
ext_imm
);
mux_8_bit ALU_MUX (
ext_imm,
reg_b_data,
alu_src,
mx_t_alu
);
alu_control ALU_CTRL (
to_alu_ctrl,
inst[2:0],
alu_ctrl_t_alu
);
alu ALU (
reg_a_data,
mx_t_alu,
alu_ctrl_t_alu,
alu_out,
zero
);
dmem D_MEM (
alu_out,
reg_b_data,
m_r_enbl,
m_w_enbl,
clk,
mem_out
);
mux_8_bit MEM_MUX (
mem_out,
alu_out,
mem_mux_sel,
reg_w_data
);
pc_incrmntr PC_INCR (
pc_out,
inc_pc
);
andg ANDG (
and_t_mx,
zero,
br
);
mux_8_bit IMM_MUX (
ext_imm,
inc_pc,
and_t_mx,
imm_mux_out
);
mux_8_bit JUM_MUX (
inst[7:0],
imm_mux_out,
jump,
pc_in
);
always #5 clk = ~clk;
initial begin
pc_rst = 1;
reg_rst = 1;
$monitor($time, " reg _1 %d reg_2 = %d reg_3 = %d data[0] = %d data[0] = %d",
REG_FILE.reg_array[1], REG_FILE.reg_array[2], REG_FILE.reg_array[3], D_MEM.DATA[0],
D_MEM.DATA[1]);
#6;
pc_rst = 0;
reg_rst = 0;
#1000;
$finish;
end
endmodule
| 6.915037 |
module thedesign (
input wire i_clk,
input wire i_reset,
input wire i_btn,
`ifdef VERILATOR
output wire [31:0] o_setup,
`endif
`ifdef USB_UART
input wire i_clk48,
inout wire usb_p,
inout wire usb_n,
`endif
output wire o_uart_tx,
output wire [7:0] o_debug
);
wire tx_stb, tx_busy, debounced;
reg btn_event, last_debounced;
wire [31:0] counter, tx_data;
parameter CLOCK_RATE_HZ = 16_000_000;
parameter BAUD_RATE = 115200;
parameter UART_SETUP = CLOCK_RATE_HZ / BAUD_RATE;
`ifdef VERILATOR
assign o_setup = UART_SETUP;
`endif
debouncer mydebouncer (
.i_clk(i_clk),
.i_btn(i_btn),
.o_debounced(debounced)
);
initial last_debounced = 0;
always @(posedge i_clk) last_debounced <= debounced;
initial btn_event = 0;
always @(posedge i_clk) btn_event <= (debounced && !last_debounced);
counter mycounter (
.i_clk(i_clk),
.i_event(btn_event),
.i_busy(0),
.i_reset(i_reset),
.o_counter(counter)
);
chgdetector mychgdetector (
.i_clk (i_clk),
.i_data(counter),
.i_busy(tx_busy),
.o_stb (tx_stb),
.o_data(tx_data)
);
txdata #(
.UART_SETUP(UART_SETUP[23:0])
) myuart (
.i_clk(i_clk),
.i_stb(tx_stb),
.i_data(tx_data),
.i_reset(i_reset),
.o_uart_tx(o_uart_tx),
.o_busy(tx_busy),
`ifdef USB_UART
.i_clk48(i_clk48),
.usb_n(usb_n),
.usb_p(usb_p),
`endif
.o_debug(o_debug)
);
endmodule
| 7.893862 |
module theFFT (
clk,
reset_n,
inverse,
sink_valid,
sink_sop,
sink_eop,
sink_real,
sink_imag,
sink_error,
source_ready,
sink_ready,
source_error,
source_sop,
source_eop,
source_valid,
source_exp,
source_real,
source_imag
);
input clk;
input reset_n;
input inverse;
input sink_valid;
input sink_sop;
input sink_eop;
input [17:0] sink_real;
input [17:0] sink_imag;
input [1:0] sink_error;
input source_ready;
output sink_ready;
output [1:0] source_error;
output source_sop;
output source_eop;
output source_valid;
output [5:0] source_exp;
output [17:0] source_real;
output [17:0] source_imag;
endmodule
| 7.019736 |
module thermometer_to_bcd (
bcd,
thermometer
);
output [7:0] bcd;
input [15:0] thermometer;
assign bcd = (thermometer == 16'b0) ? 0 :
(thermometer == 16'b1) ? 1 :
(thermometer == 16'b11) ? 2 :
(thermometer == 16'b111) ? 3 :
(thermometer == 16'b1111) ? 4 :
(thermometer == 16'b11111) ? 5 :
(thermometer == 16'b111111) ? 6 :
(thermometer == 16'b1111111) ? 7 :
(thermometer == 16'b11111111) ? 8 :
(thermometer == 16'b111111111) ? 9 :
(thermometer == 16'b1111111111) ? 9 :
(thermometer == 16'b11111111111) ? {4'd1, 4'd0} :
(thermometer == 16'b111111111111) ? {4'd1, 4'd1} :
(thermometer == 16'b1111111111111) ? {4'd1, 4'd2} :
(thermometer == 16'b11111111111111) ? {4'd1, 4'd3} :
(thermometer == 16'b111111111111111) ? {4'd1, 4'd4} :
(thermometer == 16'b1111111111111111) ? {4'd1, 4'd5} :
{4'd1, 4'd6};
endmodule
| 7.27633 |
module thermometer_to_bcd_tb;
wire [ 7:0] bcd;
reg [15:0] thermometer = 0;
thermometer_to_bcd translator (
bcd,
thermometer
);
initial begin
$monitor("thermometer: %b, bcd: %b, dec: %d%d", thermometer, bcd, bcd[7:4], bcd[3:0]);
repeat (16) #5 thermometer = {thermometer[14:0], 1'b1};
$finish;
end
endmodule
| 7.27633 |
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode & too_cold;
assign aircon = ~mode & too_hot;
assign fan = (mode & too_cold) | (~mode & too_hot) | fan_on;
endmodule
| 7.203305 |
module thermo_maj (
in1,
in2,
in3,
in4,
out
);
input [14:0] in1, in2, in3, in4;
output [3:0] out;
wire [14:0] thermo_out;
majority maj0 (
.in1(in1),
.in2(in2),
.in3(in3),
.in4(in4),
.out(thermo_out)
);
thermo_to_bin encoder0 (
.thermo(thermo_out),
.bin(out)
);
endmodule
| 6.811401 |
module thermo_to_onehot (
thermo,
onehot
);
input [14:0] thermo;
output reg [15:0] onehot;
integer i;
always @(thermo) begin
if (thermo[0] == 0) onehot[0] = 1;
else onehot[0] = 0;
onehot[15] = thermo[14];
for (i = 14; i > 0; i = i - 1) begin
onehot[i] = thermo[i] ^ thermo[i-1];
end
end
endmodule
| 6.77721 |
module therm_out (
input wire clk,
input wire rst,
input wire [31:0] therm_in,
output wire therm_do,
output wire therm_fs
);
reg [5:0] therm_in_buf;
wire [4:0] therm_z;
count_lead_zero #(
.W_IN (32),
.W_OUT(5)
) clz (
.in (therm_in_buf),
.out(therm_z)
);
reg [4:0] sr;
reg [3:0] counter;
always @(posedge clk) begin
if (counter == 3'd4) begin
counter <= 0;
therm_in_buf <= therm_in;
sr <= therm_z;
end else begin
counter <= counter + 1;
end
if (rst) begin
counter <= 0;
end
end
wire therm_fs_pre = counter == 0;
wire therm_do_pre = sr[counter];
sky130_fd_sc_hd__buf_16 fs_buf (
.A(therm_fs_pre),
.X(therm_fs)
);
sky130_fd_sc_hd__buf_16 do_buf (
.A(therm_do_pre),
.X(therm_do)
);
endmodule
| 6.82457 |
module count_lead_zero #(
parameter W_IN = 64, // Must be power of 2, >=2
parameter W_OUT = 6
) (
input wire [ W_IN-1:0] in,
output wire [W_OUT-1:0] out
);
generate
if (W_IN == 2) begin : base
assign out = !in[1];
end else begin : recurse
wire [ W_OUT-2:0] half_count;
wire [W_IN / 2-1:0] lhs = in[W_IN/2+:W_IN/2];
wire [W_IN / 2-1:0] rhs = in[0+:W_IN/2];
wire left_empty = ~|lhs;
count_lead_zero #(
.W_IN(W_IN / 2)
) inner (
.in (left_empty ? rhs : lhs),
.out(half_count)
);
assign out = {left_empty, half_count};
end
endgenerate
endmodule
| 7.246378 |
module.
module BCD_TO_7SEG(
bcd,
leds
);
// Declare inputs, outputs and internal variables.
input [3:0] bcd;
output reg [6:0] leds;
// always block for converting bcd digit into 7 segment format
always @ (*) begin
case (bcd)
4'b0000 : leds = 7'b1111110; // O or 0
4'b0001 : leds = 7'b0110000;
4'b0010 : leds = 7'b1101101;
4'b0011 : leds = 7'b1111001;
4'b0101 : leds = 7'b1011011;
4'b0110 : leds = 7'b1011111;
4'b0111 : leds = 7'b1110000;
4'b1000 : leds = 7'b1111111;
4'b1001 : leds = 7'b1110011;
4'b1010 : leds = 7'b1100111; // P
4'b1011 : leds = 7'b1001111; // E
4'b1100 : leds = 7'b0010101; // n
4'b1101 : leds = 7'b0001110; // L
4'b1110 : leds = 7'b0001101; // c
4'b1111 : leds = 7'b0110111; // k
// switch off 7 segment character when the bcd digit is not a decimal number.
default : leds = 7'b0000000;
endcase
end
endmodule
| 8.215158 |
module the_test (
input tb_clk,
input tb_rst
);
reg [31:0] d_out;
task run_the_test;
begin
// --------------------------------------------------------------------
// insert test below
// --------------------------------------------------------------------
repeat (6) @(posedge tb_clk);
// wbm.wb_write(0, 0, 32'h6000_0004, 32'habba_beef);
// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);
// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000);
// repeat(2) @(posedge tb_clk);
//
// wbm.wb_write(0, 0, 32'h6000_0004, 32'hcafe_1a7a);
// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);
// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000);
// repeat(2) @(posedge tb_clk);
//
// wbm.wb_write(0, 0, 32'h6000_0004, 32'h3333_3333);
// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);
// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000);
// repeat(2) @(posedge tb_clk);
//
//
// wbm.wb_write(0, 0, 32'h6000_0004, 32'hffff_ffff);
// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);
// wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0000);
// repeat(2) @(posedge tb_clk);
wbm.wb_write(0, 0, 32'h6000_0010, 32'h8001_0000);
repeat (2) @(posedge tb_clk);
// enable i2s
repeat (2) @(posedge tb_clk);
rx_bfm.enable_bfm();
repeat (2) @(posedge tb_clk);
wbm.wb_write(0, 0, 32'h6000_0000, 32'h0000_0001);
// repeat(6*32) @(posedge tb_clk);
repeat ('h72) @(posedge i_i2s_to_wb_top.i2s_ws_i);
// --------------------------------------------------------------------
// insert test above
// --------------------------------------------------------------------
end
endtask
endmodule
| 7.031746 |
module The_Top (
input clk_in,
input reset,
input key_clk,
input key_data,
output [7:0] o_seg,
output [7:0] o_sel
);
wire clk;
wire key_state;
wire [7:0] key_ascii;
wire [31:0] final_num;
Divider #(800) divider (
clk_in,
reset,
clk
);
Keyboard_PS2 keyboard (
clk,
reset,
key_clk,
key_data,
key_state,
key_ascii
);
Input_Num inputnum (
reset,
key_state,
key_ascii,
final_num
);
seg7x16(
clk_in, reset, 1, final_num, o_seg, o_sel
);
endmodule
| 7.977606 |
modules in order to be authentic to the SM83 topology. We will leave the architectural solution as an appendix to the developers of the SM83.
module Thingy ( w8, w31, w35, ALU_to_Thingy, WR, Temp_Z, TTB1, TTB2, TTB3, Thingy_to_bot, bot_to_Thingy );
input w8;
input w31;
input w35;
input ALU_to_Thingy;
input WR;
input Temp_Z; // Flag Z from temp Z register (zbus[7])
output TTB1; // 1: Perform pairwise increment/decrement (simultaneously for two 8-bit IncDec halves)
output TTB2; // 1: Perform decrement
output TTB3; // 1: Perform increment
input bot_to_Thingy; // IE access detected (Address = 0xffff)
output Thingy_to_bot; // Load a value into the IE register from the DL bus.
wire t1;
wire t2;
assign t1 = ~(w8 & ALU_to_Thingy & ~Temp_Z);
assign t2 = ~(w8 & ~ALU_to_Thingy & Temp_Z);
assign TTB1 = ~(t1 & t2);
assign TTB2 = ~(~w35 & t2);
assign TTB3 = ~(~w31 & t1);
assign Thingy_to_bot = bot_to_Thingy & WR;
endmodule
| 7.347743 |
module add (
out,
A,
B
);
output [63:0] out;
input [63:0] A;
input [63:0] B;
assign out = A + B;
endmodule
| 6.843391 |
module And (
out,
A,
B
);
output [63:0] out;
input [63:0] A;
input [63:0] B;
assign out = A & B;
endmodule
| 6.789627 |
module Xor (
out,
A,
B
);
output [63:0] out;
input [63:0] A;
input [63:0] B;
assign out = A ^ B;
endmodule
| 7.144897 |
module ThirdTap (
rst,
clk,
Xin,
Yout
);
input rst; //复位信号，高电平有效
input clk; //FPGA系统时钟，频率为2kHz
input signed [8:0] Xin; //数据输入频率为2kHZ
output signed [10:0] Yout; //滤波后的输出数据
//零点系数的实现代码/////////////////////////
//将输入数据存入移位寄存器中
reg signed [8:0] Xin1, Xin2;
always @(posedge clk or posedge rst)
if (rst)
//初始化寄存器值为0
begin
Xin1 <= 9'd0;
Xin2 <= 9'd0;
end else begin
Xin1 <= Xin;
Xin2 <= Xin1;
end
//采用移位运算及加法运算实现乘法运算
wire signed [23:0] XMult0, XMult1, XMult2;
assign XMult0 = {{5{Xin[8]}}, Xin, 10'd0}; //*1024
assign XMult1 = {{10{Xin1[8]}},Xin1,5'd0}+{{11{Xin1[8]}},Xin1,4'd0}+{{13{Xin1[8]}},Xin1,2'd0}; //*52
assign XMult2 = {{5{Xin2[8]}}, Xin2, 10'd0}; //*1024
//对滤波器系数与输入数据乘法结果进行累加
wire signed [23:0] Xout;
assign Xout = XMult0 + XMult1 + XMult2;
//极点系数的实现代码///////////////////////
wire signed [10:0] Yin;
reg signed [10:0] Yin1, Yin2;
always @(posedge clk or posedge rst)
if (rst)
//初始化寄存器值为0
begin
Yin1 <= 11'd0;
Yin2 <= 11'd0;
end else begin
Yin1 <= Yin;
Yin2 <= Yin1;
end
//采用移位运算及加法运算实现乘法运算
wire signed [23:0] YMult1, YMult2;
wire signed [23:0] Ysum, Ydiv;
assign YMult1 = {{4{Yin1[10]}},Yin1,9'd0}+{{5{Yin1[10]}},Yin1,8'd0}+{{8{Yin1[10]}},Yin1,5'd0}+
{{11{Yin1[10]}},Yin1,2'd0}+{{13{Yin1[10]}},Yin1}; //*805
assign YMult2 = {{3{Yin2[10]}},Yin2,10'd0}-{{5{Yin2[10]}},Yin2,8'd0}-{{9{Yin2[10]}},Yin2,4'd0}-
{{10{Yin2[10]}},Yin2,3'd0}-{{13{Yin2[10]}},Yin2}; //*743
//第三级IIR滤波器实现代码///////////////////////////
assign Ysum = Xout + YMult1 - YMult2;
assign Ydiv = {{10{Ysum[23]}}, Ysum[23:10]}; //1204
//根据仿真结果可知，第4级滤波器的输出范围可用11位表示
assign Yin = (rst ? 11'd0 : Ydiv[10:0]);
//增加一级寄存器，提高运行速度
reg signed [10:0] Yout_reg;
always @(posedge clk) Yout_reg <= Yin;
assign Yout = Yout_reg;
endmodule
| 7.175866 |
module third_assign_osc (
CLOCK_50,
SWTCH,
VGA_CLK,
VGA_VS,
VGA_HS,
VGA_BLANK_n,
VGA_B,
VGA_G,
VGA_R
);
input CLOCK_50;
input SWTCH;
output VGA_CLK;
output VGA_VS;
output VGA_HS;
output VGA_BLANK_n;
output wire [7:0] VGA_B;
output wire [7:0] VGA_G;
output wire [7:0] VGA_R;
wire VGA_BLANK_n, VGA_HS, VGA_VS, VGA_CLK;
////////////////////////////////////////////
//wire to hold the signal
wire [15:0] ValSignal1;
wire [15:0] ValSignal2;
wire [15:0] ValSignal;
///////////////////////////////////////////
// signal_generator instance
signal_generator sg_ins (
.CLOCK_50(CLOCK_50),
.signal (ValSignal1)
);
signal_generator2 sg_ins2 (
.CLOCK_50(CLOCK_50),
.signal (ValSignal2)
);
// bfsk modulator instance
bfsk_modulator bfsk_mod_ins (
.CLOCK_50(CLOCK_50),
.signal1 (ValSignal1),
.signal2 (ValSignal2),
.signal (ValSignal)
);
/////////////////////////////////////////////
//oscilloscope instance
oscilloscope osc_ins (
.CLOCK_50(CLOCK_50),
.SWTCH (SWTCH),
.signal (ValSignal),
.oVGA_CLK(VGA_CLK),
.oVS (VGA_VS),
.oHS (VGA_HS),
.oBLANK_n(VGA_BLANK_n),
.b_data (VGA_B),
.g_data (VGA_G),
.r_data (VGA_R)
);
endmodule
| 7.499189 |
module: thirteen
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module thirteen_test;
// Inputs
reg MR;
reg LOAD;
reg EN;
reg UpDown;
reg CLK;
reg [3:0] D;
// Outputs
wire [3:0] Q;
wire CO;
// Instantiate the Unit Under Test (UUT)
thirteen uut (
.MR(MR),
.LOAD(LOAD),
.EN(EN),
.UpDown(UpDown),
.CLK(CLK),
.D(D),
.Q(Q),
.CO(CO)
);
always #10 CLK=~CLK;
initial begin
// Initialize Inputs
MR = 1;LOAD = 0;EN = 1;UpDown = 0;CLK = 0;D = 0;#30;
MR = 0;LOAD = 0;EN = 1;UpDown = 0;D = 4'b1100;#50;
MR = 0;LOAD = 1;EN = 1;UpDown = 0;D = 4'b1100;#270;
MR = 0;LOAD = 1;EN = 1;UpDown = 1;D = 4'b1100;#300;
MR = 0;LOAD = 1;EN = 0;UpDown = 1;D = 4'b1100;#100;
// Wait 100 ns for global reset to finish
// Add stimulus here
end
endmodule
| 6.71885 |
module ThirtyTwoBitAdderTB ();
reg [31:0] A;
reg [31:0] B;
reg cin;
wire [31:0] sum;
wire cout;
wire overFlow;
ThirtyTwoBitAdder uut (
.A,
.B,
.cin,
.sum,
.cout,
.overFlow
);
initial begin
assign cin = 0;
assign A = 32'b01010100101100111101010011000011;
assign B = 32'b00101101011101010000000101110111;
end
endmodule
| 6.829372 |
module ThirtyTwoBitSub (
input [31:0] B,
input [31:0] A,
input cin,
output [31:0] Diff
);
//cin = 1 to be subtraction
wire [31:0] Ba;
wire [31:0] ecin;
wire cout;
wire overFlow;
//[31:0] array of cins --> bitwise XORed with B --> this bitwise XORed value then will go into B
// if Cin is 1 then B is being subtracted, if Cin is 0 then it is being added
// this module will now determine if we are adding or subtracting
assign ecin = {{(31) {cin}}, cin};
assign Ba = B ^ ecin;
//keep in mind that this can be implmeneted to be the adder/subtractor module. If we were to
//take the cin, make it a 32 bit array of the same value, xor it with B and feed it into the Cin
//of the adder instantiation, we can control if it adds or subtracts all from one set of inputs.
ThirtyTwoBitAdder u0 (
.A(A),
.B(Ba),
.cin(cin),
.sum(Diff),
.cout(cout),
.overFlow(overFlow)
);
endmodule
| 7.948503 |
module ThirtyTwoBitSubTB ();
reg [31:0] A;
reg [31:0] B;
reg cin;
wire [31:0] Diff;
ThirtyTwoBitSub uut (
.A,
.B,
.cin,
.Diff
);
initial begin
assign A = 32'b01010100101100111101010011000011;
assign B = 32'b00101101011101010000000101110111;
assign cin = 1;
end
endmodule
| 7.948503 |
module thirty_second_timer (
clk,
rst,
show,
ssd_active
);
input clk, rst;
output [7:0] show;
output [3:0] ssd_active;
reg [4:0] q_temp;
reg [4:0] q;
reg [7:0] a;
reg [7:0] b;
reg [7:0] show;
reg [3:0] ssd_active;
wire clk_1hz;
wire ssd_ctrl;
frequency_divider_about_1hz U0 (
.clk(clk),
.rst(rst),
.k (clk_1hz),
.a (ssd_ctrl)
);
//frequency_divider_exact_1hz U1 (.clk(clk), .rst(rst), .clk_out(ssd_ctrl));
always @* begin
q_temp = q - 1'b1;
end
always @(posedge clk_1hz or negedge rst) begin
if (~rst) begin
q <= 5'd30;
end else begin
q <= q_temp;
end
end
always @* begin
case (q)
5'd00: a = `SS_0;
5'd01: a = `SS_0;
5'd02: a = `SS_0;
5'd03: a = `SS_0;
5'd04: a = `SS_0;
5'd05: a = `SS_0;
5'd06: a = `SS_0;
5'd07: a = `SS_0;
5'd08: a = `SS_0;
5'd09: a = `SS_0;
5'd10: a = `SS_1;
5'd11: a = `SS_1;
5'd12: a = `SS_1;
5'd13: a = `SS_1;
5'd14: a = `SS_1;
5'd15: a = `SS_1;
5'd16: a = `SS_1;
5'd17: a = `SS_1;
5'd18: a = `SS_1;
5'd19: a = `SS_1;
5'd20: a = `SS_2;
5'd21: a = `SS_2;
5'd22: a = `SS_2;
5'd23: a = `SS_2;
5'd24: a = `SS_2;
5'd25: a = `SS_2;
5'd26: a = `SS_2;
5'd27: a = `SS_2;
5'd28: a = `SS_2;
5'd29: a = `SS_2;
5'd30: a = `SS_3;
default: a = `SS_F;
endcase
end
always @* begin
case (q)
5'd00: b = `SS_0;
5'd01: b = `SS_1;
5'd02: b = `SS_2;
5'd03: b = `SS_3;
5'd04: b = `SS_4;
5'd05: b = `SS_5;
5'd06: b = `SS_6;
5'd07: b = `SS_7;
5'd08: b = `SS_8;
5'd09: b = `SS_9;
5'd10: b = `SS_0;
5'd11: b = `SS_1;
5'd12: b = `SS_2;
5'd13: b = `SS_3;
5'd14: b = `SS_4;
5'd15: b = `SS_5;
5'd16: b = `SS_6;
5'd17: b = `SS_7;
5'd18: b = `SS_8;
5'd19: b = `SS_9;
5'd20: b = `SS_0;
5'd21: b = `SS_1;
5'd22: b = `SS_2;
5'd23: b = `SS_3;
5'd24: b = `SS_4;
5'd25: b = `SS_5;
5'd26: b = `SS_6;
5'd27: b = `SS_7;
5'd28: b = `SS_8;
5'd29: b = `SS_9;
5'd30: b = `SS_0;
default: b = `SS_F;
endcase
end
always @* begin
if (ssd_ctrl == 1'b0) begin
ssd_active = 4'b1110;
show = b;
end else begin
ssd_active = 4'b1101;
show = a;
end
end
endmodule
| 7.43344 |
module thirty_two_bit_alu (
a,
b,
inp,
out
);
input [31:0] a, b;
input [2:0] inp;
output reg [31:0] out;
always @(inp) begin
case (inp)
3'b000: out = 0; //clear
3'b001: out = a + b; //addition
3'b010: out = a - b; //subtraction
3'b011: out = a << 1; //left shift
3'b100: out = a >> 1; //right shift
3'b101: out = a & b; //AND
3'b110: out = a | b; //OR
3'b111: out = a ^ b; //XOR
endcase
end
endmodule
| 6.672265 |
module thirty_two_bit_cla (
a,
b,
c0,
s,
cout
);
input [31:0] a, b; //32 bit input
input c0;
output [31:0] s;
output cout;
//32 bit CLA made from 8 4-bit CLA
wire c1, c2, c3, c4, c5, c6, c7;
carry_look CA1 (
a[3:0],
b[3:0],
c0,
s[3:0],
c1
);
carry_look CA2 (
a[7:4],
b[7:4],
c1,
s[7:4],
c2
);
carry_look CA3 (
a[11:8],
b[11:8],
c2,
s[11:8],
c3
);
carry_look CA4 (
a[15:12],
b[15:12],
c3,
s[15:12],
c4
);
carry_look CA5 (
a[19:16],
b[19:16],
c4,
s[19:16],
c5
);
carry_look CA6 (
a[23:20],
b[23:20],
c5,
s[23:20],
c6
);
carry_look CA7 (
a[27:24],
b[27:24],
c6,
s[27:24],
c7
);
carry_look CA8 (
a[31:28],
b[31:28],
c7,
s[31:28],
cout
);
endmodule
| 6.672265 |
module thirty_two_bit_cselect (
a,
b,
c0,
s,
cout
);
input [31:0] a, b;
input c0;
output [31:0] s;
output cout;
//32 bit carry select adder with 8 4-bit carry select adder
wire [3:0] x, y, c1, c2, c3, c4, c5, c6, c7, c8;
carry_select CSL1 (
a[3:0],
b[3:0],
c0,
s[3:0],
c1
);
carry_select CSL2 (
a[7:4],
b[7:4],
c1,
s[7:4],
c2
);
carry_select CSL3 (
a[11:8],
b[11:8],
c2,
s[11:8],
c3
);
carry_select CSL4 (
a[15:12],
b[15:12],
c3,
s[15:12],
c4
);
carry_select CSL5 (
a[19:16],
b[19:16],
c4,
s[19:16],
c5
);
carry_select CSL6 (
a[23:20],
b[23:20],
c5,
s[23:20],
c6
);
carry_select CSL7 (
a[27:24],
b[27:24],
c6,
s[27:24],
c7
);
carry_select CSL8 (
a[31:28],
b[31:28],
c7,
s[31:28],
cout
);
endmodule
| 6.672265 |
module thirty_two_bit_cskip (
a,
b,
c0,
s,
cout
);
input [31:0] a, b;
input c0;
output [31:0] s;
output cout;
//32 bit carry skip adder with 8 4-bit Carry Skip Adder
wire c1, c2, c3, c4, c5, c6, c7;
carry_skip CS1 (
a[3:0],
b[3:0],
c0,
s[3:0],
c1
);
carry_skip CS2 (
a[7:4],
b[7:4],
c1,
s[7:4],
c2
);
carry_skip CS3 (
a[11:8],
b[11:8],
c2,
s[11:8],
c3
);
carry_skip CS4 (
a[15:12],
b[15:12],
c3,
s[15:12],
c4
);
carry_skip CS5 (
a[19:16],
b[19:16],
c4,
s[19:16],
c5
);
carry_skip CS6 (
a[23:20],
b[23:20],
c5,
s[23:20],
c6
);
carry_skip CS7 (
a[27:24],
b[27:24],
c6,
s[27:24],
c7
);
carry_skip CS8 (
a[31:28],
b[31:28],
c7,
s[31:28],
cout
);
endmodule
| 6.672265 |
module thread_number #(
parameter N_CORES = -1,
parameter N_THREADS = 2 * N_CORES,
parameter N_THREADS_MSB = `MSB(N_THREADS - 1)
) (
input CLK,
input entry_pt_switch,
output [N_THREADS_MSB : 0] ts_rd_num,
input [`THREAD_STATE_MSB : 0] ts_rd,
input NEXT_THREAD,
output RELOAD,
output reg [`MSB(N_THREADS-1) : 0] thread_num = 0,
thread_num_ahead = 1,
output reg thread_init = 1
);
reg suspended_r = 1;
// Next thread (in sequence)
wire [`MSB(N_THREADS-1) : 0] thread_num_next;
next_thread_num #(
.N_CORES(N_CORES)
) next_thread_num (
.in (thread_num),
.out(thread_num_next)
);
// Look ahead for WR_RDY thread
assign ts_rd_num = thread_num_ahead;
wire thread_ahead_not_ready = ts_rd != `THREAD_STATE_WR_RDY;
wire [`MSB(N_THREADS-1) : 0] thread_num_ahead_next;
next_thread_num #(
.N_CORES(N_CORES)
) next_thread_num_ahead (
.in (thread_num_ahead),
.out(thread_num_ahead_next)
);
// Allow to select the same thread after thread_state propagates
localparam TS_DELAY = 2;
reg [TS_DELAY-1:0] allow_same_thread = {TS_DELAY{1'b0}};
always @(posedge CLK) allow_same_thread <= {allow_same_thread[TS_DELAY-2:0], suspended_r};
task thread_num_ahead_next_set;
begin
thread_num_ahead <= (thread_num_ahead_next == thread_num
& ~allow_same_thread[TS_DELAY-1])
? thread_num_next : thread_num_ahead_next;
end
endtask
always @(posedge CLK) begin
if (entry_pt_switch) thread_init <= 1;
if (thread_init) begin // traverse all threads on init
thread_num <= thread_num_next;
if (thread_num == N_THREADS - 1) thread_init <= 0;
end else begin
if (suspended_r & ~thread_ahead_not_ready) begin
suspended_r <= 0;
thread_num <= thread_num_ahead;
thread_num_ahead_next_set();
end else if (NEXT_THREAD) begin
if (thread_ahead_not_ready) begin
suspended_r <= 1;
end else begin
thread_num <= thread_num_ahead;
thread_num_ahead_next_set();
end
end else begin
if (thread_ahead_not_ready) thread_num_ahead_next_set();
end
end
end
assign RELOAD = ~thread_init & (
suspended_r & ~thread_ahead_not_ready
| NEXT_THREAD & ~thread_ahead_not_ready
);
`ifdef SIMULATION
reg [31:0] X_CYCLES_TOTAL = 0;
reg [31:0] X_CYCLES_SUSPENDED = 0;
always @(posedge CLK) begin
X_CYCLES_TOTAL <= X_CYCLES_TOTAL + 1'b1;
if (suspended_r) X_CYCLES_SUSPENDED <= X_CYCLES_SUSPENDED + 1'b1;
end
`endif
endmodule
| 6.849515 |
module three (
G1,
G2,
G3,
A,
Y
);
input G1, G2, G3;
input [2:0] A;
output [7:0] Y;
wire G1, G2, G3;
wire [2:0] A;
reg [7:0] Y;
always @(A, G1, G2, G3) begin
if (~G1 | G2 | G3) Y = 8'b1111_1111;
else
case (A)
3'b000: Y = 8'b1111_1110;
3'b001: Y = 8'b1111_1101;
3'b010: Y = 8'b1111_1011;
3'b011: Y = 8'b1111_0111;
3'b100: Y = 8'b1110_1111;
3'b101: Y = 8'b1101_1111;
3'b110: Y = 8'b1011_1111;
3'b111: Y = 8'b0111_1111;
endcase
end
endmodule
| 6.570476 |
module tb_comparator3 ();
reg [2:0] A;
reg [2:0] B;
reg l;
reg e;
reg g;
wire lt;
wire eq;
wire gt;
comparator3 test_comparator3 (
.A (A),
.B (B),
.l (l),
.e (e),
.g (g),
.lt(lt),
.eq(eq),
.gt(gt)
);
initial begin
A = 3'b001;
B = 3'b001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
A = 3'b010;
B = 3'b001;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
//////////////////
A = 3'b001;
B = 3'b010;
l = 1'b0;
e = 1'b1;
g = 1'b0;
#10;
l = 1'b1;
e = 1'b0;
g = 1'b0;
#10;
l = 1'b0;
e = 1'b0;
g = 1'b1;
#20;
$finish;
//////////////////
end
endmodule
| 6.843472 |
module threeBitDFFupCounterWasynClock (
count,
Clk,
ClrN
);
output [2:0] count;
input Clk, ClrN;
wire w2, w1, w0;
wire [2:0] dummy;
dFlipFlopNegClkNegRst
c0 (
w0,
dummy[0],
~w0,
Clk,
ClrN
),
c1 (
w1,
dummy[1],
~w1,
w0,
ClrN
),
c2 (
w2,
dummy[2],
~w2,
w1,
ClrN
);
assign count[0] = w0, count[1] = w1, count[2] = w2;
endmodule
| 7.228737 |
module threeBitDFFupCounterWasynClock_tb;
input [2:0] count;
output reg Clk, ClrN;
threeBitDFFupCounterWasynClock dffAsynClock (
count,
Clk,
ClrN
);
initial /*stimulus*/
begin
$dumpfile("Simulation/threeBitDFFupCounterWasynClock_tb.vcd");
$dumpvars;
$monitor($time, " Clk=%b, ClrN=%b -> count=%3b", Clk, ClrN, count);
ClrN = 0;
Clk = 0;
end
initial begin
#45;
ClrN = 1;
#1000 $finish;
end
always begin
#20 Clk = ~Clk;
end
endmodule
| 7.228737 |
module threebit_adder (
input carry_in,
input [2:0] a,
input [2:0] b,
output [2:0] sum,
output carry_out
);
// internal signals
wire stage1_carry;
wire stage2_carry;
full_adder stage1 (
.carry_in(carry_in),
.a(a[0]),
.b(b[0]),
.sum(sum[0]),
.carry_out(stage1_carry)
);
full_adder stage2 (
.carry_in(stage1_carry),
.a(a[1]),
.b(b[1]),
.sum(sum[1]),
.carry_out(stage2_carry)
);
full_adder stage3 (
.carry_in(stage2_carry),
.a(a[2]),
.b(b[2]),
.sum(sum[2]),
.carry_out(carry_out)
);
endmodule
| 8.166291 |
module threebit_adder_tb;
// Inputs
reg [2:0] t_a;
reg [2:0] t_b;
reg t_carry_in;
// Outputs
wire [2:0] t_sum;
wire t_carry_out;
// Instantiate the Unit Under Test (UUT)
threebit_adder UUT (
.carry_in(t_carry_in),
.a(t_a),
.b(t_b),
.sum(t_sum),
.carry_out(t_carry_out)
);
initial begin
$dumpfile("haout.vcd");
$dumpvars(1, threebit_adder_tb);
t_a = 0;
t_b = 0;
t_carry_in = 0;
#10 $display("a=%d, b=%d, cin=%d, s=%d, cout=%d", t_a, t_b, t_carry_in, t_sum, t_carry_out);
t_a = 3;
t_b = 4;
t_carry_in = 0;
#10 $display("a=%d, b=%d, cin=%d, s=%d, cout=%d", t_a, t_b, t_carry_in, t_sum, t_carry_out);
t_a = 2;
t_b = 2;
t_carry_in = 0;
#10 $display("a=%d, b=%d, cin=%d, s=%d, cout=%d", t_a, t_b, t_carry_in, t_sum, t_carry_out);
t_a = 3'd5;
t_b = 3'd1;
t_carry_in = 0;
#10 $display("a=%d, b=%d, cin=%d, s=%d, cout=%d", t_a, t_b, t_carry_in, t_sum, t_carry_out);
$stop;
end
endmodule
| 8.166291 |
module represents a three by one mux.
**********************************************************************/
`timescale 1ns / 1ps
module threebyone_MUX(input [31:0] A, [31:0] B, [31:0] C,input [1:0]S, output reg[31:0] r );
always @(*) begin
case(S)
2'b00: r=A;
2'b01: r=B;
2'b10: r=C;
default: r=A;
endcase
end
endmodule
| 7.311982 |
module ThreeInOneSelector5Bit (
input [1:0] Control,
input [4:0] OneInput,
input [4:0] TwoInput,
output reg [4:0] DataOutput
);
always @(Control or TwoInput or OneInput) begin
if (Control == 2'b00) DataOutput = 5'b11111;
else if (Control == 2'b01) DataOutput = OneInput;
else if (Control == 2'b10) DataOutput = TwoInput;
else DataOutput = 5'bzzzzz;
end
endmodule
| 6.944395 |
module ThreeInputOrGate (
input i1,
input i2,
input i3,
output gateOutput
);
or (gateOutput, i1, i2, i3);
endmodule
| 7.420145 |
module ThreeMusicNotes (
keyC,
keyD,
keyE,
Speaker,
Reset,
Clock
);
parameter NumberOfBits = 20;
input keyC, keyD, keyE, Reset, Clock;
output Speaker;
wire [NumberOfBits-1:0] NoteC, NoteD, NoteE;
wire NoteCoutput, NoteDoutput, NoteEoutput;
assign Speaker = NoteCoutput || NoteDoutput || NoteEoutput;
//module InputModule(keyC,keyD,keyE,NoteC,NoteD,NoteE,Reset, Clock);
InputModule UnitInput (
keyC,
keyD,
keyE,
NoteC,
NoteD,
NoteE,
Reset,
Clock
);
//module Waveform(HalfPeriod, Waveform, Reset, Clock) ;
Waveform NoteCWave (
NoteC,
NoteCoutput,
Reset,
Clock
);
Waveform NoteDWave (
NoteD,
NoteDoutput,
Reset,
Clock
);
Waveform NoteEWave (
NoteE,
NoteEoutput,
Reset,
Clock
);
endmodule
| 8.544833 |
module THREEtoEIGHT_decoder (
DA,
R0,
R1,
R2,
R3,
R4,
R5,
R6,
R7
);
input [2:0] DA; //address to which data will be written
output wire R0, R1, R2, R3, R4, R5, R6, R7; //wire corresponding to one of 8 registers
//combinational logic
assign R0 = ~DA[2] & ~DA[1] & ~DA[0];
assign R1 = ~DA[2] & ~DA[1] & DA[0];
assign R2 = ~DA[2] & DA[1] & ~DA[0];
assign R3 = ~DA[2] & DA[1] & DA[0];
assign R4 = DA[2] & ~DA[1] & ~DA[0];
assign R5 = DA[2] & ~DA[1] & DA[0];
assign R6 = DA[2] & DA[1] & ~DA[0];
assign R7 = DA[2] & DA[1] & DA[0];
endmodule
| 6.895561 |
module ThreeToOneMux #(
parameter integer RV_BIT_NUM_THREE = `RV_BIT_NUM_THREE)
(
input [`MUX_WIDTH_THREE-1:0] sel,
input [(RV_BIT_NUM_THREE*`MUX_OPTION_THREE)-1 : 0] d,
output reg [RV_BIT_NUM_THREE-1:0]q);
always@(*) begin
case( sel )
`muxcasethree(`MUX_WIDTH_THREE'd0, 0)
`muxcasethree(`MUX_WIDTH_THREE'd1, 1)
`muxcasethree(`MUX_WIDTH_THREE'd2, 2)
default: q = `RV_BIT_NUM_THREE'd0;
endcase
end
endmodule
| 8.292129 |
module three_1_mux (
data1,
data2,
data3,
sel,
outputdata
);
input [15:0] data1;
input [15:0] data2;
input [15:0] data3;
input [1:0] sel;
output [15:0] outputdata;
reg [15:0] outputdata;
parameter first = 2'b00;
parameter second = 2'b01;
parameter third = 2'b10;
always @(sel or data1 or data2 or data3) begin
case (sel)
first: begin
outputdata = data1;
end
second: begin
outputdata = data2;
end
third: begin
outputdata = data3;
end
default: begin
outputdata = 16'd0;
end
endcase
end
endmodule
| 8.449086 |
module tri_3_input_and_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
a2,
b2,
c2,
a3,
b3,
c3,
output wire y1,
y2,
y3
);
and #DELAY (y1, a1, b1, c1);
and #DELAY (y2, a2, b2, c2);
and #DELAY (y3, a3, b3, c3);
endmodule
| 8.188634 |
module tri_3_input_nand_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
a2,
b2,
c2,
a3,
b3,
c3,
output wire y1,
y2,
y3
);
nand #DELAY (y1, a1, b1, c1);
nand #DELAY (y2, a2, b2, c2);
nand #DELAY (y3, a3, b3, c3);
endmodule
| 8.082136 |
module tri_3_input_nor_gate #(
parameter DELAY = 10
) (
input wire a1,
b1,
c1,
a2,
b2,
c2,
a3,
b3,
c3,
output wire y1,
y2,
y3
);
nor #DELAY (y1, a1, b1, c1);
nor #DELAY (y2, a2, b2, c2);
nor #DELAY (y3, a3, b3, c3);
endmodule
| 8.082136 |
module three_bits_decoder_enable (
output reg [7:0] Y,
input [2:0] I,
input En
);
always @(I or En) begin
if (En == 1'b1)
case (I)
3'b000: Y = 8'b00000001;
3'b001: Y = 8'b00000010;
3'b010: Y = 8'b00000100;
3'b011: Y = 8'b00001000;
3'b100: Y = 8'b00010000;
3'b101: Y = 8'b00100000;
3'b110: Y = 8'b01000000;
3'b111: Y = 8'b10000000;
endcase
else if (En == 1'b0) Y = 8'b00000000;
end
endmodule
| 8.452091 |
module Three_Bit_Comparator (
A,
B,
Greater,
Less,
Equal
);
input [2:0] A, B;
output Greater, Less, Equal;
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13;
not n1 (w1, A[0]);
not n2 (w2, A[1]);
not n3 (w3, A[2]);
not n4 (w4, B[0]);
not n5 (w5, B[1]);
not n6 (w6, B[2]);
//equal to
xnor x1 (w7, A[0], B[0]);
xnor x2 (w8, A[1], B[1]);
xnor x3 (w9, A[2], B[2]);
and a1 (Equal, w7, w8, w9);
//greater than
and a2 (w10, A[2], w6);
and a3 (w11, A[1], w5);
and a4 (w12, w9, w11);
and a5 (w13, A[0], w4);
and a6 (w14, w13, w9, w8);
or o1 (Greater, w10, w12, w14);
//less than
and a7 (w15, B[2], w3);
and a8 (w16, B[1], w2);
and a9 (w17, w9, w16);
and a10 (w18, B[0], w1);
and a11 (w19, w18, w9, w8);
or o2 (Less, w19, w15, w17);
endmodule
| 6.599156 |
module Three_Bit_Comparator_TB;
reg [2:0] A;
reg [2:0] B;
wire Greater;
wire Less;
wire Equal;
Three_Bit_Comparator uut (
.A(A),
.B(B),
.Greater(Greater),
.Less(Less),
.Equal(Equal)
);
initial
$monitor("A = %d | B = %d | Greater = %b | Equal = %b | Less = %b", A, B, Greater, Equal, Less);
initial begin
A = 100;
B = 111;
#100 A = 001;
B = 011;
#100 A = 101;
B = 010;
#100 A = 110;
B = 101;
#100 A = 111;
B = 111;
#100 A = 011;
B = 011;
end
initial #600 $finish;
endmodule
| 6.599156 |
module three_bit_comparator_test;
// Inputs
reg [2:0] A;
reg [2:0] B;
// Outputs
wire GT;
wire LT;
wire EQ;
// Instantiate two counter variables for both loop
integer count;
// Instantiate the Unit Under Test (UUT)
three_bit_comparator uut (
.A (A),
.B (B),
.GT(GT),
.LT(LT),
.EQ(EQ)
);
initial begin
// Initialize Inputs
A = 0;
B = 0;
// Initialize counter variables
count = 0;
end
// Whenever the value of either A or B changes, iterate the possible combinations
always @(A or B) begin
// Loops over the possible combinations for A and B
for (count = 0; count < 64; count = count + 1) #1{A, B} = count;
#5 $stop;
end
endmodule
| 8.281171 |
module: three_bit_counter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module three_bit_test;
// Inputs
reg enable;
reg mode;
reg clk;
reg clear;
reg preset;
reg [2:0] load;
// Outputs
wire [2:0] out;
// Instantiate the Unit Under Test (UUT)
three_bit_counter uut (
.enable(enable),
.mode(mode),
.clk(clk),
.clear(clear),
.preset(preset),
.load(load),
.out(out)
);
integer i;
initial begin
// Initialize Inputs
enable = 0;
mode = 1;
clear = 0;
load = 0;
preset = 1;
#100;
preset = 0;
#100;
for(i = 0; i < 8; i=i+1)
#100 load = i;
// Add stimulus here
end
initial begin
clk = 0;
repeat(100) #50 clk = ~clk;
end
endmodule
| 7.884088 |
module up_down_synchronous_counter (
Q,
M,
CLR,
CLK
);
input M, CLR, CLK;
output [2:0] Q;
wire [2:0] J, K, Qbar;
// Dataflow Modeling
assign J[0] = (~M & ~Q[1] & ~Q[2]) | (M & Q[1] & Q[2]),
K[0] = J[0],
J[1] = ~(M ^ Q[2]),
K[1] = J[1],
J[2] = 1,
K[2] = 1;
// Gate Level Modeling
JKFF jk1 (
Q[0],
Qbar[0],
J[0],
K[0],
CLR,
CLK
);
JKFF jk2 (
Q[1],
Qbar[1],
J[1],
K[1],
CLR,
CLK
);
JKFF jk3 (
Q[2],
Qbar[2],
J[2],
K[2],
CLR,
CLK
);
endmodule
| 7.759982 |
module Level1 (
input [15:0] addr,
output [15:0] data
);
wire [15:0] level2_addr;
wire [15:0] level2_data;
Level2 level2 (
.addr(level2_addr),
.data(level2_data)
);
assign data = level2_data;
assign level2_addr = addr;
endmodule
| 7.460002 |
module Level2 (
input [15:0] addr,
output [15:0] data
);
wire [15:0] memory_addr;
wire [15:0] memory_data;
Level3 memory (
.addr(memory_addr),
.data(memory_data)
);
assign data = memory_data;
assign memory_addr = addr;
endmodule
| 7.782242 |
module Level3 (
input [15:0] addr,
output [15:0] data
);
assign data = addr;
endmodule
| 6.678458 |
module Top (
input clk,
input reset,
input [15:0] addr,
output [15:0] data
);
wire [15:0] level1_addr;
wire [15:0] level1_data;
Level1 level1 (
.addr(level1_addr),
.data(level1_data)
);
assign data = level1_data;
assign level1_addr = addr;
endmodule
| 6.64497 |
module with_SSI (
input a,
b,
c,
d,
output f3,
f2,
f1,
f0
);
// GATE LEVEL DESIGN
wire temp1, temp2, temp3, temp4, temp5, temp6;
and (temp1, a, d);
and (temp2, b, c);
and (f3, temp1, temp2);
and (temp3, a, c);
NAND nand0 (
temp4,
b,
d
);
and (f2, temp3, temp4);
EXOR exor0 (
f1,
temp1,
temp2
);
and (f0, b, d);
endmodule
| 6.893239 |
module with_MUX (
input a,
b,
c,
d,
output f3,
f2,
f1,
f0
);
// With MUX
wire temp12, temp13, temp14, temp15, temp16, temp17, temp18;
and (temp12, b, d);
MUX mux0 (
f0,
{temp12, temp12, temp12, temp12},
{a, c}
);
NOT not0 (
temp13,
d
);
NOT not1 (
temp14,
b
);
and (temp15, b, temp13);
and (temp16, d, temp14);
OR or0 (
temp17,
temp16,
temp15
);
MUX mux1 (
f1,
{temp17, d, b, 1'b0},
{a, c}
);
NAND nand0 (
temp18,
b,
d
);
MUX mux2 (
f2,
{temp18, 1'b0, 1'b0, 1'b0},
{a, c}
);
MUX mux3 (
f3,
{temp12, 1'b0, 1'b0, 1'b0},
{a, c}
);
endmodule
| 6.760408 |
module three_eight (
m,
y
);
input wire [2:0] m;
output reg [7:0] y;
reg move;
always @(*) begin
move = 1;
y = ~(move << m);
end
endmodule
| 7.168577 |
module Three_EightMux (
out1,
mov_out,
Not_out,
add_out,
sub_out,
or_out,
and_out,
select
);
input mov_out, Not_out, add_out, sub_out, or_out, and_out;
input [2:0] select;
output reg out1;
always @(*) begin
case (select)
3'b000: out1 = mov_out;
3'b001: out1 = Not_out;
3'b011: out1 = and_out;
3'b100: out1 = or_out;
3'b101: out1 = sub_out;
3'b110: out1 = add_out;
default: out1 = 0;
endcase
end
endmodule
| 7.141743 |
module three_eight_decoder (
d,
a
);
output [7:0] d;
input [2:0] a;
wire [2:0] nota;
not not_gates[2:0] (nota, a);
and (d[0], nota[2], nota[1], nota[0]);
and (d[1], nota[2], nota[1], a[0]);
and (d[2], nota[2], a[1], nota[0]);
and (d[3], nota[2], a[1], a[0]);
and (d[4], a[2], nota[1], nota[0]);
and (d[5], a[2], nota[1], a[0]);
and (d[6], a[2], a[1], nota[0]);
and (d[7], a[2], a[1], a[0]);
endmodule
| 6.538449 |
module three_eight_decoder_tb;
reg [2:0] a;
wire [7:0] d;
three_eight_decoder decoder (
d,
a
);
initial begin
$monitor($time, " d: %b, a: %b", d, a);
a = 0;
repeat (7) #5 a = a + 1;
end
endmodule
| 6.538449 |
module three_fsm_tb;
reg clk;
reg [3:0] choose;
reg [15:0] hs_3fsm = 16'b1111_1111_1010_1010;
reg [15:0] vs_3fsm = 16'b1111_1111_0001_0001;
reg [15:0] pic_ena = 16'b1111_1111_1111_1111;
wire [11:0] VGA_data;
wire final_pic_ena;
wire HSYNC, VSYNC;
three_fsm U_3fsm (
.clk(clk),
.rst(1'b0),
.choose(choose), //选择
.origin_data(16'b0111_1110_1001_0011),
.grey_data(8'b1110_1111),
.median_data(8'b0101_1111),
.hs(hs_3fsm), //4 bits 的choose 有16种 预留好
.vs(vs_3fsm),
.pic_ena(pic_ena),
.sobel_data(1'b1),
.erode_data(1'b1),
.dilate_data(1'b1),
.post_hs(HSYNC), //[15:0]
.post_vs(VSYNC), //[15:0]
.post_pic_ena(final_pic_ena), //[15:0]
.VGA_data(VGA_data)
);
//reg [7:0] median_value;
//wire [11:0] sobel_value;
//integer i;
integer j;
initial begin
choose = 4'b0;
#5;
for (j = 0; j <= 3; j = j + 1) begin
clk = 0;
choose = choose + 1;
#1;
clk = 1;
#5;
/*
for(i = 1; i <= 20; i = i + 1)
begin
clk = ~clk;
median_value = i[7:0] + vcount;
#1;
clk = ~clk;
#5;
end
*/
end
end
endmodule
| 8.211055 |
module three_inputs_gate (
a,
b,
c,
out
);
input wire a;
input wire b;
input wire c;
output wire out;
assign out = a | b | c;
endmodule
| 8.156517 |
module three_inputs_gate_tb;
`define THREE_INPUTS_TEST(ID, A, B, C, OUT) \
a = A; \
b = B; \
c=C;\
#5; \
if(out == OUT) \
$display("Case %d passed!", ID); \
else begin \
$display("Case %d failed!", ID); \
$finish; \
end \
#5;
reg a;
reg b;
reg c;
wire out;
three_inputs_gate x_three_inputs_gate (
.a (a),
.b (b),
.c (c),
.out(out)
);
initial begin
`THREE_INPUTS_TEST(8'd1, 1'b0, 1'b0, 1'b0, 1'b0);
`THREE_INPUTS_TEST(8'd2, 1'b0, 1'b1, 1'b0, 1'b1);
`THREE_INPUTS_TEST(8'd3, 1'b0, 1'b0, 1'b1, 1'b1);
`THREE_INPUTS_TEST(8'd4, 1'b0, 1'b1, 1'b1, 1'b1);
`THREE_INPUTS_TEST(8'd5, 1'b1, 1'b0, 1'b0, 1'b1);
`THREE_INPUTS_TEST(8'd6, 1'b1, 1'b1, 1'b0, 1'b1);
`THREE_INPUTS_TEST(8'd7, 1'b1, 1'b0, 1'b1, 1'b1);
`THREE_INPUTS_TEST(8'd8, 1'b1, 1'b1, 1'b1, 1'b1);
$display("Success!");
$finish;
end
endmodule
| 8.156517 |
module three_input_and_gate (
input a,
b,
c,
output x,
y
);
assign x = a & b;
assign y = x & c;
endmodule
| 7.125004 |
module three_input_and_gate_a (
input a,
input b,
input c,
output d
);
assign d = a & b & c;
endmodule
| 7.125004 |
module three_input_and_gate_a_tb;
reg aa, bb, cc;
wire y;
three_input_and_gate_a u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(y)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 7.125004 |
module three_input_AND_gate_b (
input A,
input B,
output D,
input C,
output E
);
assign D = A & B;
assign E = D & C;
endmodule
| 7.245442 |
module three_input_AND_gate_b_tb;
reg aa, bb, cc;
wire dd, ee;
three_input_AND_gate_b u_inv (
.A(aa),
.B(bb),
.D(dd),
.C(cc),
.E(ee)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 7.245442 |
module three_input_and_gate_tb;
reg aa, bb, cc;
wire x, y;
three_input_and_gate u_three_input_and_gate (
.a(aa),
.b(bb),
.c(cc),
.x(x),
.y(y)
);
initial aa = 0'b0;
initial bb = 0'b0;
initial cc = 0'b0;
always aa = #50 ~aa;
always bb = #100 ~bb;
always cc = #200 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 7.125004 |
module three_input_nand_gate_a (
input a,
input b,
input c,
output d
);
assign d = ~(a & b & c);
endmodule
| 6.503775 |
module three_input_nand_gate_a_tb;
reg aa, bb, cc;
wire y;
three_input_nand_gate_a u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(y)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 6.503775 |
module three_input_nand_gate_b (
input a,
input b,
input c,
output d,
output e
);
assign d = ~(a & b);
assign e = ~(d & c);
endmodule
| 6.503775 |
module three_input_nand_gate_b_tb;
reg aa, bb, cc;
wire d, e;
three_input_nand_gate_b u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(d),
.e(e)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 6.503775 |
module three_input_nor_gate_a (
input a,
input b,
input c,
output d
);
assign d = ~(a | b | c);
endmodule
| 6.503775 |
module three_input_nor_gate_a_tb;
reg aa, bb, cc;
wire d;
three_input_nor_gate_a u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(d)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 6.503775 |
module three_input_nor_gate_b (
input a,
input b,
input c,
output d,
output e
);
assign d = ~(a | b);
assign e = ~(d | c);
endmodule
| 6.503775 |
module three_input_nor_gate_b_tb;
reg aa, bb, cc;
wire d, e;
three_input_nor_gate_b u_inv (
.a(aa),
.b(bb),
.c(cc),
.d(d),
.e(e)
);
initial aa = 1'b0;
initial bb = 1'b0;
initial cc = 1'b0;
always aa = #200 ~aa;
always bb = #100 ~bb;
always cc = #50 ~cc;
initial begin
#1000 $finish;
end
endmodule
| 6.503775 |
module three_input_or_gate (
input a,
b,
c,
output x,
y
);
assign x = a | b;
assign y = x | c;
endmodule
| 6.687992 |
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