code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module: netwalk_flow_meter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_netwalk_flow_meter;
// Inputs
reg clk;
reg reset;
reg glbl_program_en;
reg [5:0] meter_program_addr;
reg meter_program_enable;
reg meter_delete_enable;
reg [5:0] meter_of_match_addr;
reg meter_of_match_found;
reg meter_read_en;
reg [5:0] meter_read_addr;
// Outputs
wire [31:0] meter_count;
wire meter_count_valid;
wire [31:0] meter_read_data;
integer i;
// Instantiate the Unit Under Test (UUT)
netwalk_flow_meter uut (
.clk(clk),
.reset(reset),
.glbl_program_en(glbl_program_en),
.meter_program_addr(meter_program_addr),
.meter_program_enable(meter_program_enable),
.meter_delete_enable(meter_delete_enable),
.meter_of_match_addr(meter_of_match_addr),
.meter_of_match_found(meter_of_match_found),
.meter_count(meter_count),
.meter_count_valid(meter_count_valid),
.meter_read_en(meter_read_en),
.meter_read_addr(meter_read_addr),
.meter_read_data(meter_read_data)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
glbl_program_en = 0;
meter_program_addr = 0;
meter_program_enable = 0;
meter_delete_enable = 0;
meter_of_match_addr = 0;
meter_of_match_found = 0;
meter_read_en = 0;
meter_read_addr = 0;
reset=1;
#10;
reset=0;
// Wait 100 ns for global reset to finish
#100;
meter_program_addr = 0;
meter_program_enable = 1;
meter_delete_enable = 0;
#10;
meter_program_addr = 1;
#10;
meter_program_addr = 2;
#10;
meter_program_enable =0;
meter_delete_enable = 0;
#40;
for(i=0;i<10;i=i+1)begin
meter_of_match_addr = 0;
meter_of_match_found = 1;
#10;
end
meter_of_match_found = 0;
#40;
// Add stimulus here
end
always begin
#5 clk=~clk;
end
endmodule
| 6.555677 |
module tb_thermo_maj;
reg [14:0] in1;
reg [14:0] in2;
reg [14:0] in3;
reg [14:0] in4;
wire [14:0] out2;
majority first (
.in1(in1),
.in2(in2),
.in3(in3),
.in4(in4),
.out(out2)
);
initial begin
in1 <= 15'b000000000000011;
in2 <= 15'b000000001111111;
in3 <= 15'b000000000111111;
in4 <= 15'b000000000000001;
$display("tb_thermo_maj.v: %b", out2);
end
endmodule
| 6.775331 |
module tb_new_CPU ();
reg Clk, Rst, key_data, key_clk;
wire [15:0] RdestOut;
wire [7:0] red, green, blue;
wire hsync, vsync, blankN, vgaClk;
CPU uut (
.Clk(Clk),
.Rst(Rst),
.key_data(key_data),
.key_clk(key_clk),
.red(red),
.green(green),
.blue(blue),
.hsync(hsync),
.vsync(vsync),
.blankN(blankN),
.vgaClk(vgaClk),
.RdestOut(RdestOut)
);
initial begin
Clk = 0;
Rst = 1;
#5;
Rst = 0;
#5;
Rst = 1;
#5;
end
always #5 Clk = ~Clk;
endmodule
| 6.899623 |
module tb (
seg,
an,
clk,
sw
);
input clk;
wire rst;
// reg clk_rst;
wire clk_2hz;
wire clk_1hz;
wire clk_fast;
wire clk_blink;
wire reg_mode;
wire adj_sec_mode;
wire adj_min_mode;
wire pause_mode;
wire [3:0] digit_1;
wire [3:0] digit_2;
wire [3:0] digit_3;
wire [3:0] digit_4;
input [7:0] sw;
output [7:0] seg;
output [3:0] an;
assign reg_mode = sw[0];
// initial
// begin
// master_clk = 0;
// clk_rst = 1;
// rst = 1;
// digit_1 = 0;
// digit_2 = 1;
// digit_3 = 2;
// digit_4 = 3;
// #1000 rst = 0; clk_rst = 0;
// $finish;
// end
// always #5 master_clk = ~master_clk;
clocks clks__ (
.rst(rst),
.master_clock(clk),
.clock1hz(clk_1hz),
.clock2hz(clk_2hz),
.clock_adjust(clk_blink),
.clock_fast(clk_fast)
);
totalCounter counter0 (
.rst(rst),
.counting_clock(clk_1hz),
.adjust_clock(clk_2hz),
.regular_mode(reg_mode),
.adjust_seconds_mode(adj_sec_mode),
.adjust_minutes_mode(adj_min_mode),
.pause_mode(pause_mode),
.digit1(digit_1),
.digit2(digit_2),
.digit3(digit_3),
.digit4(digit_4)
);
display display__ (
.clk_fast(clk_fast),
.clk_adjust(clk_blink),
.reg_mode(reg_mode),
.adj_sec_mode(adj_sec_mode),
.adj_min_mode(adj_min_mode),
.pause_mode(pause_mode),
.digit_1(digit_1),
.digit_2(digit_2),
.digit_3(digit_3),
.digit_4(digit_4),
.seg(seg),
.an(an)
);
endmodule
| 6.86926 |
module tb_nic;
parameter DATA_WIDTH = 64;
parameter CLK_CYCLE = 4;
parameter NUM_OF_PAC = 10000; // how many packets will be sent
reg clk, reset; // sync high active reset
// Ports from router side
reg net_ro, net_polarity, net_si;
reg [0:DATA_WIDTH - 1] net_di;
wire net_so, net_ri;
wire [0:DATA_WIDTH - 1] net_do;
// Ports from router side
reg [0:1] addr;
reg [0:DATA_WIDTH - 1] d_in;
reg nicEn, nicEnWr;
wire [0:DATA_WIDTH - 1] d_out;
// Instantiation of DUT
nic_design #(
.PACKET_SIZE(DATA_WIDTH)
) nic_design_dut (
.clk(clk),
.reset(reset),
.net_so(net_so),
.net_ro(net_ro),
.net_do(net_do),
.net_polarity(net_polarity),
.net_si(net_si),
.net_ri(net_ri),
.net_di(net_di),
.addr(addr),
.d_in(d_in),
.d_out(d_out),
.nicEn(nicEn),
.nicEnWr(nicEnWr)
);
// Generates clock signal
always #(0.5 * CLK_CYCLE) clk = ~clk;
// Generates polarity signal
always @(posedge clk) begin
if (reset) net_polarity <= 0;
else net_polarity <= ~net_polarity;
end
integer data_received_pe, data_received_router;
initial begin
data_received_pe =
$fopen("data_received_pe.res", "w"); // report data received in processor side
data_received_router =
$fopen("data_received_router.res", "w"); // report data received in router side
end
// a flag used to indicate if data sending from router finished
// if send_finish == 1, data sending from processor started
reg send_finish;
initial begin : test
integer i;
clk = 1;
reset = 1;
nicEn = 1; // always reading
nicEnWr = 0;
net_ro = 0;
net_si = 0;
send_finish = 0;
#(3.5 * CLK_CYCLE) reset = 0;
// sending data from router side
for (i = 0; i < NUM_OF_PAC; i = i + 1) begin
wait (net_ri == 1) #(0.1 * CLK_CYCLE) net_si = 1;
net_di = i;
#(CLK_CYCLE) net_si = 0;
end
#(10 * CLK_CYCLE);
send_finish = 1; // change flag
#(10 * CLK_CYCLE);
// sending data from processor side
i = 0;
while (i < NUM_OF_PAC) begin
#(0.1 * CLK_CYCLE) addr = 2'b11;
#(0.1 * CLK_CYCLE)
if(d_out[63] == 0) // checking status reg of output buffer
begin
addr = 2'b10;
nicEnWr = 1;
d_in = i;
d_in[0] = i % 2; // change the vc bit to test conditional sending to router
i = i + 1;
end
#(0.8 * CLK_CYCLE) nicEnWr = 0;
end
#(10 * CLK_CYCLE) $fclose(data_received_pe | data_received_router);
$finish;
end
// Reveiving data at processor side
initial begin : loop_1
#(3.5 * CLK_CYCLE)
forever begin
if (send_finish == 1)
disable loop_1; // if data sending from router finished, disable this block
addr = 2'b01;
#(0.1 * CLK_CYCLE)
if(d_out[63] == 1) //check the status reg of input buffer
begin
addr = 2'b00;
#(0.1 * CLK_CYCLE) $fdisplay(data_received_pe, "%1d", d_out[32:63]);
end else #(0.1 * CLK_CYCLE);
#(0.8 * CLK_CYCLE);
end
end
//Receiving data from router side
initial begin
#(3.5 * CLK_CYCLE)
forever
@(posedge clk) begin
net_ro = 1;
#(0.1 * CLK_CYCLE) if (net_so == 1) $fdisplay(data_received_router, "%1d", net_do[32:63]);
end
end
endmodule
| 6.700027 |
module tb_noise;
reg clk, rst;
reg [7:0] din;
wire [31:0] a, b;
wire [3:0] state;
wire adivbyzero, bdivbyzero;
wire ab_start;
wire [7:0] gin;
wire window_7x7_start;
reg [7:0] image_data[163839:0];
//图像像素索引
reg [31:0] index;
reg empty;
integer fp1, fp2, fp3, fp4;
initial begin
//初始化激励
clk = 0;
rst = 0;
din = 0;
//等待100ns全局初始化
#100 rst = 1;
end
//产生时钟信号
always #5 clk = ~clk;
//读存储着的图像数据
initial begin
index = 32'b0;
#50 $readmemb("medinoise.txt", image_data);
end
//连接输出数据的文件
initial begin
fp1 = $fopen("medinoise_a.txt");
fp2 = $fopen("medinoise_b.txt");
fp3 = $fopen("medinoise_state.txt");
fp4 = $fopen("medinoise_gaussian.txt");
end
//依次读入图像数据
always @(posedge clk or negedge rst)
if (~rst) begin
index <= 32'd0;
end else begin
din <= image_data[index];
index <= index + 32'd1;
end
top_noise top_noise_inst (
.clk(clk),
.rst(rst),
.din(din),
.window_7x7_start (window_7x7_start),
.gin (gin),
.result_a (a),
.adivbyzero(adivbyzero),
.result_b (b),
.bdivbyzero(bdivbyzero),
.ab_start (ab_start),
.state (state),
.frame_complete (frame_complete)
);
//输出结果
always @(posedge clk or posedge ab_start)
if (~ab_start)
//$display("please wait data valid\n");
empty <= 1'b0;
else begin
$fdisplay(fp1, "%h", a);
$fdisplay(fp2, "%h", b);
$fdisplay(fp3, "%b", state);
end
reg [0:0] empty2;
always @(posedge clk or posedge ab_start)
if (~window_7x7_start)
//$display("please wait data valid\n");
empty2 <= 1'b0;
else begin
$fdisplay(fp4, "%b", gin);
end
endmodule
| 7.737418 |
module tb_non_blocking ();
wire [1:0] out;
reg sys_clk;
reg sys_rst_n;
reg [1:0] in;
//初始化系统时钟、全局复位和输入信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
in <= 2'b0;
#20;
sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_clk = ~sys_clk;
//key_in:产生输入随机数，模拟按键的输入情况
always #20
in <= {$random} % 4; //取模求余数，产生非负随机数0、1，每隔20ns产生一次随机数
//------------------------non_blocking_inst------------------------
non_blocking non_blocking_inst (
.sys_clk (sys_clk), //input sys_clk
.sys_rst_n(sys_rst_n), //input sys_rst_n
.in (in), //input [1:0] in
.out(out) //output [1:0] out
);
endmodule
| 8.165388 |
module nor_gate_top;
reg I0, I1;
wire Out;
nor_gate gate0 (
I0,
I1,
Out
);
initial begin
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 1;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 1;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 1;
I1 = 1;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
end
endmodule
| 6.849274 |
module not_gate_top;
reg I0;
wire Out;
not_gate gate0 (
I0,
Out
);
initial begin
$display("I0 : %b, Out : %b", I0, Out);
I0 = 0;
#1;
$display("I0 : %b, Out : %b", I0, Out);
I0 = 1;
#1;
$display("I0 : %b, Out : %b", I0, Out);
end
endmodule
| 6.836215 |
module tb_Num_Inm;
reg [7:0] i_Instruction;
wire [7:0] NUM;
Num_Inm uut(
.i_Instruction(i_Instruction),
.NUM(NUM)
);
initial
begin
i_Instruction = 0;
#2i_Instruction = 8'b00000001;
#2i_Instruction = 8'b00001011;
#2i_Instruction = 8'b11111111;
end
endmodule
| 6.883674 |
module tb_odd_fre ();
reg clk_i;
reg rst_n;
wire clk_div;
odd_fre odd_fre_inst (
.clk_i (clk_i),
.rst_n (rst_n),
.clk_div(clk_div)
);
always #1 clk_i = ~clk_i;
initial begin
clk_i = 0;
rst_n = 0;
#100 rst_n = 1;
end
endmodule
| 7.478758 |
module tb_odd_parity_check ();
reg serial;
reg clk;
reg reset;
wire parity;
OddParityCheck pc (
.serial_in(serial),
.clk(clk),
.reset(reset),
.parity_valid(parity)
);
initial begin
clk <= 0;
reset <= 1;
serial <= 0;
#5 reset <= 0;
#10 serial <= 1; //Parity should be asserted after this is clocked in
#10 serial <= 0;
#10 serial <= 1; //Parity should be de-asserted after this is clocked in
#10 serial <= 0;
#10 reset <= 1;
end
always begin
#5 clk = ~clk;
end
endmodule
| 7.11386 |
module tb_ofdm ();
reg clk;
reg reset;
reg [3:0] inputdata;
reg in;
reg [3:0] out_count;
wire esig;
wire [3:0] out;
reg eesig;
OFDM ofdm1 (
.reset(reset),
.clk (clk),
.x_in (in),
.x_out(out)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
integer i;
initial begin
reset = 1;
clk = 1;
i = 0;
#100 reset = 0;
end
always @(posedge clk)
if (reset) begin
eesig <= 0;
out_count <= 0;
inputdata <= 4'b0110;
end else begin
if (i < 4) begin
in = inputdata[i];
i = i + 1;
end else begin
in = inputdata[0];
i = 1;
end
end
endmodule
| 7.054788 |
module testbench #(
parameter PW = 256, // packet total width
parameter CW = 16, // packet control width
parameter N = 32, // ctrl/status width
parameter DEPTH = 8192, // simulus memory depth
parameter TARGET = "DEFAULT", // physical synthesis/sim target
parameter FILENAME = "NONE" // Simulus hexfile for $readmemh
) (
// control signals to drive
input nreset, // async active low reset
input clk, // core clock
input fastclk, // fast clock
input slowclk, //slow clock
input [ 2:0] mode, //0=load,1=go,2=bypass,3=rng
input [ N-1:0] ctrl, // generic ctrl vector
input [ N-1:0] seed, // seed(s) for rng
// external write interface
input ext_clk, //ext packet clock
input ext_valid, // ext valid signal
input [PW-1:0] ext_packet, // ext packet
input ext_ready, // external ready to receive
// dut response packets
output dut_clk, // due packet clock
output dut_valid, //dut packet valid signal
output [PW-1:0] dut_packet, // dut packet to drive
output dut_ready, // dut is ready for packet
// dut status interface
output [ N-1:0] dut_status, // generic status vector
output dut_error, // dut error flag (leads to failure)
output dut_done, // test done
output dut_fail // test failed
);
//#################################
// LOCAL WIRES
//#################################
/*AUTOWIRE*/
/*AUTOINPUT*/
//#################################
// DUT LOGIC
//#################################
assign dut_ready = 1'b1;
assign dut_error = 1'b0;
assign dut_done = 1'b0;
assign dut_valid = 1'b0;
assign dut_clk = clk;
oh_lfsr #(
.N(N)
) oh_lfsr ( // outputs
.out (dut_status[N-1:0]),
// inputs
.taps (ctrl[N-1:0]),
.seed (seed[N-1:0]),
.en (1'b1),
.clk (clk),
.nreset(nreset)
);
endmodule
| 6.640835 |
module tb_ones_count;
integer i;
reg [7:0] dat_in;
wire [3:0] count;
ones_count counter (
count,
dat_in
);
initial begin
for (i = 0; i <= 8'b11111111; i = i + 1) begin
dat_in = i;
#10;
end
end
endmodule
| 6.544435 |
module tb_one_port_mem;
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
//Auto-calculated, user dont touch
localparam addressWidth = $clog2(addresses);
wire [ width-1:0] readData;
reg readEnable;
reg [addressWidth-1:0] address;
reg clk;
reg writeEnable;
reg [ width-1:0] writeData;
initial begin
readEnable = 0;
address = 0;
clk = 0;
writeEnable = 0;
writeData = 0;
end
always begin
#5 clk = ~clk;
end
integer i;
initial begin
repeat (10) @(posedge clk);
for (i = 0; i < addresses; i = i + 1) begin
readEnable = 0;
address = i;
writeEnable = 1;
writeData = i[width-1:0];
@(posedge clk);
end
readEnable = 0;
address = 0;
writeEnable = 0;
writeData = 0;
repeat (10) @(posedge clk);
for (i = 0; i < addresses; i = i + 1) begin
readEnable = 1;
address = i;
writeEnable = 0;
writeData = 0;
@(posedge clk);
#1;
if (readData[width-1:0] != i[width-1:0]) begin
$display("ERROR");
$finish;
end
end // for (i=0;i<addresses;i=i+1)
$display("Tested %d addresses", addresses);
$display("PASS");
$finish;
end
onePortMem #(
.addresses(addresses),
.width (width),
.muxFactor(muxFactor)
) mem (
.readData(readData),
.readEnable(readEnable),
.address(address),
.clk(clk),
.writeEnable(writeEnable),
.writeData(writeData)
);
endmodule
| 7.798339 |
module tb_openmips_min_sopc ();
reg CLOCK_50;
reg rst;
//Turn ovr the time signal per 50 sec, so the T = 20ns, f = 50MHz
initial begin
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
//The resetting signal is valid in the beginning, in the 195ns it becomes invalid, so as the min SOPC start
//After 1000ns, the simulation paused
initial begin
rst = `RstEnable;
#195 rst = `RstDisable;
#3500 $stop;
end
//SOPC for instance
openmips_min_sopc openmips_min_sopc0 (
.clk(CLOCK_50),
.rst(rst)
);
endmodule
| 8.249896 |
module tb ();
reg CLK;
reg RST;
wire [ 2:0] x_min;
wire [ 2:0] y_min;
wire [15:0] cost_mini;
wire output_vld;
parameter DUTY = 1;
always #1 CLK = ~CLK;
initial begin
CLK = 1;
RST = 0;
#10 RST = 1;
end
always @(posedge CLK or negedge RST) begin : proc_output_vld
if (output_vld == 1'b1) begin
$display("x = %d, y= %d, total_cost = %d", x_min, y_min, cost_mini);
$display("At_time: %t", $time);
$stop;
end
end
optimal_place U_OPTIMAL_PLACE (
.CLK(CLK),
.RST_n(RST),
.x_min(x_min),
.y_min(y_min),
.cost_mini(cost_mini),
.output_vld(output_vld)
);
endmodule
| 7.002324 |
module or_gate_top;
reg I0, I1;
wire Out;
or_gate gate0 (
I0,
I1,
Out
);
initial begin
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 1;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 1;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 1;
I1 = 1;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
end
endmodule
| 6.94011 |
module tb_or1200_ic_ram ();
parameter dw = `OR1200_OPERAND_WIDTH; // value is 32
parameter aw = `OR1200_ICINDX; // value is 11
wire [63:0] dataout;
reg clk, rst;
reg [aw-1:0] addr;
reg [3:0] we;
reg [63:0] datain;
reg en;
initial begin
// #100 $finish;
end
initial begin
#0 rst = 1;
we = 0;
en = 0;
clk = 0;
addr = 11'b0;
#20 rst = 0;
en = 1;
addr = 11'b0;
#10 addr = 11'd2;
#10 addr = 11'd4;
#10 addr = 11'd6;
end
always #5 clk = ~clk;
or1200_ic_ram or1200_ic_ram (
.clk(clk),
.rst(rst),
.dataout(dataout),
.addr(addr),
.en(en),
.we(we),
.datain(datain)
);
endmodule
| 6.808996 |
module tb_ov5640 ();
wire ov5640_pwdn;
wire ov5640_rst_n;
wire power_done;
wire busy;
wire rd_iic_data;
wire iic_clk;
wire iic_sda;
reg sys_clk;
reg sys_rst_n;
reg start;
reg [31:0] wr_data;
initial begin
sys_clk = 1'b0;
sys_rst_n <= 1'b0;
start <= 1'b0;
wr_data <= 32'h78300a56;
#100 sys_rst_n <= 1'b1;
#100 start <= 1'b1;
#20 start <= 1'b0;
#2000 start <= 1'b1;
wr_data <= 32'h79300a56;
#20 start <= 1'b0;
end
always #10 sys_clk = ~sys_clk;
power_ctrl power_ctrl_inst (
.sclk (sys_clk),
.s_rst_n(sys_rst_n),
.ov5640_pwdn (ov5640_pwdn),
.ov5640_rst_n(ov5640_rst_n),
.power_done (power_done)
);
ov5640_iic ov5640_iic_inst (
.sclk (sys_clk),
.s_rst_n(sys_rst_n),
.start (start), //iic总线工作的触发信号
.wdata (wr_data),
.busy (busy), //iic总线处于忙碌状态
.riic_data(rd_iic_data),
.iic_scl (iic_clk),
.iic_sda (iic_sda)
);
endmodule
| 6.931881 |
module tb_ov7725_data ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter H_VALID = 10'd640, //行有效数据
H_TOTAL = 10'd784; //行扫描周期
parameter V_SYNC = 10'd4, //场同步
V_BACK = 10'd18, //场时序后沿
V_VALID = 10'd480, //场有效数据
V_FRONT = 10'd8, //场时序前沿
V_TOTAL = 10'd510; //场扫描周期
//wire define
wire ov7725_wr_en; //有效图像使能信号
wire [15:0] ov7725_data_out; //有效图像数据
wire ov7725_href; //行同步信号
wire ov7725_vsync; //场同步信号
//reg define
reg sys_clk; //模拟时钟信号
reg sys_rst_n; //模拟复位信号
reg [ 7:0] ov7725_data; //模拟摄像头采集图像数据
reg [11:0] cnt_h; //行同步计数器
reg [ 9:0] cnt_v; //场同步计数器
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//时钟、复位信号
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
always #20 sys_clk = ~sys_clk;
//cnt_h:行同步信号计数器
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_h <= 12'd0;
else if (cnt_h == ((H_TOTAL * 2) - 1'b1)) cnt_h <= 12'd0;
else cnt_h <= cnt_h + 1'd1;
//ov7725_href:行同步信号
assign ov7725_href = (((cnt_h >= 0)
&& (cnt_h <= ((H_VALID * 2) - 1'b1)))
&& ((cnt_v >= (V_SYNC + V_BACK))
&& (cnt_v <= (V_SYNC + V_BACK + V_VALID - 1'b1))))
? 1'b1 : 1'b0 ;
//cnt_v:场同步信号计数器
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_v <= 10'd0;
else if ((cnt_v == (V_TOTAL - 1'b1)) && (cnt_h == ((H_TOTAL * 2) - 1'b1))) cnt_v <= 10'd0;
else if (cnt_h == ((H_TOTAL * 2) - 1'b1)) cnt_v <= cnt_v + 1'd1;
else cnt_v <= cnt_v;
//vsync:场同步信号
assign ov7725_vsync = (cnt_v <= (V_SYNC - 1'b1)) ? 1'b1 : 1'b0;
//ov7725_data:模拟摄像头采集图像数据
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) ov7725_data <= 8'd0;
else if (ov7725_href == 1'b1) ov7725_data <= ov7725_data + 1'b1;
else ov7725_data <= 8'd0;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- ov7725_data_inst -------------
ov7725_data ov7725_data_inst (
.sys_rst_n (sys_rst_n), //复位信号
.ov7725_pclk (sys_clk), //摄像头像素时钟
.ov7725_href (ov7725_href), //摄像头行同步信号
.ov7725_vsync(ov7725_vsync), //摄像头场同步信号
.ov7725_data (ov7725_data), //摄像头图像数据
.ov7725_wr_en (ov7725_wr_en), //图像数据有效使能信号
.ov7725_data_out(ov7725_data_out) //图像数据
);
endmodule
| 7.829089 |
module tb_ov7725_top ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//parameter define
parameter H_VALID = 10'd640, //行有效数据
H_TOTAL = 10'd784; //行扫描周期
parameter V_SYNC = 10'd4, //场同步
V_BACK = 10'd18, //场时序后沿
V_VALID = 10'd480, //场有效数据
V_FRONT = 10'd8, //场时序前沿
V_TOTAL = 10'd510; //场扫描周期
//wire define
wire ov7725_href; //行同步信号
wire ov7725_vsync; //场同步信号
wire cfg_done; //寄存器配置完成
wire sccb_scl; //SCL
wire sccb_sda; //SDA
wire wr_en; //图像数据有效使能信号
wire [15:0] wr_data; //图像数据
wire ov7725_rst_n; //模拟ov7725复位信号
//reg define
reg sys_clk; //模拟时钟信号
reg sys_rst_n; //模拟复位信号
reg ov7725_pclk; //模拟摄像头时钟信号
reg [ 7:0] ov7725_data; //模拟摄像头采集图像数据
reg [11:0] cnt_h; //行同步计数器
reg [ 9:0] cnt_v; //场同步计数器
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//时钟、复位信号
initial begin
sys_clk = 1'b1;
ov7725_pclk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
always #20 sys_clk = ~sys_clk;
always #20 ov7725_pclk = ~ov7725_pclk;
assign ov7725_rst_n = sys_rst_n && cfg_done;
//cnt_h:行同步信号计数器
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_h <= 12'd0;
else if (cnt_h == ((H_TOTAL * 2) - 1'b1)) cnt_h <= 12'd0;
else cnt_h <= cnt_h + 1'd1;
//ov7725_href:行同步信号
assign ov7725_href = (((cnt_h >= 0)
&& (cnt_h <= ((H_VALID * 2) - 1'b1)))
&& ((cnt_v >= (V_SYNC + V_BACK))
&& (cnt_v <= (V_SYNC + V_BACK + V_VALID - 1'b1))))
? 1'b1 : 1'b0 ;
//cnt_v:场同步信号计数器
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) cnt_v <= 10'd0;
else if ((cnt_v == (V_TOTAL - 1'b1)) && (cnt_h == ((H_TOTAL * 2) - 1'b1))) cnt_v <= 10'd0;
else if (cnt_h == ((H_TOTAL * 2) - 1'b1)) cnt_v <= cnt_v + 1'd1;
else cnt_v <= cnt_v;
//vsync:场同步信号
assign ov7725_vsync = (cnt_v <= (V_SYNC - 1'b1)) ? 1'b1 : 1'b0;
//ov7725_data:模拟摄像头采集图像数据
always @(posedge sys_clk or negedge sys_rst_n)
if (sys_rst_n == 1'b0) ov7725_data <= 8'd0;
else if (ov7725_href == 1'b1) ov7725_data <= ov7725_data + 1'b1;
else ov7725_data <= 8'd0;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------- ov7725_top_inst -------------
ov7725_top ov7725_top_inst (
.sys_clk (sys_clk), //系统时钟
.sys_rst_n (sys_rst_n), //复位信号
.sys_init_done(ov7725_rst_n), //系统初始化完成(SDRAM + 摄像头)
.ov7725_pclk (ov7725_pclk), //摄像头像素时钟
.ov7725_href (ov7725_href), //摄像头行同步信号
.ov7725_vsync(ov7725_vsync), //摄像头场同步信号
.ov7725_data (ov7725_data), //摄像头图像数据
.cfg_done (cfg_done), //寄存器配置完成
.sccb_scl (sccb_scl), //SCL
.sccb_sda (sccb_sda), //SDA
.ov7725_wr_en (wr_en), //图像数据有效使能信号
.ov7725_data_out(wr_data) //图像数据
);
endmodule
| 6.854354 |
module tb_overall #(
parameter AMBA_WORD = 32,
parameter AMBA_ADDR_WIDTH = 20,
parameter DATA_WIDTH = 32
);
Interface IF ();
Stimulus stm (.stim_bus(IF));
Checker chk (.chkbus(IF));
GoldModel gld (.goldenbus(IF));
golden_bank gldbnk (.goldenbnk(IF));
Coverage covbus (.covbus(IF));
//=================================================== DUT INSTANTATION
ecc_enc_dec ECC_ENC_DEC_inst (
.clk(IF.clk),
.rst(IF.rst),
.PADDR(IF.paddr),
.PWRITE(IF.pwrite),
.PSEL(IF.psel),
.PENABLE(IF.penable),
.PWDATA(IF.pwdata),
.PRDATA(IF.prdata),
.data_out(IF.data_out),
.operation_done(IF.operation_done),
.err_num(IF.num_of_errors)
);
//==================================================================== SHADOW REGISTERS INSTANTATION
//====================================================================
//========================================================================
//clk generator
initial begin : reset_generator_proc
#10.2ps IF.rst = 0;
#10 IF.rst = 1;
end
always begin : clock_generator_proc
#1 IF.clk = ~IF.clk;
end
endmodule
| 6.550032 |
module: packet_sender
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_packet_sender;
// Inputs
reg clk;
reg reset;
reg wr_dst_rdy_i;
reg [7:0] packet_size_i;
reg start;
// Outputs
wire [3:0] wr_flags_o;
wire [31:0] wr_data_o;
wire wr_src_rdy_o;
// Instantiate the Unit Under Test (UUT)
packet_sender uut (
.clk(clk),
.reset(reset),
.wr_flags_o(wr_flags_o),
.wr_data_o(wr_data_o),
.wr_src_rdy_o(wr_src_rdy_o),
.wr_dst_rdy_i(wr_dst_rdy_i),
.packet_size_i(packet_size_i),
.start(start)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 1;
wr_dst_rdy_i = 0;
packet_size_i = 8'b0001_0000;
start = 0;
#100;
reset <= 0;
wr_dst_rdy_i <= 1;
@(posedge clk);
start <= 1;
@(posedge clk);
start <= 0;
#2000;
// Simulate a pause flag from the MAC
wr_dst_rdy_i <= 0;
#200;
wr_dst_rdy_i <= 1;
// Wait for EOF
wait(wr_flags_o == 4'b0010);
@(posedge clk);
@(posedge clk);
$stop;
end
always begin
#10;
clk = ~clk;
end
endmodule
| 6.779287 |
module tb_padding ();
parameter DATA_WIDTH = 32;
parameter STRIDE = 2;
parameter IMAGE_WIDTH = 6; //Width
parameter IMAGE_HEIGHT = 6; //Height
parameter PADDING = 3; //3*3 Kernel
parameter CHANNEL_NUM = 4; //Height
localparam IMAGE_SIZE = IMAGE_WIDTH * IMAGE_HEIGHT;
localparam IMAGE_SIZE_PADDING = (IMAGE_WIDTH + (PADDING * 2)) * (IMAGE_HEIGHT + (PADDING * 2));
parameter T = 10000;
parameter C = 1.25;
parameter I = 2.5;
reg clk;
reg reset;
reg valid_in;
reg [DATA_WIDTH-1:0] pxl_in;
wire [DATA_WIDTH-1:0] pxl_out;
wire valid_out;
integer i;
// reg clk ;
// reg reset ;
// reg valid_in ;
// reg [DATA_WIDTH-1:0] pxl_in ;
// reg valid_in_weight;
// reg [DATA_WIDTH-1:0] weight ;
// wire [DATA_WIDTH-1:0] pxl_out ;
// wire valid_out;
reg [DATA_WIDTH-1:0] In [ (IMAGE_SIZE*CHANNEL_NUM)-1:0];
reg [DATA_WIDTH-1:0] out_padding[(IMAGE_SIZE_PADDING*CHANNEL_NUM)-1:0];
reg [DATA_WIDTH-1:0] Out;
initial begin
clk = 0;
i = 0;
valid_in = 1'b0;
reset = 1;
// stride = 1;
#I reset = 0;
valid_in <= 1'b0;
$readmemb("D:/GitHub/CNNs/Floating_points/Floating_points.srcs/sources_1/new/data_test.txt",
In);
$readmemh("D:/GitHub/CNNs/Text_file/out_padding_4channel.txt", out_padding);
Out = $fopen("D:/GitHub/CNNs/Text_file/out_padding_4channel.txt");
end
always #(C) clk = ~clk;
always @(posedge clk) begin
pxl_in <= In[i];
valid_in <= 1'b1;
if (i >= IMAGE_SIZE * CHANNEL_NUM) begin
valid_in <= 1'b0;
end
#(I) i <= i + 1'b1;
if (valid_out == 1'b1) begin
$fdisplay(Out, "%b", pxl_out);
end
if (i == T) begin
$finish;
end
end
// conv_3x3_pad1_str2 #(
// .DATA_WIDTH (DATA_WIDTH ),
// .STRIDE (STRIDE ),
// .IMAGE_WIDTH (IMAGE_WIDTH ),
// .IMAGE_HEIGHT(IMAGE_HEIGHT),
// .KERNEL_SIZE (KERNEL_SIZE )
// ) DUT (
// //input
// .clk (clk ),
// .reset (reset ),
// .valid_in (valid_in ),
// .pxl_in (pxl_in ),
// //kernel 3x3
// .weight (weight ),
// .valid_in_weight(valid_in_weight),
// //output
// .pxl_out (pxl_out ),
// .valid_out (valid_out )
// );
// buffer #(
// .IMAGE_WIDTH(IMAGE_WIDTH),
// .KERNEL_SIZE(KERNEL_SIZE),
// .DIN_WIDTH (DATA_WIDTH )
// ) DUT (
// clk,
// reset,
// valid_in,
// in,
// stride,
// pxl_00,
// pxl_01,
// pxl_02,
// pxl_03,
// pxl_04,
// pxl_05,
// pxl_06,
// pxl_07,
// pxl_08,
// valid_out
// );
conv_3x3_top #(
.IMAGE_WIDTH (IMAGE_WIDTH),
.IMAGE_HEIGHT(IMAGE_HEIGHT),
.PADDING (PADDING),
.DATA_WIDTH (DATA_WIDTH),
.CHANNEL_NUM (CHANNEL_NUM)
) DUT (
clk,
reset,
valid_in,
pxl_in,
pxl_out,
valid_out
);
endmodule
| 6.709442 |
module tb_parallel_converter;
reg [ 9:0] counter;
reg clock;
reg reset;
reg enable;
reg [ 65 : 0] data;
wire valid;
wire [(66*10)-1 : 0] out;
reg [(66*10)-1 : 0] out_aux;
reg [ 65:0] lanes [0 : 9];
integer i;
initial begin
clock = 0;
reset = 1;
enable = 0;
data = {66{1'b0}};
counter = 0;
#5 reset = 0;
end
always @(posedge clock) begin
counter <= counter + 1;
if (counter == 10) enable <= 1;
else if (counter > 10) data <= data + 1;
end
always @(posedge clock) begin
if (valid) out_aux <= out;
end
always #2.5 clock = ~clock;
parallel_converter #(
.LEN_CODED_BLOCK(66),
.N_LANES(10)
) u_parallel_converter (
.i_clock (clock),
.i_reset (reset),
.i_enable(enable),
.i_data (data),
.o_valid (valid),
.o_data (out)
);
always @* begin //para ver cada dato por separado
for (i = 0; i < 10; i = i + 1) lanes[i] = out_aux[(((66*10)-1)-(i*66))-:66];
end
endmodule
| 6.580864 |
module tb_parallel_crc_ccitt;
reg clk;
reg reset;
reg enable;
reg init;
reg [ 7:0] data_in;
wire [15:0] crc_out;
serial_crc_ccitt dut (
clk,
reset,
enable,
init,
data_in,
crc_out
);
initial begin
clk = 0;
data_in = 0;
init = 0;
enable = 1;
forever #10 clk = ~clk;
end
task resetit;
begin
@(negedge clk) reset = 1'b1;
@(negedge clk) reset = 1'b0;
end
endtask
initial begin
resetit;
data_in = 1'b0;
repeat (30) begin
data_in = {$random} % 256;
#10;
end
#10 $stop;
end
initial begin
$monitor("data_in=%b, crc_out=%b", data_in, crc_out);
end
endmodule
| 6.580864 |
module tb_parall_interf ();
parameter setup_time = 2;
parameter hold_time = 2;
parameter data_time = 4;
parameter read_wait = 5;
parameter read_time = 2;
reg tb_sclk;
reg tb_rst_n;
reg tb_cs_n;
reg tb_rd_n;
reg tb_wr_n;
reg [7:0] tb_addr;
reg [15:0] wr_data;
wire [15:0] tb_data;
assign tb_data = (tb_wr_n == 1'b0) ? wr_data : 16'hzzzz;
initial begin
tb_sclk = 1'b0;
tb_rst_n = 1'b0;
#200;
tb_rst_n = 1'b1;
end
always #10 tb_sclk = ~tb_sclk;
parall_interf parall_interf_instance (
.sclk (tb_sclk),
.rst_n(tb_rst_n),
.cs_n (tb_cs_n),
.rd_n (tb_rd_n),
.wr_n (tb_wr_n),
.data (tb_data),
.addr (tb_addr)
);
initial begin
tb_cs_n = 1'b1;
tb_rd_n = 1'b1;
tb_wr_n = 1'b1;
tb_addr = 8'h00;
wr_data = 16'h0000;
//@(posedge tb_rst_n);
#300;
write_data(8);
#100;
read_data(8);
end
//reg [7:0] tb_addr;
//reg [15:0] tb_data;
task write_data(len);
integer i, len;
begin
for (i = 0; i < len; i = i + 1) begin
tb_cs_n = 1'b0;
tb_rd_n = 1'b1;
tb_wr_n = 1'b1;
tb_addr = i[7:0];
wr_data = i[15:0];
setup_dly();
tb_wr_n = 1'b0;
data_dly();
tb_wr_n = 1'b1;
hold_dly();
//tb_cs_n=1'b1;
end
tb_cs_n = 1'b1;
end
endtask
task read_data(len);
integer i, len;
begin
for (i = 0; i < len; i = i + 1) begin
tb_cs_n = 1'b0;
tb_rd_n = 1'b1;
tb_wr_n = 1'b1;
tb_addr = i[7:0];
read_dly();
tb_rd_n = 1'b0;
data_dly();
$display("read data addr is %d = %d", i, tb_data);
tb_rd_n = 1'b1;
//tb_cs_n=1'b1;
end
tb_cs_n = 1'b1;
end
endtask
task setup_dly();
integer i;
begin
for (i = 0; i < setup_time; i = i + 1) @(posedge tb_sclk);
end
endtask
task hold_dly();
integer i;
begin
for (i = 0; i < hold_time; i = i + 1) @(posedge tb_sclk);
end
endtask
task data_dly();
integer i;
begin
for (i = 0; i < data_time; i = i + 1) @(posedge tb_sclk);
end
endtask
task wait_dly();
integer i;
begin
for (i = 0; i < read_wait; i = i + 1) @(posedge tb_sclk);
end
endtask
task read_dly();
integer i;
begin
for (i = 0; i < read_time; i = i + 1) @(posedge tb_sclk);
end
endtask
endmodule
| 7.095777 |
module tb_parking_system;
// Inputs
reg clk;
reg reset_n;
reg sensor_entrance;
reg sensor_exit;
reg [1:0] password_1;
reg [1:0] password_2;
// Outputs
wire GREEN_LED;
wire RED_LED;
wire [6:0] HEX_1;
wire [6:0] HEX_2;
// Instantiate the Unit Under Test (UUT)
parking_system uut (
.clk(clk),
.reset_n(reset_n),
.sensor_entrance(sensor_entrance),
.sensor_exit(sensor_exit),
.password_1(password_1),
.password_2(password_2),
.GREEN_LED(GREEN_LED),
.RED_LED(RED_LED),
.HEX_1(HEX_1),
.HEX_2(HEX_2)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
// Initialize Inputs
reset_n = 0;
sensor_entrance = 0;
sensor_exit = 0;
password_1 = 0;
password_2 = 0;
// Wait 100 ns for global reset to finish
#100;
reset_n = 1;
#20;
sensor_entrance = 1;
#1000;
sensor_entrance = 0;
password_1 = 1;
password_2 = 2;
#2000;
sensor_exit = 1;
// Add stimulus here
end
endmodule
| 6.907139 |
module receives signals from a Test sequence
// which are sent to a data monitor.
`ifndef TB_PASSIVE
`define TB_PASSIVE
// scale time unit (value of one) / precision
`timescale 1ns / 100ps
// Includes verilog files
// Can be omitted and called from the testbench
`include "./src/Passive_b.v"
`include "./src/Passive_s.v"
`include "./testers/t_passive.v"
// Testbench module
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
module TestsBench;
wire PassiveSignal_b_tb, PassiveSignal_s_tb, CarLightsOnSign, OpenDoorSign, IgnitionSignalOn;
// Behavioral alarm description
Passive_b tb_Passive_b( /*AUTOINST*/
.PassiveSignal_b (PassiveSignal_b_tb),
.CarLightsOnSign (CarLightsOnSign),
.OpenDoorSign (OpenDoorSign),
.IgnitionSignalOn (IgnitionSignalOn)
);
// Structural description of alarm
Passive_s tb_Passive_s( /*AUTOINST*/
.PassiveSignal_s (PassiveSignal_s_tb),
.CarLightsOnSign (CarLightsOnSign),
.OpenDoorSign (OpenDoorSign),
.IgnitionSignalOn (IgnitionSignalOn)
);
// Tester: signal generator and monitor
tester tester_testbench(/*AUTOINST*/
.PassiveSignal_s (PassiveSignal_s_tb),
.PassiveSignal_b (PassiveSignal_b_tb),
.CarLightsOnSign (CarLightsOnSign),
.OpenDoorSign (OpenDoorSign),
.IgnitionSignalOn (IgnitionSignalOn)
);
endmodule
| 8.459918 |
module tb_upcntr;
// Inputs
reg clk, reset;
// Outputs
wire [3:0] cnt;
// Instantiate the Unit Under Test (UUT)
upcntr uut (
.clk(clk),
.reset(reset),
.din(din),
.pattern_detect(pattern_detect)
);
initial begin
$dumpfile("tb_upcntr.vcd");
$dumpvars(0, tb_upcntr);
// Initialize Inputs
clk = 0;
reset = 1;
#3000 $finish;
end
always #10 clk = ~clk;
always #123 reset = 0;
endmodule
| 7.679218 |
module tb_pattern_gen (
input wire i_clk,
input wire i_res_n,
output wire [7:0] o_ptn
);
parameter LSB_POS = 10;
reg [31:0] r_cnt;
always @(posedge i_clk or negedge i_res_n) begin
if (~i_res_n) begin
r_cnt <= 32'd0;
end else begin
r_cnt <= r_cnt + 32'd1;
end
end
assign o_ptn[7:0] = r_cnt[LSB_POS+7:LSB_POS];
endmodule
| 6.502916 |
module tb_hmac;
localparam DataLength = 20;
// HMAC input
reg clk, rst_n, start, stop;
reg [1087:0] passward_in;
reg [127:0] salt_in;
reg [255:0] golden;
wire [255:0] key_out;
wire ready;
reg [1087:0] pw_mem[0:DataLength-1];
reg [127:0] salt_mem[0:DataLength-1];
reg [255:0] golden_mem[0:DataLength-1];
integer i, err_num;
PBKDF2 pbkdf2 (
.clk(clk),
.rst_n(rst_n),
.i_start(start),
.i_pw(passward_in),
.i_salt(salt_in),
.o_key(key_out),
.o_ready(ready)
);
`ifdef SDF
initial $sdf_annotate(`SDFFILE, pbkdf2);
`endif
initial $readmemh(`PASSWORD_IN, pw_mem);
initial $readmemh(`SALT_IN, salt_mem);
initial $readmemh(`GOLDEN, golden_mem);
initial begin
clk = 0;
rst_n = 1;
end
always #(`HCYCLE) clk = ~clk;
initial begin
$fsdbDumpfile("pbkdf2.fsdb");
$fsdbDumpvars;
end
initial begin
start = 0;
stop = 0;
err_num = 0;
i = 0;
passward_in = 0;
salt_in = 0;
golden = 0;
#(`CYCLE);
rst_n = 0;
#(`CYCLE);
rst_n = 1;
#(`CYCLE);
start = 1;
passward_in = pw_mem[i];
salt_in = salt_mem[i];
golden = golden_mem[i];
#(`CYCLE * 2);
start = 0;
end
always @(posedge ready) begin
#(`HCYCLE);
if (key_out !== golden) begin
$display("Error at %d:\nmsg=%h\nkey=%h\noutput=%h\nexpect=%h", i, passward_in, salt_in,
key_out, golden);
err_num = err_num + 1;
end
i = i + 1;
#(`HCYCLE);
if (i == DataLength) stop = 1;
else begin
#(`CYCLE);
rst_n = 0;
#(`CYCLE);
rst_n = 1;
#(`CYCLE);
#(`HCYCLE);
start = 1;
passward_in = pw_mem[i];
salt_in = salt_mem[i];
golden = golden_mem[i];
#(`CYCLE * 2);
start = 0;
end
end
always @(posedge stop) begin
if (err_num == 0) begin
$display("---------------------------------------------\n");
$display("All data have been generated successfully!\n");
$display("--------------------PASS--------------------\n");
$display("---------------------------------------------\n");
end else begin
$display("---------------------------------------------\n");
$display("There are %d errors!\n", err_num);
$display("--------------------FAIL--------------------\n");
$display("---------------------------------------------\n");
end
#(`CYCLE);
i = 0;
err_num = 0;
// finish tb
#(`CYCLE) $finish;
end
initial begin
#(`CYCLE * 10000 * DataLength);
$display("--------------------FAIL--------------------\n");
$display("Too slow....");
#(`CYCLE) $finish;
end
endmodule
| 6.66928 |
module tb_pc ();
reg clk;
reg rst;
reg [31:0] pcin;
wire [31:0] pc;
wire inst_ce;
pc mypc (
.clk(clk),
.rst(rst),
.pcin(pcin),
.pc(pc),
.inst_ce(inst_ce)
);
initial begin
clk = 0;
end
always #1 clk = ~clk;
initial begin
rst = 1;
pcin = 32'b0;
#5 rst = 0;
#20 rst = 1;
end
//module pc(
// input clk,
// input rst,
// input [31:0] pcin,
// output reg [31:0] pc,
// output reg inst_ce
// );
endmodule
| 6.666841 |
module tb_pc_mux ();
localparam STEP = 10;
reg [31 : 0] pc;
reg [31 : 0] rs1;
reg [31 : 0] imm;
reg [`SEL_PC_WIDTH - 1 : 0] pc_sel;
reg taken;
reg stall;
wire [31 : 0] next_pc;
pc_mux pc_mux (
.pc(pc),
.rs1(rs1),
.imm(imm),
.pc_sel(pc_sel),
.taken(taken),
.stall(stall),
.next_pc(next_pc)
);
initial begin
pc = 32'h0;
rs1 = 32'h8;
imm = 32'h8;
pc_sel = `SEL_PC_NONE;
taken = 0;
stall = 0;
#(STEP * 10)
// pc = pc + 4
for (
integer i = 0; i < 4; i = i + 1
) begin
#(STEP) pc_sel = `SEL_PC_ADD4;
$display("next_pc: %h", next_pc);
pc = next_pc;
end
// pc = pc + imm
#(STEP) pc_sel = `SEL_PC_JAL;
taken = 1;
$display("next_pc: %h", next_pc);
pc = next_pc;
// pc = rs1 + imm;
#(STEP) pc_sel = `SEL_PC_JALR;
taken = 1;
$display("next_pc: %h", next_pc);
pc = next_pc;
// pc = pc
for (integer i = 0; i < 4; i = i + 1) begin
#(STEP) stall = 1;
pc_sel = `SEL_PC_ADD4;
taken = 0;
$display("next_pc: %h", next_pc);
pc = next_pc;
end
#(STEP * 100) $stop;
end
endmodule
| 7.105148 |
module tb ();
reg clk;
reg reset;
reg countSteps;
reg updateWeight;
reg dualUpdateWeights;
reg [7 : 0] A, B;
reg [2 : 0] Addr1, Addr2;
reg [7 : 0] Data1, Data2;
pedometer Ped (
.clk(clk),
.reset(reset),
.countSteps(countSteps),
.updateWeight(updateWeight),
.dualUpdateWeights(dualUpdateWeights),
.A(A),
.B(B),
.Addr1(Addr1),
.Addr2(Addr2),
.Data1(Data1),
.Data2(Data2)
);
initial begin
clk = 1'b0;
reset = 1'b0;
countSteps = 1'b1;
updateWeight = 1'b0;
dualUpdateWeights = 1'b0;
A = 8'd30;
B = 8'd30;
Addr1 = 3'b0;
Addr2 = 3'b0;
Data1 = 8'b0;
Data2 = 8'b0;
#5 reset = 1'b0;
countSteps = 1'b1;
updateWeight = 1'b0;
dualUpdateWeights = 1'b0;
A = 8'd10;
B = 8'd10;
Addr1 = 3'b0;
Addr2 = 3'b0;
Data1 = 8'b0;
Data2 = 8'b0;
#5 reset = 1'b0;
countSteps = 1'b1;
updateWeight = 1'b0;
dualUpdateWeights = 1'b0;
A = 8'd0;
B = 8'd0;
Addr1 = 3'b0;
Addr2 = 3'b0;
Data1 = 8'b0;
Data2 = 8'b0;
#5 reset = 1'b1;
countSteps = 1'b1;
updateWeight = 1'b0;
dualUpdateWeights = 1'b0; // Reset = 1
A = 8'd30;
B = 8'd30;
Addr1 = 3'b0;
Addr2 = 3'b0;
Data1 = 8'b0;
Data2 = 8'b0;
#5 reset = 1'b0;
countSteps = 1'b0;
updateWeight = 1'b1;
dualUpdateWeights = 1'b0; // Reset = 0; updateWeight = 1; dualUpdate = 0
A = 8'd30;
B = 8'd30;
Addr1 = 3'd1;
Addr2 = 3'b0;
Data1 = 8'd5;
Data2 = 8'b0; // Addr1 = 1; Data1 = 8'd5;
#5 clk = 1'b0;
reset = 1'b0;
countSteps = 1'b1;
updateWeight = 1'b0;
dualUpdateWeights = 1'b0; // Reset = 0; updateWeight = 1; dualUpdate = 1
A = 8'd30;
B = 8'd30;
Addr1 = 3'd1;
Addr2 = 3'd2;
Data1 = 8'd5;
Data2 = 8'd6; // Addr1 = 1; Data1 = 8'd5; Addr = 2; Data2 = 8'd6
#5 clk = 1'b0;
reset = 1'b0;
countSteps = 1'b1;
updateWeight = 1'b0;
dualUpdateWeights = 1'b0; // Dummy Case
A = 8'd30;
B = 8'd30;
Addr1 = 3'b0;
Addr2 = 3'b0;
Data1 = 8'b0;
Data2 = 8'b0;
end
always #5 clk = ~clk;
initial begin
$dumpfile("pedometer.vcd");
$dumpvars();
#200 $finish;
end
endmodule
| 7.195167 |
module: Permute
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_Permute;
// Inputs
reg [263:0] state_in;
reg [15:0] IV_in, INV_IV_in;
reg clk;
reg rst;
reg en;
// Outputs
wire [263:0] state_out;
wire [15:0] IV_out, INV_IV_out;
wire rdy;
// Instantiate the Unit Under Test (UUT)
Permute uut (
.state_in(state_in),
.IV_in(IV_in),
.INV_IV_in(INV_IV_in),
.state_out(state_out),
.IV_out(IV_out),
.INV_IV_out(INV_IV_out),
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy)
);
reg [31:0] iteration;
integer i, j;
initial begin
// Initialize Inputs
state_in = 0;
clk = 0;
rst = 1;
en = 0;
iteration = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here (run for 49.00us)
rst = 0;
IV_in = 16'hc6;
INV_IV_in = 16'h0;
$display("[INITIALIZING]");
for (i=0; i<`nSBox; i=i+1) begin
state_in = state_in | i<<(i*8);
end
j = 0;
$display("state in: %h", state_in);
en = 1;
repeat (135) begin
rst = 0;
repeat (70) begin // takes 70 cycles (optimizable?)
#5;
end
if (rdy) begin
// feed new state input
state_in = state_out;
IV_in = IV_out;
INV_IV_in = INV_IV_out;
end
rst = 1;
j = j+1;
if (j == 135)
$display("state_out: %h", state_out);
#5;
end
end
always begin
#5; clk = !clk;
end
endmodule
| 6.536171 |
module tb_pe_array_bd;
// Inputs
reg clk;
reg rst;
reg load;
reg din_v;
reg [`DATA_WIDTH*2-1:0] din;
wire dout_v;
wire [`DATA_WIDTH*2-1:0] dout;
// Instantiate the Unit Under Test (UUT)
pe_array_bd uut (
.clk(clk),
.rst(rst),
.load(load),
.din_v(din_v),
.din(din),
.dout_v(dout_v),
.dout(dout)
);
parameter PERIOD = 20;
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
integer cycle;
initial cycle = 0;
always @(posedge clk) cycle = cycle + 1;
integer data_file; // file handler
integer scan_file; // file handler
integer fd;
reg [`DATA_WIDTH*2-1:0] captured_data;
reg [`DATA_WIDTH*2-1:0] dout_r;
reg dout_v_r;
always @(posedge clk) begin
dout_r <= dout;
dout_v_r <= dout_v;
// if (dout_v_r)
$fwrite(fd, "%x\n", dout);
scan_file = $fscanf(data_file, "%x\n", captured_data);
if (!$feof(data_file) && !rst) begin
//use captured_data as you would any other wire or reg value;
din <= captured_data;
din_v <= 1;
end else begin
din <= 0;
din_v <= 0;
end
// if (dout_v)
end
reg sim_done = 0;
// always @(posedge clk) begin
// if (din_v)
// $fwrite(fd, "%x\n", din);
// if (sim_done) begin
// $fclose(fd);
// $finish;
// end
// end
initial begin
// Initialize Inputs
clk = 0;
load = 0;
din_v = 0;
din = 0;
// Wait 100 ns for global reset to finish
rst = 1;
#100;
// Add stimulus here
#20;
rst = 0;
// Load the data
// data_file = $fopen("array_input_hex.txt", "rb"); //read mode, binary (128-PE array -> 256*32*2)
data_file = $fopen(
"/home/louis/workspace/vivado/pe_array_bd/pe_array_bd.srcs/sim_1/new/array16_input_hex.txt",
"rb"
); //read mode, binary (8-PE array -> 16*32*2)
if (data_file == `NULL) begin
$display("data_file handle was NULL");
$stop; // $finish;
end
#20;
fd = $fopen("/home/louis/workspace/vivado/pe_array_bd/pe_array_bd.srcs/sim_1/new/log.txt",
"w"); // write mode
if (fd == `NULL) begin
$display("Could not open file '%s' for writing", "log.txt");
$stop;
end
#5000;
sim_done = 1; //
end
endmodule
| 6.5146 |
module tb_con ();
parameter L_RAM_SIZE = 4;
parameter CLK_PERIOD = 10;
reg aclk;
reg aresetn;
reg start;
reg [31:0] din;
wire done;
wire [L_RAM_SIZE:0] rdaddr;
//input data
reg [31:0] din_mem[2**(L_RAM_SIZE+1)-1:0];
integer i;
initial begin
aclk <= 0;
start <= 0;
aresetn <= 0;
#(CLK_PERIOD * 5);
aresetn <= 1;
#(CLK_PERIOD * 5);
start = 1;
#(CLK_PERIOD);
start = 0;
end
initial $readmemh("din.txt", din_mem);
always @(posedge aclk) din <= din_mem[rdaddr];
always #(CLK_PERIOD / 2) aclk = ~aclk;
pe_con #(2 ** L_RAM_SIZE, L_RAM_SIZE) UUT (
.start(start),
.aclk(aclk),
.aresetn(aresetn),
.rddata(din),
.done(done),
.rdaddr(rdaddr)
);
endmodule
| 6.644733 |
module tb_pe_simd;
// Inputs
reg clk;
reg rst;
reg din_v;
reg [`DATA_WIDTH*2-1:0] din_pe;
reg inst_in_v;
reg [`INST_WIDTH-1:0] inst_in;
// Outputs
wire dout_v;
wire [`DATA_WIDTH*2-1:0] dout_pe;
// Instantiate the Unit Under Test (UUT)
pe_simd uut (
.clk(clk),
.rst(rst),
.din_v(din_v),
.din_pe(din_pe),
.inst_in_v(inst_in_v),
.inst_in(inst_in),
.dout_v(dout_v),
.dout_pe(dout_pe)
);
parameter PERIOD = 20;
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
integer cycle;
initial cycle = 0;
always @(posedge clk) cycle = cycle + 1;
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
din_v = 0;
din_pe = 0;
inst_in_v = 0;
// Wait 100 ns for global reset to finish
rst = 1;
#100;
// Add stimulus here
#20;
rst = 0;
#20;
#20;
// Load the instructions
#20; // inst_in_v = 1; inst_in = 64'h0_0_0000000_0_00_00_00; // din_pe
#20; // inst_in_v = 1; inst_in = 64'h0_0_0000000_0_01_00_00; // din_pe
#20; // inst_in_v = 1; inst_in = 64'h0_0_0000000_0_02_00_00; // din_pe
#20; // inst_in_v = 1; inst_in = 64'h0_0_0000000_0_03_00_00; // din_pe
#20; // inst_in_v = 1; inst_in = 64'h0_0_0000000_0_04_00_00; // din_pe
#20; // inst_in_v = 1; inst_in = 64'h0_0_0000000_0_05_00_00; // din_pe
#20;
inst_in_v = 1;
inst_in = 32'h60_01_00_80; // CMPLX_MULT
#20;
inst_in_v = 1;
inst_in = 32'h60_03_02_81; // CMPLX_MULT
#20;
inst_in_v = 1;
inst_in = 32'h60_05_04_82; // CMPLX_MULT
// Load the data
#20;
inst_in_v = 0;
inst_in = 0;
din_v = 0;
#20;
inst_in_v = 0;
inst_in = 0;
din_v = 0;
#20;
inst_in_v = 0;
inst_in = 0;
din_v = 1;
din_pe = 32'h0004_0002; // 4 + j*2
#20;
inst_in_v = 0;
inst_in = 0;
din_v = 1;
din_pe = 32'h0003_0001; // 3 + j*1
#20;
inst_in_v = 0;
inst_in = 0;
din_v = 1;
din_pe = 32'h0008_0006; // 8 + j*6
#20;
inst_in_v = 0;
inst_in = 0;
din_v = 1;
din_pe = 32'h0007_0005; // 7 + j*5
#20;
inst_in_v = 0;
inst_in = 0;
din_v = 1;
din_pe = 32'h000c_000a; // 12 + j*10
#20;
inst_in_v = 0;
inst_in = 0;
din_v = 1;
din_pe = 32'h000b_0009; // 11 + j*9
#20;
din_v = 0;
din_pe = 1;
#20;
din_v = 0;
din_pe = 2;
#20;
din_v = 0;
din_pe = 3;
#20;
din_v = 0;
din_pe = 4;
#20;
din_v = 0;
din_pe = 5;
#20;
din_v = 0;
din_pe = 6;
#1000;
end
endmodule
| 6.562255 |
module tb_phase_ctrl ();
reg clk, rst_n;
reg send_signal;
wire gen_en, phase_ctrl;
wire ram_clk;
wire [7:0] ram_rd_data;
wire ram_en;
wire [7:0] ram_addr;
wire ram_we;
wire [7:0] ram_wr_data;
wire ram_rst;
initial begin
clk = 1;
rst_n = 0;
send_signal = 0;
#10 rst_n = 1;
send_signal = 1;
end
always begin
#5 // 100MHz
clk = ~clk;
end
//always begin
// #62500000 // 100MHz
// send_signal=~send_signal;
//end
Phase_Ctrl uut (
.clk (clk),
.rst_n (rst_n),
.send_signal(send_signal),
.gen_en (gen_en),
.phase_ctrl (phase_ctrl),
.ram_clk (ram_clk),
.ram_rd_data(ram_rd_data),
.ram_en (ram_en),
.ram_addr (ram_addr),
.ram_we (ram_we),
.ram_wr_data(ram_wr_data),
.ram_rst (ram_rst)
);
blk_mem_gen_0 your_instance_name (
.clkb (ram_clk), // input wire clkb
.enb (ram_en), // input wire enb
.web (ram_we), // input wire [0 : 0] web
.addrb(ram_addr), // input wire [7 : 0] addrb
.dinb (ram_wr_data), // input wire [7 : 0] dinb
.doutb(ram_rd_data) // output wire [7 : 0] doutb
);
endmodule
| 6.505544 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire reset, clk1f, clk2f, clk4f, clk32f;
wire [7:0] in0_TB, in1_TB, in2_TB, in3_TB;
wire [7:0] out0_BTB, out1_BTB, out2_BTB, out3_BTB, out_rx_txBTB;
wire [7:0] out0_STB, out1_STB, out2_STB, out3_STB, out_rx_txSTB;
wire [3:0] validout_STB;
wire [3:0] validout_BTB;
wire [3:0] validin_TB;
wire [7:0] out0_recir;
wire [7:0] out1_recir;
wire [7:0] out2_recir;
wire [7:0] out3_recir;
wire [7:0] valid_out_recir;
wire [7:0] out0_recir_s;
wire [7:0] out1_recir_s;
wire [7:0] out2_recir_s;
wire [7:0] out3_recir_s;
wire [7:0] valid_out_recir_s;
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY BEHAVIORAL
////////////
///////////////////////////////////////////////////////////////////////////////////////////
phy phy_tb ( /*AUTOINST*/
//Outputs
.out0_recir(out0_recir),
.out1_recir(out1_recir),
.out2_recir(out2_recir),
.out3_recir(out3_recir),
.valid_out_recir(valid_out_recir),
.out0(out0_BTB),
.out1(out1_BTB),
.out2(out2_BTB),
.out3(out3_BTB),
.validout(validout_BTB),
// Inputs
.clk1f(clk1f),
.clk2f(clk2f),
.clk4f(clk4f),
.clk32f(clk32f),
.reset(reset),
.in0(in0_TB),
.in1(in1_TB),
.in2(in2_TB),
.in3(in3_TB),
.validin(validin_TB)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY SYN
////////////
///////////////////////////////////////////////////////////////////////////////////////////
phy_syn phy_syn_tb ( /*AUTOINST*/
//Outputs
.out0_recir(out0_recir_s),
.out1_recir(out1_recir_s),
.out2_recir(out2_recir_s),
.out3_recir(out3_recir_s),
.valid_out_recir(valid_out_recir_s),
.out0(out0_STB),
.out1(out1_STB),
.out2(out2_STB),
.out3(out3_STB),
.validout(validout_STB),
// Inputs
.clk1f(clk1f),
.clk2f(clk2f),
.clk4f(clk4f),
.clk32f(clk32f),
.reset(reset),
.in0(in0_TB),
.in1(in1_TB),
.in2(in2_TB),
.in3(in3_TB),
.validin(validin_TB)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY TESTER
////////////
///////////////////////////////////////////////////////////////////////////////////////////
t_phy t_phy_tb ( /*AUTOINST*/
//Outputs
.out0_recir(out0_recir),
.out1_recir(out1_recir),
.out2_recir(out2_recir),
.out3_recir(out3_recir),
.valid_out_recir(valid_out_recir),
.out0_recir_s(out0_recir_s),
.out1_recir_s(out1_recir_s),
.out2_recir_s(out2_recir_s),
.out3_recir_s(out3_recir_s),
.valid_out_recir_s(valid_out_recir_s),
.out0(out0_BTB),
.out1(out1_BTB),
.out2(out2_BTB),
.out3(out3_BTB),
.validout(validout_BTB),
.out0_s(out0_STB),
.out1_s(out1_STB),
.out2_s(out2_STB),
.out3_s(out3_STB),
.validout_s(validout_STB),
// Inputs
.clk1f(clk1f),
.clk2f(clk2f),
.clk4f(clk4f),
.clk32f(clk32f),
.reset(reset),
.in0(in0_TB),
.in1(in1_TB),
.in2(in2_TB),
.in3(in3_TB),
.validin(validin_TB)
);
endmodule
| 7.554736 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire reset, clk1f, clk2f, clk4f, clk32f;
wire inTB;
wire [7:0] out0_BTB, out1_BTB, out2_BTB, out3_BTB, out_rx_txBTB;
wire [7:0] out0_STB, out1_STB, out2_STB, out3_STB, out_rx_txSTB;
wire [3:0] valid_out_mux14TB;
wire [3:0] valid_out_mux14TS;
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY_RX BEHAVIORAL
////////////
///////////////////////////////////////////////////////////////////////////////////////////
phy_rx phy_x_b ( /*AUTOINST*/
// Outputs
.out0(out0_BTB),
.out1(out1_BTB),
.out2(out2_BTB),
.out3(out3_BTB),
.out_rx_tx(out_rx_tx_BTB),
.valid_out_mux14(valid_out_mux14TB),
// Inputs
.clk1f(clk1f),
.clk2f(clk2f),
.clk4f(clk4f),
.clk32f(clk32f),
.reset(reset),
.in(inTB)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY_RX SYN
////////////
///////////////////////////////////////////////////////////////////////////////////////////
phy_rx_syn phy_x_s ( /*AUTOINST*/
// Outputs
.out0(out0_STB),
.out1(out1_STB),
.out2(out2_STB),
.out3(out3_STB),
.out_rx_tx(out_rx_tx_STB),
.valid_out_mux14(valid_out_mux14TS),
// Inputs
.clk1f(clk1f),
.clk2f(clk2f),
.clk4f(clk4f),
.clk32f(clk32f),
.reset(reset),
.in(inTB)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY_RX TESTER
////////////
///////////////////////////////////////////////////////////////////////////////////////////
t_phy_rx t_phy_rx_tb ( /*AUTOINST*/
// Outputs
.out0(out0_BTB),
.out1(out1_BTB),
.out2(out2_BTB),
.out3(out3_BTB),
.out_rx_tx(out_rx_tx_BTB),
.out0_s(out0_STB),
.out1_s(out1_STB),
.out2_s(out2_STB),
.out3_s(out3_STB),
.out_rx_tx_s(out_rx_tx_STB),
.valid_out_mux14B(valid_out_mux14TB),
.valid_out_mux14S(valid_out_mux14TS),
// Inputs
.clk1f(clk1f),
.clk2f(clk2f),
.clk4f(clk4f),
.clk32f(clk32f),
.reset(reset),
.in(inTB)
);
endmodule
| 7.554736 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire reset_TB, clk1fTB, clk2fTB, clk4fTB, clk32fTB;
wire [7:0] in0_TB, in1_TB, in2_TB, in3_TB;
wire in_rx_txTB;
wire out_BTB, out_STB;
wire [3:0] validmux41_TB;
// wires for recirc module
wire [7:0] out0_recir_BTB;
wire [7:0] out1_recir_BTB;
wire [7:0] out2_recir_BTB;
wire [7:0] out3_recir_BTB;
wire [7:0] out0_recir_STB;
wire [7:0] out1_recir_STB;
wire [7:0] out2_recir_STB;
wire [7:0] out3_recir_STB;
/*AUTOREGINPUT*/
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY TX BEHAVIORAL
////////////
///////////////////////////////////////////////////////////////////////////////////////////
phy_tx_b phy_tx_b_TB ( /*AUTOINST*/
// One output
.out_b(out_BTB),
.out0_recir(out0_recir_BTB),
.out1_recir(out1_recir_BTB),
.out2_recir(out2_recir_BTB),
.out3_recir(out3_recir_BTB),
// clks at different frequency and reset
.clk1f(clk1fTB),
.clk2f(clk2fTB),
.clk4f(clk4fTB),
.clk32f(clk32fTB),
.reset(reset_TB),
// Four inputs
.in0(in0_TB),
.in1(in1_TB),
.in2(in2_TB),
.in3(in3_TB),
.in_rx_tx(in_rx_txTB),
// Valid for inputs
.validmux41(validmux41_TB)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY TX SYN
////////////
///////////////////////////////////////////////////////////////////////////////////////////
// Synthesis
phy_tx_b_syn phy_tx_b_syn_TB ( /*AUTOINST*/
// One output
.out_b(out_STB),
.out0_recir(out0_recir_STB),
.out1_recir(out1_recir_STB),
.out2_recir(out2_recir_STB),
.out3_recir(out3_recir_STB),
// clks at different frequency and reset
.clk1f(clk1fTB),
.clk2f(clk2fTB),
.clk4f(clk4fTB),
.clk32f(clk32fTB),
.reset(reset_TB),
// Four inputs
.in0(in0_TB),
.in1(in1_TB),
.in2(in2_TB),
.in3(in3_TB),
.in_rx_tx(in_rx_txTB),
// Valid for inputs
.validmux41(validmux41_TB)
);
///////////////////////////////////////////////////////////////////////////////////////////
//////////// PHY TX TESTER
////////////
///////////////////////////////////////////////////////////////////////////////////////////
t_phy_tx t_phy_tx_TB ( /*AUTOINST*/
//Outputs
.out_s(out_STB),
.out_b(out_BTB),
// Clks at different frequency and reset
.clk1f (clk1fTB),
.clk2f (clk2fTB),
.clk4f (clk4fTB),
.clk32f(clk32fTB),
.reset (reset_TB)
);
t_active t_active (.in_rx_tx(in_rx_txTB));
t_data t_data (
.in0(in0_TB),
.in1(in1_TB),
.in2(in2_TB),
.in3(in3_TB),
.validmux41(validmux41_TB)
);
endmodule
| 7.554736 |
module TB_PID;
parameter WAITTIME = 10;
parameter CLKTIME = 500000000;
reg clk, reset;
wire ready;
reg signed [15:0] PV;
wire signed [15:0] result;
reg signed [15:0] Kp;
reg signed [15:0] Kd;
reg signed [15:0] Ki;
reg enable;
PID pid (
.clk(clk),
.reset(!reset),
.Kp(Kp),
.Kd(Kd),
.Ki(Ki),
.Sp(16'd500),
.Pv(PV),
.data(result),
.ready(ready),
.enable(enable)
);
initial begin
$display("Setting Up");
PV = 0;
Kp = 0;
Kd = 0;
Ki = 0;
reset = 0;
clk = 0;
enable = 1;
#WAITTIME;
reset = 1;
#WAITTIME reset = 0;
end
always @(posedge ready) begin
$display(result);
PV = PV + (result / 10) + ($random % 11);
end
always #CLKTIME begin
clk = ~clk;
end
endmodule
| 6.579252 |
module tb_pingpang ();
//reg define
reg sys_clk;
reg sys_rst_n;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
initial begin
sys_clk = 1'b1;
sys_rst_n <= 1'b0;
#200 sys_rst_n <= 1'b1;
end
//sys_clk:模拟系统时钟，每10ns电平取反一次，周期为20ns，频率为50Mhz
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//-------------pingpang_inst-------------
pingpang pingpang_inst (
.sys_clk (sys_clk), //系统时钟
.sys_rst_n(sys_rst_n) //复位信号，低有效
);
endmodule
| 7.634423 |
module tb_PipelineCPU;
reg tb_i_clk;
reg tb_i_rst_n;
wire [31:0] tb_o_write_data;
parameter STEP = 10;
always #(STEP / 2) tb_i_clk = ~tb_i_clk; // clock assign
PipelineCPU abcdefg (
tb_i_clk,
tb_i_rst_n,
tb_o_write_data
);
initial begin
tb_i_clk = 1'b0;
tb_i_rst_n = 1'b0;
#15;
tb_i_rst_n = 1'b1;
#500;
$stop;
end
endmodule
| 7.326475 |
module: PipelineCPU_Hazards
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_PipelineCPU_Hazards;
// Inputs
reg i_clk;
reg i_rst_n;
// Outputs
wire [31:0] o_write_data;
// Instantiate the Unit Under Test (UUT)
PipelineCPU_Hazards uut (
.i_clk(i_clk),
.i_rst_n(i_rst_n),
.o_write_data(o_write_data)
);
parameter STEP =10;
always #(STEP/2) i_clk=~i_clk; // clock assign
initial begin
// Initialize Inputs
i_clk = 0;
i_rst_n = 0;
#15; i_rst_n = 1;
// Wait 100 ns for global reset to finish
#500;
$stop;
// Add stimulus here
end
endmodule
| 7.765113 |
module tb_pipelined_mips_forwarding ();
reg clk;
reg nrst;
wire [ `WORD_WIDTH - 1:0] inst; // 32-bit instruction (from instruction memory)
wire [ `WORD_WIDTH - 1:0] proc_data_in; // data from memory to processor
wire [ `WORD_WIDTH - 1:0] proc_data_out; // data from processor to memory
wire data_wr; // data memory write enable
wire [`MEM_ADDR_WIDTH - 1:0] inst_addr; // program counter
wire [`MEM_ADDR_WIDTH - 1:0] data_addr; // data memory address
wire [ 31:0] pc_IF;
wire [ 31:0] pc_ID;
wire [ 31:0] pc_EXE;
wire [ 31:0] pc_MEM;
wire [ 31:0] pc_WB;
// Debug signals
/* wire [31:0] IDec_inst;
wire flush_out;
wire IDec_wr_en;
wire IDec_data_wr;
wire [31:0] WBack_data;
wire [4:0] WBack_addr;*/
pipelined_mips_forwarding UUT (
.clk(clk),
.nrst(nrst),
.inst(inst),
.data_in(proc_data_in),
.inst_addr(inst_addr),
.data_addr(data_addr),
.data_out(proc_data_out),
.data_wr(data_wr),
.pc_IF(pc_IF),
.pc_ID(pc_ID),
.pc_EXE(pc_EXE),
.pc_MEM(pc_MEM),
.pc_WB(pc_WB) /*,
// Debug signals
.IDec_inst(IDec_inst),
.flush_out(flush_out),
.IDec_wr_en(IDec_wr_en),
.IDec_data_wr(IDec_data_wr),
.WBack_data(WBack_data),
.WBack_addr(WBack_addr)*/
);
instmem I1 (
.clk(clk),
.inst_addr(inst_addr),
.inst(inst)
);
datamem D1 (
.clk(clk),
.data_addr(data_addr),
.data_wr(data_wr),
.data_in(proc_data_in),
.data_out(proc_data_out)
);
datamem_ans D2 ();
always #(`CLK_PERIOD / 2) clk = ~clk;
integer i;
integer done;
integer check_done;
integer pass;
initial begin
$vcdplusfile("tb_pipelined_mips_forwarding.vpd");
$vcdpluson;
$sdf_annotate("../mapped/pipelined_mips_forwarding_mapped.sdf", UUT);
clk = 0;
nrst = 0;
done = 0;
check_done = 0;
#(`DEL_IN) nrst = 1;
end
always @(posedge clk) begin
if (inst == 32'h0) check_done = check_done + 1;
end
always @(posedge clk) begin
if (check_done == 10) done = 1;
end
always @(posedge done) begin
pass = 0;
$display("== SUMMARY ==");
$display("Actual \tExpected");
$display("========\t========");
for (i = 0; i < 100; i = i + 1) begin
if(D1.memory[(i*4)]==D2.memory[(i*4)] && D1.memory[(i*4)+1]==D2.memory[(i*4)+1] && D1.memory[(i*4)+2]==D2.memory[(i*4)+2] && D1.memory[(i*4)+3]==D2.memory[(i*4)+3]) begin
$display("%X%X%X%X\t%X%X%X%X\tPass", D1.memory[(i*4)], D1.memory[(i*4)+1],
D1.memory[(i*4)+2], D1.memory[(i*4)+3], D2.memory[(i*4)], D2.memory[(i*4)+1],
D2.memory[(i*4)+2], D2.memory[(i*4)+3]);
pass = pass + 1;
end else begin
$display("%X%X%X%X\t%X%X%X%X\tFail", D1.memory[(i*4)], D1.memory[(i*4)+1],
D1.memory[(i*4)+2], D1.memory[(i*4)+3], D2.memory[(i*4)], D2.memory[(i*4)+1],
D2.memory[(i*4)+2], D2.memory[(i*4)+3]);
end
end
$display("\n\n");
$display("Passed\t%d/%d test cases", pass, i); //*/
$finish;
end
endmodule
| 6.611668 |
module tb_pipelined_mips_raw ();
reg clk;
reg nrst;
wire [ `WORD_WIDTH - 1:0] inst; // 32-bit instruction (from instruction memory)
wire [ `WORD_WIDTH - 1:0] proc_data_in; // data from memory to processor
wire [ `WORD_WIDTH - 1:0] proc_data_out; // data from processor to memory
wire data_wr; // data memory write enable
wire [`MEM_ADDR_WIDTH - 1:0] inst_addr; // program counter
wire [`MEM_ADDR_WIDTH - 1:0] data_addr; // data memory address
wire [ 31:0] pc_IF;
wire [ 31:0] pc_ID;
wire [ 31:0] pc_EXE;
wire [ 31:0] pc_MEM;
wire [ 31:0] pc_WB;
// Debug signals
/* wire [31:0] IDec_inst;
wire flush_out;
wire IDec_wr_en;
wire IDec_data_wr;
wire [31:0] WBack_data;
wire [4:0] WBack_addr;*/
pipelined_mips_raw UUT (
.clk(clk),
.nrst(nrst),
.inst(inst),
.data_in(proc_data_in),
.inst_addr(inst_addr),
.data_addr(data_addr),
.data_out(proc_data_out),
.data_wr(data_wr),
.pc_IF(pc_IF),
.pc_ID(pc_ID),
.pc_EXE(pc_EXE),
.pc_MEM(pc_MEM),
.pc_WB(pc_WB) /*,
// Debug signals
.IDec_inst(IDec_inst),
.flush_out(flush_out),
.IDec_wr_en(IDec_wr_en),
.IDec_data_wr(IDec_data_wr),
.WBack_data(WBack_data),
.WBack_addr(WBack_addr)*/
);
instmem I1 (
.clk(clk),
.inst_addr(inst_addr),
.inst(inst)
);
datamem D1 (
.clk(clk),
.data_addr(data_addr),
.data_wr(data_wr),
.data_in(proc_data_in),
.data_out(proc_data_out)
);
datamem_ans D2 ();
always #(`CLK_PERIOD / 2) clk = ~clk;
integer i;
integer done;
integer check_done;
integer pass;
initial begin
$vcdplusfile("tb_pipelined_mips_raw.vpd");
$vcdpluson;
$sdf_annotate("../mapped/pipelined_mips_raw_mapped.sdf", UUT);
clk = 0;
nrst = 0;
done = 0;
check_done = 0;
#(`DEL_IN) nrst = 1;
end
always @(posedge clk) begin
if (inst == 32'h0) check_done = check_done + 1;
end
always @(posedge clk) begin
if (check_done == 10) done = 1;
end
always @(posedge done) begin
pass = 0;
$display("== SUMMARY ==");
$display("Actual \tExpected");
$display("========\t========");
for (i = 0; i < 100; i = i + 1) begin
if(D1.memory[(i*4)]==D2.memory[(i*4)] && D1.memory[(i*4)+1]==D2.memory[(i*4)+1] && D1.memory[(i*4)+2]==D2.memory[(i*4)+2] && D1.memory[(i*4)+3]==D2.memory[(i*4)+3]) begin
$display("%X%X%X%X\t%X%X%X%X\tPass", D1.memory[(i*4)], D1.memory[(i*4)+1],
D1.memory[(i*4)+2], D1.memory[(i*4)+3], D2.memory[(i*4)], D2.memory[(i*4)+1],
D2.memory[(i*4)+2], D2.memory[(i*4)+3]);
pass = pass + 1;
end else begin
$display("%X%X%X%X\t%X%X%X%X\tFail", D1.memory[(i*4)], D1.memory[(i*4)+1],
D1.memory[(i*4)+2], D1.memory[(i*4)+3], D2.memory[(i*4)], D2.memory[(i*4)+1],
D2.memory[(i*4)+2], D2.memory[(i*4)+3]);
end
end
$display("\n\n");
$display("Passed\t%d/%d test cases", pass, i); //*/
$finish;
end
endmodule
| 6.611668 |
module tb_pipelined_mips_stalling ();
reg clk;
reg nrst;
wire [ `WORD_WIDTH - 1:0] inst; // 32-bit instruction (from instruction memory)
wire [ `WORD_WIDTH - 1:0] proc_data_in; // data from memory to processor
wire [ `WORD_WIDTH - 1:0] proc_data_out; // data from processor to memory
wire data_wr; // data memory write enable
wire [`MEM_ADDR_WIDTH - 1:0] inst_addr; // program counter
wire [`MEM_ADDR_WIDTH - 1:0] data_addr; // data memory address
wire [ 31:0] pc_IF;
wire [ 31:0] pc_ID;
wire [ 31:0] pc_EXE;
wire [ 31:0] pc_MEM;
wire [ 31:0] pc_WB;
// Debug signals
/* wire [31:0] IDec_inst;
wire flush_out;
wire IDec_wr_en;
wire IDec_data_wr;
wire [31:0] WBack_data;
wire [4:0] WBack_addr;*/
pipelined_mips_stalling UUT (
.clk(clk),
.nrst(nrst),
.inst(inst),
.data_in(proc_data_in),
.inst_addr(inst_addr),
.data_addr(data_addr),
.data_out(proc_data_out),
.data_wr(data_wr),
.pc_IF(pc_IF),
.pc_ID(pc_ID),
.pc_EXE(pc_EXE),
.pc_MEM(pc_MEM),
.pc_WB(pc_WB) /*,
// Debug signals
.IDec_inst(IDec_inst),
.flush_out(flush_out),
.IDec_wr_en(IDec_wr_en),
.IDec_data_wr(IDec_data_wr),
.WBack_data(WBack_data),
.WBack_addr(WBack_addr)*/
);
instmem I1 (
.clk(clk),
.inst_addr(inst_addr),
.inst(inst)
);
datamem D1 (
.clk(clk),
.data_addr(data_addr),
.data_wr(data_wr),
.data_in(proc_data_in),
.data_out(proc_data_out)
);
datamem_ans D2 ();
always #(`CLK_PERIOD / 2) clk = ~clk;
integer i;
integer done;
integer check_done;
integer pass;
initial begin
$vcdplusfile("tb_pipelined_mips_stalling.vpd");
$vcdpluson;
$sdf_annotate("../mapped/pipelined_mips_stalling_mapped.sdf", UUT);
clk = 0;
nrst = 0;
done = 0;
check_done = 0;
#(`DEL_IN) nrst = 1;
end
always @(posedge clk) begin
if (inst == 32'h0) check_done = check_done + 1;
end
always @(posedge clk) begin
if (check_done == 10) done = 1;
end
always @(posedge done) begin
pass = 0;
$display("== SUMMARY ==");
$display("Actual \tExpected");
$display("========\t========");
for (i = 0; i < 100; i = i + 1) begin
if(D1.memory[(i*4)]==D2.memory[(i*4)] && D1.memory[(i*4)+1]==D2.memory[(i*4)+1] && D1.memory[(i*4)+2]==D2.memory[(i*4)+2] && D1.memory[(i*4)+3]==D2.memory[(i*4)+3]) begin
$display("%X%X%X%X\t%X%X%X%X\tPass", D1.memory[(i*4)], D1.memory[(i*4)+1],
D1.memory[(i*4)+2], D1.memory[(i*4)+3], D2.memory[(i*4)], D2.memory[(i*4)+1],
D2.memory[(i*4)+2], D2.memory[(i*4)+3]);
pass = pass + 1;
end else begin
$display("%X%X%X%X\t%X%X%X%X\tFail", D1.memory[(i*4)], D1.memory[(i*4)+1],
D1.memory[(i*4)+2], D1.memory[(i*4)+3], D2.memory[(i*4)], D2.memory[(i*4)+1],
D2.memory[(i*4)+2], D2.memory[(i*4)+3]);
end
end
$display("\n\n");
$display("Passed\t%d/%d test cases", pass, i); //*/
$finish;
end
endmodule
| 6.611668 |
module tb_pipeline_insert_ff ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_pipeline_insert_ff.vcd");
$dumpvars(0, tb_pipeline_insert_ff);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
localparam DATA_WIDTH = 16;
wire [DATA_WIDTH-1:0] s_data;
wire s_valid;
wire s_ready;
wire [DATA_WIDTH-1:0] m_data;
wire m_valid;
wire m_ready;
wire buffered;
jelly_pipeline_insert_ff #(
.DATA_WIDTH (DATA_WIDTH),
.SLAVE_REGS (1),
.MASTER_REGS(1)
) i_pipeline_insert_ff (
.reset(reset),
.clk (clk),
.cke (1'b1),
.s_data (s_data),
.s_valid(s_valid),
.s_ready(s_ready),
.m_data (m_data),
.m_valid(m_valid),
.m_ready(m_ready),
.buffered(buffered)
);
// write
reg [DATA_WIDTH-1:0] reg_data;
reg reg_valid;
always @(posedge clk) begin
if (reset) begin
reg_data <= 0;
reg_valid <= 1'b0;
end else begin
if (!(s_valid && !s_ready)) begin
reg_valid <= {$random};
end
if (s_valid && s_ready) begin
reg_data <= reg_data + 1'b1;
end
end
end
assign s_data = reg_data;
assign s_valid = reg_valid;
// read
integer fp;
initial begin
fp = $fopen("log.txt", "w");
end
reg [DATA_WIDTH-1:0] reg_expectation_value;
reg reg_ready;
always @(posedge clk) begin
if (reset) begin
reg_expectation_value <= 0;
reg_ready <= 1'b0;
end else begin
reg_ready <= {$random};
if (m_valid && m_ready) begin
$fdisplay(fp, "%h %h", m_data, reg_expectation_value);
if (m_data != reg_expectation_value) begin
$display("error!");
end
reg_expectation_value <= reg_expectation_value + 1'b1;
end
end
end
assign m_ready = reg_ready;
endmodule
| 7.761626 |
module : tb_pipeline_register
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_pipeline_register();
task print_state;
begin
$display("reset\t:%b", reset);
$display("stall\t:%b", stall);
$display("flush\t:%b", flush);
$display("pipe_input\t:%b", pipe_input);
$display("flush_input\t:%b", flush_input);
$display("pipe_output\t:%b", pipe_output);
$display("i\t:%b", i);
end
endtask
parameter PIPELINE_STAGE = 0;
parameter PIPE_WIDTH = 32;
parameter SCAN_CYCLES_MIN = 1;
parameter SCAN_CYCLES_MAX = 1000;
reg clock;
reg reset;
reg stall;
reg flush;
reg [PIPE_WIDTH-1:0] pipe_input;
reg [PIPE_WIDTH-1:0] flush_input;
wire [PIPE_WIDTH-1:0] pipe_output;
//scan signal
reg scan;
//value generators
integer i;
//instantiate pipeline_register
pipeline_register #(
.PIPELINE_STAGE(PIPELINE_STAGE),
.PIPE_WIDTH(PIPE_WIDTH),
.SCAN_CYCLES_MIN(SCAN_CYCLES_MIN),
.SCAN_CYCLES_MAX(SCAN_CYCLES_MAX)
) DUT (
.clock(clock),
.reset(reset),
.stall(stall),
.flush(flush),
.pipe_input(pipe_input),
.flush_input(flush_input),
.pipe_output(pipe_output),
.scan(scan)
);
// generate clock signal
always #1 clock = ~clock;
always @(posedge clock)begin
if(~reset)begin
pipe_input <= pipe_input + 1;
i <= i + 1;
end
end
initial begin
clock <= 0;
reset <= 1;
stall <= 0;
flush <= 0;
scan <= 0;
i <= 0;
pipe_input <= 1;
flush_input <= 32'h00000013;
repeat(3) @(posedge clock);
@(posedge clock)begin
reset <= 0;
end
repeat(1) @(posedge clock);
if(pipe_output != i)begin
$display("\ntb_pipeline_register --> Test Failed!\n\n");
print_state();
end
repeat(3) @(posedge clock);
@(posedge clock)begin
stall <= 1;
end
@(posedge clock)begin
stall <= 0;
end
@(stall)
if(pipe_output != i-1)begin
$display("\ntb_pipeline_register --> Test Failed!\n\n");
print_state();
end
repeat(1) @(posedge clock);
@(pipe_output)
if(pipe_output != i)begin
$display("\ntb_pipeline_register --> Test Failed!\n\n");
print_state();
end
repeat(3) @(posedge clock);
@(posedge clock)begin
flush <= 1;
end
@(posedge clock)begin
flush <= 0;
end
@(flush)
if(pipe_output != 32'h00000013)begin
$display("\ntb_pipeline_register --> Test Failed!\n\n");
print_state();
end
repeat(1) @(posedge clock);
@(pipe_output)
if(pipe_output != i)begin
$display("\ntb_pipeline_register --> Test Failed!\n\n");
print_state();
end
$display("\ntb_pipeline_register --> Test Passed!\n\n");
$stop;
end
initial begin
#500;
$display("Error: timeout");
$display("\ntb_pipeline_register --> Test Failed!\n\n");
$stop;
end
endmodule
| 7.497975 |
module piso_left_cyclic_Nb_top;
parameter W = 4, SW = 4;
reg RST;
reg CLK;
reg LOAD;
reg LSHIFT;
reg [W-1:0] IN[SW-1:0];
wire [W-1:0] OUT;
integer i = 0;
piso_left_cyclic_Nb #(
.BUS_WIDTH (W),
.SISO_WIDTH(SW)
) piso_l (
.RST(RST),
.CLK(CLK),
.LOAD(LOAD),
.LSHIFT(LSHIFT),
.IN0(IN[0]),
.IN1(IN[1]),
.IN2(IN[2]),
.IN3(IN[3]),
.OUT(OUT)
);
initial begin
RST = 1;
#100 RST = 0;
fork
begin
CLK = 1;
forever begin
#5 CLK = ~CLK;
end
end
begin
@(negedge CLK);
repeat (2) begin
@(posedge CLK);
#1;
for (i = 0; i < SW; i = i + 1) begin
$display("IN[%0d] : %0d", i, IN[i]);
end
$display("LOAD : %0d, LSHIFT : %0d == OUT : %d", LOAD, LSHIFT, OUT);
LSHIFT = 1;
LOAD = 0;
for (i = 0; i < SW; i = i + 1) begin
IN[i] = $urandom;
end
@(negedge CLK);
end
repeat (1) begin
@(posedge CLK);
#1;
for (i = 0; i < SW; i = i + 1) begin
$display("IN[%0d] : %0d", i, IN[i]);
end
$display("LOAD : %0d, LSHIFT : %0d == OUT : %d", LOAD, LSHIFT, OUT);
LSHIFT = 1;
LOAD = 1;
for (i = 0; i < SW; i = i + 1) begin
IN[i] = $urandom;
end
@(negedge CLK);
end
repeat (8) begin
@(posedge CLK);
#1;
for (i = 0; i < SW; i = i + 1) begin
$display("IN[%0d] : %0d", i, IN[i]);
end
$display("LOAD : %0d, LSHIFT : %0d == OUT : %d", LOAD, LSHIFT, OUT);
LSHIFT = 1;
LOAD = 0;
for (i = 0; i < SW; i = i + 1) begin
IN[i] = $urandom;
end
@(negedge CLK);
end
$finish;
end
join
end
endmodule
| 7.03152 |
module tb_piso_macro;
// Inputs
reg clk;
reg rst;
reg load;
reg ce;
reg [`DATA_WIDTH*2-1:0] p_in;
// Outputs
wire s_out;
// Instantiate the Unit Under Test (UUT)
piso_macro uut (
.clk(clk),
.rst(rst),
.load(load),
.ce(ce),
.p_in(p_in),
.s_out(s_out)
);
parameter PERIOD = 20;
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
integer cycle;
initial cycle = 0;
always @(posedge clk) cycle = cycle + 1;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
load = 0;
ce = 0;
p_in = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
#20;
load = 1;
p_in = 32'h0100_0001;
#20;
load = 1;
p_in = 32'h0100_0000;
#20;
load = 1;
p_in = 32'h0100_0001;
#20;
load = 0;
ce = 1;
#640;
#20;
ce = 0;
p_in = 32'd0;
#1000;
end
endmodule
| 7.458659 |
module tb_piso_new;
// Inputs
reg clk;
reg load;
reg p_in_v;
reg [`PE_NUM*`DATA_WIDTH*2-1:0] p_in;
// Outputs
wire s_out_v;
wire [`DATA_WIDTH*2-1:0] s_out;
// Instantiate the Unit Under Test (UUT)
piso_new uut (
.clk(clk),
.load(load),
.p_in_v(p_in_v),
.p_in(p_in),
.s_out_v(s_out_v),
.s_out(s_out)
);
parameter PERIOD = 20;
always begin
clk = 1'b0;
#(PERIOD / 2) clk = 1'b1;
#(PERIOD / 2);
end
integer cycle;
initial cycle = 0;
always @(posedge clk) cycle = cycle + 1;
initial begin
// Initialize Inputs
clk = 0;
load = 0;
p_in_v = 0;
p_in = 32'h0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#20;
p_in_v = 1;
load = 1;
p_in = 128'h00000001_00001000_00010000_01000000;
#20;
p_in_v = 1;
load = 1;
p_in = 128'h00000002_00002000_00020000_02000000;
#20;
p_in_v = 1;
load = 1;
p_in = 128'h00000003_00003000_00030000_03000000;
#20;
p_in_v = 1;
load = 1;
p_in = 128'h00000004_00004000_00040000_04000000;
#20;
p_in_v = 1;
load = 0;
p_in = 128'h00000005_00005000_00050000_05000000;
#20;
p_in_v = 1;
p_in = 128'h00000006_00006000_00060000_06000000;
#20;
p_in_v = 1;
p_in = 128'h00000007_00007000_00070000_07000000;
#20;
p_in_v = 1;
p_in = 128'h00000008_00008000_00080000_08000000;
#20;
p_in_v = 1;
p_in = 128'h00000009_00009000_00090000_09000000;
#20;
p_in_v = 1;
p_in = 128'h0000000a_0000a000_000a0000_0a000000;
#20;
p_in_v = 1;
p_in = 128'h0000000b_0000b000_000b0000_0b000000;
#20;
p_in_v = 1;
p_in = 128'h0000000c_0000c000_000c0000_0c000000;
#20;
p_in_v = 1;
p_in = 128'h0000000d_0000d000_000d0000_0d000000;
#20;
p_in_v = 1;
p_in = 128'h0000000e_0000e000_000e0000_0e000000;
#20;
p_in_v = 1;
p_in = 128'h0000000f_0000f000_000f0000_0f000000;
#20;
p_in_v = 1;
p_in = 128'h00000010_00010000_00100000_10000000;
#20;
p_in_v = 1;
p_in = 128'h00000011_00011000_00110000_11000000;
#20;
p_in_v = 1;
p_in = 128'h00000012_00012000_00120000_12000000;
#20;
p_in_v = 1;
p_in = 128'h00000013_00013000_00130000_13000000;
#20;
p_in_v = 1;
p_in = 128'h00000014_00014000_00140000_14000000;
#20;
p_in_v = 1;
p_in = 128'h00000015_00015000_00150000_15000000;
#20;
p_in_v = 1;
p_in = 128'h00000016_00016000_00160000_16000000;
#20;
p_in_v = 1;
p_in = 128'h00000017_00017000_00170000_17000000;
#20;
p_in_v = 1;
p_in = 128'h00000018_00018000_00180000_18000000;
#20;
p_in_v = 1;
p_in = 128'h00000019_00019000_00190000_19000000;
#20;
p_in_v = 1;
p_in = 128'h0000001a_0001a000_001a0000_1a000000;
#20;
p_in_v = 1;
p_in = 128'h0000001b_0001b000_001b0000_1b000000;
#20;
p_in_v = 1;
p_in = 128'h0000001c_0001c000_001c0000_1c000000;
#20;
p_in_v = 1;
p_in = 128'h0000001d_0001d000_001d0000_1d000000;
#20;
p_in_v = 1;
p_in = 128'h0000001e_0001e000_001e0000_1e000000;
#20;
p_in_v = 1;
p_in = 128'h0000001f_0001f000_001f0000_1f000000;
#20;
p_in_v = 1;
p_in = 128'h00000020_00020000_00200000_20000000;
#20;
p_in_v = 0;
#1000;
end
endmodule
| 7.729949 |
module testbench;
localparam RCLK_PERIOD = 4000;
localparam TCLK_PERIOD = 4000;
localparam RST_TIME = 10000;
reg rx_clk;
reg clk;
always begin
rx_clk = 0;
forever #RCLK_PERIOD rx_clk = ~rx_clk;
end
always begin
clk = 0;
forever #TCLK_PERIOD clk = ~clk;
end
wire tx_clk;
wire [15:0] rand;
assign rand = {$random}%2000;
assign #(rand) tx_clk = clk;
reg rstn;
reg tx_en;
reg tx_type;
reg [15:0] tx_data;
wire rx_data_valid;
wire [23:0] rx_data;
initial begin
rstn = 0;
tx_type = 1;
tx_en = 0;
tx_data = 16'b0;
#RST_TIME
rstn = 1;
//#400000000
//$finish();
end
initial begin
$fsdbDumpfile("test.fsdb");
$fsdbDumpvars;
end
reg [7:0] rand0;
reg [7:0] rand1;
reg rd;
wire tx_done;
always @(*) begin
if (tx_done & !tx_type) begin
rand0 = {$random}%256;
rand1 = {$random}%256;
rd = {$random}%2;
tx_data = rd ? {rand0, rand1} : {6'b0, rand1};
end
end
always @(*) begin
if (tx_done)
tx_en = 0;
else begin
#1000000
tx_en = 1;
tx_type = ~tx_type;
end
end
always @(*) begin
if (rx_data_valid && tx_data!=rx_data[15:0]) begin
$display($time, "Error!");
$finish();
end
end
reg [31:0] cnt;
always @(posedge tx_clk or negedge rstn) begin
if (!rstn)
cnt <= 0;
else if (tx_done)
cnt <= cnt +1;
end
always @(*) begin
if (cnt == 1000)
$finish();
else if (cnt%100 == 0)
$display("Processing cnt: %d", cnt);
end
wire data;
fcp_tx_ctrl U_TX_CTRL (
.clk (tx_clk)
,.rstn (rstn)
,.tx_en (tx_en)
,.tx_type (tx_type)
,.tx_data (tx_data)
,.data (data)
,.tx_done (tx_done)
);
fcp_rx_ctrl U_RX_CTRL (
.clk (rx_clk)
,.rstn (rstn)
,.data (data)
,.rx_own_bus (1'b1)
,.ping_from_master ()
,.reset_from_master ()
,.rx_data (rx_data)
,.rx_data_valid (rx_data_valid)
);
endmodule
| 7.956616 |
module tb_pla;
reg clk;
reg rst_n;
reg [2:0] P;
reg [15:0] ADDR;
reg [14:0] VADDR;
reg AEC;
reg BA;
reg GAME_n;
reg EXTROM_n;
reg RW;
integer i;
integer j;
pla pla_e (
.A(ADDR),
._LORAM(P[0]),
._HIRAM(P[1]),
._CHAREN(P[2]),
._CAS(1'b0),
.VA12(VADDR[12]),
.VA13(VADDR[13]),
._VA14(!VADDR[14]),
._AEC(AEC),
.BA(BA),
._GAME(GAME_n),
._EXROM(EXTROM_n),
.R__W(!RW)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_pla.vcd");
$dumpvars(0, tb_pla);
end
initial begin
P <= 0;
VADDR <= 0;
ADDR <= 0;
AEC <= 0;
BA <= 0;
GAME_n <= 1;
EXTROM_n <= 1;
RW <= 0;
#1 rst_n <= 1'bx;
clk <= 1'bx;
#(CLK_PERIOD * 3) rst_n <= 1;
#(CLK_PERIOD * 3) rst_n <= 0;
clk <= 0;
repeat (5) @(posedge clk);
rst_n <= 1;
@(posedge clk);
repeat (2) @(posedge clk);
for (i = 0; i < 7; i = i + 1) begin
P <= i;
for (j = 0; j < 16; j = j + 1) begin
ADDR <= j << 12;
repeat (2) @(posedge clk);
end
end
$finish(2);
end
endmodule
| 6.542614 |
module: pLayer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_pLayer;
// Inputs
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
// Outputs
wire [263:0] state_out;
wire out_rdy;
// Instantiate the Unit Under Test (UUT)
pLayer uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.out_rdy(out_rdy)
);
//integer i;
initial begin
// Initialize Inputs
state_in = 0;
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
$display("[INITIALIZING]");
en = 1;
state_in = 264'h20d6d3dcd9d5d8dad7dfd4d1d2d0dbdddee6e3ece9e5e8eae7efe4e1e2e0ebed94;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
rst = 1; en = 0;
#5;
en = 1; rst = 0;
state_in = 264'ha8365886353658867333568863335688ca2ed1e22f3856833e55353353dd2d22a5;
$display("state in: %h", state_in);
repeat (66)
#5;
if (out_rdy) begin
$display("state out: %h", state_out);
end
end
always begin
#5; clk = !clk;
end
endmodule
| 6.661257 |
module: pLayer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_pLayer2;
// Inputs
reg [263:0] state_in;
reg [31:0] index;
reg clk;
reg rst;
reg enable;
// Outputs
wire [263:0] state_out;
wire output_rdy;
reg [7:0] state [0:32];
// Instantiate the Unit Under Test (UUT)
pLayer uut (
.state_in(state_in),
.state_out(state_out),
.index(index),
.clk(clk),
.rst(rst),
.enable(enable),
.output_rdy(output_rdy)
);
reg [263:0] temp_state_in;
integer i;
initial begin
// Initialize Inputs
state_in = 0;
index = 0;
clk = 0;
rst = 0;
enable = 0;
for (i=0; i<`nSBox; i=i+1) begin
state [i] = i;
end
for (i=0; i < `nSBox ; i = i+1) begin
temp_state_in[((`nSBox-1)*8)-(8*i) +: 8] = i;
end
$display("input state: %h", state);
// Wait 100 ns for global reset to finish
#100;
enable = 1;
state_in = temp_state_in;
$display("out: %h", state_out);
#5;
$display("out: %h", state_out);
#5;
$display("out: %h", state_out);
// Add stimulus here
end
always begin
#5; clk = !clk;
end
endmodule
| 6.661257 |
module top ();
localparam ITERATIONS = 100000;
reg clk;
reg reset;
always #`CLK_P clk <= ~clk;
wire [15:0] random;
rng RNG (
.clk (clk),
.reset(reset),
.rng_o(random)
);
////////////////////////////////////////////////////////////////////////////////
// DUTs
reg [15+1:0] a_data;
reg a_valid;
reg [15+1:0] b_data;
wire b_stall;
wire b_valid;
wire b_change;
reg [15+1:0] c_data;
reg [3:0] cssd;
wire c_stall;
wire c_valid;
wire c_change;
wire c_self_stall = (c_data[2] && c_data[11] && c_data[15] && c_data[6]) && (cssd < 5);
reg [15+1:0] d_data;
wire d_stall;
wire d_valid;
wire d_change;
wire end_stall = random[1] && random[3] && (random[4] ^ random[13]);
reg [23:0] i;
reg [23:0] j;
reg [15+1:0] values[ITERATIONS:0];
reg done;
wire [15:0] new_data = random;
wire can_launch;
wire new_value_ready;
wire last;
assign can_launch = !a_valid || (a_valid && !b_stall);
assign new_value_ready = (random[3:0] != 3) && (i < ITERATIONS);
assign last = (i == (ITERATIONS - 1));
// First PL stage generally produces, but now and then stalls (emits valid=0)
always @(posedge clk) begin
if (reset) begin
a_valid <= 0;
a_data <= 0;
b_data <= 0;
c_data <= 0;
d_data <= 0;
cssd <= 0;
i <= 0;
j <= 0;
done <= 0;
end else if (can_launch) begin
if (new_value_ready) begin
a_valid <= 1;
$display("In: Write %x at %d", new_data, i);
values[i] <= {last, new_data};
a_data <= {last, new_data};
i <= i + 1;
end else begin
a_valid <= 0;
end
end
// The pipeline:
if (b_change) b_data <= a_data;
if (c_change) c_data <= b_data;
if (c_self_stall) cssd <= cssd + 1;
else cssd <= 0;
if (d_change) d_data <= c_data;
// The end:
//
if (d_valid && !end_stall) begin
if (d_data[15:0] != values[j][15:0]) begin
$fatal(1, "FAIL: Mismatch at idx %d: %x, should be %x", j, d_data[15:0], values[j][15:0]);
end else begin
$display("\tOut: Read %x from %d", values[j][15:0], j);
end
j <= j + 1;
if (d_data[16]) begin
done <= 1;
end
end
end
plc PLCB (
.clk (clk),
.reset(reset),
/* To/from previous stage */
.valid_in (a_valid),
.stall_out(b_stall),
.self_stall(0),
/* To/from next stage */
.valid_out(b_valid),
.stall_in (c_stall),
.annul_in (0),
.enable_change(b_change)
);
plc PLCC (
.clk (clk),
.reset(reset),
/* To/from previous stage */
.valid_in (b_valid),
.stall_out(c_stall),
.self_stall(c_self_stall),
/* To/from next stage */
.valid_out(c_valid),
.stall_in (d_stall),
.annul_in (0),
.enable_change(c_change)
);
plc PLCD (
.clk (clk),
.reset(reset),
/* To/from previous stage */
.valid_in (c_valid),
.stall_out(d_stall),
.self_stall(0),
/* To/from next stage */
.valid_out(d_valid),
.stall_in (end_stall),
.annul_in (0),
.enable_change(d_change)
);
////////////////////////////////////////////////////////////////////////////////
initial begin
$dumpfile("tb_plc.vcd");
$dumpvars(0, top);
clk <= 0;
reset <= 1;
#`CLK;
reset <= 0;
//////////////////////////////////////////////////////////////////////
//#(`CLK*2000);
@(posedge done);
$display("PASS");
$finish(0);
end
endmodule
| 7.239517 |
module tb_pll ();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire clk_mul_2;
wire clk_div_2;
wire clk_phase_90;
wire clk_ducle_20;
wire locked;
//reg define
reg sys_clk;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化系统时钟
initial sys_clk = 1'b1;
//sys_clk:模拟系统时钟，每10ns电平翻转一次，周期为20ns，频率为50Mhz
always #10 sys_clk = ~sys_clk;
//********************************************************************//
//*************************** Instantiation **************************//
//********************************************************************//
//------------------------pll_inst------------------------
pll pll_inst (
.sys_clk(sys_clk), //input sys_clk
.clk_mul_2 (clk_mul_2), //output clk_mul_2
.clk_div_2 (clk_div_2), //output clk_div_2
.clk_phase_90(clk_phase_90), //output clk_phase_90
.clk_ducle_20(clk_ducle_20), //output clk_ducle_20
.locked (locked) //output locked
);
endmodule
| 7.447949 |
module DFIFO #(
parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32
) // fifo width in bit
(
input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [ FIFO_SIZE:0] cnt
);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem[(1<<FIFO_SIZE)-1:0];
assign emp = (cnt == 0);
assign full = (cnt == (1 << FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({
enq, deq
})
2'b01: begin
head <= head + 1;
cnt <= cnt - 1;
end
2'b10: begin
mem[tail] <= din;
tail <= tail + 1;
cnt <= cnt + 1;
end
2'b11: begin
mem[tail] <= din;
head <= head + 1;
tail <= tail + 1;
end
endcase
end
end
endmodule
| 7.141186 |
module tb_pooling;
parameter N = 512;
parameter P = N * N;
parameter L = P * 3;
parameter N2 = N / 2;
parameter P2 = N2 * N2;
parameter L2 = P2 * 3;
integer input_file, output_file;
integer i, j, c;
integer status;
integer count;
reg [7:0] tmp;
reg [3:0] din[0:L-1];
reg [3:0] dout[0:L-1];
reg [3:0] in1, in2, in3, in4;
wire [3:0] out;
second_largest dut (
.in1(in1),
.in2(in2),
.in3(in3),
.in4(in4),
.out(out)
);
initial begin
input_file = $fopen("royce.bin", "rb");
for (i = 0; i < L; i = i + 2) begin
status = $fread(tmp, input_file);
din[i] = tmp[7:4];
din[i+1] = tmp[3:0];
end
$fclose(input_file);
count = 0;
for (c = 0; c < 3; c = c + 1) begin
for (i = 0; i < N2; i = i + 1) begin
for (j = 0; j < N2; j = j + 1) begin
in1 = din[c*P+(2*i+0)*N+(2*j+0)];
in2 = din[c*P+(2*i+0)*N+(2*j+1)];
in3 = din[c*P+(2*i+1)*N+(2*j+0)];
in4 = din[c*P+(2*i+1)*N+(2*j+1)];
#1 dout[c*P2+i*N2+j] = out;
if (count % 1024 == 0) begin
$display("%0d/%0d", count, L2);
end
count = count + 1;
end
end
end
output_file = $fopen("filtered.bin", "wb");
for (i = 0; i < L2; i = i + 2) begin
$fwrite(output_file, "%c", {dout[i], dout[i+1]});
end
$fclose(output_file);
end
endmodule
| 6.737786 |
module tb_pos_level_latch;
// Inputs
reg clk, din;
// Outputs
wire dout;
// Instantiate the Unit Under Test (UUT)
pos_level_latch uut (
.dout(dout),
.clk (clk),
.din (din)
);
initial begin
$dumpfile("tb_pos_level_latch.vcd");
$dumpvars(0, tb_pos_level_latch);
// Initialize Inputs
din = 0;
clk = 0;
#50 $finish;
end
always #2 clk = ~clk;
always #1 din = $random;
endmodule
| 7.414157 |
module tb_ppfifo ();
//local parameters
localparam DATA_WIDTH = 32; //32-bit data
localparam ADDR_WIDTH = 4; //2 ** 4 = 16 positions
//registes/wires
reg clk = 0;
reg rd_clk = 0;
reg rst = 0;
//write side
wire [ 1:0] write_ready;
wire [ 1:0] write_activate;
wire [ 23:0] write_fifo_size;
wire write_strobe;
wire [DATA_WIDTH - 1:0] write_data;
wire starved;
//read side
wire read_strobe;
wire read_ready;
wire read_activate;
wire [ 23:0] read_count;
wire [DATA_WIDTH - 1:0] read_data;
wire inactive;
//submodules
//Write Side
ppfifo_source #(
.DATA_WIDTH(DATA_WIDTH)
) source (
.clk (clk),
.rst (rst),
.i_enable(1'b1),
//Ping Pong FIFO Interface
.i_wr_rdy (write_ready),
.o_wr_act (write_activate),
.i_wr_size(write_fifo_size),
.o_wr_stb (write_strobe),
.o_wr_data(write_data)
);
//PPFIFO
ppfifo #(
.DATA_WIDTH (DATA_WIDTH),
.ADDRESS_WIDTH(ADDR_WIDTH)
) f (
//universal input
.reset(rst),
//write side
.write_clock (clk),
.write_ready (write_ready),
.write_activate (write_activate),
.write_fifo_size(write_fifo_size),
.write_strobe (write_strobe),
.write_data (write_data),
.starved (starved),
//read side
.read_clock (rd_clk),
.read_strobe (read_strobe),
.read_ready (read_ready),
.read_activate(read_activate),
.read_count (read_count),
.read_data (read_data),
.inactive(inactive)
);
//Read Side
ppfifo_sink #(
.DATA_WIDTH(DATA_WIDTH)
) sink (
.clk(rd_clk),
.rst(rst),
//Ping Pong FIFO Interface
.i_rd_rdy (read_ready),
.o_rd_act (read_activate),
.i_rd_size(read_count),
.o_rd_stb (read_strobe),
.i_rd_data(read_data)
);
//asynchronous logic
//synchronous logic
always #`CLK_HALF_PERIOD clk = ~clk;
always #`RD_CLK_HALF_PERIOD rd_clk = ~rd_clk;
initial begin
$dumpfile("design.vcd");
$dumpvars(0, tb_ppfifo);
rst <= 0;
`SLEEP_CLK(10);
rst <= 1;
`SLEEP_CLK(10);
rst <= 0;
end
endmodule
| 7.567386 |
module tb_pram_adr_cnt ();
parameter data_wl = 16;
parameter adr_wl = 12;
reg [adr_wl - 1 : 0] adr_in;
reg adr_ld_in;
reg inc_in;
reg init_mode_in;
reg init_ack_in;
wire [data_wl - 1 : 0] data_in1;
wire [data_wl - 1 : 0] data_in2;
reg clk;
reg a_reset_l;
wire [adr_wl - 1 : 0] adr_out;
wire we_out, start_out;
wire ovr_out;
pram_adr_cnt pram_adr_cnt_i (
.adr_in(adr_in),
.adr_ld_in(adr_ld_in),
.inc_in(inc_in),
.init_mode_in(init_mode_in),
.init_ack_in(init_ack_in),
.data_in1(data_in1),
.data_in2(data_in2),
.clk(clk),
.a_reset_l(a_reset_l),
.adr_out(adr_out),
.we_out(we_out),
.start_out(start_out),
.ovr_out(ovr_out)
);
pram #(
.INITFILE("./mem.txt")
) pram_i (
.data_in(data_in1),
.adr_in(adr_out),
.cs(1'b1),
.we(we_out),
.clk(clk),
.data_out(data_in2)
);
///////////////////////////////////////////////
//// Template for clk and reset generation ////
//// uncomment it when needed ////
///////////////////////////////////////////////
parameter CLKPERIODE = 100;
initial clk = 1'b1;
always #(CLKPERIODE / 2) clk = !clk;
initial begin
a_reset_l = 1'b0;
#33 a_reset_l = 1'b1;
end
///////////////////////////////////////////////
// Template for testcase specific pattern generation
// File has to be situated in simulation/<simulator_name>/[testcase] directory
`include "testcase.v"
endmodule
| 7.319754 |
module tb ();
reg clk, reset;
wire [28:0] pi_out;
real pi_real;
initial begin
reset = 1'b0;
clk = 1'b0;
#10 reset = 1'b1;
#10 reset = 1'b0;
while (1) #10 clk = ~clk;
end
initial begin
$dumpfile("new.vcd");
$dumpvars();
#10000000 $display("pi = %f", pi_real);
$finish();
end
calc_pi _i_calc_pi (
.clk (clk),
.rst (reset),
.pi_out(pi_out)
);
always @(*) begin
pi_real = ($itor(pi_out)) / (2 ** 23);
end
endmodule
| 7.195167 |
module tb_preescaller ();
reg clock;
reg enable;
wire slow_clock;
always #1 clock = ~clock;
preescaller tb_preescaller_DUT (
.clock(clock),
.enable(enable),
.slow_clock(slow_clock)
);
initial begin
clock = 0;
enable = 1;
#100 $display("Simulation for Preescaller Finished");
$stop;
end
endmodule
| 7.595127 |
module tb_prefix;
reg [7:0] t_a, t_b;
reg t_cin;
wire [7:0] t_S;
initial begin
$dumpfile("dump.vcd");
$dumpvars(0, tb_prefix);
end
prefixAdd pra (
.a (t_a),
.b (t_b),
.cin(t_cin),
.S (t_S)
);
initial begin
t_a[7:0] = 8'b00000000; //0
t_b[7:0] = 8'b01000001; //65
t_cin = 1'b0;
#5 t_a[7:0] = 8'b01100100; //100
t_b[7:0] = 8'b00011000; //24
t_cin = 1'b0;
#5 t_a[7:0] = 8'b00010100; //20
t_b[7:0] = 8'b10110010; //178
t_cin = 1'b0;
#5 t_a[7:0] = 8'b00100001; //33
t_b[7:0] = 8'b00111111; //63
t_cin = 1'b0;
#5 t_a[7:0] = 8'b01100100; //100
t_b[7:0] = 8'b00110010; //50
t_cin = 1'b0;
#5 t_a[7:0] = 8'b01100100; //100
t_b[7:0] = 8'b00101000; //40
t_cin = 1'b0;
#5 t_a[7:0] = 8'b10110001; //177
t_b[7:0] = 8'b00110110; //54
t_cin = 1'b0;
#5 t_a[7:0] = 8'b01011010; //90
t_b[7:0] = 8'b00111100; //60
t_cin = 1'b0;
#5 t_a[7:0] = 8'b00011000; //24
t_b[7:0] = 8'b01001100; //76
t_cin = 1'b0;
#10 t_a[7:0] = 8'b00000000;
t_b[7:0] = 8'b00000001;
t_cin = 1'b0;
end
endmodule
| 6.766041 |
module: PrimeDetector
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tb_PrimeDetector;
// Inputs
reg [3:0] N;
//Outputs
wire F;
// Instantiate the Unit Under Test (UUT)
PrimeDetector uut (
.N(N),
.F(F)
);
initial begin
// Initialize Inputs
N = 0; #10;
N = 1; #10;
N = 2; #10;
N = 3; #10;
N = 4; #10;
N = 5; #10;
N = 6; #10;
N = 7; #10;
N = 8; #10;
N = 9; #10;
N = 10; #10;
N = 11; #10;
N = 12; #10;
N = 13; #10;
N = 14; #10;
N = 15; #10;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 6.844203 |
module tb_toplevel_primerLoopback;
localparam NMODULES = 2;
localparam LEN_DATA_BLOCK = 64;
localparam LEN_CTRL_BLOCK = 8;
reg tb_clock, tb_reset, tb_enable_frameGenerator, tb_enable_frameChecker;
reg [NMODULES-1 : 0] tb_enable_tx, tb_enable_rx;
wire [LEN_DATA_BLOCK-1 : 0] tb_data_out;
wire [LEN_CTRL_BLOCK-1 : 0] tb_ctrl_out;
initial begin
tb_clock = 0;
tb_reset = 0;
tb_enable_frameGenerator = 1'b0;
tb_enable_frameChecker = 1'b0;
tb_enable_tx = 2'b00;
tb_enable_rx = 2'b00;
#2 tb_reset = 1;
#2 tb_reset = 0;
tb_enable_frameGenerator = 1'b1;
tb_enable_tx = 2'b11;
tb_enable_rx = 2'b11;
#20 tb_enable_frameChecker = 1'b1;
#10000000 $finish;
end
always #1 tb_clock = ~tb_clock;
toplevel_primerLoopback #() u_toplevel_primerLoopback (
.i_clock(tb_clock),
.i_reset(tb_reset),
.i_enable_frameGenerator(tb_enable_frameGenerator),
.i_enable_frameChecker(tb_enable_frameChecker),
.i_enable_tx(tb_enable_tx),
.i_enable_rx(tb_enable_rx),
.o_rx_raw_data(tb_data_out),
.o_rx_raw_ctrl(tb_ctrl_out)
);
endmodule
| 7.119476 |
module tb_proc ();
reg clk, rst, interrupt;
main A (
clk,
rst,
interrupt
);
always #5 clk = ~clk;
initial begin
$monitor($time, " r0=%d, r1=%d, r3=%d r4=%d mem16=%d mem17=%d", A.regs.reg_num[0],
A.regs.reg_num[1], A.regs.reg_num[3], A.regs.reg_num[4], A.D_mem.d_mem[16],
A.D_mem.d_mem[17]);
rst = 1'b1;
clk = 1'b0;
interrupt = 1'b0;
#1 rst = 1'b0;
repeat (10) @(negedge clk);
$finish;
end
initial begin
$dumpfile("proc.vcd");
$dumpvars(0, tb_proc);
end
endmodule
| 6.732844 |
module: Procesador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_Procesador;
// Inputs
reg clk;
reg [7:0] sw;
// Outputs
wire [7:0] leds;
// Instantiate the Unit Under Test (UUT)
Procesador uut (
.clk(clk),
.sw(sw),
.leds(leds)
);
always #50 clk = !clk;
initial begin
// Initialize Inputs
clk = 1;
sw = 8'b00000100;
// Wait 100 ns for global reset to finish
#10;
// Add stimulus here
end
endmodule
| 7.091721 |
module tb_processor ();
// inputs
reg clk;
reg rst;
// outputs
wire [31:0] tb_Result;
processor processor_isnt (
.clk(clk),
.reset(rst),
.Result(tb_Result)
);
always begin
#10;
clk = ~clk;
end
initial begin
clk = 0;
@(posedge clk);
rst = 1;
@(posedge clk);
rst = 0;
end
integer point = 0;
always @(*) begin
#20;
if (tb_Result == 32'h00000000) // and
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000001) // addi
begin
point = point + 1;
end
#20
if (tb_Result == 32'h00000002) // addi
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000004) // addi
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000005) // addi
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000007) // addi
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000008) // addi
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h0000000b) // addi
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000003) // add
begin
point = point + 1;
end
#20;
if (tb_Result == 32'hfffffffe) // sub
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000000) // add
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000005) // or
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000001) // SLT
begin
point = point + 1;
end
#20;
if (tb_Result == 32'hfffffff4) // NOR
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h000004D2) // andi
begin
point = point + 1;
end
#20;
if (tb_Result == 32'hfffff8D7) // ori
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000001) // SLT
begin
point = point + 1;
end
#20;
if (tb_Result == 32'hfffffb2c) // nori
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000030) // sw
begin
point = point + 1;
end
#20;
if (tb_Result == 32'h00000030) // lw
begin
point = point + 1;
end
$display("%s%d", "The number of correct test caese is:", point);
end
initial begin
#430;
$finish;
end
endmodule
| 6.782286 |
module uartprog #(
parameter FILENAME = "program.hex"
) (
input mprj_ready,
output reg r_Rx_Serial // used by task UART_WRITE_BYTE
);
reg r_Clock = 0;
parameter c_BIT_PERIOD = 8681; // used by task UART_WRITE_BYTE
parameter c_CLOCK_PERIOD_NS = 100;
reg [7:0] INSTR[16384-1:0];
integer instr_count = 0;
reg ready;
reg test;
always @(posedge r_Clock) begin
if (mprj_ready) begin
ready <= 1'b1;
end else begin
ready <= 1'b0;
end
end
initial begin
$readmemh(FILENAME, INSTR);
end
task UART_WRITE_BYTE;
input [7:0] i_Data;
integer ii;
begin
// Send Start Bit
r_Rx_Serial <= 1'b0;
#(c_BIT_PERIOD);
#1000;
// Send Data Byte
for (ii = 0; ii < 8; ii = ii + 1) begin
r_Rx_Serial <= i_Data[ii];
#(c_BIT_PERIOD);
end
// Send Stop Bit
r_Rx_Serial <= 1'b1;
#(c_BIT_PERIOD);
end
endtask // UART_WRITE_BYTE
initial begin
test = 1'b0;
#1000 test = 1'b1;
end
always #(c_CLOCK_PERIOD_NS / 2) r_Clock <= !r_Clock;
initial begin
r_Rx_Serial <= 1'b1;
#2000;
while (!ready && test) begin
@(posedge r_Clock) r_Rx_Serial <= 1'b1;
end
while ((instr_count < 16384) && ({INSTR[instr_count],INSTR[instr_count+1],INSTR[instr_count+2],INSTR[instr_count+3]} != 32'h00000FFF)) begin
@(posedge r_Clock);
UART_WRITE_BYTE(INSTR[instr_count][7:0]);
@(posedge r_Clock);
UART_WRITE_BYTE(INSTR[instr_count+1][7:0]);
@(posedge r_Clock);
UART_WRITE_BYTE(INSTR[instr_count+2][7:0]);
@(posedge r_Clock);
UART_WRITE_BYTE(INSTR[instr_count+3][7:0]);
@(posedge r_Clock);
instr_count = instr_count + 32'd4;
end
@(posedge r_Clock);
UART_WRITE_BYTE(8'h00);
@(posedge r_Clock);
UART_WRITE_BYTE(8'h00);
@(posedge r_Clock);
UART_WRITE_BYTE(8'h0F);
@(posedge r_Clock);
UART_WRITE_BYTE(8'hFF);
@(posedge r_Clock);
end
endmodule
| 6.509248 |
module tb_ps2_state_controller ();
reg clk;
reg data;
reg parity_valid;
wire shift_en;
wire write_en;
wire reset;
wire frame_valid;
PS2InterfaceStateController control (
.clk(clk),
.data(data),
.parity_valid(parity_valid),
.shift_en(shift_en),
.write_en(write_en),
.reset(reset),
.frame_valid(frame_valid)
);
initial begin
clk = 1;
data = 1;
parity_valid = 0;
#10 data = 0; //start bit
#10 data = 1; //d0
#10 data = 1; //d1
#10 data = 0; //d2
#10 data = 1; //d3
#10 data = 0; //d4
#10 data = 0; //d5
#10 data = 0; //d6
#10 data = 1; //d7
#10 data = 0; //parity. don't care since we're generating our own parity
#10 parity_valid = 1;
data = 1; //stop bit
#50 data = 0; //start bit
#10 data = 1;
end
always begin
#5 clk = ~clk;
end
endmodule
| 6.647612 |
module pulse_tb ();
// Signal Declarations
reg clock, reset, enable; // Inputs
reg [5:0] divideby;
wire go; // Outputs
wire [9:0] LEDR;
//wire [5:0] count;
// Unit Under Test Instantiation
pulse UUT (
.clock(clock),
.reset(reset),
.enable(enable),
.divideby(divideby),
.go(go),
.LEDR(LEDR)
);
initial begin
clock = 1'b0;
#1000000
// Automatically stop testbench execution
$stop;
end
always begin
#100 clock = ~clock;
end
initial begin
$display("Testing divideby = 2");
enable = 1'b0;
divideby = 6'b000_010;
reset = 1'b0;
#500 @(posedge clock);
#10;
enable = 1'b1;
reset = 1'b1;
@(posedge clock);
#10;
reset = 1'b0;
repeat (10) begin
@(posedge clock);
#10;
//$display("count = %6b", count);
end
$display("Testing divideby = 3");
divideby = 6'b000_011;
#500 @(posedge clock);
#10;
enable = 1'b1;
reset = 1'b1;
@(posedge clock);
#10;
reset = 1'b0;
repeat (20) begin
@(posedge clock);
#10;
//$display("count = %6b", count);
end
// Automatically stop testbench execution
$stop;
end
endmodule
| 8.562464 |
module tb_pulse_sync_toggle ();
reg clock_a;
reg clock_b;
reg async_rst_n;
reg pls_a;
wire pls_b;
pulse_sync_toggle pulse_sync_toggle_i (
.clock_a (clock_a),
.clock_b (clock_b),
.async_rst_n(async_rst_n),
.pls_a (pls_a),
.pls_b (pls_b)
);
always begin
#5 clock_a = ~clock_a;
end
always begin
#3.33 clock_b = ~clock_b;
end
initial begin
clock_a = 1'b0;
clock_b = 1'b0;
pls_a = 1'b0;
async_rst_n = 1'b0;
#10;
async_rst_n = 1'b1;
pls_a = 1'b0;
#45;
pls_a = 1'b1;
#10;
pls_a = 1'b0;
#245;
pls_a = 1'b1;
#10;
pls_a = 1'b0;
#2000;
$finish();
end
endmodule
| 7.151773 |
module tb_pwm;
// Parameters
parameter CLOCK_PERIOD = 10; // Clock period in ns
parameter SIM_DURATION = 1000; // Simulation duration in ns
// Inputs
reg clk;
reg rst;
reg [6:0] duty_cycle; // Using 7 bits to represent duty cycle from 0 to 100 (0 to 100%)
reg [15:0] frequency; // Using 16 bits to represent frequency (in Hz)
// Outputs
wire pwm_out;
// Instantiate the PWM Generator
pwm_top pwm_gen (
.clk(clk),
.rst(rst),
.duty_cycle(duty_cycle),
.frequency(frequency),
.pwm_out(pwm_out)
);
// Clock generation (50% duty cycle)
always begin
#(CLOCK_PERIOD / 2) clk = ~clk;
end
// Initial values
initial begin
// Case 1
clk = 0;
rst = 1;
duty_cycle = 25; // 25% duty cycle
frequency = 2000; // 2 kHz frequency
#20 rst = 0; // Release reset after 20 ns
#50;
// Case 2
rst = 1;
#5;
duty_cycle = 65; // 25% duty cycle
frequency = 2000; // 2 kHz frequency
#20 rst = 0; // Release reset after 20 ns
// Case 3
rst = 1;
#5;
duty_cycle = 100; // 25% duty cycle
frequency = 2000; // 2 kHz frequency
#20 rst = 0; // Release reset after 20 ns
end
// Monitor statements
initial
@(posedge clk) begin
$display("time\tclk\trst\tPWM");
$monitor("[@%0t]", $time, "\t", clk, "\t", rst, "\t", pwm_out);
// $monitor("[@%0t]", $time,"\t", clk,"\t", rst,"\t", pwm_out,"\t", duty_cycle, "\t", frequency);
end
initial begin
$dumpfile("tb_pwm.vcd");
#300;
$finish;
$dumpvars(0, tb_pwm);
end
endmodule
| 7.083046 |
module tb_PWM_Generator_Verilog;
// Inputs
reg clk;
reg reset;
// Outputs
wire [35:0] PWM_OUT;
// Instantiate the PWM Generator with variable duty cycle in Verilog
robot_arm_controller PWM_Generator_Unit (
clk,
reset,
PWM_OUT
);
//
initial begin
clk = 0;
forever #100 clk = ~clk;
end
initial begin
#50 reset = 1;
#50 reset = 0;
end
endmodule
| 6.704379 |
module tb_decade_counter ();
wire [3:0] q;
reg clk = 0;
integer i;
decade_counter UUT (
q,
clk
);
initial begin
for (i = 0; i < 100; i = i + 1) #10;
end
always @(i) clk = ~clk;
initial begin
#7;
$monitor("%d", q);
end
endmodule
| 6.875652 |
module: random
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_QAM;
// Inputs
reg clk;
reg rst;
// Outputs
//wire [27:0] shift_reg;
//System Freqency
wire en_clk;
main_cntr
#(.freq_prescale(0))
main_cntr_(
.clk(clk),
.rst(rst),
.en_clk(en_clk)
);
wire adat_be_S;
wire data_change;
wire data_ready;
Adat_Gen Adat (
.clock(clk),
.reset(rst),
.adat_ki(adat_be_S),
.data_change(data_change),
.enable_cntr(en_clk),
.data_ready(data_ready)
);
wire [1:0]elojel_sin_cos;
wire [1:0]parallel_reg;
wire data_change_cntr;
S2P sor2par(
.clock(clk),
.reset(rst),
.adat_be_S(adat_be_S),
.data_change,
.elojel_sin_cos(elojel_sin_cos),
.parallel_reg(parallel_reg),
.data_change_cntr(data_change_cntr)
);
initial begin
// Initialize Inputs
clk = 0;
rst=1;
// Wait 100 ns for global reset to finish
#100;
rst=0;
// Add stimulus here
end
always #5 clk= ~clk;
endmodule
| 7.080575 |
module clk_wiz_0 (
input clk48,
output clk20,
input reset,
output locked
);
// just reflect the input to the output and set the input to be 20MHz in the testbench
assign clk20 = clk48;
assign locked = 1;
endmodule
| 6.750754 |
module tb_qupdater;
reg [15:0] old_Q;
reg [15:0] max_Q;
reg [ 3:0] gamma;
reg [15:0] rt;
reg [ 3:0] alpha;
wire [15:0] new_Q;
QUpdater q_updater (
old_Q,
max_Q,
gamma,
alpha,
rt,
new_Q
);
initial begin
old_Q = 16'b0000000000000001;
max_Q = 16'b0000000000000011;
gamma = 4'b0001;
alpha = 4'b0001;
rt = 16'b0000000000000111;
#10;
$stop;
end
endmodule
| 7.710726 |
module tb_Q_column3_pre;
reg enable, clk, reset_n, accept_in;
wire accept_out, ready_out;
//
reg [63:0] H_col3, Q_col1, Q_col2;
wire [63:0] Q_col3_pre;
Q_column3_pre uut (
enable,
clk,
reset_n,
accept_in,
accept_out,
ready_out,
H_col3,
Q_col1,
Q_col2,
Q_col3_pre
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset_n = 0;
@(negedge clk);
reset_n = 1;
end
initial begin
enable = 1;
accept_in = 1;
end
reg [63:0] in[0 : 1];
initial begin
in[0] = 64'b0000110011001100000010011001100100000110011001100000100110011001;
in[1] = 64'b0000100110011001000100110011001100001001100110010000110000101000;
end
reg i;
initial i = 0;
always @(accept_out) begin
if (accept_out) begin
Q_col1 = in[i];
Q_col2 = in[i];
H_col3 = in[i];
i = i + 1;
end
end
endmodule
| 6.842615 |
module R5FP_sqrt_seq_wrap #(
parameter EXP_W = 5,
parameter SIG_W = 6
) (
input [EXP_W+SIG_W:0] a,
input [2:0] rnd,
output [7:0] status,
output [EXP_W+SIG_W:0] z,
input clk,
reset,
strobe,
output ready,
complete
);
wire [EXP_W+SIG_W+1:0] ax, zx;
R5FP_exp_incr #(
.SIG_W(SIG_W),
.EXP_W(EXP_W)
) a_i (
.a(a),
.z(ax)
);
R5FP_sqrt_seq #(
.SIG_W(SIG_W),
.EXP_W(EXP_W + 1)
) sqrt (
.a_in(ax),
.rnd_in(rnd),
.clk(clk),
.reset(reset),
.strobe(strobe),
.complete(complete),
.ready(ready),
.z(zx),
.status(status)
);
R5FP_exp_decr #(
.SIG_W(SIG_W),
.EXP_W(EXP_W)
) z_d (
.a(zx),
.z(z)
);
endmodule
| 6.507974 |
module tb_ram;
parameter ADDR_WIDTH = 6;
parameter DATA_WIDTH = 8;
reg [DATA_WIDTH-1:0] data;
reg [ADDR_WIDTH-1:0] addr;
reg we, clk;
wire [DATA_WIDTH-1:0] q;
// duration for each bit = 20 * timescale = 20 * 1 ns = 20ns
localparam period = 20;
ram UUT (
.clk(clk),
.we(we),
.addr(addr),
.data(data),
.q(q)
);
initial // Clock generation
begin
clk = 0;
forever begin
#(period / 2);
clk = ~clk;
end
end
initial begin
// write to ram[0]
data = 8'hab;
addr = 0;
we = 1;
#period;
if (q !== 8'hab) begin
$display("test 1 failed");
$finish;
end else $display("q=%b", q);
// write to ram[20]
data = 8'h77;
addr = 20;
we = 1;
#period;
if (q !== 8'h77) begin
$display("test 2 failed");
$finish;
end else $display("q=%b", q);
// read ram[0]
data = 8'h77;
addr = 0;
we = 0;
#period;
if (q !== 8'hab) begin
$display("test 3 failed");
$finish;
end else $display("q=%b", q);
// read ram[20]
data = 8'h12;
addr = 20;
we = 0;
#period;
if (q !== 8'h77) begin
$display("test 3 failed");
$finish;
end else $display("q=%b", q);
$display("all tests passed");
$finish;
end
endmodule
| 7.147927 |
module: ramtest
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_ramtest;
// Inputs
reg clk;
reg rst;
// Outputs
wire [20:0] sram_a;
wire sram_we_n;
wire test_in_progress;
wire test_result;
// Bidirs
wire [7:0] sram_d;
// Instantiate the Unit Under Test (UUT)
ramtest uut (
.clk(clk),
.rst(rst),
.sram_a(sram_a),
.sram_d(sram_d),
.sram_we_n(sram_we_n),
.test_in_progress(test_in_progress),
.test_result(test_result)
);
ram512kb la_ram (
.a(sram_a),
.d(sram_d),
.we_n(sram_we_n)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
@(negedge test_in_progress);
@(posedge clk);
$finish;
end
always begin
clk = #70 ~clk;
end
endmodule
| 6.773392 |
module ram512kb (
input wire [20:0] a,
inout wire [7:0] d,
input wire we_n
);
reg [7:0] ram[0:524287];
assign #15 d = (we_n == 1'b1) ? ram[a[18:0]] : 8'hZZ;
always @* begin
if (we_n == 1'b0) ram[a[18:0]] = #15 d;
end
endmodule
| 7.071599 |
module tb_RAM_0 ();
//-----------定义接口---------//
reg sclk;
reg [9:0] data; //输入的数据
reg [11:0] cnt; //计数,当cnt=12'd1023时写数据使能，其他读数据使能
reg [9:0] addr_we; //写地址
reg [11:0] addr_rd; //读地址
reg data_tvalid; //数据有效信号
//----------设置时钟信号----------//
initial sclk = 0;
always #5 sclk = ~sclk; //100M
//-------------------------------//
//------------初始化-------------//
initial begin
data = 0;
cnt = 0;
addr_we = 0;
addr_rd = 0;
data_tvalid = 0;
end
//------------计数器-------------//
always @(posedge sclk) begin
if (cnt == 12'd3096) begin
cnt <= 0;
addr_rd <= 0;
end else begin
cnt <= cnt + 1;
addr_rd <= addr_rd + 1;
end
end
//----------读写数据使能----------//
always @(posedge sclk) begin
if (cnt <= 12'd1023) begin
data_tvalid <= 1;
addr_we <= cnt;
end else if (cnt >= 12'd1024) begin
data_tvalid <= 0;
addr_we <= addr_we;
end else begin
data_tvalid <= data_tvalid;
end
end
//-------------------------------//
endmodule
| 6.579001 |
module tb_ram_controller;
// Inputs
reg clk;
reg sw0;
// Outputs
wire [7:0] seg;
wire [3:0] an;
wire [7:0] Led;
wire [25:0] ADDR;
wire MEMnOE;
wire MEMnWR;
wire MEMnAdv;
wire MEMWait;
wire MEMClk;
wire RAMnCS;
wire RAMCRE;
wire RAMnUB;
wire RAMnLB;
// Bidirs
wire [15:0] DATA;
// Instantiate the Unit Under Test (UUT)
ram_async_interface ram_async_interface_u (
.clk(clk),
.sw0(sw0),
.seg(seg),
.an(an),
.Led(Led),
.ADDR(ADDR),
.DATA(DATA),
.MEMnOE(MEMnOE),
.MEMnWR(MEMnWR),
.MEMnAdv(MEMnAdv),
.MEMWait(MEMWait),
.MEMClk(MEMClk),
.RAMnCS(RAMnCS),
.RAMCRE(RAMCRE),
.RAMnUB(RAMnUB),
.RAMnLB(RAMnLB)
);
cellram cellram_u (
.clk(MEMClk),
.adv_n(MEMnAdv),
.cre(RAMCRE),
.o_wait(MEMWait),
.ce_n(RAMnCS),
.oe_n(MEMnOE),
.we_n(MEMnWR),
.lb_n(RAMnLB),
.ub_n(RAMnUB),
.addr(ADDR),
.dq(DATA)
);
initial begin
// Initialize Inputs
clk = 0;
sw0 = 0;
// Wait 100 ns for global reset to finish
#165000;
/*MEMClk = 0;
MEMnAdv = 0;
RAMCRE = 1;
RAMnCS = 0;
MEMnOE = 1;
MEMnWR = 0;
RAMnLB = 0;
RAMnUB = 0;
ADDR = 0;
DATA = 0;
#100;
ADDR = 1;
#100;
RAMnCS = 1;
#100;*/
sw0 = 1;
// Add stimulus here
end
always @(clk) clk <= #5 ~clk;
endmodule
| 6.509288 |
module tb_ram_sp;
parameter DWIDTH = 8;
parameter AWIDTH = 12;
parameter CONTENT = "./memory.txt";
reg clock;
reg wren;
reg [AWIDTH-1:0] address;
reg [DWIDTH-1:0] data;
wire [DWIDTH-1:0] q;
ram_sp #(
.DWIDTH (8),
.AWIDTH (12),
.CONTENT("./ram_content.txt")
) _ram_sp (
.clock (clock),
.wren (wren),
.address(address),
.data (data),
.q (q)
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD / 2) clock = ~clock;
integer i;
initial begin
$dumpfile("tb_ram_sp.vcd");
$dumpvars(0, tb_ram_sp);
#1 clock = 1'bx;
wren = 1'bx;
address = {AWIDTH{1'bx}};
data = {DWIDTH{1'bx}};
#(CLK_PERIOD) clock = 0;
address = 0;
wren = 0;
data = 0;
for (i = 0; i <= 100; i = i + 1) begin
#(CLK_PERIOD) address = i;
wren = 1;
data = (100 - i);
end
#(CLK_PERIOD) wren = 0;
for (i = 0; i <= 100; i = i + 1) begin
#(CLK_PERIOD) address = i;
end
#(CLK_PERIOD * 50);
$finish(2);
end
endmodule
| 6.830129 |
module test packet cua anh chang lang tu tai hoa
module tb_load_2;
parameter NUM_OUTPUT = 250; // Số spike bắn ra
parameter NUM_PICTURE = 100; // Số ảnh test
parameter NUM_PACKET = 13910; // số lượng input packet trong file
reg clk, reset_n, sys_rst, csr_rst;
wire tick, input_buffer_empty;
wire [29:0] packet_in;
wire [7:0] packet_out;
wire packet_out_valid, ren_to_input_buffer, grid_controller_error, scheduler_error;
wire complete;
reg start;
wire [NUM_OUTPUT - 1:0] spike_out;
wire [2:0] state;
wire [2:0] grid_state;
wire forward_north_local_buffer_empty_all;
RANCNetworkGrid_3x2 uut(
clk, reset_n, tick, input_buffer_empty, packet_in, packet_out, packet_out_valid, ren_to_input_buffer, grid_controller_error, scheduler_error, grid_state, forward_north_local_buffer_empty_all
);
tick_gen tick_dut(
clk, reset_n, state, grid_state, input_buffer_empty, forward_north_local_buffer_empty_all, complete, tick
);
load_packet #(30,NUM_PACKET,NUM_PICTURE) packet_loader (
clk, reset_n, start, ren_to_input_buffer, tick, packet_out_valid, packet_out, grid_state, input_buffer_empty, complete, state, spike_out, packet_in
);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
sys_rst = 1;
csr_rst = 0; @(negedge clk); sys_rst = 0;
#50 csr_rst = 1;
end
always @(sys_rst, csr_rst) begin
reset_n = sys_rst | csr_rst;
end
initial begin
#100 start = 1;
#10 start = 0;
#1200000 $finish();
end
reg [NUM_OUTPUT - 1: 0] output_file [0:NUM_PICTURE - 1];
reg [NUM_OUTPUT - 1: 0] output_soft [0:NUM_PICTURE - 1];
always @ (*) begin
if (tick && packet_loader.ptr_pic_reg >= 4)
output_file [packet_loader.ptr_pic_reg - 4] = spike_out;
end
// integer i, j;
always @ (*) begin
if (packet_loader.ptr_pic_reg == 104) begin
$writememb ("output_with_loader_tick_gen.txt",output_file);
end
end
// $readmemb ("simulator_output.txt",output_soft);
// for(i = 0; i < NUM_PICTURE; i = i + 1) begin
// for(j = 0; j < NUM_OUTPUT; j = j + 1) begin
// if(output_file[i][j] != output_soft[i][j]) begin
// $display("Error at neuron %d, picture %d", j, i);
// end
// end
// end
// end
// end
endmodule
| 6.714146 |
module tb_random ();
localparam CLK_PER = 20; // 50 MHz
reg tb_clk;
reg reset_n;
reg [31:0] tb_seed;
wire [ 7:0] data;
initial begin
tb_clk = 1'b0;
forever begin
#(CLK_PER) tb_clk = ~tb_clk;
#(CLK_PER) tb_clk = ~tb_clk;
end
end
initial begin
reset_n = 1'b0;
#(25 * CLK_PER);
reset_n = 1'b1;
end
initial begin
tb_seed = 64'h12345678abcdef01;
#(1000 * CLK_PER);
$stop;
end
random dut (
.i_clk (tb_clk),
.i_reset_n(reset_n),
.i_seed (tb_seed),
.o_data(data)
);
endmodule
| 6.815512 |
module tb_randomNumber1;
//Input
reg clk;
//Outputs
wire [3:0] n;
wire [2:0] Q;
integer i;
//Instancia a unidade a ser testada
randomNumber1 uut (
.clk(clk),
.Q (Q),
.n (n)
);
//Pulso do clock
always begin
clk = 1'b1;
#10;
clk = 1'b0;
#10;
end
//Encerra a simulacao apos determinado tempo
initial begin
#500;
$finish;
end
endmodule
| 6.834485 |
module tb ();
reg CLK;
reg RST_n;
reg [3:0] seed;
wire [3:0] random_gen;
reg load;
parameter DUTY = 1;
always #DUTY CLK = ~CLK;
initial begin
CLK = 1;
RST_n = 0;
load = 0;
#10 RST_n = 1;
load = 1;
seed = 4'b0110;
#2 load = 0;
#30 load = 1;
seed = 4'b1111;
#2 load = 0;
#10 RST_n = 1;
end
random_gen U_random_gen (
.clk(CLK),
.rst_n(RST_n),
.seed(seed),
.load(load),
.random_gen(random_gen)
);
endmodule
| 7.002324 |
module tb_rca;
// TB_SIGNALS
reg clk, reset;
reg [7:0] num1;
reg [7:0] num2;
wire [8:0] sum_out;
// Instantiate the Unit Under Test (UUT)
rca uut (
.num1(num1),
.num2(num2),
.sum (sum_out)
);
initial begin
$dumpfile("tb_rca.vcd");
$dumpvars(0, tb_rca);
// Initialize Inputs
clk = 0;
reset = 0;
reset = 1;
#1;
reset = 0;
#10;
#30000 $finish;
end
always #10 clk = ~clk;
always @(clk, reset) begin
if (reset) begin
num1 <= 8'b0;
num2 <= 8'b0;
end else begin
num1 = num1 + 1;
if (num1[3:0] == 4'b1111) num2 = num2 + 1;
end
end
endmodule
| 7.160656 |
module tb_rca_36b (); //tb module declaration
integer i; //Declare integer variables to automatically transfer values,
//through mathematical operations
reg [35:0] A; //Each input must be declared as a register type,
reg [35:0] B; //Only then can a certain value be output until the next signal is input
reg Cin; //The output doesn't need to be stored,
wire [35:0] S; //so it doesn't matter whether it's a wire or a reg
wire Cout;
rca_36b m1 (
.A(A),
.B(B),
.Cin(Cin),
.S(S),
.Cout(Cout)
); //rca_36b module is instanciated to be tested
initial //start of test bench
begin //initializing each inputs
A = 0;
B = 0;
Cin = 0;
end
initial $monitor("A(%b) + B(%b) = COUT S(%b %b)", A, B, Cout, S); //monitor the values to console
always @ (A or B) //the values will be changed all time
begin
for (
i = 0; i < 64 * 64; i = i + 1
) //Assign an i value to a 72-bit storage that combines A and B every 5 nanoseconds
#5{A, B} = i;
#5 begin
A = 0;
B = 0;
end //End of first iteration statement, initialize variables
for (i = 0; i < 64 * 64; i = i + 1) //Assign i to A and i + 1 to B
#5 begin
A = i;
B = i + 1;
end
//Assing 36'b1xxx to A and B to check Carry out
#5 begin
A = 36'b100000000000000000000000000000000000;
B = 36'b100000000000000000000000000000000000;
end
#5 Cin = 1;
#5 $stop(); //end of test
end
endmodule
| 8.576883 |
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