code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module: MemoryUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_m6;
// Inputs
reg arst;
reg clk;
reg wren;
reg [34:0] din;
// Outputs
wire [34:0] dout;
// Instantiate the Unit Under Test (UUT)
MemoryUnit uut (
.arst(arst),
.clk(clk),
.wren(wren),
.din(din),
.dout(dout)
);
initial begin
clk = 1'b1;
#100;
$finish;
end
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
wren = 1'b0;
din = 35'b00000011100010000000100000000000001;
arst = 1'b0;
#1
arst = 1'b1;
#1
arst = 1'b0;
#5
#30;
wren = 1'b1;
end
endmodule
| 7.210848 |
module tb_m6502_alu;
reg [ 7 : 0] tb_operation;
reg [ 7 : 0] tb_op_a;
reg [ 7 : 0] tb_op_b;
reg tb_carry_in;
wire [ 7 : 0] tb_result;
wire tb_carry;
wire tb_zero;
wire tb_overflow;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
//----------------------------------------------------------------
// dut
//----------------------------------------------------------------
m6502_alu dut (
.operation(tb_operation),
.op_a(tb_op_a),
.op_b(tb_op_b),
.carry_in(tb_carry_in),
.result(tb_result),
.carry(tb_carry),
.zero(tb_zero),
.overflow(tb_overflow)
);
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0) begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end else begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//----------------------------------------------------------------
task init_sim;
begin
tc_ctr = 0;
error_ctr = 0;
tb_operation = 8'h0;
tb_op_a = 8'h0;
tb_op_b = 8'h0;
tb_carry_in = 0;
end
endtask // init_sim
//----------------------------------------------------------------
// main
//----------------------------------------------------------------
initial begin : main
$display(" -= Testbench for m6502 ALU started =-");
$display(" ====================================");
$display("");
init_sim();
display_test_results();
$display("");
$display("*** m6502 ALU simulation done. ***");
$finish;
end // main
endmodule
| 7.384695 |
module: M65C02_RAM
//
// Dependencies:
//
// Revision:
//
// 1.00 12B04 MAM File Created
//
// 2.00 12K18 MAM Modified to support new version of the M65C02_RAM
// module which emulates Asynchronous LUT-based RAM,
// Synchronous, flow-through RAM (Block RAM), and
// Synchronous, pipelined RAM (SynchSRAM).
//
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_M65C02_RAM;
reg Rst;
reg Clk;
reg WE;
wire [10:0] AI;
reg [ 7:0] DI;
wire [ 7:0] DO;
// Simulation Variables
reg [10:0] Cntr;
wire TC_Cntr;
reg Ext, ZP;
// Instantiate the Unit Under Test (UUT)
M65C02_RAM #(
.pAddrSize(11),
.pDataSize(8),
.pFileName("M65C02_Tst2.txt")
) RAM (
.Clk(Clk),
.Ext(Ext),
.ZP(ZP),
.WE(WE),
.AI(Cntr),
.DI(DI),
.DO(DO)
);
initial begin
// Initialize Inputs
Rst = 1;
Clk = 1;
WE = 0;
DI = 0;
// Wait 100 ns for global reset to finish
#101 Rst = 0;
// Add stimulus here
end
///////////////////////////////////////////////////////////////////////////////
//
// Clocks
always #5 Clk = ~Clk;
///////////////////////////////////////////////////////////////////////////////
always @(posedge Clk)
begin
if(Rst | TC_Cntr)
Cntr = #1 0;
else
Cntr = #1 Cntr + 1;
end
assign TC_Cntr = (Cntr == 11'h661); // Last used location in test program
assign AI = Cntr;
// Cycle through the various modes
always @(posedge Clk)
begin
if(Rst)
{Ext, ZP} <= #1 1;
else if(TC_Cntr)
{Ext, ZP} <= #1 ({Ext, ZP} + 1);
end
endmodule
| 7.521356 |
module: ControlUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_m7;
// Inputs
reg arst;
reg clk;
reg request;
reg confirm;
reg [1:0] password;
reg [1:0] syskey;
reg [34:0] configin;
// Outputs
wire [34:0] configout;
wire write_en;
wire [2:0] dbg_state;
// Instantiate the Unit Under Test (UUT)
ControlUnit uut (
.arst(arst),
.clk(clk),
.request(request),
.confirm(confirm),
.password(password),
.syskey(syskey),
.configin(configin),
.configout(configout),
.write_en(write_en),
.dbg_state(dbg_state)
);
initial begin
clk = 1'b1;
#300;
$finish;
end
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
password = 2'b00;
syskey = 2'b10;
request = 1'b1;
confirm = 1'b0;
configin = 35'b00000000000000000000000000000000011;
arst = 1'b0;
#1
arst = 1'b1;
#1
arst = 1'b0;
#50
confirm = 1'b1;
#100
request = 1'b0;
#1
request = 1'b1;
#5
password = 2'b10;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 7.944032 |
module tb ();
reg i_clk;
reg i_rstn;
reg [15:0] i_data;
reg [15:0] i_weight;
reg [31:0] i_pre_result;
wire [15:0] o_data_next;
wire [15:0] o_result;
mac u0 (
.i_clk(i_clk),
.i_rstn(i_rstn),
.i_data(i_data),
.i_weight(i_weight),
.i_pre_result(i_pre_result),
.o_data_next(o_data_next),
.o_result(o_result)
);
always begin
#5;
i_clk <= ~i_clk;
end
task d_in;
input [15:0] i_d;
input [15:0] i_w;
input [31:0] i_pr;
begin
i_data <= i_d;
i_weight <= i_w;
i_pre_result <= i_pr;
@(posedge i_clk);
end
endtask
initial begin
i_clk = 0;
i_rstn = 1;
#1 i_rstn = 0;
#1 i_rstn = 1;
@(posedge i_clk);
//d_in(.i_d(1), .i_w(2), .i_pre(3));
d_in(1, 2, 3);
d_in(1, 4, 3);
d_in(4, 2, 6);
@(posedge i_clk);
$finish;
end
initial begin
$dumpfile("test.vcd");
$dumpvars(-1, u0);
end
endmodule
| 7.195167 |
module tb_MACC ();
parameter BITWIDTH = 32;
parameter ADDRWIDTH = 4;
parameter MEMHEIGHT = 2 ** ADDRWIDTH;
localparam input_A_data_path = {`path, "tb/data/MACC_input_A.bin"};
localparam input_B_data_path = {`path, "tb/data/MACC_input_B.bin"};
localparam input_C_data_path = {`path, "tb/data/MACC_input_C.bin"};
localparam expected_data_path = {`path, "tb/data/MACC_expected.bin"};
localparam S_RUNNING = 1'b1;
localparam S_STOPPED = 1'b0;
reg [ BITWIDTH - 1 : 0] mem_a_data[MEMHEIGHT - 1 : 0];
reg [ BITWIDTH - 1 : 0] mem_b_data[MEMHEIGHT - 1 : 0];
reg [ BITWIDTH - 1 : 0] mem_c_data[MEMHEIGHT - 1 : 0];
reg [ BITWIDTH - 1 : 0] mem_result[MEMHEIGHT - 1 : 0];
reg aclk;
reg [ BITWIDTH - 1 : 0] a_data;
reg [ BITWIDTH - 1 : 0] b_data;
reg [ BITWIDTH - 1 : 0] c_data;
wire a_valid;
wire b_valid;
wire c_valid;
wire [ BITWIDTH - 1 : 0] d_data;
wire d_valid;
reg state;
reg start;
reg stop;
reg [ADDRWIDTH - 1 : 0] addr;
assign a_valid = (state == S_RUNNING);
assign b_valid = (state == S_RUNNING);
assign c_valid = (state == S_RUNNING);
always #(`period / 2) aclk = ~aclk;
initial begin
$readmemh(input_A_data_path, mem_a_data);
$readmemh(input_B_data_path, mem_b_data);
$readmemh(input_C_data_path, mem_c_data);
$readmemh(expected_data_path, mem_result);
aclk <= 1'b1;
state <= S_STOPPED;
start <= 1'b0;
addr <= 'b0;
end
integer i;
initial begin
#(`period);
start = 1'b1;
#(2 * `period);
for (i = 0; i < MEMHEIGHT; i = i + 1) begin
#(`period);
if (d_data == mem_result[i] && d_valid) $display("[ TEST CASE #%d ] PASS", i);
else $display("[ TEST CASE #%d ] FAIL : %x expected(%x)", i, d_data, mem_result[i]);
end
end
always @(posedge aclk) if (stop) state <= S_STOPPED;
always @(posedge aclk) if (start) state <= S_RUNNING;
always @(posedge aclk) if (state == S_RUNNING) start <= 1'b0;
always @(posedge aclk) if (state == S_STOPPED) stop <= 1'b0;
always @(posedge aclk)
if (state == S_RUNNING) addr <= addr + 1;
else addr <= 'd0;
always @(posedge aclk) if (state == S_RUNNING && addr == MEMHEIGHT - 1) stop <= 'd1;
always @(posedge aclk)
if (state == S_RUNNING) begin
a_data <= mem_a_data[addr];
b_data <= mem_b_data[addr];
c_data <= mem_c_data[addr];
end else begin
a_data <= 'd0;
b_data <= 'd0;
c_data <= 'd0;
end
MACC #(
.BITWIDTH(BITWIDTH)
) u_macc (
.aclk(aclk),
.s_axis_a_tdata(a_data),
.s_axis_a_tvalid(a_valid),
.s_axis_b_tdata(b_data),
.s_axis_b_tvalid(b_valid),
.s_axis_c_tdata(c_data),
.s_axis_c_tvalid(c_valid),
.m_axis_result_tdata(d_data),
.m_axis_result_tvalid(d_valid)
);
endmodule
| 7.086065 |
module: multi_MAC_Base
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mac_base;
// Inputs
reg clk;
reg sof;
reg [79:0] A;
reg [15:0] B;
// Outputs
wire [179:0] C;
wire [4:0] valid;
// Instantiate the Unit Under Test (UUT)
multi_MAC_Base uut (
.clk(clk),
.sof(sof),
.A(A),
.B(B),
.C(C),
.valid(valid)
);
initial begin
// Initialize Inputs
clk = 0;
sof = 0;
A = 0;
B = 0;
#310
A = 80'h00020007000900030005; B = 16'h0004;
#20
sof = 1'b1;
#200
#100
$stop;
end
always
#`clkperiodby2 clk <= ~clk;
endmodule
| 7.174319 |
module tb_MAC_mac_unit;
reg clk;
reg reset;
reg [7:0] in_1;
reg [7:0] in_2;
reg [7:0] in_add, num_a, num_x, num_b, num_c;
reg mode;
reg mul_input_mux, adder_input_mux;
wire [16:0] mac_output;
reg [16:0] check_tri;
reg [7:0] num_a_test[2:0];
reg [7:0] num_x_test[2:0];
reg [7:0] num_b_test[2:0];
reg [7:0] num_c_test[2:0];
reg [1:0] tri_test_inputs;
reg test_mode;
parameter TEST_TRI = 1'b0;
parameter TEST_SUMP = 1'b1;
MAC_mac_unit dut_mac_0 (
.clk(clk),
.reset(reset),
.in_1(in_1),
.in_2(in_2),
.in_add(in_add),
.mode(mode),
.mul_input_mux(mul_input_mux),
.adder_input_mux(adder_input_mux),
.mac_output(mac_output)
);
//Trinomial ideal unit
always @(posedge clk or posedge reset) begin
if (reset) begin
check_tri <= 1'b0;
end else begin
//(a*x + b)*x+c
//(in_1*in_2 + in_add)*in_2 + in_add
check_tri <= (((num_a * num_x) + num_b) * num_x) + num_c;
end
end
//Trinomial checker
always @(posedge clk or posedge reset) begin
if (check_tri == mac_output) begin
$display("Success\n");
$display("\t%d,\t%d,\t%d,\t%d,\t%d,\t%d", in_1, in_2, in_add, mode, mac_output, check_tri);
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
num_a_test[0] <= 'd5;
num_x_test[0] <= 'd3;
num_b_test[0] <= 'd2;
num_c_test[0] <= 'd1;
num_a_test[1] <= 'd9;
num_x_test[1] <= 'd8;
num_b_test[1] <= 'd7;
num_c_test[1] <= 'd6;
num_a_test[2] <= $random;
num_x_test[2] <= $random;
num_b_test[2] <= $random;
num_c_test[2] <= $random;
end
end
initial begin
$display("\t\tin_1,\tin_2,\tin_add,\tmode,\tmac_output, \tideal_out");
clk = 1;
reset = 1;
//tri_test_inputs = 'b0;
#10;
reset = 0;
test_mode = TEST_SUMP;
//Assert/De-assert reset
//#1 -> reset_triger;#19;
case (test_mode)
TEST_TRI: begin
for (
tri_test_inputs = 0; tri_test_inputs < 3; tri_test_inputs = tri_test_inputs + 1'b1
) begin
//(a*x + b)*x+c
mul_input_mux = 1'b0;
adder_input_mux = 1'b0;
//Mode 1 for tri
mode = 'd1;
//a
in_1 = num_a_test[tri_test_inputs];
num_a = num_a_test[tri_test_inputs];
//x
in_2 = num_x_test[tri_test_inputs];
num_x = num_x_test[tri_test_inputs];
//b
in_add = num_b_test[tri_test_inputs];
num_b = num_b_test[tri_test_inputs];
//c for testing
num_c = num_c_test[tri_test_inputs];
#10;
//c
mul_input_mux = 1'b1;
in_add = num_c_test[tri_test_inputs];
#30;
end
end
TEST_SUMP: begin
for (
tri_test_inputs = 0; tri_test_inputs < 3; tri_test_inputs = tri_test_inputs + 1'b1
) begin
mul_input_mux = 1'b0;
adder_input_mux = 1'b1;
mode = 1'b0;
in_1 = num_a_test[tri_test_inputs];
in_2 = num_x_test[tri_test_inputs];
#20;
end
end
default: begin
end
endcase
$finish;
end
//code for reset logic
event reset_triger;
event reset_done_trigger;
initial begin
forever begin
@(reset_triger);
@(posedge clk);
reset = 1'b1;
@(posedge clk);
reset = 1'b0;
->reset_done_trigger;
end
end
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
endmodule
| 7.906038 |
module tb_MAC_SWITCH ();
reg clk;
reg arst_n;
initial begin
$dumpfile("./vcd/tb_switch.vcd");
$dumpvars(0, mac_switch);
arst_n <= 1'b0;
#100 arst_n <= 1'b1;
#10000 $finish;
end
always begin
clk <= 1'b1;
#10;
clk <= 1'b0;
#10;
end
reg [127:0] h_fifo_dout;
wire h_fifo_rden;
reg h_fifo_empty;
reg [7:0] b_fifo_dout;
wire b_fifo_rden;
reg b_fifo_empty;
reg b_fifo_del;
initial begin
h_fifo_empty <= 1'b1;
h_fifo_dout <= {12'b0, 1'b1, 1'b0, 2'd2, 48'hFF_FF_FF_FF_FF_FF, 48'h0A_0B_0C_0D_0E, 16'h08_10};
b_fifo_dout <= 8'h11;
b_fifo_empty <= 1'b0;
b_fifo_del <= 1'b0;
#1000;
h_fifo_empty <= 1'b0;
end
always @(posedge clk) begin
if (h_fifo_rden) h_fifo_dout <= h_fifo_dout + 1'b1;
if (b_fifo_rden) b_fifo_dout <= b_fifo_dout + 1'b1;
if (b_fifo_dout == 8'hFF) b_fifo_del <= 1'b1;
end
MAC_SWITCH mac_switch (
.clk(clk),
.arst_n(arst_n),
/* INPUT : Header FIFO */
.h_fifo_dout (h_fifo_dout),
.h_fifo_rden (h_fifo_rden),
.h_fifo_empty(h_fifo_empty),
.b_fifo_dout (b_fifo_dout),
.b_fifo_rden (b_fifo_rden),
.b_fifo_empty(b_fifo_empty),
.b_fifo_del (b_fifo_del),
.p0_fifo_afull(1'b0),
.p1_fifo_afull(1'b0),
.p2_fifo_afull(1'b0),
.p3_fifo_afull(1'b0),
.mutex_req(),
.mutex_val(4'b1111),
.mask_port(4'b0000)
);
endmodule
| 7.392951 |
module tb_main_fsmc;
// design_main_fsmc Inputs
reg clk;
reg rst_n;
reg [15:0] fsmc_A;
reg fsmc_NE;
reg fsmc_NWE;
reg fsmc_NOE;
// design_main_fsmc Outputs
// design_main_fsmc Bidirs
wire [15:0] fsmc_D;
reg [15:0] fsmc_wdata;
wire [15:0] fsmc_rdata;
assign fsmc_rdata = fsmc_D;
assign fsmc_D = (fsmc_NOE) ? fsmc_wdata : {16{1'bz}};
design_main_fsmc #(
.sim_present(1)
) u_design_main_fsmc (
.clk (clk),
.rst_n (rst_n),
.fsmc_A (fsmc_A),
.fsmc_NE (fsmc_NE),
.fsmc_NWE(fsmc_NWE),
.fsmc_NOE(fsmc_NOE),
.fsmc_D(fsmc_D)
// .fsmc_wdata (fsmc_wdata),
// .fsmc_rdata (fsmc_rdata)
);
localparam FSMC_width_addr = 16;
localparam FSMC_width_data = 16;
localparam FSMC_ADDSET = 200;
localparam FSMC_DATAST = 200;
// mode A
task hostWrite;
input [FSMC_width_addr-1:0] addr;
input [FSMC_width_data-1:0] wdata;
begin : Block_hostWrite
fsmc_A = addr;
fsmc_NE = 0;
fsmc_NOE = 1;
fsmc_NWE = 1;
#FSMC_ADDSET fsmc_wdata = wdata;
fsmc_NWE = 0;
#FSMC_DATAST // ingore the end one HCLK
fsmc_NE = 1;
fsmc_NOE = 1;
fsmc_NWE = 1;
end
endtask
task hostRead;
input [FSMC_width_addr-1:0] addr;
output [FSMC_width_data-1:0] rdata;
begin : Block_hostRead
fsmc_A = addr;
fsmc_NE = 0;
fsmc_NOE = 1;
fsmc_NWE = 1;
#FSMC_ADDSET fsmc_NOE = 0;
#FSMC_DATAST fsmc_NE = 1;
fsmc_NOE = 1;
fsmc_NWE = 1;
rdata = fsmc_rdata;
end
endtask
integer i;
reg [15:0] hostRece;
reg [15:0] data[2:0];
always #10 clk = ~clk;
initial begin
clk = 0;
rst_n = 0;
fsmc_A = 'd0;
fsmc_wdata = 'd0;
fsmc_NE = 1;
fsmc_NWE = 1;
fsmc_NOE = 1;
hostRece = 0;
data[0] = 0;
data[1] = 0;
data[2] = 0;
#1000 rst_n = 1;
// en sys
hostWrite(16'd4, 16'd1);
// test sync register
$write("test sync register\n");
for (i = 0; i < 10; i = i + 1) begin
data[0] = {$random};
data[1] = {$random};
data[2] = {$random};
#100 hostWrite(16'd1, data[0]);
#100 hostWrite(16'd2, data[1]);
#100 hostWrite(16'd3, data[2]);
#100 hostRead(16'd0, hostRece);
if (hostRece == (data[0] + data[1] + data[2])) begin
$write("test%d pass\n", i);
end else begin
$write("test%d failed, data0:%h, data1:%h, data2:%h, rece:%h\n", i, data[0], data[1],
data[2], hostRece);
end
end
$write("\n");
// test fifo
$write("test fifo\n");
// write
for (i = 0; i < 10; i = i + 1) begin
#100 hostWrite(16'd5, i + 1);
end
// read
for (i = 0; i < 10; i = i + 1) begin
#100 hostRead(16'd5, hostRece);
if (hostRece == i + 1) $write("test%d pass\n", i);
else $write("test%d failed, rece:%d\n", i, hostRece);
end
$write("\n");
// test ram
$write("test ram\n");
data[0] = 16'd0;
hostRece = 16'd0;
// write
for (i = 0; i < 10; i = i + 1) begin
#100 hostWrite(16'h0100 + i, i + 1);
end
// read
for (i = 0; i < 10; i = i + 1) begin
#100 hostRead(16'h0100 + 9 - i, hostRece);
if (hostRece == (9 - i + 1)) $write("test%d pass\n", i);
else $write("test%d failed, rece:%d\n", i, hostRece);
end
$write("\n");
$write("Simulation finish!\n");
$stop;
end
endmodule
| 7.383994 |
module: mapping_controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mapping_controller;
// Inputs
reg clk_rxg;
reg rst_rx_n;
reg [11:0] data_trained0;
reg [11:0] data_trained1;
reg [11:0] data_trained2;
reg [11:0] data_trained3;
reg [11:0] data_trained4;
reg [11:0] data_trained5;
reg [11:0] data_trained6;
reg [11:0] data_trained7;
reg [11:0] data_trained8;
reg [11:0] data_trained9;
reg [11:0] data_trained10;
reg [11:0] data_trained11;
reg [11:0] data_trained12;
reg [11:0] data_trained13;
reg [11:0] data_trained14;
reg [11:0] data_trained15;
reg fvals_map;
reg lvals_map;
reg [11:0] cnt_lvals;
reg [11:0] cnt_fvals;
reg [1:0] cnt;
reg [1:0] fsm_lval;
parameter s_HIGH = 2'b00,
s_LOW = 2'b01;
// Outputs
wire [11:0] datapar_out0;
wire [11:0] datapar_out1;
wire [11:0] datapar_out2;
wire [11:0] datapar_out3;
wire [11:0] datapar_out4;
wire [11:0] datapar_out5;
wire [11:0] datapar_out6;
wire [11:0] datapar_out7;
wire fvals;
wire lvals;
// Instantiate the Unit Under Test (UUT)
mapping_controller uut (
.clk_rxg(clk_rxg),
.rst_rx_n(rst_rx_n),
.data_trained0(data_trained0),
.data_trained1(data_trained1),
.data_trained2(data_trained2),
.data_trained3(data_trained3),
.data_trained4(data_trained4),
.data_trained5(data_trained5),
.data_trained6(data_trained6),
.data_trained7(data_trained7),
.data_trained8(data_trained8),
.data_trained9(data_trained9),
.data_trained10(data_trained10),
.data_trained11(data_trained11),
.data_trained12(data_trained12),
.data_trained13(data_trained13),
.data_trained14(data_trained14),
.data_trained15(data_trained15),
.datapar_out0(datapar_out0),
.datapar_out1(datapar_out1),
.datapar_out2(datapar_out2),
.datapar_out3(datapar_out3),
.datapar_out4(datapar_out4),
.datapar_out5(datapar_out5),
.datapar_out6(datapar_out6),
.datapar_out7(datapar_out7),
.fvals_map(fvals_map),
.lvals_map(lvals_map),
.fvals(fvals),
.lvals(lvals)
);
initial begin
// Initialize Inputs
clk_rxg = 0;
rst_rx_n = 0;
data_trained0 = 1;
data_trained1 = 2;
data_trained2 = 1;
data_trained3 = 2;
data_trained4 = 1;
data_trained5 = 2;
data_trained6 = 1;
data_trained7 = 2;
data_trained8 = 1;
data_trained9 = 2;
data_trained10 = 1;
data_trained11 = 2;
data_trained12 = 1;
data_trained13 = 2;
data_trained14 = 1;
data_trained15 = 2;
fvals_map = 0;
lvals_map = 0;
// Wait 100 ns for global reset to finish
#100;
rst_rx_n = 1;
// Add stimulus here
end
always #10 clk_rxg = ~clk_rxg;
always @(posedge clk_rxg) begin
if(!rst_rx_n) begin
fvals_map <= 1'b0;
lvals_map <= 1'b0;
cnt_lvals <= 10'd0;
cnt_fvals <= 12'd0;
cnt <= 2'd0;
fsm_lval <= s_HIGH;
end
else begin
case(fsm_lval)
s_HIGH: begin
if(cnt_lvals == 10'd128)begin
cnt_lvals <= 10'd0;
lvals_map <= 1'b0;
fsm_lval <= s_LOW;
end
else begin
lvals_map <= 1'b1;
cnt_lvals <= cnt_lvals + 10'd1;
end
end
s_LOW: begin
if(cnt_lvals == 10'd1)begin
cnt_lvals <= 10'd1;
lvals_map <= 1'b1;
fsm_lval <= s_HIGH;
end
else begin
cnt_lvals <= cnt_lvals + 10'd1;
lvals_map <= 1'b0;
end
end
endcase
if(cnt_fvals == 12'd1028) begin
cnt_fvals <= 12'd0;
fvals_map <= 1'b0;
end
else begin
cnt_fvals <= cnt_fvals + 12'd1;
fvals_map <= 1'b1;
end
end
end
endmodule
| 6.927136 |
module tb_mash111;
// mash111 Parameters
parameter PERIOD = 10;
parameter WIDTH = 24;
parameter A_GAIN = 1;
// mash111 Inputs
reg clk = 0;
reg rst_n = 0;
reg [WIDTH-1:0] x_i = 0;
// mash111 Outputs
wire [ 3:0] y_o;
wire [WIDTH-1:0] e_o;
initial begin
forever #(PERIOD / 2) clk = ~clk;
end
initial begin
#(PERIOD * 2) rst_n = 1;
end
integer dout_file;
initial begin
dout_file = $fopen("/home/EDA/vsim/mash/tb/data.txt"); //打开所创建的文件
if (dout_file == 0) begin
$display("can not open the file!"); //创建文件失败，显示can not open the file!
$stop;
end
end
always @(posedge clk) begin
$fdisplay(dout_file, "%d", $signed(y_o)); //保存有符号数据
end
mash111 #(
.WIDTH (WIDTH),
.A_GAIN(A_GAIN)
) u_mash111 (
.clk (clk),
.rst_n(rst_n),
.x_i (x_i[WIDTH-1:0]),
.y_o(y_o[3:0]),
.e_o(e_o[WIDTH-1:0])
);
initial begin
x_i = 'd8388607; // 2^23 - 1
#(PERIOD * 10000);
$finish;
end
endmodule
| 7.252604 |
module tb_master #(
parameter data_width = 8,
reg_num = 4
) (
input wire clk,
input wire rst,
// outputs: generated inputs for DUT
output reg [data_width - 1 : 0] reg_a,
output reg [data_width - 1 : 0] reg_b,
// input: outputs of DUT
input wire [data_width : 0] inp
);
// file handles
integer infile, outfile;
// status of file input
integer statusI;
integer in_a, in_b;
integer count = 0;
// open and check files
initial begin
infile = $fopen("input.txt", "r");
outfile = $fopen("output.txt", "w");
if (0 == infile) begin
$display("ERROR: could not read input.txt");
$finish();
end
if (0 == outfile) begin
$display("ERROR: could not open output.txt");
$finish();
end
end
// write outputs to file, then read inputs from file
always @(posedge clk) begin
if (rst) begin
reg_a <= 0;
reg_b <= 0;
end
if (~rst) begin
count <= count + 1;
if (count > 0) begin
$fwrite(outfile, "%d %d -> %d\n", reg_a, reg_b, inp);
end
// print inputs and outputs on each cycle
#(0.1_000)
$display(
$time, ": a=%d, b=%d => =%d", reg_a, reg_b, inp
); //added delay to give time to DUT because DUT uses clk as well
// read inputs from file
#(0.2_000) statusI = $fscanf(infile, "%d %d\n", reg_a, reg_b);
//statusI = $fscanf(infile, "%d %d\n", in_a, in_b);
//reg_a <= in_a;
//reg_b <= in_b;
end
end
endmodule
| 6.644801 |
module tb_master_mem ();
reg clk, reset, active;
reg [7:0] base_addr;
reg [3:0] num_row, num_col;
wire [127:0] out_addr;
wire [15:0] out_en;
wire done;
always begin
#5;
clk = ~clk;
end
initial begin
clk = 0;
#5;
reset = 1;
active = 0;
base_addr = 8'h00;
num_col = 4'd7;
num_row = 4'd3;
#10;
reset = 0;
active = 1;
#10;
active = 0;
repeat (16) begin
#10;
end
$stop;
end
master_mem_control MEM (
.clk(clk),
.reset(reset),
.active(active),
.out_en(out_en),
.base_addr(base_addr),
.num_row(num_row),
.num_col(num_col),
.out_addr(out_addr),
.done(done)
);
endmodule
| 7.060122 |
module TB_MAXPOOL2;
// Inputs
reg [35:0] y;
reg clk;
reg start;
reg reset;
// Outputs
wire [1:0] mx2_done;
wire [3:0] mx2_count;
wire [35:0] mx2_output;
// Instantiate the Unit Under Test (UUT)
MAXPOOL2 uut (
.mx2_input(y),
.clk(clk),
.start(start),
.reset(reset),
.mx2_done(mx2_done),
.mx2_count(mx2_count),
.mx2_output(mx2_output)
);
initial begin
// Initialize Inputs
y = 0;
clk = 0;
start = 0;
reset = 0;
#50;
reset = 1;
// Add stimulus here
#100 reset = 0;
start = 1;
y = 15;
#50 y = 20;
#50 y = 25;
#50 y = 30;
#50 y = 35;
#50 y = 40;
#50 y = 45;
#50 y = 50;
#50 y = 55;
#50 y = 60;
#50 y = 65;
#50 y = 70;
#50 y = 75;
#50 y = 80;
#50 y = 15;
#50 y = 90;
#50 y = 100;
#50 y = 120;
#50 y = 125;
#50 y = 30;
#50 y = 35;
#50 y = 40;
#50 y = 45;
#50 y = 50;
#50 y = 55;
#50 y = 60;
#50 y = 65;
#50 y = 70;
#50 y = 75;
#50 y = 80;
#50 y = 85;
#50 y = 90;
#50 y = 55;
#50 y = 60;
#50 y = 65;
#50 y = 70;
#50 y = 75;
#50 y = 80;
#50 y = 15;
#50 y = 90;
#50 y = 100;
#50 y = 120;
#50 y = 125;
#50 y = 30;
#50 y = 35;
#50 y = 40;
#50 y = 45;
#50 y = 50;
#50 y = 55;
#50 y = 60;
#50 y = 65;
#50 y = 70;
#50 y = 75;
#50 y = 80;
#50 y = 85;
#50 y = 90;
#50 y = 55;
#50 y = 60;
#50 y = 65;
#50 y = 70;
#50 y = 75;
#50 y = 80;
#50 y = 15;
#50 y = 90;
#50 y = 100;
#50 y = 120;
#50 y = 125;
#50 y = 30;
#50 y = 35;
#50 y = 40;
#50 y = 45;
#50 y = 1000;
#50 y = 55;
#50 y = 60;
#50 y = 65;
#50 y = 70;
#50 y = 75;
#50 y = 80;
#50 y = 85;
#50 y = 90;
#50 y = 55;
#50 y = 60;
#50 y = 65;
#50 y = 150;
#50 y = 75;
#50 y = 80;
#50 y = 15;
#50 y = 90;
#50 y = 100;
#50 y = 120;
#50 y = 125;
#50 y = 30;
#50 y = 35;
#50 y = 40;
#50 y = 45;
#50 y = 50;
#50 y = 55;
#50 y = 60;
#50 y = 65;
#50 y = 70;
#50 y = 75;
#50 y = 80;
#50 y = 85;
#50 y = 90; //#10000 start = 0;
end
always #25 clk = ~clk;
endmodule
| 6.554961 |
module tb_mdct;
reg clock;
reg reset;
reg [ 7:0] dcti;
reg idv;
wire [11:0] dcto;
wire odv;
reg [31:0] icnt = 0;
reg [31:0] ocnt = 0;
initial begin
$dumpfile("output/vcd/_tb_mdct.vcd");
$dumpvars(0, tb_mdct);
end
initial begin
$from_myhdl(clock, reset, dcti, idv);
$to_myhdl(dcto, odv);
end
always @(posedge clock) begin
if (idv) begin
icnt <= icnt + 1;
end
if (odv) begin
ocnt <= ocnt + 1;
end
end
MDCT DUT (
.clk (clock),
.rst (reset),
.dcti(dcti),
.idv (idv),
.dcto(dcto),
.odv (odv)
);
endmodule
| 7.44928 |
module: MDF
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_MDF;
// Inputs
reg clk;
reg rst;
reg [3:0] entrada;
// Outputs
wire salida;
wire [15:0]q;
// Instantiate the Unit Under Test (UUT)
MDF uut (
.clk(clk),
.rst(rst),
.entrada(entrada),
.salida(salida),
.q(q)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
entrada = 0;
// Wait 100 ns for global reset to finish
#10;
entrada = 4'b1111;
#10000;
entrada = 4'b1010;
end
always #1000 clk = ~clk;
/* initial
begin
$monitor("%d,\t%b,\t%b,\t%b,\t%d",$time, clk,rst,div,clkd);
end
initial
#500 $finish;
*/
endmodule
| 6.629823 |
module tb_mealy ();
initial begin
$dumpfile("tb_mealy.vcd");
$dumpvars;
end
reg clock;
wire outp;
reg inp, reset;
initial clock = 1'b1;
always #5 clock = ~clock;
mealy m1 (
.reset(reset),
.clock(clock),
.inp (inp),
.outp (outp)
);
initial begin
reset <= 1'b1;
inp <= 1'b0;
#10 reset <= 1'b0;
#10 inp <= 1'b1;
#10 inp <= 1'b1;
#10 inp <= 1'b0;
#10 inp <= 1'b0;
#10 $finish;
end
endmodule
| 7.573422 |
module tb_memArr ();
parameter width_height = 4;
localparam data_width = width_height * 8;
localparam en_bits = width_height;
reg clk;
reg [en_bits - 1:0] rd_en;
reg [en_bits - 1:0] wr_en;
reg [data_width - 1:0] wr_data;
reg [data_width - 1:0] rd_addr;
reg [data_width - 1:0] wr_addr;
wire [data_width -1:0] rd_data;
memArr DUT (
.clk (clk),
.rd_en (rd_en),
.wr_en (wr_en),
.wr_data(wr_data),
.rd_addr(rd_addr),
.wr_addr(wr_addr),
.rd_data(rd_data)
);
always begin
#5;
clk = ~clk;
end // always
initial begin
clk = 1'b0;
rd_en = 4'b0000;
wr_en = 4'b0000;
wr_data = 32'h0000_0000;
wr_addr = 32'h0000_0000;
rd_addr = 32'h0000_0000;
#10;
wr_en = 4'b1111;
wr_addr = 32'h0000_0000;
wr_data = 32'h0C08_0400;
#10;
wr_addr = 32'h0101_0101;
wr_data = 32'h0D09_0501;
#10;
wr_addr = 32'h0202_0202;
wr_data = 32'h0E0A_0602;
#10;
wr_addr = 32'h0303_0303;
wr_data = 32'h0F0B_0703;
#10;
wr_en = 4'b0000;
rd_en = 4'b1111;
rd_addr = 323'h0000_0000;
#10;
rd_addr = 32'h0101_0101;
#10;
rd_addr = 32'h0202_0202;
#10;
rd_addr = 32'h0303_0303;
#30;
$stop;
end // initial
endmodule
| 6.797715 |
module tb_memories (
input wire clk_i,
input wire reset_i,
input wire [15:0] xpm_addr_i,
output reg [31:0] xpm_data_o,
input wire [15:0] xdm0_addr_i,
input wire [15:0] xdm0_data_i,
input wire xdm0_wr_en_i,
output reg [15:0] xdm0_data_o,
input wire [15:0] xdm1_addr_i,
input wire [15:0] xdm1_data_i,
input wire xdm1_wr_en_i,
output reg [15:0] xdm1_data_o
);
integer file;
integer count;
reg [0:79*8-1] line;
integer finished;
integer writeprogrammem;
integer programmemoffset;
integer dm0offset;
integer lineno;
integer i;
reg [31:0] val;
reg [31:0] xpm_data;
// The memories
reg [31:0] program_mem [0:65535];
reg [15:0] data_mem0 [0:65535];
reg [15:0] data_mem1 [0:65535];
reg [15:0] xdm0_addr_ff;
reg [15:0] xdm1_addr_ff;
reg [15:0] xpm_addr_ff;
always @(posedge clk_i) begin
if (!reset_i) begin
xpm_addr_ff <= 0;
end else begin
xdm0_addr_ff <= xdm0_addr_i;
xdm1_addr_ff <= xdm1_addr_i;
xpm_addr_ff <= xpm_addr_i;
end
end
always @* begin
// if(reset_i == 1'b1)
xpm_data = program_mem[xpm_addr_ff];
/* -----\/----- EXCLUDED -----\/-----
else
xpm_data_o <= {32{1'bx}};
-----/\----- EXCLUDED -----/\----- */
end
always @(posedge clk_i) begin
// if(reset_i == 1'b1)
xpm_data_o <= xpm_data;
/* -----\/----- EXCLUDED -----\/-----
else
xpm_data_o <= {32{1'bx}};
-----/\----- EXCLUDED -----/\----- */
end
always @(posedge clk_i) begin
if (xdm0_wr_en_i) begin
data_mem0[xdm0_addr_i] <= xdm0_data_i;
end
end
always @(posedge clk_i) begin
xdm0_data_o = data_mem0[xdm0_addr_ff];
end
always @(posedge clk_i) begin
if (xdm1_wr_en_i) begin
data_mem1[xdm1_addr_i] <= xdm1_data_i;
end
end
always @(posedge clk_i) begin
xdm1_data_o = data_mem1[xdm1_addr_ff];
end
initial begin
file = $fopen("test.hex", "r");
finished = 0;
writeprogrammem = 0;
programmemoffset = 0;
dm0offset = 0;
lineno = 0;
for (i = 0; i < 65536; i = i + 1) begin
program_mem[i] = 32'h0;
data_mem0[i] = 16'h0;
data_mem1[i] = 16'h0;
end
while (!finished) begin
lineno = lineno + 1;
count = $fgets(line, file);
if (count == 0) begin
finished = 1;
end else begin
line = line << (79 - count) * 8;
if (line[0:7] == ";") begin
// skip comments
end else if (line[0:4*8-1] == "code") begin
writeprogrammem = 1;
end else if (line[0:4*8-1] == "rom0") begin
writeprogrammem = 0;
end else if (line[0:9*8-1] == "org 32768") begin
dm0offset = 16'd32768;
end else if ($sscanf(line, "%08x", val) == 1) begin
if (writeprogrammem) begin
program_mem[programmemoffset] = val;
programmemoffset = programmemoffset + 1;
end else begin
data_mem0[dm0offset] = val[15:0];
dm0offset = dm0offset + 1;
end
end else begin
$display("%m: Error at line %d, could not understand \"%s\"", lineno, line);
$stop;
end
end // else: !if(count == 0)
end // while (!finished)
end // initial begin
endmodule
| 7.033243 |
module tb_MEMINTERFACE;
reg clk, rst;
reg gen_done, sobel_done;
wire gray_en, sobel_en;
wire [5:0] state;
FSM fsm (
clk,
rst,
gen_done,
sobel_done,
gray_en,
sobel_en,
state
);
reg gen_en;
wire [9:0] addr;
wire done;
reg [9:0] c_addr;
//module addressGen(clk, rst, gen_en, sobel_en, addr, done);
addressGen ADDGEN (
clk,
rst,
gen_en,
sobel_en,
addr,
done
);
wire [11:0] mem;
wire [ 3:0] red;
wire [ 3:0] green;
wire [ 3:0] blue;
ROM rom (
addr,
red,
green,
blue,
mem
);
reg wr_en, rd_en;
reg [ 9:0] wr_addr;
reg [11:0] wr_data;
reg [ 9:0] rd_addr;
wire [11:0] data_out;
wire [ 3:0] wr_gx;
wire [ 3:0] wr_gy;
memOp Gray (
clk,
gray_en,
rd_en,
sobel_en,
addr,
wr_data,
addr - 1'b1,
data_out,
wr_gx,
wr_gy
);
reg [11:0] rgb_in;
wire [ 3:0] gray_out;
grayScale grayscale (
clk,
rgb_in,
gray_out
);
//testing memory outputs to
reg [11:0] Gx_in;
wire Gx_out;
//module memory( clk, rd_en, wr_en, wr_addr, wr_data, rd_addr, data_out);
memory Gx (
clk,
1'b1,
sobel_en,
addr,
Gx_in,
addr - 1'b1,
Gx_out
);
initial begin
rst = 1'b1;
#300;
rst = 1'b0;
#200;
#2000;
#50000;
#1000;
#50000;
#50000; // gets to 10000_00000
#50000; // 1111110111
#2000;
#200;
#2000;
#50000;
#1000;
#50000;
#50000; // gets to 10000_00000
#50000; // 1111110111
#2000;
#200;
$stop;
end
always @(*) begin
Gx_in = {wr_gx, wr_gx, wr_gx};
rd_en = 1'b1;
gen_en = gray_en;
gen_done = done;
sobel_done = done;
rgb_in = mem;
wr_data = {gray_out, gray_out, gray_out};
end
always begin
if (rst == 1'b1) begin
clk = 1'b0;
#1;
end else begin
#100;
clk = ~clk;
end
end
endmodule
| 7.116508 |
module: MemoryUnit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_MemoryUnit;
// Inputs
reg arst;
reg clk;
reg wren;
reg [34:0] din;
// Outputs
wire [34:0] dout;
// Instantiate the Unit Under Test (UUT)
MemoryUnit uut (
.arst(arst),
.clk(clk),
.wren(wren),
.din(din),
.dout(dout)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
arst = 1;
clk = 0;
wren = 0;
din = 0;
// Wait 100 ns for global reset to finish
#20;
arst = 0;
#100
din = 35'b01010101010101010101010101010101010;
#100
wren = 1;
#100
din = 35'b01010101010101010101011111111111111;
#100
arst = 1;
// Add stimulus here
end
endmodule
| 7.210848 |
module tb_memory_writeback ();
localparam STEP = 10;
parameter OP_LOAD = 7'b0000011;
parameter OP_STORE = 7'b0100011;
parameter OP_BRANCH = 7'b1100011;
parameter OP_IMM = 7'b0010011;
parameter OP_OP = 7'b0110011;
parameter OP_JUMP = 7'b1101111;
parameter FUNC3_B = 3'b000; // sb, lb
parameter FUNC3_H = 3'b001; // sh, lh
parameter FUNC3_W = 3'b010; // sw, lw,
parameter FUNC3_BU = 3'b100; // lbu
parameter FUNC3_HU = 3'b101; // lhu
reg clk;
reg rst;
reg [6 : 0] opcode;
reg [2 : 0] func3;
reg wb_reg;
reg [4 : 0] rd_num;
reg [31 : 0] alu_out;
wire wb_enable;
wire [4 : 0] wb_rd_num;
wire [31 : 0] wb_rd_data;
wire done;
memory_writeback memory_writeback (
.clk(clk),
.rst(rst),
.opcode(opcode),
.func3(func3),
.wb_reg(wb_reg),
.rd_num(rd_num),
.alu_out(alu_out),
.wb_enable(wb_enable),
.wb_rd_num(wb_rd_num),
.wb_rd_data(wb_rd_data),
.done(done)
);
always begin
clk = 0;
#(STEP / 2);
clk = 1;
#(STEP / 2);
end
initial begin
rst = 0;
rd_num = 5'b00001;
alu_out = 32'h10000;
#(STEP * 10) rst = 1;
#(STEP * 10) rst = 0;
opcode = OP_LOAD;
func3 = FUNC3_B;
wb_reg = 1;
#(STEP)
$display(
"[LB] en:%b, num:%h, data:%h, done:%b", wb_enable, wb_rd_num, wb_rd_data, done
);
opcode = OP_LOAD;
func3 = FUNC3_H;
wb_reg = 1;
#(STEP)
$display(
"[LH] en:%b, num:%h, data:%h, done:%b", wb_enable, wb_rd_num, wb_rd_data, done
);
opcode = OP_LOAD;
func3 = FUNC3_W;
wb_reg = 1;
#(STEP)
$display(
"[LW] en:%b, num:%h, data:%h, done:%b", wb_enable, wb_rd_num, wb_rd_data, done
);
opcode = OP_STORE;
func3 = 0;
wb_reg = 0;
#(STEP)
$display(
"[STORE] en:%b, num:%h, data:%h, done:%b", wb_enable, wb_rd_num, wb_rd_data, done
);
opcode = OP_BRANCH;
func3 = 0;
wb_reg = 0;
#(STEP)
$display(
"[BRANCH] en:%b, num:%h, data:%h, done:%b", wb_enable, wb_rd_num, wb_rd_data, done
);
opcode = OP_IMM;
func3 = 0;
wb_reg = 1;
#(STEP)
$display(
"[IMM] en:%b, num:%h, data:%h, done:%b", wb_enable, wb_rd_num, wb_rd_data, done
);
opcode = OP_OP;
func3 = 0;
wb_reg = 1;
#(STEP)
$display(
"[OP] en:%b, num:%h, data:%h, done:%b", wb_enable, wb_rd_num, wb_rd_data, done
);
opcode = OP_JUMP;
func3 = 0;
wb_reg = 1;
#(STEP)
$display(
"[JUMP] en:%b, num:%h, data:%h, done:%b", wb_enable, wb_rd_num, wb_rd_data, done
);
#(STEP * 100) $stop;
end
endmodule
| 7.484526 |
module tb_memtest ();
parameter fml_depth = 26;
reg sys_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
wire [fml_depth-1:0] fml_adr;
wire fml_we;
wire fml_stb;
reg fml_ack;
reg [63:0] fml_di;
wire [63:0] fml_do;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
memtest #(
.fml_depth(fml_depth),
.csr_addr (4'h0)
) dut (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a (csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.fml_adr(fml_adr),
.fml_we (fml_we),
.fml_stb(fml_stb),
.fml_ack(fml_ack),
.fml_sel(fml_sel),
.fml_di (fml_di),
.fml_do (fml_do)
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x (%d)", address, csr_do, csr_do);
end
endtask
parameter memsize = 32 * 1024 * 1024;
reg [63:0] mem[0:memsize-1];
integer burstcount;
integer addr;
integer we;
initial burstcount = 0;
always @(posedge sys_clk) begin
fml_ack = 1'b0;
if (burstcount == 0) begin
if (fml_stb & (($random % 5) == 0)) begin
burstcount = 1;
addr = fml_adr;
we = fml_we;
//$display("Starting FML burst at address %x, data=%x", addr, fml_do);
fml_di = mem[addr/8];
if (we) mem[addr/8] = fml_do;
fml_ack = 1'b1;
end
end else begin
addr = addr + 8;
burstcount = burstcount + 1;
fml_di = mem[addr/8];
if (we) mem[addr/8] = fml_do;
//$display("Continuing FML burst at address %x, data=%x", addr, fml_do);
if (burstcount == 4) burstcount = 0;
end
end
always begin
sys_rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
fml_di = 64'd0;
fml_ack = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
$dumpfile("memtest.vcd");
$dumpvars(0, dut);
$display("WRITING");
csrwrite(32'h4, 32'd0);
csrwrite(32'h8, 32'd0);
csrwrite(32'hc, 32'd1);
csrwrite(32'h0, 32'd209716);
csrread(32'h0);
while (|csr_do) begin
#10000;
csrread(32'h0);
end
$display("");
$display("READING");
csrwrite(32'h4, 32'd0);
csrwrite(32'h8, 32'd0);
csrwrite(32'hc, 32'd0);
csrwrite(32'h0, 32'd209716);
csrread(32'h0);
while (|csr_do) begin
#10000;
csrread(32'h0);
end
csrread(32'h4); /* error count */
$finish;
end
endmodule
| 7.513725 |
module : tb_mem_interface
* @author : Adaptive & Secure Computing Systems (ASCS) Laboratory
* Copyright (c) 2018 BRISC-V (ASCS/ECE/BU)
*/
module tb_mem_interface ();
reg clk, reset;
reg read, write;
reg [7:0] address;
reg [31:0]in_data;
wire valid, ready;
wire[7:0] out_addr;
wire[31:0]out_data;
reg report;
//mem_interface #(parameter CORE = 0, DATA_WIDTH = 32, INDEX_BITS = 6,
// OFFSET_BITS = 3, ADDRESS_BITS = 20)
mem_interface #(0, 32, 4, 3, 8)U (
clk, reset,
read, write, address, in_data,
out_addr, out_data, valid, ready,
report
);
// Clock generator
always #1 clk = ~clk;
initial begin
$dumpfile ("mem_interface.vcd");
$dumpvars();
clk = 0;
reset = 1;
read = 0;
write = 0;
address = 0;
report = 1;
#10 reset = 0;
$display (" --- Start --- ");
repeat (1) @ (posedge clk);
address <= 0;
in_data <= 32'h0000_0000_0000_0002;
write <= 1'b1;
repeat (1) @ (posedge clk);
address <= 2;
in_data <= 32'h0000_0000_0000_0008;
write <= 1'b1;
repeat (1) @ (posedge clk);
address <= 4;
in_data <= 32'h0000_0000_0000_0002;
write <= 1'b1;
repeat (1) @ (posedge clk);
address <= 6;
in_data <= 32'h0000_0000_0000_0008;
write <= 1'b1;
repeat (1) @ (posedge clk);
write <= 1'b0;
repeat (1) @ (posedge clk);
address <= 0;
read <= 1'b1;
repeat (1) @ (posedge clk);
address <= 4;
read <= 1'b1;
repeat (1) @ (posedge clk);
address <= 8;
read <= 1'b1;
repeat (1) @ (posedge clk);
address <= 2;
read <= 1'b1;
repeat (1) @ (posedge clk);
end
endmodule
| 7.266902 |
module tb_mergeBoard ();
parameter STEP = 20;
reg [79:0] board_in;
reg [1:0] movDir;
wire movable;
wire [79:0] board_after;
mergeBoard mb (
.board_in(board_in),
.movDir(movDir),
.movable(movable),
.board_after(board_after)
);
initial begin
$dumpfile("tb_mergeBoard.vcd");
$dumpvars(0, tb_mergeBoard);
#STEP movDir = 0;
#STEP board_in = {5'd3, {7{5'd0}}, 5'd1, 5'd2, 5'd3, 5'd3, 5'd1, 5'd2, 5'd2, 5'd1};
#STEP showBoardIn;
#STEP showBoardAfter;
#STEP movDir = 1;
#STEP board_in = {5'd3, {7{5'd0}}, 5'd1, 5'd2, 5'd3, 5'd3, 5'd1, 5'd2, 5'd2, 5'd1};
#STEP showBoardIn;
#STEP showBoardAfter;
#STEP movDir = 2;
#STEP board_in = {5'd3, {7{5'd0}}, 5'd1, 5'd2, 5'd3, 5'd3, 5'd1, 5'd2, 5'd2, 5'd1};
#STEP showBoardIn;
#STEP showBoardAfter;
#STEP movDir = 3;
#STEP board_in = {5'd3, {7{5'd0}}, 5'd1, 5'd2, 5'd3, 5'd3, 5'd1, 5'd2, 5'd2, 5'd1};
#STEP showBoardIn;
#STEP showBoardAfter;
$dumpflush;
$finish;
end
task showBoardAfter;
begin
$display("movDir:%d", movDir);
$display("%d %d %d %d", board_after[19:15], board_after[14:10], board_after[9:5],
board_after[4:0]);
$display("%d %d %d %d", board_after[39:35], board_after[34:30], board_after[29:25],
board_after[24:20]);
$display("%d %d %d %d", board_after[59:55], board_after[54:50], board_after[49:45],
board_after[44:40]);
$display("%d %d %d %d", board_after[79:75], board_after[74:70], board_after[69:65],
board_after[64:60]);
end
endtask
task showBoardIn;
begin
$display("movDir:%d", movDir);
$display("%d %d %d %d", board_in[19:15], board_in[14:10], board_in[9:5], board_in[4:0]);
$display("%d %d %d %d", board_in[39:35], board_in[34:30], board_in[29:25], board_in[24:20]);
$display("%d %d %d %d", board_in[59:55], board_in[54:50], board_in[49:45], board_in[44:40]);
$display("%d %d %d %d", board_in[79:75], board_in[74:70], board_in[69:65], board_in[64:60]);
end
endtask
endmodule
| 6.88557 |
module TB_message_collector;
reg clk;
reg reset;
reg start;
reg [31:0] a;
reg [31:0] b;
wire [511:0] message;
MessageCollector U1 (
clk,
reset,
start, // Execution inputs
a,
b, // Data inputs
message // Message output
);
initial begin
clk = 1;
reset = 1;
start = 0;
a = 32'd0;
b = 32'd0;
end
always #100 clk = ~clk;
// For testing purposes, using instructed base message in testbench
// "XXXX Keep your FPGA spinning!", which is 232 bits (29 bytes x 8)
parameter WORD_SIZE = 32;
parameter TOTAL_WORDS = 16;
parameter BASE_MESSAGE = "XXXX Keep your FPGA spinning!";
parameter [WORD_SIZE*TOTAL_WORDS-1:0] MESSAGE = {
BASE_MESSAGE, 152'h0, 4'h8, 60'h0, 32'h00000000, 32'h00000180
};
integer j;
initial begin
// Test changing input with start disabled
for (j = 0; j < TOTAL_WORDS; j = j + 2) begin
#200 reset = 0;
start = 0;
a = MESSAGE[((WORD_SIZE*TOTAL_WORDS-1)-(j*WORD_SIZE))-:WORD_SIZE];
b = MESSAGE[((WORD_SIZE*TOTAL_WORDS-1)-((j+1)*WORD_SIZE))-:WORD_SIZE];
#200 start = 0;
end
// Test sending the message we have defined
for (j = 0; j < TOTAL_WORDS; j = j + 2) begin
#200 reset = 0;
start = 1;
a = MESSAGE[((WORD_SIZE*TOTAL_WORDS-1)-(j*WORD_SIZE))-:WORD_SIZE];
b = MESSAGE[((WORD_SIZE*TOTAL_WORDS-1)-((j+1)*WORD_SIZE))-:WORD_SIZE];
#200 start = 0;
end
// Test the reset
#200 reset = 1;
#200 reset = 0;
// Test sending the message we have defined (again)
for (j = 0; j < TOTAL_WORDS; j = j + 2) begin
#200 reset = 0;
start = 1;
a = MESSAGE[((WORD_SIZE*TOTAL_WORDS-1)-(j*WORD_SIZE))-:WORD_SIZE];
b = MESSAGE[((WORD_SIZE*TOTAL_WORDS-1)-((j+1)*WORD_SIZE))-:WORD_SIZE];
#200 start = 0;
end
// Test sending an override series of bytes
for (j = 0; j < TOTAL_WORDS; j = j + 2) begin
#200 reset = 0;
start = 1;
a = 32'h01234567;
b = 32'h89ABCDEF;
#200 start = 0;
end
end
endmodule
| 6.631377 |
module tb_me_double;
localparam MEM_SW_A = "../memory/memory_sw_A.txt";
localparam MEM_SW_B = "../memory/memory_sw_B.txt";
localparam MEM_SW_C = "../memory/memory_sw_C.txt";
localparam MEM_SW_D = "../memory/memory_sw_D.txt";
localparam MEM_TB_A = "../memory/memory_tb_A.txt";
localparam MEM_TB_B = "../memory/memory_tb_B.txt";
localparam MEM_TB_C = "../memory/memory_tb_C.txt";
localparam MEM_TB_D = "../memory/memory_tb_D.txt";
reg rst_n;
reg clk;
reg req;
wire [15:0] min_sad;
wire [ 4:0] min_mvec_h;
wire [ 4:0] min_mvec_w;
wire ack;
wire [31:0] pel_sw;
wire [31:0] pel_tb;
wire [ 9:0] addr_sw;
wire [ 5:0] addr_tb;
me_double _me_double (
.rst_n (rst_n),
.clk (clk),
.req (req),
.min_sad (min_sad),
.min_mvec({min_mvec_w, min_mvec_h}),
.ack (ack),
// memory access ports
.pel_sw (pel_sw),
.pel_tb (pel_tb),
.addr_sw(addr_sw),
.addr_tb(addr_tb)
);
memory_sw _memory_sw (
.rst_n (rst_n),
.clk (clk),
.addr_a(addr_sw),
.addr_b(12'd0),
.data_a(pel_sw),
.data_b()
);
defparam _memory_sw.MEM_SW_A = MEM_SW_A; defparam _memory_sw.MEM_SW_B = MEM_SW_B;
defparam _memory_sw.MEM_SW_C = MEM_SW_C; defparam _memory_sw.MEM_SW_D = MEM_SW_D;
memory_tb _memory_tb (
.rst_n (rst_n),
.clk (clk),
.addr_a(addr_tb),
.addr_b(8'd0),
.data_a(pel_tb),
.data_b()
);
defparam _memory_tb.MEM_TB_A = MEM_TB_A; defparam _memory_tb.MEM_TB_B = MEM_TB_B;
defparam _memory_tb.MEM_TB_C = MEM_TB_C; defparam _memory_tb.MEM_TB_D = MEM_TB_D;
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_me_double.vcd");
$dumpvars(0, tb_me_double);
end
initial begin
#1 rst_n <= 1'bx;
clk <= 1'bx;
req <= 1'bx;
#(CLK_PERIOD) rst_n <= 1;
#(CLK_PERIOD * 3) rst_n <= 0;
clk <= 0;
req <= 0;
repeat (5) @(posedge clk);
rst_n <= 1;
repeat (3) @(posedge clk);
req <= 1;
while (~ack) @(posedge clk);
$display("motion vector");
$display(" h : %d", min_mvec_h);
$display(" w : %d", min_mvec_w);
$display(" sad: %d", min_sad);
repeat (10) @(posedge clk);
req <= 0;
repeat (10) @(posedge clk);
$finish(2);
end
endmodule
| 6.524799 |
module tb_micron_controller_init ();
parameter BUS_WIDTH = 32;
parameter CTRL_WIDTH = 8;
reg clk50MHz;
wire [BUS_WIDTH-1:0] bus;
wire [CTRL_WIDTH-1:0] ctrl;
wire [7:0] req;
assign req[6:0] = 0;
wire [ 7:0] ack;
wire [22:0] BCR_CONFIG;
assign BCR_CONFIG = {
3'b000, // [22:20] Reserved, must be 0
2'b10, // [19:18] Register select (BCR)
2'b00, // [17:16] Reserved, must be 0
1'b0, // [15:15] Operating mode (Synchronous)
1'b1, // [14:14] Initial latency (Fixed)
3'b011, // [13:11] Latency counter (Code 3)
1'b1, // [10:10] WAIT polarity (Active high)
1'b0, // [9:9] Reserved, must be set to 0
1'b1, // [8:8] Wait config (Asserted one cycle before delay)
2'b00, // [7:6] Reserved, must be set to 0
2'b01, // [5:4] Drive strength (1/2 strength, this is default)
1'b1, // [3:3] Burst wrap (No wrap)
3'b001 // [2:0] Burst length (4 words)
};
//Signals to memory
wire [22:0] maddr;
wire [15:0] mdata;
assign mdata = (moe_L == 0) ? BCR_CONFIG : 'bz;
wire moe_L;
wire mwe_L;
wire madv_L;
wire mclk;
wire mub_L;
wire mlb_L;
wire mce_L;
wire mcre;
wire ready;
wire [BUS_WIDTH-1:0] slave_out;
wire [CTRL_WIDTH-1:0] slave_ctrl_out;
reg reset;
micron_controller sramctrl (
.clk50MHz(clk50MHz),
.bus_data_in(0),
.bus_data_out(slave_out),
.bus_ctrl_in(0),
.bus_ctrl_out(slave_ctrl_out),
.bus_ack(0),
.ready(ready),
.reset_external(reset),
.mem_data(mdata),
.maddr(maddr),
.moe_L(moe_L),
.mwe_L(mwe_L),
.madv_L(madv_L),
.mclk(mclk),
.mub_L(mub_L),
.mlb_L(mlb_L),
.mce_L(mce_L),
.mcre(mcre),
.mwait(0)
);
initial begin
clk50MHz <= 0;
reset <= 1;
#30 reset <= 0;
#500 reset <= 1;
#30 reset <= 0;
end
always begin
#10 clk50MHz = ~clk50MHz;
end
endmodule
| 7.50232 |
module tb_microstep_pwm_control ();
localparam RATE = 1000.0 / 125.0;
initial begin
$dumpfile("tb_microstep_pwm_control.vcd");
$dumpvars(0, tb_microstep_pwm_control);
#10000000 $finish;
end
reg reset = 1'b1;
initial #(RATE * 100) reset = 1'b0;
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
parameter PAHSE_WIDTH = 16;
parameter Q_WIDTH = 12;
parameter OUTPUT_WIDTH = PAHSE_WIDTH - Q_WIDTH;
parameter MICROSTEP_WIDTH = 8;
wire microstep_en = 1'b1;
wire nanostep_en = 1'b1;
wire asyc_update_en = 1'b0;
wire [ PAHSE_WIDTH-1:0] phase;
wire update;
wire [OUTPUT_WIDTH-1:0] out_val;
microstep_pwm_control #(
.PAHSE_WIDTH (PAHSE_WIDTH),
.Q_WIDTH (Q_WIDTH),
.OUTPUT_WIDTH (OUTPUT_WIDTH),
.MICROSTEP_WIDTH(MICROSTEP_WIDTH)
) microstep_pwm_control (
.reset(reset),
.clk (clk),
.microstep_en (microstep_en),
.nanostep_en (nanostep_en),
.asyc_update_en(asyc_update_en),
.phase (phase),
.update(update),
.out_val(out_val)
);
reg [PAHSE_WIDTH-1:0] reg_phase;
always @(posedge clk) begin
if (reset) begin
reg_phase <= 0;
end else begin
if (update) begin
reg_phase <= reg_phase + 7;
end
end
end
assign phase = reg_phase;
endmodule
| 6.970791 |
module micro_sim_tb ();
parameter GPIO_D = `GPIO_D;
parameter N = 4;
parameter IMG_SIZE = 439;
localparam PATH = "/home/ivan/XilinxProjects/2dconv-FPGA/src/TEST/MEM_CONV_MCU/";
localparam FILENAME = "mem0";
localparam OUTFNAME = "out_mem0";
wire [GPIO_D-1:0] gpio_i_data_tri_i;
wire o_led;
reg CLK100MHZ;
wire [GPIO_D-1:0] gpio_o_data_tri_o;
reg [ 23:0] i_GPIOdata;
reg [ 2:0] i_GPIOctrl;
reg i_GPIOvalid;
reg rst;
integer i, j, k, aux, aux_name;
integer file[0:N+1];
assign gpio_o_data_tri_o = {i_GPIOctrl, i_GPIOvalid, 3'b0, i_GPIOdata, rst};
initial begin
CLK100MHZ = 1'b0;
i_GPIOdata = 24'b0;
i_GPIOctrl = 3'b0;
i_GPIOvalid = 1'b0;
rst = 1'b0;
//RESET
#100 rst = 1'b1;
#100 rst = 1'b0;
//CARGO KERNEL
#200 i_GPIOctrl = 3'b000;
i_GPIOdata = 24'h002000;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
#100 i_GPIOdata = 24'h208020;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
#100 i_GPIOdata = 24'h002000;
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
//CARGO IMAGE LENGTH
#500 i_GPIOctrl = 3'b001;
i_GPIOdata = IMG_SIZE;
for (k = 0; k < 2; k = k + 1) begin
if (k == 0) aux = N + 2;
else aux = N;
//CARGO IMAGEN EN MEMORIA
#500 i_GPIOctrl = 3'b010;
for (j = 0; j < aux; j = j + 1) begin
if (k == 0) file[j] = $fopen({PATH, FILENAME + j, ".txt"}, "r");
else file[j] = $fopen({PATH, FILENAME + N + 2 + j + aux * (k - 1), ".txt"}, "r");
if (!file[j]) begin
$display("Error abriendo archivo");
$stop;
end else begin
for (i = 0; i <= IMG_SIZE; i = i + 1) begin
if (i == IMG_SIZE && j == aux - 1) #100 i_GPIOctrl = 100; //ultimo dato a cargar
#100 $fscanf(file[j], "%h", i_GPIOdata);
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
end
end
end
for (j = 0; j < N + 2; j = j + 1) begin
$fclose(file[j]);
end
wait (o_led);
#100 i_GPIOctrl = 011;
for (j = 0; j < N; j = j + 1) begin
file[j] = $fopen({PATH, OUTFNAME + j + k * N, ".txt"}, "w");
end
j = 0;
for (i = 0; i < N * (IMG_SIZE - 1); i = i + 1) begin
if (i % (IMG_SIZE - 1) == 0 && i > IMG_SIZE - 2) begin
j = j + 1;
$display("Paso a memoria %d", j);
end
$fwrite(file[j], "%h\n", gpio_i_data_tri_i[12:0]);
#100 i_GPIOvalid = 1'b1;
#100 i_GPIOvalid = 1'b0;
end
for (j = 0; j < N; j = j + 1) begin
$fclose(file[j]);
end
end
$finish;
end
always #2 CLK100MHZ = ~CLK100MHZ;
micro_sim #(
.N(N)
) u_micro (
.gpio_o_data_tri_o(gpio_o_data_tri_o),
.gpio_i_data_tri_i(gpio_i_data_tri_i),
.o_led(o_led),
.CLK100MHZ(CLK100MHZ)
);
endmodule
| 6.639304 |
module tb_minimac ();
/* 100MHz system clock */
reg sys_clk;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
/* 25MHz RX clock */
reg phy_rx_clk;
initial phy_rx_clk = 1'b0;
always #20 phy_rx_clk = ~phy_rx_clk;
/* 25MHz TX clock */
reg phy_tx_clk;
initial phy_tx_clk = 1'b0;
always #20 phy_tx_clk = ~phy_tx_clk;
reg sys_rst;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
reg [3:0] phy_rx_data;
reg phy_dv;
reg phy_rx_er;
wire phy_tx_en;
wire [3:0] phy_tx_data;
wire irq_rx;
wire irq_tx;
minimac2 #(
.csr_addr(4'h0)
) ethernet (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a (csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i (wb_we_i),
.wb_sel_i(4'hf),
.wb_ack_o(wb_ack_o),
.irq_rx(irq_rx),
.irq_tx(irq_tx),
.phy_tx_clk(phy_tx_clk),
.phy_tx_data(phy_tx_data),
.phy_tx_en(phy_tx_en),
.phy_tx_er(),
.phy_rx_clk(phy_rx_clk),
.phy_rx_data(phy_rx_data),
.phy_dv(phy_dv),
.phy_rx_er(phy_rx_er),
.phy_col(),
.phy_crs(),
.phy_mii_clk(),
.phy_mii_data()
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("Configuration Write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("Configuration Read : %x=%x", address, csr_do);
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while (~wb_ack_o) begin
i = i + 1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while (~wb_ack_o) begin
i = i + 1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
integer cycle;
initial cycle = 0;
always @(posedge phy_rx_clk) begin
cycle <= cycle + 1;
phy_rx_er <= 1'b0;
phy_rx_data <= cycle;
if (phy_dv) begin
//$display("rx: %x", phy_rx_data);
if ((cycle % 16) == 13) begin
phy_dv <= 1'b0;
//$display("** stopping transmission");
end
end else begin
if ((cycle % 16) == 15) begin
phy_dv <= 1'b1;
//$display("** starting transmission");
end
end
end
always @(posedge phy_tx_clk) begin
if (phy_tx_en) $display("tx: %x", phy_tx_data);
end
initial begin
/* Reset / Initialize our logic */
sys_rst = 1'b1;
csr_a = 14'd0;
csr_di = 32'd0;
csr_we = 1'b0;
phy_dv = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
csrwrite(32'h00, 0);
csrwrite(32'h08, 1);
wbwrite(32'h1000, 32'h12345678);
wbread(32'h1000);
csrwrite(32'h18, 10);
csrwrite(32'h10, 1);
#5000;
csrread(32'h08);
csrread(32'h0C);
csrread(32'h10);
csrread(32'h14);
wbread(32'h0000);
wbread(32'h0004);
wbread(32'h0008);
wbread(32'h0800);
wbread(32'h0804);
wbread(32'h0808);
$finish;
end
endmodule
| 7.256816 |
module tb_minority ();
reg [2:0] test_vector;
wire y;
minority uut (
.a(test_vector[2]),
.b(test_vector[1]),
.c(test_vector[0]),
.y(y)
);
integer i;
initial begin
test_vector = 3'b000;
#5;
$display(test_vector, y);
for (i = 0; i < 7; i = i + 1) begin
assign test_vector = test_vector + 1;
#5;
$display(test_vector, " ", y);
end
end
endmodule
| 6.578721 |
module tb_minuse ();
reg run_code, clk, in_flag, out_flag;
reg [ 7:0] in;
reg [11:0] address;
reg [15:0] code;
wire fgo, fgi;
wire [ 7:0] out;
wire [15:0] te;
mano_cpu mc (
run_code,
clk,
in_flag,
out_flag,
in,
address,
code,
fgo,
fgi,
out,
te
);
initial begin
clk = 1'b1;
run_code = 1'b0;
address = 12'h100;
code = 16'h2107;
#2 address = 12'h101;
code = 16'h7200;
#2 address = 12'h102;
code = 16'h7020;
#2 address = 12'h103;
code = 16'h1106;
#2 address = 12'h104;
code = 16'h3108;
#2 address = 12'h105;
code = 16'h7001;
#2 address = 12'h106;
code = 16'h0053;
#2 address = 12'h107;
code = 16'hffe9;
#2 address = 12'h108;
code = 16'h0000;
#3 run_code = 1'b1;
#20;
$stop();
end
always #1 clk = ~clk;
endmodule
| 6.705289 |
module: mips_16
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Testbench Verilog code for 16 bit single cycle MIPS CPU
module tb_mips16;
// Inputs
reg clk;
reg reset;
// Outputs
wire [15:0] pc_out;
wire [15:0] alu_result;//,reg3,reg4;
// Instantiate the Unit Under Test (UUT)
mips_16 uut (
.clk(clk),
.reset(reset),
.pc_out(pc_out),
.alu_result(alu_result)
//.reg3(reg3),
// .reg4(reg4)
);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
// Initialize Inputs
//$monitor ("register 3=%d, register 4=%d", reg3,reg4);
reset = 1;
// Wait 100 ns for global reset to finish
#100;
reset = 0;
#300;
$finish;
// Add stimulus here
end
endmodule
| 6.692025 |
module TBMipsTestLoopJalSim ();
reg clk, rst;
MIPS cpu (
.clk(clk),
.rst(rst)
);
integer i = 0;
integer cnt = 0;
initial begin
$readmemh("C:/Users/24312/Desktop/tiny-CPU/dat/mipstestloopjal_sim.dat",
cpu.im.instruction_memory);
end
initial clk = 0;
initial begin
rst = 0;
#5 rst = 1;
#5 rst = 0;
end
always begin
#5 clk = ~clk;
if (clk) begin
$display("PC = 0x%8h, instruction = 0x%8h", cpu.PC, cpu.AnInstruction);
$display("");
cnt = cnt + 1;
end
if (cnt == 30) begin
ShowRegFile;
$display("m[0x%2X] = %d", 80, cpu.dm.dataMem[80/4]);
$display("m[0x%2X] = %d", 84, cpu.dm.dataMem[84/4]);
$stop();
end
end
task ShowRegFile;
begin
$display("R[00-07]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", 0, cpu.rf.rf[1],
cpu.rf.rf[2], cpu.rf.rf[3], cpu.rf.rf[4], cpu.rf.rf[5], cpu.rf.rf[6], cpu.rf.rf[7]);
$display("R[08-15]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[8],
cpu.rf.rf[9], cpu.rf.rf[10], cpu.rf.rf[11], cpu.rf.rf[12], cpu.rf.rf[13],
cpu.rf.rf[14], cpu.rf.rf[15]);
$display("R[16-23]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[16],
cpu.rf.rf[17], cpu.rf.rf[18], cpu.rf.rf[19], cpu.rf.rf[20], cpu.rf.rf[21],
cpu.rf.rf[22], cpu.rf.rf[23]);
$display("R[24-31]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[24],
cpu.rf.rf[25], cpu.rf.rf[26], cpu.rf.rf[27], cpu.rf.rf[28], cpu.rf.rf[29],
cpu.rf.rf[30], cpu.rf.rf[31]);
end
endtask
endmodule
| 6.533401 |
module TBMipsTestLoop ();
reg clk, rst;
MIPS cpu (
.clk(clk),
.rst(rst)
);
integer i = 0;
integer cnt = 0;
initial begin
$readmemh("C:/Users/24312/Desktop/tiny-CPU/dat/mipstestloop_sim.dat",
cpu.im.instruction_memory);
end
initial clk = 0;
initial begin
rst = 0;
#5 rst = 1;
#5 rst = 0;
end
always begin
#5 clk = ~clk;
if (clk) begin
$display("PC = 0x%8h, instruction = 0x%8h", cpu.PC, cpu.AnInstruction);
$display("");
cnt = cnt + 1;
end
if (cnt == 40) begin
ShowRegFile;
$display("m[0x%2X] = %d", 80, cpu.dm.dataMem[80/4]);
$display("m[0x%2X] = %d", 84, cpu.dm.dataMem[84/4]);
$stop();
end
end
task ShowRegFile;
begin
$display("R[00-07]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", 0, cpu.rf.rf[1],
cpu.rf.rf[2], cpu.rf.rf[3], cpu.rf.rf[4], cpu.rf.rf[5], cpu.rf.rf[6], cpu.rf.rf[7]);
$display("R[08-15]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[8],
cpu.rf.rf[9], cpu.rf.rf[10], cpu.rf.rf[11], cpu.rf.rf[12], cpu.rf.rf[13],
cpu.rf.rf[14], cpu.rf.rf[15]);
$display("R[16-23]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[16],
cpu.rf.rf[17], cpu.rf.rf[18], cpu.rf.rf[19], cpu.rf.rf[20], cpu.rf.rf[21],
cpu.rf.rf[22], cpu.rf.rf[23]);
$display("R[24-31]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", cpu.rf.rf[24],
cpu.rf.rf[25], cpu.rf.rf[26], cpu.rf.rf[27], cpu.rf.rf[28], cpu.rf.rf[29],
cpu.rf.rf[30], cpu.rf.rf[31]);
end
endtask
endmodule
| 6.533401 |
module tb_mipstest_pipelinedloop ();
reg clk, rst;
CPU cpu (
.clk(clk),
.rst(rst)
);
wire [31:0] p1_IF_PC = cpu.IF_PC;
wire [31:0] p2_ID_PC = cpu.ID_PC;
wire [31:0] p3_EX_PC = cpu.EX_PC;
wire [31:0] p4_MEM_PC = cpu.MEM_PC;
wire [31:0] p5_WB_PC = cpu.WB_PC;
integer _cnt = 0;
initial begin
//$readmemh("dat_mipstestloopjal_sim.txt", cpu.insMem.innerIM.ROM);
$readmemh(
"C:/Users/zhb/Desktop/ComputerOrgainzationExperiment/dat/dat_mipstest_pipelinedloop.txt",
cpu.insMem.innerIM.ROM);
//$monitor("PC = 0x%8h, instruction = 0x%8h", cpu.PC, cpu.inst);
_cnt = 0;
clk = 0;
end
initial begin
rst = 1;
#18 rst = 0;
end
always begin
#5 clk = ~clk;
if (clk) _cnt = _cnt + 1;
if (_cnt == (`INST_NUM + 20) * 5) begin
printRegFile;
printDataMem;
$stop();
end
end
task printRegFile;
begin
$display("r[00-07]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X", 0,
cpu.regFile.rf[1], cpu.regFile.rf[2], cpu.regFile.rf[3], cpu.regFile.rf[4],
cpu.regFile.rf[5], cpu.regFile.rf[6], cpu.regFile.rf[7]);
$display("r[08-15]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X",
cpu.regFile.rf[8], cpu.regFile.rf[9], cpu.regFile.rf[10], cpu.regFile.rf[11],
cpu.regFile.rf[12], cpu.regFile.rf[13], cpu.regFile.rf[14], cpu.regFile.rf[15]);
$display("r[16-23]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X",
cpu.regFile.rf[16], cpu.regFile.rf[17], cpu.regFile.rf[18], cpu.regFile.rf[19],
cpu.regFile.rf[20], cpu.regFile.rf[21], cpu.regFile.rf[22], cpu.regFile.rf[23]);
$display("r[24-31]=0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X, 0x%8X",
cpu.regFile.rf[24], cpu.regFile.rf[25], cpu.regFile.rf[26], cpu.regFile.rf[27],
cpu.regFile.rf[28], cpu.regFile.rf[29], cpu.regFile.rf[30], cpu.regFile.rf[31]);
end
endtask
task printDataMem;
begin
$display("m[80/4] = %d", cpu.dataMem.innerDM.dmem[80/4]);
$display("m[84/4] = %d", cpu.dataMem.innerDM.dmem[84/4]);
end
endtask
endmodule
| 6.559166 |
module tb_mips_bard;
// The `assert` module is defined in the same file.
// Instantiate the `mips_bard` module.
mips_bard mips_bard (
.clk(clk),
.rst(rst),
.instruction(instruction),
.pc(pc),
.data_out(data_out)
);
// Clock signal.
reg clk;
always #1 clk = ~clk;
// Reset signal.
reg rst;
initial begin
rst = 1;
#10 rst = 0;
end
// Instruction signals.
reg [31:0] instruction;
initial begin
instruction = 32'h10000000; // R-type instruction
#10 instruction = 32'h20000000; // I-type instruction
#10 instruction = 32'h30000000; // J-type instruction
end
// Expected outputs.
reg [31:0] expected_pc;
reg [31:0] expected_data_out;
initial begin
expected_pc = 32'h10000004;
expected_data_out = 32'h0;
end
// Assert that the outputs match the expected values.
assert(pc == expected_pc);
assert(data_out == expected_data_out);
endmodule
| 7.965727 |
module tb_mips_cpu ();
reg rst, clk;
wire [31:0] out_pc;
wire [15:0] out_result;
mips_cpu m_cpu (
rst,
clk,
out_pc,
out_result
);
initial begin
rst = 0;
#33;
rst = 1;
end
initial begin
clk = 0;
forever #5 clk = ~clk;
end
endmodule
| 6.93793 |
module tb_miriscv_top ();
parameter HF_CYCLE = 2.5; // 200 MHz clock
parameter RST_WAIT = 10; // 10 ns reset
parameter RAM_SIZE = 1024; // in 32-bit words
// clock, reset
reg clk;
reg rst_n;
miriscv_top #(
.RAM_SIZE (RAM_SIZE),
.RAM_INIT_FILE("C:\\altera\\13.0sp1\\Projects\\Riscv_Processor\\data\\data.txt")
) dut (
.clk_i (clk),
.rst_n_i(rst_n)
);
initial begin
clk = 1'b0;
rst_n = 1'b0;
#RST_WAIT;
rst_n = 1'b1;
end
always begin
#HF_CYCLE;
clk = ~clk;
end
endmodule
| 7.796864 |
module tb_mm2s ();
reg clk = 1;
always @(*) clk <= #2 ~clk;
reg [15:0] resetn_reg = 0;
wire resetn;
wire send_data;
always @(posedge clk) resetn_reg <= {resetn_reg[14:0], 1'b1};
assign resetn = resetn_reg[12];
assign send_data = resetn_reg[15];
reg [31:0] reg_data;
initial begin
wait (send_data == 1);
@(posedge clk);
axilite_wr(16'h10, 32'h4000); //mm2s
axilite_wr(16'h18, 32'd6);
axilite_wr(16'h00, 32'h1); //ap start
wait (axis_out_tvalid && axis_out_tready && axis_out_tlast == 1'b1);
@(posedge clk);
axilite_wr(16'h10, 32'h4200); //mm2s
axilite_wr(16'h18, 32'd1028);
axilite_wr(16'h00, 32'h1); //ap start
end
wire [127:0] axis_out_tdata;
wire [ 15:0] axis_out_tkeep;
wire axis_out_tlast;
wire axis_out_tvalid;
reg axis_out_tready = 1'b1;
reg [ 15:0] s_axi_araddr = 0;
wire s_axi_arready;
reg s_axi_arvalid = 0;
wire [ 31:0] s_axi_rdata;
reg s_axi_rready = 1;
wire [ 1:0] s_axi_rresp;
wire s_axi_rvalid;
reg [ 15:0] s_axi_awaddr = 0;
wire s_axi_awready;
reg s_axi_awvalid = 0;
reg s_axi_bready = 1;
wire s_axi_bresp;
wire s_axi_bvalid;
reg [ 31:0] s_axi_wdata = 0;
wire s_axi_wready;
reg [ 3:0] s_axi_wstrb = 0;
reg s_axi_wvalid = 0;
design_1 design_1_i (
.axis_out_tdata(axis_out_tdata),
.axis_out_tkeep(axis_out_tkeep),
.axis_out_tlast(axis_out_tlast),
.axis_out_tready(axis_out_tready),
.axis_out_tvalid(axis_out_tvalid),
.clk(clk),
.resetn(resetn),
.s_axi_control_araddr(s_axi_araddr),
.s_axi_control_arready(s_axi_arready),
.s_axi_control_arvalid(s_axi_arvalid),
.s_axi_control_awaddr(s_axi_awaddr),
.s_axi_control_awready(s_axi_awready),
.s_axi_control_awvalid(s_axi_awvalid),
.s_axi_control_bready(s_axi_bready),
.s_axi_control_bresp(s_axi_bresp),
.s_axi_control_bvalid(s_axi_bvalid),
.s_axi_control_rdata(s_axi_rdata),
.s_axi_control_rready(s_axi_rready),
.s_axi_control_rresp(s_axi_rresp),
.s_axi_control_rvalid(s_axi_rvalid),
.s_axi_control_wdata(s_axi_wdata),
.s_axi_control_wready(s_axi_wready),
.s_axi_control_wstrb(s_axi_wstrb),
.s_axi_control_wvalid(s_axi_wvalid)
);
//Task to write given data at the given address using axilite interface
task axilite_wr;
input [15:0] address;
input [31:0] data;
begin
@(posedge clk) s_axi_awaddr <= address;
s_axi_awvalid <= 1'b1;
wait ((s_axi_awvalid && s_axi_awready) == 1);
@(posedge clk) s_axi_awvalid <= 1'b0;
s_axi_wdata <= data;
s_axi_wstrb <= 4'hF;
s_axi_wvalid <= 1'b1;
wait ((s_axi_wvalid && s_axi_wready) == 1);
@(posedge clk) s_axi_wvalid <= 1'b0;
wait ((s_axi_bvalid && s_axi_bready) == 1);
@(posedge clk);
end
endtask
endmodule
| 7.906907 |
module tb_MM_control ();
reg Start;
reg clk, rst;
wire result_en, control;
wire [3:0] addr_x, addr_A, addr_P;
MM_control DUT (
.Start(Start),
.clk(clk),
.rst(rst),
.result_en(result_en),
.control(control),
.addr_x(addr_x),
.addr_A(addr_A),
.addr_P(addr_P)
);
/*iverilog*/
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, tb_MM_control);
end
/*iverilog*/
always begin
#100 clk = 0;
#100 clk = 1;
end
initial begin
rst = 1;
#1000 rst = 0;
Start = 1;
#10000 $finish;
end
endmodule
| 6.504637 |
module: Modificacion_Ciclo_Trabajo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_Modificador_ciclo_trabajo;
// Inputs
reg clk_100MHz;
reg clk_de_trabajo;
reg rst;
reg up;
reg down;
reg func_select;
reg chip_select;
// Outputs
wire signal_out;
wire [3:0] ciclo_actual;
// Instantiate the Unit Under Test (UUT)
Modificacion_Ciclo_Trabajo uut (
.clk_100MHz(clk_100MHz),
.clk_de_trabajo(clk_de_trabajo),
.rst(rst),
.up(up),
.down(down),
.func_select(func_select),
.chip_select(chip_select),
.signal_out(signal_out),
.ciclo_actual(ciclo_actual)
);
initial begin
// Initialize Inputs
clk_100MHz = 0;
clk_de_trabajo = 0;
rst = 0;
up = 0;
down = 0;
func_select = 0;
chip_select = 0;
// Wait 100 ns for global reset to finish
#10;
rst=1;
#10
rst=0;
#10
up=1;
//#2
/*
up=0;
#70
down=1;
*/
// Add stimulus here
end
always #10 clk_100MHz = ~clk_100MHz;
always #60 clk_de_trabajo = ~clk_de_trabajo;
endmodule
| 8.169432 |
module_stereo_dac_output.v
// Description: Test bench for interpolating stereo sigma-delta DAC
// -----------------------------------------------------------------------------
module tb_module_i2s();
localparam CLK_FREQ = 100_000_000;
localparam SAMPLE_WIDTH = 16;
localparam SAMPLE_RATE = 48000;
localparam SAMPLE_FREQ = SAMPLE_RATE * SAMPLE_WIDTH * 2;
localparam SAMPLE_NCLKS = CLK_FREQ / SAMPLE_FREQ;
localparam SAMPLE_NCLKS_HALF = SAMPLE_NCLKS / 2;
reg clk;
reg reset;
reg bclk;
reg lrclk;
reg adcda;
reg [SAMPLE_WIDTH-1:0] left_in;
reg [SAMPLE_WIDTH-1:0] right_in;
wire [SAMPLE_WIDTH-1:0] left_out;
wire [SAMPLE_WIDTH-1:0] right_out;
wire dataready;
wire bclk_s;
wire lrclk_s;
wire dacda;
// dut
i2s #(SAMPLE_WIDTH) dut (
.clk (clk ),
.reset (reset ),
.bclk (bclk ),
.lrclk (lrclk ),
.adcda (adcda ),
.left_in (left_in ),
.right_in (right_in ),
.left_out (left_out ),
.right_out (right_out ),
.dataready (dataready ),
.bclk_s (bclk_s ),
.lrclk_s (lrclk_s ),
.dacda (dacda )
);
initial $timeformat(-9, 0, " ns", 0);
always begin
#5;
clk <= ~clk;
end
initial begin
clk <= 0;
reset <= 1;
repeat (100) @(posedge clk);
reset <= 0;
end
initial begin
bclk <= 0;
lrclk <= 0;
adcda <= 0;
@(posedge clk);
while (reset) @(posedge clk);
bclk <= 0;
lrclk <= 0;
adcda <= 0;
forever begin
repeat (2) begin
repeat (SAMPLE_WIDTH+5) begin
repeat (SAMPLE_NCLKS_HALF) @(posedge clk);
bclk <= 1'b1;
repeat (SAMPLE_NCLKS_HALF) @(posedge clk);
bclk <= 1'b0;
adcda <= $random % 2;
end
lrclk <= ~lrclk;
end
repeat (1000) @(posedge clk);
end
end
initial begin
left_in <= 0;
right_in <= 0;
@(posedge clk);
while (reset) @(posedge clk);
repeat (SAMPLE_NCLKS) @(posedge clk);
left_in <= $random();
right_in <= $random();
end
endmodule
| 6.674981 |
module_name.v //[文件名小写]
// Created On : 2021-05-21
// Version : V 1.0
// Author : Rongye
// Description :
// Modification :
//
//======================================================================================================
module tb_MODULE_NAME;
//---------------------------------------< Parameter >----------------------------------------------
parameter PERIOD = 10 ;//[时钟周期设置，默认为100MHz]
parameter N = 2 ;
//---------------------------------------< Port Name >----------------------------------------------
// INPUTS
reg Clk ;
reg rst_n ;
reg ena ;
reg [N-1:0] Din ;
// OUTPUTS
wire Dout ;
//---------------------------------------< Clock block >--------------------------------------------
initial begin
forever #(PERIOD/2) Clk=~Clk;
end
//---------------------------------------< Reset block >--------------------------------------------
initial begin //[初始复位]
#(PERIOD*1) reset_1;
end
task reset_1; //[任务：复位一个时钟]
begin
rst_n = 0;
#(PERIOD*1)
rst_n = 1;
end
endtask
//---------------------------------------< Module Instance >----------------------------------------
MODULE_NAME #(
.N (N )
)
u_MODULE_NAME (
.Clk (Clk ),
.rst_n (rst_n ),
.ena (ena ),
.Din (Din [N-1:0] ),
.Dout (Dout )
);
//---------------------------------------< Design Input >----------------------------------------
initial begin
// Initial data in
Din = 'd0;
// Test case 1
#(PERIOD*10)
Din = 'd1;
#(PERIOD*1)
Din = 'd2;
#(PERIOD*1)
Din = 'd3;
#(PERIOD*1)
Din = 'd0;
#(PERIOD*1)
reset_1;
// Test case 2
#(PERIOD*10)
Din = 'd0;
#(PERIOD*1)
Din = 'd2;
#(PERIOD*1)
Din = 'd1;
#(PERIOD*1)
Din = 'd3;
#(PERIOD*1)
reset_1;
// Test case
// ...
$stop;
end
endmodule
| 8.2186 |
module tb_Motherboard;
reg clk;
reg rst;
reg [15:0] switches;
wire [15:0] led;
integer I;
integer K;
Motherboard #(
.CLOCK_DIVIDER(1)
) DUT (
.clk100Mhz(clk),
.rst (rst),
.switches (switches),
.led (led)
);
task tick;
begin
clk = 1'b0;
#5;
clk = 1'b1;
#5;
end
endtask
initial begin
switches = 0;
rst = 1'b0;
#1;
rst = 1'b1;
#1;
rst = 1'b0;
for (I = 32'h9E20; I < 2 ** 16 - 1; I = I + 1) begin
for (K = 0; K < 16; K = K + 1) begin
tick;
end
switches = I;
if (led == 0) begin
switches = 0;
$stop;
end
end
$finish;
end
endmodule
| 6.969386 |
module: top_mp
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mp;
// Inputs
reg clk;
reg rst;
// Instantiate the Unit Under Test (UUT)
top_mp uut (
.clk(clk),
.rst(rst)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
| 8.791186 |
module tb_mc_ctrl ();
reg clk;
reg rstn;
reg ena;
reg [5:0] ID_from_Host;
reg [5:0] Tag_from_Bus;
wire Ready_from_PE;
reg Enable_from_Bus;
reg [31:0] value_from_Bus;
reg weight_wea_from_Host;
reg ifmap_wea_from_Host;
reg psum_wea_from_Host;
wire Enable_to_PE;
wire Ready_to_Bus;
wire [31:0] value_to_PE;
always #5 clk = ~clk;
initial begin
weight_wea_from_Host = 0;
ifmap_wea_from_Host = 0;
psum_wea_from_Host = 0;
clk = 0;
rstn = 1;
ID_from_Host = 30;
Tag_from_Bus = 0;
value_from_Bus = 0;
Enable_from_Bus = 0;
#1;
rstn = 0;
#1;
rstn = 1;
ena = 1;
Enable_from_Bus = 1;
repeat (5) @(posedge clk);
Tag_from_Bus = 30;
value_from_Bus = 1;
repeat (5) @(posedge clk);
ID_from_Host = 33;
value_from_Bus = 1;
repeat (3) @(posedge clk);
Tag_from_Bus = 33;
repeat (5) @(posedge clk);
repeat (5) begin
@(posedge clk) begin
value_from_Bus = value_from_Bus + 1;
end
end
;
value_from_Bus = 1;
weight_wea_from_Host = 1;
repeat (5) begin
@(posedge clk) begin
value_from_Bus = value_from_Bus + 1;
end
end
;
weight_wea_from_Host = 0;
ID_from_Host = 30;
Tag_from_Bus = 40;
repeat (10) @(posedge clk);
Tag_from_Bus = 30;
ifmap_wea_from_Host = 1;
value_from_Bus = 1;
repeat (35) begin
@(posedge clk) begin
value_from_Bus = value_from_Bus + 1;
end
end
;
ifmap_wea_from_Host = 0;
repeat (100) @(posedge clk);
$finish;
end
multicast_ctrl tb (
clk,
rstn,
ID_from_Host,
Tag_from_Bus,
Ready_from_PE,
Enable_from_Bus,
value_from_Bus,
weight_wea_from_Host,
ifmap_wea_from_Host,
psum_wea_from_Host,
weight_wea_to_PE,
ifmap_wea_to_PE,
psum_wea_to_PE,
Enable_to_PE,
Ready_to_Bus,
value_to_PE
);
pe pe_tb (
clk,
rstn,
ena,
weight_wea_to_PE,
ifmap_wea_to_PE,
psum_wea_to_PE,
value_to_PE,
output_Psum,
Ready_from_PE
);
endmodule
| 6.667301 |
module tb_multiplexer ();
localparam RATE = 1000.0 / 200.0;
initial begin
$dumpfile("tb_multiplexer.vcd");
$dumpvars(0, tb_multiplexer);
#100000;
$finish;
end
reg clk = 1'b1;
always #(RATE / 2.0) clk = ~clk;
reg reset = 1'b1;
initial #(RATE * 100.5) reset = 1'b0;
parameter SEL_WIDTH = 4;
parameter DATA_WIDTH = 16;
reg [ SEL_WIDTH-1:0] sel;
reg [DATA_WIDTH-1:0] data;
always @(posedge clk) begin
if (reset) begin
sel <= 0;
data <= 0;
end else begin
sel <= {$random()};
data <= {$random()};
end
end
wire result0;
wire result1;
wire result_ok = (result0 == result1);
jelly_multiplexer16 #(
.DEVICE("RTL")
) i_multiplexer16_rtl (
.o(result0),
.i(data),
.s(sel)
);
jelly_multiplexer16 #(
.DEVICE("7SERIES")
) i_multiplexer16_lut (
.o(result1),
.i(data),
.s(sel)
);
endmodule
| 6.829662 |
module tb_multiplexer ();
reg [3:0] w;
reg [1:0] sel;
wire [3:0] y;
multiplexer4x1 test_multiplexer4x1 (
.w (w),
.sel(sel),
.y (y)
);
initial begin
sel <= 2'b00;
w <= 4'b0000;
#10;
w <= 4'b0001;
#10;
w <= 4'b0010;
sel <= 2'b01;
#10;
w <= 4'b0011;
#10;
w <= 4'b0100;
#10;
w <= 4'b0101;
sel <= 2'b11;
#10;
w <= 4'b0110;
#10;
w <= 4'b0111;
#10;
w <= 4'b1000;
#10;
w <= 4'b1001;
sel <= 2'b01;
#10;
w <= 4'b1010;
#10;
w <= 4'b1011;
#10;
w <= 4'b1100;
sel <= 2'b11;
#10;
w <= 4'b1101;
#10;
sel <= 2'b00;
w <= 4'b1110;
#10;
w <= 4'b1111;
#10;
end
endmodule
| 6.829662 |
module tb_multiplier;
parameter N = 16;
parameter STEP = 10;
integer count, fd;
reg [N-1:0] inj_data;
// Inputs
reg clk, rst;
reg [(N/2)-1:0] in1, in2;
// Outputs
wire [N-1:0] out;
// Instantiate the Unit Under Test (UUT)
//fir#(.N(N)) fir(
multiplier multiplier (
.in1(in1),
.in2(in2),
.out(out)
);
//Generate a clock with 10 ns clock period.
always #(STEP / 2) begin
clk <= ~clk;
end
always #(STEP) begin
count = count + 1; //to stop the simulation
end
//Initialize and apply the inputs.
initial begin
//$dumpvars(0, tb_fir);
#0 clk <= {1'b0};
#(STEP) #(STEP / 2) count = 0;
#(STEP) $write("Start clock %d \n", count);
$dumpon;
//in2[2:0] <= {3'b111};
fd = $fopen("/home/20200969/Estimation/rtl/fir_8bit/components/multiplier/stimuli.txt", "r");
if (!fd) $display("could not read file");
while (!$feof(
fd
)) begin
$fscanf(fd, "%b", inj_data);
#(STEP) in1 <= inj_data[(N/2)-1:0];
in2 <= inj_data[N-1:(N/2)];
end
$dumpoff;
#(STEP) $write("------------------------\n");
$write("Stop clock %d \n", count);
$finish;
end
always #(STEP) begin
//$write("inj_data=%b ", inj_data);
$write("in1={%b} ", in1);
$write("in2={%b} ", in2);
$write("out={%b} ", out);
$write("clk period count= %d", count);
$write("\n");
end
endmodule
| 7.552829 |
module tb_mult_shift_add ();
parameter WIDTH = 8;
reg clk;
reg [WIDTH - 1 : 0] S_data1, S_data2;
wire [2 * WIDTH - 1 : 0] F_mult;
initial begin
clk = 0;
S_data1 = 0;
S_data2 = 0;
#10 S_data1 = 2;
S_data2 = 6;
#10 S_data1 = 7;
S_data2 = 9;
#10 S_data1 = 17;
S_data2 = 12;
// #10 $stop;
#5
repeat (5)
@(posedge clk) begin
S_data1 <= ($random);
S_data2 <= ($random);
end
$stop;
end
always #5 clk = ~clk;
mult_shift_add #(WIDTH) mult_shift_adder (
S_data1,
S_data2,
F_mult
);
endmodule
| 6.975821 |
module: mult_unsigned_pipe
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mult_unsigned_pipe;
parameter WI1 = 1, //length of the integer part, operand 1
WF1 = 5, //length of the fraction part, operand 1
WI2 = 1, //length of the integer part, operand 2
WF2 = 6, //length of the fraction part, operand 2
WIO = 2, //default length for the integer part of the required output
WFO = 15, //default length of the fraction part of the required output
PIP = 1; //number of pipeline stages
// Inputs
reg CLK;
reg RST;
reg [WI1+WF1-1:0] in1;
reg [WI2+WF2-1:0] in2;
// Outputs
wire [WIO+WFO-1:0] out;
// ================================ Function Definition =======================================//
// Present the fixed point number into real number
function real unsigned_fixedToFloat;
input [2047:0] in; //should cover every bit of the maximal value
input integer WI;
input integer WF;
integer idx;
real retVal;
begin
retVal = 0;
for (idx = 0; idx < WI+WF; idx = idx + 1) begin
if(in[idx] == 1'b1) begin
retVal = retVal + (2.0**(idx-WF));
end
end
unsigned_fixedToFloat = retVal;
end
endfunction
//==================================================================================================//
//===================================== clock generator ==========================================//
parameter ClockPeriod = 2; // Clock period
initial CLK = 0;
always # (ClockPeriod/2) CLK = ~CLK;
//==================================================================================================//
// Instantiate the Unit Under Test (UUT)
mult_unsigned_pipe
#(
.WI1(WI1), //length of the integer part, operand 1
.WF1(WF1), //length of the fraction part, operand 1
.WI2(WI2), //length of the integer part, operand 2
.WF2(WF2), //length of the fraction part, operand 2
.WIO(WIO), //default length for the integer part of the required output
.WFO(WFO), //default length of the fraction part of the required output
.PIP(PIP) //number of pipeline stages
)
uut
(
.CLK(CLK),
.RST(RST),
.in1(in1),
.in2(in2),
.out(out)
);
// Real number presentation
real real_in1, real_in2, real_out;
initial begin
// Initialize Inputs
RST = 0; @(posedge CLK); RST = 1;
in1 = 6'b1_00000; in2 = 7'b1_100000; @(posedge CLK);
in1 = 6'b1_11000; in2 = 7'b1_110000; @(posedge CLK);
in1 = 6'b1_11100; in2 = 7'b1_010000; @(posedge CLK);
@(posedge CLK); @(posedge CLK); @(posedge CLK); $finish;
end
// -- input -- //
always @ in1 real_in1 = unsigned_fixedToFloat(in1, WI1, WF1);
always @ in2 real_in2 = unsigned_fixedToFloat(in2, WI2, WF2);
always @ out real_out = unsigned_fixedToFloat(out, WIO, WFO);
endmodule
| 7.33655 |
module
// Module Name: tb_mul_mod_module.v
// Project Name: pro_fpga_sm2
// Target Device:
// Tool versions:
// Description:
// 模乘模块验证
// 1. 产生随机输入，使能模乘模块
// 2. 等待模乘模块输出结果
// 3. 与直接模乘运算的结果进行比较
// 4. 开始下一次测试
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mul_mod_module;
// Inputs
reg clk;
reg rst_n;
reg mul_vld_i;
reg [255:0] mul_a_i;
reg [255:0] mul_b_i;
// Outputs
wire mul_fin_o;
wire [255:0] mul_r_o;
wire [255:0] mod_r_ref;
wire [511:0] mul_r_ref;
wire flg_diff;
`define RANDOM_INPT 1
//素数常量 p256
wire [255:0] P256 = {
8'hFF, 8'hFF, 8'hFF, 8'hFE, 8'hFF, 8'hFF, 8'hFF, 8'hFF, /* p */
8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'hFF,
8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'h00, 8'h00, 8'h00, 8'h00,
8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'hFF, 8'hFF
} ;
// Instantiate the Unit Under Test (UUT)
// 待测试模乘模块
mul_mod_module uut (
.clk(clk),
.rst_n(rst_n),
// .p256_i(P256), //NC,内部设置为P256
.mul_vld_i(mul_vld_i), //输入使能
.mul_a_i(mul_a_i),
.mul_b_i(mul_b_i),
.mul_fin_o(mul_fin_o), //输出使能
.mul_r_o(mul_r_o) //输出结果
);
initial begin
// Initialize Inputs
clk = 0;
rst_n = 0;
mul_vld_i = 0;
mul_a_i = 0;
mul_b_i = 0;
// Wait 100 ns for global reset to finish
#100;
rst_n = 1;
// Add stimulus here
@(posedge clk);
while (1) begin
mul_vld_i = 1;
wait(mul_fin_o);
mul_vld_i = 0;
@(posedge clk);
end
end
//产生输入激励
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
mul_a_i <= 256'd0;
mul_b_i <= 256'd0;
end else if(mul_fin_o)begin //在输出后产生一个随机输入
`ifdef RANDOM_INPT
mul_a_i <= {$urandom,$urandom,$urandom,$urandom,$urandom,$urandom,$urandom,$urandom};
mul_b_i <= {$urandom,$urandom,$urandom,$urandom,$urandom,$urandom,$urandom,$urandom};
`else
mul_a_i <= {64'h1,64'h2,64'h3,64'h4};
mul_b_i <= {64'h5,64'h6,64'h7,64'h8};
`endif
end
end
always #5 clk = ~clk;
//参考运算，使用 * % 运算符
assign mul_r_ref = (mul_a_i * mul_b_i);
assign mod_r_ref = mul_r_ref % P256;
assign flg_diff = mul_fin_o && ~(mod_r_ref == mul_r_o);
//打印不同的输出
always@(flg_diff)begin
$display("Fail!\n");
$display("REF: %X,%X\n",mod_r_ref[255-:128],mod_r_ref[127-:128]);
$display("OUT: %X,%X",mul_r_o[255-:128],mul_r_o[127-:128]);
end
endmodule
| 6.999332 |
module tb_mutex ();
reg clk;
reg arst_n;
initial begin
$dumpfile("./vcd/tb_mutex.vcd");
$dumpvars(0, mutex_impl);
arst_n <= 1'b0;
#100 arst_n <= 1'b1;
#6000 $finish;
end
always begin
#10 clk <= 1'b1;
#10 clk <= 1'b0;
end
reg req_0;
reg req_1;
initial begin
req_0 <= 1'b0;
req_1 <= 1'b0;
#400 req_0 <= 1'b1;
#100 req_1 <= 1'b1;
#200 req_0 <= 1'b0;
#200 req_0 <= 1'b1;
#200 req_0 <= 1'b0;
req_1 <= 1'b0;
#200 req_0 <= 1'b1;
req_1 <= 1'b1;
#100 req_0 <= 1'b0;
end
mutex mutex_impl (
.clk(clk),
.arst_n(arst_n),
.req_0(req_0),
.req_1(req_1),
.val_0(),
.val_1()
);
endmodule
| 7.180151 |
module tb_mux16to1_gate;
reg [15:0] in;
reg [3:0] sel;
wire out;
mux16to1_gate mux (
out,
in,
sel
);
initial begin
$monitor($time, " in=%16b | sel=%4b | out=%1b", in, sel, out);
end
initial begin
#0 in = 16'b1010101010101010;
sel = 4'b0000;
repeat (15) #10 sel = sel + 4'b0001;
end
endmodule
| 8.284665 |
module tb_mux16to1_glvl ();
reg [15:0] inp;
reg [3:0] sel;
wire outp;
mux16to1_glvl mux (
.outp(outp),
.sel (sel),
.inp (inp)
);
initial begin
$dumpfile("tb_mux16to1_glvl.vcd");
$dumpvars;
end
initial begin
$monitor("inp = %b, sel = %b, outp = %b", inp, sel, outp);
end
initial begin
inp = 16'b0000_0101_1111_1010;
sel = 4'b0000;
#5 sel = 4'b0001;
#5 sel = 4'b0010;
#5 sel = 4'b0011;
#5 sel = 4'b0100;
#5 sel = 4'b0101;
#5 sel = 4'b0110;
#5 sel = 4'b0111;
#5 sel = 4'b1000;
#5 sel = 4'b1001;
#5 sel = 4'b1010;
#5 sel = 4'b1011;
#5 sel = 4'b1100;
#5 sel = 4'b1101;
#5 sel = 4'b1110;
#5 sel = 4'b1111;
#5 $finish;
end
endmodule
| 8.284665 |
module BancoPruebamux2_1_2bits_reset_ff; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
wire [1:0] data_out_banco_conduc, data_out_banco_struc, data_in0_banco_conduc, data_in1_banco_conduc;
wire reset_L_banco_conduc, clk_banco_conduc, selector_banco_conduc;
// Behavioral description
mux21 a_cond (
.data_out(data_out_banco_conduc),
.data_in0(data_in0_banco_conduc),
.data_in1(data_in1_banco_conduc),
.reset_L (reset_L_banco_conduc),
.clk (clk_banco_conduc),
.selector(selector_banco_conduc)
);
mux21_synth structuralsynt (
.data_out(data_out_banco_struc),
.data_in0(data_in0_banco_conduc),
.data_in1(data_in1_banco_conduc),
.reset_L (reset_L_banco_conduc),
.clk (clk_banco_conduc),
.selector(selector_banco_conduc)
);
// Tester: signal generator and monitor
probador prob (
.data_out_conduc_tester(data_out_banco_conduc),
.data_out_struc_tester (data_out_banco_struc),
.data_in0_probador (data_in0_banco_conduc),
.data_in1_probador (data_in1_banco_conduc),
.reset_L_probador (reset_L_banco_conduc),
.clk_probador (clk_banco_conduc),
.selector_probador (selector_banco_conduc)
);
endmodule
| 7.293212 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire select_TB, reset_TB, clk_TB;
wire [1:0] in0_TB, in1_TB, out_BTB, out_STB;
wire valid_in0_TB, valid_in1_TB, valid_out_BTB, valid_out_STB;
// Use /*AUTOREGINPUT*/ for create inputs in /*AUTOINST*/ in case inputs, outputs of inout signals
// are not declared.
/*AUTOREGINPUT*/
///////////////////////////////////////////////////////////////////////////////////////////
//////////// Mux 2:1 2 BITS
////////////
///////////////////////////////////////////////////////////////////////////////////////////
// Behavioral
/* mux21_2b AUTO_TEMPLATE (.out\(.*\) (out\1_c[]));*/
mux21_2b mux21_2b_BTB ( /*AUTOINST*/
// Outputs
.out_b (out_BTB[1:0]),
.out_valid_b(valid_out_BTB),
// Inputs
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in0 (in0_TB[1:0]),
.in1 (in1_TB[1:0])
);
// Synthesis
/* mux21_2b_syn AUTO_TEMPLATE (.out\(.*\) (out\1_c[]));*/
mux21_2b_syn mux21_2b_STB ( /*AUTOINST*/
// Outputs
.out_b (out_STB[1:0]),
.out_valid_b(valid_out_STB),
// Inputs
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in0 (in0_TB[1:0]),
.in1 (in1_TB[1:0])
);
// Tester
/* t_mux21_2b AUTO_TEMPLATE (.out\(.*\) (out\1_c[]));*/
t_mux21_2b mux21_2b_B_TBtester ( /*AUTOINST*/
// Outputs
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in0 (in0_TB[1:0]),
.in1 (in1_TB[1:0]),
// Inputs
.out_b (out_BTB[1:0]),
.out_s (out_STB[1:0]),
.out_valid_b(valid_out_BTB),
.out_valid_s(valid_out_STB)
);
endmodule
| 7.554736 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire select_TB, reset_TB, clk_TB;
wire [3:0] in0_TB, in1_TB, out_BTB, out_STB;
wire valid_in0_TB, valid_in1_TB, valid_out_BTB, valid_out_STB;
/*AUTOREGINPUT*/
///////////////////////////////////////////////////////////////////////////////////////////
//////////// Mux 2:1 4 BITS
////////////
///////////////////////////////////////////////////////////////////////////////////////////
// Behavioral
/* mux21_4b_c AUTO_TEMPLATE (.out\(.*\) (out\1_c[]));*/
mux21_4b mux21_4b_B_TB ( /*AUTOINST*/
// Outputs
.out_b (out_BTB[3:0]),
.out_valid_b(valid_out_BTB),
// Inputs
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in0 (in0_TB[3:0]),
.in1 (in1_TB[3:0])
);
// Synthesis
/* mux21_4b_syn AUTO_TEMPLATE (.out\(.*\) (out\1_s[]));*/
mux21_4b_syn mux21_4b_S_TB ( /*AUTOINST*/
// Outputs
.out_b (out_STB[3:0]),
.out_valid_b(valid_out_STB),
// Inputs
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in0 (in0_TB[3:0]),
.in1 (in1_TB[3:0])
);
// Tester
/* t_mux21_4b AUTO_TEMPLATE (.out\(.*\) (out\1_t[]));*/
t_mux21_4b mux21_4b_B_TBtester ( /*AUTOINST*/
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in0 (in0_TB[3:0]),
.in1 (in1_TB[3:0]),
// Inputs
.out_b (out_BTB[3:0]),
.out_s (out_STB[3:0]),
.out_valid_b(valid_out_BTB),
.out_valid_s(valid_out_STB)
);
endmodule
| 7.554736 |
module: mux2in1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_mux2in1;
// Inputs
reg [31:0] i_dat0;
reg [31:0] i_dat1;
reg i_control;
// Outputs
wire [31:0] o_dat;
// Instantiate the Unit Under Test (UUT)
mux2in1 uut (
.i_dat0(i_dat0),
.i_dat1(i_dat1),
.i_control(i_control),
.o_dat(o_dat)
);
initial begin
// Initialize Inputs
i_dat0 = 0;
i_dat1 = 0;
i_control = 0;
// Wait 100 ns for global reset to finish
#100;
i_dat0 = 1;
i_dat1 = 2;
i_control = 0;
#10;
i_control = 1;
#10;
i_dat0 = 3;
i_dat1 = 4;
i_control = 0;
#10;
i_control = 1;
end
endmodule
| 7.071047 |
module tb_mux2x1;
reg [1:0] din;
reg sel;
wire dout;
mux2x1 mux (
dout,
sel,
din
);
initial begin
#0 din = 2'b00;
sel = 0;
#20 sel = 1;
#20 din = 2'b01;
sel = 0;
#20 sel = 1;
#20 din = 2'b10;
sel = 0;
#20 sel = 1;
#20 din = 2'b11;
sel = 0;
#20 sel = 1;
end
endmodule
| 6.635589 |
module tb_mux2_1(); //testbench的格式和待测试RTL模块的格式相同,也是以“module”开始以“endmodule
| 6.566912 |
module
module tb_led();
//********************************************************************//
//****************** Parameter and Internal Signal *******************//
//********************************************************************//
//wire define
wire led_out ;
//reg define
reg key_in ;
//********************************************************************//
//***************************** Main Code ****************************//
//********************************************************************//
//初始化输入信号
initial key_in <= 1'b0;
//key_in:产生输入随机数,模拟按键的输入情况
always #10 key_in <= {$random} % 2; /*取模求余数,产生非负随机数0、1
每隔10ns产生一次随机数*/
//********************************************************************//
//**************************** Instantiate ***************************//
//********************************************************************//
//------------- led_inst -------------
led led_inst
(
.key_in (key_in ), //input key_in
.led_out(led_out) //output led_out
);
endmodule
| 7.342042 |
module tb_mux4 ();
parameter NB = 32;
parameter NB_SELECT = 2;
reg [NB_SELECT-1:0] select;
reg [ NB-1:0] a;
reg [ NB-1:0] b;
reg [ NB-1:0] c;
reg [ NB-1:0] d;
wire [ NB-1:0] data;
initial begin
a = 32'd1;
b = 32'd80;
c = 32'd250;
d = 32'd999;
select = 2'd0;
#100 select = 2'd1;
#100 select = 2'd2;
#100 select = 2'd3;
#200 $finish;
end
mux4 mux4 (
.i_SEL(select),
.i_A(a),
.i_B(b),
.i_C(c),
.i_D(d),
.o_data(data)
);
endmodule
| 6.617536 |
module TestBench; // Testbench
// Usually the signals in the test bench are wires.
// They do not store a value, they are handled by other module instances.
// Since they require matching the size of the inputs and outputs, they must be assigned their size
// defined in the modules
// If you define quantity format, it is recommended to keep it in the same format being the
// same used in the module for the number of bits - [1: 0] ---, another way to do it is with
// [0: 1]
// We are going to use AUTOINST: It is responsible for replacing the connections (considering it is HDL)
// pin to an instance (module) with variables as they change over time automatically in the instantiated module
// It's needed /*AUTOWIRE*/ because: Creates wires for outputs that ins't declare
/*AUTOWIRE*/
wire reset_TB, clk_TB;
wire [1:0] select_TB;
wire [3:0] in0_TB, in1_TB, in2_TB, in3_TB, out_BTB, out_STB;
wire valid_in0_TB, valid_in1_TB, valid_in2_TB, valid_in3_TB, valid_out_BTB, valid_out_STB;
/*AUTOREGINPUT*/
///////////////////////////////////////////////////////////////////////////////////////////
//////////// Mux 4:1 4 BITS
////////////
///////////////////////////////////////////////////////////////////////////////////////////
// Behavioral
/* mux41_4b_c AUTO_TEMPLATE (.out\(.*\) (out\1_c[]));*/
mux41_4b mux41_4b_B_TB ( /*AUTOINST*/
// Outputs
.out_b (out_BTB[3:0]),
.out_valid_b(valid_out_BTB),
//Inputs
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in2_valid (valid_in2_TB),
.in3_valid (valid_in3_TB),
.in0 (in0_TB[3:0]),
.in1 (in1_TB[3:0]),
.in2 (in2_TB[3:0]),
.in3 (in3_TB[3:0])
);
// Synthesis
/* mux41_4b_syn_s AUTO_TEMPLATE (.out\(.*\) (out\1_c[]));*/
mux41_4b_syn mux41_4b_S_TB ( /*AUTOINST*/
// Outputs
.out_b (out_STB[3:0]),
.out_valid_b(valid_out_STB),
//Inputs
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in2_valid (valid_in2_TB),
.in3_valid (valid_in3_TB),
.in0 (in0_TB[3:0]),
.in1 (in1_TB[3:0]),
.in2 (in2_TB[3:0]),
.in3 (in3_TB[3:0])
);
// Tester
/* tester41_4b_t AUTO_TEMPLATE (.out\(.*\) (out\1_c[]));*/
t_mux41_4b mux41_4b_B_TBtester ( /*AUTOINST*/
//Outputs
.clk (clk_TB),
.reset (reset_TB),
.select (select_TB),
.in0_valid (valid_in0_TB),
.in1_valid (valid_in1_TB),
.in2_valid (valid_in2_TB),
.in3_valid (valid_in3_TB),
.in0 (in0_TB[3:0]),
.in1 (in1_TB[3:0]),
.in2 (in2_TB[3:0]),
.in3 (in3_TB[3:0]),
// Inputs
.out_b (out_BTB[3:0]),
.out_s (out_STB[3:0]),
.out_valid_b(valid_out_BTB),
.out_valid_s(valid_out_STB)
);
endmodule
| 7.554736 |
module tb_mux4to1;
wire [31:0] out;
reg [31:0] in1, in2, in3, in4;
reg [1:0] sel;
mux4to1 m1 (
out,
in1,
in2,
in3,
in4,
sel
);
initial
$monitor($time, " in1=%h in2=%h in3=%h in4=%h sel=%b out=%h", in1, in2, in3, in4, sel, out);
initial begin
in1 = 32'b10101010_10101010_10101010_10101010;
in2 = 32'b01010101_01010101_01010101_01010101;
in3 = 32'b10011001_10011001_10011001_10011001;
in4 = 32'b01100110_01100110_01100110_01100110;
sel = 2'b00;
#100 sel = 2'b01;
#100 sel = 2'b10;
#100 sel = 2'b11;
end
endmodule
| 7.125511 |
module tb_mux4to1_glvl ();
wire outp;
reg [3:0] inp;
reg [1:0] sel;
mux4to1_glvl mux (
.outp(outp),
.inp (inp),
.sel (sel)
);
initial begin
$dumpfile("tb_mux4to1_glvl.vcd");
$dumpvars;
end
initial begin
inp = 4'b0101;
sel = 2'b00;
#5 sel = 2'b01;
#5 sel = 2'b10;
#5 sel = 2'b11;
end
endmodule
| 7.73663 |
module tb_mux4x1;
reg [3:0] din;
reg [1:0] sel;
wire dout;
mux4x1 mux (
dout,
sel,
din
);
initial begin
#0 din = 4'b0000;
sel = 2'b00;
#20 sel = 2'b01;
#20 sel = 2'b10;
#20 sel = 2'b11;
#20 din = 4'b0001;
sel = 2'b00;
#20 sel = 2'b01;
#20 sel = 2'b10;
#20 sel = 2'b11;
#20 din = 4'b0010;
sel = 2'b00;
#20 sel = 2'b01;
#20 sel = 2'b10;
#20 sel = 2'b11;
#20 din = 4'b0011;
sel = 2'b00;
#20 sel = 2'b01;
#20 sel = 2'b10;
#20 sel = 2'b11;
end
endmodule
| 6.937852 |
module: mux5
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TB_mux5;
// Inputs
reg [4:0] inputA;
reg [4:0] inputB;
reg controlSignal;
// Outputs
wire [4:0] outMux;
// Instantiate the Unit Under Test (UUT)
mux5 uut (
.inputA(inputA),
.inputB(inputB),
.controlSignal(controlSignal),
.outMux(outMux)
);
initial begin
// Initialize Inputs
inputA = 5'b0;
inputB = 5'b1;
controlSignal = 0;
// Wait 100 ns for global reset to finish
#100;
inputA = 5'b0;
inputB = 5'b1;
controlSignal = 1;
#100;
// Add stimulus here
end
endmodule
| 7.087865 |
module MuxTestbenchData;
reg [7:0] in1;
reg [7:0] in2;
reg control;
wire [7:0] out;
Mux #(
.N(8)
) dut (
.in1(in1),
.in2(in2),
.control(control),
.out(out)
);
initial begin
$display("Teste 1: Selecionando a entrada 1");
in1 = 22;
in2 = 14;
control = 0;
#1;
$display("Teste 2: Selecionando a entrada 2");
in1 = 70;
in2 = 17;
control = 1;
end
initial begin
$monitor("Tempo: %0d\tEntrada 1: %d\tEntrada 2: %d\tControle: %b\tSaida: %d\n", $time, in1,
in2, control, out);
end
endmodule
| 7.8824 |
module tb_MUXpreALU ();
wire [15:0] ALU_1_IN, ALU_2_IN;
reg [15:0] PC;
reg [15:0] D_ReadReg1RT, D_BT, D_Offset;
reg [15:0] D_ReadReg2RT, D_RegSW;
reg [15:0] D_JUMP_SE_Out, D_SE_Out, D_USE_Out, D_L1S_Out;
reg C_SignExtend;
reg [1:0] C_RegDstRead1R;
reg C_RegDstRead2R;
reg C_ALUSrc_A;
reg [2:0] C_ALUSrc_B;
MUXpreALU uut (
ALU_1_IN,
ALU_2_IN,
PC,
D_ReadReg1RT,
D_BT,
D_Offset,
D_ReadReg2RT,
D_RegSW,
D_JUMP_SE_Out,
D_SE_Out,
D_USE_Out,
D_L1S_Out,
C_SignExtend,
C_RegDstRead1R,
C_RegDstRead2R,
C_ALUSrc_A,
C_ALUSrc_B
);
initial begin
#0 PC <= 16'hFFFF;
#0 D_ReadReg1RT <= 16'hEEEE;
#0 D_BT <= 16'hDDDD;
#0 D_Offset <= 16'hCCCC;
#0 D_ReadReg2RT <= 16'hBBBB;
#0 D_RegSW <= 16'hAAAA;
#0 D_JUMP_SE_Out <= 16'h9999;
#0 D_SE_Out <= 16'h8888;
#0 D_USE_Out <= 16'h7777;
#0 D_L1S_Out <= 16'h6666;
end
initial begin
#000 C_SignExtend = 1'b0;
#010 C_SignExtend = 1'b1;
#010 C_RegDstRead1R = 2'b00;
#010 C_RegDstRead1R = 2'b01;
#010 C_RegDstRead1R = 2'b10;
#010 C_RegDstRead1R = 2'b11;
#010 C_RegDstRead2R = 1'b0;
#010 C_RegDstRead2R = 1'b1;
#010 C_ALUSrc_A = 1'b0;
#010 C_ALUSrc_A = 1'b1;
#010 C_ALUSrc_B = 3'b000;
#010 C_ALUSrc_B = 3'b001;
#010 C_ALUSrc_B = 3'b010;
#010 C_ALUSrc_B = 3'b011;
#010 C_ALUSrc_B = 3'b100;
#010 C_ALUSrc_B = 3'b101;
#010 C_ALUSrc_B = 3'b110;
#010 C_ALUSrc_B = 3'b111;
#010 $stop;
end
initial begin
$dumpfile("MUXpreALU.vcd");
$dumpvars;
end
initial $monitor("time=%3d, ALU_1_IN=%16h, ALU_2_IN=%16h", $time, ALU_1_IN, ALU_2_IN);
endmodule
| 6.969239 |
module MuxTestbenchData;
reg [1:0] in1;
reg [1:0] in2;
reg control;
wire [1:0] out;
Mux #(
.N(2)
) dut (
.in1(in1),
.in2(in2),
.control(control),
.out(out)
);
initial begin
$display("Teste 1: Selecionando a entrada 1");
in1 = 1;
in2 = 0;
control = 0;
#1;
$display("Teste 2: Selecionando a entrada 2");
in1 = 3;
in2 = 2;
control = 1;
end
initial begin
$monitor("Tempo: %0d\tEntrada 1: %d\tEntrada 2: %d\tControle: %b\tSaida: %d\n", $time, in1,
in2, control, out);
end
endmodule
| 7.8824 |
module tb_mux_2_1 ();
reg in_1;
reg in_2;
reg sel;
wire out;
initial
//begin end之间顺序执行，速度极快
begin
in_1 <= 1'b0;
in_2 <= 1'b0;
sel <= 1'b0;
end
//每隔10ns对in_1赋值
always #10 in_1 <= {$random} % 2; //结果只能为1 0
always #10 in_2 <= {$random} % 2; //结果只能为1 0
always #10 sel <= {$random} % 2; //结果只能为1 0
initial begin
/*
显示时间格式为10^-9 即纳秒
0表示小数点后位数
"ns"与-9对于
6表示打印的最小数字字符
*/
$timeformat(-9, 0, "ns", 6);
$monitor("@time %t:in_1=%b in_2=%b sel=%b out=%b", $time, in_1, in_2, sel, out);
end
/********实例化********/
//模块名 实例化名称
mux_2_1 mux_2_1_inst (
.in_1(in_1), //将仿真模块in_1与被仿真模块in_1相连接
.in_2(in_2),
.sel (sel),
.out (out)
);
endmodule
| 6.981773 |
module TB_Mux_3x1;
parameter P = 32;
// Inputs
reg CLK;
reg [1:0] MS;
reg [P-1:0] D_0;
reg [P-1:0] D_1;
reg [P-1:0] D_2;
//outputs
wire [P-1:0] D_out;
// Instantiate the Unit Under Test (UUT)
Mux_3x1 uut (
.MS(MS),
.D_0(D_0),
.D_1(D_1),
.D_2(D_2),
.D_out(D_out)
);
initial begin
// Initialize Inputs
CLK = 0;
MS = 2'b00;
D_0 = 32'b00000000000000000000000000000000;
D_1 = 32'b10000000000000000000000000000001;
D_2 = 32'b11000000000000000000000000000011;
#100 MS = 2'b00;
// // Wait 100 ns for global reset to finish
#100 MS = 2'b01;
#100 MS = 2'b10;
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 CLK = ~CLK;
endmodule
| 6.570949 |
module tb_mux8_2;
wire [7:0] t_out;
reg [7:0] t_in_a, t_in_b;
reg t_sel;
mux8_2 dut (
.in_a(t_in_a),
.in_b(t_in_b),
.sel (t_sel),
.out (t_out)
);
initial begin
$monitor(t_in_a, t_in_b, t_sel, t_out);
t_in_a = 8'b10101010;
t_in_b = 8'b01010101;
t_sel = 1'b0;
#5 t_sel = 1'b0;
#5 t_sel = 1'b1;
#5 t_sel = 1'b0;
#5 t_sel = 1'b1;
end
endmodule
| 6.743904 |
module tb_mux_behav ();
reg in1, in2, sel;
wire out;
mux_behav UUT (
out,
in1,
in2,
sel
);
initial begin
in1 = 1'b0; // here we apply inputs to the logic
in2 = 1'b0;
sel = 1'b0;
#10;
in1 = 1'b0;
in2 = 1'b1;
sel = 1'b0;
#10;
in1 = 1'b1;
in2 = 1'b0;
sel = 1'b0;
#10;
in1 = 1'b1;
in2 = 1'b1;
sel = 1'b0;
#10;
in1 = 1'b0;
in2 = 1'b0;
sel = 1'b1;
#10;
in1 = 1'b0;
in2 = 1'b1;
sel = 1'b1;
#10;
in1 = 1'b1;
in2 = 1'b0;
sel = 1'b1;
#10;
in1 = 1'b1;
in2 = 1'b1;
sel = 1'b1;
#10;
end
// set up the monitoring
initial begin
$monitor("sel=%b, in1=%b, in2=%b, out=%b, time=%t\n", sel, in1, in1, out, $time);
end
endmodule
| 6.553501 |
module : tb_mux_bus
* @author : Secure, Trusted, and Assured Microelectronics (STAM) Center
* Copyright (c) 2022 Trireme (STAM/SCAI/ASU)
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module tb_mux_bus();
parameter WIDTH = 8,
NUM_PORTS = 4;
//Define the log2 function
function integer log2;
input integer num;
integer i, result;
begin
for (i = 0; 2 ** i < num; i = i + 1)
result = i + 1;
log2 = result;
end
endfunction
reg [WIDTH*NUM_PORTS-1 : 0] data_in;
reg [log2(NUM_PORTS)-1 : 0] enable_port;
reg valid_enable;
wire [WIDTH-1 : 0] data_out;
// Instantiate tristate_bus
mux_bus #(WIDTH, NUM_PORTS)
DUT(data_in, enable_port, valid_enable, data_out);
initial begin
data_in = 32'h89ABCDEF;
enable_port = 0;
valid_enable = 0;
#100;
enable_port = 1;
valid_enable = 1;
#50;
enable_port = 2;
#50;
enable_port = 3;
#50;
enable_port = 0;
#50;
valid_enable = 0;
#50;
enable_port = 3;
valid_enable = 1;
end
//Automatic verification code
initial begin
#1;
if(data_out != 8'h00)begin
$display("\ntb_mux_bus --> Test Failed!\n\n");
$stop;
end
#100;
if(data_out != 8'hCD)begin
$display("\ntb_mux_bus --> Test Failed!\n\n");
$stop;
end
#50;
if(data_out != 8'hAB)begin
$display("\ntb_mux_bus --> Test Failed!\n\n");
$stop;
end
#50;
if(data_out != 8'h89)begin
$display("\ntb_mux_bus --> Test Failed!\n\n");
$stop;
end
#50;
if(data_out != 8'hEF)begin
$display("\ntb_mux_bus --> Test Failed!\n\n");
$stop;
end
#50;
if(data_out != 8'h00)begin
$display("\ntb_mux_bus --> Test Failed!\n\n");
$stop;
end
#50;
if(data_out != 8'h89)begin
$display("\ntb_mux_bus --> Test Failed!\n\n");
$stop;
end
#50;
$display("\ntb_mux_bus --> Test Passed!\n\n");
$finish;
end
//Timeout
initial begin
#500;
$display("\ntb_mux_bus --> Test Failed!\n\n");
$finish;
end
endmodule
| 7.250913 |
module tb_mux_for;
// Inputs
reg i0, i1;
reg i2, i3;
reg [1:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux_for uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.i3 (i3),
.y (y)
);
initial begin
$dumpfile("tb_mux_for.vcd");
$dumpvars(0, tb_mux_for);
// Initialize Inputs
i0 = 1'b0;
i1 = 1'b0;
i2 = 1'b0;
i3 = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#3000 $finish;
end
always #17 i0 = ~i0;
always #37 i1 = ~i1;
always #88 i2 = ~i2;
always #155 i3 = ~i3;
always #300 clk = ~clk;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 2'b00;
else sel <= sel + 1;
end
endmodule
| 7.764209 |
module tb_mux_for_net;
// Inputs
reg i0, i1;
reg i2, i3;
reg [1:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux_for uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.i3 (i3),
.y (y)
);
initial begin
$dumpfile("tb_mux_for_net.vcd");
$dumpvars(0, tb_mux_for_net);
// Initialize Inputs
i0 = 1'b0;
i1 = 1'b0;
i2 = 1'b0;
i3 = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#3000 $finish;
end
always #17 i0 = ~i0;
always #37 i1 = ~i1;
always #88 i2 = ~i2;
always #155 i3 = ~i3;
always #300 clk = ~clk;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 2'b00;
else sel <= sel + 1;
end
endmodule
| 7.89109 |
module tb_mux_generate;
// Inputs
reg i0, i1;
reg i2, i3;
reg [1:0] sel;
//TB Signals
reg clk, reset;
// Outputs
wire y;
// Instantiate the Unit Under Test (UUT)
mux_generate uut (
.sel(sel),
.i0 (i0),
.i1 (i1),
.i2 (i2),
.i3 (i3),
.y (y)
);
initial begin
$dumpfile("tb_mux_generate.vcd");
$dumpvars(0, tb_mux_generate);
// Initialize Inputs
i0 = 1'b0;
i1 = 1'b0;
i2 = 1'b0;
i3 = 1'b0;
clk = 1'b0;
reset = 1'b0;
#1;
reset = 1'b1;
#10;
reset = 1'b0;
#3000 $finish;
end
always #17 i0 = ~i0;
always #37 i1 = ~i1;
always #88 i2 = ~i2;
always #155 i3 = ~i3;
always #300 clk = ~clk;
always @(posedge clk, posedge reset) begin
if (reset) sel <= 2'b00;
else sel <= sel + 1;
end
endmodule
| 8.324065 |
module tb_mux_mem_data (
input [15:0] in_1,
input [15:0] in_2,
input mem_data_select,
output [15:0] mux_out
);
assign mux_out = mem_data_select ? in_1 : in_2;
endmodule
| 8.328469 |
module tb_myHough ();
// UUT Inputs
wire tb_x[10:0];
wire tb_y[9:0];
wire tb_value;
wire clk;
wire ce;
// UUT Outputs
wire [4:0] theta;
wire [10:0] rho;
// ile blockramów? 2048 x ? tyle blockramów ile theta, długość to rho
myHough myInstance (
.pixel_x(tb_x), // up to 2000px
.pixel_y(tb_y), // up to 1000px
.pixel_value(tb_value), // 0 or 1, black or white, no edge or edge
.clk(clk),
.ce(ce),
.theta (theta), // up to 180, if step is greater than 1 degree theta can has less bits (30 values needed - 5 bits)
.rho(rho) // up to ???
);
endmodule
| 7.961568 |
module tb_myosctest;
reg rst_n; //͵ƽλź
wire clkdiv; //8Ƶź
myosctest myosctest (
.rst_n (rst_n),
.clkdiv(clkdiv)
);
initial begin
rst_n = 0;
#1000;
rst_n = 1;
#50000;
$stop;
end
endmodule
| 6.956316 |
module tb_mythcore_test;
// Inputs
reg clk, reset;
// Outputs
wire [9:0] out;
// Instantiate the Unit Under Test (UUT)
core uut (
.clk (clk),
.reset(reset),
.out (out)
);
initial begin
$dumpfile("tb_mythcore_test.vcd");
$dumpvars(0, tb_mythcore_test);
clk = 1;
reset = 0;
#2 reset = 1;
#10 reset = 0;
#2000 $finish;
end
always #1 clk = ~clk;
endmodule
| 7.170844 |
module tb_m_delay_line;
reg clk;
reg [3:0] delay;
reg [9:0] din;
wire [9:0] dout;
initial begin
$from_myhdl(clk, delay, din);
$to_myhdl(dout);
end
m_delay_line dut (
clk,
delay,
din,
dout
);
endmodule
| 7.290343 |
module tb_m_delay_line_w10;
reg clk;
reg [3:0] delay;
reg [9:0] din;
wire [9:0] dout;
initial begin
$from_myhdl(clk, delay, din);
$to_myhdl(dout);
end
m_delay_line_w10 dut (
clk,
delay,
din,
dout
);
endmodule
| 7.290343 |
module tb_m_fifo_2clock_cascade;
reg wclk;
reg [35:0] datain;
reg src_rdy_i;
wire dst_rdy_o;
reg [15:0] space;
reg rclk;
wire [35:0] dataout;
wire src_rdy_o;
reg dst_rdy_i;
reg [15:0] occupied;
reg reset;
initial begin
$from_myhdl(wclk, datain, src_rdy_i, space, rclk, dst_rdy_i, occupied, reset);
$to_myhdl(dst_rdy_o, dataout, src_rdy_o);
end
m_fifo_2clock_cascade dut (
wclk,
datain,
src_rdy_i,
dst_rdy_o,
space,
rclk,
dataout,
src_rdy_o,
dst_rdy_i,
occupied,
reset
);
endmodule
| 6.682988 |
module nand_gate_top;
reg I0, I1;
wire Out;
nand_gate gate0 (
I0,
I1,
Out
);
initial begin
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 0;
I1 = 1;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 1;
I1 = 0;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
I0 = 1;
I1 = 1;
#1;
$display("I0 : %b, I1 : %b, Out : %b", I0, I1, Out);
end
endmodule
| 6.783006 |
module NanoRiscTestbench;
reg clock;
wire [7:0] instructionFromInstructionMemory;
wire [7:0] instructionAddressToInstructionMemory;
wire [7:0] dataFromDataMemory;
wire [3:0] addressToDataMemory;
wire [7:0] dataToDataMemory;
reg [15:0] cycleCounter;
integer i;
NanoRisc nRisc (
clock,
instructionFromInstructionMemory,
dataFromDataMemory,
instructionAddressToInstructionMemory,
addressToDataMemory,
dataToDataMemory
);
InstructionMemory instructionMemory (
clock,
instructionAddressToInstructionMemory,
instructionFromInstructionMemory
);
DataMemory dataMemory (
clock,
addressToDataMemory,
dataToDataMemory,
dataFromDataMemory,
nRisc.MemRead,
nRisc.MemWrite
);
initial begin
clock = 0;
cycleCounter = 1;
forever begin
if (cycleCounter == 70) begin
$finish;
end
#1;
clock = ~clock;
$display("Program Counter: %d", nRisc.programCounter.progamCounter);
$display("PCin: %d", nRisc.PCin);
$display("Numero de ciclos: %d", cycleCounter);
$display("Clock: %b", clock);
$display("Instrucao completa: %b", nRisc.instructionFromInstructionMemory);
$display("Opcode: %b", nRisc.opcode);
$display("Reg1: %b", nRisc.reg1);
$display("Reg2: %b", nRisc.reg2);
$display("Endereco: %b", nRisc.address);
$display("Bit Zero: %b", nRisc.bitZero);
$display("Sinais de Controle");
$display(
"PCWrite: %b\tRegWrite: %b\tisSend: %b\tisBranch: %b\tULAOp: %b\tMemWrite: %b\tMemRead: %b\tRegMemWrite: %b",
nRisc.PCWrite, nRisc.RegWrite, nRisc.isSend, nRisc.isBranch, nRisc.ULAOp, nRisc.MemWrite,
nRisc.MemRead, nRisc.RegMemWrite);
$display("Saidas das Portas AND");
$display("Seleciona o registrador de escrita: %b", nRisc.andRegisterWrite);
$display("Saidas dos MUXS");
$display("Seleciona o registrador de escrita: %b", nRisc.selectedForWrite);
$display("$mem: %b", nRisc.memRead);
for (i = 0; i < 4; i++) begin
$display("Registrador A -> %d: %b => %d", i, nRisc.registerBank.registersA[i],
nRisc.registerBank.registersA[i]);
end
for (i = 0; i < 4; i++) begin
$display("Registrador B -> %d: %b", i, nRisc.registerBank.registersB[i]);
end
$display("Resultado Final salvo na memoria => Posicao 5 da memoria de dados: %b",
dataMemory.data[5]);
$display("\n");
cycleCounter = cycleCounter + 1;
end
end
endmodule
| 7.674536 |
module D_Flip_Flop (
R7_OBUF,
ZERO,
MUX_B_REG_VAL,
FA1_C,
CLR_IBUF,
Q_reg_0,
Clk_With_Enabled_4,
HA0_S_5,
Q_reg_1,
Sub,
Q_reg_2,
Q_reg_3,
HA0_S_6,
Q_reg_4,
Q_reg_5,
R5_OBUF,
R4_OBUF,
Q_reg_6,
Q_reg_7
);
output [0:0] R7_OBUF;
output ZERO;
output [0:0] MUX_B_REG_VAL;
output FA1_C;
input CLR_IBUF;
input [0:0] Q_reg_0;
input Clk_With_Enabled_4;
input HA0_S_5;
input Q_reg_1;
input Sub;
input Q_reg_2;
input [2:0] Q_reg_3;
input HA0_S_6;
input Q_reg_4;
input [2:0] Q_reg_5;
input [0:0] R5_OBUF;
input [0:0] R4_OBUF;
input Q_reg_6;
input Q_reg_7;
wire CLR_IBUF;
wire Clk_With_Enabled_4;
wire FA1_C;
wire HA0_S_5;
wire HA0_S_6;
wire [0:0] MUX_B_REG_VAL;
wire [0:0] Q_reg_0;
wire Q_reg_1;
wire Q_reg_2;
wire [2:0] Q_reg_3;
wire Q_reg_4;
wire [2:0] Q_reg_5;
wire Q_reg_6;
wire Q_reg_7;
wire [0:0] R4_OBUF;
wire [0:0] R5_OBUF;
wire [0:0] R7_OBUF;
wire Sub;
wire ZERO;
wire ZERO_OBUF_inst_i_46_n_0;
wire ZERO_OBUF_inst_i_64_n_0;
wire ZERO_OBUF_inst_i_8_n_0;
LUT5 #(
.INIT(32'hDFF808D0)
) Q_i_5__0 (
.I0(MUX_B_REG_VAL),
.I1(Q_reg_3[0]),
.I2(Sub),
.I3(Q_reg_4),
.I4(Q_reg_3[1]),
.O (FA1_C)
);
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1)
) Q_reg (
.C (Clk_With_Enabled_4),
.CE(1'b1),
.D (Q_reg_0),
.Q (R7_OBUF),
.R (CLR_IBUF)
);
LUT6 #(
.INIT(64'h8008088002808002)
) ZERO_OBUF_inst_i_2 (
.I0(ZERO_OBUF_inst_i_8_n_0),
.I1(HA0_S_5),
.I2(Q_reg_1),
.I3(Sub),
.I4(Q_reg_2),
.I5(Q_reg_3[2]),
.O (ZERO)
);
LUT2 #(
.INIT(4'h8)
) ZERO_OBUF_inst_i_22 (
.I0(ZERO_OBUF_inst_i_46_n_0),
.I1(Q_reg_7),
.O (MUX_B_REG_VAL)
);
LUT2 #(
.INIT(4'hE)
) ZERO_OBUF_inst_i_46 (
.I0(ZERO_OBUF_inst_i_64_n_0),
.I1(Q_reg_6),
.O (ZERO_OBUF_inst_i_46_n_0)
);
LUT6 #(
.INIT(64'hFFFFF888F888F888)
) ZERO_OBUF_inst_i_64 (
.I0(R7_OBUF),
.I1(Q_reg_5[2]),
.I2(R5_OBUF),
.I3(Q_reg_5[1]),
.I4(R4_OBUF),
.I5(Q_reg_5[0]),
.O (ZERO_OBUF_inst_i_64_n_0)
);
LUT6 #(
.INIT(64'h8202008000808201)
) ZERO_OBUF_inst_i_8 (
.I0(HA0_S_6),
.I1(MUX_B_REG_VAL),
.I2(Q_reg_3[0]),
.I3(Sub),
.I4(Q_reg_4),
.I5(Q_reg_3[1]),
.O (ZERO_OBUF_inst_i_8_n_0)
);
endmodule
| 7.225235 |
module D_Flip_Flop_6 (
R7_OBUF,
FA4_C,
Q_reg_0,
MUX_B_REG_VAL,
CLR_IBUF,
Q_reg_1,
Clk_With_Enabled_4,
Q_reg_2,
Q_reg_3,
Sub,
Q_reg_4,
FA0_C,
Q_reg_5,
R5_OBUF,
R4_OBUF,
Q_reg_6,
Q_reg_7
);
output [0:0] R7_OBUF;
output FA4_C;
output Q_reg_0;
output [0:0] MUX_B_REG_VAL;
input CLR_IBUF;
input [0:0] Q_reg_1;
input Clk_With_Enabled_4;
input Q_reg_2;
input [3:0] Q_reg_3;
input Sub;
input [1:0] Q_reg_4;
input FA0_C;
input [2:0] Q_reg_5;
input [0:0] R5_OBUF;
input [0:0] R4_OBUF;
input Q_reg_6;
input Q_reg_7;
wire CLR_IBUF;
wire Clk_With_Enabled_4;
wire FA0_C;
wire FA4_C;
wire [0:0] MUX_B_REG_VAL;
wire Q_reg_0;
wire [0:0] Q_reg_1;
wire Q_reg_2;
wire [3:0] Q_reg_3;
wire [1:0] Q_reg_4;
wire [2:0] Q_reg_5;
wire Q_reg_6;
wire Q_reg_7;
wire [0:0] R4_OBUF;
wire [0:0] R5_OBUF;
wire [0:0] R7_OBUF;
wire Sub;
wire ZERO_OBUF_inst_i_50_n_0;
wire ZERO_OBUF_inst_i_68_n_0;
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1)
) Q_reg (
.C (Clk_With_Enabled_4),
.CE(1'b1),
.D (Q_reg_1),
.Q (R7_OBUF),
.R (CLR_IBUF)
);
LUT6 #(
.INIT(64'hB2FFFFE800E8B200)
) SIGN_OBUF_inst_i_4 (
.I0(Q_reg_0),
.I1(Q_reg_2),
.I2(Q_reg_3[2]),
.I3(Sub),
.I4(Q_reg_4[1]),
.I5(Q_reg_3[3]),
.O (FA4_C)
);
LUT6 #(
.INIT(64'hB2FFFFE800E8B200)
) ZERO_OBUF_inst_i_10 (
.I0(FA0_C),
.I1(MUX_B_REG_VAL),
.I2(Q_reg_3[0]),
.I3(Sub),
.I4(Q_reg_4[0]),
.I5(Q_reg_3[1]),
.O (Q_reg_0)
);
LUT2 #(
.INIT(4'h8)
) ZERO_OBUF_inst_i_24 (
.I0(ZERO_OBUF_inst_i_50_n_0),
.I1(Q_reg_7),
.O (MUX_B_REG_VAL)
);
LUT2 #(
.INIT(4'hE)
) ZERO_OBUF_inst_i_50 (
.I0(ZERO_OBUF_inst_i_68_n_0),
.I1(Q_reg_6),
.O (ZERO_OBUF_inst_i_50_n_0)
);
LUT6 #(
.INIT(64'hFFFFF888F888F888)
) ZERO_OBUF_inst_i_68 (
.I0(R7_OBUF),
.I1(Q_reg_5[2]),
.I2(R5_OBUF),
.I3(Q_reg_5[1]),
.I4(R4_OBUF),
.I5(Q_reg_5[0]),
.O (ZERO_OBUF_inst_i_68_n_0)
);
endmodule
| 6.607773 |
module D_Flip_Flop_60 (
R1_OBUF,
CLR_IBUF,
REG_BANK_INPUT,
Clk_With_Enabled
);
output [0:0] R1_OBUF;
input CLR_IBUF;
input [0:0] REG_BANK_INPUT;
input Clk_With_Enabled;
wire CLR_IBUF;
wire Clk_With_Enabled;
wire [0:0] R1_OBUF;
wire [0:0] REG_BANK_INPUT;
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1)
) Q_reg (
.C (Clk_With_Enabled),
.CE(1'b1),
.D (REG_BANK_INPUT),
.Q (R1_OBUF),
.R (CLR_IBUF)
);
endmodule
| 6.607773 |
module D_Flip_Flop_61 (
Q_reg_0,
NEXT_IA_OBUF,
Q_reg_1,
Q_reg_2,
CLR_IBUF,
Q_reg_3,
CLK_IBUF_BUFG,
Q_reg_4,
Q_reg_5,
JMP,
Q_reg_6,
Q_reg_7,
Q_reg_8
);
output Q_reg_0;
output [0:0] NEXT_IA_OBUF;
output [1:0] Q_reg_1;
output Q_reg_2;
input CLR_IBUF;
input Q_reg_3;
input CLK_IBUF_BUFG;
input Q_reg_4;
input Q_reg_5;
input JMP;
input Q_reg_6;
input Q_reg_7;
input Q_reg_8;
wire CLK_IBUF_BUFG;
wire CLR_IBUF;
wire JMP;
wire [0:0] NEXT_IA_OBUF;
wire Q_reg_0;
wire [1:0] Q_reg_1;
wire Q_reg_2;
wire Q_reg_3;
wire Q_reg_4;
wire Q_reg_5;
wire Q_reg_6;
wire Q_reg_7;
wire Q_reg_8;
wire [1:1] S;
LUT1 #(
.INIT(2'h1)
) \NEXT_IA_OBUFT[0]_inst_i_3 (
.I0(Q_reg_0),
.O (Q_reg_1[0])
);
LUT4 #(
.INIT(16'hF888)
) \NEXT_IA_OBUFT[1]_inst_i_1 (
.I0(S),
.I1(Q_reg_4),
.I2(Q_reg_5),
.I3(JMP),
.O (NEXT_IA_OBUF)
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6)
) \NEXT_IA_OBUFT[1]_inst_i_3 (
.I0(Q_reg_0),
.I1(Q_reg_7),
.O (S)
);
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h78)
) \NEXT_IA_OBUFT[2]_inst_i_3 (
.I0(Q_reg_0),
.I1(Q_reg_7),
.I2(Q_reg_8),
.O (Q_reg_1[1])
);
LUT2 #(
.INIT(4'h8)
) Q_i_1__5 (
.I0(NEXT_IA_OBUF),
.I1(Q_reg_6),
.O (Q_reg_2)
);
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1)
) Q_reg (
.C (CLK_IBUF_BUFG),
.CE(1'b1),
.D (Q_reg_3),
.Q (Q_reg_0),
.R (CLR_IBUF)
);
endmodule
| 6.607773 |
module D_Flip_Flop_62 (
Q_reg_0,
Q_reg_1,
NEXT_IA_OBUF,
Q_reg_2,
CLR_IBUF,
Q_reg_3,
CLK_IBUF_BUFG,
Q_reg_4,
Q_reg_5,
Q_reg_6,
JMP,
Q_reg_7,
Q_reg_8
);
output Q_reg_0;
output Q_reg_1;
output [0:0] NEXT_IA_OBUF;
output Q_reg_2;
input CLR_IBUF;
input Q_reg_3;
input CLK_IBUF_BUFG;
input Q_reg_4;
input Q_reg_5;
input Q_reg_6;
input JMP;
input Q_reg_7;
input Q_reg_8;
wire CLK_IBUF_BUFG;
wire CLR_IBUF;
wire JMP;
wire [0:0] NEXT_IA_OBUF;
wire Q_reg_0;
wire Q_reg_1;
wire Q_reg_2;
wire Q_reg_3;
wire Q_reg_4;
wire Q_reg_5;
wire Q_reg_6;
wire Q_reg_7;
wire Q_reg_8;
wire [3:3] S;
LUT4 #(
.INIT(16'hF888)
) \NEXT_IA_OBUFT[3]_inst_i_1 (
.I0(S),
.I1(Q_reg_6),
.I2(Q_reg_1),
.I3(JMP),
.O (NEXT_IA_OBUF)
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7F80)
) \NEXT_IA_OBUFT[3]_inst_i_3 (
.I0(Q_reg_0),
.I1(Q_reg_4),
.I2(Q_reg_5),
.I3(Q_reg_8),
.O (S)
);
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h04)
) \NEXT_IA_OBUFT[3]_inst_i_5 (
.I0(Q_reg_0),
.I1(Q_reg_4),
.I2(Q_reg_5),
.O (Q_reg_1)
);
LUT2 #(
.INIT(4'h8)
) Q_i_1__7 (
.I0(NEXT_IA_OBUF),
.I1(Q_reg_7),
.O (Q_reg_2)
);
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1)
) Q_reg (
.C (CLK_IBUF_BUFG),
.CE(1'b1),
.D (Q_reg_3),
.Q (Q_reg_0),
.R (CLR_IBUF)
);
endmodule
| 6.607773 |
module D_Flip_Flop_7 (
R7_OBUF,
Q_reg_0,
Q_reg_1,
CLR_IBUF,
Q_reg_2,
Clk_With_Enabled_4,
Q_reg_3,
FA1_C,
Sub,
Q_reg_4,
Q_reg_5,
R5_OBUF,
R4_OBUF,
Q_reg_6,
Q_reg_7
);
output [0:0] R7_OBUF;
output [0:0] Q_reg_0;
output [0:0] Q_reg_1;
input CLR_IBUF;
input [0:0] Q_reg_2;
input Clk_With_Enabled_4;
input [1:0] Q_reg_3;
input FA1_C;
input Sub;
input Q_reg_4;
input [2:0] Q_reg_5;
input [0:0] R5_OBUF;
input [0:0] R4_OBUF;
input Q_reg_6;
input Q_reg_7;
wire CLR_IBUF;
wire Clk_With_Enabled_4;
wire FA1_C;
wire [0:0] Q_reg_0;
wire [0:0] Q_reg_1;
wire [0:0] Q_reg_2;
wire [1:0] Q_reg_3;
wire Q_reg_4;
wire [2:0] Q_reg_5;
wire Q_reg_6;
wire Q_reg_7;
wire [0:0] R4_OBUF;
wire [0:0] R5_OBUF;
wire [0:0] R7_OBUF;
wire Sub;
wire ZERO_OBUF_inst_i_54_n_0;
wire ZERO_OBUF_inst_i_72_n_0;
LUT6 #(
.INIT(64'h4DB2E817B24D17E8)
) Q_i_4__1 (
.I0(Q_reg_3[0]),
.I1(Q_reg_1),
.I2(FA1_C),
.I3(Q_reg_3[1]),
.I4(Sub),
.I5(Q_reg_4),
.O (Q_reg_0)
);
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b1)
) Q_reg (
.C (Clk_With_Enabled_4),
.CE(1'b1),
.D (Q_reg_2),
.Q (R7_OBUF),
.R (CLR_IBUF)
);
LUT2 #(
.INIT(4'h8)
) ZERO_OBUF_inst_i_27 (
.I0(ZERO_OBUF_inst_i_54_n_0),
.I1(Q_reg_7),
.O (Q_reg_1)
);
LUT2 #(
.INIT(4'hE)
) ZERO_OBUF_inst_i_54 (
.I0(ZERO_OBUF_inst_i_72_n_0),
.I1(Q_reg_6),
.O (ZERO_OBUF_inst_i_54_n_0)
);
LUT6 #(
.INIT(64'hFFFFF888F888F888)
) ZERO_OBUF_inst_i_72 (
.I0(R7_OBUF),
.I1(Q_reg_5[2]),
.I2(R5_OBUF),
.I3(Q_reg_5[1]),
.I4(R4_OBUF),
.I5(Q_reg_5[0]),
.O (ZERO_OBUF_inst_i_72_n_0)
);
endmodule
| 7.11469 |
module tb_navre ();
reg sys_clk;
initial sys_clk = 1'b1;
always #5 sys_clk = ~sys_clk;
reg sys_rst;
wire pmem_ce;
wire [9:0] pmem_a;
reg [15:0] pmem_d;
reg [15:0] pmem[0:1023];
always @(posedge sys_clk) begin
if (pmem_ce) pmem_d <= pmem[pmem_a];
end
wire dmem_we;
wire [9:0] dmem_a;
reg [7:0] dmem_di;
wire [7:0] dmem_do;
reg [7:0] dmem[0:1023];
always @(posedge sys_clk) begin
if (dmem_we) begin
//$display("DMEM WRITE: adr=%d dat=%d", dmem_a, dmem_do);
dmem[dmem_a] <= dmem_do;
end
dmem_di <= dmem[dmem_a];
end
wire io_re;
wire io_we;
wire [5:0] io_a;
wire [7:0] io_do;
reg [7:0] io_di;
reg end_of_test;
always @(posedge sys_clk) begin
end_of_test <= 1'b0;
if (~sys_rst) begin
if (io_re) begin
$display("IO READ adr=%x", io_a);
if ((io_a == 6'h11) | (io_a == 6'h12)) io_di <= 8'hff;
else io_di <= io_a;
end
if (io_we) begin
$display("IO WRITE adr=%x dat=%x", io_a, io_do);
if ((io_a == 0) && (io_do == 254)) end_of_test <= 1'b1;
end
end
end
softusb_navre #(
.pmem_width(10),
.dmem_width(10)
) dut (
.clk(sys_clk),
.rst(sys_rst),
.pmem_ce(pmem_ce),
.pmem_a (pmem_a),
.pmem_d (pmem_d),
.dmem_we(dmem_we),
.dmem_a (dmem_a),
.dmem_di(dmem_di),
.dmem_do(dmem_do),
.io_re(io_re),
.io_we(io_we),
.io_a (io_a),
.io_do(io_do),
.io_di(io_di),
.irq(8'b0),
.dbg_pc()
);
initial begin
$display("Test: Fibonacci (assembler)");
$readmemh("fib.rom", pmem);
sys_rst = 1'b1;
#15;
sys_rst = 1'b0;
@(posedge end_of_test);
$display("Test: Fibonacci (C)");
$readmemh("fibc.rom", pmem);
sys_rst = 1'b1;
#15;
sys_rst = 1'b0;
@(posedge end_of_test);
$finish;
end
endmodule
| 6.65372 |
module tb_NbitRegister;
localparam N = 4;
reg [N-1:0] Data_in;
wire [N-1:0] Data_out;
reg clock;
reg clear;
NbitRegister reg0 (
.Data_in(Data_in),
.Data_out(Data_out),
.Clock(clock),
.Clear(clear)
);
//
initial begin
Data_in = 0;
clear = 1;
#20;
Data_in = 16;
#20;
Data_in = 10;
#20;
Data_in = 9;
#20;
clear = 0;
#20;
Data_in = 5;
#20;
end
always begin
clock = 1'b1;
#10; //wait 20ns
clock = 1'b0;
#10; //wait 20ns
end
endmodule
| 6.787769 |
module: netwalk_decoder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_netwalk_decoder;
parameter DECODER_IN_WIDTH=4;
parameter DECODER_OUT_WIDTH=1<<DECODER_IN_WIDTH;
// Inputs
reg clk;
reg reset;
reg [DECODER_IN_WIDTH-1:0] decoder_in;
// Outputs
wire [DECODER_OUT_WIDTH-1:0] decoder_out;
// Instantiate the Unit Under Test (UUT)
netwalk_decoder
#(.DECODER_IN_WIDTH(DECODER_IN_WIDTH)) decoder
(
.clk(clk),
.reset(reset),
.decoder_in(decoder_in),
.decoder_out(decoder_out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
decoder_in = 0;
// Wait 100 ns for global reset to finish
#100;
decoder_in=4'b0000;
#20;
decoder_in=4'b0001;
#20;
decoder_in=4'b0111;
#40;
// Add stimulus here
end
always begin
#5 clk=~clk;
end
endmodule
| 6.961294 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.